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author | 2023-02-21 18:24:12 -0800 | |
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committer | 2023-02-21 18:24:12 -0800 | |
commit | 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 (patch) | |
tree | cc5c2d0a898769fd59549594fedb3ee6f84e59a0 /arch/mips/include/asm/octeon/cvmx-ipd-defs.h | |
download | linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.tar.gz linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.zip |
Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted
Pull networking updates from Jakub Kicinski:
"Core:
- Add dedicated kmem_cache for typical/small skb->head, avoid having
to access struct page at kfree time, and improve memory use.
- Introduce sysctl to set default RPS configuration for new netdevs.
- Define Netlink protocol specification format which can be used to
describe messages used by each family and auto-generate parsers.
Add tools for generating kernel data structures and uAPI headers.
- Expose all net/core sysctls inside netns.
- Remove 4s sleep in netpoll if carrier is instantly detected on
boot.
- Add configurable limit of MDB entries per port, and port-vlan.
- Continue populating drop reasons throughout the stack.
- Retire a handful of legacy Qdiscs and classifiers.
Protocols:
- Support IPv4 big TCP (TSO frames larger than 64kB).
- Add IP_LOCAL_PORT_RANGE socket option, to control local port range
on socket by socket basis.
- Track and report in procfs number of MPTCP sockets used.
- Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
manager.
- IPv6: don't check net.ipv6.route.max_size and rely on garbage
collection to free memory (similarly to IPv4).
- Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).
- ICMP: add per-rate limit counters.
- Add support for user scanning requests in ieee802154.
- Remove static WEP support.
- Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
reporting.
- WiFi 7 EHT channel puncturing support (client & AP).
BPF:
- Add a rbtree data structure following the "next-gen data structure"
precedent set by recently added linked list, that is, by using
kfunc + kptr instead of adding a new BPF map type.
- Expose XDP hints via kfuncs with initial support for RX hash and
timestamp metadata.
- Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
better support decap on GRE tunnel devices not operating in collect
metadata.
- Improve x86 JIT's codegen for PROBE_MEM runtime error checks.
- Remove the need for trace_printk_lock for bpf_trace_printk and
bpf_trace_vprintk helpers.
- Extend libbpf's bpf_tracing.h support for tracing arguments of
kprobes/uprobes and syscall as a special case.
- Significantly reduce the search time for module symbols by
livepatch and BPF.
- Enable cpumasks to be used as kptrs, which is useful for tracing
programs tracking which tasks end up running on which CPUs in
different time intervals.
- Add support for BPF trampoline on s390x and riscv64.
- Add capability to export the XDP features supported by the NIC.
- Add __bpf_kfunc tag for marking kernel functions as kfuncs.
- Add cgroup.memory=nobpf kernel parameter option to disable BPF
memory accounting for container environments.
Netfilter:
- Remove the CLUSTERIP target. It has been marked as obsolete for
years, and we still have WARN splats wrt races of the out-of-band
/proc interface installed by this target.
- Add 'destroy' commands to nf_tables. They are identical to the
existing 'delete' commands, but do not return an error if the
referenced object (set, chain, rule...) did not exist.
Driver API:
- Improve cpumask_local_spread() locality to help NICs set the right
IRQ affinity on AMD platforms.
- Separate C22 and C45 MDIO bus transactions more clearly.
- Introduce new DCB table to control DSCP rewrite on egress.
- Support configuration of Physical Layer Collision Avoidance (PLCA)
Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
shared medium Ethernet.
- Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
preemption of low priority frames by high priority frames.
- Add support for controlling MACSec offload using netlink SET.
- Rework devlink instance refcounts to allow registration and
de-registration under the instance lock. Split the code into
multiple files, drop some of the unnecessarily granular locks and
factor out common parts of netlink operation handling.
- Add TX frame aggregation parameters (for USB drivers).
- Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
messages with notifications for debug.
- Allow offloading of UDP NEW connections via act_ct.
- Add support for per action HW stats in TC.
- Support hardware miss to TC action (continue processing in SW from
a specific point in the action chain).
- Warn if old Wireless Extension user space interface is used with
modern cfg80211/mac80211 drivers. Do not support Wireless
Extensions for Wi-Fi 7 devices at all. Everyone should switch to
using nl80211 interface instead.
- Improve the CAN bit timing configuration. Use extack to return
error messages directly to user space, update the SJW handling,
including the definition of a new default value that will benefit
CAN-FD controllers, by increasing their oscillator tolerance.
New hardware / drivers:
- Ethernet:
- nVidia BlueField-3 support (control traffic driver)
- Ethernet support for imx93 SoCs
- Motorcomm yt8531 gigabit Ethernet PHY
- onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
- Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
- Amlogic gxl MDIO mux
- WiFi:
- RealTek RTL8188EU (rtl8xxxu)
- Qualcomm Wi-Fi 7 devices (ath12k)
- CAN:
- Renesas R-Car V4H
Drivers:
- Bluetooth:
- Set Per Platform Antenna Gain (PPAG) for Intel controllers.
- Ethernet NICs:
- Intel (1G, igc):
- support TSN / Qbv / packet scheduling features of i226 model
- Intel (100G, ice):
- use GNSS subsystem instead of TTY
- multi-buffer XDP support
- extend support for GPIO pins to E823 devices
- nVidia/Mellanox:
- update the shared buffer configuration on PFC commands
- implement PTP adjphase function for HW offset control
- TC support for Geneve and GRE with VF tunnel offload
- more efficient crypto key management method
- multi-port eswitch support
- Netronome/Corigine:
- add DCB IEEE support
- support IPsec offloading for NFP3800
- Freescale/NXP (enetc):
- support XDP_REDIRECT for XDP non-linear buffers
- improve reconfig, avoid link flap and waiting for idle
- support MAC Merge layer
- Other NICs:
- sfc/ef100: add basic devlink support for ef100
- ionic: rx_push mode operation (writing descriptors via MMIO)
- bnxt: use the auxiliary bus abstraction for RDMA
- r8169: disable ASPM and reset bus in case of tx timeout
- cpsw: support QSGMII mode for J721e CPSW9G
- cpts: support pulse-per-second output
- ngbe: add an mdio bus driver
- usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
- r8152: handle devices with FW with NCM support
- amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
- virtio-net: support multi buffer XDP
- virtio/vsock: replace virtio_vsock_pkt with sk_buff
- tsnep: XDP support
- Ethernet high-speed switches:
- nVidia/Mellanox (mlxsw):
- add support for latency TLV (in FW control messages)
- Microchip (sparx5):
- separate explicit and implicit traffic forwarding rules, make
the implicit rules always active
- add support for egress DSCP rewrite
- IS0 VCAP support (Ingress Classification)
- IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
etc.)
- ES2 VCAP support (Egress Access Control)
- support for Per-Stream Filtering and Policing (802.1Q,
8.6.5.1)
- Ethernet embedded switches:
- Marvell (mv88e6xxx):
- add MAB (port auth) offload support
- enable PTP receive for mv88e6390
- NXP (ocelot):
- support MAC Merge layer
- support for the the vsc7512 internal copper phys
- Microchip:
- lan9303: convert to PHYLINK
- lan966x: support TC flower filter statistics
- lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
- lan937x: support Credit Based Shaper configuration
- ksz9477: support Energy Efficient Ethernet
- other:
- qca8k: convert to regmap read/write API, use bulk operations
- rswitch: Improve TX timestamp accuracy
- Intel WiFi (iwlwifi):
- EHT (Wi-Fi 7) rate reporting
- STEP equalizer support: transfer some STEP (connection to radio
on platforms with integrated wifi) related parameters from the
BIOS to the firmware.
- Qualcomm 802.11ax WiFi (ath11k):
- IPQ5018 support
- Fine Timing Measurement (FTM) responder role support
- channel 177 support
- MediaTek WiFi (mt76):
- per-PHY LED support
- mt7996: EHT (Wi-Fi 7) support
- Wireless Ethernet Dispatch (WED) reset support
- switch to using page pool allocator
- RealTek WiFi (rtw89):
- support new version of Bluetooth co-existance
- Mobile:
- rmnet: support TX aggregation"
* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
page_pool: add a comment explaining the fragment counter usage
net: ethtool: fix __ethtool_dev_mm_supported() implementation
ethtool: pse-pd: Fix double word in comments
xsk: add linux/vmalloc.h to xsk.c
sefltests: netdevsim: wait for devlink instance after netns removal
selftest: fib_tests: Always cleanup before exit
net/mlx5e: Align IPsec ASO result memory to be as required by hardware
net/mlx5e: TC, Set CT miss to the specific ct action instance
net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
net/mlx5: Refactor tc miss handling to a single function
net/mlx5: Kconfig: Make tc offload depend on tc skb extension
net/sched: flower: Support hardware miss to tc action
net/sched: flower: Move filter handle initialization earlier
net/sched: cls_api: Support hardware miss to tc action
net/sched: Rename user cookie and act cookie
sfc: fix builds without CONFIG_RTC_LIB
sfc: clean up some inconsistent indentings
net/mlx4_en: Introduce flexible array to silence overflow warning
net: lan966x: Fix possible deadlock inside PTP
net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
...
Diffstat (limited to '')
-rw-r--r-- | arch/mips/include/asm/octeon/cvmx-ipd-defs.h | 1472 |
1 files changed, 1472 insertions, 0 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h new file mode 100644 index 000000000..c0a4ac7b4 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h @@ -0,0 +1,1472 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_IPD_DEFS_H__ +#define __CVMX_IPD_DEFS_H__ + +#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull)) +#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) +#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) +#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) +#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8) +#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8) +#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) +#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) +#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull)) +#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) +#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull)) +#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull)) +#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull)) +#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull)) +#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) +#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) +#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull)) +#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull)) +#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) +#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull)) +#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) +#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull)) +#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) +#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) +#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36) +#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40) +#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36) +#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40) +#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44) +#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) +#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull)) +#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) +#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) +#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) +#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull)) +#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) +#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) +#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) +#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull)) +#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0) +#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1) +#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2) +#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3) +#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4) +#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5) +#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6) +#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) +#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) +#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) +#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull)) +#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull)) +#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) +#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) +#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) +#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1) +#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2) +#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3) +#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4) +#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5) +#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) +#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) +#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) +#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull)) +#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) +#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) +#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) +#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull)) +#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull)) + +union cvmx_ipd_1st_mbuff_skip { + uint64_t u64; + struct cvmx_ipd_1st_mbuff_skip_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t skip_sz:6; +#else + uint64_t skip_sz:6; + uint64_t reserved_6_63:58; +#endif + } s; +}; + +union cvmx_ipd_1st_next_ptr_back { + uint64_t u64; + struct cvmx_ipd_1st_next_ptr_back_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t back:4; +#else + uint64_t back:4; + uint64_t reserved_4_63:60; +#endif + } s; +}; + +union cvmx_ipd_2nd_next_ptr_back { + uint64_t u64; + struct cvmx_ipd_2nd_next_ptr_back_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t back:4; +#else + uint64_t back:4; + uint64_t reserved_4_63:60; +#endif + } s; +}; + +union cvmx_ipd_bist_status { + uint64_t u64; + struct cvmx_ipd_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t iiwo1:1; + uint64_t iiwo0:1; + uint64_t iio1:1; + uint64_t iio0:1; + uint64_t pbm4:1; + uint64_t csr_mem:1; + uint64_t csr_ncmd:1; + uint64_t pwq_wqed:1; + uint64_t pwq_wp1:1; + uint64_t pwq_pow:1; + uint64_t ipq_pbe1:1; + uint64_t ipq_pbe0:1; + uint64_t pbm3:1; + uint64_t pbm2:1; + uint64_t pbm1:1; + uint64_t pbm0:1; + uint64_t pbm_word:1; + uint64_t pwq1:1; + uint64_t pwq0:1; + uint64_t prc_off:1; + uint64_t ipd_old:1; + uint64_t ipd_new:1; + uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t csr_ncmd:1; + uint64_t csr_mem:1; + uint64_t pbm4:1; + uint64_t iio0:1; + uint64_t iio1:1; + uint64_t iiwo0:1; + uint64_t iiwo1:1; + uint64_t reserved_23_63:41; +#endif + } s; + struct cvmx_ipd_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t pwq_wqed:1; + uint64_t pwq_wp1:1; + uint64_t pwq_pow:1; + uint64_t ipq_pbe1:1; + uint64_t ipq_pbe0:1; + uint64_t pbm3:1; + uint64_t pbm2:1; + uint64_t pbm1:1; + uint64_t pbm0:1; + uint64_t pbm_word:1; + uint64_t pwq1:1; + uint64_t pwq0:1; + uint64_t prc_off:1; + uint64_t ipd_old:1; + uint64_t ipd_new:1; + uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t reserved_16_63:48; +#endif + } cn30xx; + struct cvmx_ipd_bist_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t csr_mem:1; + uint64_t csr_ncmd:1; + uint64_t pwq_wqed:1; + uint64_t pwq_wp1:1; + uint64_t pwq_pow:1; + uint64_t ipq_pbe1:1; + uint64_t ipq_pbe0:1; + uint64_t pbm3:1; + uint64_t pbm2:1; + uint64_t pbm1:1; + uint64_t pbm0:1; + uint64_t pbm_word:1; + uint64_t pwq1:1; + uint64_t pwq0:1; + uint64_t prc_off:1; + uint64_t ipd_old:1; + uint64_t ipd_new:1; + uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t csr_ncmd:1; + uint64_t csr_mem:1; + uint64_t reserved_18_63:46; +#endif + } cn52xx; +}; + +union cvmx_ipd_bp_prt_red_end { + uint64_t u64; + struct cvmx_ipd_bp_prt_red_end_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t prt_enb:48; +#else + uint64_t prt_enb:48; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_ipd_bp_prt_red_end_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_36_63:28; + uint64_t prt_enb:36; +#else + uint64_t prt_enb:36; + uint64_t reserved_36_63:28; +#endif + } cn30xx; + struct cvmx_ipd_bp_prt_red_end_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_40_63:24; + uint64_t prt_enb:40; +#else + uint64_t prt_enb:40; + uint64_t reserved_40_63:24; +#endif + } cn52xx; + struct cvmx_ipd_bp_prt_red_end_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t prt_enb:44; +#else + uint64_t prt_enb:44; + uint64_t reserved_44_63:20; +#endif + } cn63xx; +}; + +union cvmx_ipd_bpidx_mbuf_th { + uint64_t u64; + struct cvmx_ipd_bpidx_mbuf_th_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t bp_enb:1; + uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif + } s; +}; + +union cvmx_ipd_bpid_bp_counterx { + uint64_t u64; + struct cvmx_ipd_bpid_bp_counterx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_clk_count { + uint64_t u64; + struct cvmx_ipd_clk_count_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clk_cnt:64; +#else + uint64_t clk_cnt:64; +#endif + } s; +}; + +union cvmx_ipd_credits { + uint64_t u64; + struct cvmx_ipd_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t iob_wrc:8; + uint64_t iob_wr:8; +#else + uint64_t iob_wr:8; + uint64_t iob_wrc:8; + uint64_t reserved_16_63:48; +#endif + } s; +}; + +union cvmx_ipd_ctl_status { + uint64_t u64; + struct cvmx_ipd_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t use_sop:1; + uint64_t rst_done:1; + uint64_t clken:1; + uint64_t no_wptr:1; + uint64_t pq_apkt:1; + uint64_t pq_nabuf:1; + uint64_t ipd_full:1; + uint64_t pkt_off:1; + uint64_t len_m8:1; + uint64_t reset:1; + uint64_t addpkt:1; + uint64_t naddbuf:1; + uint64_t pkt_lend:1; + uint64_t wqe_lend:1; + uint64_t pbp_en:1; + uint64_t opc_mode:2; + uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t clken:1; + uint64_t rst_done:1; + uint64_t use_sop:1; + uint64_t reserved_18_63:46; +#endif + } s; + struct cvmx_ipd_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t len_m8:1; + uint64_t reset:1; + uint64_t addpkt:1; + uint64_t naddbuf:1; + uint64_t pkt_lend:1; + uint64_t wqe_lend:1; + uint64_t pbp_en:1; + uint64_t opc_mode:2; + uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t reserved_10_63:54; +#endif + } cn30xx; + struct cvmx_ipd_ctl_status_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t reset:1; + uint64_t addpkt:1; + uint64_t naddbuf:1; + uint64_t pkt_lend:1; + uint64_t wqe_lend:1; + uint64_t pbp_en:1; + uint64_t opc_mode:2; + uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t reserved_9_63:55; +#endif + } cn38xxp2; + struct cvmx_ipd_ctl_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t no_wptr:1; + uint64_t pq_apkt:1; + uint64_t pq_nabuf:1; + uint64_t ipd_full:1; + uint64_t pkt_off:1; + uint64_t len_m8:1; + uint64_t reset:1; + uint64_t addpkt:1; + uint64_t naddbuf:1; + uint64_t pkt_lend:1; + uint64_t wqe_lend:1; + uint64_t pbp_en:1; + uint64_t opc_mode:2; + uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t reserved_15_63:49; +#endif + } cn50xx; + struct cvmx_ipd_ctl_status_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t ipd_full:1; + uint64_t pkt_off:1; + uint64_t len_m8:1; + uint64_t reset:1; + uint64_t addpkt:1; + uint64_t naddbuf:1; + uint64_t pkt_lend:1; + uint64_t wqe_lend:1; + uint64_t pbp_en:1; + uint64_t opc_mode:2; + uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t reserved_12_63:52; +#endif + } cn58xx; + struct cvmx_ipd_ctl_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t clken:1; + uint64_t no_wptr:1; + uint64_t pq_apkt:1; + uint64_t pq_nabuf:1; + uint64_t ipd_full:1; + uint64_t pkt_off:1; + uint64_t len_m8:1; + uint64_t reset:1; + uint64_t addpkt:1; + uint64_t naddbuf:1; + uint64_t pkt_lend:1; + uint64_t wqe_lend:1; + uint64_t pbp_en:1; + uint64_t opc_mode:2; + uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t clken:1; + uint64_t reserved_16_63:48; +#endif + } cn63xxp1; +}; + +union cvmx_ipd_ecc_ctl { + uint64_t u64; + struct cvmx_ipd_ecc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t pm3_syn:2; + uint64_t pm2_syn:2; + uint64_t pm1_syn:2; + uint64_t pm0_syn:2; +#else + uint64_t pm0_syn:2; + uint64_t pm1_syn:2; + uint64_t pm2_syn:2; + uint64_t pm3_syn:2; + uint64_t reserved_8_63:56; +#endif + } s; +}; + +union cvmx_ipd_free_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_free_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t max_cnts:7; + uint64_t wraddr:8; + uint64_t praddr:8; + uint64_t cena:1; + uint64_t raddr:8; +#else + uint64_t raddr:8; + uint64_t cena:1; + uint64_t praddr:8; + uint64_t wraddr:8; + uint64_t max_cnts:7; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_ipd_free_ptr_value { + uint64_t u64; + struct cvmx_ipd_free_ptr_value_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; +}; + +union cvmx_ipd_hold_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_hold_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_43_63:21; + uint64_t ptr:33; + uint64_t max_pkt:3; + uint64_t praddr:3; + uint64_t cena:1; + uint64_t raddr:3; +#else + uint64_t raddr:3; + uint64_t cena:1; + uint64_t praddr:3; + uint64_t max_pkt:3; + uint64_t ptr:33; + uint64_t reserved_43_63:21; +#endif + } s; +}; + +union cvmx_ipd_int_enb { + uint64_t u64; + struct cvmx_ipd_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t pw3_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw0_sbe:1; + uint64_t dat:1; + uint64_t eop:1; + uint64_t sop:1; + uint64_t pq_sub:1; + uint64_t pq_add:1; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t sop:1; + uint64_t eop:1; + uint64_t dat:1; + uint64_t pw0_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw3_dbe:1; + uint64_t reserved_23_63:41; +#endif + } s; + struct cvmx_ipd_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_5_63:59; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t reserved_5_63:59; +#endif + } cn30xx; + struct cvmx_ipd_int_enb_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t reserved_10_63:54; +#endif + } cn38xx; + struct cvmx_ipd_int_enb_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t pq_sub:1; + uint64_t pq_add:1; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; +}; + +union cvmx_ipd_int_sum { + uint64_t u64; + struct cvmx_ipd_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t pw3_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw0_sbe:1; + uint64_t dat:1; + uint64_t eop:1; + uint64_t sop:1; + uint64_t pq_sub:1; + uint64_t pq_add:1; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t sop:1; + uint64_t eop:1; + uint64_t dat:1; + uint64_t pw0_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw3_dbe:1; + uint64_t reserved_23_63:41; +#endif + } s; + struct cvmx_ipd_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_5_63:59; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t reserved_5_63:59; +#endif + } cn30xx; + struct cvmx_ipd_int_sum_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t reserved_10_63:54; +#endif + } cn38xx; + struct cvmx_ipd_int_sum_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t pq_sub:1; + uint64_t pq_add:1; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; +}; + +union cvmx_ipd_next_pkt_ptr { + uint64_t u64; + struct cvmx_ipd_next_pkt_ptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; +}; + +union cvmx_ipd_next_wqe_ptr { + uint64_t u64; + struct cvmx_ipd_next_wqe_ptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; +}; + +union cvmx_ipd_not_1st_mbuff_skip { + uint64_t u64; + struct cvmx_ipd_not_1st_mbuff_skip_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t skip_sz:6; +#else + uint64_t skip_sz:6; + uint64_t reserved_6_63:58; +#endif + } s; +}; + +union cvmx_ipd_on_bp_drop_pktx { + uint64_t u64; + struct cvmx_ipd_on_bp_drop_pktx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prt_enb:64; +#else + uint64_t prt_enb:64; +#endif + } s; +}; + +union cvmx_ipd_packet_mbuff_size { + uint64_t u64; + struct cvmx_ipd_packet_mbuff_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t mb_size:12; +#else + uint64_t mb_size:12; + uint64_t reserved_12_63:52; +#endif + } s; +}; + +union cvmx_ipd_pkt_err { + uint64_t u64; + struct cvmx_ipd_pkt_err_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t reasm:6; +#else + uint64_t reasm:6; + uint64_t reserved_6_63:58; +#endif + } s; +}; + +union cvmx_ipd_pkt_ptr_valid { + uint64_t u64; + struct cvmx_ipd_pkt_ptr_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t ptr:29; +#else + uint64_t ptr:29; + uint64_t reserved_29_63:35; +#endif + } s; +}; + +union cvmx_ipd_portx_bp_page_cnt { + uint64_t u64; + struct cvmx_ipd_portx_bp_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t bp_enb:1; + uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif + } s; +}; + +union cvmx_ipd_portx_bp_page_cnt2 { + uint64_t u64; + struct cvmx_ipd_portx_bp_page_cnt2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t bp_enb:1; + uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif + } s; +}; + +union cvmx_ipd_portx_bp_page_cnt3 { + uint64_t u64; + struct cvmx_ipd_portx_bp_page_cnt3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t bp_enb:1; + uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif + } s; +}; + +union cvmx_ipd_port_bp_counters2_pairx { + uint64_t u64; + struct cvmx_ipd_port_bp_counters2_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_port_bp_counters3_pairx { + uint64_t u64; + struct cvmx_ipd_port_bp_counters3_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_port_bp_counters4_pairx { + uint64_t u64; + struct cvmx_ipd_port_bp_counters4_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_port_bp_counters_pairx { + uint64_t u64; + struct cvmx_ipd_port_bp_counters_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_port_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_port_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t ptr:33; + uint64_t max_pkt:7; + uint64_t cena:1; + uint64_t raddr:7; +#else + uint64_t raddr:7; + uint64_t cena:1; + uint64_t max_pkt:7; + uint64_t ptr:33; + uint64_t reserved_48_63:16; +#endif + } s; +}; + +union cvmx_ipd_port_qos_x_cnt { + uint64_t u64; + struct cvmx_ipd_port_qos_x_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t wmark:32; + uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t wmark:32; +#endif + } s; +}; + +union cvmx_ipd_port_qos_intx { + uint64_t u64; + struct cvmx_ipd_port_qos_intx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else + uint64_t intr:64; +#endif + } s; +}; + +union cvmx_ipd_port_qos_int_enbx { + uint64_t u64; + struct cvmx_ipd_port_qos_int_enbx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else + uint64_t enb:64; +#endif + } s; +}; + +union cvmx_ipd_port_sopx { + uint64_t u64; + struct cvmx_ipd_port_sopx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t sop:64; +#else + uint64_t sop:64; +#endif + } s; +}; + +union cvmx_ipd_prc_hold_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_39_63:25; + uint64_t max_pkt:3; + uint64_t praddr:3; + uint64_t ptr:29; + uint64_t cena:1; + uint64_t raddr:3; +#else + uint64_t raddr:3; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t praddr:3; + uint64_t max_pkt:3; + uint64_t reserved_39_63:25; +#endif + } s; +}; + +union cvmx_ipd_prc_port_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t max_pkt:7; + uint64_t ptr:29; + uint64_t cena:1; + uint64_t raddr:7; +#else + uint64_t raddr:7; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t max_pkt:7; + uint64_t reserved_44_63:20; +#endif + } s; +}; + +union cvmx_ipd_ptr_count { + uint64_t u64; + struct cvmx_ipd_ptr_count_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_19_63:45; + uint64_t pktv_cnt:1; + uint64_t wqev_cnt:1; + uint64_t pfif_cnt:3; + uint64_t pkt_pcnt:7; + uint64_t wqe_pcnt:7; +#else + uint64_t wqe_pcnt:7; + uint64_t pkt_pcnt:7; + uint64_t pfif_cnt:3; + uint64_t wqev_cnt:1; + uint64_t pktv_cnt:1; + uint64_t reserved_19_63:45; +#endif + } s; +}; + +union cvmx_ipd_pwp_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_pwp_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_61_63:3; + uint64_t max_cnts:7; + uint64_t wraddr:8; + uint64_t praddr:8; + uint64_t ptr:29; + uint64_t cena:1; + uint64_t raddr:8; +#else + uint64_t raddr:8; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t praddr:8; + uint64_t wraddr:8; + uint64_t max_cnts:7; + uint64_t reserved_61_63:3; +#endif + } s; +}; + +union cvmx_ipd_qosx_red_marks { + uint64_t u64; + struct cvmx_ipd_qosx_red_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t drop:32; + uint64_t pass:32; +#else + uint64_t pass:32; + uint64_t drop:32; +#endif + } s; +}; + +union cvmx_ipd_que0_free_page_cnt { + uint64_t u64; + struct cvmx_ipd_que0_free_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t q0_pcnt:32; +#else + uint64_t q0_pcnt:32; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_ipd_red_bpid_enablex { + uint64_t u64; + struct cvmx_ipd_red_bpid_enablex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prt_enb:64; +#else + uint64_t prt_enb:64; +#endif + } s; +}; + +union cvmx_ipd_red_delay { + uint64_t u64; + struct cvmx_ipd_red_delay_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t prb_dly:14; + uint64_t avg_dly:14; +#else + uint64_t avg_dly:14; + uint64_t prb_dly:14; + uint64_t reserved_28_63:36; +#endif + } s; +}; + +union cvmx_ipd_red_port_enable { + uint64_t u64; + struct cvmx_ipd_red_port_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prb_dly:14; + uint64_t avg_dly:14; + uint64_t prt_enb:36; +#else + uint64_t prt_enb:36; + uint64_t avg_dly:14; + uint64_t prb_dly:14; +#endif + } s; +}; + +union cvmx_ipd_red_port_enable2 { + uint64_t u64; + struct cvmx_ipd_red_port_enable2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t prt_enb:12; +#else + uint64_t prt_enb:12; + uint64_t reserved_12_63:52; +#endif + } s; + struct cvmx_ipd_red_port_enable2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t prt_enb:4; +#else + uint64_t prt_enb:4; + uint64_t reserved_4_63:60; +#endif + } cn52xx; + struct cvmx_ipd_red_port_enable2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t prt_enb:8; +#else + uint64_t prt_enb:8; + uint64_t reserved_8_63:56; +#endif + } cn63xx; +}; + +union cvmx_ipd_red_quex_param { + uint64_t u64; + struct cvmx_ipd_red_quex_param_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t use_pcnt:1; + uint64_t new_con:8; + uint64_t avg_con:8; + uint64_t prb_con:32; +#else + uint64_t prb_con:32; + uint64_t avg_con:8; + uint64_t new_con:8; + uint64_t use_pcnt:1; + uint64_t reserved_49_63:15; +#endif + } s; +}; + +union cvmx_ipd_req_wgt { + uint64_t u64; + struct cvmx_ipd_req_wgt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t wgt7:8; + uint64_t wgt6:8; + uint64_t wgt5:8; + uint64_t wgt4:8; + uint64_t wgt3:8; + uint64_t wgt2:8; + uint64_t wgt1:8; + uint64_t wgt0:8; +#else + uint64_t wgt0:8; + uint64_t wgt1:8; + uint64_t wgt2:8; + uint64_t wgt3:8; + uint64_t wgt4:8; + uint64_t wgt5:8; + uint64_t wgt6:8; + uint64_t wgt7:8; +#endif + } s; +}; + +union cvmx_ipd_sub_port_bp_page_cnt { + uint64_t u64; + struct cvmx_ipd_sub_port_bp_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_31_63:33; + uint64_t port:6; + uint64_t page_cnt:25; +#else + uint64_t page_cnt:25; + uint64_t port:6; + uint64_t reserved_31_63:33; +#endif + } s; +}; + +union cvmx_ipd_sub_port_fcs { + uint64_t u64; + struct cvmx_ipd_sub_port_fcs_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_40_63:24; + uint64_t port_bit2:4; + uint64_t reserved_32_35:4; + uint64_t port_bit:32; +#else + uint64_t port_bit:32; + uint64_t reserved_32_35:4; + uint64_t port_bit2:4; + uint64_t reserved_40_63:24; +#endif + } s; + struct cvmx_ipd_sub_port_fcs_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t port_bit:3; +#else + uint64_t port_bit:3; + uint64_t reserved_3_63:61; +#endif + } cn30xx; + struct cvmx_ipd_sub_port_fcs_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t port_bit:32; +#else + uint64_t port_bit:32; + uint64_t reserved_32_63:32; +#endif + } cn38xx; +}; + +union cvmx_ipd_sub_port_qos_cnt { + uint64_t u64; + struct cvmx_ipd_sub_port_qos_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_41_63:23; + uint64_t port_qos:9; + uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t port_qos:9; + uint64_t reserved_41_63:23; +#endif + } s; +}; + +union cvmx_ipd_wqe_fpa_queue { + uint64_t u64; + struct cvmx_ipd_wqe_fpa_queue_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t wqe_pool:3; +#else + uint64_t wqe_pool:3; + uint64_t reserved_3_63:61; +#endif + } s; +}; + +union cvmx_ipd_wqe_ptr_valid { + uint64_t u64; + struct cvmx_ipd_wqe_ptr_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t ptr:29; +#else + uint64_t ptr:29; + uint64_t reserved_29_63:35; +#endif + } s; +}; + +#endif |