diff options
| author |  Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 18:24:12 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 18:24:12 -0800 |
| commit | 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 (patch) | |
| tree | cc5c2d0a898769fd59549594fedb3ee6f84e59a0 /drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h | |
| download | linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.tar.gz linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.zip | |
Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted
Pull networking updates from Jakub Kicinski:
"Core:
- Add dedicated kmem_cache for typical/small skb->head, avoid having
to access struct page at kfree time, and improve memory use.
- Introduce sysctl to set default RPS configuration for new netdevs.
- Define Netlink protocol specification format which can be used to
describe messages used by each family and auto-generate parsers.
Add tools for generating kernel data structures and uAPI headers.
- Expose all net/core sysctls inside netns.
- Remove 4s sleep in netpoll if carrier is instantly detected on
boot.
- Add configurable limit of MDB entries per port, and port-vlan.
- Continue populating drop reasons throughout the stack.
- Retire a handful of legacy Qdiscs and classifiers.
Protocols:
- Support IPv4 big TCP (TSO frames larger than 64kB).
- Add IP_LOCAL_PORT_RANGE socket option, to control local port range
on socket by socket basis.
- Track and report in procfs number of MPTCP sockets used.
- Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
manager.
- IPv6: don't check net.ipv6.route.max_size and rely on garbage
collection to free memory (similarly to IPv4).
- Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).
- ICMP: add per-rate limit counters.
- Add support for user scanning requests in ieee802154.
- Remove static WEP support.
- Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
reporting.
- WiFi 7 EHT channel puncturing support (client & AP).
BPF:
- Add a rbtree data structure following the "next-gen data structure"
precedent set by recently added linked list, that is, by using
kfunc + kptr instead of adding a new BPF map type.
- Expose XDP hints via kfuncs with initial support for RX hash and
timestamp metadata.
- Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
better support decap on GRE tunnel devices not operating in collect
metadata.
- Improve x86 JIT's codegen for PROBE_MEM runtime error checks.
- Remove the need for trace_printk_lock for bpf_trace_printk and
bpf_trace_vprintk helpers.
- Extend libbpf's bpf_tracing.h support for tracing arguments of
kprobes/uprobes and syscall as a special case.
- Significantly reduce the search time for module symbols by
livepatch and BPF.
- Enable cpumasks to be used as kptrs, which is useful for tracing
programs tracking which tasks end up running on which CPUs in
different time intervals.
- Add support for BPF trampoline on s390x and riscv64.
- Add capability to export the XDP features supported by the NIC.
- Add __bpf_kfunc tag for marking kernel functions as kfuncs.
- Add cgroup.memory=nobpf kernel parameter option to disable BPF
memory accounting for container environments.
Netfilter:
- Remove the CLUSTERIP target. It has been marked as obsolete for
years, and we still have WARN splats wrt races of the out-of-band
/proc interface installed by this target.
- Add 'destroy' commands to nf_tables. They are identical to the
existing 'delete' commands, but do not return an error if the
referenced object (set, chain, rule...) did not exist.
Driver API:
- Improve cpumask_local_spread() locality to help NICs set the right
IRQ affinity on AMD platforms.
- Separate C22 and C45 MDIO bus transactions more clearly.
- Introduce new DCB table to control DSCP rewrite on egress.
- Support configuration of Physical Layer Collision Avoidance (PLCA)
Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
shared medium Ethernet.
- Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
preemption of low priority frames by high priority frames.
- Add support for controlling MACSec offload using netlink SET.
- Rework devlink instance refcounts to allow registration and
de-registration under the instance lock. Split the code into
multiple files, drop some of the unnecessarily granular locks and
factor out common parts of netlink operation handling.
- Add TX frame aggregation parameters (for USB drivers).
- Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
messages with notifications for debug.
- Allow offloading of UDP NEW connections via act_ct.
- Add support for per action HW stats in TC.
- Support hardware miss to TC action (continue processing in SW from
a specific point in the action chain).
- Warn if old Wireless Extension user space interface is used with
modern cfg80211/mac80211 drivers. Do not support Wireless
Extensions for Wi-Fi 7 devices at all. Everyone should switch to
using nl80211 interface instead.
- Improve the CAN bit timing configuration. Use extack to return
error messages directly to user space, update the SJW handling,
including the definition of a new default value that will benefit
CAN-FD controllers, by increasing their oscillator tolerance.
New hardware / drivers:
- Ethernet:
- nVidia BlueField-3 support (control traffic driver)
- Ethernet support for imx93 SoCs
- Motorcomm yt8531 gigabit Ethernet PHY
- onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
- Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
- Amlogic gxl MDIO mux
- WiFi:
- RealTek RTL8188EU (rtl8xxxu)
- Qualcomm Wi-Fi 7 devices (ath12k)
- CAN:
- Renesas R-Car V4H
Drivers:
- Bluetooth:
- Set Per Platform Antenna Gain (PPAG) for Intel controllers.
- Ethernet NICs:
- Intel (1G, igc):
- support TSN / Qbv / packet scheduling features of i226 model
- Intel (100G, ice):
- use GNSS subsystem instead of TTY
- multi-buffer XDP support
- extend support for GPIO pins to E823 devices
- nVidia/Mellanox:
- update the shared buffer configuration on PFC commands
- implement PTP adjphase function for HW offset control
- TC support for Geneve and GRE with VF tunnel offload
- more efficient crypto key management method
- multi-port eswitch support
- Netronome/Corigine:
- add DCB IEEE support
- support IPsec offloading for NFP3800
- Freescale/NXP (enetc):
- support XDP_REDIRECT for XDP non-linear buffers
- improve reconfig, avoid link flap and waiting for idle
- support MAC Merge layer
- Other NICs:
- sfc/ef100: add basic devlink support for ef100
- ionic: rx_push mode operation (writing descriptors via MMIO)
- bnxt: use the auxiliary bus abstraction for RDMA
- r8169: disable ASPM and reset bus in case of tx timeout
- cpsw: support QSGMII mode for J721e CPSW9G
- cpts: support pulse-per-second output
- ngbe: add an mdio bus driver
- usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
- r8152: handle devices with FW with NCM support
- amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
- virtio-net: support multi buffer XDP
- virtio/vsock: replace virtio_vsock_pkt with sk_buff
- tsnep: XDP support
- Ethernet high-speed switches:
- nVidia/Mellanox (mlxsw):
- add support for latency TLV (in FW control messages)
- Microchip (sparx5):
- separate explicit and implicit traffic forwarding rules, make
the implicit rules always active
- add support for egress DSCP rewrite
- IS0 VCAP support (Ingress Classification)
- IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
etc.)
- ES2 VCAP support (Egress Access Control)
- support for Per-Stream Filtering and Policing (802.1Q,
8.6.5.1)
- Ethernet embedded switches:
- Marvell (mv88e6xxx):
- add MAB (port auth) offload support
- enable PTP receive for mv88e6390
- NXP (ocelot):
- support MAC Merge layer
- support for the the vsc7512 internal copper phys
- Microchip:
- lan9303: convert to PHYLINK
- lan966x: support TC flower filter statistics
- lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
- lan937x: support Credit Based Shaper configuration
- ksz9477: support Energy Efficient Ethernet
- other:
- qca8k: convert to regmap read/write API, use bulk operations
- rswitch: Improve TX timestamp accuracy
- Intel WiFi (iwlwifi):
- EHT (Wi-Fi 7) rate reporting
- STEP equalizer support: transfer some STEP (connection to radio
on platforms with integrated wifi) related parameters from the
BIOS to the firmware.
- Qualcomm 802.11ax WiFi (ath11k):
- IPQ5018 support
- Fine Timing Measurement (FTM) responder role support
- channel 177 support
- MediaTek WiFi (mt76):
- per-PHY LED support
- mt7996: EHT (Wi-Fi 7) support
- Wireless Ethernet Dispatch (WED) reset support
- switch to using page pool allocator
- RealTek WiFi (rtw89):
- support new version of Bluetooth co-existance
- Mobile:
- rmnet: support TX aggregation"
* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
page_pool: add a comment explaining the fragment counter usage
net: ethtool: fix __ethtool_dev_mm_supported() implementation
ethtool: pse-pd: Fix double word in comments
xsk: add linux/vmalloc.h to xsk.c
sefltests: netdevsim: wait for devlink instance after netns removal
selftest: fib_tests: Always cleanup before exit
net/mlx5e: Align IPsec ASO result memory to be as required by hardware
net/mlx5e: TC, Set CT miss to the specific ct action instance
net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
net/mlx5: Refactor tc miss handling to a single function
net/mlx5: Kconfig: Make tc offload depend on tc skb extension
net/sched: flower: Support hardware miss to tc action
net/sched: flower: Move filter handle initialization earlier
net/sched: cls_api: Support hardware miss to tc action
net/sched: Rename user cookie and act cookie
sfc: fix builds without CONFIG_RTC_LIB
sfc: clean up some inconsistent indentings
net/mlx4_en: Introduce flexible array to silence overflow warning
net: lan966x: Fix possible deadlock inside PTP
net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
...
Diffstat (limited to 'drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h')
| -rw-r--r-- | drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h | 905 |
1 files changed, 905 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h new file mode 100644 index 000000000..eaee29da4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h @@ -0,0 +1,905 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QPC0_REGS_H_ +#define ASIC_REG_NIC0_QPC0_REGS_H_ + +/* + ***************************************** + * NIC0_QPC0 + * (Prototype: NIC_QPC) + ***************************************** + */ + +#define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F000 + +#define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F004 + +#define mmNIC0_QPC0_REQ_STATIC_CONFIG 0x541F008 + +#define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C + +#define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F010 + +#define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F014 + +#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F018 + +#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C + +#define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F020 + +#define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F024 + +#define mmNIC0_QPC0_RETRY_COUNT_MAX 0x541F028 + +#define mmNIC0_QPC0_AXI_PROT 0x541F030 + +#define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F034 + +#define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F038 + +#define mmNIC0_QPC0_RES_STATIC_CONFIG 0x541F03C + +#define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F040 + +#define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F044 + +#define mmNIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F048 + +#define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F050 + +#define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F054 + +#define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F058 + +#define mmNIC0_QPC0_ERR_FIFO_MASK 0x541F05C + +#define mmNIC0_QPC0_ERR_FIFO_CREDIT 0x541F060 + +#define mmNIC0_QPC0_ERR_FIFO_CFG 0x541F064 + +#define mmNIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F068 + +#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C + +#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F070 + +#define mmNIC0_QPC0_GW_BUSY 0x541F080 + +#define mmNIC0_QPC0_GW_CTRL 0x541F084 + +#define mmNIC0_QPC0_GW_DATA_0 0x541F08C + +#define mmNIC0_QPC0_GW_DATA_1 0x541F090 + +#define mmNIC0_QPC0_GW_DATA_2 0x541F094 + +#define mmNIC0_QPC0_GW_DATA_3 0x541F098 + +#define mmNIC0_QPC0_GW_DATA_4 0x541F09C + +#define mmNIC0_QPC0_GW_DATA_5 0x541F0A0 + +#define mmNIC0_QPC0_GW_DATA_6 0x541F0A4 + +#define mmNIC0_QPC0_GW_DATA_7 0x541F0A8 + +#define mmNIC0_QPC0_GW_DATA_8 0x541F0AC + +#define mmNIC0_QPC0_GW_DATA_9 0x541F0B0 + +#define mmNIC0_QPC0_GW_DATA_10 0x541F0B4 + +#define mmNIC0_QPC0_GW_DATA_11 0x541F0B8 + +#define mmNIC0_QPC0_GW_DATA_12 0x541F0BC + +#define mmNIC0_QPC0_GW_DATA_13 0x541F0C0 + +#define mmNIC0_QPC0_GW_DATA_14 0x541F0C4 + +#define mmNIC0_QPC0_GW_DATA_15 0x541F0C8 + +#define mmNIC0_QPC0_GW_DATA_16 0x541F0CC + +#define mmNIC0_QPC0_GW_DATA_17 0x541F0D0 + +#define mmNIC0_QPC0_GW_DATA_18 0x541F0D4 + +#define mmNIC0_QPC0_GW_DATA_19 0x541F0D8 + +#define mmNIC0_QPC0_GW_DATA_20 0x541F0DC + +#define mmNIC0_QPC0_GW_DATA_21 0x541F0E0 + +#define mmNIC0_QPC0_GW_DATA_22 0x541F0E4 + +#define mmNIC0_QPC0_GW_DATA_23 0x541F0E8 + +#define mmNIC0_QPC0_GW_DATA_24 0x541F0EC + +#define mmNIC0_QPC0_GW_DATA_25 0x541F0F0 + +#define mmNIC0_QPC0_GW_DATA_26 0x541F0F4 + +#define mmNIC0_QPC0_GW_DATA_27 0x541F0F8 + +#define mmNIC0_QPC0_GW_DATA_28 0x541F0FC + +#define mmNIC0_QPC0_GW_DATA_29 0x541F100 + +#define mmNIC0_QPC0_GW_DATA_30 0x541F104 + +#define mmNIC0_QPC0_GW_DATA_31 0x541F108 + +#define mmNIC0_QPC0_GW_MASK_0 0x541F124 + +#define mmNIC0_QPC0_GW_MASK_1 0x541F128 + +#define mmNIC0_QPC0_GW_MASK_2 0x541F12C + +#define mmNIC0_QPC0_GW_MASK_3 0x541F130 + +#define mmNIC0_QPC0_GW_MASK_4 0x541F134 + +#define mmNIC0_QPC0_GW_MASK_5 0x541F138 + +#define mmNIC0_QPC0_GW_MASK_6 0x541F13C + +#define mmNIC0_QPC0_GW_MASK_7 0x541F140 + +#define mmNIC0_QPC0_GW_MASK_8 0x541F144 + +#define mmNIC0_QPC0_GW_MASK_9 0x541F148 + +#define mmNIC0_QPC0_GW_MASK_10 0x541F14C + +#define mmNIC0_QPC0_GW_MASK_11 0x541F150 + +#define mmNIC0_QPC0_GW_MASK_12 0x541F154 + +#define mmNIC0_QPC0_GW_MASK_13 0x541F158 + +#define mmNIC0_QPC0_GW_MASK_14 0x541F15C + +#define mmNIC0_QPC0_GW_MASK_15 0x541F160 + +#define mmNIC0_QPC0_GW_MASK_16 0x541F164 + +#define mmNIC0_QPC0_GW_MASK_17 0x541F168 + +#define mmNIC0_QPC0_GW_MASK_18 0x541F16C + +#define mmNIC0_QPC0_GW_MASK_19 0x541F170 + +#define mmNIC0_QPC0_GW_MASK_20 0x541F174 + +#define mmNIC0_QPC0_GW_MASK_21 0x541F178 + +#define mmNIC0_QPC0_GW_MASK_22 0x541F17C + +#define mmNIC0_QPC0_GW_MASK_23 0x541F180 + +#define mmNIC0_QPC0_GW_MASK_24 0x541F184 + +#define mmNIC0_QPC0_GW_MASK_25 0x541F188 + +#define mmNIC0_QPC0_GW_MASK_26 0x541F18C + +#define mmNIC0_QPC0_GW_MASK_27 0x541F190 + +#define mmNIC0_QPC0_GW_MASK_28 0x541F194 + +#define mmNIC0_QPC0_GW_MASK_29 0x541F198 + +#define mmNIC0_QPC0_GW_MASK_30 0x541F19C + +#define mmNIC0_QPC0_GW_MASK_31 0x541F1A0 + +#define mmNIC0_QPC0_CC_TIMEOUT 0x541F1B0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC + +#define mmNIC0_QPC0_CC_TICK_WRAP 0x541F200 + +#define mmNIC0_QPC0_CC_ROLLBACK 0x541F204 + +#define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208 + +#define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_0 0x541F250 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_1 0x541F254 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_2 0x541F258 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_4 0x541F260 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_5 0x541F264 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_6 0x541F268 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_8 0x541F270 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_9 0x541F274 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_10 0x541F278 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_12 0x541F280 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_13 0x541F284 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_14 0x541F288 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC + +#define mmNIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC + +#define mmNIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC + +#define mmNIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC + +#define mmNIC0_QPC0_CC_WINDOW_INC_12 0x541F300 + +#define mmNIC0_QPC0_CC_WINDOW_INC_13 0x541F304 + +#define mmNIC0_QPC0_CC_WINDOW_INC_14 0x541F308 + +#define mmNIC0_QPC0_CC_WINDOW_INC_15 0x541F30C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC + +#define mmNIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0 + +#define mmNIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4 + +#define mmNIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8 + +#define mmNIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC + +#define mmNIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0 + +#define mmNIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4 + +#define mmNIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8 + +#define mmNIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC + +#define mmNIC0_QPC0_DB_FIFO_CFG_8 0x541F400 + +#define mmNIC0_QPC0_DB_FIFO_CFG_9 0x541F404 + +#define mmNIC0_QPC0_DB_FIFO_CFG_10 0x541F408 + +#define mmNIC0_QPC0_DB_FIFO_CFG_11 0x541F40C + +#define mmNIC0_QPC0_DB_FIFO_CFG_12 0x541F410 + +#define mmNIC0_QPC0_DB_FIFO_CFG_13 0x541F414 + +#define mmNIC0_QPC0_DB_FIFO_CFG_14 0x541F418 + +#define mmNIC0_QPC0_DB_FIFO_CFG_15 0x541F41C + +#define mmNIC0_QPC0_DB_FIFO_CFG_16 0x541F420 + +#define mmNIC0_QPC0_DB_FIFO_CFG_17 0x541F424 + +#define mmNIC0_QPC0_DB_FIFO_CFG_18 0x541F428 + +#define mmNIC0_QPC0_DB_FIFO_CFG_19 0x541F42C + +#define mmNIC0_QPC0_DB_FIFO_CFG_20 0x541F430 + +#define mmNIC0_QPC0_DB_FIFO_CFG_21 0x541F434 + +#define mmNIC0_QPC0_DB_FIFO_CFG_22 0x541F438 + +#define mmNIC0_QPC0_DB_FIFO_CFG_23 0x541F43C + +#define mmNIC0_QPC0_DB_FIFO_CFG_24 0x541F440 + +#define mmNIC0_QPC0_DB_FIFO_CFG_25 0x541F444 + +#define mmNIC0_QPC0_DB_FIFO_CFG_26 0x541F448 + +#define mmNIC0_QPC0_DB_FIFO_CFG_27 0x541F44C + +#define mmNIC0_QPC0_DB_FIFO_CFG_28 0x541F450 + +#define mmNIC0_QPC0_DB_FIFO_CFG_29 0x541F454 + +#define mmNIC0_QPC0_DB_FIFO_CFG_30 0x541F458 + +#define mmNIC0_QPC0_DB_FIFO_CFG_31 0x541F45C + +#define mmNIC0_QPC0_SECURED_DB_FIRST32 0x541F460 + +#define mmNIC0_QPC0_SECURED_DB_SECOND32 0x541F464 + +#define mmNIC0_QPC0_SECURED_DB_THIRD32 0x541F468 + +#define mmNIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C + +#define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470 + +#define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474 + +#define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478 + +#define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C + +#define mmNIC0_QPC0_DBG_INDICATION 0x541F480 + +#define mmNIC0_QPC0_WTD_WC_FSM 0x541F484 + +#define mmNIC0_QPC0_WTD_SLICE_FSM 0x541F488 + +#define mmNIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C + +#define mmNIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490 + +#define mmNIC0_QPC0_NUM_ROLLBACKS 0x541F494 + +#define mmNIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498 + +#define mmNIC0_QPC0_NUM_TIMEOUTS 0x541F49C + +#define mmNIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0 + +#define mmNIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8 + +#define mmNIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC + +#define mmNIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8 + +#define mmNIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC + +#define mmNIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC + +#define mmNIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0 + +#define mmNIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4 + +#define mmNIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC + +#define mmNIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0 + +#define mmNIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4 + +#define mmNIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC + +#define mmNIC0_QPC0_INTERRUPT_DATA_9 0x541F500 + +#define mmNIC0_QPC0_INTERRUPT_DATA_10 0x541F504 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C + +#define mmNIC0_QPC0_DOORBELL_SECURITY 0x541F648 + +#define mmNIC0_QPC0_DBG_CFG 0x541F64C + +#define mmNIC0_QPC0_RES_RING0_PI 0x541F650 + +#define mmNIC0_QPC0_RES_RING0_CI 0x541F654 + +#define mmNIC0_QPC0_RES_RING0_CFG 0x541F658 + +#define mmNIC0_QPC0_RES_RING1_PI 0x541F65C + +#define mmNIC0_QPC0_RES_RING1_CI 0x541F660 + +#define mmNIC0_QPC0_RES_RING1_CFG 0x541F664 + +#define mmNIC0_QPC0_RES_RING2_PI 0x541F668 + +#define mmNIC0_QPC0_RES_RING2_CI 0x541F66C + +#define mmNIC0_QPC0_RES_RING2_CFG 0x541F670 + +#define mmNIC0_QPC0_RES_RING3_PI 0x541F674 + +#define mmNIC0_QPC0_RES_RING3_CI 0x541F678 + +#define mmNIC0_QPC0_RES_RING3_CFG 0x541F67C + +#define mmNIC0_QPC0_REQ_RING0_CI 0x541F680 + +#define mmNIC0_QPC0_REQ_RING1_CI 0x541F684 + +#define mmNIC0_QPC0_REQ_RING2_CI 0x541F688 + +#define mmNIC0_QPC0_REQ_RING3_CI 0x541F68C + +#define mmNIC0_QPC0_INTERRUPT_CAUSE 0x541F690 + +#define mmNIC0_QPC0_INTERRUPT_MASK 0x541F694 + +#define mmNIC0_QPC0_INTERRUPT_CLR 0x541F698 + +#define mmNIC0_QPC0_INTERRUPT_EN 0x541F69C + +#define mmNIC0_QPC0_INTERRUPT_CFG 0x541F6F0 + +#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4 + +#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8 + +#define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700 + +#define mmNIC0_QPC0_TMR_GW_VALID 0x541F704 + +#define mmNIC0_QPC0_TMR_GW_DATA0 0x541F708 + +#define mmNIC0_QPC0_TMR_GW_DATA1 0x541F70C + +#define mmNIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710 + +#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830 + +#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834 + +#define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838 + +#define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C + +#define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840 + +#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844 + +#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848 + +#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C + +#define mmNIC0_QPC0_EVENT_QUE_CFG 0x541F850 + +#define mmNIC0_QPC0_LBW_PROT 0x541F858 + +#define mmNIC0_QPC0_MEM_WRITE_INIT 0x541F85C + +#define mmNIC0_QPC0_QMAN_DOORBELL 0x541F8E8 + +#define mmNIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC + +#define mmNIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0 + +#define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4 + +#define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8 + +#define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C + +#define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980 + +#define mmNIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984 + +#define mmNIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988 + +#define mmNIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C + +#define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990 + +#define mmNIC0_QPC0_WTD_CONFIG 0x541F994 + +#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998 + +#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C + +#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0 + +#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4 + +#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8 + +#define mmNIC0_QPC0_ARM_CQ_NUM 0x541F9AC + +#define mmNIC0_QPC0_ARM_CQ_INDEX 0x541F9B0 + +#define mmNIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4 + +#define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8 + +#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC + +#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0 + +#define mmNIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4 + +#define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8 + +#define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC + +#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0 + +#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4 + +#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8 + +#define mmNIC0_QPC0_CONG_QUE_CFG 0x541F9DC + +#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54 + +#define mmNIC0_QPC0_LINEAR_WQE_QPN 0x541FA58 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8 + +#endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */ |