Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted

Pull networking updates from Jakub Kicinski:
 "Core:

   - Add dedicated kmem_cache for typical/small skb->head, avoid having
     to access struct page at kfree time, and improve memory use.

   - Introduce sysctl to set default RPS configuration for new netdevs.

   - Define Netlink protocol specification format which can be used to
     describe messages used by each family and auto-generate parsers.
     Add tools for generating kernel data structures and uAPI headers.

   - Expose all net/core sysctls inside netns.

   - Remove 4s sleep in netpoll if carrier is instantly detected on
     boot.

   - Add configurable limit of MDB entries per port, and port-vlan.

   - Continue populating drop reasons throughout the stack.

   - Retire a handful of legacy Qdiscs and classifiers.

  Protocols:

   - Support IPv4 big TCP (TSO frames larger than 64kB).

   - Add IP_LOCAL_PORT_RANGE socket option, to control local port range
     on socket by socket basis.

   - Track and report in procfs number of MPTCP sockets used.

   - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
     manager.

   - IPv6: don't check net.ipv6.route.max_size and rely on garbage
     collection to free memory (similarly to IPv4).

   - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).

   - ICMP: add per-rate limit counters.

   - Add support for user scanning requests in ieee802154.

   - Remove static WEP support.

   - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
     reporting.

   - WiFi 7 EHT channel puncturing support (client & AP).

  BPF:

   - Add a rbtree data structure following the "next-gen data structure"
     precedent set by recently added linked list, that is, by using
     kfunc + kptr instead of adding a new BPF map type.

   - Expose XDP hints via kfuncs with initial support for RX hash and
     timestamp metadata.

   - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
     better support decap on GRE tunnel devices not operating in collect
     metadata.

   - Improve x86 JIT's codegen for PROBE_MEM runtime error checks.

   - Remove the need for trace_printk_lock for bpf_trace_printk and
     bpf_trace_vprintk helpers.

   - Extend libbpf's bpf_tracing.h support for tracing arguments of
     kprobes/uprobes and syscall as a special case.

   - Significantly reduce the search time for module symbols by
     livepatch and BPF.

   - Enable cpumasks to be used as kptrs, which is useful for tracing
     programs tracking which tasks end up running on which CPUs in
     different time intervals.

   - Add support for BPF trampoline on s390x and riscv64.

   - Add capability to export the XDP features supported by the NIC.

   - Add __bpf_kfunc tag for marking kernel functions as kfuncs.

   - Add cgroup.memory=nobpf kernel parameter option to disable BPF
     memory accounting for container environments.

  Netfilter:

   - Remove the CLUSTERIP target. It has been marked as obsolete for
     years, and we still have WARN splats wrt races of the out-of-band
     /proc interface installed by this target.

   - Add 'destroy' commands to nf_tables. They are identical to the
     existing 'delete' commands, but do not return an error if the
     referenced object (set, chain, rule...) did not exist.

  Driver API:

   - Improve cpumask_local_spread() locality to help NICs set the right
     IRQ affinity on AMD platforms.

   - Separate C22 and C45 MDIO bus transactions more clearly.

   - Introduce new DCB table to control DSCP rewrite on egress.

   - Support configuration of Physical Layer Collision Avoidance (PLCA)
     Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
     shared medium Ethernet.

   - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
     preemption of low priority frames by high priority frames.

   - Add support for controlling MACSec offload using netlink SET.

   - Rework devlink instance refcounts to allow registration and
     de-registration under the instance lock. Split the code into
     multiple files, drop some of the unnecessarily granular locks and
     factor out common parts of netlink operation handling.

   - Add TX frame aggregation parameters (for USB drivers).

   - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
     messages with notifications for debug.

   - Allow offloading of UDP NEW connections via act_ct.

   - Add support for per action HW stats in TC.

   - Support hardware miss to TC action (continue processing in SW from
     a specific point in the action chain).

   - Warn if old Wireless Extension user space interface is used with
     modern cfg80211/mac80211 drivers. Do not support Wireless
     Extensions for Wi-Fi 7 devices at all. Everyone should switch to
     using nl80211 interface instead.

   - Improve the CAN bit timing configuration. Use extack to return
     error messages directly to user space, update the SJW handling,
     including the definition of a new default value that will benefit
     CAN-FD controllers, by increasing their oscillator tolerance.

  New hardware / drivers:

   - Ethernet:
      - nVidia BlueField-3 support (control traffic driver)
      - Ethernet support for imx93 SoCs
      - Motorcomm yt8531 gigabit Ethernet PHY
      - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
      - Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
      - Amlogic gxl MDIO mux

   - WiFi:
      - RealTek RTL8188EU (rtl8xxxu)
      - Qualcomm Wi-Fi 7 devices (ath12k)

   - CAN:
      - Renesas R-Car V4H

  Drivers:

   - Bluetooth:
      - Set Per Platform Antenna Gain (PPAG) for Intel controllers.

   - Ethernet NICs:
      - Intel (1G, igc):
         - support TSN / Qbv / packet scheduling features of i226 model
      - Intel (100G, ice):
         - use GNSS subsystem instead of TTY
         - multi-buffer XDP support
         - extend support for GPIO pins to E823 devices
      - nVidia/Mellanox:
         - update the shared buffer configuration on PFC commands
         - implement PTP adjphase function for HW offset control
         - TC support for Geneve and GRE with VF tunnel offload
         - more efficient crypto key management method
         - multi-port eswitch support
      - Netronome/Corigine:
         - add DCB IEEE support
         - support IPsec offloading for NFP3800
      - Freescale/NXP (enetc):
         - support XDP_REDIRECT for XDP non-linear buffers
         - improve reconfig, avoid link flap and waiting for idle
         - support MAC Merge layer
      - Other NICs:
         - sfc/ef100: add basic devlink support for ef100
         - ionic: rx_push mode operation (writing descriptors via MMIO)
         - bnxt: use the auxiliary bus abstraction for RDMA
         - r8169: disable ASPM and reset bus in case of tx timeout
         - cpsw: support QSGMII mode for J721e CPSW9G
         - cpts: support pulse-per-second output
         - ngbe: add an mdio bus driver
         - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
         - r8152: handle devices with FW with NCM support
         - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
         - virtio-net: support multi buffer XDP
         - virtio/vsock: replace virtio_vsock_pkt with sk_buff
         - tsnep: XDP support

   - Ethernet high-speed switches:
      - nVidia/Mellanox (mlxsw):
         - add support for latency TLV (in FW control messages)
      - Microchip (sparx5):
         - separate explicit and implicit traffic forwarding rules, make
           the implicit rules always active
         - add support for egress DSCP rewrite
         - IS0 VCAP support (Ingress Classification)
         - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
           etc.)
         - ES2 VCAP support (Egress Access Control)
         - support for Per-Stream Filtering and Policing (802.1Q,
           8.6.5.1)

   - Ethernet embedded switches:
      - Marvell (mv88e6xxx):
         - add MAB (port auth) offload support
         - enable PTP receive for mv88e6390
      - NXP (ocelot):
         - support MAC Merge layer
         - support for the the vsc7512 internal copper phys
      - Microchip:
         - lan9303: convert to PHYLINK
         - lan966x: support TC flower filter statistics
         - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
         - lan937x: support Credit Based Shaper configuration
         - ksz9477: support Energy Efficient Ethernet
      - other:
         - qca8k: convert to regmap read/write API, use bulk operations
         - rswitch: Improve TX timestamp accuracy

   - Intel WiFi (iwlwifi):
      - EHT (Wi-Fi 7) rate reporting
      - STEP equalizer support: transfer some STEP (connection to radio
        on platforms with integrated wifi) related parameters from the
        BIOS to the firmware.

   - Qualcomm 802.11ax WiFi (ath11k):
      - IPQ5018 support
      - Fine Timing Measurement (FTM) responder role support
      - channel 177 support

   - MediaTek WiFi (mt76):
      - per-PHY LED support
      - mt7996: EHT (Wi-Fi 7) support
      - Wireless Ethernet Dispatch (WED) reset support
      - switch to using page pool allocator

   - RealTek WiFi (rtw89):
      - support new version of Bluetooth co-existance

   - Mobile:
      - rmnet: support TX aggregation"

* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
  page_pool: add a comment explaining the fragment counter usage
  net: ethtool: fix __ethtool_dev_mm_supported() implementation
  ethtool: pse-pd: Fix double word in comments
  xsk: add linux/vmalloc.h to xsk.c
  sefltests: netdevsim: wait for devlink instance after netns removal
  selftest: fib_tests: Always cleanup before exit
  net/mlx5e: Align IPsec ASO result memory to be as required by hardware
  net/mlx5e: TC, Set CT miss to the specific ct action instance
  net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
  net/mlx5: Refactor tc miss handling to a single function
  net/mlx5: Kconfig: Make tc offload depend on tc skb extension
  net/sched: flower: Support hardware miss to tc action
  net/sched: flower: Move filter handle initialization earlier
  net/sched: cls_api: Support hardware miss to tc action
  net/sched: Rename user cookie and act cookie
  sfc: fix builds without CONFIG_RTC_LIB
  sfc: clean up some inconsistent indentings
  net/mlx4_en: Introduce flexible array to silence overflow warning
  net: lan966x: Fix possible deadlock inside PTP
  net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
  ...

1 files changed, 514 insertions, 0 deletions

diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
new file mode 100644
index 000000000..2eab14f86
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *  linux/drivers/pinctrl/pinmux-falcon.c
+ *  based on linux/drivers/pinctrl/pinmux-pxa910.c
+ *
+ *  Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
+ *  Copyright (C) 2012 John Crispin <john@phrozen.org>
+ */
+
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+
+#include "pinctrl-lantiq.h"
+
+#include <lantiq_soc.h>
+
+/* Multiplexer Control Register */
+#define LTQ_PADC_MUX(x)         (x * 0x4)
+/* Pull Up Enable Register */
+#define LTQ_PADC_PUEN		0x80
+/* Pull Down Enable Register */
+#define LTQ_PADC_PDEN		0x84
+/* Slew Rate Control Register */
+#define LTQ_PADC_SRC		0x88
+/* Drive Current Control Register */
+#define LTQ_PADC_DCC		0x8C
+/* Pad Control Availability Register */
+#define LTQ_PADC_AVAIL          0xF0
+
+#define pad_r32(p, reg)		ltq_r32(p + reg)
+#define pad_w32(p, val, reg)	ltq_w32(val, p + reg)
+#define pad_w32_mask(c, clear, set, reg) \
+		pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
+
+#define pad_getbit(m, r, p)	(!!(ltq_r32(m + r) & (1 << p)))
+
+#define PORTS			5
+#define PINS			32
+#define PORT(x)                 (x / PINS)
+#define PORT_PIN(x)             (x % PINS)
+
+#define MFP_FALCON(a, f0, f1, f2, f3)		\
+{						\
+	.name = #a,				\
+	.pin = a,				\
+	.func = {				\
+		FALCON_MUX_##f0,		\
+		FALCON_MUX_##f1,		\
+		FALCON_MUX_##f2,		\
+		FALCON_MUX_##f3,		\
+	},					\
+}
+
+#define GRP_MUX(a, m, p)	\
+{				\
+	.name = a,		\
+	.mux = FALCON_MUX_##m,	\
+	.pins = p,		\
+	.npins = ARRAY_SIZE(p),	\
+}
+
+enum falcon_mux {
+	FALCON_MUX_GPIO = 0,
+	FALCON_MUX_RST,
+	FALCON_MUX_NTR,
+	FALCON_MUX_PPS,
+	FALCON_MUX_MDIO,
+	FALCON_MUX_LED,
+	FALCON_MUX_SPI,
+	FALCON_MUX_ASC,
+	FALCON_MUX_I2C,
+	FALCON_MUX_HOSTIF,
+	FALCON_MUX_SLIC,
+	FALCON_MUX_JTAG,
+	FALCON_MUX_PCM,
+	FALCON_MUX_MII,
+	FALCON_MUX_PHY,
+	FALCON_MUX_NONE = 0xffff,
+};
+
+static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
+static int pad_count[PORTS];
+
+static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
+{
+	int base = bank * PINS;
+	int i;
+
+	for (i = 0; i < len; i++) {
+		d[i].number = base + i;
+		d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i);
+	}
+	pad_count[bank] = len;
+}
+
+static struct ltq_mfp_pin falcon_mfp[] = {
+	/*	pin		f0	f1	f2	f3 */
+	MFP_FALCON(GPIO0,	RST,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO1,	GPIO,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO2,	GPIO,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO3,	GPIO,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO4,	NTR,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO5,	NTR,	GPIO,   PPS,    NONE),
+	MFP_FALCON(GPIO6,	RST,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO7,	MDIO,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO8,	MDIO,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO9,	LED,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO10,	LED,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO11,	LED,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO12,	LED,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO13,	LED,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO14,	LED,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO32,	ASC,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO33,	ASC,	GPIO,   NONE,   NONE),
+	MFP_FALCON(GPIO34,	SPI,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO35,	SPI,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO36,	SPI,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO37,	SPI,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO38,	SPI,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO39,	I2C,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO40,	I2C,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO41,	HOSTIF,	GPIO,	HOSTIF,	JTAG),
+	MFP_FALCON(GPIO42,	HOSTIF,	GPIO,	HOSTIF,	NONE),
+	MFP_FALCON(GPIO43,	SLIC,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO44,	SLIC,	GPIO,	PCM,	ASC),
+	MFP_FALCON(GPIO45,	SLIC,	GPIO,	PCM,	ASC),
+	MFP_FALCON(GPIO64,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO65,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO66,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO67,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO68,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO69,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO70,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO71,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO72,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO73,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO74,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO75,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO76,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO77,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO78,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO79,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO80,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO81,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO82,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO83,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO84,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO85,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO86,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO87,	MII,	GPIO,	NONE,	NONE),
+	MFP_FALCON(GPIO88,	PHY,	GPIO,	NONE,	NONE),
+};
+
+static const unsigned pins_por[] = {GPIO0};
+static const unsigned pins_ntr[] = {GPIO4};
+static const unsigned pins_ntr8k[] = {GPIO5};
+static const unsigned pins_pps[] = {GPIO5};
+static const unsigned pins_hrst[] = {GPIO6};
+static const unsigned pins_mdio[] = {GPIO7, GPIO8};
+static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
+					GPIO12, GPIO13, GPIO14};
+static const unsigned pins_asc0[] = {GPIO32, GPIO33};
+static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
+static const unsigned pins_spi_cs0[] = {GPIO37};
+static const unsigned pins_spi_cs1[] = {GPIO38};
+static const unsigned pins_i2c[] = {GPIO39, GPIO40};
+static const unsigned pins_jtag[] = {GPIO41};
+static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
+static const unsigned pins_pcm[] = {GPIO44, GPIO45};
+static const unsigned pins_asc1[] = {GPIO44, GPIO45};
+
+static struct ltq_pin_group falcon_grps[] = {
+	GRP_MUX("por", RST, pins_por),
+	GRP_MUX("ntr", NTR, pins_ntr),
+	GRP_MUX("ntr8k", NTR, pins_ntr8k),
+	GRP_MUX("pps", PPS, pins_pps),
+	GRP_MUX("hrst", RST, pins_hrst),
+	GRP_MUX("mdio", MDIO, pins_mdio),
+	GRP_MUX("bootled", LED, pins_bled),
+	GRP_MUX("asc0", ASC, pins_asc0),
+	GRP_MUX("spi", SPI, pins_spi),
+	GRP_MUX("spi cs0", SPI, pins_spi_cs0),
+	GRP_MUX("spi cs1", SPI, pins_spi_cs1),
+	GRP_MUX("i2c", I2C, pins_i2c),
+	GRP_MUX("jtag", JTAG, pins_jtag),
+	GRP_MUX("slic", SLIC, pins_slic),
+	GRP_MUX("pcm", PCM, pins_pcm),
+	GRP_MUX("asc1", ASC, pins_asc1),
+};
+
+static const char * const ltq_rst_grps[] = {"por", "hrst"};
+static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
+static const char * const ltq_mdio_grps[] = {"mdio"};
+static const char * const ltq_bled_grps[] = {"bootled"};
+static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
+static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
+static const char * const ltq_i2c_grps[] = {"i2c"};
+static const char * const ltq_jtag_grps[] = {"jtag"};
+static const char * const ltq_slic_grps[] = {"slic"};
+static const char * const ltq_pcm_grps[] = {"pcm"};
+
+static struct ltq_pmx_func falcon_funcs[] = {
+	{"rst",		ARRAY_AND_SIZE(ltq_rst_grps)},
+	{"ntr",		ARRAY_AND_SIZE(ltq_ntr_grps)},
+	{"mdio",	ARRAY_AND_SIZE(ltq_mdio_grps)},
+	{"led",		ARRAY_AND_SIZE(ltq_bled_grps)},
+	{"asc",		ARRAY_AND_SIZE(ltq_asc_grps)},
+	{"spi",		ARRAY_AND_SIZE(ltq_spi_grps)},
+	{"i2c",		ARRAY_AND_SIZE(ltq_i2c_grps)},
+	{"jtag",	ARRAY_AND_SIZE(ltq_jtag_grps)},
+	{"slic",	ARRAY_AND_SIZE(ltq_slic_grps)},
+	{"pcm",		ARRAY_AND_SIZE(ltq_pcm_grps)},
+};
+
+
+
+
+/* ---------  pinconf related code --------- */
+static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
+				unsigned group, unsigned long *config)
+{
+	return -ENOTSUPP;
+}
+
+static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
+				unsigned group, unsigned long *configs,
+				unsigned num_configs)
+{
+	return -ENOTSUPP;
+}
+
+static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
+				unsigned pin, unsigned long *config)
+{
+	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+	enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
+	void __iomem *mem = info->membase[PORT(pin)];
+
+	switch (param) {
+	case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
+		*config = LTQ_PINCONF_PACK(param,
+			!!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
+		break;
+
+	case LTQ_PINCONF_PARAM_SLEW_RATE:
+		*config = LTQ_PINCONF_PACK(param,
+			!!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
+		break;
+
+	case LTQ_PINCONF_PARAM_PULL:
+		if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
+			*config = LTQ_PINCONF_PACK(param, 1);
+		else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
+			*config = LTQ_PINCONF_PACK(param, 2);
+		else
+			*config = LTQ_PINCONF_PACK(param, 0);
+
+		break;
+
+	default:
+		return -ENOTSUPP;
+	}
+
+	return 0;
+}
+
+static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
+			unsigned pin, unsigned long *configs,
+			unsigned num_configs)
+{
+	enum ltq_pinconf_param param;
+	int arg;
+	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+	void __iomem *mem = info->membase[PORT(pin)];
+	u32 reg;
+	int i;
+
+	for (i = 0; i < num_configs; i++) {
+		param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
+		arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
+
+		switch (param) {
+		case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
+			reg = LTQ_PADC_DCC;
+			break;
+
+		case LTQ_PINCONF_PARAM_SLEW_RATE:
+			reg = LTQ_PADC_SRC;
+			break;
+
+		case LTQ_PINCONF_PARAM_PULL:
+			if (arg == 1)
+				reg = LTQ_PADC_PDEN;
+			else
+				reg = LTQ_PADC_PUEN;
+			break;
+
+		default:
+			pr_err("%s: Invalid config param %04x\n",
+			pinctrl_dev_get_name(pctrldev), param);
+			return -ENOTSUPP;
+		}
+
+		pad_w32(mem, BIT(PORT_PIN(pin)), reg);
+		if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
+			return -ENOTSUPP;
+	} /* for each config */
+
+	return 0;
+}
+
+static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
+			struct seq_file *s, unsigned offset)
+{
+	unsigned long config;
+	struct pin_desc *desc;
+
+	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+	int port = PORT(offset);
+
+	seq_printf(s, " (port %d) mux %d -- ", port,
+		pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
+
+	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
+	if (!falcon_pinconf_get(pctrldev, offset, &config))
+		seq_printf(s, "pull %d ",
+			(int)LTQ_PINCONF_UNPACK_ARG(config));
+
+	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
+	if (!falcon_pinconf_get(pctrldev, offset, &config))
+		seq_printf(s, "drive-current %d ",
+			(int)LTQ_PINCONF_UNPACK_ARG(config));
+
+	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
+	if (!falcon_pinconf_get(pctrldev, offset, &config))
+		seq_printf(s, "slew-rate %d ",
+			(int)LTQ_PINCONF_UNPACK_ARG(config));
+
+	desc = pin_desc_get(pctrldev, offset);
+	if (desc) {
+		if (desc->gpio_owner)
+			seq_printf(s, " owner: %s", desc->gpio_owner);
+	} else {
+		seq_printf(s, " not registered");
+	}
+}
+
+static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
+			struct seq_file *s, unsigned selector)
+{
+}
+
+static const struct pinconf_ops falcon_pinconf_ops = {
+	.pin_config_get			= falcon_pinconf_get,
+	.pin_config_set			= falcon_pinconf_set,
+	.pin_config_group_get		= falcon_pinconf_group_get,
+	.pin_config_group_set		= falcon_pinconf_group_set,
+	.pin_config_dbg_show		= falcon_pinconf_dbg_show,
+	.pin_config_group_dbg_show	= falcon_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc falcon_pctrl_desc = {
+	.owner		= THIS_MODULE,
+	.pins		= falcon_pads,
+	.confops	= &falcon_pinconf_ops,
+};
+
+static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
+			int mfp, int mux)
+{
+	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+	int port = PORT(info->mfp[mfp].pin);
+
+	if ((port >= PORTS) || (!info->membase[port]))
+		return -ENODEV;
+
+	pad_w32(info->membase[port], mux,
+		LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
+	return 0;
+}
+
+static const struct ltq_cfg_param falcon_cfg_params[] = {
+	{"lantiq,pull",			LTQ_PINCONF_PARAM_PULL},
+	{"lantiq,drive-current",	LTQ_PINCONF_PARAM_DRIVE_CURRENT},
+	{"lantiq,slew-rate",		LTQ_PINCONF_PARAM_SLEW_RATE},
+};
+
+static struct ltq_pinmux_info falcon_info = {
+	.desc		= &falcon_pctrl_desc,
+	.apply_mux	= falcon_mux_apply,
+	.params		= falcon_cfg_params,
+	.num_params	= ARRAY_SIZE(falcon_cfg_params),
+};
+
+
+
+
+/* --------- register the pinctrl layer --------- */
+
+int pinctrl_falcon_get_range_size(int id)
+{
+	u32 avail;
+
+	if ((id >= PORTS) || (!falcon_info.membase[id]))
+		return -EINVAL;
+
+	avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
+
+	return fls(avail);
+}
+
+void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
+{
+	pinctrl_add_gpio_range(falcon_info.pctrl, range);
+}
+
+static int pinctrl_falcon_probe(struct platform_device *pdev)
+{
+	struct device_node *np;
+	int pad_count = 0;
+	int ret = 0;
+
+	/* load and remap the pad resources of the different banks */
+	for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
+		const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
+		struct resource res;
+		struct platform_device *ppdev;
+		u32 avail;
+		int pins;
+
+		if (!of_device_is_available(np))
+			continue;
+
+		if (!bank || *bank >= PORTS)
+			continue;
+		if (of_address_to_resource(np, 0, &res))
+			continue;
+
+		ppdev = of_find_device_by_node(np);
+		if (!ppdev) {
+			dev_err(&pdev->dev, "failed to find pad pdev\n");
+			continue;
+		}
+
+		falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
+		put_device(&ppdev->dev);
+		if (IS_ERR(falcon_info.clk[*bank])) {
+			dev_err(&ppdev->dev, "failed to get clock\n");
+			of_node_put(np);
+			return PTR_ERR(falcon_info.clk[*bank]);
+		}
+		falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
+								   &res);
+		if (IS_ERR(falcon_info.membase[*bank])) {
+			of_node_put(np);
+			return PTR_ERR(falcon_info.membase[*bank]);
+		}
+
+		avail = pad_r32(falcon_info.membase[*bank],
+					LTQ_PADC_AVAIL);
+		pins = fls(avail);
+		lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
+		pad_count += pins;
+		clk_enable(falcon_info.clk[*bank]);
+		dev_dbg(&pdev->dev, "found %s with %d pads\n",
+				res.name, pins);
+	}
+	dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
+	falcon_pctrl_desc.name	= dev_name(&pdev->dev);
+	falcon_pctrl_desc.npins	= pad_count;
+
+	falcon_info.mfp		= falcon_mfp;
+	falcon_info.num_mfp	= ARRAY_SIZE(falcon_mfp);
+	falcon_info.grps	= falcon_grps;
+	falcon_info.num_grps	= ARRAY_SIZE(falcon_grps);
+	falcon_info.funcs	= falcon_funcs;
+	falcon_info.num_funcs	= ARRAY_SIZE(falcon_funcs);
+
+	ret = ltq_pinctrl_register(pdev, &falcon_info);
+	if (!ret)
+		dev_info(&pdev->dev, "Init done\n");
+	return ret;
+}
+
+static const struct of_device_id falcon_match[] = {
+	{ .compatible = "lantiq,pinctrl-falcon" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, falcon_match);
+
+static struct platform_driver pinctrl_falcon_driver = {
+	.probe = pinctrl_falcon_probe,
+	.driver = {
+		.name = "pinctrl-falcon",
+		.of_match_table = falcon_match,
+	},
+};
+
+int __init pinctrl_falcon_init(void)
+{
+	return platform_driver_register(&pinctrl_falcon_driver);
+}
+
+core_initcall_sync(pinctrl_falcon_init);