From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- arch/arm/mach-meson/platsmp.c | 432 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 432 insertions(+) create mode 100644 arch/arm/mach-meson/platsmp.c (limited to 'arch/arm/mach-meson/platsmp.c') diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c new file mode 100644 index 000000000..32ac60b89 --- /dev/null +++ b/arch/arm/mach-meson/platsmp.c @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2015 Carlo Caione + * Copyright (C) 2017 Martin Blumenstingl + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define MESON_SMP_SRAM_CPU_CTRL_REG (0x00) +#define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2)) + +#define MESON_CPU_AO_RTI_PWR_A9_CNTL0 (0x00) +#define MESON_CPU_AO_RTI_PWR_A9_CNTL1 (0x04) +#define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0 (0x14) + +#define MESON_CPU_PWR_A9_CNTL0_M(c) (0x03 << ((c * 2) + 16)) +#define MESON_CPU_PWR_A9_CNTL1_M(c) (0x03 << ((c + 1) << 1)) +#define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4))) +#define MESON_CPU_PWR_A9_CNTL1_ST(c) (0x01 << (c + 16)) + +static void __iomem *sram_base; +static void __iomem *scu_base; +static struct regmap *pmu; + +static struct reset_control *meson_smp_get_core_reset(int cpu) +{ + struct device_node *np = of_get_cpu_node(cpu, 0); + + return of_reset_control_get_exclusive(np, NULL); +} + +static void meson_smp_set_cpu_ctrl(int cpu, bool on_off) +{ + u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG); + + if (on_off) + val |= BIT(cpu); + else + val &= ~BIT(cpu); + + /* keep bit 0 always enabled */ + val |= BIT(0); + + writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG); +} + +static void __init meson_smp_prepare_cpus(const char *scu_compatible, + const char *pmu_compatible, + const char *sram_compatible) +{ + static struct device_node *node; + + /* SMP SRAM */ + node = of_find_compatible_node(NULL, NULL, sram_compatible); + if (!node) { + pr_err("Missing SRAM node\n"); + return; + } + + sram_base = of_iomap(node, 0); + of_node_put(node); + if (!sram_base) { + pr_err("Couldn't map SRAM registers\n"); + return; + } + + /* PMU */ + pmu = syscon_regmap_lookup_by_compatible(pmu_compatible); + if (IS_ERR(pmu)) { + pr_err("Couldn't map PMU registers\n"); + return; + } + + /* SCU */ + node = of_find_compatible_node(NULL, NULL, scu_compatible); + if (!node) { + pr_err("Missing SCU node\n"); + return; + } + + scu_base = of_iomap(node, 0); + of_node_put(node); + if (!scu_base) { + pr_err("Couldn't map SCU registers\n"); + return; + } + + scu_enable(scu_base); +} + +static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus) +{ + meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", + "amlogic,meson8b-smp-sram"); +} + +static void __init meson8_smp_prepare_cpus(unsigned int max_cpus) +{ + meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", + "amlogic,meson8-smp-sram"); +} + +static void meson_smp_begin_secondary_boot(unsigned int cpu) +{ + /* + * Set the entry point before powering on the CPU through the SCU. This + * is needed if the CPU is in "warm" state (= after rebooting the + * system without power-cycling, or when taking the CPU offline and + * then taking it online again. + */ + writel(__pa_symbol(secondary_startup), + sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu)); + + /* + * SCU Power on CPU (needs to be done before starting the CPU, + * otherwise the secondary CPU will not start). + */ + scu_cpu_power_enable(scu_base, cpu); +} + +static int meson_smp_finalize_secondary_boot(unsigned int cpu) +{ + unsigned long timeout; + + timeout = jiffies + (10 * HZ); + while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) { + if (!time_before(jiffies, timeout)) { + pr_err("Timeout while waiting for CPU%d status\n", + cpu); + return -ETIMEDOUT; + } + } + + writel(__pa_symbol(secondary_startup), + sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu)); + + meson_smp_set_cpu_ctrl(cpu, true); + + return 0; +} + +static int meson8_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + struct reset_control *rstc; + int ret; + + rstc = meson_smp_get_core_reset(cpu); + if (IS_ERR(rstc)) { + pr_err("Couldn't get the reset controller for CPU%d\n", cpu); + return PTR_ERR(rstc); + } + + meson_smp_begin_secondary_boot(cpu); + + /* Reset enable */ + ret = reset_control_assert(rstc); + if (ret) { + pr_err("Failed to assert CPU%d reset\n", cpu); + goto out; + } + + /* CPU power ON */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't wake up CPU%d\n", cpu); + goto out; + } + + udelay(10); + + /* Isolation disable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), + 0); + if (ret < 0) { + pr_err("Error when disabling isolation of CPU%d\n", cpu); + goto out; + } + + /* Reset disable */ + ret = reset_control_deassert(rstc); + if (ret) { + pr_err("Failed to de-assert CPU%d reset\n", cpu); + goto out; + } + + ret = meson_smp_finalize_secondary_boot(cpu); + if (ret) + goto out; + +out: + reset_control_put(rstc); + + return 0; +} + +static int meson8b_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + struct reset_control *rstc; + int ret; + u32 val; + + rstc = meson_smp_get_core_reset(cpu); + if (IS_ERR(rstc)) { + pr_err("Couldn't get the reset controller for CPU%d\n", cpu); + return PTR_ERR(rstc); + } + + meson_smp_begin_secondary_boot(cpu); + + /* CPU power UP */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, + MESON_CPU_PWR_A9_CNTL0_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't power up CPU%d\n", cpu); + goto out; + } + + udelay(5); + + /* Reset enable */ + ret = reset_control_assert(rstc); + if (ret) { + pr_err("Failed to assert CPU%d reset\n", cpu); + goto out; + } + + /* Memory power UP */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0, + MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't power up the memory for CPU%d\n", cpu); + goto out; + } + + /* Wake up CPU */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't wake up CPU%d\n", cpu); + goto out; + } + + udelay(10); + + ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val, + val & MESON_CPU_PWR_A9_CNTL1_ST(cpu), + 10, 10000); + if (ret) { + pr_err("Timeout while polling PMU for CPU%d status\n", cpu); + goto out; + } + + /* Isolation disable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), + 0); + if (ret < 0) { + pr_err("Error when disabling isolation of CPU%d\n", cpu); + goto out; + } + + /* Reset disable */ + ret = reset_control_deassert(rstc); + if (ret) { + pr_err("Failed to de-assert CPU%d reset\n", cpu); + goto out; + } + + ret = meson_smp_finalize_secondary_boot(cpu); + if (ret) + goto out; + +out: + reset_control_put(rstc); + + return 0; +} + +#ifdef CONFIG_HOTPLUG_CPU +static void meson8_smp_cpu_die(unsigned int cpu) +{ + meson_smp_set_cpu_ctrl(cpu, false); + + v7_exit_coherency_flush(louis); + + scu_power_mode(scu_base, SCU_PM_POWEROFF); + + dsb(); + wfi(); + + /* we should never get here */ + WARN_ON(1); +} + +static int meson8_smp_cpu_kill(unsigned int cpu) +{ + int ret, power_mode; + unsigned long timeout; + + timeout = jiffies + (50 * HZ); + do { + power_mode = scu_get_cpu_power_mode(scu_base, cpu); + + if (power_mode == SCU_PM_POWEROFF) + break; + + usleep_range(10000, 15000); + } while (time_before(jiffies, timeout)); + + if (power_mode != SCU_PM_POWEROFF) { + pr_err("Error while waiting for SCU power-off on CPU%d\n", + cpu); + return -ETIMEDOUT; + } + + msleep(30); + + /* Isolation enable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), + 0x3); + if (ret < 0) { + pr_err("Error when enabling isolation for CPU%d\n", cpu); + return ret; + } + + udelay(10); + + /* CPU power OFF */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3); + if (ret < 0) { + pr_err("Couldn't change sleep status of CPU%d\n", cpu); + return ret; + } + + return 1; +} + +static int meson8b_smp_cpu_kill(unsigned int cpu) +{ + int ret, power_mode, count = 5000; + + do { + power_mode = scu_get_cpu_power_mode(scu_base, cpu); + + if (power_mode == SCU_PM_POWEROFF) + break; + + udelay(10); + } while (++count); + + if (power_mode != SCU_PM_POWEROFF) { + pr_err("Error while waiting for SCU power-off on CPU%d\n", + cpu); + return -ETIMEDOUT; + } + + udelay(10); + + /* CPU power DOWN */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, + MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3); + if (ret < 0) { + pr_err("Couldn't power down CPU%d\n", cpu); + return ret; + } + + /* Isolation enable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), + 0x3); + if (ret < 0) { + pr_err("Error when enabling isolation for CPU%d\n", cpu); + return ret; + } + + udelay(10); + + /* Sleep status */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3); + if (ret < 0) { + pr_err("Couldn't change sleep status of CPU%d\n", cpu); + return ret; + } + + /* Memory power DOWN */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0, + MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf); + if (ret < 0) { + pr_err("Couldn't power down the memory of CPU%d\n", cpu); + return ret; + } + + return 1; +} +#endif + +static struct smp_operations meson8_smp_ops __initdata = { + .smp_prepare_cpus = meson8_smp_prepare_cpus, + .smp_boot_secondary = meson8_smp_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = meson8_smp_cpu_die, + .cpu_kill = meson8_smp_cpu_kill, +#endif +}; + +static struct smp_operations meson8b_smp_ops __initdata = { + .smp_prepare_cpus = meson8b_smp_prepare_cpus, + .smp_boot_secondary = meson8b_smp_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = meson8_smp_cpu_die, + .cpu_kill = meson8b_smp_cpu_kill, +#endif +}; + +CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops); +CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops); -- cgit v1.2.3