From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- arch/arm/mach-orion5x/common.c | 378 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 378 insertions(+) create mode 100644 arch/arm/mach-orion5x/common.c (limited to 'arch/arm/mach-orion5x/common.c') diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c new file mode 100644 index 000000000..df056d60b --- /dev/null +++ b/arch/arm/mach-orion5x/common.c @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * arch/arm/mach-orion5x/common.c + * + * Core functions for Marvell Orion 5x SoCs + * + * Maintainer: Tzachi Perelstein + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bridge-regs.h" +#include "common.h" +#include "orion5x.h" + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc orion5x_io_desc[] __initdata = { + { + .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), + .length = ORION5X_REGS_SIZE, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), + .length = ORION5X_PCIE_WA_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init orion5x_map_io(void) +{ + iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); +} + + +/***************************************************************************** + * CLK tree + ****************************************************************************/ +static struct clk *tclk; + +void __init clk_init(void) +{ + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk); + + orion_clkdev_init(tclk); +} + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +void __init orion5x_ehci0_init(void) +{ + orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, + EHCI_PHY_ORION); +} + + +/***************************************************************************** + * EHCI1 + ****************************************************************************/ +void __init orion5x_ehci1_init(void) +{ + orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); +} + + +/***************************************************************************** + * GE00 + ****************************************************************************/ +void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) +{ + orion_ge00_init(eth_data, + ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, + IRQ_ORION5X_ETH_ERR, + MV643XX_TX_CSUM_DEFAULT_LIMIT); +} + + +/***************************************************************************** + * I2C + ****************************************************************************/ +void __init orion5x_i2c_init(void) +{ + orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); + +} + + +/***************************************************************************** + * SATA + ****************************************************************************/ +void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) +{ + orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); +} + + +/***************************************************************************** + * SPI + ****************************************************************************/ +void __init orion5x_spi_init(void) +{ + orion_spi_init(SPI_PHYS_BASE); +} + + +/***************************************************************************** + * UART0 + ****************************************************************************/ +void __init orion5x_uart0_init(void) +{ + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_ORION5X_UART0, tclk); +} + +/***************************************************************************** + * UART1 + ****************************************************************************/ +void __init orion5x_uart1_init(void) +{ + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_ORION5X_UART1, tclk); +} + +/***************************************************************************** + * XOR engine + ****************************************************************************/ +void __init orion5x_xor_init(void) +{ + orion_xor0_init(ORION5X_XOR_PHYS_BASE, + ORION5X_XOR_PHYS_BASE + 0x200, + IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); +} + +/***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ +static void __init orion5x_crypto_init(void) +{ + mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, + ORION_MBUS_SRAM_ATTR, + ORION5X_SRAM_PHYS_BASE, + ORION5X_SRAM_SIZE); + orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, + SZ_8K, IRQ_ORION5X_CESA); +} + +/***************************************************************************** + * Watchdog + ****************************************************************************/ +static struct resource orion_wdt_resource[] = { + DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), + DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), +}; + +static struct platform_device orion_wdt_device = { + .name = "orion_wdt", + .id = -1, + .num_resources = ARRAY_SIZE(orion_wdt_resource), + .resource = orion_wdt_resource, +}; + +static void __init orion5x_wdt_init(void) +{ + platform_device_register(&orion_wdt_device); +} + + +/***************************************************************************** + * Time handling + ****************************************************************************/ +void __init orion5x_init_early(void) +{ + u32 rev, dev; + const char *mbus_soc_name; + + orion_time_set_base(TIMER_VIRT_BASE); + + /* Initialize the MBUS driver */ + orion5x_pcie_id(&dev, &rev); + if (dev == MV88F5281_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5281-mbus"; + else if (dev == MV88F5182_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5182-mbus"; + else if (dev == MV88F5181_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5181-mbus"; + else if (dev == MV88F6183_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f6183-mbus"; + else + mbus_soc_name = NULL; + mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, + ORION5X_BRIDGE_WINS_SZ, + ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); +} + +void orion5x_setup_wins(void) +{ + /* + * The PCIe windows will no longer be statically allocated + * here once Orion5x is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, + ORION_MBUS_PCIE_IO_ATTR, + ORION5X_PCIE_IO_PHYS_BASE, + ORION5X_PCIE_IO_SIZE, + ORION5X_PCIE_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, + ORION_MBUS_PCIE_MEM_ATTR, + ORION5X_PCIE_MEM_PHYS_BASE, + ORION5X_PCIE_MEM_SIZE); + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, + ORION_MBUS_PCI_IO_ATTR, + ORION5X_PCI_IO_PHYS_BASE, + ORION5X_PCI_IO_SIZE, + ORION5X_PCI_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, + ORION_MBUS_PCI_MEM_ATTR, + ORION5X_PCI_MEM_PHYS_BASE, + ORION5X_PCI_MEM_SIZE); +} + +int orion5x_tclk; + +static int __init orion5x_find_tclk(void) +{ + u32 dev, rev; + + orion5x_pcie_id(&dev, &rev); + if (dev == MV88F6183_DEV_ID && + (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) + return 133333333; + + return 166666667; +} + +void __init orion5x_timer_init(void) +{ + orion5x_tclk = orion5x_find_tclk(); + + orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + IRQ_ORION5X_BRIDGE, orion5x_tclk); +} + + +/***************************************************************************** + * General + ****************************************************************************/ +/* + * Identify device ID and rev from PCIe configuration header space '0'. + */ +void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) +{ + orion5x_pcie_id(dev, rev); + + if (*dev == MV88F5281_DEV_ID) { + if (*rev == MV88F5281_REV_D2) { + *dev_name = "MV88F5281-D2"; + } else if (*rev == MV88F5281_REV_D1) { + *dev_name = "MV88F5281-D1"; + } else if (*rev == MV88F5281_REV_D0) { + *dev_name = "MV88F5281-D0"; + } else { + *dev_name = "MV88F5281-Rev-Unsupported"; + } + } else if (*dev == MV88F5182_DEV_ID) { + if (*rev == MV88F5182_REV_A2) { + *dev_name = "MV88F5182-A2"; + } else { + *dev_name = "MV88F5182-Rev-Unsupported"; + } + } else if (*dev == MV88F5181_DEV_ID) { + if (*rev == MV88F5181_REV_B1) { + *dev_name = "MV88F5181-Rev-B1"; + } else if (*rev == MV88F5181L_REV_A1) { + *dev_name = "MV88F5181L-Rev-A1"; + } else { + *dev_name = "MV88F5181(L)-Rev-Unsupported"; + } + } else if (*dev == MV88F6183_DEV_ID) { + if (*rev == MV88F6183_REV_B0) { + *dev_name = "MV88F6183-Rev-B0"; + } else { + *dev_name = "MV88F6183-Rev-Unsupported"; + } + } else { + *dev_name = "Device-Unknown"; + } +} + +void __init orion5x_init(void) +{ + char *dev_name; + u32 dev, rev; + + orion5x_id(&dev, &rev, &dev_name); + printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); + + /* + * Setup Orion address map + */ + orion5x_setup_wins(); + + /* Setup root of clk tree */ + clk_init(); + + /* + * Don't issue "Wait for Interrupt" instruction if we are + * running on D0 5281 silicon. + */ + if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { + printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); + cpu_idle_poll_ctrl(true); + } + + /* + * The 5082/5181l/5182/6082/6082l/6183 have crypto + * while 5180n/5181/5281 don't have crypto. + */ + if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || + dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) + orion5x_crypto_init(); + + /* + * Register watchdog driver + */ + orion5x_wdt_init(); +} + +void orion5x_restart(enum reboot_mode mode, const char *cmd) +{ + /* + * Enable and issue soft reset + */ + orion5x_setbits(RSTOUTn_MASK, (1 << 2)); + orion5x_setbits(CPU_SOFT_RESET, 1); + mdelay(200); + orion5x_clrbits(CPU_SOFT_RESET, 1); +} + +/* + * Many orion-based systems have buggy bootloader implementations. + * This is a common fixup for bogus memory tags. + */ +void __init tag_fixup_mem32(struct tag *t, char **from) +{ + for (; t->hdr.size; t = tag_next(t)) + if (t->hdr.tag == ATAG_MEM && + (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || + t->u.mem.start & ~PAGE_MASK)) { + printk(KERN_WARNING + "Clearing invalid memory bank %dKB@0x%08x\n", + t->u.mem.size / 1024, t->u.mem.start); + t->hdr.tag = 0; + } +} -- cgit v1.2.3