From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- arch/mips/include/asm/octeon/cvmx-sriox-defs.h | 1614 ++++++++++++++++++++++++ 1 file changed, 1614 insertions(+) create mode 100644 arch/mips/include/asm/octeon/cvmx-sriox-defs.h (limited to 'arch/mips/include/asm/octeon/cvmx-sriox-defs.h') diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h new file mode 100644 index 000000000..34d0fadb5 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h @@ -0,0 +1,1614 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SRIOX_DEFS_H__ +#define __CVMX_SRIOX_DEFS_H__ + +#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull) + +union cvmx_sriox_acc_ctrl { + uint64_t u64; + struct cvmx_sriox_acc_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t deny_adr2:1; + uint64_t deny_adr1:1; + uint64_t deny_adr0:1; + uint64_t reserved_3_3:1; + uint64_t deny_bar2:1; + uint64_t deny_bar1:1; + uint64_t deny_bar0:1; +#else + uint64_t deny_bar0:1; + uint64_t deny_bar1:1; + uint64_t deny_bar2:1; + uint64_t reserved_3_3:1; + uint64_t deny_adr0:1; + uint64_t deny_adr1:1; + uint64_t deny_adr2:1; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_sriox_acc_ctrl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t deny_bar2:1; + uint64_t deny_bar1:1; + uint64_t deny_bar0:1; +#else + uint64_t deny_bar0:1; + uint64_t deny_bar1:1; + uint64_t deny_bar2:1; + uint64_t reserved_3_63:61; +#endif + } cn63xx; +}; + +union cvmx_sriox_asmbly_id { + uint64_t u64; + struct cvmx_sriox_asmbly_id_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t assy_id:16; + uint64_t assy_ven:16; +#else + uint64_t assy_ven:16; + uint64_t assy_id:16; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_asmbly_info { + uint64_t u64; + struct cvmx_sriox_asmbly_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t assy_rev:16; + uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t assy_rev:16; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_bell_resp_ctrl { + uint64_t u64; + struct cvmx_sriox_bell_resp_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t rp1_sid:1; + uint64_t rp0_sid:2; + uint64_t rp1_pid:1; + uint64_t rp0_pid:2; +#else + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_6_63:58; +#endif + } s; +}; + +union cvmx_sriox_bist_status { + uint64_t u64; + struct cvmx_sriox_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_45_63:19; + uint64_t lram:1; + uint64_t mram:2; + uint64_t cram:2; + uint64_t bell:2; + uint64_t otag:2; + uint64_t itag:1; + uint64_t ofree:1; + uint64_t rtn:2; + uint64_t obulk:4; + uint64_t optrs:4; + uint64_t oarb2:2; + uint64_t rxbuf2:2; + uint64_t oarb:2; + uint64_t ispf:1; + uint64_t ospf:1; + uint64_t txbuf:2; + uint64_t rxbuf:2; + uint64_t imsg:5; + uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t rxbuf2:2; + uint64_t oarb2:2; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t lram:1; + uint64_t reserved_45_63:19; +#endif + } s; + struct cvmx_sriox_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t mram:2; + uint64_t cram:2; + uint64_t bell:2; + uint64_t otag:2; + uint64_t itag:1; + uint64_t ofree:1; + uint64_t rtn:2; + uint64_t obulk:4; + uint64_t optrs:4; + uint64_t oarb2:2; + uint64_t rxbuf2:2; + uint64_t oarb:2; + uint64_t ispf:1; + uint64_t ospf:1; + uint64_t txbuf:2; + uint64_t rxbuf:2; + uint64_t imsg:5; + uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t rxbuf2:2; + uint64_t oarb2:2; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_sriox_bist_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t mram:2; + uint64_t cram:2; + uint64_t bell:2; + uint64_t otag:2; + uint64_t itag:1; + uint64_t ofree:1; + uint64_t rtn:2; + uint64_t obulk:4; + uint64_t optrs:4; + uint64_t reserved_20_23:4; + uint64_t oarb:2; + uint64_t ispf:1; + uint64_t ospf:1; + uint64_t txbuf:2; + uint64_t rxbuf:2; + uint64_t imsg:5; + uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t reserved_20_23:4; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t reserved_44_63:20; +#endif + } cn63xxp1; +}; + +union cvmx_sriox_imsg_ctrl { + uint64_t u64; + struct cvmx_sriox_imsg_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t to_mode:1; + uint64_t reserved_30_30:1; + uint64_t rsp_thr:6; + uint64_t reserved_22_23:2; + uint64_t rp1_sid:1; + uint64_t rp0_sid:2; + uint64_t rp1_pid:1; + uint64_t rp0_pid:2; + uint64_t reserved_15_15:1; + uint64_t prt_sel:3; + uint64_t lttr:4; + uint64_t prio:4; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t prio:4; + uint64_t lttr:4; + uint64_t prt_sel:3; + uint64_t reserved_15_15:1; + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_22_23:2; + uint64_t rsp_thr:6; + uint64_t reserved_30_30:1; + uint64_t to_mode:1; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_imsg_inst_hdrx { + uint64_t u64; + struct cvmx_sriox_imsg_inst_hdrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t r:1; + uint64_t reserved_58_62:5; + uint64_t pm:2; + uint64_t reserved_55_55:1; + uint64_t sl:7; + uint64_t reserved_46_47:2; + uint64_t nqos:1; + uint64_t ngrp:1; + uint64_t ntt:1; + uint64_t ntag:1; + uint64_t reserved_35_41:7; + uint64_t rs:1; + uint64_t tt:2; + uint64_t tag:32; +#else + uint64_t tag:32; + uint64_t tt:2; + uint64_t rs:1; + uint64_t reserved_35_41:7; + uint64_t ntag:1; + uint64_t ntt:1; + uint64_t ngrp:1; + uint64_t nqos:1; + uint64_t reserved_46_47:2; + uint64_t sl:7; + uint64_t reserved_55_55:1; + uint64_t pm:2; + uint64_t reserved_58_62:5; + uint64_t r:1; +#endif + } s; +}; + +union cvmx_sriox_imsg_qos_grpx { + uint64_t u64; + struct cvmx_sriox_imsg_qos_grpx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_63_63:1; + uint64_t qos7:3; + uint64_t grp7:4; + uint64_t reserved_55_55:1; + uint64_t qos6:3; + uint64_t grp6:4; + uint64_t reserved_47_47:1; + uint64_t qos5:3; + uint64_t grp5:4; + uint64_t reserved_39_39:1; + uint64_t qos4:3; + uint64_t grp4:4; + uint64_t reserved_31_31:1; + uint64_t qos3:3; + uint64_t grp3:4; + uint64_t reserved_23_23:1; + uint64_t qos2:3; + uint64_t grp2:4; + uint64_t reserved_15_15:1; + uint64_t qos1:3; + uint64_t grp1:4; + uint64_t reserved_7_7:1; + uint64_t qos0:3; + uint64_t grp0:4; +#else + uint64_t grp0:4; + uint64_t qos0:3; + uint64_t reserved_7_7:1; + uint64_t grp1:4; + uint64_t qos1:3; + uint64_t reserved_15_15:1; + uint64_t grp2:4; + uint64_t qos2:3; + uint64_t reserved_23_23:1; + uint64_t grp3:4; + uint64_t qos3:3; + uint64_t reserved_31_31:1; + uint64_t grp4:4; + uint64_t qos4:3; + uint64_t reserved_39_39:1; + uint64_t grp5:4; + uint64_t qos5:3; + uint64_t reserved_47_47:1; + uint64_t grp6:4; + uint64_t qos6:3; + uint64_t reserved_55_55:1; + uint64_t grp7:4; + uint64_t qos7:3; + uint64_t reserved_63_63:1; +#endif + } s; +}; + +union cvmx_sriox_imsg_statusx { + uint64_t u64; + struct cvmx_sriox_imsg_statusx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t val1:1; + uint64_t err1:1; + uint64_t toe1:1; + uint64_t toc1:1; + uint64_t prt1:1; + uint64_t reserved_58_58:1; + uint64_t tt1:1; + uint64_t dis1:1; + uint64_t seg1:4; + uint64_t mbox1:2; + uint64_t lttr1:2; + uint64_t sid1:16; + uint64_t val0:1; + uint64_t err0:1; + uint64_t toe0:1; + uint64_t toc0:1; + uint64_t prt0:1; + uint64_t reserved_26_26:1; + uint64_t tt0:1; + uint64_t dis0:1; + uint64_t seg0:4; + uint64_t mbox0:2; + uint64_t lttr0:2; + uint64_t sid0:16; +#else + uint64_t sid0:16; + uint64_t lttr0:2; + uint64_t mbox0:2; + uint64_t seg0:4; + uint64_t dis0:1; + uint64_t tt0:1; + uint64_t reserved_26_26:1; + uint64_t prt0:1; + uint64_t toc0:1; + uint64_t toe0:1; + uint64_t err0:1; + uint64_t val0:1; + uint64_t sid1:16; + uint64_t lttr1:2; + uint64_t mbox1:2; + uint64_t seg1:4; + uint64_t dis1:1; + uint64_t tt1:1; + uint64_t reserved_58_58:1; + uint64_t prt1:1; + uint64_t toc1:1; + uint64_t toe1:1; + uint64_t err1:1; + uint64_t val1:1; +#endif + } s; +}; + +union cvmx_sriox_imsg_vport_thr { + uint64_t u64; + struct cvmx_sriox_imsg_vport_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t max_tot:6; + uint64_t reserved_46_47:2; + uint64_t max_s1:6; + uint64_t reserved_38_39:2; + uint64_t max_s0:6; + uint64_t sp_vport:1; + uint64_t reserved_20_30:11; + uint64_t buf_thr:4; + uint64_t reserved_14_15:2; + uint64_t max_p1:6; + uint64_t reserved_6_7:2; + uint64_t max_p0:6; +#else + uint64_t max_p0:6; + uint64_t reserved_6_7:2; + uint64_t max_p1:6; + uint64_t reserved_14_15:2; + uint64_t buf_thr:4; + uint64_t reserved_20_30:11; + uint64_t sp_vport:1; + uint64_t max_s0:6; + uint64_t reserved_38_39:2; + uint64_t max_s1:6; + uint64_t reserved_46_47:2; + uint64_t max_tot:6; + uint64_t reserved_54_63:10; +#endif + } s; +}; + +union cvmx_sriox_imsg_vport_thr2 { + uint64_t u64; + struct cvmx_sriox_imsg_vport_thr2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_46_63:18; + uint64_t max_s3:6; + uint64_t reserved_38_39:2; + uint64_t max_s2:6; + uint64_t reserved_0_31:32; +#else + uint64_t reserved_0_31:32; + uint64_t max_s2:6; + uint64_t reserved_38_39:2; + uint64_t max_s3:6; + uint64_t reserved_46_63:18; +#endif + } s; +}; + +union cvmx_sriox_int2_enable { + uint64_t u64; + struct cvmx_sriox_int2_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t pko_rst:1; +#else + uint64_t pko_rst:1; + uint64_t reserved_1_63:63; +#endif + } s; +}; + +union cvmx_sriox_int2_reg { + uint64_t u64; + struct cvmx_sriox_int2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t int_sum:1; + uint64_t reserved_1_30:30; + uint64_t pko_rst:1; +#else + uint64_t pko_rst:1; + uint64_t reserved_1_30:30; + uint64_t int_sum:1; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_int_enable { + uint64_t u64; + struct cvmx_sriox_int_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_27_63:37; + uint64_t zero_pkt:1; + uint64_t ttl_tout:1; + uint64_t fail:1; + uint64_t degrade:1; + uint64_t mac_buf:1; + uint64_t f_error:1; + uint64_t rtry_err:1; + uint64_t pko_err:1; + uint64_t omsg_err:1; + uint64_t omsg1:1; + uint64_t omsg0:1; + uint64_t link_up:1; + uint64_t link_dwn:1; + uint64_t phy_erb:1; + uint64_t log_erb:1; + uint64_t soft_rx:1; + uint64_t soft_tx:1; + uint64_t mce_rx:1; + uint64_t mce_tx:1; + uint64_t wr_done:1; + uint64_t sli_err:1; + uint64_t deny_wr:1; + uint64_t bar_err:1; + uint64_t maint_op:1; + uint64_t rxbell:1; + uint64_t bell_err:1; + uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t mac_buf:1; + uint64_t degrade:1; + uint64_t fail:1; + uint64_t ttl_tout:1; + uint64_t zero_pkt:1; + uint64_t reserved_27_63:37; +#endif + } s; + struct cvmx_sriox_int_enable_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t f_error:1; + uint64_t rtry_err:1; + uint64_t pko_err:1; + uint64_t omsg_err:1; + uint64_t omsg1:1; + uint64_t omsg0:1; + uint64_t link_up:1; + uint64_t link_dwn:1; + uint64_t phy_erb:1; + uint64_t log_erb:1; + uint64_t soft_rx:1; + uint64_t soft_tx:1; + uint64_t mce_rx:1; + uint64_t mce_tx:1; + uint64_t wr_done:1; + uint64_t sli_err:1; + uint64_t deny_wr:1; + uint64_t bar_err:1; + uint64_t maint_op:1; + uint64_t rxbell:1; + uint64_t bell_err:1; + uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t reserved_22_63:42; +#endif + } cn63xxp1; +}; + +union cvmx_sriox_int_info0 { + uint64_t u64; + struct cvmx_sriox_int_info0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t cmd:4; + uint64_t type:4; + uint64_t tag:8; + uint64_t reserved_42_47:6; + uint64_t length:10; + uint64_t status:3; + uint64_t reserved_16_28:13; + uint64_t be0:8; + uint64_t be1:8; +#else + uint64_t be1:8; + uint64_t be0:8; + uint64_t reserved_16_28:13; + uint64_t status:3; + uint64_t length:10; + uint64_t reserved_42_47:6; + uint64_t tag:8; + uint64_t type:4; + uint64_t cmd:4; +#endif + } s; +}; + +union cvmx_sriox_int_info1 { + uint64_t u64; + struct cvmx_sriox_int_info1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t info1:64; +#else + uint64_t info1:64; +#endif + } s; +}; + +union cvmx_sriox_int_info2 { + uint64_t u64; + struct cvmx_sriox_int_info2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prio:2; + uint64_t tt:1; + uint64_t sis:1; + uint64_t ssize:4; + uint64_t did:16; + uint64_t xmbox:4; + uint64_t mbox:2; + uint64_t letter:2; + uint64_t rsrvd:30; + uint64_t lns:1; + uint64_t intr:1; +#else + uint64_t intr:1; + uint64_t lns:1; + uint64_t rsrvd:30; + uint64_t letter:2; + uint64_t mbox:2; + uint64_t xmbox:4; + uint64_t did:16; + uint64_t ssize:4; + uint64_t sis:1; + uint64_t tt:1; + uint64_t prio:2; +#endif + } s; +}; + +union cvmx_sriox_int_info3 { + uint64_t u64; + struct cvmx_sriox_int_info3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prio:2; + uint64_t tt:2; + uint64_t type:4; + uint64_t other:48; + uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t other:48; + uint64_t type:4; + uint64_t tt:2; + uint64_t prio:2; +#endif + } s; +}; + +union cvmx_sriox_int_reg { + uint64_t u64; + struct cvmx_sriox_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t int2_sum:1; + uint64_t reserved_27_30:4; + uint64_t zero_pkt:1; + uint64_t ttl_tout:1; + uint64_t fail:1; + uint64_t degrad:1; + uint64_t mac_buf:1; + uint64_t f_error:1; + uint64_t rtry_err:1; + uint64_t pko_err:1; + uint64_t omsg_err:1; + uint64_t omsg1:1; + uint64_t omsg0:1; + uint64_t link_up:1; + uint64_t link_dwn:1; + uint64_t phy_erb:1; + uint64_t log_erb:1; + uint64_t soft_rx:1; + uint64_t soft_tx:1; + uint64_t mce_rx:1; + uint64_t mce_tx:1; + uint64_t wr_done:1; + uint64_t sli_err:1; + uint64_t deny_wr:1; + uint64_t bar_err:1; + uint64_t maint_op:1; + uint64_t rxbell:1; + uint64_t bell_err:1; + uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t mac_buf:1; + uint64_t degrad:1; + uint64_t fail:1; + uint64_t ttl_tout:1; + uint64_t zero_pkt:1; + uint64_t reserved_27_30:4; + uint64_t int2_sum:1; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_sriox_int_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t f_error:1; + uint64_t rtry_err:1; + uint64_t pko_err:1; + uint64_t omsg_err:1; + uint64_t omsg1:1; + uint64_t omsg0:1; + uint64_t link_up:1; + uint64_t link_dwn:1; + uint64_t phy_erb:1; + uint64_t log_erb:1; + uint64_t soft_rx:1; + uint64_t soft_tx:1; + uint64_t mce_rx:1; + uint64_t mce_tx:1; + uint64_t wr_done:1; + uint64_t sli_err:1; + uint64_t deny_wr:1; + uint64_t bar_err:1; + uint64_t maint_op:1; + uint64_t rxbell:1; + uint64_t bell_err:1; + uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t reserved_22_63:42; +#endif + } cn63xxp1; +}; + +union cvmx_sriox_ip_feature { + uint64_t u64; + struct cvmx_sriox_ip_feature_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t ops:32; + uint64_t reserved_15_31:17; + uint64_t no_vmin:1; + uint64_t a66:1; + uint64_t a50:1; + uint64_t reserved_11_11:1; + uint64_t tx_flow:1; + uint64_t pt_width:2; + uint64_t tx_pol:4; + uint64_t rx_pol:4; +#else + uint64_t rx_pol:4; + uint64_t tx_pol:4; + uint64_t pt_width:2; + uint64_t tx_flow:1; + uint64_t reserved_11_11:1; + uint64_t a50:1; + uint64_t a66:1; + uint64_t no_vmin:1; + uint64_t reserved_15_31:17; + uint64_t ops:32; +#endif + } s; + struct cvmx_sriox_ip_feature_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t ops:32; + uint64_t reserved_14_31:18; + uint64_t a66:1; + uint64_t a50:1; + uint64_t reserved_11_11:1; + uint64_t tx_flow:1; + uint64_t pt_width:2; + uint64_t tx_pol:4; + uint64_t rx_pol:4; +#else + uint64_t rx_pol:4; + uint64_t tx_pol:4; + uint64_t pt_width:2; + uint64_t tx_flow:1; + uint64_t reserved_11_11:1; + uint64_t a50:1; + uint64_t a66:1; + uint64_t reserved_14_31:18; + uint64_t ops:32; +#endif + } cn63xx; +}; + +union cvmx_sriox_mac_buffers { + uint64_t u64; + struct cvmx_sriox_mac_buffers_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t tx_enb:8; + uint64_t reserved_44_47:4; + uint64_t tx_inuse:4; + uint64_t tx_stat:8; + uint64_t reserved_24_31:8; + uint64_t rx_enb:8; + uint64_t reserved_12_15:4; + uint64_t rx_inuse:4; + uint64_t rx_stat:8; +#else + uint64_t rx_stat:8; + uint64_t rx_inuse:4; + uint64_t reserved_12_15:4; + uint64_t rx_enb:8; + uint64_t reserved_24_31:8; + uint64_t tx_stat:8; + uint64_t tx_inuse:4; + uint64_t reserved_44_47:4; + uint64_t tx_enb:8; + uint64_t reserved_56_63:8; +#endif + } s; +}; + +union cvmx_sriox_maint_op { + uint64_t u64; + struct cvmx_sriox_maint_op_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t wr_data:32; + uint64_t reserved_27_31:5; + uint64_t fail:1; + uint64_t pending:1; + uint64_t op:1; + uint64_t addr:24; +#else + uint64_t addr:24; + uint64_t op:1; + uint64_t pending:1; + uint64_t fail:1; + uint64_t reserved_27_31:5; + uint64_t wr_data:32; +#endif + } s; +}; + +union cvmx_sriox_maint_rd_data { + uint64_t u64; + struct cvmx_sriox_maint_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t valid:1; + uint64_t rd_data:32; +#else + uint64_t rd_data:32; + uint64_t valid:1; + uint64_t reserved_33_63:31; +#endif + } s; +}; + +union cvmx_sriox_mce_tx_ctl { + uint64_t u64; + struct cvmx_sriox_mce_tx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t mce:1; +#else + uint64_t mce:1; + uint64_t reserved_1_63:63; +#endif + } s; +}; + +union cvmx_sriox_mem_op_ctrl { + uint64_t u64; + struct cvmx_sriox_mem_op_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t rr_ro:1; + uint64_t w_ro:1; + uint64_t reserved_6_7:2; + uint64_t rp1_sid:1; + uint64_t rp0_sid:2; + uint64_t rp1_pid:1; + uint64_t rp0_pid:2; +#else + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_6_7:2; + uint64_t w_ro:1; + uint64_t rr_ro:1; + uint64_t reserved_10_63:54; +#endif + } s; +}; + +union cvmx_sriox_omsg_ctrlx { + uint64_t u64; + struct cvmx_sriox_omsg_ctrlx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t testmode:1; + uint64_t reserved_37_62:26; + uint64_t silo_max:5; + uint64_t rtry_thr:16; + uint64_t rtry_en:1; + uint64_t reserved_11_14:4; + uint64_t idm_tt:1; + uint64_t idm_sis:1; + uint64_t idm_did:1; + uint64_t lttr_sp:4; + uint64_t lttr_mp:4; +#else + uint64_t lttr_mp:4; + uint64_t lttr_sp:4; + uint64_t idm_did:1; + uint64_t idm_sis:1; + uint64_t idm_tt:1; + uint64_t reserved_11_14:4; + uint64_t rtry_en:1; + uint64_t rtry_thr:16; + uint64_t silo_max:5; + uint64_t reserved_37_62:26; + uint64_t testmode:1; +#endif + } s; + struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t testmode:1; + uint64_t reserved_32_62:31; + uint64_t rtry_thr:16; + uint64_t rtry_en:1; + uint64_t reserved_11_14:4; + uint64_t idm_tt:1; + uint64_t idm_sis:1; + uint64_t idm_did:1; + uint64_t lttr_sp:4; + uint64_t lttr_mp:4; +#else + uint64_t lttr_mp:4; + uint64_t lttr_sp:4; + uint64_t idm_did:1; + uint64_t idm_sis:1; + uint64_t idm_tt:1; + uint64_t reserved_11_14:4; + uint64_t rtry_en:1; + uint64_t rtry_thr:16; + uint64_t reserved_32_62:31; + uint64_t testmode:1; +#endif + } cn63xxp1; +}; + +union cvmx_sriox_omsg_done_countsx { + uint64_t u64; + struct cvmx_sriox_omsg_done_countsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t bad:16; + uint64_t good:16; +#else + uint64_t good:16; + uint64_t bad:16; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_omsg_fmp_mrx { + uint64_t u64; + struct cvmx_sriox_omsg_fmp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t ctlr_sp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_nmp:1; + uint64_t id_sp:1; + uint64_t id_fmp:1; + uint64_t id_nmp:1; + uint64_t id_psd:1; + uint64_t mbox_sp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_nmp:1; + uint64_t mbox_psd:1; + uint64_t all_sp:1; + uint64_t all_fmp:1; + uint64_t all_nmp:1; + uint64_t all_psd:1; +#else + uint64_t all_psd:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t mbox_psd:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t id_psd:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t reserved_15_63:49; +#endif + } s; +}; + +union cvmx_sriox_omsg_nmp_mrx { + uint64_t u64; + struct cvmx_sriox_omsg_nmp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t ctlr_sp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_nmp:1; + uint64_t id_sp:1; + uint64_t id_fmp:1; + uint64_t id_nmp:1; + uint64_t reserved_8_8:1; + uint64_t mbox_sp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_nmp:1; + uint64_t reserved_4_4:1; + uint64_t all_sp:1; + uint64_t all_fmp:1; + uint64_t all_nmp:1; + uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t reserved_4_4:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t reserved_8_8:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t reserved_15_63:49; +#endif + } s; +}; + +union cvmx_sriox_omsg_portx { + uint64_t u64; + struct cvmx_sriox_omsg_portx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t enable:1; + uint64_t reserved_3_30:28; + uint64_t port:3; +#else + uint64_t port:3; + uint64_t reserved_3_30:28; + uint64_t enable:1; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_sriox_omsg_portx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t enable:1; + uint64_t reserved_2_30:29; + uint64_t port:2; +#else + uint64_t port:2; + uint64_t reserved_2_30:29; + uint64_t enable:1; + uint64_t reserved_32_63:32; +#endif + } cn63xx; +}; + +union cvmx_sriox_omsg_silo_thr { + uint64_t u64; + struct cvmx_sriox_omsg_silo_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_5_63:59; + uint64_t tot_silo:5; +#else + uint64_t tot_silo:5; + uint64_t reserved_5_63:59; +#endif + } s; +}; + +union cvmx_sriox_omsg_sp_mrx { + uint64_t u64; + struct cvmx_sriox_omsg_sp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t xmbox_sp:1; + uint64_t ctlr_sp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_nmp:1; + uint64_t id_sp:1; + uint64_t id_fmp:1; + uint64_t id_nmp:1; + uint64_t id_psd:1; + uint64_t mbox_sp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_nmp:1; + uint64_t mbox_psd:1; + uint64_t all_sp:1; + uint64_t all_fmp:1; + uint64_t all_nmp:1; + uint64_t all_psd:1; +#else + uint64_t all_psd:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t mbox_psd:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t id_psd:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t xmbox_sp:1; + uint64_t reserved_16_63:48; +#endif + } s; +}; + +union cvmx_sriox_priox_in_use { + uint64_t u64; + struct cvmx_sriox_priox_in_use_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t end_cnt:16; + uint64_t start_cnt:16; +#else + uint64_t start_cnt:16; + uint64_t end_cnt:16; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_rx_bell { + uint64_t u64; + struct cvmx_sriox_rx_bell_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t data:16; + uint64_t src_id:16; + uint64_t count:8; + uint64_t reserved_5_7:3; + uint64_t dest_id:1; + uint64_t id16:1; + uint64_t reserved_2_2:1; + uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t dest_id:1; + uint64_t reserved_5_7:3; + uint64_t count:8; + uint64_t src_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif + } s; +}; + +union cvmx_sriox_rx_bell_seq { + uint64_t u64; + struct cvmx_sriox_rx_bell_seq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_40_63:24; + uint64_t count:8; + uint64_t seq:32; +#else + uint64_t seq:32; + uint64_t count:8; + uint64_t reserved_40_63:24; +#endif + } s; +}; + +union cvmx_sriox_rx_status { + uint64_t u64; + struct cvmx_sriox_rx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rtn_pr3:8; + uint64_t rtn_pr2:8; + uint64_t rtn_pr1:8; + uint64_t reserved_28_39:12; + uint64_t mbox:4; + uint64_t comp:8; + uint64_t reserved_13_15:3; + uint64_t n_post:5; + uint64_t post:8; +#else + uint64_t post:8; + uint64_t n_post:5; + uint64_t reserved_13_15:3; + uint64_t comp:8; + uint64_t mbox:4; + uint64_t reserved_28_39:12; + uint64_t rtn_pr1:8; + uint64_t rtn_pr2:8; + uint64_t rtn_pr3:8; +#endif + } s; +}; + +union cvmx_sriox_s2m_typex { + uint64_t u64; + struct cvmx_sriox_s2m_typex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_19_63:45; + uint64_t wr_op:3; + uint64_t reserved_15_15:1; + uint64_t rd_op:3; + uint64_t wr_prior:2; + uint64_t rd_prior:2; + uint64_t reserved_6_7:2; + uint64_t src_id:1; + uint64_t id16:1; + uint64_t reserved_2_3:2; + uint64_t iaow_sel:2; +#else + uint64_t iaow_sel:2; + uint64_t reserved_2_3:2; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t reserved_6_7:2; + uint64_t rd_prior:2; + uint64_t wr_prior:2; + uint64_t rd_op:3; + uint64_t reserved_15_15:1; + uint64_t wr_op:3; + uint64_t reserved_19_63:45; +#endif + } s; +}; + +union cvmx_sriox_seq { + uint64_t u64; + struct cvmx_sriox_seq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t seq:32; +#else + uint64_t seq:32; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_status_reg { + uint64_t u64; + struct cvmx_sriox_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t access:1; + uint64_t srio:1; +#else + uint64_t srio:1; + uint64_t access:1; + uint64_t reserved_2_63:62; +#endif + } s; +}; + +union cvmx_sriox_tag_ctrl { + uint64_t u64; + struct cvmx_sriox_tag_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t o_clr:1; + uint64_t reserved_13_15:3; + uint64_t otag:5; + uint64_t reserved_5_7:3; + uint64_t itag:5; +#else + uint64_t itag:5; + uint64_t reserved_5_7:3; + uint64_t otag:5; + uint64_t reserved_13_15:3; + uint64_t o_clr:1; + uint64_t reserved_17_63:47; +#endif + } s; +}; + +union cvmx_sriox_tlp_credits { + uint64_t u64; + struct cvmx_sriox_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t mbox:4; + uint64_t comp:8; + uint64_t reserved_13_15:3; + uint64_t n_post:5; + uint64_t post:8; +#else + uint64_t post:8; + uint64_t n_post:5; + uint64_t reserved_13_15:3; + uint64_t comp:8; + uint64_t mbox:4; + uint64_t reserved_28_63:36; +#endif + } s; +}; + +union cvmx_sriox_tx_bell { + uint64_t u64; + struct cvmx_sriox_tx_bell_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t data:16; + uint64_t dest_id:16; + uint64_t reserved_9_15:7; + uint64_t pending:1; + uint64_t reserved_5_7:3; + uint64_t src_id:1; + uint64_t id16:1; + uint64_t reserved_2_2:1; + uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t reserved_5_7:3; + uint64_t pending:1; + uint64_t reserved_9_15:7; + uint64_t dest_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif + } s; +}; + +union cvmx_sriox_tx_bell_info { + uint64_t u64; + struct cvmx_sriox_tx_bell_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t data:16; + uint64_t dest_id:16; + uint64_t reserved_8_15:8; + uint64_t timeout:1; + uint64_t error:1; + uint64_t retry:1; + uint64_t src_id:1; + uint64_t id16:1; + uint64_t reserved_2_2:1; + uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t retry:1; + uint64_t error:1; + uint64_t timeout:1; + uint64_t reserved_8_15:8; + uint64_t dest_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif + } s; +}; + +union cvmx_sriox_tx_ctrl { + uint64_t u64; + struct cvmx_sriox_tx_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_53_63:11; + uint64_t tag_th2:5; + uint64_t reserved_45_47:3; + uint64_t tag_th1:5; + uint64_t reserved_37_39:3; + uint64_t tag_th0:5; + uint64_t reserved_20_31:12; + uint64_t tx_th2:4; + uint64_t reserved_12_15:4; + uint64_t tx_th1:4; + uint64_t reserved_4_7:4; + uint64_t tx_th0:4; +#else + uint64_t tx_th0:4; + uint64_t reserved_4_7:4; + uint64_t tx_th1:4; + uint64_t reserved_12_15:4; + uint64_t tx_th2:4; + uint64_t reserved_20_31:12; + uint64_t tag_th0:5; + uint64_t reserved_37_39:3; + uint64_t tag_th1:5; + uint64_t reserved_45_47:3; + uint64_t tag_th2:5; + uint64_t reserved_53_63:11; +#endif + } s; +}; + +union cvmx_sriox_tx_emphasis { + uint64_t u64; + struct cvmx_sriox_tx_emphasis_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t emph:4; +#else + uint64_t emph:4; + uint64_t reserved_4_63:60; +#endif + } s; +}; + +union cvmx_sriox_tx_status { + uint64_t u64; + struct cvmx_sriox_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t s2m_pr3:8; + uint64_t s2m_pr2:8; + uint64_t s2m_pr1:8; + uint64_t s2m_pr0:8; +#else + uint64_t s2m_pr0:8; + uint64_t s2m_pr1:8; + uint64_t s2m_pr2:8; + uint64_t s2m_pr3:8; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_wr_done_counts { + uint64_t u64; + struct cvmx_sriox_wr_done_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t bad:16; + uint64_t good:16; +#else + uint64_t good:16; + uint64_t bad:16; + uint64_t reserved_32_63:32; +#endif + } s; +}; + +#endif -- cgit v1.2.3