From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/char/agp/efficeon-agp.c | 468 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 468 insertions(+) create mode 100644 drivers/char/agp/efficeon-agp.c (limited to 'drivers/char/agp/efficeon-agp.c') diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-agp.c new file mode 100644 index 000000000..f28d42319 --- /dev/null +++ b/drivers/char/agp/efficeon-agp.c @@ -0,0 +1,468 @@ +/* + * Transmeta's Efficeon AGPGART driver. + * + * Based upon a diff by Linus around November '02. + * + * Ported to the 2.6 kernel by Carlos Puchol + * and H. Peter Anvin . + */ + +/* + * NOTE-cpg-040217: + * + * - when compiled as a module, after loading the module, + * it will refuse to unload, indicating it is in use, + * when it is not. + * - no s3 (suspend to ram) testing. + * - tested on the efficeon integrated nothbridge for tens + * of iterations of starting x and glxgears. + * - tested with radeon 9000 and radeon mobility m9 cards + * - tested with c3/c4 enabled (with the mobility m9 card) + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agp.h" +#include "intel-agp.h" + +/* + * The real differences to the generic AGP code is + * in the GART mappings - a two-level setup with the + * first level being an on-chip 64-entry table. + * + * The page array is filled through the ATTPAGE register + * (Aperture Translation Table Page Register) at 0xB8. Bits: + * 31:20: physical page address + * 11:9: Page Attribute Table Index (PATI) + * must match the PAT index for the + * mapped pages (the 2nd level page table pages + * themselves should be just regular WB-cacheable, + * so this is normally zero.) + * 8: Present + * 7:6: reserved, write as zero + * 5:0: GATT directory index: which 1st-level entry + * + * The Efficeon AGP spec requires pages to be WB-cacheable + * but to be explicitly CLFLUSH'd after any changes. + */ +#define EFFICEON_ATTPAGE 0xb8 +#define EFFICEON_L1_SIZE 64 /* Number of PDE pages */ + +#define EFFICEON_PATI (0 << 9) +#define EFFICEON_PRESENT (1 << 8) + +static struct _efficeon_private { + unsigned long l1_table[EFFICEON_L1_SIZE]; +} efficeon_private; + +static const struct gatt_mask efficeon_generic_masks[] = +{ + {.mask = 0x00000001, .type = 0} +}; + +/* This function does the same thing as mask_memory() for this chipset... */ +static inline unsigned long efficeon_mask_memory(struct page *page) +{ + unsigned long addr = page_to_phys(page); + return addr | 0x00000001; +} + +static const struct aper_size_info_lvl2 efficeon_generic_sizes[4] = +{ + {256, 65536, 0}, + {128, 32768, 32}, + {64, 16384, 48}, + {32, 8192, 56} +}; + +/* + * Control interfaces are largely identical to + * the legacy Intel 440BX.. + */ + +static int efficeon_fetch_size(void) +{ + int i; + u16 temp; + struct aper_size_info_lvl2 *values; + + pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); + values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +static void efficeon_tlbflush(struct agp_memory * mem) +{ + printk(KERN_DEBUG PFX "efficeon_tlbflush()\n"); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); +} + +static void efficeon_cleanup(void) +{ + u16 temp; + struct aper_size_info_lvl2 *previous_size; + + printk(KERN_DEBUG PFX "efficeon_cleanup()\n"); + previous_size = A_SIZE_LVL2(agp_bridge->previous_size); + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); + pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, + previous_size->size_value); +} + +static int efficeon_configure(void) +{ + u16 temp2; + struct aper_size_info_lvl2 *current_size; + + printk(KERN_DEBUG PFX "efficeon_configure()\n"); + + current_size = A_SIZE_LVL2(agp_bridge->current_size); + + /* aperture size */ + pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, + current_size->size_value); + + /* address to map to */ + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, + AGP_APERTURE_BAR); + + /* agpctrl */ + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); + + /* paccfg/nbxcfg */ + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, + (temp2 & ~(1 << 10)) | (1 << 9) | (1 << 11)); + /* clear any possible error conditions */ + pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); + return 0; +} + +static int efficeon_free_gatt_table(struct agp_bridge_data *bridge) +{ + int index, freed = 0; + + for (index = 0; index < EFFICEON_L1_SIZE; index++) { + unsigned long page = efficeon_private.l1_table[index]; + if (page) { + efficeon_private.l1_table[index] = 0; + free_page(page); + freed++; + } + printk(KERN_DEBUG PFX "efficeon_free_gatt_table(%p, %02x, %08x)\n", + agp_bridge->dev, EFFICEON_ATTPAGE, index); + pci_write_config_dword(agp_bridge->dev, + EFFICEON_ATTPAGE, index); + } + printk(KERN_DEBUG PFX "efficeon_free_gatt_table() freed %d pages\n", freed); + return 0; +} + + +/* + * Since we don't need contiguous memory we just try + * to get the gatt table once + */ + +#define GET_PAGE_DIR_OFF(addr) (addr >> 22) +#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ + GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) +#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) +#undef GET_GATT +#define GET_GATT(addr) (efficeon_private.gatt_pages[\ + GET_PAGE_DIR_IDX(addr)]->remapped) + +static int efficeon_create_gatt_table(struct agp_bridge_data *bridge) +{ + int index; + const int pati = EFFICEON_PATI; + const int present = EFFICEON_PRESENT; + const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3; + int num_entries, l1_pages; + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + + printk(KERN_DEBUG PFX "efficeon_create_gatt_table(%d)\n", num_entries); + + /* There are 2^10 PTE pages per PDE page */ + BUG_ON(num_entries & 0x3ff); + l1_pages = num_entries >> 10; + + for (index = 0 ; index < l1_pages ; index++) { + int offset; + unsigned long page; + unsigned long value; + + page = efficeon_private.l1_table[index]; + BUG_ON(page); + + page = get_zeroed_page(GFP_KERNEL); + if (!page) { + efficeon_free_gatt_table(agp_bridge); + return -ENOMEM; + } + + for (offset = 0; offset < PAGE_SIZE; offset += clflush_chunk) + clflush((char *)page+offset); + + efficeon_private.l1_table[index] = page; + + value = virt_to_phys((unsigned long *)page) | pati | present | index; + + pci_write_config_dword(agp_bridge->dev, + EFFICEON_ATTPAGE, value); + } + + return 0; +} + +static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int type) +{ + int i, count = mem->page_count, num_entries; + unsigned int *page, *last_page; + const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3; + const unsigned long clflush_mask = ~(clflush_chunk-1); + + printk(KERN_DEBUG PFX "efficeon_insert_memory(%lx, %d)\n", pg_start, count); + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + if (type != 0 || mem->type != 0) + return -EINVAL; + + if (!mem->is_flushed) { + global_cache_flush(); + mem->is_flushed = true; + } + + last_page = NULL; + for (i = 0; i < count; i++) { + int index = pg_start + i; + unsigned long insert = efficeon_mask_memory(mem->pages[i]); + + page = (unsigned int *) efficeon_private.l1_table[index >> 10]; + + if (!page) + continue; + + page += (index & 0x3ff); + *page = insert; + + /* clflush is slow, so don't clflush until we have to */ + if (last_page && + (((unsigned long)page^(unsigned long)last_page) & + clflush_mask)) + clflush(last_page); + + last_page = page; + } + + if ( last_page ) + clflush(last_page); + + agp_bridge->driver->tlb_flush(mem); + return 0; +} + +static int efficeon_remove_memory(struct agp_memory * mem, off_t pg_start, int type) +{ + int i, count = mem->page_count, num_entries; + + printk(KERN_DEBUG PFX "efficeon_remove_memory(%lx, %d)\n", pg_start, count); + + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; + + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + if (type != 0 || mem->type != 0) + return -EINVAL; + + for (i = 0; i < count; i++) { + int index = pg_start + i; + unsigned int *page = (unsigned int *) efficeon_private.l1_table[index >> 10]; + + if (!page) + continue; + page += (index & 0x3ff); + *page = 0; + } + agp_bridge->driver->tlb_flush(mem); + return 0; +} + + +static const struct agp_bridge_driver efficeon_driver = { + .owner = THIS_MODULE, + .aperture_sizes = efficeon_generic_sizes, + .size_type = LVL2_APER_SIZE, + .num_aperture_sizes = 4, + .configure = efficeon_configure, + .fetch_size = efficeon_fetch_size, + .cleanup = efficeon_cleanup, + .tlb_flush = efficeon_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = efficeon_generic_masks, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + + // Efficeon-specific GATT table setup / populate / teardown + .create_gatt_table = efficeon_create_gatt_table, + .free_gatt_table = efficeon_free_gatt_table, + .insert_memory = efficeon_insert_memory, + .remove_memory = efficeon_remove_memory, + .cant_use_aperture = false, // true might be faster? + + // Generic + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_alloc_pages = agp_generic_alloc_pages, + .agp_destroy_page = agp_generic_destroy_page, + .agp_destroy_pages = agp_generic_destroy_pages, + .agp_type_to_mask_type = agp_generic_type_to_mask_type, +}; + +static int agp_efficeon_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct agp_bridge_data *bridge; + u8 cap_ptr; + struct resource *r; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + /* Probe for Efficeon controller */ + if (pdev->device != PCI_DEVICE_ID_EFFICEON) { + printk(KERN_ERR PFX "Unsupported Efficeon chipset (device id: %04x)\n", + pdev->device); + return -ENODEV; + } + + printk(KERN_INFO PFX "Detected Transmeta Efficeon TM8000 series chipset\n"); + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->driver = &efficeon_driver; + bridge->dev = pdev; + bridge->capndx = cap_ptr; + + /* + * If the device has not been properly setup, the following will catch + * the problem and should stop the system from crashing. + * 20030610 - hamish@zot.org + */ + if (pci_enable_device(pdev)) { + printk(KERN_ERR PFX "Unable to Enable PCI device\n"); + agp_put_bridge(bridge); + return -ENODEV; + } + + /* + * The following fixes the case where the BIOS has "forgotten" to + * provide an address range for the GART. + * 20030610 - hamish@zot.org + */ + r = &pdev->resource[0]; + if (!r->start && r->end) { + if (pci_assign_resource(pdev, 0)) { + printk(KERN_ERR PFX "could not assign resource 0\n"); + agp_put_bridge(bridge); + return -ENODEV; + } + } + + /* Fill in the mode register */ + if (cap_ptr) { + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, + &bridge->mode); + } + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void agp_efficeon_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static int agp_efficeon_resume(struct device *dev) +{ + printk(KERN_DEBUG PFX "agp_efficeon_resume()\n"); + return efficeon_configure(); +} + +static const struct pci_device_id agp_efficeon_pci_table[] = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_TRANSMETA, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +static DEFINE_SIMPLE_DEV_PM_OPS(agp_efficeon_pm_ops, NULL, agp_efficeon_resume); + +MODULE_DEVICE_TABLE(pci, agp_efficeon_pci_table); + +static struct pci_driver agp_efficeon_pci_driver = { + .name = "agpgart-efficeon", + .id_table = agp_efficeon_pci_table, + .probe = agp_efficeon_probe, + .remove = agp_efficeon_remove, + .driver.pm = &agp_efficeon_pm_ops, +}; + +static int __init agp_efficeon_init(void) +{ + static int agp_initialised=0; + + if (agp_off) + return -EINVAL; + + if (agp_initialised == 1) + return 0; + agp_initialised=1; + + return pci_register_driver(&agp_efficeon_pci_driver); +} + +static void __exit agp_efficeon_cleanup(void) +{ + pci_unregister_driver(&agp_efficeon_pci_driver); +} + +module_init(agp_efficeon_init); +module_exit(agp_efficeon_cleanup); + +MODULE_AUTHOR("Carlos Puchol "); +MODULE_LICENSE("GPL and additional rights"); -- cgit v1.2.3