From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/char/agp/via-agp.c | 579 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 579 insertions(+) create mode 100644 drivers/char/agp/via-agp.c (limited to 'drivers/char/agp/via-agp.c') diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c new file mode 100644 index 000000000..bc5140af2 --- /dev/null +++ b/drivers/char/agp/via-agp.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * VIA AGPGART routines. + */ + +#include +#include +#include +#include +#include +#include "agp.h" + +static const struct pci_device_id agp_via_pci_table[]; + +#define VIA_GARTCTRL 0x80 +#define VIA_APSIZE 0x84 +#define VIA_ATTBASE 0x88 + +#define VIA_AGP3_GARTCTRL 0x90 +#define VIA_AGP3_APSIZE 0x94 +#define VIA_AGP3_ATTBASE 0x98 +#define VIA_AGPSEL 0xfd + +static int via_fetch_size(void) +{ + int i; + u8 temp; + struct aper_size_info_8 *values; + + values = A_SIZE_8(agp_bridge->driver->aperture_sizes); + pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp); + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp); + return 0; +} + + +static int via_configure(void) +{ + struct aper_size_info_8 *current_size; + + current_size = A_SIZE_8(agp_bridge->current_size); + /* aperture size */ + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, + current_size->size_value); + /* address to map to */ + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, + AGP_APERTURE_BAR); + + /* GART control register */ + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f); + + /* attbase - aperture GATT base */ + pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE, + (agp_bridge->gatt_bus_addr & 0xfffff000) | 3); + return 0; +} + + +static void via_cleanup(void) +{ + struct aper_size_info_8 *previous_size; + + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, + previous_size->size_value); + /* Do not disable by writing 0 to VIA_ATTBASE, it screws things up + * during reinitialization. + */ +} + + +static void via_tlbflush(struct agp_memory *mem) +{ + u32 temp; + + pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp); + temp |= (1<<7); + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp); + temp &= ~(1<<7); + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp); +} + + +static const struct aper_size_info_8 via_generic_sizes[9] = +{ + {256, 65536, 6, 0}, + {128, 32768, 5, 128}, + {64, 16384, 4, 192}, + {32, 8192, 3, 224}, + {16, 4096, 2, 240}, + {8, 2048, 1, 248}, + {4, 1024, 0, 252}, + {2, 512, 0, 254}, + {1, 256, 0, 255} +}; + + +static int via_fetch_size_agp3(void) +{ + int i; + u16 temp; + struct aper_size_info_16 *values; + + values = A_SIZE_16(agp_bridge->driver->aperture_sizes); + pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp); + temp &= 0xfff; + + for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + return 0; +} + + +static int via_configure_agp3(void) +{ + u32 temp; + + /* address to map to */ + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, + AGP_APERTURE_BAR); + + /* attbase - aperture GATT base */ + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE, + agp_bridge->gatt_bus_addr & 0xfffff000); + + /* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch + * translation table first. + * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the + * graphics AGP aperture for the AGP3.0 port. + */ + pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7)); + return 0; +} + + +static void via_cleanup_agp3(void) +{ + struct aper_size_info_16 *previous_size; + + previous_size = A_SIZE_16(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value); +} + + +static void via_tlbflush_agp3(struct agp_memory *mem) +{ + u32 temp; + + pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7)); + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp); +} + + +static const struct agp_bridge_driver via_agp3_driver = { + .owner = THIS_MODULE, + .aperture_sizes = agp3_generic_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 10, + .needs_scratch_page = true, + .configure = via_configure_agp3, + .fetch_size = via_fetch_size_agp3, + .cleanup = via_cleanup_agp3, + .tlb_flush = via_tlbflush_agp3, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_alloc_pages = agp_generic_alloc_pages, + .agp_destroy_page = agp_generic_destroy_page, + .agp_destroy_pages = agp_generic_destroy_pages, + .agp_type_to_mask_type = agp_generic_type_to_mask_type, +}; + +static const struct agp_bridge_driver via_driver = { + .owner = THIS_MODULE, + .aperture_sizes = via_generic_sizes, + .size_type = U8_APER_SIZE, + .num_aperture_sizes = 9, + .needs_scratch_page = true, + .configure = via_configure, + .fetch_size = via_fetch_size, + .cleanup = via_cleanup, + .tlb_flush = via_tlbflush, + .mask_memory = agp_generic_mask_memory, + .masks = NULL, + .agp_enable = agp_generic_enable, + .cache_flush = global_cache_flush, + .create_gatt_table = agp_generic_create_gatt_table, + .free_gatt_table = agp_generic_free_gatt_table, + .insert_memory = agp_generic_insert_memory, + .remove_memory = agp_generic_remove_memory, + .alloc_by_type = agp_generic_alloc_by_type, + .free_by_type = agp_generic_free_by_type, + .agp_alloc_page = agp_generic_alloc_page, + .agp_alloc_pages = agp_generic_alloc_pages, + .agp_destroy_page = agp_generic_destroy_page, + .agp_destroy_pages = agp_generic_destroy_pages, + .agp_type_to_mask_type = agp_generic_type_to_mask_type, +}; + +static struct agp_device_ids via_agp_device_ids[] = +{ + { + .device_id = PCI_DEVICE_ID_VIA_82C597_0, + .chipset_name = "Apollo VP3", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_82C598_0, + .chipset_name = "Apollo MVP3", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_8501_0, + .chipset_name = "Apollo MVP4", + }, + + /* VT8601 */ + { + .device_id = PCI_DEVICE_ID_VIA_8601_0, + .chipset_name = "Apollo ProMedia/PLE133Ta", + }, + + /* VT82C693A / VT28C694T */ + { + .device_id = PCI_DEVICE_ID_VIA_82C691_0, + .chipset_name = "Apollo Pro 133", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_8371_0, + .chipset_name = "KX133", + }, + + /* VT8633 */ + { + .device_id = PCI_DEVICE_ID_VIA_8633_0, + .chipset_name = "Pro 266", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_XN266, + .chipset_name = "Apollo Pro266", + }, + + /* VT8361 */ + { + .device_id = PCI_DEVICE_ID_VIA_8361, + .chipset_name = "KLE133", + }, + + /* VT8365 / VT8362 */ + { + .device_id = PCI_DEVICE_ID_VIA_8363_0, + .chipset_name = "Twister-K/KT133x/KM133", + }, + + /* VT8753A */ + { + .device_id = PCI_DEVICE_ID_VIA_8753_0, + .chipset_name = "P4X266", + }, + + /* VT8366 */ + { + .device_id = PCI_DEVICE_ID_VIA_8367_0, + .chipset_name = "KT266/KY266x/KT333", + }, + + /* VT8633 (for CuMine/ Celeron) */ + { + .device_id = PCI_DEVICE_ID_VIA_8653_0, + .chipset_name = "Pro266T", + }, + + /* KM266 / PM266 */ + { + .device_id = PCI_DEVICE_ID_VIA_XM266, + .chipset_name = "PM266/KM266", + }, + + /* CLE266 */ + { + .device_id = PCI_DEVICE_ID_VIA_862X_0, + .chipset_name = "CLE266", + }, + + { + .device_id = PCI_DEVICE_ID_VIA_8377_0, + .chipset_name = "KT400/KT400A/KT600", + }, + + /* VT8604 / VT8605 / VT8603 + * (Apollo Pro133A chipset with S3 Savage4) */ + { + .device_id = PCI_DEVICE_ID_VIA_8605_0, + .chipset_name = "ProSavage PM133/PL133/PN133" + }, + + /* P4M266x/P4N266 */ + { + .device_id = PCI_DEVICE_ID_VIA_8703_51_0, + .chipset_name = "P4M266x/P4N266", + }, + + /* VT8754 */ + { + .device_id = PCI_DEVICE_ID_VIA_8754C_0, + .chipset_name = "PT800", + }, + + /* P4X600 */ + { + .device_id = PCI_DEVICE_ID_VIA_8763_0, + .chipset_name = "P4X600" + }, + + /* KM400 */ + { + .device_id = PCI_DEVICE_ID_VIA_8378_0, + .chipset_name = "KM400/KM400A", + }, + + /* PT880 */ + { + .device_id = PCI_DEVICE_ID_VIA_PT880, + .chipset_name = "PT880", + }, + + /* PT880 Ultra */ + { + .device_id = PCI_DEVICE_ID_VIA_PT880ULTRA, + .chipset_name = "PT880 Ultra", + }, + + /* PT890 */ + { + .device_id = PCI_DEVICE_ID_VIA_8783_0, + .chipset_name = "PT890", + }, + + /* PM800/PN800/PM880/PN880 */ + { + .device_id = PCI_DEVICE_ID_VIA_PX8X0_0, + .chipset_name = "PM800/PN800/PM880/PN880", + }, + /* KT880 */ + { + .device_id = PCI_DEVICE_ID_VIA_3269_0, + .chipset_name = "KT880", + }, + /* KTxxx/Px8xx */ + { + .device_id = PCI_DEVICE_ID_VIA_83_87XX_1, + .chipset_name = "VT83xx/VT87xx/KTxxx/Px8xx", + }, + /* P4M800 */ + { + .device_id = PCI_DEVICE_ID_VIA_3296_0, + .chipset_name = "P4M800", + }, + /* P4M800CE */ + { + .device_id = PCI_DEVICE_ID_VIA_P4M800CE, + .chipset_name = "VT3314", + }, + /* VT3324 / CX700 */ + { + .device_id = PCI_DEVICE_ID_VIA_VT3324, + .chipset_name = "CX700", + }, + /* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique + * architecture, the AGP resource and behavior are different from + * the traditional AGP which resides only in chipset. AGP is used + * by 3D driver which wasn't available for the VT3336 and VT3364 + * generation until now. Unfortunately, by testing, VT3364 works + * but VT3336 doesn't. - explanation from via, just leave this as + * as a placeholder to avoid future patches adding it back in. + */ +#if 0 + { + .device_id = PCI_DEVICE_ID_VIA_VT3336, + .chipset_name = "VT3336", + }, +#endif + /* P4M890 */ + { + .device_id = PCI_DEVICE_ID_VIA_P4M890, + .chipset_name = "P4M890", + }, + /* P4M900 */ + { + .device_id = PCI_DEVICE_ID_VIA_VT3364, + .chipset_name = "P4M900", + }, + { }, /* dummy final entry, always present */ +}; + + +/* + * VIA's AGP3 chipsets do magick to put the AGP bridge compliant + * with the same standards version as the graphics card. + */ +static void check_via_agp3 (struct agp_bridge_data *bridge) +{ + u8 reg; + + pci_read_config_byte(bridge->dev, VIA_AGPSEL, ®); + /* Check AGP 2.0 compatibility mode. */ + if ((reg & (1<<1))==0) + bridge->driver = &via_agp3_driver; +} + + +static int agp_via_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + struct agp_device_ids *devs = via_agp_device_ids; + struct agp_bridge_data *bridge; + int j = 0; + u8 cap_ptr; + + cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); + if (!cap_ptr) + return -ENODEV; + + j = ent - agp_via_pci_table; + printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name); + + bridge = agp_alloc_bridge(); + if (!bridge) + return -ENOMEM; + + bridge->dev = pdev; + bridge->capndx = cap_ptr; + bridge->driver = &via_driver; + + /* + * Garg, there are KT400s with KT266 IDs. + */ + if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) { + /* Is there a KT400 subsystem ? */ + if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) { + printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n"); + check_via_agp3(bridge); + } + } + + /* If this is an AGP3 bridge, check which mode its in and adjust. */ + get_agp_version(bridge); + if (bridge->major_version >= 3) + check_via_agp3(bridge); + + /* Fill in the mode register */ + pci_read_config_dword(pdev, + bridge->capndx+PCI_AGP_STATUS, &bridge->mode); + + pci_set_drvdata(pdev, bridge); + return agp_add_bridge(bridge); +} + +static void agp_via_remove(struct pci_dev *pdev) +{ + struct agp_bridge_data *bridge = pci_get_drvdata(pdev); + + agp_remove_bridge(bridge); + agp_put_bridge(bridge); +} + +static int agp_via_resume(struct device *dev) +{ + struct agp_bridge_data *bridge = dev_get_drvdata(dev); + + if (bridge->driver == &via_agp3_driver) + return via_configure_agp3(); + else if (bridge->driver == &via_driver) + return via_configure(); + + return 0; +} + +/* must be the same order as name table above */ +static const struct pci_device_id agp_via_pci_table[] = { +#define ID(x) \ + { \ + .class = (PCI_CLASS_BRIDGE_HOST << 8), \ + .class_mask = ~0, \ + .vendor = PCI_VENDOR_ID_VIA, \ + .device = x, \ + .subvendor = PCI_ANY_ID, \ + .subdevice = PCI_ANY_ID, \ + } + ID(PCI_DEVICE_ID_VIA_82C597_0), + ID(PCI_DEVICE_ID_VIA_82C598_0), + ID(PCI_DEVICE_ID_VIA_8501_0), + ID(PCI_DEVICE_ID_VIA_8601_0), + ID(PCI_DEVICE_ID_VIA_82C691_0), + ID(PCI_DEVICE_ID_VIA_8371_0), + ID(PCI_DEVICE_ID_VIA_8633_0), + ID(PCI_DEVICE_ID_VIA_XN266), + ID(PCI_DEVICE_ID_VIA_8361), + ID(PCI_DEVICE_ID_VIA_8363_0), + ID(PCI_DEVICE_ID_VIA_8753_0), + ID(PCI_DEVICE_ID_VIA_8367_0), + ID(PCI_DEVICE_ID_VIA_8653_0), + ID(PCI_DEVICE_ID_VIA_XM266), + ID(PCI_DEVICE_ID_VIA_862X_0), + ID(PCI_DEVICE_ID_VIA_8377_0), + ID(PCI_DEVICE_ID_VIA_8605_0), + ID(PCI_DEVICE_ID_VIA_8703_51_0), + ID(PCI_DEVICE_ID_VIA_8754C_0), + ID(PCI_DEVICE_ID_VIA_8763_0), + ID(PCI_DEVICE_ID_VIA_8378_0), + ID(PCI_DEVICE_ID_VIA_PT880), + ID(PCI_DEVICE_ID_VIA_PT880ULTRA), + ID(PCI_DEVICE_ID_VIA_8783_0), + ID(PCI_DEVICE_ID_VIA_PX8X0_0), + ID(PCI_DEVICE_ID_VIA_3269_0), + ID(PCI_DEVICE_ID_VIA_83_87XX_1), + ID(PCI_DEVICE_ID_VIA_3296_0), + ID(PCI_DEVICE_ID_VIA_P4M800CE), + ID(PCI_DEVICE_ID_VIA_VT3324), + ID(PCI_DEVICE_ID_VIA_P4M890), + ID(PCI_DEVICE_ID_VIA_VT3364), + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_via_pci_table); + +static DEFINE_SIMPLE_DEV_PM_OPS(agp_via_pm_ops, NULL, agp_via_resume); + +static struct pci_driver agp_via_pci_driver = { + .name = "agpgart-via", + .id_table = agp_via_pci_table, + .probe = agp_via_probe, + .remove = agp_via_remove, + .driver.pm = &agp_via_pm_ops, +}; + + +static int __init agp_via_init(void) +{ + if (agp_off) + return -EINVAL; + return pci_register_driver(&agp_via_pci_driver); +} + +static void __exit agp_via_cleanup(void) +{ + pci_unregister_driver(&agp_via_pci_driver); +} + +module_init(agp_via_init); +module_exit(agp_via_cleanup); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Dave Jones"); -- cgit v1.2.3