From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/gpu/drm/amd/include/arct_ip_offset.h | 1650 ++++++++++++++++++++++++++ 1 file changed, 1650 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/arct_ip_offset.h (limited to 'drivers/gpu/drm/amd/include/arct_ip_offset.h') diff --git a/drivers/gpu/drm/amd/include/arct_ip_offset.h b/drivers/gpu/drm/amd/include/arct_ip_offset.h new file mode 100644 index 000000000..af1c46991 --- /dev/null +++ b/drivers/gpu/drm/amd/include/arct_ip_offset.h @@ -0,0 +1,1650 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _arct_ip_offset_HEADER +#define _arct_ip_offset_HEADER + +#define MAX_INSTANCE 8 +#define MAX_SEGMENT 6 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +} __maybe_unused; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +} __maybe_unused; + + +static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } }, + { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } }, + { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } }, + { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } }, + { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } }, + { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } }, + { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } }, + { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } }, + { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } }, + { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } }, + { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } }, + { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } }, + { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } }, + { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } }; +static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } }, + { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; + + + +#define ATHUB_BASE__INST0_SEG0 0x00000C20 +#define ATHUB_BASE__INST0_SEG1 0x00012460 +#define ATHUB_BASE__INST0_SEG2 0x00408C00 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 +#define ATHUB_BASE__INST0_SEG5 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 +#define ATHUB_BASE__INST1_SEG5 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 +#define ATHUB_BASE__INST2_SEG5 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 +#define ATHUB_BASE__INST3_SEG5 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 +#define ATHUB_BASE__INST4_SEG5 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 +#define ATHUB_BASE__INST5_SEG5 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 +#define ATHUB_BASE__INST6_SEG5 0 + +#define ATHUB_BASE__INST7_SEG0 0 +#define ATHUB_BASE__INST7_SEG1 0 +#define ATHUB_BASE__INST7_SEG2 0 +#define ATHUB_BASE__INST7_SEG3 0 +#define ATHUB_BASE__INST7_SEG4 0 +#define ATHUB_BASE__INST7_SEG5 0 + +#define CLK_BASE__INST0_SEG0 0x000120C0 +#define CLK_BASE__INST0_SEG1 0x00016C00 +#define CLK_BASE__INST0_SEG2 0x00401800 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 +#define CLK_BASE__INST0_SEG5 0 + +#define CLK_BASE__INST1_SEG0 0x000120E0 +#define CLK_BASE__INST1_SEG1 0x00016E00 +#define CLK_BASE__INST1_SEG2 0x00401C00 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 +#define CLK_BASE__INST1_SEG5 0 + +#define CLK_BASE__INST2_SEG0 0x00012100 +#define CLK_BASE__INST2_SEG1 0x00017000 +#define CLK_BASE__INST2_SEG2 0x00402000 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 +#define CLK_BASE__INST2_SEG5 0 + +#define CLK_BASE__INST3_SEG0 0x00012120 +#define CLK_BASE__INST3_SEG1 0x00017200 +#define CLK_BASE__INST3_SEG2 0x00402400 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 +#define CLK_BASE__INST3_SEG5 0 + +#define CLK_BASE__INST4_SEG0 0x000136C0 +#define CLK_BASE__INST4_SEG1 0x0001B000 +#define CLK_BASE__INST4_SEG2 0x0042D800 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 +#define CLK_BASE__INST4_SEG5 0 + +#define CLK_BASE__INST5_SEG0 0x00013720 +#define CLK_BASE__INST5_SEG1 0x0001B200 +#define CLK_BASE__INST5_SEG2 0x0042E400 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 +#define CLK_BASE__INST5_SEG5 0 + +#define CLK_BASE__INST6_SEG0 0x000125E0 +#define CLK_BASE__INST6_SEG1 0x00017E00 +#define CLK_BASE__INST6_SEG2 0x0040BC00 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 +#define CLK_BASE__INST6_SEG5 0 + +#define CLK_BASE__INST7_SEG0 0 +#define CLK_BASE__INST7_SEG1 0 +#define CLK_BASE__INST7_SEG2 0 +#define CLK_BASE__INST7_SEG3 0 +#define CLK_BASE__INST7_SEG4 0 +#define CLK_BASE__INST7_SEG5 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x000125C0 +#define DF_BASE__INST0_SEG2 0x0040B800 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 +#define DF_BASE__INST0_SEG5 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 +#define DF_BASE__INST1_SEG5 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 +#define DF_BASE__INST2_SEG5 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 +#define DF_BASE__INST3_SEG5 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 +#define DF_BASE__INST4_SEG5 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 +#define DF_BASE__INST5_SEG5 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 +#define DF_BASE__INST6_SEG5 0 + +#define DF_BASE__INST7_SEG0 0 +#define DF_BASE__INST7_SEG1 0 +#define DF_BASE__INST7_SEG2 0 +#define DF_BASE__INST7_SEG3 0 +#define DF_BASE__INST7_SEG4 0 +#define DF_BASE__INST7_SEG5 0 + +#define FUSE_BASE__INST0_SEG0 0x000120A0 +#define FUSE_BASE__INST0_SEG1 0x00017400 +#define FUSE_BASE__INST0_SEG2 0x00401400 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 +#define FUSE_BASE__INST0_SEG5 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 +#define FUSE_BASE__INST1_SEG5 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 +#define FUSE_BASE__INST2_SEG5 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 +#define FUSE_BASE__INST3_SEG5 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 +#define FUSE_BASE__INST4_SEG5 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 +#define FUSE_BASE__INST5_SEG5 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 +#define FUSE_BASE__INST6_SEG5 0 + +#define FUSE_BASE__INST7_SEG0 0 +#define FUSE_BASE__INST7_SEG1 0 +#define FUSE_BASE__INST7_SEG2 0 +#define FUSE_BASE__INST7_SEG3 0 +#define FUSE_BASE__INST7_SEG4 0 +#define FUSE_BASE__INST7_SEG5 0 + +#define GC_BASE__INST0_SEG0 0x00002000 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x00012160 +#define GC_BASE__INST0_SEG3 0x00402C00 +#define GC_BASE__INST0_SEG4 0 +#define GC_BASE__INST0_SEG5 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 +#define GC_BASE__INST1_SEG5 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 +#define GC_BASE__INST2_SEG5 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 +#define GC_BASE__INST3_SEG5 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 +#define GC_BASE__INST4_SEG5 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 +#define GC_BASE__INST5_SEG5 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 +#define GC_BASE__INST6_SEG5 0 + +#define GC_BASE__INST7_SEG0 0 +#define GC_BASE__INST7_SEG1 0 +#define GC_BASE__INST7_SEG2 0 +#define GC_BASE__INST7_SEG3 0 +#define GC_BASE__INST7_SEG4 0 +#define GC_BASE__INST7_SEG5 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x00012520 +#define HDP_BASE__INST0_SEG2 0x0040A400 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 +#define HDP_BASE__INST0_SEG5 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 +#define HDP_BASE__INST1_SEG5 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 +#define HDP_BASE__INST2_SEG5 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 +#define HDP_BASE__INST3_SEG5 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 +#define HDP_BASE__INST4_SEG5 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 +#define HDP_BASE__INST5_SEG5 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 +#define HDP_BASE__INST6_SEG5 0 + +#define HDP_BASE__INST7_SEG0 0 +#define HDP_BASE__INST7_SEG1 0 +#define HDP_BASE__INST7_SEG2 0 +#define HDP_BASE__INST7_SEG3 0 +#define HDP_BASE__INST7_SEG4 0 +#define HDP_BASE__INST7_SEG5 0 + +#define MMHUB_BASE__INST0_SEG0 0x00012440 +#define MMHUB_BASE__INST0_SEG1 0x0001A000 +#define MMHUB_BASE__INST0_SEG2 0x00408800 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 +#define MMHUB_BASE__INST0_SEG5 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 +#define MMHUB_BASE__INST1_SEG5 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 +#define MMHUB_BASE__INST2_SEG5 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 +#define MMHUB_BASE__INST3_SEG5 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 +#define MMHUB_BASE__INST4_SEG5 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 +#define MMHUB_BASE__INST5_SEG5 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 +#define MMHUB_BASE__INST6_SEG5 0 + +#define MMHUB_BASE__INST7_SEG0 0 +#define MMHUB_BASE__INST7_SEG1 0 +#define MMHUB_BASE__INST7_SEG2 0 +#define MMHUB_BASE__INST7_SEG3 0 +#define MMHUB_BASE__INST7_SEG4 0 +#define MMHUB_BASE__INST7_SEG5 0 + +#define MP0_BASE__INST0_SEG0 0x00013FE0 +#define MP0_BASE__INST0_SEG1 0x00016000 +#define MP0_BASE__INST0_SEG2 0x0043FC00 +#define MP0_BASE__INST0_SEG3 0x00DC0000 +#define MP0_BASE__INST0_SEG4 0x00E00000 +#define MP0_BASE__INST0_SEG5 0x00E40000 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 +#define MP0_BASE__INST1_SEG5 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 +#define MP0_BASE__INST2_SEG5 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 +#define MP0_BASE__INST3_SEG5 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 +#define MP0_BASE__INST4_SEG5 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 +#define MP0_BASE__INST5_SEG5 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 +#define MP0_BASE__INST6_SEG5 0 + +#define MP0_BASE__INST7_SEG0 0 +#define MP0_BASE__INST7_SEG1 0 +#define MP0_BASE__INST7_SEG2 0 +#define MP0_BASE__INST7_SEG3 0 +#define MP0_BASE__INST7_SEG4 0 +#define MP0_BASE__INST7_SEG5 0 + +#define MP1_BASE__INST0_SEG0 0x00012020 +#define MP1_BASE__INST0_SEG1 0x00016200 +#define MP1_BASE__INST0_SEG2 0x00400400 +#define MP1_BASE__INST0_SEG3 0x00E80000 +#define MP1_BASE__INST0_SEG4 0x00EC0000 +#define MP1_BASE__INST0_SEG5 0x00F00000 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 +#define MP1_BASE__INST1_SEG5 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 +#define MP1_BASE__INST2_SEG5 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 +#define MP1_BASE__INST3_SEG5 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 +#define MP1_BASE__INST4_SEG5 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 +#define MP1_BASE__INST5_SEG5 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 +#define MP1_BASE__INST6_SEG5 0 + +#define MP1_BASE__INST7_SEG0 0 +#define MP1_BASE__INST7_SEG1 0 +#define MP1_BASE__INST7_SEG2 0 +#define MP1_BASE__INST7_SEG3 0 +#define MP1_BASE__INST7_SEG4 0 +#define MP1_BASE__INST7_SEG5 0 + +#define NBIF0_BASE__INST0_SEG0 0x00000000 +#define NBIF0_BASE__INST0_SEG1 0x00000014 +#define NBIF0_BASE__INST0_SEG2 0x00000D20 +#define NBIF0_BASE__INST0_SEG3 0x00010400 +#define NBIF0_BASE__INST0_SEG4 0x00012D80 +#define NBIF0_BASE__INST0_SEG5 0x0041B000 + +#define NBIF0_BASE__INST1_SEG0 0 +#define NBIF0_BASE__INST1_SEG1 0 +#define NBIF0_BASE__INST1_SEG2 0 +#define NBIF0_BASE__INST1_SEG3 0 +#define NBIF0_BASE__INST1_SEG4 0 +#define NBIF0_BASE__INST1_SEG5 0 + +#define NBIF0_BASE__INST2_SEG0 0 +#define NBIF0_BASE__INST2_SEG1 0 +#define NBIF0_BASE__INST2_SEG2 0 +#define NBIF0_BASE__INST2_SEG3 0 +#define NBIF0_BASE__INST2_SEG4 0 +#define NBIF0_BASE__INST2_SEG5 0 + +#define NBIF0_BASE__INST3_SEG0 0 +#define NBIF0_BASE__INST3_SEG1 0 +#define NBIF0_BASE__INST3_SEG2 0 +#define NBIF0_BASE__INST3_SEG3 0 +#define NBIF0_BASE__INST3_SEG4 0 +#define NBIF0_BASE__INST3_SEG5 0 + +#define NBIF0_BASE__INST4_SEG0 0 +#define NBIF0_BASE__INST4_SEG1 0 +#define NBIF0_BASE__INST4_SEG2 0 +#define NBIF0_BASE__INST4_SEG3 0 +#define NBIF0_BASE__INST4_SEG4 0 +#define NBIF0_BASE__INST4_SEG5 0 + +#define NBIF0_BASE__INST5_SEG0 0 +#define NBIF0_BASE__INST5_SEG1 0 +#define NBIF0_BASE__INST5_SEG2 0 +#define NBIF0_BASE__INST5_SEG3 0 +#define NBIF0_BASE__INST5_SEG4 0 +#define NBIF0_BASE__INST5_SEG5 0 + +#define NBIF0_BASE__INST6_SEG0 0 +#define NBIF0_BASE__INST6_SEG1 0 +#define NBIF0_BASE__INST6_SEG2 0 +#define NBIF0_BASE__INST6_SEG3 0 +#define NBIF0_BASE__INST6_SEG4 0 +#define NBIF0_BASE__INST6_SEG5 0 + +#define NBIF0_BASE__INST7_SEG0 0 +#define NBIF0_BASE__INST7_SEG1 0 +#define NBIF0_BASE__INST7_SEG2 0 +#define NBIF0_BASE__INST7_SEG3 0 +#define NBIF0_BASE__INST7_SEG4 0 +#define NBIF0_BASE__INST7_SEG5 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x00012500 +#define OSSSYS_BASE__INST0_SEG2 0x0040A000 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 +#define OSSSYS_BASE__INST0_SEG5 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 +#define OSSSYS_BASE__INST1_SEG5 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 +#define OSSSYS_BASE__INST2_SEG5 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 +#define OSSSYS_BASE__INST3_SEG5 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 +#define OSSSYS_BASE__INST4_SEG5 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 +#define OSSSYS_BASE__INST5_SEG5 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 +#define OSSSYS_BASE__INST6_SEG5 0 + +#define OSSSYS_BASE__INST7_SEG0 0 +#define OSSSYS_BASE__INST7_SEG1 0 +#define OSSSYS_BASE__INST7_SEG2 0 +#define OSSSYS_BASE__INST7_SEG3 0 +#define OSSSYS_BASE__INST7_SEG4 0 +#define OSSSYS_BASE__INST7_SEG5 0 + +#define PCIE0_BASE__INST0_SEG0 0x000128C0 +#define PCIE0_BASE__INST0_SEG1 0x00411800 +#define PCIE0_BASE__INST0_SEG2 0x04440000 +#define PCIE0_BASE__INST0_SEG3 0 +#define PCIE0_BASE__INST0_SEG4 0 +#define PCIE0_BASE__INST0_SEG5 0 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 +#define PCIE0_BASE__INST1_SEG5 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 +#define PCIE0_BASE__INST2_SEG5 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 +#define PCIE0_BASE__INST3_SEG5 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 +#define PCIE0_BASE__INST4_SEG5 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 +#define PCIE0_BASE__INST5_SEG5 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 +#define PCIE0_BASE__INST6_SEG5 0 + +#define PCIE0_BASE__INST7_SEG0 0 +#define PCIE0_BASE__INST7_SEG1 0 +#define PCIE0_BASE__INST7_SEG2 0 +#define PCIE0_BASE__INST7_SEG3 0 +#define PCIE0_BASE__INST7_SEG4 0 +#define PCIE0_BASE__INST7_SEG5 0 + +#define SDMA0_BASE__INST0_SEG0 0x00001260 +#define SDMA0_BASE__INST0_SEG1 0x00012540 +#define SDMA0_BASE__INST0_SEG2 0x0040A800 +#define SDMA0_BASE__INST0_SEG3 0 +#define SDMA0_BASE__INST0_SEG4 0 +#define SDMA0_BASE__INST0_SEG5 0 + +#define SDMA0_BASE__INST1_SEG0 0 +#define SDMA0_BASE__INST1_SEG1 0 +#define SDMA0_BASE__INST1_SEG2 0 +#define SDMA0_BASE__INST1_SEG3 0 +#define SDMA0_BASE__INST1_SEG4 0 +#define SDMA0_BASE__INST1_SEG5 0 + +#define SDMA0_BASE__INST2_SEG0 0 +#define SDMA0_BASE__INST2_SEG1 0 +#define SDMA0_BASE__INST2_SEG2 0 +#define SDMA0_BASE__INST2_SEG3 0 +#define SDMA0_BASE__INST2_SEG4 0 +#define SDMA0_BASE__INST2_SEG5 0 + +#define SDMA0_BASE__INST3_SEG0 0 +#define SDMA0_BASE__INST3_SEG1 0 +#define SDMA0_BASE__INST3_SEG2 0 +#define SDMA0_BASE__INST3_SEG3 0 +#define SDMA0_BASE__INST3_SEG4 0 +#define SDMA0_BASE__INST3_SEG5 0 + +#define SDMA0_BASE__INST4_SEG0 0 +#define SDMA0_BASE__INST4_SEG1 0 +#define SDMA0_BASE__INST4_SEG2 0 +#define SDMA0_BASE__INST4_SEG3 0 +#define SDMA0_BASE__INST4_SEG4 0 +#define SDMA0_BASE__INST4_SEG5 0 + +#define SDMA0_BASE__INST5_SEG0 0 +#define SDMA0_BASE__INST5_SEG1 0 +#define SDMA0_BASE__INST5_SEG2 0 +#define SDMA0_BASE__INST5_SEG3 0 +#define SDMA0_BASE__INST5_SEG4 0 +#define SDMA0_BASE__INST5_SEG5 0 + +#define SDMA0_BASE__INST6_SEG0 0 +#define SDMA0_BASE__INST6_SEG1 0 +#define SDMA0_BASE__INST6_SEG2 0 +#define SDMA0_BASE__INST6_SEG3 0 +#define SDMA0_BASE__INST6_SEG4 0 +#define SDMA0_BASE__INST6_SEG5 0 + +#define SDMA1_BASE__INST0_SEG0 0x00001860 +#define SDMA1_BASE__INST0_SEG1 0x00012560 +#define SDMA1_BASE__INST0_SEG2 0x0040AC00 +#define SDMA1_BASE__INST0_SEG3 0 +#define SDMA1_BASE__INST0_SEG4 0 +#define SDMA1_BASE__INST0_SEG5 0 + +#define SDMA1_BASE__INST1_SEG0 0 +#define SDMA1_BASE__INST1_SEG1 0 +#define SDMA1_BASE__INST1_SEG2 0 +#define SDMA1_BASE__INST1_SEG3 0 +#define SDMA1_BASE__INST1_SEG4 0 +#define SDMA1_BASE__INST1_SEG5 0 + +#define SDMA1_BASE__INST2_SEG0 0 +#define SDMA1_BASE__INST2_SEG1 0 +#define SDMA1_BASE__INST2_SEG2 0 +#define SDMA1_BASE__INST2_SEG3 0 +#define SDMA1_BASE__INST2_SEG4 0 +#define SDMA1_BASE__INST2_SEG5 0 + +#define SDMA1_BASE__INST3_SEG0 0 +#define SDMA1_BASE__INST3_SEG1 0 +#define SDMA1_BASE__INST3_SEG2 0 +#define SDMA1_BASE__INST3_SEG3 0 +#define SDMA1_BASE__INST3_SEG4 0 +#define SDMA1_BASE__INST3_SEG5 0 + +#define SDMA1_BASE__INST4_SEG0 0 +#define SDMA1_BASE__INST4_SEG1 0 +#define SDMA1_BASE__INST4_SEG2 0 +#define SDMA1_BASE__INST4_SEG3 0 +#define SDMA1_BASE__INST4_SEG4 0 +#define SDMA1_BASE__INST4_SEG5 0 + +#define SDMA1_BASE__INST5_SEG0 0 +#define SDMA1_BASE__INST5_SEG1 0 +#define SDMA1_BASE__INST5_SEG2 0 +#define SDMA1_BASE__INST5_SEG3 0 +#define SDMA1_BASE__INST5_SEG4 0 +#define SDMA1_BASE__INST5_SEG5 0 + + +#define SDMA1_BASE__INST6_SEG0 0 +#define SDMA1_BASE__INST6_SEG1 0 +#define SDMA1_BASE__INST6_SEG2 0 +#define SDMA1_BASE__INST6_SEG3 0 +#define SDMA1_BASE__INST6_SEG4 0 +#define SDMA1_BASE__INST6_SEG5 0 + + +#define SDMA2_BASE__INST0_SEG0 0x00013760 +#define SDMA2_BASE__INST0_SEG1 0x0001E000 +#define SDMA2_BASE__INST0_SEG2 0x0042EC00 +#define SDMA2_BASE__INST0_SEG3 0 +#define SDMA2_BASE__INST0_SEG4 0 +#define SDMA2_BASE__INST0_SEG5 0 + + +#define SDMA2_BASE__INST1_SEG0 0 +#define SDMA2_BASE__INST1_SEG1 0 +#define SDMA2_BASE__INST1_SEG2 0 +#define SDMA2_BASE__INST1_SEG3 0 +#define SDMA2_BASE__INST1_SEG4 0 +#define SDMA2_BASE__INST1_SEG5 0 + +#define SDMA2_BASE__INST2_SEG0 0 +#define SDMA2_BASE__INST2_SEG1 0 +#define SDMA2_BASE__INST2_SEG2 0 +#define SDMA2_BASE__INST2_SEG3 0 +#define SDMA2_BASE__INST2_SEG4 0 +#define SDMA2_BASE__INST2_SEG5 0 + +#define SDMA2_BASE__INST3_SEG0 0 +#define SDMA2_BASE__INST3_SEG1 0 +#define SDMA2_BASE__INST3_SEG2 0 +#define SDMA2_BASE__INST3_SEG3 0 +#define SDMA2_BASE__INST3_SEG4 0 +#define SDMA2_BASE__INST3_SEG5 0 + +#define SDMA2_BASE__INST4_SEG0 0 +#define SDMA2_BASE__INST4_SEG1 0 +#define SDMA2_BASE__INST4_SEG2 0 +#define SDMA2_BASE__INST4_SEG3 0 +#define SDMA2_BASE__INST4_SEG4 0 +#define SDMA2_BASE__INST4_SEG5 0 + +#define SDMA2_BASE__INST5_SEG0 0 +#define SDMA2_BASE__INST5_SEG1 0 +#define SDMA2_BASE__INST5_SEG2 0 +#define SDMA2_BASE__INST5_SEG3 0 +#define SDMA2_BASE__INST5_SEG4 0 +#define SDMA2_BASE__INST5_SEG5 0 + +#define SDMA2_BASE__INST6_SEG0 0 +#define SDMA2_BASE__INST6_SEG1 0 +#define SDMA2_BASE__INST6_SEG2 0 +#define SDMA2_BASE__INST6_SEG3 0 +#define SDMA2_BASE__INST6_SEG4 0 +#define SDMA2_BASE__INST6_SEG5 0 + +#define SDMA3_BASE__INST0_SEG0 0x00013780 +#define SDMA3_BASE__INST0_SEG1 0x0001E400 +#define SDMA3_BASE__INST0_SEG2 0x0042F000 +#define SDMA3_BASE__INST0_SEG3 0 +#define SDMA3_BASE__INST0_SEG4 0 +#define SDMA3_BASE__INST0_SEG5 0 + +#define SDMA3_BASE__INST1_SEG0 0 +#define SDMA3_BASE__INST1_SEG1 0 +#define SDMA3_BASE__INST1_SEG2 0 +#define SDMA3_BASE__INST1_SEG3 0 +#define SDMA3_BASE__INST1_SEG4 0 +#define SDMA3_BASE__INST1_SEG5 0 + +#define SDMA3_BASE__INST2_SEG0 0 +#define SDMA3_BASE__INST2_SEG1 0 +#define SDMA3_BASE__INST2_SEG2 0 +#define SDMA3_BASE__INST2_SEG3 0 +#define SDMA3_BASE__INST2_SEG4 0 +#define SDMA3_BASE__INST2_SEG5 0 + +#define SDMA3_BASE__INST3_SEG0 0 +#define SDMA3_BASE__INST3_SEG1 0 +#define SDMA3_BASE__INST3_SEG2 0 +#define SDMA3_BASE__INST3_SEG3 0 +#define SDMA3_BASE__INST3_SEG4 0 +#define SDMA3_BASE__INST3_SEG5 0 + +#define SDMA3_BASE__INST4_SEG0 0 +#define SDMA3_BASE__INST4_SEG1 0 +#define SDMA3_BASE__INST4_SEG2 0 +#define SDMA3_BASE__INST4_SEG3 0 +#define SDMA3_BASE__INST4_SEG4 0 +#define SDMA3_BASE__INST4_SEG5 0 + +#define SDMA3_BASE__INST5_SEG0 0 +#define SDMA3_BASE__INST5_SEG1 0 +#define SDMA3_BASE__INST5_SEG2 0 +#define SDMA3_BASE__INST5_SEG3 0 +#define SDMA3_BASE__INST5_SEG4 0 +#define SDMA3_BASE__INST5_SEG5 0 + +#define SDMA3_BASE__INST6_SEG0 0 +#define SDMA3_BASE__INST6_SEG1 0 +#define SDMA3_BASE__INST6_SEG2 0 +#define SDMA3_BASE__INST6_SEG3 0 +#define SDMA3_BASE__INST6_SEG4 0 +#define SDMA3_BASE__INST6_SEG5 0 + +#define SDMA4_BASE__INST0_SEG0 0x000137A0 +#define SDMA4_BASE__INST0_SEG1 0x0001E800 +#define SDMA4_BASE__INST0_SEG2 0x0042F400 +#define SDMA4_BASE__INST0_SEG3 0 +#define SDMA4_BASE__INST0_SEG4 0 +#define SDMA4_BASE__INST0_SEG5 0 + +#define SDMA4_BASE__INST1_SEG0 0 +#define SDMA4_BASE__INST1_SEG1 0 +#define SDMA4_BASE__INST1_SEG2 0 +#define SDMA4_BASE__INST1_SEG3 0 +#define SDMA4_BASE__INST1_SEG4 0 +#define SDMA4_BASE__INST1_SEG5 0 + +#define SDMA4_BASE__INST2_SEG0 0 +#define SDMA4_BASE__INST2_SEG1 0 +#define SDMA4_BASE__INST2_SEG2 0 +#define SDMA4_BASE__INST2_SEG3 0 +#define SDMA4_BASE__INST2_SEG4 0 +#define SDMA4_BASE__INST2_SEG5 0 + +#define SDMA4_BASE__INST3_SEG0 0 +#define SDMA4_BASE__INST3_SEG1 0 +#define SDMA4_BASE__INST3_SEG2 0 +#define SDMA4_BASE__INST3_SEG3 0 +#define SDMA4_BASE__INST3_SEG4 0 +#define SDMA4_BASE__INST3_SEG5 0 + +#define SDMA4_BASE__INST4_SEG0 0 +#define SDMA4_BASE__INST4_SEG1 0 +#define SDMA4_BASE__INST4_SEG2 0 +#define SDMA4_BASE__INST4_SEG3 0 +#define SDMA4_BASE__INST4_SEG4 0 +#define SDMA4_BASE__INST4_SEG5 0 + +#define SDMA4_BASE__INST5_SEG0 0 +#define SDMA4_BASE__INST5_SEG1 0 +#define SDMA4_BASE__INST5_SEG2 0 +#define SDMA4_BASE__INST5_SEG3 0 +#define SDMA4_BASE__INST5_SEG4 0 +#define SDMA4_BASE__INST5_SEG5 0 + +#define SDMA4_BASE__INST6_SEG0 0 +#define SDMA4_BASE__INST6_SEG1 0 +#define SDMA4_BASE__INST6_SEG2 0 +#define SDMA4_BASE__INST6_SEG3 0 +#define SDMA4_BASE__INST6_SEG4 0 +#define SDMA4_BASE__INST6_SEG5 0 + +#define SDMA5_BASE__INST0_SEG0 0x000137C0 +#define SDMA5_BASE__INST0_SEG1 0x0001EC00 +#define SDMA5_BASE__INST0_SEG2 0x0042F800 +#define SDMA5_BASE__INST0_SEG3 0 +#define SDMA5_BASE__INST0_SEG4 0 +#define SDMA5_BASE__INST0_SEG5 0 + +#define SDMA5_BASE__INST1_SEG0 0 +#define SDMA5_BASE__INST1_SEG1 0 +#define SDMA5_BASE__INST1_SEG2 0 +#define SDMA5_BASE__INST1_SEG3 0 +#define SDMA5_BASE__INST1_SEG4 0 +#define SDMA5_BASE__INST1_SEG5 0 + +#define SDMA5_BASE__INST2_SEG0 0 +#define SDMA5_BASE__INST2_SEG1 0 +#define SDMA5_BASE__INST2_SEG2 0 +#define SDMA5_BASE__INST2_SEG3 0 +#define SDMA5_BASE__INST2_SEG4 0 +#define SDMA5_BASE__INST2_SEG5 0 + +#define SDMA5_BASE__INST3_SEG0 0 +#define SDMA5_BASE__INST3_SEG1 0 +#define SDMA5_BASE__INST3_SEG2 0 +#define SDMA5_BASE__INST3_SEG3 0 +#define SDMA5_BASE__INST3_SEG4 0 +#define SDMA5_BASE__INST3_SEG5 0 + +#define SDMA5_BASE__INST4_SEG0 0 +#define SDMA5_BASE__INST4_SEG1 0 +#define SDMA5_BASE__INST4_SEG2 0 +#define SDMA5_BASE__INST4_SEG3 0 +#define SDMA5_BASE__INST4_SEG4 0 +#define SDMA5_BASE__INST4_SEG5 0 + +#define SDMA5_BASE__INST5_SEG0 0 +#define SDMA5_BASE__INST5_SEG1 0 +#define SDMA5_BASE__INST5_SEG2 0 +#define SDMA5_BASE__INST5_SEG3 0 +#define SDMA5_BASE__INST5_SEG4 0 +#define SDMA5_BASE__INST5_SEG5 0 + +#define SDMA5_BASE__INST6_SEG0 0 +#define SDMA5_BASE__INST6_SEG1 0 +#define SDMA5_BASE__INST6_SEG2 0 +#define SDMA5_BASE__INST6_SEG3 0 +#define SDMA5_BASE__INST6_SEG4 0 +#define SDMA5_BASE__INST6_SEG5 0 + +#define SDMA6_BASE__INST0_SEG0 0x000137E0 +#define SDMA6_BASE__INST0_SEG1 0x0001F000 +#define SDMA6_BASE__INST0_SEG2 0x0042FC00 +#define SDMA6_BASE__INST0_SEG3 0 +#define SDMA6_BASE__INST0_SEG4 0 +#define SDMA6_BASE__INST0_SEG5 0 + +#define SDMA6_BASE__INST1_SEG0 0 +#define SDMA6_BASE__INST1_SEG1 0 +#define SDMA6_BASE__INST1_SEG2 0 +#define SDMA6_BASE__INST1_SEG3 0 +#define SDMA6_BASE__INST1_SEG4 0 +#define SDMA6_BASE__INST1_SEG5 0 + +#define SDMA6_BASE__INST2_SEG0 0 +#define SDMA6_BASE__INST2_SEG1 0 +#define SDMA6_BASE__INST2_SEG2 0 +#define SDMA6_BASE__INST2_SEG3 0 +#define SDMA6_BASE__INST2_SEG4 0 +#define SDMA6_BASE__INST2_SEG5 0 + +#define SDMA6_BASE__INST3_SEG0 0 +#define SDMA6_BASE__INST3_SEG1 0 +#define SDMA6_BASE__INST3_SEG2 0 +#define SDMA6_BASE__INST3_SEG3 0 +#define SDMA6_BASE__INST3_SEG4 0 +#define SDMA6_BASE__INST3_SEG5 0 + +#define SDMA6_BASE__INST4_SEG0 0 +#define SDMA6_BASE__INST4_SEG1 0 +#define SDMA6_BASE__INST4_SEG2 0 +#define SDMA6_BASE__INST4_SEG3 0 +#define SDMA6_BASE__INST4_SEG4 0 +#define SDMA6_BASE__INST4_SEG5 0 + +#define SDMA6_BASE__INST5_SEG0 0 +#define SDMA6_BASE__INST5_SEG1 0 +#define SDMA6_BASE__INST5_SEG2 0 +#define SDMA6_BASE__INST5_SEG3 0 +#define SDMA6_BASE__INST5_SEG4 0 +#define SDMA6_BASE__INST5_SEG5 0 + +#define SDMA6_BASE__INST6_SEG0 0 +#define SDMA6_BASE__INST6_SEG1 0 +#define SDMA6_BASE__INST6_SEG2 0 +#define SDMA6_BASE__INST6_SEG3 0 +#define SDMA6_BASE__INST6_SEG4 0 +#define SDMA6_BASE__INST6_SEG5 0 + +#define SDMA7_BASE__INST0_SEG0 0x00013800 +#define SDMA7_BASE__INST0_SEG1 0x0001F400 +#define SDMA7_BASE__INST0_SEG2 0x00430000 +#define SDMA7_BASE__INST0_SEG3 0 +#define SDMA7_BASE__INST0_SEG4 0 +#define SDMA7_BASE__INST0_SEG5 0 + +#define SDMA7_BASE__INST1_SEG0 0 +#define SDMA7_BASE__INST1_SEG1 0 +#define SDMA7_BASE__INST1_SEG2 0 +#define SDMA7_BASE__INST1_SEG3 0 +#define SDMA7_BASE__INST1_SEG4 0 +#define SDMA7_BASE__INST1_SEG5 0 + +#define SDMA7_BASE__INST2_SEG0 0 +#define SDMA7_BASE__INST2_SEG1 0 +#define SDMA7_BASE__INST2_SEG2 0 +#define SDMA7_BASE__INST2_SEG3 0 +#define SDMA7_BASE__INST2_SEG4 0 +#define SDMA7_BASE__INST2_SEG5 0 + +#define SDMA7_BASE__INST3_SEG0 0 +#define SDMA7_BASE__INST3_SEG1 0 +#define SDMA7_BASE__INST3_SEG2 0 +#define SDMA7_BASE__INST3_SEG3 0 +#define SDMA7_BASE__INST3_SEG4 0 +#define SDMA7_BASE__INST3_SEG5 0 + +#define SDMA7_BASE__INST4_SEG0 0 +#define SDMA7_BASE__INST4_SEG1 0 +#define SDMA7_BASE__INST4_SEG2 0 +#define SDMA7_BASE__INST4_SEG3 0 +#define SDMA7_BASE__INST4_SEG4 0 +#define SDMA7_BASE__INST4_SEG5 0 + +#define SDMA7_BASE__INST5_SEG0 0 +#define SDMA7_BASE__INST5_SEG1 0 +#define SDMA7_BASE__INST5_SEG2 0 +#define SDMA7_BASE__INST5_SEG3 0 +#define SDMA7_BASE__INST5_SEG4 0 +#define SDMA7_BASE__INST5_SEG5 0 + +#define SDMA7_BASE__INST6_SEG0 0 +#define SDMA7_BASE__INST6_SEG1 0 +#define SDMA7_BASE__INST6_SEG2 0 +#define SDMA7_BASE__INST6_SEG3 0 +#define SDMA7_BASE__INST6_SEG4 0 +#define SDMA7_BASE__INST6_SEG5 0 + +#define SMUIO_BASE__INST0_SEG0 0x00012080 +#define SMUIO_BASE__INST0_SEG1 0x00016800 +#define SMUIO_BASE__INST0_SEG2 0x00016A00 +#define SMUIO_BASE__INST0_SEG3 0x00401000 +#define SMUIO_BASE__INST0_SEG4 0x00440000 +#define SMUIO_BASE__INST0_SEG5 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 +#define SMUIO_BASE__INST1_SEG5 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 +#define SMUIO_BASE__INST2_SEG5 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 +#define SMUIO_BASE__INST3_SEG5 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 +#define SMUIO_BASE__INST4_SEG5 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 +#define SMUIO_BASE__INST5_SEG5 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 +#define SMUIO_BASE__INST6_SEG5 0 + +#define SMUIO_BASE__INST7_SEG0 0 +#define SMUIO_BASE__INST7_SEG1 0 +#define SMUIO_BASE__INST7_SEG2 0 +#define SMUIO_BASE__INST7_SEG3 0 +#define SMUIO_BASE__INST7_SEG4 0 +#define SMUIO_BASE__INST7_SEG5 0 + +#define THM_BASE__INST0_SEG0 0x00012060 +#define THM_BASE__INST0_SEG1 0x00016600 +#define THM_BASE__INST0_SEG2 0x00400C00 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 +#define THM_BASE__INST0_SEG5 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 +#define THM_BASE__INST1_SEG5 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 +#define THM_BASE__INST2_SEG5 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 +#define THM_BASE__INST3_SEG5 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 +#define THM_BASE__INST4_SEG5 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 +#define THM_BASE__INST5_SEG5 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 +#define THM_BASE__INST6_SEG5 0 + +#define THM_BASE__INST7_SEG0 0 +#define THM_BASE__INST7_SEG1 0 +#define THM_BASE__INST7_SEG2 0 +#define THM_BASE__INST7_SEG3 0 +#define THM_BASE__INST7_SEG4 0 +#define THM_BASE__INST7_SEG5 0 + +#define UMC_BASE__INST0_SEG0 0x000132C0 +#define UMC_BASE__INST0_SEG1 0x00014000 +#define UMC_BASE__INST0_SEG2 0x00425800 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 +#define UMC_BASE__INST0_SEG5 0 + +#define UMC_BASE__INST1_SEG0 0x000132E0 +#define UMC_BASE__INST1_SEG1 0x00054000 +#define UMC_BASE__INST1_SEG2 0x00425C00 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 +#define UMC_BASE__INST1_SEG5 0 + +#define UMC_BASE__INST2_SEG0 0x00013300 +#define UMC_BASE__INST2_SEG1 0x00094000 +#define UMC_BASE__INST2_SEG2 0x00426000 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 +#define UMC_BASE__INST2_SEG5 0 + +#define UMC_BASE__INST3_SEG0 0x00013320 +#define UMC_BASE__INST3_SEG1 0x000D4000 +#define UMC_BASE__INST3_SEG2 0x00426400 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 +#define UMC_BASE__INST3_SEG5 0 + +#define UMC_BASE__INST4_SEG0 0x00013340 +#define UMC_BASE__INST4_SEG1 0x00114000 +#define UMC_BASE__INST4_SEG2 0x00426800 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 +#define UMC_BASE__INST4_SEG5 0 + +#define UMC_BASE__INST5_SEG0 0x00013360 +#define UMC_BASE__INST5_SEG1 0x00154000 +#define UMC_BASE__INST5_SEG2 0x00426C00 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 +#define UMC_BASE__INST5_SEG5 0 + +#define UMC_BASE__INST6_SEG0 0x00013380 +#define UMC_BASE__INST6_SEG1 0x00194000 +#define UMC_BASE__INST6_SEG2 0x00427000 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 +#define UMC_BASE__INST6_SEG5 0 + +#define UMC_BASE__INST7_SEG0 0x000133A0 +#define UMC_BASE__INST7_SEG1 0x001D4000 +#define UMC_BASE__INST7_SEG2 0x00427400 +#define UMC_BASE__INST7_SEG3 0 +#define UMC_BASE__INST7_SEG4 0 +#define UMC_BASE__INST7_SEG5 0 + +#define UVD_BASE__INST0_SEG0 0x00007800 +#define UVD_BASE__INST0_SEG1 0x00007E00 +#define UVD_BASE__INST0_SEG2 0x00012180 +#define UVD_BASE__INST0_SEG3 0x00403000 +#define UVD_BASE__INST0_SEG4 0 +#define UVD_BASE__INST0_SEG5 0 + +#define UVD_BASE__INST1_SEG0 0x00007A00 +#define UVD_BASE__INST1_SEG1 0x00009000 +#define UVD_BASE__INST1_SEG2 0x000136E0 +#define UVD_BASE__INST1_SEG3 0x0042DC00 +#define UVD_BASE__INST1_SEG4 0 +#define UVD_BASE__INST1_SEG5 0 + +#define UVD_BASE__INST2_SEG0 0 +#define UVD_BASE__INST2_SEG1 0 +#define UVD_BASE__INST2_SEG2 0 +#define UVD_BASE__INST2_SEG3 0 +#define UVD_BASE__INST2_SEG4 0 +#define UVD_BASE__INST2_SEG5 0 + +#define UVD_BASE__INST3_SEG0 0 +#define UVD_BASE__INST3_SEG1 0 +#define UVD_BASE__INST3_SEG2 0 +#define UVD_BASE__INST3_SEG3 0 +#define UVD_BASE__INST3_SEG4 0 +#define UVD_BASE__INST3_SEG5 0 + +#define UVD_BASE__INST4_SEG0 0 +#define UVD_BASE__INST4_SEG1 0 +#define UVD_BASE__INST4_SEG2 0 +#define UVD_BASE__INST4_SEG3 0 +#define UVD_BASE__INST4_SEG4 0 +#define UVD_BASE__INST4_SEG5 0 + +#define UVD_BASE__INST5_SEG0 0 +#define UVD_BASE__INST5_SEG1 0 +#define UVD_BASE__INST5_SEG2 0 +#define UVD_BASE__INST5_SEG3 0 +#define UVD_BASE__INST5_SEG4 0 +#define UVD_BASE__INST5_SEG5 0 + +#define UVD_BASE__INST6_SEG0 0 +#define UVD_BASE__INST6_SEG1 0 +#define UVD_BASE__INST6_SEG2 0 +#define UVD_BASE__INST6_SEG3 0 +#define UVD_BASE__INST6_SEG4 0 +#define UVD_BASE__INST6_SEG5 0 + +#define UVD_BASE__INST7_SEG0 0 +#define UVD_BASE__INST7_SEG1 0 +#define UVD_BASE__INST7_SEG2 0 +#define UVD_BASE__INST7_SEG3 0 +#define UVD_BASE__INST7_SEG4 0 +#define UVD_BASE__INST7_SEG5 0 + +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 +#define DBGU_IO_BASE__INST0_SEG1 0x000125A0 +#define DBGU_IO_BASE__INST0_SEG2 0x0040B400 +#define DBGU_IO_BASE__INST0_SEG3 0 +#define DBGU_IO_BASE__INST0_SEG4 0 +#define DBGU_IO_BASE__INST0_SEG5 0 + +#define DBGU_IO_BASE__INST1_SEG0 0 +#define DBGU_IO_BASE__INST1_SEG1 0 +#define DBGU_IO_BASE__INST1_SEG2 0 +#define DBGU_IO_BASE__INST1_SEG3 0 +#define DBGU_IO_BASE__INST1_SEG4 0 +#define DBGU_IO_BASE__INST1_SEG5 0 + +#define DBGU_IO_BASE__INST2_SEG0 0 +#define DBGU_IO_BASE__INST2_SEG1 0 +#define DBGU_IO_BASE__INST2_SEG2 0 +#define DBGU_IO_BASE__INST2_SEG3 0 +#define DBGU_IO_BASE__INST2_SEG4 0 +#define DBGU_IO_BASE__INST2_SEG5 0 + +#define DBGU_IO_BASE__INST3_SEG0 0 +#define DBGU_IO_BASE__INST3_SEG1 0 +#define DBGU_IO_BASE__INST3_SEG2 0 +#define DBGU_IO_BASE__INST3_SEG3 0 +#define DBGU_IO_BASE__INST3_SEG4 0 +#define DBGU_IO_BASE__INST3_SEG5 0 + +#define DBGU_IO_BASE__INST4_SEG0 0 +#define DBGU_IO_BASE__INST4_SEG1 0 +#define DBGU_IO_BASE__INST4_SEG2 0 +#define DBGU_IO_BASE__INST4_SEG3 0 +#define DBGU_IO_BASE__INST4_SEG4 0 +#define DBGU_IO_BASE__INST4_SEG5 0 + +#define DBGU_IO_BASE__INST5_SEG0 0 +#define DBGU_IO_BASE__INST5_SEG1 0 +#define DBGU_IO_BASE__INST5_SEG2 0 +#define DBGU_IO_BASE__INST5_SEG3 0 +#define DBGU_IO_BASE__INST5_SEG4 0 +#define DBGU_IO_BASE__INST5_SEG5 0 + +#define DBGU_IO_BASE__INST6_SEG0 0 +#define DBGU_IO_BASE__INST6_SEG1 0 +#define DBGU_IO_BASE__INST6_SEG2 0 +#define DBGU_IO_BASE__INST6_SEG3 0 +#define DBGU_IO_BASE__INST6_SEG4 0 +#define DBGU_IO_BASE__INST6_SEG5 0 + +#define DBGU_IO_BASE__INST7_SEG0 0 +#define DBGU_IO_BASE__INST7_SEG1 0 +#define DBGU_IO_BASE__INST7_SEG2 0 +#define DBGU_IO_BASE__INST7_SEG3 0 +#define DBGU_IO_BASE__INST7_SEG4 0 +#define DBGU_IO_BASE__INST7_SEG5 0 + +#define RSMU_BASE__INST0_SEG0 0x00012000 +#define RSMU_BASE__INST0_SEG1 0 +#define RSMU_BASE__INST0_SEG2 0 +#define RSMU_BASE__INST0_SEG3 0 +#define RSMU_BASE__INST0_SEG4 0 +#define RSMU_BASE__INST0_SEG5 0 + +#define RSMU_BASE__INST1_SEG0 0 +#define RSMU_BASE__INST1_SEG1 0 +#define RSMU_BASE__INST1_SEG2 0 +#define RSMU_BASE__INST1_SEG3 0 +#define RSMU_BASE__INST1_SEG4 0 +#define RSMU_BASE__INST1_SEG5 0 + +#define RSMU_BASE__INST2_SEG0 0 +#define RSMU_BASE__INST2_SEG1 0 +#define RSMU_BASE__INST2_SEG2 0 +#define RSMU_BASE__INST2_SEG3 0 +#define RSMU_BASE__INST2_SEG4 0 +#define RSMU_BASE__INST2_SEG5 0 + +#define RSMU_BASE__INST3_SEG0 0 +#define RSMU_BASE__INST3_SEG1 0 +#define RSMU_BASE__INST3_SEG2 0 +#define RSMU_BASE__INST3_SEG3 0 +#define RSMU_BASE__INST3_SEG4 0 +#define RSMU_BASE__INST3_SEG5 0 + +#define RSMU_BASE__INST4_SEG0 0 +#define RSMU_BASE__INST4_SEG1 0 +#define RSMU_BASE__INST4_SEG2 0 +#define RSMU_BASE__INST4_SEG3 0 +#define RSMU_BASE__INST4_SEG4 0 +#define RSMU_BASE__INST4_SEG5 0 + +#define RSMU_BASE__INST5_SEG0 0 +#define RSMU_BASE__INST5_SEG1 0 +#define RSMU_BASE__INST5_SEG2 0 +#define RSMU_BASE__INST5_SEG3 0 +#define RSMU_BASE__INST5_SEG4 0 +#define RSMU_BASE__INST5_SEG5 0 + +#define RSMU_BASE__INST6_SEG0 0 +#define RSMU_BASE__INST6_SEG1 0 +#define RSMU_BASE__INST6_SEG2 0 +#define RSMU_BASE__INST6_SEG3 0 +#define RSMU_BASE__INST6_SEG4 0 +#define RSMU_BASE__INST6_SEG5 0 + +#define RSMU_BASE__INST7_SEG0 0 +#define RSMU_BASE__INST7_SEG1 0 +#define RSMU_BASE__INST7_SEG2 0 +#define RSMU_BASE__INST7_SEG3 0 +#define RSMU_BASE__INST7_SEG4 0 +#define RSMU_BASE__INST7_SEG5 0 + + +#endif -- cgit v1.2.3