From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 432 +++++++++++++++++++++++++ 1 file changed, 432 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_combo_phy.c (limited to 'drivers/gpu/drm/i915/display/intel_combo_phy.c') diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c new file mode 100644 index 000000000..8b870b2dd --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2018 Intel Corporation + */ + +#include "i915_reg.h" +#include "intel_combo_phy.h" +#include "intel_combo_phy_regs.h" +#include "intel_de.h" +#include "intel_display_types.h" + +#define for_each_combo_phy(__dev_priv, __phy) \ + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) + +#define for_each_combo_phy_reverse(__dev_priv, __phy) \ + for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) + +enum { + PROCMON_0_85V_DOT_0, + PROCMON_0_95V_DOT_0, + PROCMON_0_95V_DOT_1, + PROCMON_1_05V_DOT_0, + PROCMON_1_05V_DOT_1, +}; + +static const struct icl_procmon { + const char *name; + u32 dw1, dw9, dw10; +} icl_procmon_values[] = { + [PROCMON_0_85V_DOT_0] = { + .name = "0.85V dot0 (low-voltage)", + .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, + }, + [PROCMON_0_95V_DOT_0] = { + .name = "0.95V dot0", + .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, + }, + [PROCMON_0_95V_DOT_1] = { + .name = "0.95V dot1", + .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, + }, + [PROCMON_1_05V_DOT_0] = { + .name = "1.05V dot0", + .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, + }, + [PROCMON_1_05V_DOT_1] = { + .name = "1.05V dot1", + .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, + }, +}; + +static const struct icl_procmon * +icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) +{ + u32 val; + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); + switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { + default: + MISSING_CASE(val); + fallthrough; + case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: + return &icl_procmon_values[PROCMON_0_85V_DOT_0]; + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: + return &icl_procmon_values[PROCMON_0_95V_DOT_0]; + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: + return &icl_procmon_values[PROCMON_0_95V_DOT_1]; + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: + return &icl_procmon_values[PROCMON_1_05V_DOT_0]; + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: + return &icl_procmon_values[PROCMON_1_05V_DOT_1]; + } +} + +static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv, + enum phy phy) +{ + const struct icl_procmon *procmon; + u32 val; + + procmon = icl_get_procmon_ref_values(dev_priv, phy); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); + val &= ~((0xff << 16) | 0xff); + val |= procmon->dw1; + intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); + + intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); + intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); +} + +static bool check_phy_reg(struct drm_i915_private *dev_priv, + enum phy phy, i915_reg_t reg, u32 mask, + u32 expected_val) +{ + u32 val = intel_de_read(dev_priv, reg); + + if ((val & mask) != expected_val) { + drm_dbg(&dev_priv->drm, + "Combo PHY %c reg %08x state mismatch: " + "current %08x mask %08x expected %08x\n", + phy_name(phy), + reg.reg, val, mask, expected_val); + return false; + } + + return true; +} + +static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, + enum phy phy) +{ + const struct icl_procmon *procmon; + bool ret; + + procmon = icl_get_procmon_ref_values(dev_priv, phy); + + drm_dbg_kms(&dev_priv->drm, + "Combo PHY %c Voltage/Process Info : %s\n", + phy_name(phy), procmon->name); + + ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), + (0xff << 16) | 0xff, procmon->dw1); + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), + -1U, procmon->dw9); + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), + -1U, procmon->dw10); + + return ret; +} + +static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) +{ + /* + * Some platforms only expect PHY_MISC to be programmed for PHY-A and + * PHY-B and may not even have instances of the register for the + * other combo PHY's. + * + * ADL-S technically has three instances of PHY_MISC, but only requires + * that we program it for PHY A. + */ + + if (IS_ALDERLAKE_S(i915)) + return phy == PHY_A; + else if (IS_JSL_EHL(i915) || + IS_ROCKETLAKE(i915) || + IS_DG1(i915)) + return phy < PHY_C; + + return true; +} + +static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, + enum phy phy) +{ + /* The PHY C added by EHL has no PHY_MISC register */ + if (!has_phy_misc(dev_priv, phy)) + return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; + else + return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & + ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && + (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); +} + +static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) +{ + bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A); + bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D); + bool dsi_present = intel_bios_is_dsi_present(i915, NULL); + + /* + * VBT's 'dvo port' field for child devices references the DDI, not + * the PHY. So if combo PHY A is wired up to drive an external + * display, we should see a child device present on PORT_D and + * nothing on PORT_A and no DSI. + */ + if (ddi_d_present && !ddi_a_present && !dsi_present) + return true; + + /* + * If we encounter a VBT that claims to have an external display on + * DDI-D _and_ an internal display on DDI-A/DSI leave an error message + * in the log and let the internal display win. + */ + if (ddi_d_present) + drm_err(&i915->drm, + "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); + + return false; +} + +static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) +{ + /* + * Certain PHYs are connected to compensation resistors and act + * as masters to other PHYs. + * + * ICL,TGL: + * A(master) -> B(slave), C(slave) + * RKL,DG1: + * A(master) -> B(slave) + * C(master) -> D(slave) + * ADL-S: + * A(master) -> B(slave), C(slave) + * D(master) -> E(slave) + * + * We must set the IREFGEN bit for any PHY acting as a master + * to another PHY. + */ + if (phy == PHY_A) + return true; + else if (IS_ALDERLAKE_S(dev_priv)) + return phy == PHY_D; + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + return phy == PHY_C; + + return false; +} + +static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, + enum phy phy) +{ + bool ret = true; + u32 expected_val = 0; + + if (!icl_combo_phy_enabled(dev_priv, phy)) + return false; + + if (DISPLAY_VER(dev_priv) >= 12) { + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy), + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); + + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), + DCC_MODE_SELECT_MASK, + DCC_MODE_SELECT_CONTINUOSLY); + } + + ret &= icl_verify_procmon_ref_values(dev_priv, phy); + + if (phy_is_master(dev_priv, phy)) { + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), + IREFGEN, IREFGEN); + + if (IS_JSL_EHL(dev_priv)) { + if (ehl_vbt_ddi_d_present(dev_priv)) + expected_val = ICL_PHY_MISC_MUX_DDID; + + ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), + ICL_PHY_MISC_MUX_DDID, + expected_val); + } + } + + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), + CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); + + return ret; +} + +void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, + enum phy phy, bool is_dsi, + int lane_count, bool lane_reversal) +{ + u8 lane_mask; + u32 val; + + if (is_dsi) { + drm_WARN_ON(&dev_priv->drm, lane_reversal); + + switch (lane_count) { + case 1: + lane_mask = PWR_DOWN_LN_3_1_0; + break; + case 2: + lane_mask = PWR_DOWN_LN_3_1; + break; + case 3: + lane_mask = PWR_DOWN_LN_3; + break; + default: + MISSING_CASE(lane_count); + fallthrough; + case 4: + lane_mask = PWR_UP_ALL_LANES; + break; + } + } else { + switch (lane_count) { + case 1: + lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : + PWR_DOWN_LN_3_2_1; + break; + case 2: + lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : + PWR_DOWN_LN_3_2; + break; + default: + MISSING_CASE(lane_count); + fallthrough; + case 4: + lane_mask = PWR_UP_ALL_LANES; + break; + } + } + + val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); + val &= ~PWR_DOWN_LN_MASK; + val |= lane_mask; + intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); +} + +static void icl_combo_phys_init(struct drm_i915_private *dev_priv) +{ + enum phy phy; + + for_each_combo_phy(dev_priv, phy) { + u32 val; + + if (icl_combo_phy_verify_state(dev_priv, phy)) { + drm_dbg(&dev_priv->drm, + "Combo PHY %c already enabled, won't reprogram it.\n", + phy_name(phy)); + continue; + } + + if (!has_phy_misc(dev_priv, phy)) + goto skip_phy_misc; + + /* + * EHL's combo PHY A can be hooked up to either an external + * display (via DDI-D) or an internal display (via DDI-A or + * the DSI DPHY). This is a motherboard design decision that + * can't be changed on the fly, so initialize the PHY's mux + * based on whether our VBT indicates the presence of any + * "internal" child devices. + */ + val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); + if (IS_JSL_EHL(dev_priv) && phy == PHY_A) { + val &= ~ICL_PHY_MISC_MUX_DDID; + + if (ehl_vbt_ddi_d_present(dev_priv)) + val |= ICL_PHY_MISC_MUX_DDID; + } + + val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; + intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); + +skip_phy_misc: + if (DISPLAY_VER(dev_priv) >= 12) { + val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); + val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK; + val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL; + val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2; + intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); + + val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); + val &= ~DCC_MODE_SELECT_MASK; + val |= DCC_MODE_SELECT_CONTINUOSLY; + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); + } + + icl_set_procmon_ref_values(dev_priv, phy); + + if (phy_is_master(dev_priv, phy)) { + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); + val |= IREFGEN; + intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); + } + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); + val |= COMP_INIT; + intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); + + val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); + val |= CL_POWER_DOWN_ENABLE; + intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); + } +} + +static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) +{ + enum phy phy; + + for_each_combo_phy_reverse(dev_priv, phy) { + u32 val; + + if (phy == PHY_A && + !icl_combo_phy_verify_state(dev_priv, phy)) { + if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) { + /* + * A known problem with old ifwi: + * https://gitlab.freedesktop.org/drm/intel/-/issues/2411 + * Suppress the warning for CI. Remove ASAP! + */ + drm_dbg_kms(&dev_priv->drm, + "Combo PHY %c HW state changed unexpectedly\n", + phy_name(phy)); + } else { + drm_warn(&dev_priv->drm, + "Combo PHY %c HW state changed unexpectedly\n", + phy_name(phy)); + } + } + + if (!has_phy_misc(dev_priv, phy)) + goto skip_phy_misc; + + val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); + val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; + intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); + +skip_phy_misc: + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); + val &= ~COMP_INIT; + intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); + } +} + +void intel_combo_phy_init(struct drm_i915_private *i915) +{ + icl_combo_phys_init(i915); +} + +void intel_combo_phy_uninit(struct drm_i915_private *i915) +{ + icl_combo_phys_uninit(i915); +} -- cgit v1.2.3