From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/media/pci/smipcie/smipcie.h | 309 ++++++++++++++++++++++++++++++++++++ 1 file changed, 309 insertions(+) create mode 100644 drivers/media/pci/smipcie/smipcie.h (limited to 'drivers/media/pci/smipcie/smipcie.h') diff --git a/drivers/media/pci/smipcie/smipcie.h b/drivers/media/pci/smipcie/smipcie.h new file mode 100644 index 000000000..2b5e01548 --- /dev/null +++ b/drivers/media/pci/smipcie/smipcie.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * SMI PCIe driver for DVBSky cards. + * + * Copyright (C) 2014 Max nibble + */ + +#ifndef _SMI_PCIE_H_ +#define _SMI_PCIE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* -------- Register Base -------- */ +#define MSI_CONTROL_REG_BASE 0x0800 +#define SYSTEM_CONTROL_REG_BASE 0x0880 +#define PCIE_EP_DEBUG_REG_BASE 0x08C0 +#define IR_CONTROL_REG_BASE 0x0900 +#define I2C_A_CONTROL_REG_BASE 0x0940 +#define I2C_B_CONTROL_REG_BASE 0x0980 +#define ATV_PORTA_CONTROL_REG_BASE 0x09C0 +#define DTV_PORTA_CONTROL_REG_BASE 0x0A00 +#define AES_PORTA_CONTROL_REG_BASE 0x0A80 +#define DMA_PORTA_CONTROL_REG_BASE 0x0AC0 +#define ATV_PORTB_CONTROL_REG_BASE 0x0B00 +#define DTV_PORTB_CONTROL_REG_BASE 0x0B40 +#define AES_PORTB_CONTROL_REG_BASE 0x0BC0 +#define DMA_PORTB_CONTROL_REG_BASE 0x0C00 +#define UART_A_REGISTER_BASE 0x0C40 +#define UART_B_REGISTER_BASE 0x0C80 +#define GPS_CONTROL_REG_BASE 0x0CC0 +#define DMA_PORTC_CONTROL_REG_BASE 0x0D00 +#define DMA_PORTD_CONTROL_REG_BASE 0x0D00 +#define AES_RANDOM_DATA_BASE 0x0D80 +#define AES_KEY_IN_BASE 0x0D90 +#define RANDOM_DATA_LIB_BASE 0x0E00 +#define IR_DATA_BUFFER_BASE 0x0F00 +#define PORTA_TS_BUFFER_BASE 0x1000 +#define PORTA_I2S_BUFFER_BASE 0x1400 +#define PORTB_TS_BUFFER_BASE 0x1800 +#define PORTB_I2S_BUFFER_BASE 0x1C00 + +/* -------- MSI control and state register -------- */ +#define MSI_DELAY_TIMER (MSI_CONTROL_REG_BASE + 0x00) +#define MSI_INT_STATUS (MSI_CONTROL_REG_BASE + 0x08) +#define MSI_INT_STATUS_CLR (MSI_CONTROL_REG_BASE + 0x0C) +#define MSI_INT_STATUS_SET (MSI_CONTROL_REG_BASE + 0x10) +#define MSI_INT_ENA (MSI_CONTROL_REG_BASE + 0x14) +#define MSI_INT_ENA_CLR (MSI_CONTROL_REG_BASE + 0x18) +#define MSI_INT_ENA_SET (MSI_CONTROL_REG_BASE + 0x1C) +#define MSI_SOFT_RESET (MSI_CONTROL_REG_BASE + 0x20) +#define MSI_CFG_SRC0 (MSI_CONTROL_REG_BASE + 0x24) + +/* -------- Hybird Controller System Control register -------- */ +#define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00) + #define rbPaMSMask 0x07 + #define rbPaMSDtvNoGpio 0x00 /*[2:0], DTV Simple mode */ + #define rbPaMSDtv4bitGpio 0x01 /*[2:0], DTV TS2 Serial mode)*/ + #define rbPaMSDtv7bitGpio 0x02 /*[2:0], DTV TS0 Serial mode*/ + #define rbPaMS8bitGpio 0x03 /*[2:0], GPIO mode selected;(8bit GPIO)*/ + #define rbPaMSAtv 0x04 /*[2:0], 3'b1xx: ATV mode select*/ + #define rbPbMSMask 0x38 + #define rbPbMSDtvNoGpio 0x00 /*[5:3], DTV Simple mode */ + #define rbPbMSDtv4bitGpio 0x08 /*[5:3], DTV TS2 Serial mode*/ + #define rbPbMSDtv7bitGpio 0x10 /*[5:3], DTV TS0 Serial mode*/ + #define rbPbMS8bitGpio 0x18 /*[5:3], GPIO mode selected;(8bit GPIO)*/ + #define rbPbMSAtv 0x20 /*[5:3], 3'b1xx: ATV mode select*/ + #define rbPaAESEN 0x40 /*[6], port A AES enable bit*/ + #define rbPbAESEN 0x80 /*[7], port B AES enable bit*/ + +#define INTERNAL_RST (SYSTEM_CONTROL_REG_BASE + 0x04) +#define PERIPHERAL_CTRL (SYSTEM_CONTROL_REG_BASE + 0x08) +#define GPIO_0to7_CTRL (SYSTEM_CONTROL_REG_BASE + 0x0C) +#define GPIO_8to15_CTRL (SYSTEM_CONTROL_REG_BASE + 0x10) +#define GPIO_16to24_CTRL (SYSTEM_CONTROL_REG_BASE + 0x14) +#define GPIO_INT_SRC_CFG (SYSTEM_CONTROL_REG_BASE + 0x18) +#define SYS_BUF_STATUS (SYSTEM_CONTROL_REG_BASE + 0x1C) +#define PCIE_IP_REG_ACS (SYSTEM_CONTROL_REG_BASE + 0x20) +#define PCIE_IP_REG_ACS_ADDR (SYSTEM_CONTROL_REG_BASE + 0x24) +#define PCIE_IP_REG_ACS_DATA (SYSTEM_CONTROL_REG_BASE + 0x28) + +/* -------- IR Control register -------- */ +#define IR_Init_Reg (IR_CONTROL_REG_BASE + 0x00) +#define IR_Idle_Cnt_Low (IR_CONTROL_REG_BASE + 0x04) +#define IR_Idle_Cnt_High (IR_CONTROL_REG_BASE + 0x05) +#define IR_Unit_Cnt_Low (IR_CONTROL_REG_BASE + 0x06) +#define IR_Unit_Cnt_High (IR_CONTROL_REG_BASE + 0x07) +#define IR_Data_Cnt (IR_CONTROL_REG_BASE + 0x08) +#define rbIRen 0x80 +#define rbIRhighidle 0x10 +#define rbIRlowidle 0x00 +#define rbIRVld 0x04 + +/* -------- I2C A control and state register -------- */ +#define I2C_A_CTL_STATUS (I2C_A_CONTROL_REG_BASE + 0x00) +#define I2C_A_ADDR (I2C_A_CONTROL_REG_BASE + 0x04) +#define I2C_A_SW_CTL (I2C_A_CONTROL_REG_BASE + 0x08) +#define I2C_A_TIME_OUT_CNT (I2C_A_CONTROL_REG_BASE + 0x0C) +#define I2C_A_FIFO_STATUS (I2C_A_CONTROL_REG_BASE + 0x10) +#define I2C_A_FS_EN (I2C_A_CONTROL_REG_BASE + 0x14) +#define I2C_A_FIFO_DATA (I2C_A_CONTROL_REG_BASE + 0x20) + +/* -------- I2C B control and state register -------- */ +#define I2C_B_CTL_STATUS (I2C_B_CONTROL_REG_BASE + 0x00) +#define I2C_B_ADDR (I2C_B_CONTROL_REG_BASE + 0x04) +#define I2C_B_SW_CTL (I2C_B_CONTROL_REG_BASE + 0x08) +#define I2C_B_TIME_OUT_CNT (I2C_B_CONTROL_REG_BASE + 0x0C) +#define I2C_B_FIFO_STATUS (I2C_B_CONTROL_REG_BASE + 0x10) +#define I2C_B_FS_EN (I2C_B_CONTROL_REG_BASE + 0x14) +#define I2C_B_FIFO_DATA (I2C_B_CONTROL_REG_BASE + 0x20) + +#define VIDEO_CTRL_STATUS_A (ATV_PORTA_CONTROL_REG_BASE + 0x04) + +/* -------- Digital TV control register, Port A -------- */ +#define MPEG2_CTRL_A (DTV_PORTA_CONTROL_REG_BASE + 0x00) +#define SERIAL_IN_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x4C) +#define VLD_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x60) +#define ERR_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x64) +#define BRD_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x68) + +/* -------- DMA Control Register, Port A -------- */ +#define DMA_PORTA_CHAN0_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x00) +#define DMA_PORTA_CHAN0_ADDR_HI (DMA_PORTA_CONTROL_REG_BASE + 0x04) +#define DMA_PORTA_CHAN0_TRANS_STATE (DMA_PORTA_CONTROL_REG_BASE + 0x08) +#define DMA_PORTA_CHAN0_CONTROL (DMA_PORTA_CONTROL_REG_BASE + 0x0C) +#define DMA_PORTA_CHAN1_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x10) +#define DMA_PORTA_CHAN1_ADDR_HI (DMA_PORTA_CONTROL_REG_BASE + 0x14) +#define DMA_PORTA_CHAN1_TRANS_STATE (DMA_PORTA_CONTROL_REG_BASE + 0x18) +#define DMA_PORTA_CHAN1_CONTROL (DMA_PORTA_CONTROL_REG_BASE + 0x1C) +#define DMA_PORTA_MANAGEMENT (DMA_PORTA_CONTROL_REG_BASE + 0x20) +#define VIDEO_CTRL_STATUS_B (ATV_PORTB_CONTROL_REG_BASE + 0x04) + +/* -------- Digital TV control register, Port B -------- */ +#define MPEG2_CTRL_B (DTV_PORTB_CONTROL_REG_BASE + 0x00) +#define SERIAL_IN_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x4C) +#define VLD_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x60) +#define ERR_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x64) +#define BRD_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x68) + +/* -------- AES control register, Port B -------- */ +#define AES_CTRL_B (AES_PORTB_CONTROL_REG_BASE + 0x00) +#define AES_KEY_BASE_B (AES_PORTB_CONTROL_REG_BASE + 0x04) + +/* -------- DMA Control Register, Port B -------- */ +#define DMA_PORTB_CHAN0_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x00) +#define DMA_PORTB_CHAN0_ADDR_HI (DMA_PORTB_CONTROL_REG_BASE + 0x04) +#define DMA_PORTB_CHAN0_TRANS_STATE (DMA_PORTB_CONTROL_REG_BASE + 0x08) +#define DMA_PORTB_CHAN0_CONTROL (DMA_PORTB_CONTROL_REG_BASE + 0x0C) +#define DMA_PORTB_CHAN1_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x10) +#define DMA_PORTB_CHAN1_ADDR_HI (DMA_PORTB_CONTROL_REG_BASE + 0x14) +#define DMA_PORTB_CHAN1_TRANS_STATE (DMA_PORTB_CONTROL_REG_BASE + 0x18) +#define DMA_PORTB_CHAN1_CONTROL (DMA_PORTB_CONTROL_REG_BASE + 0x1C) +#define DMA_PORTB_MANAGEMENT (DMA_PORTB_CONTROL_REG_BASE + 0x20) + +#define DMA_TRANS_UNIT_188 (0x00000007) + +/* -------- Macro define of 24 interrupt resource --------*/ +#define DMA_A_CHAN0_DONE_INT (0x00000001) +#define DMA_A_CHAN1_DONE_INT (0x00000002) +#define DMA_B_CHAN0_DONE_INT (0x00000004) +#define DMA_B_CHAN1_DONE_INT (0x00000008) +#define DMA_C_CHAN0_DONE_INT (0x00000010) +#define DMA_C_CHAN1_DONE_INT (0x00000020) +#define DMA_D_CHAN0_DONE_INT (0x00000040) +#define DMA_D_CHAN1_DONE_INT (0x00000080) +#define DATA_BUF_OVERFLOW_INT (0x00000100) +#define UART_0_X_INT (0x00000200) +#define UART_1_X_INT (0x00000400) +#define IR_X_INT (0x00000800) +#define GPIO_0_INT (0x00001000) +#define GPIO_1_INT (0x00002000) +#define GPIO_2_INT (0x00004000) +#define GPIO_3_INT (0x00008000) +#define ALL_INT (0x0000FFFF) + +/* software I2C bit mask */ +#define SW_I2C_MSK_MODE 0x01 +#define SW_I2C_MSK_CLK_OUT 0x02 +#define SW_I2C_MSK_DAT_OUT 0x04 +#define SW_I2C_MSK_CLK_EN 0x08 +#define SW_I2C_MSK_DAT_EN 0x10 +#define SW_I2C_MSK_DAT_IN 0x40 +#define SW_I2C_MSK_CLK_IN 0x80 + +#define SMI_VID 0x1ADE +#define SMI_PID 0x3038 +#define SMI_TS_DMA_BUF_SIZE (1024 * 188) + +struct smi_cfg_info { +#define SMI_DVBSKY_S952 0 +#define SMI_DVBSKY_S950 1 +#define SMI_DVBSKY_T9580 2 +#define SMI_DVBSKY_T982 3 +#define SMI_TECHNOTREND_S2_4200 4 + int type; + char *name; +#define SMI_TS_NULL 0 +#define SMI_TS_DMA_SINGLE 1 +#define SMI_TS_DMA_BOTH 3 +/* SMI_TS_NULL: not use; + * SMI_TS_DMA_SINGLE: use DMA 0 only; + * SMI_TS_DMA_BOTH:use DMA 0 and 1.*/ + int ts_0; + int ts_1; +#define DVBSKY_FE_NULL 0 +#define DVBSKY_FE_M88RS6000 1 +#define DVBSKY_FE_M88DS3103 2 +#define DVBSKY_FE_SIT2 3 + int fe_0; + int fe_1; + char *rc_map; +}; + +struct smi_rc { + struct smi_dev *dev; + struct rc_dev *rc_dev; + char input_phys[64]; + char device_name[64]; + u8 irData[256]; + + int users; +}; + +struct smi_port { + struct smi_dev *dev; + int idx; + int enable; + int fe_type; + /* regs */ + u32 DMA_CHAN0_ADDR_LOW; + u32 DMA_CHAN0_ADDR_HI; + u32 DMA_CHAN0_TRANS_STATE; + u32 DMA_CHAN0_CONTROL; + u32 DMA_CHAN1_ADDR_LOW; + u32 DMA_CHAN1_ADDR_HI; + u32 DMA_CHAN1_TRANS_STATE; + u32 DMA_CHAN1_CONTROL; + u32 DMA_MANAGEMENT; + /* dma */ + dma_addr_t dma_addr[2]; + u8 *cpu_addr[2]; + u32 _dmaInterruptCH0; + u32 _dmaInterruptCH1; + u32 _int_status; + struct tasklet_struct tasklet; + /* dvb */ + struct dmx_frontend hw_frontend; + struct dmx_frontend mem_frontend; + struct dmxdev dmxdev; + struct dvb_adapter dvb_adapter; + struct dvb_demux demux; + struct dvb_net dvbnet; + int users; + struct dvb_frontend *fe; + /* frontend i2c module */ + struct i2c_client *i2c_client_demod; + struct i2c_client *i2c_client_tuner; +}; + +struct smi_dev { + int nr; + struct smi_cfg_info *info; + + /* pcie */ + struct pci_dev *pci_dev; + u32 __iomem *lmmio; + + /* ts port */ + struct smi_port ts_port[2]; + + /* i2c */ + struct i2c_adapter i2c_bus[2]; + struct i2c_algo_bit_data i2c_bit[2]; + + /* ir */ + struct smi_rc ir; +}; + +#define smi_read(reg) readl(dev->lmmio + ((reg)>>2)) +#define smi_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) + +#define smi_andor(reg, mask, value) \ + writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ + ((value) & (mask)), dev->lmmio+((reg)>>2)) + +#define smi_set(reg, bit) smi_andor((reg), (bit), (bit)) +#define smi_clear(reg, bit) smi_andor((reg), (bit), 0) + +int smi_ir_irq(struct smi_rc *ir, u32 int_status); +void smi_ir_start(struct smi_rc *ir); +void smi_ir_exit(struct smi_dev *dev); +int smi_ir_init(struct smi_dev *dev); + +#endif /* #ifndef _SMI_PCIE_H_ */ -- cgit v1.2.3