From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- .../include/gaudi2/asic_reg/psoc_etr_masks.h | 311 +++++++++++++++++++++ 1 file changed, 311 insertions(+) create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h (limited to 'drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h') diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h new file mode 100644 index 000000000..42e67c105 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_MASKS_H_ +#define ASIC_REG_PSOC_ETR_MASKS_H_ + +/* + ***************************************** + * PSOC_ETR + * (Prototype: ETR) + ***************************************** + */ + +/* PSOC_ETR_RSZ */ +#define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0 +#define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF + +/* PSOC_ETR_STS */ +#define PSOC_ETR_STS_FULL_SHIFT 0 +#define PSOC_ETR_STS_FULL_MASK 0x1 +#define PSOC_ETR_STS_TRIGGERED_SHIFT 1 +#define PSOC_ETR_STS_TRIGGERED_MASK 0x2 +#define PSOC_ETR_STS_TMCREADY_SHIFT 2 +#define PSOC_ETR_STS_TMCREADY_MASK 0x4 +#define PSOC_ETR_STS_FTEMPTY_SHIFT 3 +#define PSOC_ETR_STS_FTEMPTY_MASK 0x8 +#define PSOC_ETR_STS_EMPTY_SHIFT 4 +#define PSOC_ETR_STS_EMPTY_MASK 0x10 +#define PSOC_ETR_STS_MEMERR_SHIFT 5 +#define PSOC_ETR_STS_MEMERR_MASK 0x20 + +/* PSOC_ETR_RRD */ +#define PSOC_ETR_RRD_RRD_SHIFT 0 +#define PSOC_ETR_RRD_RRD_MASK 0xFFFFFFFF + +/* PSOC_ETR_RRP */ +#define PSOC_ETR_RRP_RRP_SHIFT 0 +#define PSOC_ETR_RRP_RRP_MASK 0xFFFFFFFF + +/* PSOC_ETR_RWP */ +#define PSOC_ETR_RWP_RWP_SHIFT 0 +#define PSOC_ETR_RWP_RWP_MASK 0xFFFFFFFF + +/* PSOC_ETR_TRG */ +#define PSOC_ETR_TRG_TRG_SHIFT 0 +#define PSOC_ETR_TRG_TRG_MASK 0xFFFFFFFF + +/* PSOC_ETR_CTL */ +#define PSOC_ETR_CTL_TRACECAPTEN_SHIFT 0 +#define PSOC_ETR_CTL_TRACECAPTEN_MASK 0x1 + +/* PSOC_ETR_RWD */ +#define PSOC_ETR_RWD_RWD_SHIFT 0 +#define PSOC_ETR_RWD_RWD_MASK 0xFFFFFFFF + +/* PSOC_ETR_MODE */ +#define PSOC_ETR_MODE_MODE_SHIFT 0 +#define PSOC_ETR_MODE_MODE_MASK 0x3 + +/* PSOC_ETR_LBUFLEVEL */ +#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_SHIFT 0 +#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_MASK 0x7FFFFFFF + +/* PSOC_ETR_CBUFLEVEL */ +#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_SHIFT 0 +#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_MASK 0x7FFFFFFF + +/* PSOC_ETR_BUFWM */ +#define PSOC_ETR_BUFWM_BUFWM_SHIFT 0 +#define PSOC_ETR_BUFWM_BUFWM_MASK 0x3FFFFFFF + +/* PSOC_ETR_RRPHI */ +#define PSOC_ETR_RRPHI_RRPHI_SHIFT 0 +#define PSOC_ETR_RRPHI_RRPHI_MASK 0xFF + +/* PSOC_ETR_RWPHI */ +#define PSOC_ETR_RWPHI_RWPHI_SHIFT 0 +#define PSOC_ETR_RWPHI_RWPHI_MASK 0xFF + +/* PSOC_ETR_AXICTL */ +#define PSOC_ETR_AXICTL_PROTCTRLBIT0_SHIFT 0 +#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 +#define PSOC_ETR_AXICTL_CACHECTRLBIT0_SHIFT 2 +#define PSOC_ETR_AXICTL_CACHECTRLBIT0_MASK 0x4 +#define PSOC_ETR_AXICTL_CACHECTRLBIT1_SHIFT 3 +#define PSOC_ETR_AXICTL_CACHECTRLBIT1_MASK 0x8 +#define PSOC_ETR_AXICTL_CACHECTRLBIT2_SHIFT 4 +#define PSOC_ETR_AXICTL_CACHECTRLBIT2_MASK 0x10 +#define PSOC_ETR_AXICTL_CACHECTRLBIT3_SHIFT 5 +#define PSOC_ETR_AXICTL_CACHECTRLBIT3_MASK 0x20 +#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_SHIFT 7 +#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_MASK 0x80 +#define PSOC_ETR_AXICTL_WRBURSTLEN_SHIFT 8 +#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 + +/* PSOC_ETR_DBALO */ +#define PSOC_ETR_DBALO_BUFADDRLO_SHIFT 0 +#define PSOC_ETR_DBALO_BUFADDRLO_MASK 0xFFFFFFFF + +/* PSOC_ETR_DBAHI */ +#define PSOC_ETR_DBAHI_BUFADDRHI_SHIFT 0 +#define PSOC_ETR_DBAHI_BUFADDRHI_MASK 0xFF + +/* PSOC_ETR_FFSR */ +#define PSOC_ETR_FFSR_FLINPROG_SHIFT 0 +#define PSOC_ETR_FFSR_FLINPROG_MASK 0x1 +#define PSOC_ETR_FFSR_FTSTOPPED_SHIFT 1 +#define PSOC_ETR_FFSR_FTSTOPPED_MASK 0x2 + +/* PSOC_ETR_FFCR */ +#define PSOC_ETR_FFCR_ENFT_SHIFT 0 +#define PSOC_ETR_FFCR_ENFT_MASK 0x1 +#define PSOC_ETR_FFCR_ENTI_SHIFT 1 +#define PSOC_ETR_FFCR_ENTI_MASK 0x2 +#define PSOC_ETR_FFCR_FONFLIN_SHIFT 4 +#define PSOC_ETR_FFCR_FONFLIN_MASK 0x10 +#define PSOC_ETR_FFCR_FONTRIGEVT_SHIFT 5 +#define PSOC_ETR_FFCR_FONTRIGEVT_MASK 0x20 +#define PSOC_ETR_FFCR_FLUSHMAN_SHIFT 6 +#define PSOC_ETR_FFCR_FLUSHMAN_MASK 0x40 +#define PSOC_ETR_FFCR_TRIGONTRIGIN_SHIFT 8 +#define PSOC_ETR_FFCR_TRIGONTRIGIN_MASK 0x100 +#define PSOC_ETR_FFCR_TRIGONTRIGEVT_SHIFT 9 +#define PSOC_ETR_FFCR_TRIGONTRIGEVT_MASK 0x200 +#define PSOC_ETR_FFCR_TRIGONFL_SHIFT 10 +#define PSOC_ETR_FFCR_TRIGONFL_MASK 0x400 +#define PSOC_ETR_FFCR_STOPONFL_SHIFT 12 +#define PSOC_ETR_FFCR_STOPONFL_MASK 0x1000 +#define PSOC_ETR_FFCR_STOPONTRIGEVT_SHIFT 13 +#define PSOC_ETR_FFCR_STOPONTRIGEVT_MASK 0x2000 + +/* PSOC_ETR_PSCR */ +#define PSOC_ETR_PSCR_PSCOUNT_SHIFT 0 +#define PSOC_ETR_PSCR_PSCOUNT_MASK 0x1F + +/* PSOC_ETR_ITMISCOP0 */ +#define PSOC_ETR_ITMISCOP0_ACQCOMP_SHIFT 0 +#define PSOC_ETR_ITMISCOP0_ACQCOMP_MASK 0x1 +#define PSOC_ETR_ITMISCOP0_FULL_SHIFT 1 +#define PSOC_ETR_ITMISCOP0_FULL_MASK 0x2 + +/* PSOC_ETR_ITTRFLIN */ +#define PSOC_ETR_ITTRFLIN_TRIGIN_SHIFT 0 +#define PSOC_ETR_ITTRFLIN_TRIGIN_MASK 0x1 +#define PSOC_ETR_ITTRFLIN_FLUSHIN_SHIFT 1 +#define PSOC_ETR_ITTRFLIN_FLUSHIN_MASK 0x2 + +/* PSOC_ETR_ITATBDATA0 */ +#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_SHIFT 0 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_MASK 0x1 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_SHIFT 1 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_MASK 0x2 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_SHIFT 2 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_MASK 0x4 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_SHIFT 3 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_MASK 0x8 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_SHIFT 4 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_MASK 0x10 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_SHIFT 5 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_MASK 0x20 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_SHIFT 6 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_MASK 0x40 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_SHIFT 7 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_MASK 0x80 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_SHIFT 8 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_MASK 0x100 + +/* PSOC_ETR_ITATBCTR2 */ +#define PSOC_ETR_ITATBCTR2_ATREADYS_SHIFT 0 +#define PSOC_ETR_ITATBCTR2_ATREADYS_MASK 0x1 +#define PSOC_ETR_ITATBCTR2_AFVALIDS_SHIFT 1 +#define PSOC_ETR_ITATBCTR2_AFVALIDS_MASK 0x2 +#define PSOC_ETR_ITATBCTR2_SYNCREQS_SHIFT 2 +#define PSOC_ETR_ITATBCTR2_SYNCREQS_MASK 0x4 + +/* PSOC_ETR_ITATBCTR1 */ +#define PSOC_ETR_ITATBCTR1_ATIDS_SHIFT 0 +#define PSOC_ETR_ITATBCTR1_ATIDS_MASK 0x7F + +/* PSOC_ETR_ITATBCTR0 */ +#define PSOC_ETR_ITATBCTR0_ATVALIDS_SHIFT 0 +#define PSOC_ETR_ITATBCTR0_ATVALIDS_MASK 0x1 +#define PSOC_ETR_ITATBCTR0_AFREADYS_SHIFT 1 +#define PSOC_ETR_ITATBCTR0_AFREADYS_MASK 0x2 +#define PSOC_ETR_ITATBCTR0_ATBYTESS_SHIFT 8 +#define PSOC_ETR_ITATBCTR0_ATBYTESS_MASK 0x700 + +/* PSOC_ETR_ITCTRL */ +#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_SHIFT 0 +#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_MASK 0x1 + +/* PSOC_ETR_CLAIMSET */ +#define PSOC_ETR_CLAIMSET_CLAIMSET_SHIFT 0 +#define PSOC_ETR_CLAIMSET_CLAIMSET_MASK 0xF + +/* PSOC_ETR_CLAIMCLR */ +#define PSOC_ETR_CLAIMCLR_CLAIMCLR_SHIFT 0 +#define PSOC_ETR_CLAIMCLR_CLAIMCLR_MASK 0xF + +/* PSOC_ETR_LAR */ +#define PSOC_ETR_LAR_ACCESS_W_SHIFT 0 +#define PSOC_ETR_LAR_ACCESS_W_MASK 0xFFFFFFFF + +/* PSOC_ETR_LSR */ +#define PSOC_ETR_LSR_LOCKEXIST_SHIFT 0 +#define PSOC_ETR_LSR_LOCKEXIST_MASK 0x1 +#define PSOC_ETR_LSR_LOCKGRANT_SHIFT 1 +#define PSOC_ETR_LSR_LOCKGRANT_MASK 0x2 +#define PSOC_ETR_LSR_LOCKTYPE_SHIFT 2 +#define PSOC_ETR_LSR_LOCKTYPE_MASK 0x4 + +/* PSOC_ETR_AUTHSTATUS */ +#define PSOC_ETR_AUTHSTATUS_NSID_SHIFT 0 +#define PSOC_ETR_AUTHSTATUS_NSID_MASK 0x3 +#define PSOC_ETR_AUTHSTATUS_NSNID_SHIFT 2 +#define PSOC_ETR_AUTHSTATUS_NSNID_MASK 0xC +#define PSOC_ETR_AUTHSTATUS_SID_SHIFT 4 +#define PSOC_ETR_AUTHSTATUS_SID_MASK 0x30 +#define PSOC_ETR_AUTHSTATUS_SNID_SHIFT 6 +#define PSOC_ETR_AUTHSTATUS_SNID_MASK 0xC0 + +/* PSOC_ETR_DEVID */ +#define PSOC_ETR_DEVID_ATBINPORTCOUNT_SHIFT 0 +#define PSOC_ETR_DEVID_ATBINPORTCOUNT_MASK 0x1F +#define PSOC_ETR_DEVID_CLKSCHEME_SHIFT 5 +#define PSOC_ETR_DEVID_CLKSCHEME_MASK 0x20 +#define PSOC_ETR_DEVID_CONFIGTYPE_SHIFT 6 +#define PSOC_ETR_DEVID_CONFIGTYPE_MASK 0xC0 +#define PSOC_ETR_DEVID_MEMWIDTH_SHIFT 8 +#define PSOC_ETR_DEVID_MEMWIDTH_MASK 0x700 +#define PSOC_ETR_DEVID_WBUF_DEPTH_SHIFT 11 +#define PSOC_ETR_DEVID_WBUF_DEPTH_MASK 0x3800 + +/* PSOC_ETR_DEVTYPE */ +#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_SHIFT 0 +#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_MASK 0xF +#define PSOC_ETR_DEVTYPE_SUB_TYPE_SHIFT 4 +#define PSOC_ETR_DEVTYPE_SUB_TYPE_MASK 0xF0 + +/* PSOC_ETR_PERIPHID4 */ +#define PSOC_ETR_PERIPHID4_JEP106_CONT_SHIFT 0 +#define PSOC_ETR_PERIPHID4_JEP106_CONT_MASK 0xF +#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_SHIFT 4 +#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_MASK 0xF0 + +/* PSOC_ETR_PERIPHID5 */ +#define PSOC_ETR_PERIPHID5_PERIPHID5_SHIFT 0 +#define PSOC_ETR_PERIPHID5_PERIPHID5_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID6 */ +#define PSOC_ETR_PERIPHID6_PERIPHID6_SHIFT 0 +#define PSOC_ETR_PERIPHID6_PERIPHID6_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID7 */ +#define PSOC_ETR_PERIPHID7_PERIPHID7_SHIFT 0 +#define PSOC_ETR_PERIPHID7_PERIPHID7_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID0 */ +#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_SHIFT 0 +#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_MASK 0xFF + +/* PSOC_ETR_PERIPHID1 */ +#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_SHIFT 0 +#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_MASK 0xF +#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_SHIFT 4 +#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_MASK 0xF0 + +/* PSOC_ETR_PERIPHID2 */ +#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_SHIFT 0 +#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_MASK 0x7 +#define PSOC_ETR_PERIPHID2_JEDEC_SHIFT 3 +#define PSOC_ETR_PERIPHID2_JEDEC_MASK 0x8 +#define PSOC_ETR_PERIPHID2_REVISION_SHIFT 4 +#define PSOC_ETR_PERIPHID2_REVISION_MASK 0xF0 + +/* PSOC_ETR_PERIPHID3 */ +#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_SHIFT 0 +#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_MASK 0xF +#define PSOC_ETR_PERIPHID3_REVAND_SHIFT 4 +#define PSOC_ETR_PERIPHID3_REVAND_MASK 0xF0 + +/* PSOC_ETR_COMPID0 */ +#define PSOC_ETR_COMPID0_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID0_PREAMBLE_MASK 0xFF + +/* PSOC_ETR_COMPID1 */ +#define PSOC_ETR_COMPID1_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID1_PREAMBLE_MASK 0xF +#define PSOC_ETR_COMPID1_F_CLASS_SHIFT 4 +#define PSOC_ETR_COMPID1_F_CLASS_MASK 0xF0 + +/* PSOC_ETR_COMPID2 */ +#define PSOC_ETR_COMPID2_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID2_PREAMBLE_MASK 0xFF + +/* PSOC_ETR_COMPID3 */ +#define PSOC_ETR_COMPID3_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID3_PREAMBLE_MASK 0xFF + +#endif /* ASIC_REG_PSOC_ETR_MASKS_H_ */ -- cgit v1.2.3