From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- .../habanalabs/include/gaudi2/gaudi2_coresight.h | 984 +++++++++++++++++++++ 1 file changed, 984 insertions(+) create mode 100644 drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h (limited to 'drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h') diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h new file mode 100644 index 000000000..14f09d775 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h @@ -0,0 +1,984 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI2_CORESIGHT_H +#define GAUDI2_CORESIGHT_H + +enum gaudi2_debug_stm_regs_index { + GAUDI2_STM_FIRST = 0, + GAUDI2_STM_DCORE0_TPC0_EML = GAUDI2_STM_FIRST, + GAUDI2_STM_DCORE0_TPC1_EML, + GAUDI2_STM_DCORE0_TPC2_EML, + GAUDI2_STM_DCORE0_TPC3_EML, + GAUDI2_STM_DCORE0_TPC4_EML, + GAUDI2_STM_DCORE0_TPC5_EML, + GAUDI2_STM_DCORE0_TPC6_EML, + GAUDI2_STM_DCORE1_TPC0_EML, + GAUDI2_STM_DCORE1_TPC1_EML, + GAUDI2_STM_DCORE1_TPC2_EML, + GAUDI2_STM_DCORE1_TPC3_EML, + GAUDI2_STM_DCORE1_TPC4_EML, + GAUDI2_STM_DCORE1_TPC5_EML, + GAUDI2_STM_DCORE2_TPC0_EML, + GAUDI2_STM_DCORE2_TPC1_EML, + GAUDI2_STM_DCORE2_TPC2_EML, + GAUDI2_STM_DCORE2_TPC3_EML, + GAUDI2_STM_DCORE2_TPC4_EML, + GAUDI2_STM_DCORE2_TPC5_EML, + GAUDI2_STM_DCORE3_TPC0_EML, + GAUDI2_STM_DCORE3_TPC1_EML, + GAUDI2_STM_DCORE3_TPC2_EML, + GAUDI2_STM_DCORE3_TPC3_EML, + GAUDI2_STM_DCORE3_TPC4_EML, + GAUDI2_STM_DCORE3_TPC5_EML, + GAUDI2_STM_DCORE0_HMMU0_CS, + GAUDI2_STM_DCORE0_HMMU1_CS, + GAUDI2_STM_DCORE0_HMMU2_CS, + GAUDI2_STM_DCORE0_HMMU3_CS, + GAUDI2_STM_DCORE0_MME_CTRL, + GAUDI2_STM_DCORE0_MME_SBTE0, + GAUDI2_STM_DCORE0_MME_SBTE1, + GAUDI2_STM_DCORE0_MME_SBTE2, + GAUDI2_STM_DCORE0_MME_SBTE3, + GAUDI2_STM_DCORE0_MME_SBTE4, + GAUDI2_STM_DCORE0_MME_ACC, + GAUDI2_STM_DCORE0_SM, + GAUDI2_STM_DCORE0_EDMA0_CS, + GAUDI2_STM_DCORE0_EDMA1_CS, + GAUDI2_STM_DCORE0_VDEC0_CS, + GAUDI2_STM_DCORE0_VDEC1_CS, + GAUDI2_STM_DCORE1_HMMU0_CS, + GAUDI2_STM_DCORE1_HMMU1_CS, + GAUDI2_STM_DCORE1_HMMU2_CS, + GAUDI2_STM_DCORE1_HMMU3_CS, + GAUDI2_STM_DCORE1_MME_CTRL, + GAUDI2_STM_DCORE1_MME_SBTE0, + GAUDI2_STM_DCORE1_MME_SBTE1, + GAUDI2_STM_DCORE1_MME_SBTE2, + GAUDI2_STM_DCORE1_MME_SBTE3, + GAUDI2_STM_DCORE1_MME_SBTE4, + GAUDI2_STM_DCORE1_MME_ACC, + GAUDI2_STM_DCORE1_SM, + GAUDI2_STM_DCORE1_EDMA0_CS, + GAUDI2_STM_DCORE1_EDMA1_CS, + GAUDI2_STM_DCORE1_VDEC0_CS, + GAUDI2_STM_DCORE1_VDEC1_CS, + GAUDI2_STM_DCORE2_HMMU0_CS, + GAUDI2_STM_DCORE2_HMMU1_CS, + GAUDI2_STM_DCORE2_HMMU2_CS, + GAUDI2_STM_DCORE2_HMMU3_CS, + GAUDI2_STM_DCORE2_MME_CTRL, + GAUDI2_STM_DCORE2_MME_SBTE0, + GAUDI2_STM_DCORE2_MME_SBTE1, + GAUDI2_STM_DCORE2_MME_SBTE2, + GAUDI2_STM_DCORE2_MME_SBTE3, + GAUDI2_STM_DCORE2_MME_SBTE4, + GAUDI2_STM_DCORE2_MME_ACC, + GAUDI2_STM_DCORE2_SM, + GAUDI2_STM_DCORE2_EDMA0_CS, + GAUDI2_STM_DCORE2_EDMA1_CS, + GAUDI2_STM_DCORE2_VDEC0_CS, + GAUDI2_STM_DCORE2_VDEC1_CS, + GAUDI2_STM_DCORE3_HMMU0_CS, + GAUDI2_STM_DCORE3_HMMU1_CS, + GAUDI2_STM_DCORE3_HMMU2_CS, + GAUDI2_STM_DCORE3_HMMU3_CS, + GAUDI2_STM_DCORE3_MME_CTRL, + GAUDI2_STM_DCORE3_MME_SBTE0, + GAUDI2_STM_DCORE3_MME_SBTE1, + GAUDI2_STM_DCORE3_MME_SBTE2, + GAUDI2_STM_DCORE3_MME_SBTE3, + GAUDI2_STM_DCORE3_MME_SBTE4, + GAUDI2_STM_DCORE3_MME_ACC, + GAUDI2_STM_DCORE3_SM, + GAUDI2_STM_DCORE3_EDMA0_CS, + GAUDI2_STM_DCORE3_EDMA1_CS, + GAUDI2_STM_DCORE3_VDEC0_CS, + GAUDI2_STM_DCORE3_VDEC1_CS, + GAUDI2_STM_PCIE, + GAUDI2_STM_PSOC, + GAUDI2_STM_PSOC_ARC0_CS, + GAUDI2_STM_PSOC_ARC1_CS, + GAUDI2_STM_PDMA0_CS, + GAUDI2_STM_PDMA1_CS, + GAUDI2_STM_CPU, + GAUDI2_STM_PMMU_CS, + GAUDI2_STM_ROT0_CS, + GAUDI2_STM_ROT1_CS, + GAUDI2_STM_ARC_FARM_CS, + GAUDI2_STM_KDMA_CS, + GAUDI2_STM_PCIE_VDEC0_CS, + GAUDI2_STM_PCIE_VDEC1_CS, + GAUDI2_STM_HBM0_MC0_CS, + GAUDI2_STM_HBM0_MC1_CS, + GAUDI2_STM_HBM1_MC0_CS, + GAUDI2_STM_HBM1_MC1_CS, + GAUDI2_STM_HBM2_MC0_CS, + GAUDI2_STM_HBM2_MC1_CS, + GAUDI2_STM_HBM3_MC0_CS, + GAUDI2_STM_HBM3_MC1_CS, + GAUDI2_STM_HBM4_MC0_CS, + GAUDI2_STM_HBM4_MC1_CS, + GAUDI2_STM_HBM5_MC0_CS, + GAUDI2_STM_HBM5_MC1_CS, + GAUDI2_STM_NIC0_DBG_0, + GAUDI2_STM_NIC0_DBG_1, + GAUDI2_STM_NIC1_DBG_0, + GAUDI2_STM_NIC1_DBG_1, + GAUDI2_STM_NIC2_DBG_0, + GAUDI2_STM_NIC2_DBG_1, + GAUDI2_STM_NIC3_DBG_0, + GAUDI2_STM_NIC3_DBG_1, + GAUDI2_STM_NIC4_DBG_0, + GAUDI2_STM_NIC4_DBG_1, + GAUDI2_STM_NIC5_DBG_0, + GAUDI2_STM_NIC5_DBG_1, + GAUDI2_STM_NIC6_DBG_0, + GAUDI2_STM_NIC6_DBG_1, + GAUDI2_STM_NIC7_DBG_0, + GAUDI2_STM_NIC7_DBG_1, + GAUDI2_STM_NIC8_DBG_0, + GAUDI2_STM_NIC8_DBG_1, + GAUDI2_STM_NIC9_DBG_0, + GAUDI2_STM_NIC9_DBG_1, + GAUDI2_STM_NIC10_DBG_0, + GAUDI2_STM_NIC10_DBG_1, + GAUDI2_STM_NIC11_DBG_0, + GAUDI2_STM_NIC11_DBG_1, + GAUDI2_STM_LAST = GAUDI2_STM_NIC11_DBG_1 +}; + +enum gaudi2_debug_etf_regs_index { + GAUDI2_ETF_FIRST = 0, + GAUDI2_ETF_DCORE0_TPC0_EML = GAUDI2_ETF_FIRST, + GAUDI2_ETF_DCORE0_TPC1_EML, + GAUDI2_ETF_DCORE0_TPC2_EML, + GAUDI2_ETF_DCORE0_TPC3_EML, + GAUDI2_ETF_DCORE0_TPC4_EML, + GAUDI2_ETF_DCORE0_TPC5_EML, + GAUDI2_ETF_DCORE0_TPC6_EML, + GAUDI2_ETF_DCORE1_TPC0_EML, + GAUDI2_ETF_DCORE1_TPC1_EML, + GAUDI2_ETF_DCORE1_TPC2_EML, + GAUDI2_ETF_DCORE1_TPC3_EML, + GAUDI2_ETF_DCORE1_TPC4_EML, + GAUDI2_ETF_DCORE1_TPC5_EML, + GAUDI2_ETF_DCORE2_TPC0_EML, + GAUDI2_ETF_DCORE2_TPC1_EML, + GAUDI2_ETF_DCORE2_TPC2_EML, + GAUDI2_ETF_DCORE2_TPC3_EML, + GAUDI2_ETF_DCORE2_TPC4_EML, + GAUDI2_ETF_DCORE2_TPC5_EML, + GAUDI2_ETF_DCORE3_TPC0_EML, + GAUDI2_ETF_DCORE3_TPC1_EML, + GAUDI2_ETF_DCORE3_TPC2_EML, + GAUDI2_ETF_DCORE3_TPC3_EML, + GAUDI2_ETF_DCORE3_TPC4_EML, + GAUDI2_ETF_DCORE3_TPC5_EML, + GAUDI2_ETF_DCORE0_HMMU0_CS, + GAUDI2_ETF_DCORE0_HMMU1_CS, + GAUDI2_ETF_DCORE0_HMMU2_CS, + GAUDI2_ETF_DCORE0_HMMU3_CS, + GAUDI2_ETF_DCORE0_MME_CTRL, + GAUDI2_ETF_DCORE0_MME_SBTE0, + GAUDI2_ETF_DCORE0_MME_SBTE1, + GAUDI2_ETF_DCORE0_MME_SBTE2, + GAUDI2_ETF_DCORE0_MME_SBTE3, + GAUDI2_ETF_DCORE0_MME_SBTE4, + GAUDI2_ETF_DCORE0_MME_ACC, + GAUDI2_ETF_DCORE0_SM, + GAUDI2_ETF_DCORE0_EDMA0_CS, + GAUDI2_ETF_DCORE0_EDMA1_CS, + GAUDI2_ETF_DCORE0_VDEC0_CS, + GAUDI2_ETF_DCORE0_VDEC1_CS, + GAUDI2_ETF_DCORE1_HMMU0_CS, + GAUDI2_ETF_DCORE1_HMMU1_CS, + GAUDI2_ETF_DCORE1_HMMU2_CS, + GAUDI2_ETF_DCORE1_HMMU3_CS, + GAUDI2_ETF_DCORE1_MME_CTRL, + GAUDI2_ETF_DCORE1_MME_SBTE0, + GAUDI2_ETF_DCORE1_MME_SBTE1, + GAUDI2_ETF_DCORE1_MME_SBTE2, + GAUDI2_ETF_DCORE1_MME_SBTE3, + GAUDI2_ETF_DCORE1_MME_SBTE4, + GAUDI2_ETF_DCORE1_MME_ACC, + GAUDI2_ETF_DCORE1_SM, + GAUDI2_ETF_DCORE1_EDMA0_CS, + GAUDI2_ETF_DCORE1_EDMA1_CS, + GAUDI2_ETF_DCORE1_VDEC0_CS, + GAUDI2_ETF_DCORE1_VDEC1_CS, + GAUDI2_ETF_DCORE2_HMMU0_CS, + GAUDI2_ETF_DCORE2_HMMU1_CS, + GAUDI2_ETF_DCORE2_HMMU2_CS, + GAUDI2_ETF_DCORE2_HMMU3_CS, + GAUDI2_ETF_DCORE2_MME_CTRL, + GAUDI2_ETF_DCORE2_MME_SBTE0, + GAUDI2_ETF_DCORE2_MME_SBTE1, + GAUDI2_ETF_DCORE2_MME_SBTE2, + GAUDI2_ETF_DCORE2_MME_SBTE3, + GAUDI2_ETF_DCORE2_MME_SBTE4, + GAUDI2_ETF_DCORE2_MME_ACC, + GAUDI2_ETF_DCORE2_SM, + GAUDI2_ETF_DCORE2_EDMA0_CS, + GAUDI2_ETF_DCORE2_EDMA1_CS, + GAUDI2_ETF_DCORE2_VDEC0_CS, + GAUDI2_ETF_DCORE2_VDEC1_CS, + GAUDI2_ETF_DCORE3_HMMU0_CS, + GAUDI2_ETF_DCORE3_HMMU1_CS, + GAUDI2_ETF_DCORE3_HMMU2_CS, + GAUDI2_ETF_DCORE3_HMMU3_CS, + GAUDI2_ETF_DCORE3_MME_CTRL, + GAUDI2_ETF_DCORE3_MME_SBTE0, + GAUDI2_ETF_DCORE3_MME_SBTE1, + GAUDI2_ETF_DCORE3_MME_SBTE2, + GAUDI2_ETF_DCORE3_MME_SBTE3, + GAUDI2_ETF_DCORE3_MME_SBTE4, + GAUDI2_ETF_DCORE3_MME_ACC, + GAUDI2_ETF_DCORE3_SM, + GAUDI2_ETF_DCORE3_EDMA0_CS, + GAUDI2_ETF_DCORE3_EDMA1_CS, + GAUDI2_ETF_DCORE3_VDEC0_CS, + GAUDI2_ETF_DCORE3_VDEC1_CS, + GAUDI2_ETF_PCIE, + GAUDI2_ETF_PSOC, + GAUDI2_ETF_PSOC_ARC0_CS, + GAUDI2_ETF_PSOC_ARC1_CS, + GAUDI2_ETF_PDMA0_CS, + GAUDI2_ETF_PDMA1_CS, + GAUDI2_ETF_CPU_0, + GAUDI2_ETF_CPU_1, + GAUDI2_ETF_CPU_TRACE, + GAUDI2_ETF_PMMU_CS, + GAUDI2_ETF_ROT0_CS, + GAUDI2_ETF_ROT1_CS, + GAUDI2_ETF_ARC_FARM_CS, + GAUDI2_ETF_KDMA_CS, + GAUDI2_ETF_PCIE_VDEC0_CS, + GAUDI2_ETF_PCIE_VDEC1_CS, + GAUDI2_ETF_HBM0_MC0_CS, + GAUDI2_ETF_HBM0_MC1_CS, + GAUDI2_ETF_HBM1_MC0_CS, + GAUDI2_ETF_HBM1_MC1_CS, + GAUDI2_ETF_HBM2_MC0_CS, + GAUDI2_ETF_HBM2_MC1_CS, + GAUDI2_ETF_HBM3_MC0_CS, + GAUDI2_ETF_HBM3_MC1_CS, + GAUDI2_ETF_HBM4_MC0_CS, + GAUDI2_ETF_HBM4_MC1_CS, + GAUDI2_ETF_HBM5_MC0_CS, + GAUDI2_ETF_HBM5_MC1_CS, + GAUDI2_ETF_NIC0_DBG_0, + GAUDI2_ETF_NIC0_DBG_1, + GAUDI2_ETF_NIC1_DBG_0, + GAUDI2_ETF_NIC1_DBG_1, + GAUDI2_ETF_NIC2_DBG_0, + GAUDI2_ETF_NIC2_DBG_1, + GAUDI2_ETF_NIC3_DBG_0, + GAUDI2_ETF_NIC3_DBG_1, + GAUDI2_ETF_NIC4_DBG_0, + GAUDI2_ETF_NIC4_DBG_1, + GAUDI2_ETF_NIC5_DBG_0, + GAUDI2_ETF_NIC5_DBG_1, + GAUDI2_ETF_NIC6_DBG_0, + GAUDI2_ETF_NIC6_DBG_1, + GAUDI2_ETF_NIC7_DBG_0, + GAUDI2_ETF_NIC7_DBG_1, + GAUDI2_ETF_NIC8_DBG_0, + GAUDI2_ETF_NIC8_DBG_1, + GAUDI2_ETF_NIC9_DBG_0, + GAUDI2_ETF_NIC9_DBG_1, + GAUDI2_ETF_NIC10_DBG_0, + GAUDI2_ETF_NIC10_DBG_1, + GAUDI2_ETF_NIC11_DBG_0, + GAUDI2_ETF_NIC11_DBG_1, + GAUDI2_ETF_LAST = GAUDI2_ETF_NIC11_DBG_1 +}; + +enum gaudi2_debug_funnel_regs_index { + GAUDI2_FUNNEL_FIRST = 0, + GAUDI2_FUNNEL_DCORE0_TPC0_EML = GAUDI2_FUNNEL_FIRST, + GAUDI2_FUNNEL_DCORE0_TPC1_EML, + GAUDI2_FUNNEL_DCORE0_TPC2_EML, + GAUDI2_FUNNEL_DCORE0_TPC3_EML, + GAUDI2_FUNNEL_DCORE0_TPC4_EML, + GAUDI2_FUNNEL_DCORE0_TPC5_EML, + GAUDI2_FUNNEL_DCORE0_TPC6_EML, + GAUDI2_FUNNEL_DCORE1_TPC0_EML, + GAUDI2_FUNNEL_DCORE1_TPC1_EML, + GAUDI2_FUNNEL_DCORE1_TPC2_EML, + GAUDI2_FUNNEL_DCORE1_TPC3_EML, + GAUDI2_FUNNEL_DCORE1_TPC4_EML, + GAUDI2_FUNNEL_DCORE1_TPC5_EML, + GAUDI2_FUNNEL_DCORE2_TPC0_EML, + GAUDI2_FUNNEL_DCORE2_TPC1_EML, + GAUDI2_FUNNEL_DCORE2_TPC2_EML, + GAUDI2_FUNNEL_DCORE2_TPC3_EML, + GAUDI2_FUNNEL_DCORE2_TPC4_EML, + GAUDI2_FUNNEL_DCORE2_TPC5_EML, + GAUDI2_FUNNEL_DCORE3_TPC0_EML, + GAUDI2_FUNNEL_DCORE3_TPC1_EML, + GAUDI2_FUNNEL_DCORE3_TPC2_EML, + GAUDI2_FUNNEL_DCORE3_TPC3_EML, + GAUDI2_FUNNEL_DCORE3_TPC4_EML, + GAUDI2_FUNNEL_DCORE3_TPC5_EML, + GAUDI2_FUNNEL_DCORE0_XFT, + GAUDI2_FUNNEL_DCORE0_TFT0, + GAUDI2_FUNNEL_DCORE0_TFT1, + GAUDI2_FUNNEL_DCORE0_TFT2, + GAUDI2_FUNNEL_DCORE0_RTR0, + GAUDI2_FUNNEL_DCORE0_RTR1, + GAUDI2_FUNNEL_DCORE0_RTR2, + GAUDI2_FUNNEL_DCORE0_RTR3, + GAUDI2_FUNNEL_DCORE0_RTR4, + GAUDI2_FUNNEL_DCORE0_MIF0, + GAUDI2_FUNNEL_DCORE0_RTR5, + GAUDI2_FUNNEL_DCORE0_MIF1, + GAUDI2_FUNNEL_DCORE0_RTR6, + GAUDI2_FUNNEL_DCORE0_MIF2, + GAUDI2_FUNNEL_DCORE0_RTR7, + GAUDI2_FUNNEL_DCORE0_MIF3, + GAUDI2_FUNNEL_DCORE1_XFT, + GAUDI2_FUNNEL_DCORE1_TFT0, + GAUDI2_FUNNEL_DCORE1_TFT1, + GAUDI2_FUNNEL_DCORE1_TFT2, + GAUDI2_FUNNEL_DCORE1_RTR0, + GAUDI2_FUNNEL_DCORE1_MIF0, + GAUDI2_FUNNEL_DCORE1_RTR1, + GAUDI2_FUNNEL_DCORE1_MIF1, + GAUDI2_FUNNEL_DCORE1_RTR2, + GAUDI2_FUNNEL_DCORE1_MIF2, + GAUDI2_FUNNEL_DCORE1_RTR3, + GAUDI2_FUNNEL_DCORE1_MIF3, + GAUDI2_FUNNEL_DCORE1_RTR4, + GAUDI2_FUNNEL_DCORE1_RTR5, + GAUDI2_FUNNEL_DCORE1_RTR6, + GAUDI2_FUNNEL_DCORE1_RTR7, + GAUDI2_FUNNEL_DCORE2_XFT, + GAUDI2_FUNNEL_DCORE2_TFT0, + GAUDI2_FUNNEL_DCORE2_TFT1, + GAUDI2_FUNNEL_DCORE2_TFT2, + GAUDI2_FUNNEL_DCORE2_RTR0, + GAUDI2_FUNNEL_DCORE2_RTR1, + GAUDI2_FUNNEL_DCORE2_RTR2, + GAUDI2_FUNNEL_DCORE2_RTR3, + GAUDI2_FUNNEL_DCORE2_RTR4, + GAUDI2_FUNNEL_DCORE2_MIF0, + GAUDI2_FUNNEL_DCORE2_RTR5, + GAUDI2_FUNNEL_DCORE2_MIF1, + GAUDI2_FUNNEL_DCORE2_RTR6, + GAUDI2_FUNNEL_DCORE2_MIF2, + GAUDI2_FUNNEL_DCORE2_RTR7, + GAUDI2_FUNNEL_DCORE2_MIF3, + GAUDI2_FUNNEL_DCORE3_XFT, + GAUDI2_FUNNEL_DCORE3_TFT0, + GAUDI2_FUNNEL_DCORE3_TFT1, + GAUDI2_FUNNEL_DCORE3_TFT2, + GAUDI2_FUNNEL_DCORE3_RTR0, + GAUDI2_FUNNEL_DCORE3_MIF0, + GAUDI2_FUNNEL_DCORE3_RTR1, + GAUDI2_FUNNEL_DCORE3_MIF1, + GAUDI2_FUNNEL_DCORE3_RTR2, + GAUDI2_FUNNEL_DCORE3_MIF2, + GAUDI2_FUNNEL_DCORE3_RTR3, + GAUDI2_FUNNEL_DCORE3_MIF3, + GAUDI2_FUNNEL_DCORE3_RTR4, + GAUDI2_FUNNEL_DCORE3_RTR5, + GAUDI2_FUNNEL_DCORE3_RTR6, + GAUDI2_FUNNEL_DCORE3_RTR7, + GAUDI2_FUNNEL_PSOC, + GAUDI2_FUNNEL_PSOC_ARC0, + GAUDI2_FUNNEL_PSOC_ARC1, + GAUDI2_FUNNEL_XDMA, + GAUDI2_FUNNEL_CPU, + GAUDI2_FUNNEL_PMMU, + GAUDI2_FUNNEL_PMMU_DEC, + GAUDI2_FUNNEL_DCORE0_XBAR_MID, + GAUDI2_FUNNEL_DCORE0_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE1_XBAR_MID, + GAUDI2_FUNNEL_DCORE1_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE2_XBAR_MID, + GAUDI2_FUNNEL_DCORE2_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE3_XBAR_MID, + GAUDI2_FUNNEL_DCORE3_XBAR_EDGE, + GAUDI2_FUNNEL_ARC_FARM, + GAUDI2_FUNNEL_HBM0_MC0, + GAUDI2_FUNNEL_HBM0_MC1, + GAUDI2_FUNNEL_HBM1_MC0, + GAUDI2_FUNNEL_HBM1_MC1, + GAUDI2_FUNNEL_HBM2_MC0, + GAUDI2_FUNNEL_HBM2_MC1, + GAUDI2_FUNNEL_HBM3_MC0, + GAUDI2_FUNNEL_HBM3_MC1, + GAUDI2_FUNNEL_HBM4_MC0, + GAUDI2_FUNNEL_HBM4_MC1, + GAUDI2_FUNNEL_HBM5_MC0, + GAUDI2_FUNNEL_HBM5_MC1, + GAUDI2_FUNNEL_NIC0_DBG_TX, + GAUDI2_FUNNEL_NIC0_DBG_NCH, + GAUDI2_FUNNEL_NIC1_DBG_TX, + GAUDI2_FUNNEL_NIC1_DBG_NCH, + GAUDI2_FUNNEL_NIC2_DBG_TX, + GAUDI2_FUNNEL_NIC2_DBG_NCH, + GAUDI2_FUNNEL_NIC3_DBG_TX, + GAUDI2_FUNNEL_NIC3_DBG_NCH, + GAUDI2_FUNNEL_NIC4_DBG_TX, + GAUDI2_FUNNEL_NIC4_DBG_NCH, + GAUDI2_FUNNEL_NIC5_DBG_TX, + GAUDI2_FUNNEL_NIC5_DBG_NCH, + GAUDI2_FUNNEL_NIC6_DBG_TX, + GAUDI2_FUNNEL_NIC6_DBG_NCH, + GAUDI2_FUNNEL_NIC7_DBG_TX, + GAUDI2_FUNNEL_NIC7_DBG_NCH, + GAUDI2_FUNNEL_NIC8_DBG_TX, + GAUDI2_FUNNEL_NIC8_DBG_NCH, + GAUDI2_FUNNEL_NIC9_DBG_TX, + GAUDI2_FUNNEL_NIC9_DBG_NCH, + GAUDI2_FUNNEL_NIC10_DBG_TX, + GAUDI2_FUNNEL_NIC10_DBG_NCH, + GAUDI2_FUNNEL_NIC11_DBG_TX, + GAUDI2_FUNNEL_NIC11_DBG_NCH, + GAUDI2_FUNNEL_LAST = GAUDI2_FUNNEL_NIC11_DBG_NCH +}; + +enum gaudi2_debug_bmon_regs_index { + GAUDI2_BMON_FIRST = 0, + GAUDI2_BMON_DCORE0_TPC0_EML_0 = GAUDI2_BMON_FIRST, + GAUDI2_BMON_DCORE0_TPC0_EML_1, + GAUDI2_BMON_DCORE0_TPC0_EML_2, + GAUDI2_BMON_DCORE0_TPC0_EML_3, + GAUDI2_BMON_DCORE0_TPC1_EML_0, + GAUDI2_BMON_DCORE0_TPC1_EML_1, + GAUDI2_BMON_DCORE0_TPC1_EML_2, + GAUDI2_BMON_DCORE0_TPC1_EML_3, + GAUDI2_BMON_DCORE0_TPC2_EML_0, + GAUDI2_BMON_DCORE0_TPC2_EML_1, + GAUDI2_BMON_DCORE0_TPC2_EML_2, + GAUDI2_BMON_DCORE0_TPC2_EML_3, + GAUDI2_BMON_DCORE0_TPC3_EML_0, + GAUDI2_BMON_DCORE0_TPC3_EML_1, + GAUDI2_BMON_DCORE0_TPC3_EML_2, + GAUDI2_BMON_DCORE0_TPC3_EML_3, + GAUDI2_BMON_DCORE0_TPC4_EML_0, + GAUDI2_BMON_DCORE0_TPC4_EML_1, + GAUDI2_BMON_DCORE0_TPC4_EML_2, + GAUDI2_BMON_DCORE0_TPC4_EML_3, + GAUDI2_BMON_DCORE0_TPC5_EML_0, + GAUDI2_BMON_DCORE0_TPC5_EML_1, + GAUDI2_BMON_DCORE0_TPC5_EML_2, + GAUDI2_BMON_DCORE0_TPC5_EML_3, + GAUDI2_BMON_DCORE0_TPC6_EML_0, + GAUDI2_BMON_DCORE0_TPC6_EML_1, + GAUDI2_BMON_DCORE0_TPC6_EML_2, + GAUDI2_BMON_DCORE0_TPC6_EML_3, + GAUDI2_BMON_DCORE1_TPC0_EML_0, + GAUDI2_BMON_DCORE1_TPC0_EML_1, + GAUDI2_BMON_DCORE1_TPC0_EML_2, + GAUDI2_BMON_DCORE1_TPC0_EML_3, + GAUDI2_BMON_DCORE1_TPC1_EML_0, + GAUDI2_BMON_DCORE1_TPC1_EML_1, + GAUDI2_BMON_DCORE1_TPC1_EML_2, + GAUDI2_BMON_DCORE1_TPC1_EML_3, + GAUDI2_BMON_DCORE1_TPC2_EML_0, + GAUDI2_BMON_DCORE1_TPC2_EML_1, + GAUDI2_BMON_DCORE1_TPC2_EML_2, + GAUDI2_BMON_DCORE1_TPC2_EML_3, + GAUDI2_BMON_DCORE1_TPC3_EML_0, + GAUDI2_BMON_DCORE1_TPC3_EML_1, + GAUDI2_BMON_DCORE1_TPC3_EML_2, + GAUDI2_BMON_DCORE1_TPC3_EML_3, + GAUDI2_BMON_DCORE1_TPC4_EML_0, + GAUDI2_BMON_DCORE1_TPC4_EML_1, + GAUDI2_BMON_DCORE1_TPC4_EML_2, + GAUDI2_BMON_DCORE1_TPC4_EML_3, + GAUDI2_BMON_DCORE1_TPC5_EML_0, + GAUDI2_BMON_DCORE1_TPC5_EML_1, + GAUDI2_BMON_DCORE1_TPC5_EML_2, + GAUDI2_BMON_DCORE1_TPC5_EML_3, + GAUDI2_BMON_DCORE2_TPC0_EML_0, + GAUDI2_BMON_DCORE2_TPC0_EML_1, + GAUDI2_BMON_DCORE2_TPC0_EML_2, + GAUDI2_BMON_DCORE2_TPC0_EML_3, + GAUDI2_BMON_DCORE2_TPC1_EML_0, + GAUDI2_BMON_DCORE2_TPC1_EML_1, + GAUDI2_BMON_DCORE2_TPC1_EML_2, + GAUDI2_BMON_DCORE2_TPC1_EML_3, + GAUDI2_BMON_DCORE2_TPC2_EML_0, + GAUDI2_BMON_DCORE2_TPC2_EML_1, + GAUDI2_BMON_DCORE2_TPC2_EML_2, + GAUDI2_BMON_DCORE2_TPC2_EML_3, + GAUDI2_BMON_DCORE2_TPC3_EML_0, + GAUDI2_BMON_DCORE2_TPC3_EML_1, + GAUDI2_BMON_DCORE2_TPC3_EML_2, + GAUDI2_BMON_DCORE2_TPC3_EML_3, + GAUDI2_BMON_DCORE2_TPC4_EML_0, + GAUDI2_BMON_DCORE2_TPC4_EML_1, + GAUDI2_BMON_DCORE2_TPC4_EML_2, + GAUDI2_BMON_DCORE2_TPC4_EML_3, + GAUDI2_BMON_DCORE2_TPC5_EML_0, + GAUDI2_BMON_DCORE2_TPC5_EML_1, + GAUDI2_BMON_DCORE2_TPC5_EML_2, + GAUDI2_BMON_DCORE2_TPC5_EML_3, + GAUDI2_BMON_DCORE3_TPC0_EML_0, + GAUDI2_BMON_DCORE3_TPC0_EML_1, + GAUDI2_BMON_DCORE3_TPC0_EML_2, + GAUDI2_BMON_DCORE3_TPC0_EML_3, + GAUDI2_BMON_DCORE3_TPC1_EML_0, + GAUDI2_BMON_DCORE3_TPC1_EML_1, + GAUDI2_BMON_DCORE3_TPC1_EML_2, + GAUDI2_BMON_DCORE3_TPC1_EML_3, + GAUDI2_BMON_DCORE3_TPC2_EML_0, + GAUDI2_BMON_DCORE3_TPC2_EML_1, + GAUDI2_BMON_DCORE3_TPC2_EML_2, + GAUDI2_BMON_DCORE3_TPC2_EML_3, + GAUDI2_BMON_DCORE3_TPC3_EML_0, + GAUDI2_BMON_DCORE3_TPC3_EML_1, + GAUDI2_BMON_DCORE3_TPC3_EML_2, + GAUDI2_BMON_DCORE3_TPC3_EML_3, + GAUDI2_BMON_DCORE3_TPC4_EML_0, + GAUDI2_BMON_DCORE3_TPC4_EML_1, + GAUDI2_BMON_DCORE3_TPC4_EML_2, + GAUDI2_BMON_DCORE3_TPC4_EML_3, + GAUDI2_BMON_DCORE3_TPC5_EML_0, + GAUDI2_BMON_DCORE3_TPC5_EML_1, + GAUDI2_BMON_DCORE3_TPC5_EML_2, + GAUDI2_BMON_DCORE3_TPC5_EML_3, + GAUDI2_BMON_DCORE0_HMMU0_0, + GAUDI2_BMON_DCORE0_HMMU0_1, + GAUDI2_BMON_DCORE0_HMMU0_3, + GAUDI2_BMON_DCORE0_HMMU0_2, + GAUDI2_BMON_DCORE0_HMMU0_4, + GAUDI2_BMON_DCORE0_HMMU1_0, + GAUDI2_BMON_DCORE0_HMMU1_1, + GAUDI2_BMON_DCORE0_HMMU1_3, + GAUDI2_BMON_DCORE0_HMMU1_2, + GAUDI2_BMON_DCORE0_HMMU1_4, + GAUDI2_BMON_DCORE0_HMMU2_0, + GAUDI2_BMON_DCORE0_HMMU2_1, + GAUDI2_BMON_DCORE0_HMMU2_3, + GAUDI2_BMON_DCORE0_HMMU2_2, + GAUDI2_BMON_DCORE0_HMMU2_4, + GAUDI2_BMON_DCORE0_HMMU3_0, + GAUDI2_BMON_DCORE0_HMMU3_1, + GAUDI2_BMON_DCORE0_HMMU3_3, + GAUDI2_BMON_DCORE0_HMMU3_2, + GAUDI2_BMON_DCORE0_HMMU3_4, + GAUDI2_BMON_DCORE0_MME_CTRL_0, + GAUDI2_BMON_DCORE0_MME_CTRL_1, + GAUDI2_BMON_DCORE0_MME_CTRL_2, + GAUDI2_BMON_DCORE0_MME_CTRL_3, + GAUDI2_BMON_DCORE0_MME_SBTE0_0, + GAUDI2_BMON_DCORE0_MME_SBTE1_0, + GAUDI2_BMON_DCORE0_MME_SBTE2_0, + GAUDI2_BMON_DCORE0_MME_SBTE3_0, + GAUDI2_BMON_DCORE0_MME_SBTE4_0, + GAUDI2_BMON_DCORE0_MME_ACC_0, + GAUDI2_BMON_DCORE0_MME_ACC_1, + GAUDI2_BMON_DCORE0_SM, + GAUDI2_BMON_DCORE0_SM_1, + GAUDI2_BMON_DCORE0_EDMA0_0, + GAUDI2_BMON_DCORE0_EDMA0_1, + GAUDI2_BMON_DCORE0_EDMA1_0, + GAUDI2_BMON_DCORE0_EDMA1_1, + GAUDI2_BMON_DCORE0_VDEC0_0, + GAUDI2_BMON_DCORE0_VDEC0_1, + GAUDI2_BMON_DCORE0_VDEC0_2, + GAUDI2_BMON_DCORE0_VDEC1_0, + GAUDI2_BMON_DCORE0_VDEC1_1, + GAUDI2_BMON_DCORE0_VDEC1_2, + GAUDI2_BMON_DCORE1_HMMU0_0, + GAUDI2_BMON_DCORE1_HMMU0_1, + GAUDI2_BMON_DCORE1_HMMU0_3, + GAUDI2_BMON_DCORE1_HMMU0_2, + GAUDI2_BMON_DCORE1_HMMU0_4, + GAUDI2_BMON_DCORE1_HMMU1_0, + GAUDI2_BMON_DCORE1_HMMU1_1, + GAUDI2_BMON_DCORE1_HMMU1_3, + GAUDI2_BMON_DCORE1_HMMU1_2, + GAUDI2_BMON_DCORE1_HMMU1_4, + GAUDI2_BMON_DCORE1_HMMU2_0, + GAUDI2_BMON_DCORE1_HMMU2_1, + GAUDI2_BMON_DCORE1_HMMU2_3, + GAUDI2_BMON_DCORE1_HMMU2_2, + GAUDI2_BMON_DCORE1_HMMU2_4, + GAUDI2_BMON_DCORE1_HMMU3_0, + GAUDI2_BMON_DCORE1_HMMU3_1, + GAUDI2_BMON_DCORE1_HMMU3_3, + GAUDI2_BMON_DCORE1_HMMU3_2, + GAUDI2_BMON_DCORE1_HMMU3_4, + GAUDI2_BMON_DCORE1_MME_CTRL_0, + GAUDI2_BMON_DCORE1_MME_CTRL_1, + GAUDI2_BMON_DCORE1_MME_CTRL_2, + GAUDI2_BMON_DCORE1_MME_CTRL_3, + GAUDI2_BMON_DCORE1_MME_SBTE0_0, + GAUDI2_BMON_DCORE1_MME_SBTE1_0, + GAUDI2_BMON_DCORE1_MME_SBTE2_0, + GAUDI2_BMON_DCORE1_MME_SBTE3_0, + GAUDI2_BMON_DCORE1_MME_SBTE4_0, + GAUDI2_BMON_DCORE1_MME_ACC_0, + GAUDI2_BMON_DCORE1_MME_ACC_1, + GAUDI2_BMON_DCORE1_SM, + GAUDI2_BMON_DCORE1_SM_1, + GAUDI2_BMON_DCORE1_EDMA0_0, + GAUDI2_BMON_DCORE1_EDMA0_1, + GAUDI2_BMON_DCORE1_EDMA1_0, + GAUDI2_BMON_DCORE1_EDMA1_1, + GAUDI2_BMON_DCORE1_VDEC0_0, + GAUDI2_BMON_DCORE1_VDEC0_1, + GAUDI2_BMON_DCORE1_VDEC0_2, + GAUDI2_BMON_DCORE1_VDEC1_0, + GAUDI2_BMON_DCORE1_VDEC1_1, + GAUDI2_BMON_DCORE1_VDEC1_2, + GAUDI2_BMON_DCORE2_HMMU0_0, + GAUDI2_BMON_DCORE2_HMMU0_1, + GAUDI2_BMON_DCORE2_HMMU0_3, + GAUDI2_BMON_DCORE2_HMMU0_2, + GAUDI2_BMON_DCORE2_HMMU0_4, + GAUDI2_BMON_DCORE2_HMMU1_0, + GAUDI2_BMON_DCORE2_HMMU1_1, + GAUDI2_BMON_DCORE2_HMMU1_3, + GAUDI2_BMON_DCORE2_HMMU1_2, + GAUDI2_BMON_DCORE2_HMMU1_4, + GAUDI2_BMON_DCORE2_HMMU2_0, + GAUDI2_BMON_DCORE2_HMMU2_1, + GAUDI2_BMON_DCORE2_HMMU2_3, + GAUDI2_BMON_DCORE2_HMMU2_2, + GAUDI2_BMON_DCORE2_HMMU2_4, + GAUDI2_BMON_DCORE2_HMMU3_0, + GAUDI2_BMON_DCORE2_HMMU3_1, + GAUDI2_BMON_DCORE2_HMMU3_3, + GAUDI2_BMON_DCORE2_HMMU3_2, + GAUDI2_BMON_DCORE2_HMMU3_4, + GAUDI2_BMON_DCORE2_MME_CTRL_0, + GAUDI2_BMON_DCORE2_MME_CTRL_1, + GAUDI2_BMON_DCORE2_MME_CTRL_2, + GAUDI2_BMON_DCORE2_MME_CTRL_3, + GAUDI2_BMON_DCORE2_MME_SBTE0_0, + GAUDI2_BMON_DCORE2_MME_SBTE1_0, + GAUDI2_BMON_DCORE2_MME_SBTE2_0, + GAUDI2_BMON_DCORE2_MME_SBTE3_0, + GAUDI2_BMON_DCORE2_MME_SBTE4_0, + GAUDI2_BMON_DCORE2_MME_ACC_0, + GAUDI2_BMON_DCORE2_MME_ACC_1, + GAUDI2_BMON_DCORE2_SM, + GAUDI2_BMON_DCORE2_SM_1, + GAUDI2_BMON_DCORE2_EDMA0_0, + GAUDI2_BMON_DCORE2_EDMA0_1, + GAUDI2_BMON_DCORE2_EDMA1_0, + GAUDI2_BMON_DCORE2_EDMA1_1, + GAUDI2_BMON_DCORE2_VDEC0_0, + GAUDI2_BMON_DCORE2_VDEC0_1, + GAUDI2_BMON_DCORE2_VDEC0_2, + GAUDI2_BMON_DCORE2_VDEC1_0, + GAUDI2_BMON_DCORE2_VDEC1_1, + GAUDI2_BMON_DCORE2_VDEC1_2, + GAUDI2_BMON_DCORE3_HMMU0_0, + GAUDI2_BMON_DCORE3_HMMU0_1, + GAUDI2_BMON_DCORE3_HMMU0_3, + GAUDI2_BMON_DCORE3_HMMU0_2, + GAUDI2_BMON_DCORE3_HMMU0_4, + GAUDI2_BMON_DCORE3_HMMU1_0, + GAUDI2_BMON_DCORE3_HMMU1_1, + GAUDI2_BMON_DCORE3_HMMU1_3, + GAUDI2_BMON_DCORE3_HMMU1_2, + GAUDI2_BMON_DCORE3_HMMU1_4, + GAUDI2_BMON_DCORE3_HMMU2_0, + GAUDI2_BMON_DCORE3_HMMU2_1, + GAUDI2_BMON_DCORE3_HMMU2_3, + GAUDI2_BMON_DCORE3_HMMU2_2, + GAUDI2_BMON_DCORE3_HMMU2_4, + GAUDI2_BMON_DCORE3_HMMU3_0, + GAUDI2_BMON_DCORE3_HMMU3_1, + GAUDI2_BMON_DCORE3_HMMU3_3, + GAUDI2_BMON_DCORE3_HMMU3_2, + GAUDI2_BMON_DCORE3_HMMU3_4, + GAUDI2_BMON_DCORE3_MME_CTRL_0, + GAUDI2_BMON_DCORE3_MME_CTRL_1, + GAUDI2_BMON_DCORE3_MME_CTRL_2, + GAUDI2_BMON_DCORE3_MME_CTRL_3, + GAUDI2_BMON_DCORE3_MME_SBTE0_0, + GAUDI2_BMON_DCORE3_MME_SBTE1_0, + GAUDI2_BMON_DCORE3_MME_SBTE2_0, + GAUDI2_BMON_DCORE3_MME_SBTE3_0, + GAUDI2_BMON_DCORE3_MME_SBTE4_0, + GAUDI2_BMON_DCORE3_MME_ACC_0, + GAUDI2_BMON_DCORE3_MME_ACC_1, + GAUDI2_BMON_DCORE3_SM, + GAUDI2_BMON_DCORE3_SM_1, + GAUDI2_BMON_DCORE3_EDMA0_0, + GAUDI2_BMON_DCORE3_EDMA0_1, + GAUDI2_BMON_DCORE3_EDMA1_0, + GAUDI2_BMON_DCORE3_EDMA1_1, + GAUDI2_BMON_DCORE3_VDEC0_0, + GAUDI2_BMON_DCORE3_VDEC0_1, + GAUDI2_BMON_DCORE3_VDEC0_2, + GAUDI2_BMON_DCORE3_VDEC1_0, + GAUDI2_BMON_DCORE3_VDEC1_1, + GAUDI2_BMON_DCORE3_VDEC1_2, + GAUDI2_BMON_PCIE_MSTR_WR, + GAUDI2_BMON_PCIE_MSTR_RD, + GAUDI2_BMON_PCIE_SLV_WR, + GAUDI2_BMON_PCIE_SLV_RD, + GAUDI2_BMON_PSOC_ARC0_0, + GAUDI2_BMON_PSOC_ARC0_1, + GAUDI2_BMON_PSOC_ARC1_0, + GAUDI2_BMON_PSOC_ARC1_1, + GAUDI2_BMON_PDMA0_0, + GAUDI2_BMON_PDMA0_1, + GAUDI2_BMON_PDMA1_0, + GAUDI2_BMON_PDMA1_1, + GAUDI2_BMON_CPU_WR, + GAUDI2_BMON_CPU_RD, + GAUDI2_BMON_PMMU_0, + GAUDI2_BMON_PMMU_1, + GAUDI2_BMON_PMMU_2, + GAUDI2_BMON_PMMU_3, + GAUDI2_BMON_PMMU_4, + GAUDI2_BMON_ROT0_0, + GAUDI2_BMON_ROT0_1, + GAUDI2_BMON_ROT0_2, + GAUDI2_BMON_ROT0_3, + GAUDI2_BMON_ROT1_0, + GAUDI2_BMON_ROT1_1, + GAUDI2_BMON_ROT1_2, + GAUDI2_BMON_ROT1_3, + GAUDI2_BMON_ARC_FARM_0, + GAUDI2_BMON_ARC_FARM_1, + GAUDI2_BMON_ARC_FARM_2, + GAUDI2_BMON_ARC_FARM_3, + GAUDI2_BMON_KDMA_0, + GAUDI2_BMON_KDMA_1, + GAUDI2_BMON_KDMA_2, + GAUDI2_BMON_KDMA_3, + GAUDI2_BMON_PCIE_VDEC0_0, + GAUDI2_BMON_PCIE_VDEC0_1, + GAUDI2_BMON_PCIE_VDEC0_2, + GAUDI2_BMON_PCIE_VDEC1_0, + GAUDI2_BMON_PCIE_VDEC1_1, + GAUDI2_BMON_PCIE_VDEC1_2, + GAUDI2_BMON_NIC0_DBG_0_0, + GAUDI2_BMON_NIC0_DBG_1_0, + GAUDI2_BMON_NIC0_DBG_2_0, + GAUDI2_BMON_NIC0_DBG_0_1, + GAUDI2_BMON_NIC0_DBG_1_1, + GAUDI2_BMON_NIC0_DBG_2_1, + GAUDI2_BMON_NIC1_DBG_0_0, + GAUDI2_BMON_NIC1_DBG_1_0, + GAUDI2_BMON_NIC1_DBG_2_0, + GAUDI2_BMON_NIC1_DBG_0_1, + GAUDI2_BMON_NIC1_DBG_1_1, + GAUDI2_BMON_NIC1_DBG_2_1, + GAUDI2_BMON_NIC2_DBG_0_0, + GAUDI2_BMON_NIC2_DBG_1_0, + GAUDI2_BMON_NIC2_DBG_2_0, + GAUDI2_BMON_NIC2_DBG_0_1, + GAUDI2_BMON_NIC2_DBG_1_1, + GAUDI2_BMON_NIC2_DBG_2_1, + GAUDI2_BMON_NIC3_DBG_0_0, + GAUDI2_BMON_NIC3_DBG_1_0, + GAUDI2_BMON_NIC3_DBG_2_0, + GAUDI2_BMON_NIC3_DBG_0_1, + GAUDI2_BMON_NIC3_DBG_1_1, + GAUDI2_BMON_NIC3_DBG_2_1, + GAUDI2_BMON_NIC4_DBG_0_0, + GAUDI2_BMON_NIC4_DBG_1_0, + GAUDI2_BMON_NIC4_DBG_2_0, + GAUDI2_BMON_NIC4_DBG_0_1, + GAUDI2_BMON_NIC4_DBG_1_1, + GAUDI2_BMON_NIC4_DBG_2_1, + GAUDI2_BMON_NIC5_DBG_0_0, + GAUDI2_BMON_NIC5_DBG_1_0, + GAUDI2_BMON_NIC5_DBG_2_0, + GAUDI2_BMON_NIC5_DBG_0_1, + GAUDI2_BMON_NIC5_DBG_1_1, + GAUDI2_BMON_NIC5_DBG_2_1, + GAUDI2_BMON_NIC6_DBG_0_0, + GAUDI2_BMON_NIC6_DBG_1_0, + GAUDI2_BMON_NIC6_DBG_2_0, + GAUDI2_BMON_NIC6_DBG_0_1, + GAUDI2_BMON_NIC6_DBG_1_1, + GAUDI2_BMON_NIC6_DBG_2_1, + GAUDI2_BMON_NIC7_DBG_0_0, + GAUDI2_BMON_NIC7_DBG_1_0, + GAUDI2_BMON_NIC7_DBG_2_0, + GAUDI2_BMON_NIC7_DBG_0_1, + GAUDI2_BMON_NIC7_DBG_1_1, + GAUDI2_BMON_NIC7_DBG_2_1, + GAUDI2_BMON_NIC8_DBG_0_0, + GAUDI2_BMON_NIC8_DBG_1_0, + GAUDI2_BMON_NIC8_DBG_2_0, + GAUDI2_BMON_NIC8_DBG_0_1, + GAUDI2_BMON_NIC8_DBG_1_1, + GAUDI2_BMON_NIC8_DBG_2_1, + GAUDI2_BMON_NIC9_DBG_0_0, + GAUDI2_BMON_NIC9_DBG_1_0, + GAUDI2_BMON_NIC9_DBG_2_0, + GAUDI2_BMON_NIC9_DBG_0_1, + GAUDI2_BMON_NIC9_DBG_1_1, + GAUDI2_BMON_NIC9_DBG_2_1, + GAUDI2_BMON_NIC10_DBG_0_0, + GAUDI2_BMON_NIC10_DBG_1_0, + GAUDI2_BMON_NIC10_DBG_2_0, + GAUDI2_BMON_NIC10_DBG_0_1, + GAUDI2_BMON_NIC10_DBG_1_1, + GAUDI2_BMON_NIC10_DBG_2_1, + GAUDI2_BMON_NIC11_DBG_0_0, + GAUDI2_BMON_NIC11_DBG_1_0, + GAUDI2_BMON_NIC11_DBG_2_0, + GAUDI2_BMON_NIC11_DBG_0_1, + GAUDI2_BMON_NIC11_DBG_1_1, + GAUDI2_BMON_NIC11_DBG_2_1, + GAUDI2_BMON_LAST = GAUDI2_BMON_NIC11_DBG_2_1 +}; + +enum gaudi2_debug_spmu_regs_index { + GAUDI2_SPMU_FIRST = 0, + GAUDI2_SPMU_DCORE0_TPC0_EML = GAUDI2_SPMU_FIRST, + GAUDI2_SPMU_DCORE0_TPC1_EML, + GAUDI2_SPMU_DCORE0_TPC2_EML, + GAUDI2_SPMU_DCORE0_TPC3_EML, + GAUDI2_SPMU_DCORE0_TPC4_EML, + GAUDI2_SPMU_DCORE0_TPC5_EML, + GAUDI2_SPMU_DCORE0_TPC6_EML, + GAUDI2_SPMU_DCORE1_TPC0_EML, + GAUDI2_SPMU_DCORE1_TPC1_EML, + GAUDI2_SPMU_DCORE1_TPC2_EML, + GAUDI2_SPMU_DCORE1_TPC3_EML, + GAUDI2_SPMU_DCORE1_TPC4_EML, + GAUDI2_SPMU_DCORE1_TPC5_EML, + GAUDI2_SPMU_DCORE2_TPC0_EML, + GAUDI2_SPMU_DCORE2_TPC1_EML, + GAUDI2_SPMU_DCORE2_TPC2_EML, + GAUDI2_SPMU_DCORE2_TPC3_EML, + GAUDI2_SPMU_DCORE2_TPC4_EML, + GAUDI2_SPMU_DCORE2_TPC5_EML, + GAUDI2_SPMU_DCORE3_TPC0_EML, + GAUDI2_SPMU_DCORE3_TPC1_EML, + GAUDI2_SPMU_DCORE3_TPC2_EML, + GAUDI2_SPMU_DCORE3_TPC3_EML, + GAUDI2_SPMU_DCORE3_TPC4_EML, + GAUDI2_SPMU_DCORE3_TPC5_EML, + GAUDI2_SPMU_DCORE0_HMMU0_CS, + GAUDI2_SPMU_DCORE0_HMMU1_CS, + GAUDI2_SPMU_DCORE0_HMMU2_CS, + GAUDI2_SPMU_DCORE0_HMMU3_CS, + GAUDI2_SPMU_DCORE0_MME_CTRL, + GAUDI2_SPMU_DCORE0_MME_SBTE0, + GAUDI2_SPMU_DCORE0_MME_SBTE1, + GAUDI2_SPMU_DCORE0_MME_SBTE2, + GAUDI2_SPMU_DCORE0_MME_SBTE3, + GAUDI2_SPMU_DCORE0_MME_SBTE4, + GAUDI2_SPMU_DCORE0_MME_ACC, + GAUDI2_SPMU_DCORE0_SM, + GAUDI2_SPMU_DCORE0_EDMA0_CS, + GAUDI2_SPMU_DCORE0_EDMA1_CS, + GAUDI2_SPMU_DCORE0_VDEC0_CS, + GAUDI2_SPMU_DCORE0_VDEC1_CS, + GAUDI2_SPMU_DCORE1_HMMU0_CS, + GAUDI2_SPMU_DCORE1_HMMU1_CS, + GAUDI2_SPMU_DCORE1_HMMU2_CS, + GAUDI2_SPMU_DCORE1_HMMU3_CS, + GAUDI2_SPMU_DCORE1_MME_CTRL, + GAUDI2_SPMU_DCORE1_MME_SBTE0, + GAUDI2_SPMU_DCORE1_MME_SBTE1, + GAUDI2_SPMU_DCORE1_MME_SBTE2, + GAUDI2_SPMU_DCORE1_MME_SBTE3, + GAUDI2_SPMU_DCORE1_MME_SBTE4, + GAUDI2_SPMU_DCORE1_MME_ACC, + GAUDI2_SPMU_DCORE1_SM, + GAUDI2_SPMU_DCORE1_EDMA0_CS, + GAUDI2_SPMU_DCORE1_EDMA1_CS, + GAUDI2_SPMU_DCORE1_VDEC0_CS, + GAUDI2_SPMU_DCORE1_VDEC1_CS, + GAUDI2_SPMU_DCORE2_HMMU0_CS, + GAUDI2_SPMU_DCORE2_HMMU1_CS, + GAUDI2_SPMU_DCORE2_HMMU2_CS, + GAUDI2_SPMU_DCORE2_HMMU3_CS, + GAUDI2_SPMU_DCORE2_MME_CTRL, + GAUDI2_SPMU_DCORE2_MME_SBTE0, + GAUDI2_SPMU_DCORE2_MME_SBTE1, + GAUDI2_SPMU_DCORE2_MME_SBTE2, + GAUDI2_SPMU_DCORE2_MME_SBTE3, + GAUDI2_SPMU_DCORE2_MME_SBTE4, + GAUDI2_SPMU_DCORE2_MME_ACC, + GAUDI2_SPMU_DCORE2_SM, + GAUDI2_SPMU_DCORE2_EDMA0_CS, + GAUDI2_SPMU_DCORE2_EDMA1_CS, + GAUDI2_SPMU_DCORE2_VDEC0_CS, + GAUDI2_SPMU_DCORE2_VDEC1_CS, + GAUDI2_SPMU_DCORE3_HMMU0_CS, + GAUDI2_SPMU_DCORE3_HMMU1_CS, + GAUDI2_SPMU_DCORE3_HMMU2_CS, + GAUDI2_SPMU_DCORE3_HMMU3_CS, + GAUDI2_SPMU_DCORE3_MME_CTRL, + GAUDI2_SPMU_DCORE3_MME_SBTE0, + GAUDI2_SPMU_DCORE3_MME_SBTE1, + GAUDI2_SPMU_DCORE3_MME_SBTE2, + GAUDI2_SPMU_DCORE3_MME_SBTE3, + GAUDI2_SPMU_DCORE3_MME_SBTE4, + GAUDI2_SPMU_DCORE3_MME_ACC, + GAUDI2_SPMU_DCORE3_SM, + GAUDI2_SPMU_DCORE3_EDMA0_CS, + GAUDI2_SPMU_DCORE3_EDMA1_CS, + GAUDI2_SPMU_DCORE3_VDEC0_CS, + GAUDI2_SPMU_DCORE3_VDEC1_CS, + GAUDI2_SPMU_PCIE, + GAUDI2_SPMU_PSOC_ARC0_CS, + GAUDI2_SPMU_PSOC_ARC1_CS, + GAUDI2_SPMU_PDMA0_CS, + GAUDI2_SPMU_PDMA1_CS, + GAUDI2_SPMU_PMMU_CS, + GAUDI2_SPMU_ROT0_CS, + GAUDI2_SPMU_ROT1_CS, + GAUDI2_SPMU_ARC_FARM_CS, + GAUDI2_SPMU_KDMA_CS, + GAUDI2_SPMU_PCIE_VDEC0_CS, + GAUDI2_SPMU_PCIE_VDEC1_CS, + GAUDI2_SPMU_HBM0_MC0_CS, + GAUDI2_SPMU_HBM0_MC1_CS, + GAUDI2_SPMU_HBM1_MC0_CS, + GAUDI2_SPMU_HBM1_MC1_CS, + GAUDI2_SPMU_HBM2_MC0_CS, + GAUDI2_SPMU_HBM2_MC1_CS, + GAUDI2_SPMU_HBM3_MC0_CS, + GAUDI2_SPMU_HBM3_MC1_CS, + GAUDI2_SPMU_HBM4_MC0_CS, + GAUDI2_SPMU_HBM4_MC1_CS, + GAUDI2_SPMU_HBM5_MC0_CS, + GAUDI2_SPMU_HBM5_MC1_CS, + GAUDI2_SPMU_NIC0_DBG_0, + GAUDI2_SPMU_NIC0_DBG_1, + GAUDI2_SPMU_NIC1_DBG_0, + GAUDI2_SPMU_NIC1_DBG_1, + GAUDI2_SPMU_NIC2_DBG_0, + GAUDI2_SPMU_NIC2_DBG_1, + GAUDI2_SPMU_NIC3_DBG_0, + GAUDI2_SPMU_NIC3_DBG_1, + GAUDI2_SPMU_NIC4_DBG_0, + GAUDI2_SPMU_NIC4_DBG_1, + GAUDI2_SPMU_NIC5_DBG_0, + GAUDI2_SPMU_NIC5_DBG_1, + GAUDI2_SPMU_NIC6_DBG_0, + GAUDI2_SPMU_NIC6_DBG_1, + GAUDI2_SPMU_NIC7_DBG_0, + GAUDI2_SPMU_NIC7_DBG_1, + GAUDI2_SPMU_NIC8_DBG_0, + GAUDI2_SPMU_NIC8_DBG_1, + GAUDI2_SPMU_NIC9_DBG_0, + GAUDI2_SPMU_NIC9_DBG_1, + GAUDI2_SPMU_NIC10_DBG_0, + GAUDI2_SPMU_NIC10_DBG_1, + GAUDI2_SPMU_NIC11_DBG_0, + GAUDI2_SPMU_NIC11_DBG_1, + GAUDI2_SPMU_LAST = GAUDI2_SPMU_NIC11_DBG_1 +}; + +#endif /* GAUDI2_CORESIGHT_H */ -- cgit v1.2.3