From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/peci/controller/Kconfig | 18 + drivers/peci/controller/Makefile | 3 + drivers/peci/controller/peci-aspeed.c | 599 ++++++++++++++++++++++++++++++++++ 3 files changed, 620 insertions(+) create mode 100644 drivers/peci/controller/Kconfig create mode 100644 drivers/peci/controller/Makefile create mode 100644 drivers/peci/controller/peci-aspeed.c (limited to 'drivers/peci/controller') diff --git a/drivers/peci/controller/Kconfig b/drivers/peci/controller/Kconfig new file mode 100644 index 000000000..2fc5e2abb --- /dev/null +++ b/drivers/peci/controller/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PECI_ASPEED + tristate "ASPEED PECI support" + depends on ARCH_ASPEED || COMPILE_TEST + depends on OF + depends on HAS_IOMEM + depends on COMMON_CLK + help + This option enables PECI controller driver for ASPEED AST2400, + AST2500 and AST2600 SoCs. It allows BMC to discover devices + connected to it, and communicate with them using PECI protocol. + + Say Y here if your system runs on ASPEED SoC and you are using it + as BMC for Intel platform. + + This driver can also be built as a module. If so, the module will + be called peci-aspeed. diff --git a/drivers/peci/controller/Makefile b/drivers/peci/controller/Makefile new file mode 100644 index 000000000..022c28ef1 --- /dev/null +++ b/drivers/peci/controller/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_PECI_ASPEED) += peci-aspeed.o diff --git a/drivers/peci/controller/peci-aspeed.c b/drivers/peci/controller/peci-aspeed.c new file mode 100644 index 000000000..731c5d8f7 --- /dev/null +++ b/drivers/peci/controller/peci-aspeed.c @@ -0,0 +1,599 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2012-2017 ASPEED Technology Inc. +// Copyright (c) 2018-2021 Intel Corporation + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* ASPEED PECI Registers */ +/* Control Register */ +#define ASPEED_PECI_CTRL 0x00 +#define ASPEED_PECI_CTRL_SAMPLING_MASK GENMASK(19, 16) +#define ASPEED_PECI_CTRL_RD_MODE_MASK GENMASK(13, 12) +#define ASPEED_PECI_CTRL_RD_MODE_DBG BIT(13) +#define ASPEED_PECI_CTRL_RD_MODE_COUNT BIT(12) +#define ASPEED_PECI_CTRL_CLK_SRC_HCLK BIT(11) +#define ASPEED_PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8) +#define ASPEED_PECI_CTRL_INVERT_OUT BIT(7) +#define ASPEED_PECI_CTRL_INVERT_IN BIT(6) +#define ASPEED_PECI_CTRL_BUS_CONTENTION_EN BIT(5) +#define ASPEED_PECI_CTRL_PECI_EN BIT(4) +#define ASPEED_PECI_CTRL_PECI_CLK_EN BIT(0) + +/* Timing Negotiation Register */ +#define ASPEED_PECI_TIMING_NEGOTIATION 0x04 +#define ASPEED_PECI_T_NEGO_MSG_MASK GENMASK(15, 8) +#define ASPEED_PECI_T_NEGO_ADDR_MASK GENMASK(7, 0) + +/* Command Register */ +#define ASPEED_PECI_CMD 0x08 +#define ASPEED_PECI_CMD_PIN_MONITORING BIT(31) +#define ASPEED_PECI_CMD_STS_MASK GENMASK(27, 24) +#define ASPEED_PECI_CMD_STS_ADDR_T_NEGO 0x3 +#define ASPEED_PECI_CMD_IDLE_MASK \ + (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MONITORING) +#define ASPEED_PECI_CMD_FIRE BIT(0) + +/* Read/Write Length Register */ +#define ASPEED_PECI_RW_LENGTH 0x0c +#define ASPEED_PECI_AW_FCS_EN BIT(31) +#define ASPEED_PECI_RD_LEN_MASK GENMASK(23, 16) +#define ASPEED_PECI_WR_LEN_MASK GENMASK(15, 8) +#define ASPEED_PECI_TARGET_ADDR_MASK GENMASK(7, 0) + +/* Expected FCS Data Register */ +#define ASPEED_PECI_EXPECTED_FCS 0x10 +#define ASPEED_PECI_EXPECTED_RD_FCS_MASK GENMASK(23, 16) +#define ASPEED_PECI_EXPECTED_AW_FCS_AUTO_MASK GENMASK(15, 8) +#define ASPEED_PECI_EXPECTED_WR_FCS_MASK GENMASK(7, 0) + +/* Captured FCS Data Register */ +#define ASPEED_PECI_CAPTURED_FCS 0x14 +#define ASPEED_PECI_CAPTURED_RD_FCS_MASK GENMASK(23, 16) +#define ASPEED_PECI_CAPTURED_WR_FCS_MASK GENMASK(7, 0) + +/* Interrupt Register */ +#define ASPEED_PECI_INT_CTRL 0x18 +#define ASPEED_PECI_TIMING_NEGO_SEL_MASK GENMASK(31, 30) +#define ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO 0 +#define ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO 1 +#define ASPEED_PECI_MESSAGE_NEGO 2 +#define ASPEED_PECI_INT_MASK GENMASK(4, 0) +#define ASPEED_PECI_INT_BUS_TIMEOUT BIT(4) +#define ASPEED_PECI_INT_BUS_CONTENTION BIT(3) +#define ASPEED_PECI_INT_WR_FCS_BAD BIT(2) +#define ASPEED_PECI_INT_WR_FCS_ABORT BIT(1) +#define ASPEED_PECI_INT_CMD_DONE BIT(0) + +/* Interrupt Status Register */ +#define ASPEED_PECI_INT_STS 0x1c +#define ASPEED_PECI_INT_TIMING_RESULT_MASK GENMASK(29, 16) + /* bits[4..0]: Same bit fields in the 'Interrupt Register' */ + +/* Rx/Tx Data Buffer Registers */ +#define ASPEED_PECI_WR_DATA0 0x20 +#define ASPEED_PECI_WR_DATA1 0x24 +#define ASPEED_PECI_WR_DATA2 0x28 +#define ASPEED_PECI_WR_DATA3 0x2c +#define ASPEED_PECI_RD_DATA0 0x30 +#define ASPEED_PECI_RD_DATA1 0x34 +#define ASPEED_PECI_RD_DATA2 0x38 +#define ASPEED_PECI_RD_DATA3 0x3c +#define ASPEED_PECI_WR_DATA4 0x40 +#define ASPEED_PECI_WR_DATA5 0x44 +#define ASPEED_PECI_WR_DATA6 0x48 +#define ASPEED_PECI_WR_DATA7 0x4c +#define ASPEED_PECI_RD_DATA4 0x50 +#define ASPEED_PECI_RD_DATA5 0x54 +#define ASPEED_PECI_RD_DATA6 0x58 +#define ASPEED_PECI_RD_DATA7 0x5c +#define ASPEED_PECI_DATA_BUF_SIZE_MAX 32 + +/* Timing Negotiation */ +#define ASPEED_PECI_CLK_FREQUENCY_MIN 2000 +#define ASPEED_PECI_CLK_FREQUENCY_DEFAULT 1000000 +#define ASPEED_PECI_CLK_FREQUENCY_MAX 2000000 +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT 8 +/* Timeout */ +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US (50 * USEC_PER_MSEC) +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US (10 * USEC_PER_MSEC) +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT 1000 +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX 1000 + +#define ASPEED_PECI_CLK_DIV1(msg_timing) (4 * (msg_timing) + 1) +#define ASPEED_PECI_CLK_DIV2(clk_div_exp) BIT(clk_div_exp) +#define ASPEED_PECI_CLK_DIV(msg_timing, clk_div_exp) \ + (4 * ASPEED_PECI_CLK_DIV1(msg_timing) * ASPEED_PECI_CLK_DIV2(clk_div_exp)) + +struct aspeed_peci { + struct peci_controller *controller; + struct device *dev; + void __iomem *base; + struct reset_control *rst; + int irq; + spinlock_t lock; /* to sync completion status handling */ + struct completion xfer_complete; + struct clk *clk; + u32 clk_frequency; + u32 status; + u32 cmd_timeout_ms; +}; + +struct clk_aspeed_peci { + struct clk_hw hw; + struct aspeed_peci *aspeed_peci; +}; + +static void aspeed_peci_controller_enable(struct aspeed_peci *priv) +{ + u32 val = readl(priv->base + ASPEED_PECI_CTRL); + + val |= ASPEED_PECI_CTRL_PECI_CLK_EN; + val |= ASPEED_PECI_CTRL_PECI_EN; + + writel(val, priv->base + ASPEED_PECI_CTRL); +} + +static void aspeed_peci_init_regs(struct aspeed_peci *priv) +{ + u32 val; + + /* Clear interrupts */ + writel(ASPEED_PECI_INT_MASK, priv->base + ASPEED_PECI_INT_STS); + + /* Set timing negotiation mode and enable interrupts */ + val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK, ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO); + val |= ASPEED_PECI_INT_MASK; + writel(val, priv->base + ASPEED_PECI_INT_CTRL); + + val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT); + writel(val, priv->base + ASPEED_PECI_CTRL); +} + +static int aspeed_peci_check_idle(struct aspeed_peci *priv) +{ + u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD); + int ret; + + /* + * Under normal circumstances, we expect to be idle here. + * In case there were any errors/timeouts that led to the situation + * where the hardware is not in idle state - we need to reset and + * reinitialize it to avoid potential controller hang. + */ + if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts)) { + ret = reset_control_assert(priv->rst); + if (ret) { + dev_err(priv->dev, "cannot assert reset control\n"); + return ret; + } + + ret = reset_control_deassert(priv->rst); + if (ret) { + dev_err(priv->dev, "cannot deassert reset control\n"); + return ret; + } + + aspeed_peci_init_regs(priv); + + ret = clk_set_rate(priv->clk, priv->clk_frequency); + if (ret < 0) { + dev_err(priv->dev, "cannot set clock frequency\n"); + return ret; + } + + aspeed_peci_controller_enable(priv); + } + + return readl_poll_timeout(priv->base + ASPEED_PECI_CMD, + cmd_sts, + !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK), + ASPEED_PECI_IDLE_CHECK_INTERVAL_US, + ASPEED_PECI_IDLE_CHECK_TIMEOUT_US); +} + +static int aspeed_peci_xfer(struct peci_controller *controller, + u8 addr, struct peci_request *req) +{ + struct aspeed_peci *priv = dev_get_drvdata(controller->dev.parent); + unsigned long timeout = msecs_to_jiffies(priv->cmd_timeout_ms); + u32 peci_head; + int ret, i; + + if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX || + req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX) + return -EINVAL; + + /* Check command sts and bus idle state */ + ret = aspeed_peci_check_idle(priv); + if (ret) + return ret; /* -ETIMEDOUT */ + + spin_lock_irq(&priv->lock); + reinit_completion(&priv->xfer_complete); + + peci_head = FIELD_PREP(ASPEED_PECI_TARGET_ADDR_MASK, addr) | + FIELD_PREP(ASPEED_PECI_WR_LEN_MASK, req->tx.len) | + FIELD_PREP(ASPEED_PECI_RD_LEN_MASK, req->rx.len); + + writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH); + + for (i = 0; i < req->tx.len; i += 4) { + u32 reg = (i < 16 ? ASPEED_PECI_WR_DATA0 : ASPEED_PECI_WR_DATA4) + i % 16; + + writel(get_unaligned_le32(&req->tx.buf[i]), priv->base + reg); + } + +#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) + dev_dbg(priv->dev, "HEAD : %#08x\n", peci_head); + print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req->tx.len); +#endif + + priv->status = 0; + writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD); + spin_unlock_irq(&priv->lock); + + ret = wait_for_completion_interruptible_timeout(&priv->xfer_complete, timeout); + if (ret < 0) + return ret; + + if (ret == 0) { + dev_dbg(priv->dev, "timeout waiting for a response\n"); + return -ETIMEDOUT; + } + + spin_lock_irq(&priv->lock); + + if (priv->status != ASPEED_PECI_INT_CMD_DONE) { + spin_unlock_irq(&priv->lock); + dev_dbg(priv->dev, "no valid response, status: %#02x\n", priv->status); + return -EIO; + } + + spin_unlock_irq(&priv->lock); + + /* + * We need to use dword reads for register access, make sure that the + * buffer size is multiple of 4-bytes. + */ + BUILD_BUG_ON(PECI_REQUEST_MAX_BUF_SIZE % 4); + + for (i = 0; i < req->rx.len; i += 4) { + u32 reg = (i < 16 ? ASPEED_PECI_RD_DATA0 : ASPEED_PECI_RD_DATA4) + i % 16; + u32 rx_data = readl(priv->base + reg); + + put_unaligned_le32(rx_data, &req->rx.buf[i]); + } + +#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) + print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req->rx.len); +#endif + return 0; +} + +static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg) +{ + struct aspeed_peci *priv = arg; + u32 status; + + spin_lock(&priv->lock); + status = readl(priv->base + ASPEED_PECI_INT_STS); + writel(status, priv->base + ASPEED_PECI_INT_STS); + priv->status |= (status & ASPEED_PECI_INT_MASK); + + /* + * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE bit + * set even in an error case. + */ + if (status & ASPEED_PECI_INT_CMD_DONE) + complete(&priv->xfer_complete); + + writel(0, priv->base + ASPEED_PECI_CMD); + + spin_unlock(&priv->lock); + + return IRQ_HANDLED; +} + +static void clk_aspeed_peci_find_div_values(unsigned long rate, int *msg_timing, int *clk_div_exp) +{ + unsigned long best_diff = ~0ul, diff; + int msg_timing_temp, clk_div_exp_temp, i, j; + + for (i = 1; i <= 255; i++) + for (j = 0; j < 8; j++) { + diff = abs(rate - ASPEED_PECI_CLK_DIV1(i) * ASPEED_PECI_CLK_DIV2(j)); + if (diff < best_diff) { + msg_timing_temp = i; + clk_div_exp_temp = j; + best_diff = diff; + } + } + + *msg_timing = msg_timing_temp; + *clk_div_exp = clk_div_exp_temp; +} + +static int clk_aspeed_peci_get_div(unsigned long rate, const unsigned long *prate) +{ + unsigned long this_rate = *prate / (4 * rate); + int msg_timing, clk_div_exp; + + clk_aspeed_peci_find_div_values(this_rate, &msg_timing, &clk_div_exp); + + return ASPEED_PECI_CLK_DIV(msg_timing, clk_div_exp); +} + +static int clk_aspeed_peci_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_aspeed_peci *peci_clk = container_of(hw, struct clk_aspeed_peci, hw); + struct aspeed_peci *aspeed_peci = peci_clk->aspeed_peci; + unsigned long this_rate = prate / (4 * rate); + int clk_div_exp, msg_timing; + u32 val; + + clk_aspeed_peci_find_div_values(this_rate, &msg_timing, &clk_div_exp); + + val = readl(aspeed_peci->base + ASPEED_PECI_CTRL); + val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, clk_div_exp); + writel(val, aspeed_peci->base + ASPEED_PECI_CTRL); + + val = FIELD_PREP(ASPEED_PECI_T_NEGO_MSG_MASK, msg_timing); + val |= FIELD_PREP(ASPEED_PECI_T_NEGO_ADDR_MASK, msg_timing); + writel(val, aspeed_peci->base + ASPEED_PECI_TIMING_NEGOTIATION); + + return 0; +} + +static long clk_aspeed_peci_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + int div = clk_aspeed_peci_get_div(rate, prate); + + return DIV_ROUND_UP_ULL(*prate, div); +} + +static unsigned long clk_aspeed_peci_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct clk_aspeed_peci *peci_clk = container_of(hw, struct clk_aspeed_peci, hw); + struct aspeed_peci *aspeed_peci = peci_clk->aspeed_peci; + int div, msg_timing, addr_timing, clk_div_exp; + u32 reg; + + reg = readl(aspeed_peci->base + ASPEED_PECI_TIMING_NEGOTIATION); + msg_timing = FIELD_GET(ASPEED_PECI_T_NEGO_MSG_MASK, reg); + addr_timing = FIELD_GET(ASPEED_PECI_T_NEGO_ADDR_MASK, reg); + + if (msg_timing != addr_timing) + return 0; + + reg = readl(aspeed_peci->base + ASPEED_PECI_CTRL); + clk_div_exp = FIELD_GET(ASPEED_PECI_CTRL_CLK_DIV_MASK, reg); + + div = ASPEED_PECI_CLK_DIV(msg_timing, clk_div_exp); + + return DIV_ROUND_UP_ULL(prate, div); +} + +static const struct clk_ops clk_aspeed_peci_ops = { + .set_rate = clk_aspeed_peci_set_rate, + .round_rate = clk_aspeed_peci_round_rate, + .recalc_rate = clk_aspeed_peci_recalc_rate, +}; + +/* + * PECI HW contains a clock divider which is a combination of: + * div0: 4 (fixed divider) + * div1: x + 1 + * div2: 1 << y + * In other words, out_clk = in_clk / (div0 * div1 * div2) + * The resulting frequency is used by PECI Controller to drive the PECI bus to + * negotiate optimal transfer rate. + */ +static struct clk *devm_aspeed_peci_register_clk_div(struct device *dev, struct clk *parent, + struct aspeed_peci *priv) +{ + struct clk_aspeed_peci *peci_clk; + struct clk_init_data init; + const char *parent_name; + char name[32]; + int ret; + + snprintf(name, sizeof(name), "%s_div", dev_name(dev)); + + parent_name = __clk_get_name(parent); + + init.ops = &clk_aspeed_peci_ops; + init.name = name; + init.parent_names = (const char* []) { parent_name }; + init.num_parents = 1; + init.flags = 0; + + peci_clk = devm_kzalloc(dev, sizeof(struct clk_aspeed_peci), GFP_KERNEL); + if (!peci_clk) + return ERR_PTR(-ENOMEM); + + peci_clk->hw.init = &init; + peci_clk->aspeed_peci = priv; + + ret = devm_clk_hw_register(dev, &peci_clk->hw); + if (ret) + return ERR_PTR(ret); + + return peci_clk->hw.clk; +} + +static void aspeed_peci_property_sanitize(struct device *dev, const char *propname, + u32 min, u32 max, u32 default_val, u32 *propval) +{ + u32 val; + int ret; + + ret = device_property_read_u32(dev, propname, &val); + if (ret) { + val = default_val; + } else if (val > max || val < min) { + dev_warn(dev, "invalid %s: %u, falling back to: %u\n", + propname, val, default_val); + + val = default_val; + } + + *propval = val; +} + +static void aspeed_peci_property_setup(struct aspeed_peci *priv) +{ + aspeed_peci_property_sanitize(priv->dev, "clock-frequency", + ASPEED_PECI_CLK_FREQUENCY_MIN, ASPEED_PECI_CLK_FREQUENCY_MAX, + ASPEED_PECI_CLK_FREQUENCY_DEFAULT, &priv->clk_frequency); + aspeed_peci_property_sanitize(priv->dev, "cmd-timeout-ms", + 1, ASPEED_PECI_CMD_TIMEOUT_MS_MAX, + ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT, &priv->cmd_timeout_ms); +} + +static struct peci_controller_ops aspeed_ops = { + .xfer = aspeed_peci_xfer, +}; + +static void aspeed_peci_reset_control_release(void *data) +{ + reset_control_assert(data); +} + +static int devm_aspeed_peci_reset_control_deassert(struct device *dev, struct reset_control *rst) +{ + int ret; + + ret = reset_control_deassert(rst); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, aspeed_peci_reset_control_release, rst); +} + +static void aspeed_peci_clk_release(void *data) +{ + clk_disable_unprepare(data); +} + +static int devm_aspeed_peci_clk_enable(struct device *dev, struct clk *clk) +{ + int ret; + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, aspeed_peci_clk_release, clk); +} + +static int aspeed_peci_probe(struct platform_device *pdev) +{ + struct peci_controller *controller; + struct aspeed_peci *priv; + struct clk *ref_clk; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + dev_set_drvdata(priv->dev, priv); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) + return priv->irq; + + ret = devm_request_irq(&pdev->dev, priv->irq, aspeed_peci_irq_handler, + 0, "peci-aspeed", priv); + if (ret) + return ret; + + init_completion(&priv->xfer_complete); + spin_lock_init(&priv->lock); + + priv->rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(priv->rst)) + return dev_err_probe(priv->dev, PTR_ERR(priv->rst), + "failed to get reset control\n"); + + ret = devm_aspeed_peci_reset_control_deassert(priv->dev, priv->rst); + if (ret) + return dev_err_probe(priv->dev, ret, "cannot deassert reset control\n"); + + aspeed_peci_property_setup(priv); + + aspeed_peci_init_regs(priv); + + ref_clk = devm_clk_get(priv->dev, NULL); + if (IS_ERR(ref_clk)) + return dev_err_probe(priv->dev, PTR_ERR(ref_clk), "failed to get ref clock\n"); + + priv->clk = devm_aspeed_peci_register_clk_div(priv->dev, ref_clk, priv); + if (IS_ERR(priv->clk)) + return dev_err_probe(priv->dev, PTR_ERR(priv->clk), "cannot register clock\n"); + + ret = clk_set_rate(priv->clk, priv->clk_frequency); + if (ret < 0) + return dev_err_probe(priv->dev, ret, "cannot set clock frequency\n"); + + ret = devm_aspeed_peci_clk_enable(priv->dev, priv->clk); + if (ret) + return dev_err_probe(priv->dev, ret, "failed to enable clock\n"); + + aspeed_peci_controller_enable(priv); + + controller = devm_peci_controller_add(priv->dev, &aspeed_ops); + if (IS_ERR(controller)) + return dev_err_probe(priv->dev, PTR_ERR(controller), + "failed to add aspeed peci controller\n"); + + priv->controller = controller; + + return 0; +} + +static const struct of_device_id aspeed_peci_of_table[] = { + { .compatible = "aspeed,ast2400-peci", }, + { .compatible = "aspeed,ast2500-peci", }, + { .compatible = "aspeed,ast2600-peci", }, + { } +}; +MODULE_DEVICE_TABLE(of, aspeed_peci_of_table); + +static struct platform_driver aspeed_peci_driver = { + .probe = aspeed_peci_probe, + .driver = { + .name = "peci-aspeed", + .of_match_table = aspeed_peci_of_table, + }, +}; +module_platform_driver(aspeed_peci_driver); + +MODULE_AUTHOR("Ryan Chen "); +MODULE_AUTHOR("Jae Hyun Yoo "); +MODULE_DESCRIPTION("ASPEED PECI driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(PECI); -- cgit v1.2.3