From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/phy/mscc/Kconfig | 12 + drivers/phy/mscc/Makefile | 6 + drivers/phy/mscc/phy-ocelot-serdes.c | 541 +++++++++++++++++++++++++++++++++++ 3 files changed, 559 insertions(+) create mode 100644 drivers/phy/mscc/Kconfig create mode 100644 drivers/phy/mscc/Makefile create mode 100644 drivers/phy/mscc/phy-ocelot-serdes.c (limited to 'drivers/phy/mscc') diff --git a/drivers/phy/mscc/Kconfig b/drivers/phy/mscc/Kconfig new file mode 100644 index 000000000..83be16d39 --- /dev/null +++ b/drivers/phy/mscc/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Microsemi devices +# + +config PHY_OCELOT_SERDES + tristate "SerDes PHY driver for Microsemi Ocelot" + select GENERIC_PHY + depends on OF + depends on MFD_SYSCON + help + Enable this for supporting SerDes muxing with Microsemi Ocelot. diff --git a/drivers/phy/mscc/Makefile b/drivers/phy/mscc/Makefile new file mode 100644 index 000000000..7bec61adb --- /dev/null +++ b/drivers/phy/mscc/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for the Microsemi phy drivers. +# + +obj-$(CONFIG_PHY_OCELOT_SERDES) := phy-ocelot-serdes.o diff --git a/drivers/phy/mscc/phy-ocelot-serdes.c b/drivers/phy/mscc/phy-ocelot-serdes.c new file mode 100644 index 000000000..76f596365 --- /dev/null +++ b/drivers/phy/mscc/phy-ocelot-serdes.c @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * SerDes PHY driver for Microsemi Ocelot + * + * Copyright (c) 2018 Microsemi + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct serdes_ctrl { + struct regmap *regs; + struct device *dev; + struct phy *phys[SERDES_MAX]; +}; + +struct serdes_macro { + u8 idx; + /* Not used when in QSGMII or PCIe mode */ + int port; + struct serdes_ctrl *ctrl; +}; + +#define MCB_S6G_CFG_TIMEOUT 50 + +static int __serdes_write_mcb_s6g(struct regmap *regmap, u8 macro, u32 op) +{ + unsigned int regval = 0; + + regmap_write(regmap, HSIO_MCB_S6G_ADDR_CFG, op | + HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(BIT(macro))); + + return regmap_read_poll_timeout(regmap, HSIO_MCB_S6G_ADDR_CFG, regval, + (regval & op) != op, 100, + MCB_S6G_CFG_TIMEOUT * 1000); +} + +static int serdes_commit_mcb_s6g(struct regmap *regmap, u8 macro) +{ + return __serdes_write_mcb_s6g(regmap, macro, + HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT); +} + +static int serdes_update_mcb_s6g(struct regmap *regmap, u8 macro) +{ + return __serdes_write_mcb_s6g(regmap, macro, + HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT); +} + +static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode) +{ + u32 pll_fsm_ctrl_data; + u32 ob_ena1v_mode; + u32 des_bw_ana; + u32 ob_ena_cas; + u32 if_mode; + u32 ob_lev; + u32 qrate; + int ret; + + if (mode == PHY_INTERFACE_MODE_QSGMII) { + pll_fsm_ctrl_data = 120; + ob_ena1v_mode = 0; + ob_ena_cas = 0; + des_bw_ana = 5; + ob_lev = 24; + if_mode = 3; + qrate = 0; + } else { + pll_fsm_ctrl_data = 60; + ob_ena1v_mode = 1; + ob_ena_cas = 2; + des_bw_ana = 3; + ob_lev = 48; + if_mode = 1; + qrate = 1; + } + + ret = serdes_update_mcb_s6g(regmap, serdes); + if (ret) + return ret; + + /* Test pattern */ + + regmap_update_bits(regmap, HSIO_S6G_COMMON_CFG, + HSIO_S6G_COMMON_CFG_SYS_RST, 0); + + regmap_update_bits(regmap, HSIO_S6G_PLL_CFG, + HSIO_S6G_PLL_CFG_PLL_FSM_ENA, 0); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG, + HSIO_S6G_IB_CFG_IB_SIG_DET_ENA | + HSIO_S6G_IB_CFG_IB_REG_ENA | + HSIO_S6G_IB_CFG_IB_SAM_ENA | + HSIO_S6G_IB_CFG_IB_EQZ_ENA | + HSIO_S6G_IB_CFG_IB_CONCUR | + HSIO_S6G_IB_CFG_IB_CAL_ENA, + HSIO_S6G_IB_CFG_IB_SIG_DET_ENA | + HSIO_S6G_IB_CFG_IB_REG_ENA | + HSIO_S6G_IB_CFG_IB_SAM_ENA | + HSIO_S6G_IB_CFG_IB_EQZ_ENA | + HSIO_S6G_IB_CFG_IB_CONCUR); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG1, + HSIO_S6G_IB_CFG1_IB_FRC_OFFSET | + HSIO_S6G_IB_CFG1_IB_FRC_LP | + HSIO_S6G_IB_CFG1_IB_FRC_MID | + HSIO_S6G_IB_CFG1_IB_FRC_HP | + HSIO_S6G_IB_CFG1_IB_FILT_OFFSET | + HSIO_S6G_IB_CFG1_IB_FILT_LP | + HSIO_S6G_IB_CFG1_IB_FILT_MID | + HSIO_S6G_IB_CFG1_IB_FILT_HP, + HSIO_S6G_IB_CFG1_IB_FILT_OFFSET | + HSIO_S6G_IB_CFG1_IB_FILT_HP | + HSIO_S6G_IB_CFG1_IB_FILT_LP | + HSIO_S6G_IB_CFG1_IB_FILT_MID); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG2, + HSIO_S6G_IB_CFG2_IB_UREG_M, + HSIO_S6G_IB_CFG2_IB_UREG(4)); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG3, + HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M | + HSIO_S6G_IB_CFG3_IB_INI_LP_M | + HSIO_S6G_IB_CFG3_IB_INI_MID_M | + HSIO_S6G_IB_CFG3_IB_INI_HP_M, + HSIO_S6G_IB_CFG3_IB_INI_OFFSET(31) | + HSIO_S6G_IB_CFG3_IB_INI_LP(1) | + HSIO_S6G_IB_CFG3_IB_INI_MID(31) | + HSIO_S6G_IB_CFG3_IB_INI_HP(0)); + + regmap_update_bits(regmap, HSIO_S6G_MISC_CFG, + HSIO_S6G_MISC_CFG_LANE_RST, + HSIO_S6G_MISC_CFG_LANE_RST); + + ret = serdes_commit_mcb_s6g(regmap, serdes); + if (ret) + return ret; + + /* OB + DES + IB + SER CFG */ + regmap_update_bits(regmap, HSIO_S6G_OB_CFG, + HSIO_S6G_OB_CFG_OB_IDLE | + HSIO_S6G_OB_CFG_OB_ENA1V_MODE | + HSIO_S6G_OB_CFG_OB_POST0_M | + HSIO_S6G_OB_CFG_OB_PREC_M, + (ob_ena1v_mode ? HSIO_S6G_OB_CFG_OB_ENA1V_MODE : 0) | + HSIO_S6G_OB_CFG_OB_POST0(0) | + HSIO_S6G_OB_CFG_OB_PREC(0)); + + regmap_update_bits(regmap, HSIO_S6G_OB_CFG1, + HSIO_S6G_OB_CFG1_OB_ENA_CAS_M | + HSIO_S6G_OB_CFG1_OB_LEV_M, + HSIO_S6G_OB_CFG1_OB_LEV(ob_lev) | + HSIO_S6G_OB_CFG1_OB_ENA_CAS(ob_ena_cas)); + + regmap_update_bits(regmap, HSIO_S6G_DES_CFG, + HSIO_S6G_DES_CFG_DES_PHS_CTRL_M | + HSIO_S6G_DES_CFG_DES_CPMD_SEL_M | + HSIO_S6G_DES_CFG_DES_BW_ANA_M, + HSIO_S6G_DES_CFG_DES_PHS_CTRL(2) | + HSIO_S6G_DES_CFG_DES_CPMD_SEL(0) | + HSIO_S6G_DES_CFG_DES_BW_ANA(des_bw_ana)); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG, + HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M | + HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M, + HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(0) | + HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(0)); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG1, + HSIO_S6G_IB_CFG1_IB_TSDET_M, + HSIO_S6G_IB_CFG1_IB_TSDET(16)); + + regmap_update_bits(regmap, HSIO_S6G_SER_CFG, + HSIO_S6G_SER_CFG_SER_ALISEL_M | + HSIO_S6G_SER_CFG_SER_ENALI, + HSIO_S6G_SER_CFG_SER_ALISEL(0)); + + regmap_update_bits(regmap, HSIO_S6G_PLL_CFG, + HSIO_S6G_PLL_CFG_PLL_DIV4 | + HSIO_S6G_PLL_CFG_PLL_ENA_ROT | + HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M | + HSIO_S6G_PLL_CFG_PLL_ROT_DIR | + HSIO_S6G_PLL_CFG_PLL_ROT_FRQ, + HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA + (pll_fsm_ctrl_data)); + + regmap_update_bits(regmap, HSIO_S6G_COMMON_CFG, + HSIO_S6G_COMMON_CFG_SYS_RST | + HSIO_S6G_COMMON_CFG_ENA_LANE | + HSIO_S6G_COMMON_CFG_PWD_RX | + HSIO_S6G_COMMON_CFG_PWD_TX | + HSIO_S6G_COMMON_CFG_HRATE | + HSIO_S6G_COMMON_CFG_QRATE | + HSIO_S6G_COMMON_CFG_ENA_ELOOP | + HSIO_S6G_COMMON_CFG_ENA_FLOOP | + HSIO_S6G_COMMON_CFG_IF_MODE_M, + HSIO_S6G_COMMON_CFG_SYS_RST | + HSIO_S6G_COMMON_CFG_ENA_LANE | + (qrate ? HSIO_S6G_COMMON_CFG_QRATE : 0) | + HSIO_S6G_COMMON_CFG_IF_MODE(if_mode)); + + regmap_update_bits(regmap, HSIO_S6G_MISC_CFG, + HSIO_S6G_MISC_CFG_LANE_RST | + HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA | + HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA | + HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA, + HSIO_S6G_MISC_CFG_LANE_RST | + HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA); + + + ret = serdes_commit_mcb_s6g(regmap, serdes); + if (ret) + return ret; + + regmap_update_bits(regmap, HSIO_S6G_PLL_CFG, + HSIO_S6G_PLL_CFG_PLL_FSM_ENA, + HSIO_S6G_PLL_CFG_PLL_FSM_ENA); + + ret = serdes_commit_mcb_s6g(regmap, serdes); + if (ret) + return ret; + + /* Wait for PLL bringup */ + msleep(20); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG, + HSIO_S6G_IB_CFG_IB_CAL_ENA, + HSIO_S6G_IB_CFG_IB_CAL_ENA); + + regmap_update_bits(regmap, HSIO_S6G_MISC_CFG, + HSIO_S6G_MISC_CFG_LANE_RST, 0); + + ret = serdes_commit_mcb_s6g(regmap, serdes); + if (ret) + return ret; + + /* Wait for calibration */ + msleep(60); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG, + HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M | + HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M, + HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(0) | + HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(7)); + + regmap_update_bits(regmap, HSIO_S6G_IB_CFG1, + HSIO_S6G_IB_CFG1_IB_TSDET_M, + HSIO_S6G_IB_CFG1_IB_TSDET(3)); + + /* IB CFG */ + + return 0; +} + +#define MCB_S1G_CFG_TIMEOUT 50 + +static int __serdes_write_mcb_s1g(struct regmap *regmap, u8 macro, u32 op) +{ + unsigned int regval; + + regmap_write(regmap, HSIO_MCB_S1G_ADDR_CFG, op | + HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(BIT(macro))); + + return regmap_read_poll_timeout(regmap, HSIO_MCB_S1G_ADDR_CFG, regval, + (regval & op) != op, 100, + MCB_S1G_CFG_TIMEOUT * 1000); +} + +static int serdes_commit_mcb_s1g(struct regmap *regmap, u8 macro) +{ + return __serdes_write_mcb_s1g(regmap, macro, + HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT); +} + +static int serdes_update_mcb_s1g(struct regmap *regmap, u8 macro) +{ + return __serdes_write_mcb_s1g(regmap, macro, + HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT); +} + +static int serdes_init_s1g(struct regmap *regmap, u8 serdes) +{ + int ret; + + ret = serdes_update_mcb_s1g(regmap, serdes); + if (ret) + return ret; + + regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG, + HSIO_S1G_COMMON_CFG_SYS_RST | + HSIO_S1G_COMMON_CFG_ENA_LANE | + HSIO_S1G_COMMON_CFG_ENA_ELOOP | + HSIO_S1G_COMMON_CFG_ENA_FLOOP, + HSIO_S1G_COMMON_CFG_ENA_LANE); + + regmap_update_bits(regmap, HSIO_S1G_PLL_CFG, + HSIO_S1G_PLL_CFG_PLL_FSM_ENA | + HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M, + HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(200) | + HSIO_S1G_PLL_CFG_PLL_FSM_ENA); + + regmap_update_bits(regmap, HSIO_S1G_MISC_CFG, + HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA | + HSIO_S1G_MISC_CFG_LANE_RST, + HSIO_S1G_MISC_CFG_LANE_RST); + + ret = serdes_commit_mcb_s1g(regmap, serdes); + if (ret) + return ret; + + regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG, + HSIO_S1G_COMMON_CFG_SYS_RST, + HSIO_S1G_COMMON_CFG_SYS_RST); + + regmap_update_bits(regmap, HSIO_S1G_MISC_CFG, + HSIO_S1G_MISC_CFG_LANE_RST, 0); + + ret = serdes_commit_mcb_s1g(regmap, serdes); + if (ret) + return ret; + + return 0; +} + +struct serdes_mux { + u8 idx; + u8 port; + enum phy_mode mode; + int submode; + u32 mask; + u32 mux; +}; + +#define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \ + .idx = _idx, \ + .port = _port, \ + .mode = _mode, \ + .submode = _submode, \ + .mask = _mask, \ + .mux = _mux, \ +} + +#define SERDES_MUX_SGMII(i, p, m, c) \ + SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c) +#define SERDES_MUX_QSGMII(i, p, m, c) \ + SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c) + +static const struct serdes_mux ocelot_serdes_muxes[] = { + SERDES_MUX_SGMII(SERDES1G(0), 0, 0, 0), + SERDES_MUX_SGMII(SERDES1G(1), 1, HSIO_HW_CFG_DEV1G_5_MODE, 0), + SERDES_MUX_SGMII(SERDES1G(1), 5, HSIO_HW_CFG_QSGMII_ENA | + HSIO_HW_CFG_DEV1G_5_MODE, HSIO_HW_CFG_DEV1G_5_MODE), + SERDES_MUX_SGMII(SERDES1G(2), 2, HSIO_HW_CFG_DEV1G_4_MODE, 0), + SERDES_MUX_SGMII(SERDES1G(2), 4, HSIO_HW_CFG_QSGMII_ENA | + HSIO_HW_CFG_DEV1G_4_MODE, HSIO_HW_CFG_DEV1G_4_MODE), + SERDES_MUX_SGMII(SERDES1G(3), 3, HSIO_HW_CFG_DEV1G_6_MODE, 0), + SERDES_MUX_SGMII(SERDES1G(3), 6, HSIO_HW_CFG_QSGMII_ENA | + HSIO_HW_CFG_DEV1G_6_MODE, HSIO_HW_CFG_DEV1G_6_MODE), + SERDES_MUX_SGMII(SERDES1G(4), 4, HSIO_HW_CFG_QSGMII_ENA | + HSIO_HW_CFG_DEV1G_4_MODE | HSIO_HW_CFG_DEV1G_9_MODE, + 0), + SERDES_MUX_SGMII(SERDES1G(4), 9, HSIO_HW_CFG_DEV1G_4_MODE | + HSIO_HW_CFG_DEV1G_9_MODE, HSIO_HW_CFG_DEV1G_4_MODE | + HSIO_HW_CFG_DEV1G_9_MODE), + SERDES_MUX_SGMII(SERDES1G(5), 5, HSIO_HW_CFG_QSGMII_ENA | + HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE, + 0), + SERDES_MUX_SGMII(SERDES1G(5), 10, HSIO_HW_CFG_PCIE_ENA | + HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE, + HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE), + SERDES_MUX_QSGMII(SERDES6G(0), 4, HSIO_HW_CFG_QSGMII_ENA, + HSIO_HW_CFG_QSGMII_ENA), + SERDES_MUX_QSGMII(SERDES6G(0), 5, HSIO_HW_CFG_QSGMII_ENA, + HSIO_HW_CFG_QSGMII_ENA), + SERDES_MUX_QSGMII(SERDES6G(0), 6, HSIO_HW_CFG_QSGMII_ENA, + HSIO_HW_CFG_QSGMII_ENA), + SERDES_MUX_SGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA, 0), + SERDES_MUX_QSGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA, + HSIO_HW_CFG_QSGMII_ENA), + SERDES_MUX_SGMII(SERDES6G(1), 8, 0, 0), + SERDES_MUX_SGMII(SERDES6G(2), 10, HSIO_HW_CFG_PCIE_ENA | + HSIO_HW_CFG_DEV2G5_10_MODE, 0), + SERDES_MUX(SERDES6G(2), 10, PHY_MODE_PCIE, 0, HSIO_HW_CFG_PCIE_ENA, + HSIO_HW_CFG_PCIE_ENA), +}; + +static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct serdes_macro *macro = phy_get_drvdata(phy); + unsigned int i; + int ret; + + /* As of now only PHY_MODE_ETHERNET is supported */ + if (mode != PHY_MODE_ETHERNET) + return -EOPNOTSUPP; + + for (i = 0; i < ARRAY_SIZE(ocelot_serdes_muxes); i++) { + if (macro->idx != ocelot_serdes_muxes[i].idx || + mode != ocelot_serdes_muxes[i].mode || + submode != ocelot_serdes_muxes[i].submode) + continue; + + if (submode != PHY_INTERFACE_MODE_QSGMII && + macro->port != ocelot_serdes_muxes[i].port) + continue; + + ret = regmap_update_bits(macro->ctrl->regs, HSIO_HW_CFG, + ocelot_serdes_muxes[i].mask, + ocelot_serdes_muxes[i].mux); + if (ret) + return ret; + + if (macro->idx <= SERDES1G_MAX) + return serdes_init_s1g(macro->ctrl->regs, macro->idx); + else if (macro->idx <= SERDES6G_MAX) + return serdes_init_s6g(macro->ctrl->regs, + macro->idx - (SERDES1G_MAX + 1), + ocelot_serdes_muxes[i].submode); + + /* PCIe not supported yet */ + return -EOPNOTSUPP; + } + + return -EINVAL; +} + +static const struct phy_ops serdes_ops = { + .set_mode = serdes_set_mode, + .owner = THIS_MODULE, +}; + +static struct phy *serdes_simple_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct serdes_ctrl *ctrl = dev_get_drvdata(dev); + unsigned int port, idx, i; + + if (args->args_count != 2) + return ERR_PTR(-EINVAL); + + port = args->args[0]; + idx = args->args[1]; + + for (i = 0; i < SERDES_MAX; i++) { + struct serdes_macro *macro = phy_get_drvdata(ctrl->phys[i]); + + if (idx != macro->idx) + continue; + + /* SERDES6G(0) is the only SerDes capable of QSGMII */ + if (idx != SERDES6G(0) && macro->port >= 0) + return ERR_PTR(-EBUSY); + + macro->port = port; + return ctrl->phys[i]; + } + + return ERR_PTR(-ENODEV); +} + +static int serdes_phy_create(struct serdes_ctrl *ctrl, u8 idx, struct phy **phy) +{ + struct serdes_macro *macro; + + *phy = devm_phy_create(ctrl->dev, NULL, &serdes_ops); + if (IS_ERR(*phy)) + return PTR_ERR(*phy); + + macro = devm_kzalloc(ctrl->dev, sizeof(*macro), GFP_KERNEL); + if (!macro) + return -ENOMEM; + + macro->idx = idx; + macro->ctrl = ctrl; + macro->port = -1; + + phy_set_drvdata(*phy, macro); + + return 0; +} + +static int serdes_probe(struct platform_device *pdev) +{ + struct phy_provider *provider; + struct serdes_ctrl *ctrl; + unsigned int i; + int ret; + + ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->dev = &pdev->dev; + ctrl->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(ctrl->regs)) + return PTR_ERR(ctrl->regs); + + for (i = 0; i < SERDES_MAX; i++) { + ret = serdes_phy_create(ctrl, i, &ctrl->phys[i]); + if (ret) + return ret; + } + + dev_set_drvdata(&pdev->dev, ctrl); + + provider = devm_of_phy_provider_register(ctrl->dev, + serdes_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id serdes_ids[] = { + { .compatible = "mscc,vsc7514-serdes", }, + {}, +}; +MODULE_DEVICE_TABLE(of, serdes_ids); + +static struct platform_driver mscc_ocelot_serdes = { + .probe = serdes_probe, + .driver = { + .name = "mscc,ocelot-serdes", + .of_match_table = of_match_ptr(serdes_ids), + }, +}; + +module_platform_driver(mscc_ocelot_serdes); + +MODULE_AUTHOR("Quentin Schulz "); +MODULE_DESCRIPTION("SerDes driver for Microsemi Ocelot"); +MODULE_LICENSE("Dual MIT/GPL"); -- cgit v1.2.3