From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/pinctrl/mediatek/pinctrl-mt8365.c | 500 ++++++++++++++++++++++++++++++ 1 file changed, 500 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8365.c (limited to 'drivers/pinctrl/mediatek/pinctrl-mt8365.c') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c new file mode 100644 index 000000000..db4492e9e --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Zhiyong Tao + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8365.h" + +static const struct mtk_drv_group_desc mt8365_drv_grp[] = { + /* 0E4E8SR 4/8/12/16 */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* 0E2E4SR 2/4/6/8 */ + MTK_DRV_GRP(2, 8, 1, 2, 2), + /* E8E4E2 2/4/6/8/10/12/14/16 */ + MTK_DRV_GRP(2, 16, 0, 2, 2) +}; + +static const struct mtk_pin_drv_grp mt8365_pin_drv[] = { + + MTK_PIN_DRV_GRP(0, 0x710, 0, 2), + MTK_PIN_DRV_GRP(1, 0x710, 0, 2), + MTK_PIN_DRV_GRP(2, 0x710, 0, 2), + MTK_PIN_DRV_GRP(3, 0x710, 0, 2), + MTK_PIN_DRV_GRP(4, 0x710, 4, 2), + MTK_PIN_DRV_GRP(5, 0x710, 4, 2), + MTK_PIN_DRV_GRP(6, 0x710, 4, 2), + MTK_PIN_DRV_GRP(7, 0x710, 4, 2), + MTK_PIN_DRV_GRP(8, 0x710, 8, 2), + MTK_PIN_DRV_GRP(9, 0x710, 8, 2), + MTK_PIN_DRV_GRP(10, 0x710, 8, 2), + MTK_PIN_DRV_GRP(11, 0x710, 8, 2), + MTK_PIN_DRV_GRP(12, 0x710, 12, 2), + MTK_PIN_DRV_GRP(13, 0x710, 12, 2), + MTK_PIN_DRV_GRP(14, 0x710, 12, 2), + MTK_PIN_DRV_GRP(15, 0x710, 12, 2), + MTK_PIN_DRV_GRP(16, 0x710, 16, 2), + MTK_PIN_DRV_GRP(17, 0x710, 16, 2), + MTK_PIN_DRV_GRP(18, 0x710, 16, 2), + MTK_PIN_DRV_GRP(19, 0x710, 20, 2), + MTK_PIN_DRV_GRP(20, 0x710, 24, 2), + MTK_PIN_DRV_GRP(21, 0x710, 24, 2), + MTK_PIN_DRV_GRP(22, 0x710, 28, 2), + MTK_PIN_DRV_GRP(23, 0x720, 0, 2), + MTK_PIN_DRV_GRP(24, 0x720, 0, 2), + MTK_PIN_DRV_GRP(25, 0x720, 0, 2), + MTK_PIN_DRV_GRP(26, 0x720, 4, 2), + MTK_PIN_DRV_GRP(27, 0x720, 4, 2), + MTK_PIN_DRV_GRP(28, 0x720, 4, 2), + MTK_PIN_DRV_GRP(29, 0x720, 4, 2), + MTK_PIN_DRV_GRP(30, 0x720, 8, 2), + MTK_PIN_DRV_GRP(31, 0x720, 8, 2), + MTK_PIN_DRV_GRP(32, 0x720, 8, 2), + MTK_PIN_DRV_GRP(33, 0x720, 8, 2), + MTK_PIN_DRV_GRP(34, 0x720, 8, 2), + MTK_PIN_DRV_GRP(35, 0x720, 12, 2), + MTK_PIN_DRV_GRP(36, 0x720, 12, 2), + MTK_PIN_DRV_GRP(37, 0x720, 12, 2), + MTK_PIN_DRV_GRP(38, 0x720, 12, 2), + MTK_PIN_DRV_GRP(39, 0x720, 12, 2), + MTK_PIN_DRV_GRP(40, 0x720, 12, 2), + MTK_PIN_DRV_GRP(41, 0x720, 16, 2), + MTK_PIN_DRV_GRP(42, 0x720, 16, 2), + MTK_PIN_DRV_GRP(43, 0x720, 16, 2), + MTK_PIN_DRV_GRP(44, 0x720, 16, 2), + MTK_PIN_DRV_GRP(45, 0x720, 20, 2), + MTK_PIN_DRV_GRP(46, 0x720, 20, 2), + MTK_PIN_DRV_GRP(47, 0x720, 20, 2), + MTK_PIN_DRV_GRP(48, 0x720, 20, 2), + MTK_PIN_DRV_GRP(49, 0x720, 24, 2), + MTK_PIN_DRV_GRP(50, 0x720, 24, 2), + MTK_PIN_DRV_GRP(51, 0x720, 24, 2), + MTK_PIN_DRV_GRP(52, 0x720, 24, 2), + MTK_PIN_DRV_GRP(53, 0x720, 24, 2), + MTK_PIN_DRV_GRP(54, 0x720, 24, 2), + MTK_PIN_DRV_GRP(55, 0x720, 24, 2), + MTK_PIN_DRV_GRP(56, 0x720, 24, 2), + MTK_PIN_DRV_GRP(57, 0x720, 28, 2), + MTK_PIN_DRV_GRP(58, 0x720, 28, 2), + MTK_PIN_DRV_GRP(59, 0x730, 0, 2), + MTK_PIN_DRV_GRP(60, 0x730, 0, 2), + MTK_PIN_DRV_GRP(61, 0x730, 4, 2), + MTK_PIN_DRV_GRP(62, 0x730, 4, 2), + MTK_PIN_DRV_GRP(63, 0x730, 8, 2), + MTK_PIN_DRV_GRP(64, 0x730, 8, 2), + MTK_PIN_DRV_GRP(65, 0x730, 12, 2), + MTK_PIN_DRV_GRP(66, 0x730, 12, 2), + MTK_PIN_DRV_GRP(67, 0x730, 12, 2), + MTK_PIN_DRV_GRP(68, 0x730, 12, 2), + MTK_PIN_DRV_GRP(69, 0x730, 12, 2), + MTK_PIN_DRV_GRP(70, 0x730, 12, 2), + MTK_PIN_DRV_GRP(71, 0x730, 16, 2), + MTK_PIN_DRV_GRP(72, 0x730, 16, 2), + MTK_PIN_DRV_GRP(73, 0x730, 16, 2), + MTK_PIN_DRV_GRP(74, 0x730, 16, 2), + MTK_PIN_DRV_GRP(75, 0x730, 16, 2), + MTK_PIN_DRV_GRP(76, 0x730, 16, 2), + MTK_PIN_DRV_GRP(77, 0x730, 16, 2), + MTK_PIN_DRV_GRP(78, 0x730, 16, 2), + MTK_PIN_DRV_GRP(79, 0x730, 16, 2), + MTK_PIN_DRV_GRP(80, 0x730, 20, 2), + MTK_PIN_DRV_GRP(81, 0x730, 24, 2), + MTK_PIN_DRV_GRP(82, 0x730, 28, 2), + MTK_PIN_DRV_GRP(83, 0x730, 28, 2), + MTK_PIN_DRV_GRP(84, 0x730, 28, 2), + MTK_PIN_DRV_GRP(85, 0x730, 28, 2), + MTK_PIN_DRV_GRP(86, 0x740, 12, 2), + MTK_PIN_DRV_GRP(87, 0x740, 16, 2), + MTK_PIN_DRV_GRP(88, 0x740, 20, 2), + MTK_PIN_DRV_GRP(89, 0x740, 24, 2), + MTK_PIN_DRV_GRP(90, 0x740, 24, 2), + MTK_PIN_DRV_GRP(91, 0x740, 24, 2), + MTK_PIN_DRV_GRP(92, 0x740, 24, 2), + MTK_PIN_DRV_GRP(93, 0x750, 8, 2), + MTK_PIN_DRV_GRP(94, 0x750, 8, 2), + MTK_PIN_DRV_GRP(95, 0x750, 8, 2), + MTK_PIN_DRV_GRP(96, 0x750, 8, 2), + MTK_PIN_DRV_GRP(97, 0x750, 24, 2), + MTK_PIN_DRV_GRP(98, 0x750, 28, 2), + MTK_PIN_DRV_GRP(99, 0x760, 0, 2), + MTK_PIN_DRV_GRP(100, 0x750, 8, 2), + MTK_PIN_DRV_GRP(101, 0x750, 8, 2), + MTK_PIN_DRV_GRP(102, 0x750, 8, 2), + MTK_PIN_DRV_GRP(103, 0x750, 8, 2), + MTK_PIN_DRV_GRP(104, 0x760, 20, 2), + MTK_PIN_DRV_GRP(105, 0x760, 24, 2), + MTK_PIN_DRV_GRP(106, 0x760, 24, 2), + MTK_PIN_DRV_GRP(107, 0x760, 24, 2), + MTK_PIN_DRV_GRP(108, 0x760, 24, 2), + MTK_PIN_DRV_GRP(109, 0x760, 24, 2), + MTK_PIN_DRV_GRP(110, 0x760, 28, 2), + MTK_PIN_DRV_GRP(111, 0x760, 28, 2), + MTK_PIN_DRV_GRP(112, 0x760, 28, 2), + MTK_PIN_DRV_GRP(113, 0x760, 28, 2), + MTK_PIN_DRV_GRP(114, 0x770, 0, 2), + MTK_PIN_DRV_GRP(115, 0x770, 0, 2), + MTK_PIN_DRV_GRP(116, 0x770, 0, 2), + MTK_PIN_DRV_GRP(117, 0x770, 4, 2), + MTK_PIN_DRV_GRP(118, 0x770, 4, 2), + MTK_PIN_DRV_GRP(119, 0x770, 4, 2), + MTK_PIN_DRV_GRP(120, 0x770, 8, 2), + MTK_PIN_DRV_GRP(121, 0x770, 8, 2), + MTK_PIN_DRV_GRP(122, 0x770, 8, 2), + MTK_PIN_DRV_GRP(123, 0x770, 12, 2), + MTK_PIN_DRV_GRP(124, 0x770, 12, 2), + MTK_PIN_DRV_GRP(125, 0x770, 12, 2), + MTK_PIN_DRV_GRP(126, 0x770, 16, 2), + MTK_PIN_DRV_GRP(127, 0x770, 16, 2), + MTK_PIN_DRV_GRP(128, 0x770, 16, 2), + MTK_PIN_DRV_GRP(129, 0x770, 20, 2), + MTK_PIN_DRV_GRP(130, 0x770, 20, 2), + MTK_PIN_DRV_GRP(131, 0x770, 20, 2), + MTK_PIN_DRV_GRP(132, 0x770, 20, 2), + MTK_PIN_DRV_GRP(133, 0x770, 20, 2), + MTK_PIN_DRV_GRP(134, 0x770, 20, 2), + MTK_PIN_DRV_GRP(135, 0x770, 20, 2), + MTK_PIN_DRV_GRP(136, 0x770, 24, 2), + MTK_PIN_DRV_GRP(137, 0x770, 24, 2), + MTK_PIN_DRV_GRP(138, 0x770, 24, 2), + MTK_PIN_DRV_GRP(139, 0x770, 24, 2), + MTK_PIN_DRV_GRP(140, 0x770, 24, 2), + MTK_PIN_DRV_GRP(141, 0x770, 24, 2), + MTK_PIN_DRV_GRP(142, 0x770, 24, 2), + MTK_PIN_DRV_GRP(143, 0x770, 24, 2), + MTK_PIN_DRV_GRP(144, 0x770, 24, 2), +}; + +static const struct mtk_pin_spec_pupd_set_samereg mt8365_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(22, 0x070, 0, 2, 1), + MTK_PIN_PUPD_SPEC_SR(23, 0x070, 3, 5, 4), + MTK_PIN_PUPD_SPEC_SR(24, 0x070, 6, 8, 7), + MTK_PIN_PUPD_SPEC_SR(25, 0x070, 9, 11, 10), + MTK_PIN_PUPD_SPEC_SR(80, 0x070, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(81, 0x070, 17, 16, 15), + MTK_PIN_PUPD_SPEC_SR(82, 0x070, 20, 19, 18), + MTK_PIN_PUPD_SPEC_SR(83, 0x070, 23, 22, 21), + MTK_PIN_PUPD_SPEC_SR(84, 0x070, 26, 25, 24), + MTK_PIN_PUPD_SPEC_SR(85, 0x070, 29, 28, 27), + MTK_PIN_PUPD_SPEC_SR(86, 0x080, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(87, 0x080, 5, 4, 3), + MTK_PIN_PUPD_SPEC_SR(88, 0x080, 8, 7, 6), + MTK_PIN_PUPD_SPEC_SR(89, 0x080, 11, 10, 9), + MTK_PIN_PUPD_SPEC_SR(90, 0x080, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(91, 0x080, 17, 16, 15), + MTK_PIN_PUPD_SPEC_SR(92, 0x080, 20, 19, 18), + MTK_PIN_PUPD_SPEC_SR(93, 0x080, 23, 22, 21), + MTK_PIN_PUPD_SPEC_SR(94, 0x080, 26, 25, 24), + MTK_PIN_PUPD_SPEC_SR(95, 0x080, 29, 28, 27), + MTK_PIN_PUPD_SPEC_SR(96, 0x090, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(97, 0x090, 5, 4, 3), + MTK_PIN_PUPD_SPEC_SR(98, 0x090, 8, 7, 6), + MTK_PIN_PUPD_SPEC_SR(99, 0x090, 11, 10, 9), + MTK_PIN_PUPD_SPEC_SR(100, 0x090, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(101, 0x090, 17, 16, 15), + MTK_PIN_PUPD_SPEC_SR(102, 0x090, 20, 19, 18), + MTK_PIN_PUPD_SPEC_SR(103, 0x090, 23, 22, 21), + MTK_PIN_PUPD_SPEC_SR(104, 0x090, 26, 25, 24), + MTK_PIN_PUPD_SPEC_SR(105, 0x090, 29, 28, 27), + MTK_PIN_PUPD_SPEC_SR(106, 0x0F0, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(107, 0x0F0, 5, 4, 3), + MTK_PIN_PUPD_SPEC_SR(108, 0x0F0, 8, 7, 6), + MTK_PIN_PUPD_SPEC_SR(109, 0x0F0, 11, 10, 9), +}; + +static const struct mtk_pin_ies_smt_set mt8365_ies_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 3, 0x410, 0), + MTK_PIN_IES_SMT_SPEC(4, 7, 0x410, 1), + MTK_PIN_IES_SMT_SPEC(8, 11, 0x410, 2), + MTK_PIN_IES_SMT_SPEC(12, 15, 0x410, 3), + MTK_PIN_IES_SMT_SPEC(16, 18, 0x410, 4), + MTK_PIN_IES_SMT_SPEC(19, 19, 0x410, 5), + MTK_PIN_IES_SMT_SPEC(20, 21, 0x410, 6), + MTK_PIN_IES_SMT_SPEC(22, 22, 0x410, 7), + MTK_PIN_IES_SMT_SPEC(23, 25, 0x410, 8), + MTK_PIN_IES_SMT_SPEC(26, 29, 0x410, 9), + MTK_PIN_IES_SMT_SPEC(30, 34, 0x410, 10), + MTK_PIN_IES_SMT_SPEC(35, 40, 0x410, 11), + MTK_PIN_IES_SMT_SPEC(41, 44, 0x410, 12), + MTK_PIN_IES_SMT_SPEC(45, 48, 0x410, 13), + MTK_PIN_IES_SMT_SPEC(49, 56, 0x410, 14), + MTK_PIN_IES_SMT_SPEC(57, 58, 0x410, 15), + MTK_PIN_IES_SMT_SPEC(59, 60, 0x410, 16), + MTK_PIN_IES_SMT_SPEC(61, 62, 0x410, 17), + MTK_PIN_IES_SMT_SPEC(63, 64, 0x410, 18), + MTK_PIN_IES_SMT_SPEC(65, 70, 0x410, 19), + MTK_PIN_IES_SMT_SPEC(71, 79, 0x410, 20), + MTK_PIN_IES_SMT_SPEC(80, 80, 0x410, 21), + MTK_PIN_IES_SMT_SPEC(81, 81, 0x410, 22), + MTK_PIN_IES_SMT_SPEC(82, 82, 0x410, 23), + MTK_PIN_IES_SMT_SPEC(83, 83, 0x410, 24), + MTK_PIN_IES_SMT_SPEC(84, 84, 0x410, 25), + MTK_PIN_IES_SMT_SPEC(85, 85, 0x410, 26), + MTK_PIN_IES_SMT_SPEC(86, 86, 0x410, 27), + MTK_PIN_IES_SMT_SPEC(87, 87, 0x410, 28), + MTK_PIN_IES_SMT_SPEC(88, 88, 0x410, 29), + MTK_PIN_IES_SMT_SPEC(89, 89, 0x410, 30), + MTK_PIN_IES_SMT_SPEC(90, 90, 0x410, 31), + MTK_PIN_IES_SMT_SPEC(91, 91, 0x420, 0), + MTK_PIN_IES_SMT_SPEC(92, 92, 0x420, 1), + MTK_PIN_IES_SMT_SPEC(93, 93, 0x420, 2), + MTK_PIN_IES_SMT_SPEC(94, 94, 0x420, 3), + MTK_PIN_IES_SMT_SPEC(95, 95, 0x420, 4), + MTK_PIN_IES_SMT_SPEC(96, 96, 0x420, 5), + MTK_PIN_IES_SMT_SPEC(97, 97, 0x420, 6), + MTK_PIN_IES_SMT_SPEC(98, 98, 0x420, 7), + MTK_PIN_IES_SMT_SPEC(99, 99, 0x420, 8), + MTK_PIN_IES_SMT_SPEC(100, 100, 0x420, 9), + MTK_PIN_IES_SMT_SPEC(101, 101, 0x420, 10), + MTK_PIN_IES_SMT_SPEC(102, 102, 0x420, 11), + MTK_PIN_IES_SMT_SPEC(103, 103, 0x420, 12), + MTK_PIN_IES_SMT_SPEC(104, 104, 0x420, 13), + MTK_PIN_IES_SMT_SPEC(105, 109, 0x420, 14), + MTK_PIN_IES_SMT_SPEC(110, 113, 0x420, 15), + MTK_PIN_IES_SMT_SPEC(114, 116, 0x420, 16), + MTK_PIN_IES_SMT_SPEC(117, 119, 0x420, 17), + MTK_PIN_IES_SMT_SPEC(120, 122, 0x420, 18), + MTK_PIN_IES_SMT_SPEC(123, 125, 0x420, 19), + MTK_PIN_IES_SMT_SPEC(126, 128, 0x420, 20), + MTK_PIN_IES_SMT_SPEC(129, 135, 0x420, 21), + MTK_PIN_IES_SMT_SPEC(136, 144, 0x420, 22), +}; + +static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 0, 0x470, 0), + MTK_PIN_IES_SMT_SPEC(1, 1, 0x470, 0), + MTK_PIN_IES_SMT_SPEC(2, 2, 0x470, 0), + MTK_PIN_IES_SMT_SPEC(3, 3, 0x470, 0), + MTK_PIN_IES_SMT_SPEC(4, 4, 0x470, 1), + MTK_PIN_IES_SMT_SPEC(5, 5, 0x470, 1), + MTK_PIN_IES_SMT_SPEC(6, 6, 0x470, 1), + MTK_PIN_IES_SMT_SPEC(7, 7, 0x470, 1), + MTK_PIN_IES_SMT_SPEC(8, 8, 0x470, 2), + MTK_PIN_IES_SMT_SPEC(9, 9, 0x470, 2), + MTK_PIN_IES_SMT_SPEC(10, 10, 0x470, 2), + MTK_PIN_IES_SMT_SPEC(11, 11, 0x470, 2), + MTK_PIN_IES_SMT_SPEC(12, 12, 0x470, 3), + MTK_PIN_IES_SMT_SPEC(13, 13, 0x470, 3), + MTK_PIN_IES_SMT_SPEC(14, 14, 0x470, 3), + MTK_PIN_IES_SMT_SPEC(15, 15, 0x470, 3), + MTK_PIN_IES_SMT_SPEC(16, 16, 0x470, 4), + MTK_PIN_IES_SMT_SPEC(17, 17, 0x470, 4), + MTK_PIN_IES_SMT_SPEC(18, 18, 0x470, 4), + MTK_PIN_IES_SMT_SPEC(19, 19, 0x470, 5), + MTK_PIN_IES_SMT_SPEC(20, 20, 0x470, 6), + MTK_PIN_IES_SMT_SPEC(21, 21, 0x470, 6), + MTK_PIN_IES_SMT_SPEC(22, 22, 0x470, 7), + MTK_PIN_IES_SMT_SPEC(23, 23, 0x470, 8), + MTK_PIN_IES_SMT_SPEC(24, 24, 0x470, 8), + MTK_PIN_IES_SMT_SPEC(25, 25, 0x470, 8), + MTK_PIN_IES_SMT_SPEC(26, 26, 0x470, 9), + MTK_PIN_IES_SMT_SPEC(27, 27, 0x470, 9), + MTK_PIN_IES_SMT_SPEC(28, 28, 0x470, 9), + MTK_PIN_IES_SMT_SPEC(29, 29, 0x470, 9), + MTK_PIN_IES_SMT_SPEC(30, 30, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(31, 31, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(32, 32, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(34, 34, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(35, 35, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(36, 36, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(37, 37, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(38, 38, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(39, 39, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(40, 40, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(41, 41, 0x470, 12), + MTK_PIN_IES_SMT_SPEC(42, 42, 0x470, 12), + MTK_PIN_IES_SMT_SPEC(43, 43, 0x470, 12), + MTK_PIN_IES_SMT_SPEC(44, 44, 0x470, 12), + MTK_PIN_IES_SMT_SPEC(45, 45, 0x470, 13), + MTK_PIN_IES_SMT_SPEC(46, 46, 0x470, 13), + MTK_PIN_IES_SMT_SPEC(47, 47, 0x470, 13), + MTK_PIN_IES_SMT_SPEC(48, 48, 0x470, 13), + MTK_PIN_IES_SMT_SPEC(49, 49, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(50, 50, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(51, 51, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(52, 52, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(53, 53, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(54, 54, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(55, 55, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(56, 56, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(57, 57, 0x470, 15), + MTK_PIN_IES_SMT_SPEC(58, 58, 0x470, 15), + MTK_PIN_IES_SMT_SPEC(59, 59, 0x470, 16), + MTK_PIN_IES_SMT_SPEC(60, 60, 0x470, 16), + MTK_PIN_IES_SMT_SPEC(61, 61, 0x470, 17), + MTK_PIN_IES_SMT_SPEC(62, 62, 0x470, 17), + MTK_PIN_IES_SMT_SPEC(63, 63, 0x470, 18), + MTK_PIN_IES_SMT_SPEC(64, 64, 0x470, 18), + MTK_PIN_IES_SMT_SPEC(65, 65, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(66, 66, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(67, 67, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(68, 68, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(69, 69, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(70, 70, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(71, 71, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(72, 72, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(73, 73, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(74, 74, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(75, 75, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(76, 76, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(77, 77, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(78, 78, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(79, 79, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(80, 80, 0x470, 21), + MTK_PIN_IES_SMT_SPEC(81, 81, 0x470, 22), + MTK_PIN_IES_SMT_SPEC(82, 82, 0x470, 23), + MTK_PIN_IES_SMT_SPEC(83, 83, 0x470, 24), + MTK_PIN_IES_SMT_SPEC(84, 84, 0x470, 25), + MTK_PIN_IES_SMT_SPEC(85, 85, 0x470, 26), + MTK_PIN_IES_SMT_SPEC(86, 86, 0x470, 27), + MTK_PIN_IES_SMT_SPEC(87, 87, 0x470, 28), + MTK_PIN_IES_SMT_SPEC(88, 88, 0x470, 29), + MTK_PIN_IES_SMT_SPEC(89, 89, 0x470, 30), + MTK_PIN_IES_SMT_SPEC(90, 90, 0x470, 31), + MTK_PIN_IES_SMT_SPEC(91, 91, 0x480, 0), + MTK_PIN_IES_SMT_SPEC(92, 92, 0x480, 1), + MTK_PIN_IES_SMT_SPEC(93, 93, 0x480, 2), + MTK_PIN_IES_SMT_SPEC(94, 94, 0x480, 3), + MTK_PIN_IES_SMT_SPEC(95, 95, 0x480, 4), + MTK_PIN_IES_SMT_SPEC(96, 96, 0x480, 5), + MTK_PIN_IES_SMT_SPEC(97, 97, 0x480, 6), + MTK_PIN_IES_SMT_SPEC(98, 98, 0x480, 7), + MTK_PIN_IES_SMT_SPEC(99, 99, 0x480, 8), + MTK_PIN_IES_SMT_SPEC(100, 100, 0x480, 9), + MTK_PIN_IES_SMT_SPEC(101, 101, 0x480, 10), + MTK_PIN_IES_SMT_SPEC(102, 102, 0x480, 11), + MTK_PIN_IES_SMT_SPEC(103, 103, 0x480, 12), + MTK_PIN_IES_SMT_SPEC(104, 104, 0x480, 13), + MTK_PIN_IES_SMT_SPEC(105, 105, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(106, 106, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(107, 107, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(108, 108, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(109, 109, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(110, 110, 0x480, 15), + MTK_PIN_IES_SMT_SPEC(111, 111, 0x480, 15), + MTK_PIN_IES_SMT_SPEC(112, 112, 0x480, 15), + MTK_PIN_IES_SMT_SPEC(113, 113, 0x480, 15), + MTK_PIN_IES_SMT_SPEC(114, 114, 0x480, 16), + MTK_PIN_IES_SMT_SPEC(115, 115, 0x480, 16), + MTK_PIN_IES_SMT_SPEC(116, 116, 0x480, 16), + MTK_PIN_IES_SMT_SPEC(117, 117, 0x480, 17), + MTK_PIN_IES_SMT_SPEC(118, 118, 0x480, 17), + MTK_PIN_IES_SMT_SPEC(119, 119, 0x480, 17), + MTK_PIN_IES_SMT_SPEC(120, 120, 0x480, 18), + MTK_PIN_IES_SMT_SPEC(121, 121, 0x480, 18), + MTK_PIN_IES_SMT_SPEC(122, 122, 0x480, 18), + MTK_PIN_IES_SMT_SPEC(123, 123, 0x480, 19), + MTK_PIN_IES_SMT_SPEC(124, 124, 0x480, 19), + MTK_PIN_IES_SMT_SPEC(125, 125, 0x480, 19), + MTK_PIN_IES_SMT_SPEC(126, 126, 0x480, 20), + MTK_PIN_IES_SMT_SPEC(127, 127, 0x480, 20), + MTK_PIN_IES_SMT_SPEC(128, 128, 0x480, 20), + MTK_PIN_IES_SMT_SPEC(129, 129, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(130, 130, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(131, 131, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(132, 132, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(133, 133, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(134, 134, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(135, 135, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(136, 136, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(137, 137, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(138, 138, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(139, 139, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(140, 140, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(141, 141, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(142, 142, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(143, 143, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), +}; + +static int mt8365_set_clr_mode(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup) +{ + int ret; + + ret = regmap_update_bits(regmap, reg_pullen, BIT(bit), enable << bit); + if (ret) + return -EINVAL; + + ret = regmap_update_bits(regmap, reg_pullsel, BIT(bit), isup << bit); + if (ret) + return -EINVAL; + + return 0; +} + +static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { + .pins = mtk_pins_mt8365, + .npins = ARRAY_SIZE(mtk_pins_mt8365), + .grp_desc = mt8365_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt8365_drv_grp), + .pin_drv_grp = mt8365_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv), + .spec_ies = mt8365_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8365_ies_set), + .spec_smt = mt8365_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8365_smt_set), + .spec_pupd = mt8365_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, + .mt8365_set_clr_mode = mt8365_set_clr_mode, + .dir_offset = 0x0140, + .dout_offset = 0x00A0, + .din_offset = 0x0000, + .pinmux_offset = 0x01E0, + .ies_offset = 0x0410, + .smt_offset = 0x0470, + .pullen_offset = 0x0860, + .pullsel_offset = 0x0900, + .drv_offset = 0x0710, + .type1_start = 145, + .type1_end = 145, + .port_shf = 4, + .port_mask = 0x1f, + .port_align = 4, + .mode_mask = 0x1f, + .mode_per_reg = 10, + .mode_shf = 5, + .eint_hw = { + .port_mask = 7, + .ports = 5, + .ap_num = 160, + .db_cnt = 160, + .db_time = debounce_time_mt6765, + }, +}; + +static const struct of_device_id mt8365_pctrl_match[] = { + { .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data }, + {} +}; + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mtk_pctrl_common_probe, + .driver = { + .name = "mediatek-mt8365-pinctrl", + .of_match_table = mt8365_pctrl_match, + .pm = &mtk_eint_pm_ops, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} +arch_initcall(mtk_pinctrl_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek MT8365 Pinctrl Driver"); +MODULE_AUTHOR("Zhiyong Tao "); -- cgit v1.2.3