From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 312 ++++++++++++++++++++++++++ 1 file changed, 312 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h (limited to 'drivers/pinctrl/mediatek/pinctrl-mtk-common.h') diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h new file mode 100644 index 000000000..11afa12a9 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -0,0 +1,312 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang + */ + +#ifndef __PINCTRL_MTK_COMMON_H +#define __PINCTRL_MTK_COMMON_H + +#include +#include +#include + +#include "mtk-eint.h" + +#define NO_EINT_SUPPORT 255 +#define MT_EDGE_SENSITIVE 0 +#define MT_LEVEL_SENSITIVE 1 +#define EINT_DBNC_SET_DBNC_BITS 4 +#define EINT_DBNC_RST_BIT (0x1 << 1) +#define EINT_DBNC_SET_EN (0x1 << 0) + +#define MTK_PINCTRL_NOT_SUPPORT (0xffff) + +struct mtk_desc_function { + const char *name; + unsigned char muxval; +}; + +struct mtk_desc_eint { + unsigned char eintmux; + unsigned char eintnum; +}; + +struct mtk_desc_pin { + struct pinctrl_pin_desc pin; + const struct mtk_desc_eint eint; + const struct mtk_desc_function *functions; +}; + +#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ + { \ + .pin = _pin, \ + .eint = _eint, \ + .functions = (struct mtk_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \ + { \ + .eintmux = _eintmux, \ + .eintnum = _eintnum, \ + } + +#define MTK_FUNCTION(_val, _name) \ + { \ + .muxval = _val, \ + .name = _name, \ + } + +#define SET_ADDR(x, y) (x + (y->devdata->port_align)) +#define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1)) + +struct mtk_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +/** + * struct mtk_drv_group_desc - Provide driving group data. + * @max_drv: The maximum current of this group. + * @min_drv: The minimum current of this group. + * @low_bit: The lowest bit of this group. + * @high_bit: The highest bit of this group. + * @step: The step current of this group. + */ +struct mtk_drv_group_desc { + unsigned char min_drv; + unsigned char max_drv; + unsigned char low_bit; + unsigned char high_bit; + unsigned char step; +}; + +#define MTK_DRV_GRP(_min, _max, _low, _high, _step) \ + { \ + .min_drv = _min, \ + .max_drv = _max, \ + .low_bit = _low, \ + .high_bit = _high, \ + .step = _step, \ + } + +/** + * struct mtk_pin_drv_grp - Provide each pin driving info. + * @pin: The pin number. + * @offset: The offset of driving register for this pin. + * @bit: The bit of driving register for this pin. + * @grp: The group for this pin belongs to. + */ +struct mtk_pin_drv_grp { + unsigned short pin; + unsigned short offset; + unsigned char bit; + unsigned char grp; +}; + +#define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ + { \ + .pin = _pin, \ + .offset = _offset, \ + .bit = _bit, \ + .grp = _grp, \ + } + +/** + * struct mtk_pin_spec_pupd_set_samereg + * - For special pins' pull up/down setting which resides in same register + * @pin: The pin number. + * @offset: The offset of special pull up/down setting register. + * @pupd_bit: The pull up/down bit in this register. + * @r0_bit: The r0 bit of pull resistor. + * @r1_bit: The r1 bit of pull resistor. + */ +struct mtk_pin_spec_pupd_set_samereg { + unsigned short pin; + unsigned short offset; + unsigned char pupd_bit; + unsigned char r1_bit; + unsigned char r0_bit; +}; + +#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ + { \ + .pin = _pin, \ + .offset = _offset, \ + .pupd_bit = _pupd, \ + .r1_bit = _r1, \ + .r0_bit = _r0, \ + } + +/** + * struct mtk_pin_ies_set - For special pins' ies and smt setting. + * @start: The start pin number of those special pins. + * @end: The end pin number of those special pins. + * @offset: The offset of special setting register. + * @bit: The bit of special setting register. + */ +struct mtk_pin_ies_smt_set { + unsigned short start; + unsigned short end; + unsigned short offset; + unsigned char bit; +}; + +#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ + { \ + .start = _start, \ + .end = _end, \ + .bit = _bit, \ + .offset = _offset, \ + } + +struct mtk_eint_offsets { + const char *name; + unsigned int stat; + unsigned int ack; + unsigned int mask; + unsigned int mask_set; + unsigned int mask_clr; + unsigned int sens; + unsigned int sens_set; + unsigned int sens_clr; + unsigned int soft; + unsigned int soft_set; + unsigned int soft_clr; + unsigned int pol; + unsigned int pol_set; + unsigned int pol_clr; + unsigned int dom_en; + unsigned int dbnc_ctrl; + unsigned int dbnc_set; + unsigned int dbnc_clr; + u8 port_mask; + u8 ports; +}; + +/** + * struct mtk_pinctrl_devdata - Provide HW GPIO related data. + * @pins: An array describing all pins the pin controller affects. + * @npins: The number of entries in @pins. + * + * @grp_desc: The driving group info. + * @pin_drv_grp: The driving group for all pins. + * @spec_ies: Special pin setting for input enable + * @n_spec_ies: Number of entries in spec_ies + * @spec_pupd: Special pull up/down setting + * @n_spec_pupd: Number of entries in spec_pupd + * @spec_smt: Special pin setting for schmitt + * @n_spec_smt: Number of entries in spec_smt + * @spec_pull_set: Each SoC may have special pins for pull up/down setting, + * these pins' pull setting are very different, they have separate pull + * up/down bit, R0 and R1 resistor bit, so they need special pull setting. + * If special setting is success, this should return 0, otherwise it should + * return non-zero value. + * @spec_ies_smt_set: Some pins are irregular, their input enable and smt + * control register are discontinuous, but they are mapping together. That + * means when user set smt, input enable is set at the same time. So they + * also need special control. If special control is success, this should + * return 0, otherwise return non-zero value. + * @spec_pinmux_set: In some cases, there are two pinmux functions share + * the same value in the same segment of pinmux control register. If user + * want to use one of the two functions, they need an extra bit setting to + * select the right one. + * @spec_dir_set: In very few SoCs, direction control registers are not + * arranged continuously, they may be cut to parts. So they need special + * dir setting. + * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they + * need to use the main R/W register to read/update/write the modes instead of + * the SET/CLR register. + * + * @dir_offset: The direction register offset. + * @pullen_offset: The pull-up/pull-down enable register offset. + * @pinmux_offset: The pinmux register offset. + * + * @type1_start: Some chips have two base addresses for pull select register, + * that means some pins use the first address and others use the second. This + * member record the start of pin number to use the second address. + * @type1_end: The end of pin number to use the second address. + * + * @port_shf: The shift between two registers. + * @port_mask: The mask of register. + * @port_align: Provide clear register and set register step. + */ +struct mtk_pinctrl_devdata { + const struct mtk_desc_pin *pins; + unsigned int npins; + const struct mtk_drv_group_desc *grp_desc; + unsigned int n_grp_cls; + const struct mtk_pin_drv_grp *pin_drv_grp; + unsigned int n_pin_drv_grps; + const struct mtk_pin_ies_smt_set *spec_ies; + unsigned int n_spec_ies; + const struct mtk_pin_spec_pupd_set_samereg *spec_pupd; + unsigned int n_spec_pupd; + const struct mtk_pin_ies_smt_set *spec_smt; + unsigned int n_spec_smt; + int (*spec_pull_set)(struct regmap *regmap, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0); + int (*spec_ies_smt_set)(struct regmap *reg, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, int value, enum pin_config_param arg); + void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, + unsigned int mode); + void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); + int (*mt8365_set_clr_mode)(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup); + unsigned int dir_offset; + unsigned int ies_offset; + unsigned int smt_offset; + unsigned int pullen_offset; + unsigned int pullsel_offset; + unsigned int drv_offset; + unsigned int dout_offset; + unsigned int din_offset; + unsigned int pinmux_offset; + unsigned short type1_start; + unsigned short type1_end; + unsigned char port_shf; + unsigned char port_mask; + unsigned char port_align; + struct mtk_eint_hw eint_hw; + struct mtk_eint_regs *eint_regs; + unsigned int mode_mask; + unsigned int mode_per_reg; + unsigned int mode_shf; +}; + +struct mtk_pinctrl { + struct regmap *regmap1; + struct regmap *regmap2; + struct pinctrl_desc pctl_desc; + struct device *dev; + struct gpio_chip *chip; + struct mtk_pinctrl_group *groups; + unsigned ngroups; + const char **grp_names; + struct pinctrl_dev *pctl_dev; + const struct mtk_pinctrl_devdata *devdata; + struct mtk_eint *eint; +}; + +int mtk_pctrl_init(struct platform_device *pdev, + const struct mtk_pinctrl_devdata *data, + struct regmap *regmap); + +int mtk_pctrl_common_probe(struct platform_device *pdev); + +int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0); + +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, int value, enum pin_config_param arg); + +extern const struct dev_pm_ops mtk_eint_pm_ops; + +#endif /* __PINCTRL_MTK_COMMON_H */ -- cgit v1.2.3