From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/regulator/da9121-regulator.h | 321 +++++++++++++++++++++++++++++++++++ 1 file changed, 321 insertions(+) create mode 100644 drivers/regulator/da9121-regulator.h (limited to 'drivers/regulator/da9121-regulator.h') diff --git a/drivers/regulator/da9121-regulator.h b/drivers/regulator/da9121-regulator.h new file mode 100644 index 000000000..a328a0bdf --- /dev/null +++ b/drivers/regulator/da9121-regulator.h @@ -0,0 +1,321 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * DA9121 Single-channel dual-phase 10A buck converter + * DA9130 Single-channel dual-phase 10A buck converter (Automotive) + * DA9217 Single-channel dual-phase 6A buck converter + * DA9122 Dual-channel single-phase 5A buck converter + * DA9131 Dual-channel single-phase 5A buck converter (Automotive) + * DA9220 Dual-channel single-phase 3A buck converter + * DA9132 Dual-channel single-phase 3A buck converter (Automotive) + * + * Copyright (C) 2020 Dialog Semiconductor + * + * Authors: Steve Twiss, Dialog Semiconductor + * Adam Ward, Dialog Semiconductor + */ + +#ifndef __DA9121_REGISTERS_H__ +#define __DA9121_REGISTERS_H__ + +/* Values for: DA9121_REG_BUCK_BUCKx_4 registers, fields CHx_y_MODE + * DA9121_REG_BUCK_BUCKx_7 registers, fields CHx_RIPPLE_CANCEL + */ +#include + +enum da9121_variant { + DA9121_TYPE_DA9121_DA9130, + DA9121_TYPE_DA9220_DA9132, + DA9121_TYPE_DA9122_DA9131, + DA9121_TYPE_DA9217, + DA9121_TYPE_DA9141, + DA9121_TYPE_DA9142 +}; + +enum da9121_subvariant { + DA9121_SUBTYPE_DA9121, + DA9121_SUBTYPE_DA9130, + DA9121_SUBTYPE_DA9220, + DA9121_SUBTYPE_DA9132, + DA9121_SUBTYPE_DA9122, + DA9121_SUBTYPE_DA9131, + DA9121_SUBTYPE_DA9217, + DA9121_SUBTYPE_DA9141, + DA9121_SUBTYPE_DA9142 +}; + +/* Minimum, maximum and default polling millisecond periods are provided + * here as an example. It is expected that any final implementation will + * include a modification of these settings to match the required + * application. + */ +#define DA9121_DEFAULT_POLLING_PERIOD_MS 3000 +#define DA9121_MAX_POLLING_PERIOD_MS 10000 +#define DA9121_MIN_POLLING_PERIOD_MS 1000 + +/* Registers */ + +#define DA9121_REG_SYS_STATUS_0 0x01 +#define DA9121_REG_SYS_STATUS_1 0x02 +#define DA9121_REG_SYS_STATUS_2 0x03 +#define DA9121_REG_SYS_EVENT_0 0x04 +#define DA9121_REG_SYS_EVENT_1 0x05 +#define DA9121_REG_SYS_EVENT_2 0x06 +#define DA9121_REG_SYS_MASK_0 0x07 +#define DA9121_REG_SYS_MASK_1 0x08 +#define DA9121_REG_SYS_MASK_2 0x09 +#define DA9121_REG_SYS_MASK_3 0x0A +#define DA9121_REG_SYS_CONFIG_0 0x0B +#define DA9121_REG_SYS_CONFIG_1 0x0C +#define DA9121_REG_SYS_CONFIG_2 0x0D +#define DA9121_REG_SYS_CONFIG_3 0x0E +#define DA9121_REG_SYS_GPIO0_0 0x10 +#define DA9121_REG_SYS_GPIO0_1 0x11 +#define DA9121_REG_SYS_GPIO1_0 0x12 +#define DA9121_REG_SYS_GPIO1_1 0x13 +#define DA9121_REG_SYS_GPIO2_0 0x14 +#define DA9121_REG_SYS_GPIO2_1 0x15 +#define DA914x_REG_SYS_GPIO3_0 0x16 +#define DA914x_REG_SYS_GPIO3_1 0x17 +#define DA914x_REG_SYS_GPIO4_0 0x18 +#define DA914x_REG_SYS_GPIO4_1 0x19 +#define DA914x_REG_SYS_ADMUX1_0 0x1A +#define DA914x_REG_SYS_ADMUX1_1 0x1B +#define DA914x_REG_SYS_ADMUX2_0 0x1C +#define DA914x_REG_SYS_ADMUX2_1 0x1D +#define DA9121_REG_BUCK_BUCK1_0 0x20 +#define DA9121_REG_BUCK_BUCK1_1 0x21 +#define DA9121_REG_BUCK_BUCK1_2 0x22 +#define DA9121_REG_BUCK_BUCK1_3 0x23 +#define DA9121_REG_BUCK_BUCK1_4 0x24 +#define DA9121_REG_BUCK_BUCK1_5 0x25 +#define DA9121_REG_BUCK_BUCK1_6 0x26 +#define DA9121_REG_BUCK_BUCK1_7 0x27 +#define DA9xxx_REG_BUCK_BUCK2_0 0x28 +#define DA9xxx_REG_BUCK_BUCK2_1 0x29 +#define DA9xxx_REG_BUCK_BUCK2_2 0x2A +#define DA9xxx_REG_BUCK_BUCK2_3 0x2B +#define DA9xxx_REG_BUCK_BUCK2_4 0x2C +#define DA9xxx_REG_BUCK_BUCK2_5 0x2D +#define DA9xxx_REG_BUCK_BUCK2_6 0x2E +#define DA9xxx_REG_BUCK_BUCK2_7 0x2F +#define DA9121_REG_OTP_DEVICE_ID 0x48 +#define DA9121_REG_OTP_VARIANT_ID 0x49 +#define DA9121_REG_OTP_CUSTOMER_ID 0x4A +#define DA9121_REG_OTP_CONFIG_ID 0x4B + +/* Register bits */ + +/* DA9121_REG_SYS_STATUS_0 */ + +#define DA9xxx_MASK_SYS_STATUS_0_SG BIT(2) +#define DA9121_MASK_SYS_STATUS_0_TEMP_CRIT BIT(1) +#define DA9121_MASK_SYS_STATUS_0_TEMP_WARN BIT(0) + +/* DA9121_REG_SYS_STATUS_1 */ + +#define DA9xxx_MASK_SYS_STATUS_1_PG2 BIT(7) +#define DA9xxx_MASK_SYS_STATUS_1_OV2 BIT(6) +#define DA9xxx_MASK_SYS_STATUS_1_UV2 BIT(5) +#define DA9xxx_MASK_SYS_STATUS_1_OC2 BIT(4) +#define DA9121_MASK_SYS_STATUS_1_PG1 BIT(3) +#define DA9121_MASK_SYS_STATUS_1_OV1 BIT(2) +#define DA9121_MASK_SYS_STATUS_1_UV1 BIT(1) +#define DA9121_MASK_SYS_STATUS_1_OC1 BIT(0) + +/* DA9121_REG_SYS_STATUS_2 */ + +#define DA9121_MASK_SYS_STATUS_2_GPIO2 BIT(2) +#define DA9121_MASK_SYS_STATUS_2_GPIO1 BIT(1) +#define DA9121_MASK_SYS_STATUS_2_GPIO0 BIT(0) + +/* DA9121_REG_SYS_EVENT_0 */ + +#define DA9xxx_MASK_SYS_EVENT_0_E_SG BIT(2) +#define DA9121_MASK_SYS_EVENT_0_E_TEMP_CRIT BIT(1) +#define DA9121_MASK_SYS_EVENT_0_E_TEMP_WARN BIT(0) + +/* DA9121_REG_SYS_EVENT_1 */ + +#define DA9xxx_MASK_SYS_EVENT_1_E_PG2 BIT(7) +#define DA9xxx_MASK_SYS_EVENT_1_E_OV2 BIT(6) +#define DA9xxx_MASK_SYS_EVENT_1_E_UV2 BIT(5) +#define DA9xxx_MASK_SYS_EVENT_1_E_OC2 BIT(4) +#define DA9121_MASK_SYS_EVENT_1_E_PG1 BIT(3) +#define DA9121_MASK_SYS_EVENT_1_E_OV1 BIT(2) +#define DA9121_MASK_SYS_EVENT_1_E_UV1 BIT(1) +#define DA9121_MASK_SYS_EVENT_1_E_OC1 BIT(0) + +/* DA9121_REG_SYS_EVENT_2 */ + +#define DA9121_MASK_SYS_EVENT_2_E_GPIO2 BIT(2) +#define DA9121_MASK_SYS_EVENT_2_E_GPIO1 BIT(1) +#define DA9121_MASK_SYS_EVENT_2_E_GPIO0 BIT(0) + +/* DA9121_REG_SYS_MASK_0 */ + +#define DA9xxx_MASK_SYS_MASK_0_M_SG BIT(2) +#define DA9121_MASK_SYS_MASK_0_M_TEMP_CRIT BIT(1) +#define DA9121_MASK_SYS_MASK_0_M_TEMP_WARN BIT(0) + +/* DA9121_REG_SYS_MASK_1 */ + +#define DA9xxx_MASK_SYS_MASK_1_M_PG2 BIT(7) +#define DA9xxx_MASK_SYS_MASK_1_M_OV2 BIT(6) +#define DA9xxx_MASK_SYS_MASK_1_M_UV2 BIT(5) +#define DA9xxx_MASK_SYS_MASK_1_M_OC2 BIT(4) +#define DA9121_MASK_SYS_MASK_1_M_PG1 BIT(3) +#define DA9121_MASK_SYS_MASK_1_M_OV1 BIT(2) +#define DA9121_MASK_SYS_MASK_1_M_UV1 BIT(1) +#define DA9121_MASK_SYS_MASK_1_M_OC1 BIT(0) + +/* DA9121_REG_SYS_MASK_2 */ + +#define DA9121_MASK_SYS_MASK_2_M_GPIO2 BIT(2) +#define DA9121_MASK_SYS_MASK_2_M_GPIO1 BIT(1) +#define DA9121_MASK_SYS_MASK_2_M_GPIO0 BIT(0) + +/* DA9122_REG_SYS_MASK_3 */ + +#define DA9121_MASK_SYS_MASK_3_M_VR_HOT BIT(3) +#define DA9xxx_MASK_SYS_MASK_3_M_SG_STAT BIT(2) +#define DA9xxx_MASK_SYS_MASK_3_M_PG2_STAT BIT(1) +#define DA9121_MASK_SYS_MASK_3_M_PG1_STAT BIT(0) + +/* DA9121_REG_SYS_CONFIG_0 */ + +#define DA9121_MASK_SYS_CONFIG_0_CH1_DIS_DLY 0xF0 +#define DA9121_MASK_SYS_CONFIG_0_CH1_EN_DLY 0x0F + +/* DA9xxx_REG_SYS_CONFIG_1 */ + +#define DA9xxx_MASK_SYS_CONFIG_1_CH2_DIS_DLY 0xF0 +#define DA9xxx_MASK_SYS_CONFIG_1_CH2_EN_DLY 0x0F + +/* DA9121_REG_SYS_CONFIG_2 */ + +#define DA9121_MASK_SYS_CONFIG_2_OC_LATCHOFF 0x60 +#define DA9121_MASK_SYS_CONFIG_2_OC_DVC_MASK BIT(4) +#define DA9121_MASK_SYS_CONFIG_2_PG_DVC_MASK 0x0C + +/* DA9121_REG_SYS_CONFIG_3 */ + +#define DA9121_MASK_SYS_CONFIG_3_OSC_TUNE 0X70 +#define DA9121_MASK_SYS_CONFIG_3_I2C_TIMEOUT BIT(1) + +/* DA9121_REG_SYS_GPIO0_0 */ + +#define DA9121_MASK_SYS_GPIO0_0_GPIO0_MODE 0X1E +#define DA9121_MASK_SYS_GPIO0_0_GPIO0_OBUF BIT(0) + +/* DA9121_REG_SYS_GPIO0_1 */ + +#define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_FALL BIT(7) +#define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_RISE BIT(6) +#define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB 0x30 +#define DA9121_MASK_SYS_GPIO0_1_GPIO0_PUPD BIT(3) +#define DA9121_MASK_SYS_GPIO0_1_GPIO0_POL BIT(2) +#define DA9121_MASK_SYS_GPIO0_1_GPIO0_TRIG 0x03 + +/* DA9121_REG_SYS_GPIO1_0 */ + +#define DA9121_MASK_SYS_GPIO1_0_GPIO1_MODE 0x1E +#define DA9121_MASK_SYS_GPIO1_0_GPIO1_OBUF BIT(0) + +/* DA9121_REG_SYS_GPIO1_1 */ + +#define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_FALL BIT(7) +#define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_RISE BIT(6) +#define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB 0x30 +#define DA9121_MASK_SYS_GPIO1_1_GPIO1_PUPD BIT(3) +#define DA9121_MASK_SYS_GPIO1_1_GPIO1_POL BIT(2) +#define DA9121_MASK_SYS_GPIO1_1_GPIO1_TRIG 0x03 + +/* DA9121_REG_SYS_GPIO2_0 */ + +#define DA9121_MASK_SYS_GPIO2_0_GPIO2_MODE 0x1E +#define DA9121_MASK_SYS_GPIO2_0_GPIO2_OBUF BIT(0) + +/* DA9121_REG_SYS_GPIO2_1 */ + +#define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_FALL BIT(7) +#define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_RISE BIT(6) +#define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB 0x30 +#define DA9121_MASK_SYS_GPIO2_1_GPIO2_PUPD BIT(3) +#define DA9121_MASK_SYS_GPIO2_1_GPIO2_POL BIT(2) +#define DA9121_MASK_SYS_GPIO2_1_GPIO2_TRIG 0x03 + +/* DA9121_REG_BUCK_BUCK1_0 / DA9xxx_REG_BUCK_BUCK2_0 */ + +#define DA9121_MASK_BUCK_BUCKx_0_CHx_SR_DVC_DWN 0x70 +#define DA9121_MASK_BUCK_BUCKx_0_CHx_SR_DVC_UP 0x0E +#define DA9121_MASK_BUCK_BUCKx_0_CHx_EN BIT(0) + +/* DA9121_REG_BUCK_BUCK1_1 / DA9xxx_REG_BUCK_BUCK2_1 */ + +#define DA9121_MASK_BUCK_BUCKx_1_CHx_SR_SHDN 0x70 +#define DA9121_MASK_BUCK_BUCKx_1_CHx_SR_STARTUP 0x0E +#define DA9121_MASK_BUCK_BUCKx_1_CHx_PD_DIS BIT(0) + +/* DA9121_REG_BUCK_BUCK1_2 / DA9xxx_REG_BUCK_BUCK2_2 */ + +#define DA9121_MASK_BUCK_BUCKx_2_CHx_ILIM 0x0F + +/* DA9121_REG_BUCK_BUCK1_3 / DA9xxx_REG_BUCK_BUCK2_3 */ + +#define DA9121_MASK_BUCK_BUCKx_3_CHx_VMAX 0xFF + +/* DA9121_REG_BUCK_BUCK1_4 / DA9xxx_REG_BUCK_BUCK2_4 */ + +#define DA9121_MASK_BUCK_BUCKx_4_CHx_VSEL BIT(4) +#define DA9121_MASK_BUCK_BUCKx_4_CHx_B_MODE 0x0C +#define DA9121_MASK_BUCK_BUCKx_4_CHx_A_MODE 0x03 + +/* DA9121_REG_BUCK_BUCK1_5 / DA9xxx_REG_BUCK_BUCK2_5 */ + +#define DA9121_MASK_BUCK_BUCKx_5_CHx_A_VOUT 0xFF + +/* DA9121_REG_BUCK_BUCK1_6 / DA9xxx_REG_BUCK_BUCK2_6 */ + +#define DA9121_MASK_BUCK_BUCKx_6_CHx_B_VOUT 0xFF + +/* DA9121_REG_BUCK_BUCK1_7 / DA9xxx_REG_BUCK_BUCK2_7 */ + +#define DA9xxx_MASK_BUCK_BUCKx_7_CHx_RIPPLE_CANCEL 0x03 + + +/* DA9121_REG_OTP_DEVICE_ID */ + +#define DA9121_MASK_OTP_DEVICE_ID_DEV_ID 0xFF + +#define DA9121_DEVICE_ID 0x05 +#define DA914x_DEVICE_ID 0x26 + +/* DA9121_REG_OTP_VARIANT_ID */ + +#define DA9121_SHIFT_OTP_VARIANT_ID_MRC 4 +#define DA9121_MASK_OTP_VARIANT_ID_MRC 0xF0 +#define DA9121_SHIFT_OTP_VARIANT_ID_VRC 0 +#define DA9121_MASK_OTP_VARIANT_ID_VRC 0x0F + +#define DA9121_VARIANT_MRC_BASE 0x2 +#define DA9121_VARIANT_VRC 0x1 +#define DA9220_VARIANT_VRC 0x0 +#define DA9122_VARIANT_VRC 0x2 +#define DA9217_VARIANT_VRC 0x7 +#define DA9130_VARIANT_VRC 0x0 +#define DA9131_VARIANT_VRC 0x1 +#define DA9132_VARIANT_VRC 0x2 + +#define DA914x_VARIANT_MRC_BASE 0x0 +#define DA9141_VARIANT_VRC 0x1 +#define DA9142_VARIANT_VRC 0x2 + +/* DA9121_REG_OTP_CUSTOMER_ID */ + +#define DA9121_MASK_OTP_CUSTOMER_ID_CUST_ID 0xFF + +/* DA9121_REG_OTP_CONFIG_ID */ + +#define DA9121_MASK_OTP_CONFIG_ID_CONFIG_REV 0xFF + +#endif /* __DA9121_REGISTERS_H__ */ -- cgit v1.2.3