From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/regulator/mt6380-regulator.c | 341 +++++++++++++++++++++++++++++++++++ 1 file changed, 341 insertions(+) create mode 100644 drivers/regulator/mt6380-regulator.c (limited to 'drivers/regulator/mt6380-regulator.c') diff --git a/drivers/regulator/mt6380-regulator.c b/drivers/regulator/mt6380-regulator.c new file mode 100644 index 000000000..43234296d --- /dev/null +++ b/drivers/regulator/mt6380-regulator.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2017 MediaTek Inc. +// Author: Chenglin Xu + +#include +#include +#include +#include +#include +#include +#include +#include + +/* PMIC Registers */ +#define MT6380_ALDO_CON_0 0x0000 +#define MT6380_BTLDO_CON_0 0x0004 +#define MT6380_COMP_CON_0 0x0008 +#define MT6380_CPUBUCK_CON_0 0x000C +#define MT6380_CPUBUCK_CON_1 0x0010 +#define MT6380_CPUBUCK_CON_2 0x0014 +#define MT6380_DDRLDO_CON_0 0x0018 +#define MT6380_MLDO_CON_0 0x001C +#define MT6380_PALDO_CON_0 0x0020 +#define MT6380_PHYLDO_CON_0 0x0024 +#define MT6380_SIDO_CON_0 0x0028 +#define MT6380_SIDO_CON_1 0x002C +#define MT6380_SIDO_CON_2 0x0030 +#define MT6380_SLDO_CON_0 0x0034 +#define MT6380_TLDO_CON_0 0x0038 +#define MT6380_STARTUP_CON_0 0x003C +#define MT6380_STARTUP_CON_1 0x0040 +#define MT6380_SMPS_TOP_CON_0 0x0044 +#define MT6380_SMPS_TOP_CON_1 0x0048 +#define MT6380_ANA_CTRL_0 0x0050 +#define MT6380_ANA_CTRL_1 0x0054 +#define MT6380_ANA_CTRL_2 0x0058 +#define MT6380_ANA_CTRL_3 0x005C +#define MT6380_ANA_CTRL_4 0x0060 +#define MT6380_SPK_CON9 0x0064 +#define MT6380_SPK_CON11 0x0068 +#define MT6380_SPK_CON12 0x006A +#define MT6380_CLK_CTRL 0x0070 +#define MT6380_PINMUX_CTRL 0x0074 +#define MT6380_IO_CTRL 0x0078 +#define MT6380_SLP_MODE_CTRL_0 0x007C +#define MT6380_SLP_MODE_CTRL_1 0x0080 +#define MT6380_SLP_MODE_CTRL_2 0x0084 +#define MT6380_SLP_MODE_CTRL_3 0x0088 +#define MT6380_SLP_MODE_CTRL_4 0x008C +#define MT6380_SLP_MODE_CTRL_5 0x0090 +#define MT6380_SLP_MODE_CTRL_6 0x0094 +#define MT6380_SLP_MODE_CTRL_7 0x0098 +#define MT6380_SLP_MODE_CTRL_8 0x009C +#define MT6380_FCAL_CTRL_0 0x00A0 +#define MT6380_FCAL_CTRL_1 0x00A4 +#define MT6380_LDO_CTRL_0 0x00A8 +#define MT6380_LDO_CTRL_1 0x00AC +#define MT6380_LDO_CTRL_2 0x00B0 +#define MT6380_LDO_CTRL_3 0x00B4 +#define MT6380_LDO_CTRL_4 0x00B8 +#define MT6380_DEBUG_CTRL_0 0x00BC +#define MT6380_EFU_CTRL_0 0x0200 +#define MT6380_EFU_CTRL_1 0x0201 +#define MT6380_EFU_CTRL_2 0x0202 +#define MT6380_EFU_CTRL_3 0x0203 +#define MT6380_EFU_CTRL_4 0x0204 +#define MT6380_EFU_CTRL_5 0x0205 +#define MT6380_EFU_CTRL_6 0x0206 +#define MT6380_EFU_CTRL_7 0x0207 +#define MT6380_EFU_CTRL_8 0x0208 + +#define MT6380_REGULATOR_MODE_AUTO 0 +#define MT6380_REGULATOR_MODE_FORCE_PWM 1 + +/* + * mt6380 regulators' information + * + * @desc: standard fields of regulator description + * @vselon_reg: Register sections for hardware control mode of bucks + * @modeset_reg: Register for controlling the buck/LDO control mode + * @modeset_mask: Mask for controlling the buck/LDO control mode + */ +struct mt6380_regulator_info { + struct regulator_desc desc; + u32 vselon_reg; + u32 modeset_reg; + u32 modeset_mask; +}; + +#define MT6380_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, enbit, voselon, _modeset_reg, \ + _modeset_mask) \ +[MT6380_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6380_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6380_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + }, \ + .vselon_reg = voselon, \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +#define MT6380_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ + vosel_mask, _modeset_reg, _modeset_mask) \ +[MT6380_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6380_volt_table_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6380_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + }, \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +#define MT6380_REG_FIXED(match, vreg, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask) \ +[MT6380_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6380_volt_fixed_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6380_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + .min_uV = volt, \ + }, \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +static const struct linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250), +}; + +static const struct linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250), +}; + +static const struct linear_range buck_volt_range3[] = { + REGULATOR_LINEAR_RANGE(1200000, 0, 0x3c, 25000), +}; + +static const unsigned int ldo_volt_table1[] = { + 1400000, 1350000, 1300000, 1250000, 1200000, 1150000, 1100000, 1050000, +}; + +static const unsigned int ldo_volt_table2[] = { + 2200000, 3300000, +}; + +static const unsigned int ldo_volt_table3[] = { + 1240000, 1390000, 1540000, 1840000, +}; + +static const unsigned int ldo_volt_table4[] = { + 2200000, 3300000, +}; + +static int mt6380_regulator_set_mode(struct regulator_dev *rdev, + unsigned int mode) +{ + int val = 0; + struct mt6380_regulator_info *info = rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_NORMAL: + val = MT6380_REGULATOR_MODE_AUTO; + break; + case REGULATOR_MODE_FAST: + val = MT6380_REGULATOR_MODE_FORCE_PWM; + break; + default: + return -EINVAL; + } + + val <<= ffs(info->modeset_mask) - 1; + + return regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); +} + +static unsigned int mt6380_regulator_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6380_regulator_info *info = rdev_get_drvdata(rdev); + + ret = regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &= info->modeset_mask; + val >>= ffs(info->modeset_mask) - 1; + + switch (val) { + case MT6380_REGULATOR_MODE_AUTO: + mode = REGULATOR_MODE_NORMAL; + break; + case MT6380_REGULATOR_MODE_FORCE_PWM: + mode = REGULATOR_MODE_FAST; + break; + default: + return -EINVAL; + } + + return mode; +} + +static const struct regulator_ops mt6380_volt_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_mode = mt6380_regulator_set_mode, + .get_mode = mt6380_regulator_get_mode, +}; + +static const struct regulator_ops mt6380_volt_table_ops = { + .list_voltage = regulator_list_voltage_table, + .map_voltage = regulator_map_voltage_iterate, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_mode = mt6380_regulator_set_mode, + .get_mode = mt6380_regulator_get_mode, +}; + +static const struct regulator_ops mt6380_volt_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_mode = mt6380_regulator_set_mode, + .get_mode = mt6380_regulator_get_mode, +}; + +/* The array is indexed by id(MT6380_ID_XXX) */ +static struct mt6380_regulator_info mt6380_regulators[] = { + MT6380_BUCK("buck-vcore1", VCPU, 600000, 1393750, 6250, + buck_volt_range1, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_1, + 0xfe, 3, MT6380_ANA_CTRL_1, + MT6380_CPUBUCK_CON_0, 0x8000000), + MT6380_BUCK("buck-vcore", VCORE, 600000, 1393750, 6250, + buck_volt_range2, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_2, + 0xfe, 2, MT6380_ANA_CTRL_2, MT6380_SIDO_CON_0, 0x1000000), + MT6380_BUCK("buck-vrf", VRF, 1200000, 1575000, 25000, + buck_volt_range3, MT6380_ANA_CTRL_3, MT6380_SIDO_CON_0, + 0x78, 1, MT6380_SIDO_CON_0, MT6380_SIDO_CON_0, 0x8000), + MT6380_LDO("ldo-vm", VMLDO, ldo_volt_table1, MT6380_LDO_CTRL_0, + 1, MT6380_MLDO_CON_0, 0xE000, MT6380_ANA_CTRL_1, 0x4000000), + MT6380_LDO("ldo-va", VALDO, ldo_volt_table2, MT6380_LDO_CTRL_0, + 2, MT6380_ALDO_CON_0, 0x400, MT6380_ALDO_CON_0, 0x20), + MT6380_REG_FIXED("ldo-vphy", VPHYLDO, MT6380_LDO_CTRL_0, 7, 1800000, + MT6380_PHYLDO_CON_0, 0x80), + MT6380_LDO("ldo-vddr", VDDRLDO, ldo_volt_table3, MT6380_LDO_CTRL_0, + 8, MT6380_DDRLDO_CON_0, 0x3000, MT6380_DDRLDO_CON_0, 0x80), + MT6380_LDO("ldo-vt", VTLDO, ldo_volt_table4, MT6380_LDO_CTRL_0, 3, + MT6380_TLDO_CON_0, 0x400, MT6380_TLDO_CON_0, 0x20), +}; + +static int mt6380_regulator_probe(struct platform_device *pdev) +{ + struct regmap *regmap = dev_get_regmap(pdev->dev.parent, NULL); + struct regulator_config config = {}; + struct regulator_dev *rdev; + int i; + + for (i = 0; i < MT6380_MAX_REGULATOR; i++) { + config.dev = &pdev->dev; + config.driver_data = &mt6380_regulators[i]; + config.regmap = regmap; + rdev = devm_regulator_register(&pdev->dev, + &mt6380_regulators[i].desc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6380_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + return 0; +} + +static const struct platform_device_id mt6380_platform_ids[] = { + {"mt6380-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6380_platform_ids); + +static const struct of_device_id __maybe_unused mt6380_of_match[] = { + { .compatible = "mediatek,mt6380-regulator", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, mt6380_of_match); + +static struct platform_driver mt6380_regulator_driver = { + .driver = { + .name = "mt6380-regulator", + .of_match_table = of_match_ptr(mt6380_of_match), + }, + .probe = mt6380_regulator_probe, + .id_table = mt6380_platform_ids, +}; + +module_platform_driver(mt6380_regulator_driver); + +MODULE_AUTHOR("Chenglin Xu "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6380 PMIC"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3