From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/ssb/driver_gpio.c | 478 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 insertions(+) create mode 100644 drivers/ssb/driver_gpio.c (limited to 'drivers/ssb/driver_gpio.c') diff --git a/drivers/ssb/driver_gpio.c b/drivers/ssb/driver_gpio.c new file mode 100644 index 000000000..897cb8db5 --- /dev/null +++ b/drivers/ssb/driver_gpio.c @@ -0,0 +1,478 @@ +/* + * Sonics Silicon Backplane + * GPIO driver + * + * Copyright 2011, Broadcom Corporation + * Copyright 2012, Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include "ssb_private.h" + +#include +#include +#include +#include +#include +#include + + +/************************************************** + * Shared + **************************************************/ + +#if IS_ENABLED(CONFIG_SSB_EMBEDDED) +static int ssb_gpio_to_irq(struct gpio_chip *chip, unsigned int gpio) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + if (bus->bustype == SSB_BUSTYPE_SSB) + return irq_find_mapping(bus->irq_domain, gpio); + else + return -EINVAL; +} +#endif + +/************************************************** + * ChipCommon + **************************************************/ + +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned int gpio) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio); +} + +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned int gpio, + int value) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0); +} + +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip, + unsigned int gpio) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0); + return 0; +} + +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip, + unsigned int gpio, int value) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio); + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0); + return 0; +} + +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned int gpio) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0); + /* clear pulldown */ + ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0); + /* Set pullup */ + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio); + + return 0; +} + +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned int gpio) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + /* clear pullup */ + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0); +} + +#if IS_ENABLED(CONFIG_SSB_EMBEDDED) +static void ssb_gpio_irq_chipco_mask(struct irq_data *d) +{ + struct ssb_bus *bus = irq_data_get_irq_chip_data(d); + int gpio = irqd_to_hwirq(d); + + ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), 0); +} + +static void ssb_gpio_irq_chipco_unmask(struct irq_data *d) +{ + struct ssb_bus *bus = irq_data_get_irq_chip_data(d); + int gpio = irqd_to_hwirq(d); + u32 val = ssb_chipco_gpio_in(&bus->chipco, BIT(gpio)); + + ssb_chipco_gpio_polarity(&bus->chipco, BIT(gpio), val); + ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), BIT(gpio)); +} + +static struct irq_chip ssb_gpio_irq_chipco_chip = { + .name = "SSB-GPIO-CC", + .irq_mask = ssb_gpio_irq_chipco_mask, + .irq_unmask = ssb_gpio_irq_chipco_unmask, +}; + +static irqreturn_t ssb_gpio_irq_chipco_handler(int irq, void *dev_id) +{ + struct ssb_bus *bus = dev_id; + struct ssb_chipcommon *chipco = &bus->chipco; + u32 val = chipco_read32(chipco, SSB_CHIPCO_GPIOIN); + u32 mask = chipco_read32(chipco, SSB_CHIPCO_GPIOIRQ); + u32 pol = chipco_read32(chipco, SSB_CHIPCO_GPIOPOL); + unsigned long irqs = (val ^ pol) & mask; + int gpio; + + if (!irqs) + return IRQ_NONE; + + for_each_set_bit(gpio, &irqs, bus->gpio.ngpio) + generic_handle_domain_irq_safe(bus->irq_domain, gpio); + + ssb_chipco_gpio_polarity(chipco, irqs, val & irqs); + + return IRQ_HANDLED; +} + +static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus) +{ + struct ssb_chipcommon *chipco = &bus->chipco; + struct gpio_chip *chip = &bus->gpio; + int gpio, hwirq, err; + + if (bus->bustype != SSB_BUSTYPE_SSB) + return 0; + + bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio, + &irq_domain_simple_ops, chipco); + if (!bus->irq_domain) { + err = -ENODEV; + goto err_irq_domain; + } + for (gpio = 0; gpio < chip->ngpio; gpio++) { + int irq = irq_create_mapping(bus->irq_domain, gpio); + + irq_set_chip_data(irq, bus); + irq_set_chip_and_handler(irq, &ssb_gpio_irq_chipco_chip, + handle_simple_irq); + } + + hwirq = ssb_mips_irq(bus->chipco.dev) + 2; + err = request_irq(hwirq, ssb_gpio_irq_chipco_handler, IRQF_SHARED, + "gpio", bus); + if (err) + goto err_req_irq; + + ssb_chipco_gpio_intmask(&bus->chipco, ~0, 0); + chipco_set32(chipco, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO); + + return 0; + +err_req_irq: + for (gpio = 0; gpio < chip->ngpio; gpio++) { + int irq = irq_find_mapping(bus->irq_domain, gpio); + + irq_dispose_mapping(irq); + } + irq_domain_remove(bus->irq_domain); +err_irq_domain: + return err; +} + +static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus) +{ + struct ssb_chipcommon *chipco = &bus->chipco; + struct gpio_chip *chip = &bus->gpio; + int gpio; + + if (bus->bustype != SSB_BUSTYPE_SSB) + return; + + chipco_mask32(chipco, SSB_CHIPCO_IRQMASK, ~SSB_CHIPCO_IRQ_GPIO); + free_irq(ssb_mips_irq(bus->chipco.dev) + 2, chipco); + for (gpio = 0; gpio < chip->ngpio; gpio++) { + int irq = irq_find_mapping(bus->irq_domain, gpio); + + irq_dispose_mapping(irq); + } + irq_domain_remove(bus->irq_domain); +} +#else +static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus) +{ + return 0; +} + +static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus) +{ +} +#endif + +static int ssb_gpio_chipco_init(struct ssb_bus *bus) +{ + struct gpio_chip *chip = &bus->gpio; + int err; + + chip->label = "ssb_chipco_gpio"; + chip->owner = THIS_MODULE; + chip->request = ssb_gpio_chipco_request; + chip->free = ssb_gpio_chipco_free; + chip->get = ssb_gpio_chipco_get_value; + chip->set = ssb_gpio_chipco_set_value; + chip->direction_input = ssb_gpio_chipco_direction_input; + chip->direction_output = ssb_gpio_chipco_direction_output; +#if IS_ENABLED(CONFIG_SSB_EMBEDDED) + chip->to_irq = ssb_gpio_to_irq; +#endif + chip->ngpio = 16; + /* There is just one SoC in one device and its GPIO addresses should be + * deterministic to address them more easily. The other buses could get + * a random base number. + */ + if (bus->bustype == SSB_BUSTYPE_SSB) + chip->base = 0; + else + chip->base = -1; + + err = ssb_gpio_irq_chipco_domain_init(bus); + if (err) + return err; + + err = gpiochip_add_data(chip, bus); + if (err) { + ssb_gpio_irq_chipco_domain_exit(bus); + return err; + } + + return 0; +} + +/************************************************** + * EXTIF + **************************************************/ + +#ifdef CONFIG_SSB_DRIVER_EXTIF + +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned int gpio) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio); +} + +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned int gpio, + int value) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0); +} + +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip, + unsigned int gpio) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0); + return 0; +} + +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip, + unsigned int gpio, int value) +{ + struct ssb_bus *bus = gpiochip_get_data(chip); + + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio); + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0); + return 0; +} + +#if IS_ENABLED(CONFIG_SSB_EMBEDDED) +static void ssb_gpio_irq_extif_mask(struct irq_data *d) +{ + struct ssb_bus *bus = irq_data_get_irq_chip_data(d); + int gpio = irqd_to_hwirq(d); + + ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), 0); +} + +static void ssb_gpio_irq_extif_unmask(struct irq_data *d) +{ + struct ssb_bus *bus = irq_data_get_irq_chip_data(d); + int gpio = irqd_to_hwirq(d); + u32 val = ssb_extif_gpio_in(&bus->extif, BIT(gpio)); + + ssb_extif_gpio_polarity(&bus->extif, BIT(gpio), val); + ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), BIT(gpio)); +} + +static struct irq_chip ssb_gpio_irq_extif_chip = { + .name = "SSB-GPIO-EXTIF", + .irq_mask = ssb_gpio_irq_extif_mask, + .irq_unmask = ssb_gpio_irq_extif_unmask, +}; + +static irqreturn_t ssb_gpio_irq_extif_handler(int irq, void *dev_id) +{ + struct ssb_bus *bus = dev_id; + struct ssb_extif *extif = &bus->extif; + u32 val = ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN); + u32 mask = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTMASK); + u32 pol = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTPOL); + unsigned long irqs = (val ^ pol) & mask; + int gpio; + + if (!irqs) + return IRQ_NONE; + + for_each_set_bit(gpio, &irqs, bus->gpio.ngpio) + generic_handle_domain_irq_safe(bus->irq_domain, gpio); + + ssb_extif_gpio_polarity(extif, irqs, val & irqs); + + return IRQ_HANDLED; +} + +static int ssb_gpio_irq_extif_domain_init(struct ssb_bus *bus) +{ + struct ssb_extif *extif = &bus->extif; + struct gpio_chip *chip = &bus->gpio; + int gpio, hwirq, err; + + if (bus->bustype != SSB_BUSTYPE_SSB) + return 0; + + bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio, + &irq_domain_simple_ops, extif); + if (!bus->irq_domain) { + err = -ENODEV; + goto err_irq_domain; + } + for (gpio = 0; gpio < chip->ngpio; gpio++) { + int irq = irq_create_mapping(bus->irq_domain, gpio); + + irq_set_chip_data(irq, bus); + irq_set_chip_and_handler(irq, &ssb_gpio_irq_extif_chip, + handle_simple_irq); + } + + hwirq = ssb_mips_irq(bus->extif.dev) + 2; + err = request_irq(hwirq, ssb_gpio_irq_extif_handler, IRQF_SHARED, + "gpio", bus); + if (err) + goto err_req_irq; + + ssb_extif_gpio_intmask(&bus->extif, ~0, 0); + + return 0; + +err_req_irq: + for (gpio = 0; gpio < chip->ngpio; gpio++) { + int irq = irq_find_mapping(bus->irq_domain, gpio); + + irq_dispose_mapping(irq); + } + irq_domain_remove(bus->irq_domain); +err_irq_domain: + return err; +} + +static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus) +{ + struct ssb_extif *extif = &bus->extif; + struct gpio_chip *chip = &bus->gpio; + int gpio; + + if (bus->bustype != SSB_BUSTYPE_SSB) + return; + + free_irq(ssb_mips_irq(bus->extif.dev) + 2, extif); + for (gpio = 0; gpio < chip->ngpio; gpio++) { + int irq = irq_find_mapping(bus->irq_domain, gpio); + + irq_dispose_mapping(irq); + } + irq_domain_remove(bus->irq_domain); +} +#else +static int ssb_gpio_irq_extif_domain_init(struct ssb_bus *bus) +{ + return 0; +} + +static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus) +{ +} +#endif + +static int ssb_gpio_extif_init(struct ssb_bus *bus) +{ + struct gpio_chip *chip = &bus->gpio; + int err; + + chip->label = "ssb_extif_gpio"; + chip->owner = THIS_MODULE; + chip->get = ssb_gpio_extif_get_value; + chip->set = ssb_gpio_extif_set_value; + chip->direction_input = ssb_gpio_extif_direction_input; + chip->direction_output = ssb_gpio_extif_direction_output; +#if IS_ENABLED(CONFIG_SSB_EMBEDDED) + chip->to_irq = ssb_gpio_to_irq; +#endif + chip->ngpio = 5; + /* There is just one SoC in one device and its GPIO addresses should be + * deterministic to address them more easily. The other buses could get + * a random base number. + */ + if (bus->bustype == SSB_BUSTYPE_SSB) + chip->base = 0; + else + chip->base = -1; + + err = ssb_gpio_irq_extif_domain_init(bus); + if (err) + return err; + + err = gpiochip_add_data(chip, bus); + if (err) { + ssb_gpio_irq_extif_domain_exit(bus); + return err; + } + + return 0; +} + +#else +static int ssb_gpio_extif_init(struct ssb_bus *bus) +{ + return -ENOTSUPP; +} +#endif + +/************************************************** + * Init + **************************************************/ + +int ssb_gpio_init(struct ssb_bus *bus) +{ + if (ssb_chipco_available(&bus->chipco)) + return ssb_gpio_chipco_init(bus); + else if (ssb_extif_available(&bus->extif)) + return ssb_gpio_extif_init(bus); + return -1; +} + +int ssb_gpio_unregister(struct ssb_bus *bus) +{ + if (ssb_chipco_available(&bus->chipco) || + ssb_extif_available(&bus->extif)) { + gpiochip_remove(&bus->gpio); + return 0; + } + return -1; +} -- cgit v1.2.3