From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/staging/media/max96712/Kconfig | 14 + drivers/staging/media/max96712/Makefile | 2 + drivers/staging/media/max96712/max96712.c | 438 ++++++++++++++++++++++++++++++ 3 files changed, 454 insertions(+) create mode 100644 drivers/staging/media/max96712/Kconfig create mode 100644 drivers/staging/media/max96712/Makefile create mode 100644 drivers/staging/media/max96712/max96712.c (limited to 'drivers/staging/media/max96712') diff --git a/drivers/staging/media/max96712/Kconfig b/drivers/staging/media/max96712/Kconfig new file mode 100644 index 000000000..117fadf81 --- /dev/null +++ b/drivers/staging/media/max96712/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 +config VIDEO_MAX96712 + tristate "Maxim MAX96712 Quad GMSL2 Deserializer support" + depends on I2C + depends on OF_GPIO + depends on VIDEO_DEV + select V4L2_FWNODE + select VIDEO_V4L2_SUBDEV_API + select MEDIA_CONTROLLER + help + This driver supports the Maxim MAX96712 Quad GMSL2 Deserializer. + + To compile this driver as a module, choose M here: the + module will be called max96712. diff --git a/drivers/staging/media/max96712/Makefile b/drivers/staging/media/max96712/Makefile new file mode 100644 index 000000000..70c1974ce --- /dev/null +++ b/drivers/staging/media/max96712/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_VIDEO_MAX96712) += max96712.o diff --git a/drivers/staging/media/max96712/max96712.c b/drivers/staging/media/max96712/max96712.c new file mode 100644 index 000000000..99b333b68 --- /dev/null +++ b/drivers/staging/media/max96712/max96712.c @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Maxim MAX9286 Quad GMSL2 Deserializer Driver + * + * Copyright (C) 2021 Renesas Electronics Corporation + * Copyright (C) 2021 Niklas Söderlund + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#define MAX96712_ID 0x20 + +#define MAX96712_DPLL_FREQ 1000 + +enum max96712_pattern { + MAX96712_PATTERN_CHECKERBOARD = 0, + MAX96712_PATTERN_GRADIENT, +}; + +struct max96712_priv { + struct i2c_client *client; + struct regmap *regmap; + struct gpio_desc *gpiod_pwdn; + + struct v4l2_mbus_config_mipi_csi2 mipi; + + struct v4l2_subdev sd; + struct v4l2_ctrl_handler ctrl_handler; + struct media_pad pads[1]; + + enum max96712_pattern pattern; +}; + +static int max96712_read(struct max96712_priv *priv, int reg) +{ + int ret, val; + + ret = regmap_read(priv->regmap, reg, &val); + if (ret) { + dev_err(&priv->client->dev, "read 0x%04x failed\n", reg); + return ret; + } + + return val; +} + +static int max96712_write(struct max96712_priv *priv, unsigned int reg, u8 val) +{ + int ret; + + ret = regmap_write(priv->regmap, reg, val); + if (ret) + dev_err(&priv->client->dev, "write 0x%04x failed\n", reg); + + return ret; +} + +static int max96712_update_bits(struct max96712_priv *priv, unsigned int reg, + u8 mask, u8 val) +{ + int ret; + + ret = regmap_update_bits(priv->regmap, reg, mask, val); + if (ret) + dev_err(&priv->client->dev, "update 0x%04x failed\n", reg); + + return ret; +} + +static int max96712_write_bulk(struct max96712_priv *priv, unsigned int reg, + const void *val, size_t val_count) +{ + int ret; + + ret = regmap_bulk_write(priv->regmap, reg, val, val_count); + if (ret) + dev_err(&priv->client->dev, "bulk write 0x%04x failed\n", reg); + + return ret; +} + +static int max96712_write_bulk_value(struct max96712_priv *priv, + unsigned int reg, unsigned int val, + size_t val_count) +{ + unsigned int i; + u8 values[4]; + + for (i = 1; i <= val_count; i++) + values[i - 1] = (val >> ((val_count - i) * 8)) & 0xff; + + return max96712_write_bulk(priv, reg, &values, val_count); +} + +static void max96712_reset(struct max96712_priv *priv) +{ + max96712_update_bits(priv, 0x13, 0x40, 0x40); + msleep(20); +} + +static void max96712_mipi_enable(struct max96712_priv *priv, bool enable) +{ + if (enable) { + max96712_update_bits(priv, 0x40b, 0x02, 0x02); + max96712_update_bits(priv, 0x8a0, 0x80, 0x80); + } else { + max96712_update_bits(priv, 0x8a0, 0x80, 0x00); + max96712_update_bits(priv, 0x40b, 0x02, 0x00); + } +} + +static void max96712_mipi_configure(struct max96712_priv *priv) +{ + unsigned int i; + u8 phy5 = 0; + + max96712_mipi_enable(priv, false); + + /* Select 2x4 mode. */ + max96712_write(priv, 0x8a0, 0x04); + + /* Configure a 4-lane DPHY using PHY0 and PHY1. */ + /* TODO: Add support for 2-lane and 1-lane configurations. */ + /* TODO: Add support CPHY mode. */ + max96712_write(priv, 0x94a, 0xc0); + + /* Configure lane mapping for PHY0 and PHY1. */ + /* TODO: Add support for lane swapping. */ + max96712_write(priv, 0x8a3, 0xe4); + + /* Configure lane polarity for PHY0 and PHY1. */ + for (i = 0; i < priv->mipi.num_data_lanes + 1; i++) + if (priv->mipi.lane_polarities[i]) + phy5 |= BIT(i == 0 ? 5 : i < 3 ? i - 1 : i); + max96712_write(priv, 0x8a5, phy5); + + /* Set link frequency for PHY0 and PHY1. */ + max96712_update_bits(priv, 0x415, 0x3f, + ((MAX96712_DPLL_FREQ / 100) & 0x1f) | BIT(5)); + max96712_update_bits(priv, 0x418, 0x3f, + ((MAX96712_DPLL_FREQ / 100) & 0x1f) | BIT(5)); + + /* Enable PHY0 and PHY1 */ + max96712_update_bits(priv, 0x8a2, 0xf0, 0x30); +} + +static void max96712_pattern_enable(struct max96712_priv *priv, bool enable) +{ + const u32 h_active = 1920; + const u32 h_fp = 88; + const u32 h_sw = 44; + const u32 h_bp = 148; + const u32 h_tot = h_active + h_fp + h_sw + h_bp; + + const u32 v_active = 1080; + const u32 v_fp = 4; + const u32 v_sw = 5; + const u32 v_bp = 36; + const u32 v_tot = v_active + v_fp + v_sw + v_bp; + + if (!enable) { + max96712_write(priv, 0x1051, 0x00); + return; + } + + /* PCLK 75MHz. */ + max96712_write(priv, 0x0009, 0x01); + + /* Configure Video Timing Generator for 1920x1080 @ 30 fps. */ + max96712_write_bulk_value(priv, 0x1052, 0, 3); + max96712_write_bulk_value(priv, 0x1055, v_sw * h_tot, 3); + max96712_write_bulk_value(priv, 0x1058, + (v_active + v_fp + + v_bp) * h_tot, 3); + max96712_write_bulk_value(priv, 0x105b, 0, 3); + max96712_write_bulk_value(priv, 0x105e, h_sw, 2); + max96712_write_bulk_value(priv, 0x1060, h_active + h_fp + h_bp, 2); + max96712_write_bulk_value(priv, 0x1062, v_tot, 2); + max96712_write_bulk_value(priv, 0x1064, + h_tot * (v_sw + v_bp) + (h_sw + h_bp), 3); + max96712_write_bulk_value(priv, 0x1067, h_active, 2); + max96712_write_bulk_value(priv, 0x1069, h_fp + h_sw + h_bp, 2); + max96712_write_bulk_value(priv, 0x106b, v_active, 2); + + /* Generate VS, HS and DE in free-running mode. */ + max96712_write(priv, 0x1050, 0xfb); + + /* Configure Video Pattern Generator. */ + if (priv->pattern == MAX96712_PATTERN_CHECKERBOARD) { + /* Set checkerboard pattern size. */ + max96712_write(priv, 0x1074, 0x3c); + max96712_write(priv, 0x1075, 0x3c); + max96712_write(priv, 0x1076, 0x3c); + + /* Set checkerboard pattern colors. */ + max96712_write_bulk_value(priv, 0x106e, 0xfecc00, 3); + max96712_write_bulk_value(priv, 0x1071, 0x006aa7, 3); + + /* Generate checkerboard pattern. */ + max96712_write(priv, 0x1051, 0x10); + } else { + /* Set gradient increment. */ + max96712_write(priv, 0x106d, 0x10); + + /* Generate gradient pattern. */ + max96712_write(priv, 0x1051, 0x20); + } +} + +static int max96712_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct max96712_priv *priv = v4l2_get_subdevdata(sd); + + if (enable) { + max96712_pattern_enable(priv, true); + max96712_mipi_enable(priv, true); + } else { + max96712_mipi_enable(priv, false); + max96712_pattern_enable(priv, false); + } + + return 0; +} + +static const struct v4l2_subdev_video_ops max96712_video_ops = { + .s_stream = max96712_s_stream, +}; + +static int max96712_get_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + format->format.width = 1920; + format->format.height = 1080; + format->format.code = MEDIA_BUS_FMT_RGB888_1X24; + format->format.field = V4L2_FIELD_NONE; + + return 0; +} + +static const struct v4l2_subdev_pad_ops max96712_pad_ops = { + .get_fmt = max96712_get_pad_format, + .set_fmt = max96712_get_pad_format, +}; + +static const struct v4l2_subdev_ops max96712_subdev_ops = { + .video = &max96712_video_ops, + .pad = &max96712_pad_ops, +}; + +static const char * const max96712_test_pattern[] = { + "Checkerboard", + "Gradient", +}; + +static int max96712_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct max96712_priv *priv = + container_of(ctrl->handler, struct max96712_priv, ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + priv->pattern = ctrl->val ? + MAX96712_PATTERN_GRADIENT : + MAX96712_PATTERN_CHECKERBOARD; + break; + } + return 0; +} + +static const struct v4l2_ctrl_ops max96712_ctrl_ops = { + .s_ctrl = max96712_s_ctrl, +}; + +static int max96712_v4l2_register(struct max96712_priv *priv) +{ + long pixel_rate; + int ret; + + v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96712_subdev_ops); + priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; + + v4l2_ctrl_handler_init(&priv->ctrl_handler, 2); + + /* + * TODO: Once V4L2_CID_LINK_FREQ is changed from a menu control to an + * INT64 control it should be used here instead of V4L2_CID_PIXEL_RATE. + */ + pixel_rate = MAX96712_DPLL_FREQ / priv->mipi.num_data_lanes * 1000000; + v4l2_ctrl_new_std(&priv->ctrl_handler, NULL, V4L2_CID_PIXEL_RATE, + pixel_rate, pixel_rate, 1, pixel_rate); + + v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler, &max96712_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(max96712_test_pattern) - 1, + 0, 0, max96712_test_pattern); + + priv->sd.ctrl_handler = &priv->ctrl_handler; + ret = priv->ctrl_handler.error; + if (ret) + goto error; + + priv->pads[0].flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&priv->sd.entity, 1, priv->pads); + if (ret) + goto error; + + v4l2_set_subdevdata(&priv->sd, priv); + + ret = v4l2_async_register_subdev(&priv->sd); + if (ret < 0) { + dev_err(&priv->client->dev, "Unable to register subdevice\n"); + goto error; + } + + return 0; +error: + v4l2_ctrl_handler_free(&priv->ctrl_handler); + + return ret; +} + +static int max96712_parse_dt(struct max96712_priv *priv) +{ + struct fwnode_handle *ep; + struct v4l2_fwnode_endpoint v4l2_ep = { + .bus_type = V4L2_MBUS_CSI2_DPHY + }; + int ret; + + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(&priv->client->dev), 4, + 0, 0); + if (!ep) { + dev_err(&priv->client->dev, "Not connected to subdevice\n"); + return -EINVAL; + } + + ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); + fwnode_handle_put(ep); + if (ret) { + dev_err(&priv->client->dev, "Could not parse v4l2 endpoint\n"); + return -EINVAL; + } + + if (v4l2_ep.bus.mipi_csi2.num_data_lanes != 4) { + dev_err(&priv->client->dev, "Only 4 data lanes supported\n"); + return -EINVAL; + } + + priv->mipi = v4l2_ep.bus.mipi_csi2; + + return 0; +} + +static const struct regmap_config max96712_i2c_regmap = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0x1f00, +}; + +static int max96712_probe(struct i2c_client *client) +{ + struct max96712_priv *priv; + int ret; + + priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->client = client; + i2c_set_clientdata(client, priv); + + priv->regmap = devm_regmap_init_i2c(client, &max96712_i2c_regmap); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable", + GPIOD_OUT_HIGH); + if (IS_ERR(priv->gpiod_pwdn)) + return PTR_ERR(priv->gpiod_pwdn); + + gpiod_set_consumer_name(priv->gpiod_pwdn, "max96712-pwdn"); + gpiod_set_value_cansleep(priv->gpiod_pwdn, 1); + + if (priv->gpiod_pwdn) + usleep_range(4000, 5000); + + if (max96712_read(priv, 0x4a) != MAX96712_ID) + return -ENODEV; + + max96712_reset(priv); + + ret = max96712_parse_dt(priv); + if (ret) + return ret; + + max96712_mipi_configure(priv); + + return max96712_v4l2_register(priv); +} + +static void max96712_remove(struct i2c_client *client) +{ + struct max96712_priv *priv = i2c_get_clientdata(client); + + v4l2_async_unregister_subdev(&priv->sd); + + gpiod_set_value_cansleep(priv->gpiod_pwdn, 0); +} + +static const struct of_device_id max96712_of_table[] = { + { .compatible = "maxim,max96712" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, max96712_of_table); + +static struct i2c_driver max96712_i2c_driver = { + .driver = { + .name = "max96712", + .of_match_table = of_match_ptr(max96712_of_table), + }, + .probe_new = max96712_probe, + .remove = max96712_remove, +}; + +module_i2c_driver(max96712_i2c_driver); + +MODULE_DESCRIPTION("Maxim MAX96712 Quad GMSL2 Deserializer Driver"); +MODULE_AUTHOR("Niklas Söderlund "); +MODULE_LICENSE("GPL"); -- cgit v1.2.3