From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- drivers/staging/media/Kconfig | 64 + drivers/staging/media/Makefile | 18 + drivers/staging/media/atomisp/Kconfig | 39 + drivers/staging/media/atomisp/Makefile | 315 + drivers/staging/media/atomisp/TODO | 213 + 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drivers/staging/media/omap4iss/iss_ipipe.c create mode 100644 drivers/staging/media/omap4iss/iss_ipipe.h create mode 100644 drivers/staging/media/omap4iss/iss_ipipeif.c create mode 100644 drivers/staging/media/omap4iss/iss_ipipeif.h create mode 100644 drivers/staging/media/omap4iss/iss_regs.h create mode 100644 drivers/staging/media/omap4iss/iss_resizer.c create mode 100644 drivers/staging/media/omap4iss/iss_resizer.h create mode 100644 drivers/staging/media/omap4iss/iss_video.c create mode 100644 drivers/staging/media/omap4iss/iss_video.h create mode 100644 drivers/staging/media/rkvdec/Kconfig create mode 100644 drivers/staging/media/rkvdec/Makefile create mode 100644 drivers/staging/media/rkvdec/TODO create mode 100644 drivers/staging/media/rkvdec/rkvdec-h264.c create mode 100644 drivers/staging/media/rkvdec/rkvdec-regs.h create mode 100644 drivers/staging/media/rkvdec/rkvdec-vp9.c create mode 100644 drivers/staging/media/rkvdec/rkvdec.c create mode 100644 drivers/staging/media/rkvdec/rkvdec.h create mode 100644 drivers/staging/media/sunxi/Kconfig create mode 100644 drivers/staging/media/sunxi/Makefile create mode 100644 drivers/staging/media/sunxi/cedrus/Kconfig create mode 100644 drivers/staging/media/sunxi/cedrus/Makefile create mode 100644 drivers/staging/media/sunxi/cedrus/TODO create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus.c create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus.h create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_dec.c create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_dec.h create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h264.c create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h265.c create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_hw.c create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_hw.h create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_regs.h create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_video.c create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_video.h create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_vp8.c create mode 100644 drivers/staging/media/sunxi/sun6i-isp/Kconfig create mode 100644 drivers/staging/media/sunxi/sun6i-isp/Makefile create mode 100644 drivers/staging/media/sunxi/sun6i-isp/TODO.txt create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp.c create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp.h create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.c create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.h create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.h create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.h create mode 100644 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h create mode 100644 drivers/staging/media/sunxi/sun6i-isp/uapi/sun6i-isp-config.h create mode 100644 drivers/staging/media/tegra-video/Kconfig create mode 100644 drivers/staging/media/tegra-video/Makefile create mode 100644 drivers/staging/media/tegra-video/TODO create mode 100644 drivers/staging/media/tegra-video/csi.c create mode 100644 drivers/staging/media/tegra-video/csi.h create mode 100644 drivers/staging/media/tegra-video/tegra210.c create mode 100644 drivers/staging/media/tegra-video/vi.c create mode 100644 drivers/staging/media/tegra-video/vi.h create mode 100644 drivers/staging/media/tegra-video/video.c create mode 100644 drivers/staging/media/tegra-video/video.h (limited to 'drivers/staging/media') diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig new file mode 100644 index 000000000..617012e09 --- /dev/null +++ b/drivers/staging/media/Kconfig @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +menuconfig STAGING_MEDIA + bool "Media staging drivers" + default n + help + This option allows you to select a number of media drivers that + don't have the "normal" Linux kernel quality level. + Most of them don't follow properly the V4L, DVB and/or RC API's, + so, they won't likely work fine with the existing applications. + That also means that, once fixed, their API's will change to match + the existing ones. + + If you wish to work on these drivers, to help improve them, or + to report problems you have with them, please use the + linux-media@vger.kernel.org mailing list. + + If in doubt, say N here. + + +if STAGING_MEDIA && MEDIA_SUPPORT + +# Please keep them in alphabetic order +source "drivers/staging/media/atomisp/Kconfig" + +source "drivers/staging/media/imx/Kconfig" + +source "drivers/staging/media/ipu3/Kconfig" + +source "drivers/staging/media/max96712/Kconfig" + +source "drivers/staging/media/meson/vdec/Kconfig" + +source "drivers/staging/media/omap4iss/Kconfig" + +source "drivers/staging/media/rkvdec/Kconfig" + +source "drivers/staging/media/sunxi/Kconfig" + +source "drivers/staging/media/tegra-video/Kconfig" + +menuconfig STAGING_MEDIA_DEPRECATED + bool "Media staging drivers (DEPRECATED)" + default n + help + This option enables deprecated media drivers that are + scheduled for future removal from the kernel. + + If you wish to work on these drivers to prevent their removal, + then contact the linux-media@vger.kernel.org mailing list. + + If in doubt, say N here. + +if STAGING_MEDIA_DEPRECATED +source "drivers/staging/media/deprecated/atmel/Kconfig" +source "drivers/staging/media/deprecated/cpia2/Kconfig" +source "drivers/staging/media/deprecated/fsl-viu/Kconfig" +source "drivers/staging/media/deprecated/meye/Kconfig" +source "drivers/staging/media/deprecated/saa7146/Kconfig" +source "drivers/staging/media/deprecated/stkwebcam/Kconfig" +source "drivers/staging/media/deprecated/tm6000/Kconfig" +source "drivers/staging/media/deprecated/zr364xx/Kconfig" +endif + +endif diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile new file mode 100644 index 000000000..1e14edc2d --- /dev/null +++ b/drivers/staging/media/Makefile @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += deprecated/atmel/ +obj-$(CONFIG_INTEL_ATOMISP) += atomisp/ +obj-$(CONFIG_VIDEO_CPIA2) += deprecated/cpia2/ +obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx/ +obj-$(CONFIG_VIDEO_MAX96712) += max96712/ +obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/ +obj-$(CONFIG_VIDEO_MEYE) += deprecated/meye/ +obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/ +obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rkvdec/ +obj-$(CONFIG_VIDEO_STKWEBCAM) += deprecated/stkwebcam/ +obj-$(CONFIG_VIDEO_SUNXI) += sunxi/ +obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/ +obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/ +obj-$(CONFIG_VIDEO_TM6000) += deprecated/tm6000/ +obj-$(CONFIG_VIDEO_VIU) += deprecated/fsl-viu/ +obj-$(CONFIG_USB_ZR364XX) += deprecated/zr364xx/ +obj-y += deprecated/saa7146/ diff --git a/drivers/staging/media/atomisp/Kconfig b/drivers/staging/media/atomisp/Kconfig new file mode 100644 index 000000000..2c8d7fdcc --- /dev/null +++ b/drivers/staging/media/atomisp/Kconfig @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0 +menuconfig INTEL_ATOMISP + bool "Enable support to Intel Atom ISP camera drivers" + depends on X86 && EFI && PCI && ACPI + depends on COMMON_CLK + select IOSF_MBI + select MEDIA_CONTROLLER + help + Enable support for the Intel ISP2 camera interfaces and MIPI + sensor drivers. + +config VIDEO_ATOMISP + tristate "Intel Atom Image Signal Processor Driver" + depends on VIDEO_DEV && INTEL_ATOMISP + depends on PMIC_OPREGION + select IOSF_MBI + select VIDEOBUF_VMALLOC + select VIDEO_V4L2_SUBDEV_API + help + Say Y here if your platform supports Intel Atom SoC + camera imaging subsystem. + To compile this driver as a module, choose M here: the + module will be called atomisp + +config VIDEO_ATOMISP_ISP2401 + bool "Use Intel Atom ISP on Cherrytail/Anniedale (ISP2401)" + depends on VIDEO_ATOMISP + help + Enable support for Atom ISP2401-based boards. + + Select this option for Anniedale (Merrifield+ / Moorefield) + and Cherrytrail SoCs. + + Disabling it enables support for Atom ISP2400-based boards + (Merrifield and Baytrail SoCs). + +if VIDEO_ATOMISP +source "drivers/staging/media/atomisp/i2c/Kconfig" +endif diff --git a/drivers/staging/media/atomisp/Makefile b/drivers/staging/media/atomisp/Makefile new file mode 100644 index 000000000..532e12ed7 --- /dev/null +++ b/drivers/staging/media/atomisp/Makefile @@ -0,0 +1,315 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for camera drivers. +# +obj-$(CONFIG_INTEL_ATOMISP) += i2c/ +obj-$(CONFIG_VIDEO_ATOMISP) += atomisp.o +obj-$(CONFIG_VIDEO_ATOMISP) += pci/atomisp_gmin_platform.o + +# While on staging, keep debug enabled +DEFINES += -DDEBUG + +atomisp = $(srctree)/drivers/staging/media/atomisp/ + +# SPDX-License-Identifier: GPL-2.0 +atomisp-objs += \ + pci/atomisp_cmd.o \ + pci/atomisp_compat_css20.o \ + pci/atomisp_csi2.o \ + pci/atomisp_drvfs.o \ + pci/atomisp_fops.o \ + pci/atomisp_ioctl.o \ + pci/atomisp_subdev.o \ + pci/atomisp_tpg.o \ + pci/atomisp_v4l2.o \ + pci/sh_css_firmware.o \ + pci/sh_css_host_data.o \ + pci/sh_css_hrt.o \ + pci/sh_css_metrics.o \ + pci/sh_css_mipi.o \ + pci/sh_css_mmu.o \ + pci/sh_css.o \ + pci/sh_css_param_dvs.o \ + pci/sh_css_param_shading.o \ + pci/sh_css_params.o \ + pci/sh_css_properties.o \ + pci/sh_css_sp.o \ + pci/sh_css_stream_format.o \ + pci/sh_css_version.o \ + pci/base/circbuf/src/circbuf.o \ + pci/base/refcount/src/refcount.o \ + pci/camera/pipe/src/pipe_binarydesc.o \ + pci/camera/pipe/src/pipe_stagedesc.o \ + pci/camera/pipe/src/pipe_util.o \ + pci/camera/util/src/util.o \ + pci/hmm/hmm_bo.o \ + pci/hmm/hmm.o \ + pci/ia_css_device_access.o \ + pci/ia_css_isp_configs.o \ + pci/ia_css_isp_states.o \ + pci/ia_css_isp_params.o \ + pci/isp/kernels/aa/aa_2/ia_css_aa2.host.o \ + pci/isp/kernels/anr/anr_1.0/ia_css_anr.host.o \ + pci/isp/kernels/anr/anr_2/ia_css_anr2.host.o \ + pci/isp/kernels/anr/anr_2/ia_css_anr2_table.host.o \ + pci/isp/kernels/bh/bh_2/ia_css_bh.host.o \ + pci/isp/kernels/bnlm/ia_css_bnlm.host.o \ + pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.o \ + pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.o \ + pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.o \ + pci/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.o \ + pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.o \ + pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.o \ + pci/isp/kernels/crop/crop_1.0/ia_css_crop.host.o \ + pci/isp/kernels/csc/csc_1.0/ia_css_csc.host.o \ + pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.o \ + pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.o \ + pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.o \ + pci/isp/kernels/ctc/ctc2/ia_css_ctc2.host.o \ + pci/isp/kernels/de/de_1.0/ia_css_de.host.o \ + pci/isp/kernels/de/de_2/ia_css_de2.host.o \ + pci/isp/kernels/dpc2/ia_css_dpc2.host.o \ + pci/isp/kernels/dp/dp_1.0/ia_css_dp.host.o \ + pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.o \ + pci/isp/kernels/eed1_8/ia_css_eed1_8.host.o \ + pci/isp/kernels/fc/fc_1.0/ia_css_formats.host.o \ + pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.o \ + pci/isp/kernels/gc/gc_1.0/ia_css_gc.host.o \ + pci/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.o \ + pci/isp/kernels/gc/gc_2/ia_css_gc2.host.o \ + pci/isp/kernels/gc/gc_2/ia_css_gc2_table.host.o \ + pci/isp/kernels/hdr/ia_css_hdr.host.o \ + pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.o \ + pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.o \ + pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.o \ + pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.o \ + pci/isp/kernels/macc/macc_1.0/ia_css_macc.host.o \ + pci/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.o \ + pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.o \ + pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.o \ + pci/isp/kernels/norm/norm_1.0/ia_css_norm.host.o \ + pci/isp/kernels/ob/ob_1.0/ia_css_ob.host.o \ + pci/isp/kernels/ob/ob2/ia_css_ob2.host.o \ + pci/isp/kernels/output/output_1.0/ia_css_output.host.o \ + pci/isp/kernels/qplane/qplane_2/ia_css_qplane.host.o \ + pci/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.o \ + pci/isp/kernels/raw/raw_1.0/ia_css_raw.host.o \ + pci/isp/kernels/ref/ref_1.0/ia_css_ref.host.o \ + pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.o \ + pci/isp/kernels/sc/sc_1.0/ia_css_sc.host.o \ + pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.o \ + pci/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.o \ + pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.o \ + pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.o \ + pci/isp/kernels/vf/vf_1.0/ia_css_vf.host.o \ + pci/isp/kernels/wb/wb_1.0/ia_css_wb.host.o \ + pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.o \ + pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.o \ + pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.o \ + pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.o \ + pci/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.o \ + pci/mmu/isp_mmu.o \ + pci/mmu/sh_mmu_mrfld.o \ + pci/runtime/binary/src/binary.o \ + pci/runtime/bufq/src/bufq.o \ + pci/runtime/debug/src/ia_css_debug.o \ + pci/runtime/eventq/src/eventq.o \ + pci/runtime/event/src/event.o \ + pci/runtime/frame/src/frame.o \ + pci/runtime/ifmtr/src/ifmtr.o \ + pci/runtime/inputfifo/src/inputfifo.o \ + pci/runtime/isp_param/src/isp_param.o \ + pci/runtime/isys/src/csi_rx_rmgr.o \ + pci/runtime/isys/src/isys_dma_rmgr.o \ + pci/runtime/isys/src/isys_init.o \ + pci/runtime/isys/src/isys_stream2mmio_rmgr.o \ + pci/runtime/isys/src/rx.o \ + pci/runtime/isys/src/virtual_isys.o \ + pci/runtime/pipeline/src/pipeline.o \ + pci/runtime/queue/src/queue_access.o \ + pci/runtime/queue/src/queue.o \ + pci/runtime/rmgr/src/rmgr.o \ + pci/runtime/rmgr/src/rmgr_vbuf.o \ + pci/runtime/spctrl/src/spctrl.o \ + pci/runtime/timer/src/timer.o \ + pci/hive_isp_css_common/host/debug.o \ + pci/hive_isp_css_common/host/dma.o \ + pci/hive_isp_css_common/host/event_fifo.o \ + pci/hive_isp_css_common/host/fifo_monitor.o \ + pci/hive_isp_css_common/host/gdc.o \ + pci/hive_isp_css_common/host/gp_device.o \ + pci/hive_isp_css_common/host/gp_timer.o \ + pci/hive_isp_css_common/host/hmem.o \ + pci/hive_isp_css_common/host/input_formatter.o \ + pci/hive_isp_css_common/host/input_system.o \ + pci/hive_isp_css_common/host/irq.o \ + pci/hive_isp_css_common/host/isp.o \ + pci/hive_isp_css_common/host/mmu.o \ + pci/hive_isp_css_common/host/sp.o \ + pci/hive_isp_css_common/host/timed_ctrl.o \ + pci/hive_isp_css_common/host/vmem.o \ + pci/hive_isp_css_shared/host/tag.o \ + pci/system_local.o + +# These will be needed when clean merge CHT support nicely into the driver +# Keep them here handy for when we get to that point +# + +obj-cht = \ + pci/css_2401_system/host/csi_rx.o \ + pci/css_2401_system/host/ibuf_ctrl.o \ + pci/css_2401_system/host/isys_dma.o \ + pci/css_2401_system/host/isys_irq.o \ + pci/css_2401_system/host/isys_stream2mmio.o + +INCLUDES += \ + -I$(atomisp)/ \ + -I$(atomisp)/include/ \ + -I$(atomisp)/include/hmm/ \ + -I$(atomisp)/include/mmu/ \ + -I$(atomisp)/pci/ \ + -I$(atomisp)/pci/base/circbuf/interface/ \ + -I$(atomisp)/pci/base/refcount/interface/ \ + -I$(atomisp)/pci/camera/pipe/interface/ \ + -I$(atomisp)/pci/camera/util/interface/ \ + -I$(atomisp)/pci/hive_isp_css_common/ \ + -I$(atomisp)/pci/hive_isp_css_common/host/ \ + -I$(atomisp)/pci/hive_isp_css_include/ \ + -I$(atomisp)/pci/hive_isp_css_include/device_access/ \ + -I$(atomisp)/pci/hive_isp_css_include/host/ \ + -I$(atomisp)/pci/hive_isp_css_shared/ \ + -I$(atomisp)/pci/hive_isp_css_shared/host/ \ + -I$(atomisp)/pci/isp/kernels/ \ + -I$(atomisp)/pci/isp/kernels/aa/aa_2/ \ + -I$(atomisp)/pci/isp/kernels/anr/anr_1.0/ \ + -I$(atomisp)/pci/isp/kernels/anr/anr_2/ \ + -I$(atomisp)/pci/isp/kernels/bh/bh_2/ \ + -I$(atomisp)/pci/isp/kernels/bnlm/ \ + -I$(atomisp)/pci/isp/kernels/bnr/ \ + -I$(atomisp)/pci/isp/kernels/bnr/bnr_1.0/ \ + -I$(atomisp)/pci/isp/kernels/bnr/bnr2_2/ \ + -I$(atomisp)/pci/isp/kernels/cnr/ \ + -I$(atomisp)/pci/isp/kernels/cnr/cnr_1.0/ \ + -I$(atomisp)/pci/isp/kernels/cnr/cnr_2/ \ + -I$(atomisp)/pci/isp/kernels/conversion/ \ + -I$(atomisp)/pci/isp/kernels/conversion/conversion_1.0/ \ + -I$(atomisp)/pci/isp/kernels/copy_output/ \ + -I$(atomisp)/pci/isp/kernels/copy_output/copy_output_1.0/ \ + -I$(atomisp)/pci/isp/kernels/crop/ \ + -I$(atomisp)/pci/isp/kernels/crop/crop_1.0/ \ + -I$(atomisp)/pci/isp/kernels/csc/ \ + -I$(atomisp)/pci/isp/kernels/csc/csc_1.0/ \ + -I$(atomisp)/pci/isp/kernels/ctc/ \ + -I$(atomisp)/pci/isp/kernels/ctc/ctc_1.0/ \ + -I$(atomisp)/pci/isp/kernels/ctc/ctc1_5/ \ + -I$(atomisp)/pci/isp/kernels/ctc/ctc2/ \ + -I$(atomisp)/pci/isp/kernels/de/ \ + -I$(atomisp)/pci/isp/kernels/de/de_1.0/ \ + -I$(atomisp)/pci/isp/kernels/de/de_2/ \ + -I$(atomisp)/pci/isp/kernels/dp/ \ + -I$(atomisp)/pci/isp/kernels/dpc2/ \ + -I$(atomisp)/pci/isp/kernels/dp/dp_1.0/ \ + -I$(atomisp)/pci/isp/kernels/dvs/ \ + -I$(atomisp)/pci/isp/kernels/dvs/dvs_1.0/ \ + -I$(atomisp)/pci/isp/kernels/eed1_8/ \ + -I$(atomisp)/pci/isp/kernels/fc/ \ + -I$(atomisp)/pci/isp/kernels/fc/fc_1.0/ \ + -I$(atomisp)/pci/isp/kernels/fixedbds/ \ + -I$(atomisp)/pci/isp/kernels/fixedbds/fixedbds_1.0/ \ + -I$(atomisp)/pci/isp/kernels/fpn/ \ + -I$(atomisp)/pci/isp/kernels/fpn/fpn_1.0/ \ + -I$(atomisp)/pci/isp/kernels/gc/ \ + -I$(atomisp)/pci/isp/kernels/gc/gc_1.0/ \ + -I$(atomisp)/pci/isp/kernels/gc/gc_2/ \ + -I$(atomisp)/pci/isp/kernels/hdr/ \ + -I$(atomisp)/pci/isp/kernels/ipu2_io_ls/ \ + -I$(atomisp)/pci/isp/kernels/ipu2_io_ls/ \ + -I$(atomisp)/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ \ + -I$(atomisp)/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ \ + -I$(atomisp)/pci/isp/kernels/ipu2_io_ls/common/ \ + -I$(atomisp)/pci/isp/kernels/ipu2_io_ls/common/ \ + -I$(atomisp)/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ \ + -I$(atomisp)/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ \ + -I$(atomisp)/pci/isp/kernels/iterator/ \ + -I$(atomisp)/pci/isp/kernels/iterator/iterator_1.0/ \ + -I$(atomisp)/pci/isp/kernels/macc/ \ + -I$(atomisp)/pci/isp/kernels/macc/macc_1.0/ \ + -I$(atomisp)/pci/isp/kernels/macc/macc1_5/ \ + -I$(atomisp)/pci/isp/kernels/norm/ \ + -I$(atomisp)/pci/isp/kernels/norm/norm_1.0/ \ + -I$(atomisp)/pci/isp/kernels/ob/ \ + -I$(atomisp)/pci/isp/kernels/ob/ob_1.0/ \ + -I$(atomisp)/pci/isp/kernels/ob/ob2/ \ + -I$(atomisp)/pci/isp/kernels/output/ \ + -I$(atomisp)/pci/isp/kernels/output/output_1.0/ \ + -I$(atomisp)/pci/isp/kernels/qplane/ \ + -I$(atomisp)/pci/isp/kernels/qplane/qplane_2/ \ + -I$(atomisp)/pci/isp/kernels/raw/ \ + -I$(atomisp)/pci/isp/kernels/raw_aa_binning/ \ + -I$(atomisp)/pci/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ \ + -I$(atomisp)/pci/isp/kernels/raw/raw_1.0/ \ + -I$(atomisp)/pci/isp/kernels/ref/ \ + -I$(atomisp)/pci/isp/kernels/ref/ref_1.0/ \ + -I$(atomisp)/pci/isp/kernels/s3a/ \ + -I$(atomisp)/pci/isp/kernels/s3a/s3a_1.0/ \ + -I$(atomisp)/pci/isp/kernels/sc/ \ + -I$(atomisp)/pci/isp/kernels/sc/sc_1.0/ \ + -I$(atomisp)/pci/isp/kernels/sdis/ \ + -I$(atomisp)/pci/isp/kernels/sdis/common/ \ + -I$(atomisp)/pci/isp/kernels/sdis/sdis_1.0/ \ + -I$(atomisp)/pci/isp/kernels/sdis/sdis_2/ \ + -I$(atomisp)/pci/isp/kernels/tdf/ \ + -I$(atomisp)/pci/isp/kernels/tdf/tdf_1.0/ \ + -I$(atomisp)/pci/isp/kernels/tnr/ \ + -I$(atomisp)/pci/isp/kernels/tnr/tnr_1.0/ \ + -I$(atomisp)/pci/isp/kernels/tnr/tnr3/ \ + -I$(atomisp)/pci/isp/kernels/uds/ \ + -I$(atomisp)/pci/isp/kernels/uds/uds_1.0/ \ + -I$(atomisp)/pci/isp/kernels/vf/ \ + -I$(atomisp)/pci/isp/kernels/vf/vf_1.0/ \ + -I$(atomisp)/pci/isp/kernels/wb/ \ + -I$(atomisp)/pci/isp/kernels/wb/wb_1.0/ \ + -I$(atomisp)/pci/isp/kernels/xnr/ \ + -I$(atomisp)/pci/isp/kernels/xnr/xnr_1.0/ \ + -I$(atomisp)/pci/isp/kernels/xnr/xnr_3.0/ \ + -I$(atomisp)/pci/isp/kernels/ynr/ \ + -I$(atomisp)/pci/isp/kernels/ynr/ynr_1.0/ \ + -I$(atomisp)/pci/isp/kernels/ynr/ynr_2/ \ + -I$(atomisp)/pci/isp/modes/interface/ \ + -I$(atomisp)/pci/runtime/binary/interface/ \ + -I$(atomisp)/pci/runtime/bufq/interface/ \ + -I$(atomisp)/pci/runtime/debug/interface/ \ + -I$(atomisp)/pci/runtime/event/interface/ \ + -I$(atomisp)/pci/runtime/eventq/interface/ \ + -I$(atomisp)/pci/runtime/frame/interface/ \ + -I$(atomisp)/pci/runtime/ifmtr/interface/ \ + -I$(atomisp)/pci/runtime/inputfifo/interface/ \ + -I$(atomisp)/pci/runtime/isp_param/interface/ \ + -I$(atomisp)/pci/runtime/isys/interface/ \ + -I$(atomisp)/pci/runtime/isys/src/ \ + -I$(atomisp)/pci/runtime/pipeline/interface/ \ + -I$(atomisp)/pci/runtime/queue/interface/ \ + -I$(atomisp)/pci/runtime/queue/src/ \ + -I$(atomisp)/pci/runtime/rmgr/interface/ \ + -I$(atomisp)/pci/runtime/spctrl/interface/ \ + -I$(atomisp)/pci/runtime/tagger/interface/ \ + -I$(atomisp)/pci/css_2401_system/ \ + -I$(atomisp)/pci/css_2401_system/host/ \ + -I$(atomisp)/pci/css_2401_system/hrt/ + +DEFINES := -DHRT_HW -DHRT_ISP_CSS_CUSTOM_HOST -DHRT_USE_VIR_ADDRS -D__HOST__ +#DEFINES += -DUSE_DYNAMIC_BIN +#DEFINES += -DISP_POWER_GATING +#DEFINES += -DUSE_INTERRUPTS +#DEFINES += -DUSE_SSSE3 +#DEFINES += -DPUNIT_CAMERA_BUSY +#DEFINES += -DUSE_KMEM_CACHE + +ifeq ($(CONFIG_VIDEO_ATOMISP_ISP2401),y) +atomisp-objs += \ + $(obj-cht) \ + pci/runtime/isys/src/ibuf_ctrl_rmgr.o +DEFINES += -DISP2401 +endif + +ccflags-y += $(INCLUDES) $(DEFINES) -fno-common diff --git a/drivers/staging/media/atomisp/TODO b/drivers/staging/media/atomisp/TODO new file mode 100644 index 000000000..43b842043 --- /dev/null +++ b/drivers/staging/media/atomisp/TODO @@ -0,0 +1,213 @@ +For both Cherrytrail (CHT) and Baytrail (BHT) the driver +requires the "candrpv_0415_20150521_0458" firmware version. +It should be noticed that the firmware file is different, +depending on the ISP model, so they're stored with different +names: + +- for BHT: /lib/firmware/shisp_2400b0_v21.bin + + Warning: The driver was not tested yet for BHT. + +- for CHT: /lib/firmware/shisp_2401a0_v21.bin + + https://github.com/intel-aero/meta-intel-aero-base/blob/master/recipes-kernel/linux/linux-yocto/shisp_2401a0_v21.bin + +NOTE: +===== + +This driver currently doesn't work with most V4L2 applications, +as there are still some issues with regards to implementing +certain APIs at the standard way. + +Also, currently only USERPTR streaming mode is working. + +In order to test, it is needed to know what's the sensor's +resolution. This can be checked with: + +$ v4l2-ctl --get-fmt-video + Format Video Capture: + Width/Height : 1600/1200 + ... + +It is known to work with: + +- v4l2grab at contrib/test directory at https://git.linuxtv.org/v4l-utils.git/ + + The resolution should not be bigger than the max resolution + supported by the sensor, or it will fail. So, if the sensor + reports: + + The driver can be tested with: + + v4l2grab -f YUYV -x 1600 -y 1200 -d /dev/video2 -u + +- NVT at https://github.com/intel/nvt + + $ ./v4l2n -o testimage_@.raw \ + --device /dev/video2 \ + --input 0 \ + --exposure=30000,30000,30000,30000 \ + --parm type=1,capturemode=CI_MODE_PREVIEW \ + --fmt type=1,width=1600,height=1200,pixelformat=YUYV \ + --reqbufs count=2,memory=USERPTR \ + --parameters=wb_config.r=32768,wb_config.gr=21043,wb_config.gb=21043,wb_config.b=30863 \ + --capture=20 + + As the output is in raw format, images need to be converted with: + + $ for i in $(seq 0 19); do + name="testimage_$(printf "%03i" $i)" + ./raw2pnm -x$WIDTH -y$HEIGHT -f$FORMAT $name.raw $name.pnm + rm $name.raw + done + +TODO +==== + +1. Fix support for MMAP streaming mode. This is required for most + V4L2 applications; + +2. Implement and/or fix V4L2 ioctls in order to allow a normal app to + use it; + +3. Ensure that the driver will pass v4l2-compliance tests; + +4. Get manufacturer's authorization to redistribute the binaries for + the firmware files; + +5. remove VIDEO_ATOMISP_ISP2401, making the driver to auto-detect the + register address differences between ISP2400 and ISP2401; + +6. Cleanup the driver code, removing the abstraction layers inside it; + +7. The atomisp doesn't rely at the usual i2c stuff to discover the + sensors. Instead, it calls a function from atomisp_gmin_platform.c. + There are some hacks added there for it to wait for sensors to be + probed (with a timeout of 2 seconds or so). This should be converted + to the usual way, using V4L2 async subdev framework to wait for + cameras to be probed; + +8. Switch to standard V4L2 sub-device API for sensor and lens. In + particular, the user space API needs to support V4L2 controls as + defined in the V4L2 spec and references to atomisp must be removed from + these drivers. + +9. Use LED flash API for flash LED drivers such as LM3554 (which already + has a LED class driver). + +10. Migrate the sensor drivers out of staging or re-using existing + drivers; + +11. Switch the driver to use pm_runtime stuff. Right now, it probes the + existing PMIC code and sensors call it directly. + +12. There's a problem on sensor drivers: when trying to set a video + format, the atomisp main driver calls the sensor drivers with the + sensor turned off. This causes them to fail. + + This was fixed at atomisp-ov2880, which has a hack inside it + to turn it on when VIDIOC_S_FMT is called, but this has to be + cheked on other drivers as well. + + The right fix seems to power on the sensor when a video device is + opened (or at the first VIDIOC_ ioctl - except for VIDIOC_QUERYCAP), + powering it down at close() syscall. + + Such kind of control would need to be done inside the atomisp driver, + not at the sensors code. + +13. There are several issues related to memory management, that can + cause crashes and/or memory leaks. The atomisp splits the memory + management on three separate regions: + + - dynamic pool; + - reserved pool; + - generic pool + + The code implementing it is at: + + drivers/staging/media/atomisp/pci/hmm/ + + It also has a separate code for managing DMA buffers at: + + drivers/staging/media/atomisp/pci/mmu/ + + The code there is really dirty, ugly and probably wrong. I fixed + one bug there already, but the best would be to just trash it and use + something else. Maybe the code from the newer intel driver could + serve as a model: + + drivers/staging/media/ipu3/ipu3-mmu.c + + But converting it to use something like that is painful and may + cause some breakages. + +14. The file structure needs to get tidied up to resemble a normal Linux + driver. + +15. Lots of the midlayer glue. Unused code and abstraction needs removing. + +16. The AtomISP driver includes some special IOCTLS (ATOMISP_IOC_XXXX_XXXX) + and controls that require some cleanup. Some of those code may have + been removed during the cleanups. They could be needed in order to + properly support 3A algorithms. + + Such IOCTL interface needs more documentation. The better would + be to use something close to the interface used by the IPU3 IMGU driver. + +17. The ISP code has some dependencies of the exact FW version. + The version defined in pci/sh_css_firmware.c: + + BYT (isp2400): "irci_stable_candrpv_0415_20150521_0458" + + CHT (isp2401): "irci_ecr - master_20150911_0724" + + Those versions don't seem to be available anymore. On the tests we've + done so far, this version also seems to work for CHT: + + "irci_stable_candrpv_0415_20150521_0458" + + Which can be obtainable from Yocto Atom ISP respository. + + but this was not thoroughly tested. + + At some point we may need to round up a few driver versions and see if + there are any specific things that can be done to fold in support for + multiple firmware versions. + + +18. Switch from videobuf1 to videobuf2. Videobuf1 is being removed! + +19. Correct Coding Style. Please refrain sending coding style patches + for this driver until the other work is done, as there will be a lot + of code churn until this driver becomes functional again. + +20. Remove the logic which sets up pipelines inside it, moving it to + libcamera and implement MC support. + + +Limitations +=========== + +1. To test the patches, you also need the ISP firmware + + for BYT: /lib/firmware/shisp_2400b0_v21.bin + for CHT: /lib/firmware/shisp_2401a0_v21.bin + + The firmware files will usually be found in /etc/firmware on an Android + device but can also be extracted from the upgrade kit if you've managed + to lose them somehow. + +2. Without a 3A library the capture behaviour is not very good. To take a good + picture, you need tune ISP parameters by IOCTL functions or use a 3A library + such as libxcam. + +3. The driver is intended to drive the PCI exposed versions of the device. + It will not detect those devices enumerated via ACPI as a field of the + i915 GPU driver. + + There are some patches adding i915 GPU support floating at the Yocto's + Aero repository (so far, untested upstream). + +4. The driver supports only v2 of the IPU/Camera. It will not work with the + versions of the hardware in other SoCs. diff --git a/drivers/staging/media/atomisp/i2c/Kconfig b/drivers/staging/media/atomisp/i2c/Kconfig new file mode 100644 index 000000000..e726101b2 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/Kconfig @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Kconfig for sensor drivers +# + +config VIDEO_ATOMISP_OV2722 + tristate "OVT ov2722 sensor support" + depends on ACPI + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor-level driver for the OVT + OV2722 raw camera. + + OVT is a 2M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_ATOMISP_GC2235 + tristate "Galaxy gc2235 sensor support" + depends on ACPI + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor-level driver for the OVT + GC2235 raw camera. + + GC2235 is a 2M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_ATOMISP_MSRLIST_HELPER + tristate "Helper library to load, parse and apply large register lists." + depends on I2C + help + This is a helper library to be used from a sensor driver to load, parse + and apply large register lists. + + To compile this driver as a module, choose M here: the + module will be called libmsrlisthelper. + +config VIDEO_ATOMISP_MT9M114 + tristate "Aptina mt9m114 sensor support" + depends on ACPI + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor-level driver for the Micron + mt9m114 1.3 Mpixel camera. + + mt9m114 is video camera sensor. + + It currently only works with the atomisp driver. + +config VIDEO_ATOMISP_GC0310 + tristate "GC0310 sensor support" + depends on ACPI + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor-level driver for the Galaxycore + GC0310 0.3MP sensor. + +config VIDEO_ATOMISP_OV2680 + tristate "Omnivision OV2680 sensor support" + depends on ACPI + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor-level driver for the Omnivision + OV2680 raw camera. + + ov2680 is a 2M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_ATOMISP_OV5693 + tristate "Omnivision ov5693 sensor support" + depends on ACPI + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor-level driver for the Micron + ov5693 5 Mpixel camera. + + ov5693 is video camera sensor. + + It currently only works with the atomisp driver. + +# +# Kconfig for flash drivers +# + +config VIDEO_ATOMISP_LM3554 + tristate "LM3554 flash light driver" + depends on ACPI + depends on VIDEO_DEV && I2C + help + This is a Video4Linux2 sub-dev driver for the LM3554 + flash light driver. + + To compile this driver as a module, choose M here: the + module will be called lm3554 diff --git a/drivers/staging/media/atomisp/i2c/Makefile b/drivers/staging/media/atomisp/i2c/Makefile new file mode 100644 index 000000000..8d022986e --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/Makefile @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for sensor drivers +# + +obj-$(CONFIG_VIDEO_ATOMISP_OV5693) += ov5693/ +obj-$(CONFIG_VIDEO_ATOMISP_MT9M114) += atomisp-mt9m114.o +obj-$(CONFIG_VIDEO_ATOMISP_GC2235) += atomisp-gc2235.o +obj-$(CONFIG_VIDEO_ATOMISP_OV2722) += atomisp-ov2722.o +obj-$(CONFIG_VIDEO_ATOMISP_OV2680) += atomisp-ov2680.o +obj-$(CONFIG_VIDEO_ATOMISP_GC0310) += atomisp-gc0310.o + +obj-$(CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER) += atomisp-libmsrlisthelper.o + +# Makefile for flash drivers +# + +obj-$(CONFIG_VIDEO_ATOMISP_LM3554) += atomisp-lm3554.o diff --git a/drivers/staging/media/atomisp/i2c/atomisp-gc0310.c b/drivers/staging/media/atomisp/i2c/atomisp-gc0310.c new file mode 100644 index 000000000..87a634bf9 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/atomisp-gc0310.c @@ -0,0 +1,1309 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for GalaxyCore GC0310 VGA camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../include/linux/atomisp_gmin_platform.h" + +#include "gc0310.h" + +/* i2c read/write stuff */ +static int gc0310_read_reg(struct i2c_client *client, + u16 data_length, u8 reg, u8 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[1]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != GC0310_8BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0, sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == GC0310_8BIT) + *val = (u8)data[0]; + + return 0; +} + +static int gc0310_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int gc0310_write_reg(struct i2c_client *client, u16 data_length, + u8 reg, u8 val) +{ + int ret; + unsigned char data[2] = {0}; + u8 *wreg = (u8 *)data; + const u16 len = data_length + sizeof(u8); /* 8-bit address + data */ + + if (data_length != GC0310_8BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = (u8)(reg & 0xff); + + if (data_length == GC0310_8BIT) + data[1] = (u8)(val); + + ret = gc0310_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * gc0310_write_reg_array - Initializes a list of GC0310 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __gc0310_flush_reg_array, __gc0310_buf_reg_array() and + * __gc0310_write_reg_is_consecutive() are internal functions to + * gc0310_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __gc0310_flush_reg_array(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u8) + ctrl->index; /* 8-bit address + data */ + ctrl->buffer.addr = (u8)(ctrl->buffer.addr); + ctrl->index = 0; + + return gc0310_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __gc0310_buf_reg_array(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl, + const struct gc0310_reg *next) +{ + int size; + + switch (next->type) { + case GC0310_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u8) >= GC0310_MAX_WRITE_BUF_SIZE) + return __gc0310_flush_reg_array(client, ctrl); + + return 0; +} + +static int __gc0310_write_reg_is_consecutive(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl, + const struct gc0310_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int gc0310_write_reg_array(struct i2c_client *client, + const struct gc0310_reg *reglist) +{ + const struct gc0310_reg *next = reglist; + struct gc0310_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != GC0310_TOK_TERM; next++) { + switch (next->type & GC0310_TOK_MASK) { + case GC0310_TOK_DELAY: + err = __gc0310_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__gc0310_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __gc0310_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __gc0310_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __gc0310_flush_reg_array(client, &ctrl); +} + +static int gc0310_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC0310_FOCAL_LENGTH_NUM << 16) | GC0310_FOCAL_LENGTH_DEM; + return 0; +} + +static int gc0310_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (GC0310_F_NUMBER_DEFAULT_NUM << 16) | GC0310_F_NUMBER_DEM; + return 0; +} + +static int gc0310_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC0310_F_NUMBER_DEFAULT_NUM << 24) | + (GC0310_F_NUMBER_DEM << 16) | + (GC0310_F_NUMBER_DEFAULT_NUM << 8) | GC0310_F_NUMBER_DEM; + return 0; +} + +static int gc0310_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + *val = dev->res->bin_factor_x; + + return 0; +} + +static int gc0310_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + *val = dev->res->bin_factor_y; + + return 0; +} + +static int gc0310_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct gc0310_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + u16 val; + u8 reg_val; + int ret; + unsigned int hori_blanking; + unsigned int vert_blanking; + unsigned int sh_delay; + + if (!info) + return -EINVAL; + + /* pixel clock calculattion */ + dev->vt_pix_clk_freq_mhz = 14400000; // 16.8MHz + buf->vt_pix_clk_freq_mhz = dev->vt_pix_clk_freq_mhz; + dev_dbg(&client->dev, "vt_pix_clk_freq_mhz=%d\n", buf->vt_pix_clk_freq_mhz); + + /* get integration time */ + buf->coarse_integration_time_min = GC0310_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + GC0310_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = GC0310_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + GC0310_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = GC0310_FINE_INTG_TIME_MIN; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + /* Getting crop_horizontal_start */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_CROP_START_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_CROP_START_L, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = val | (reg_val & 0xFF); + dev_dbg(&client->dev, "crop_horizontal_start=%d\n", buf->crop_horizontal_start); + + /* Getting crop_vertical_start */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_CROP_START_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_CROP_START_L, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = val | (reg_val & 0xFF); + dev_dbg(&client->dev, "crop_vertical_start=%d\n", buf->crop_vertical_start); + + /* Getting output_width */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_OUTSIZE_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_width = val | (reg_val & 0xFF); + dev_dbg(&client->dev, "output_width=%d\n", buf->output_width); + + /* Getting output_height */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_OUTSIZE_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_height = val | (reg_val & 0xFF); + dev_dbg(&client->dev, "output_height=%d\n", buf->output_height); + + buf->crop_horizontal_end = buf->crop_horizontal_start + buf->output_width - 1; + buf->crop_vertical_end = buf->crop_vertical_start + buf->output_height - 1; + dev_dbg(&client->dev, "crop_horizontal_end=%d\n", buf->crop_horizontal_end); + dev_dbg(&client->dev, "crop_vertical_end=%d\n", buf->crop_vertical_end); + + /* Getting line_length_pck */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_BLANKING_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_BLANKING_L, ®_val); + if (ret) + return ret; + hori_blanking = val | (reg_val & 0xFF); + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SH_DELAY, ®_val); + if (ret) + return ret; + sh_delay = reg_val; + buf->line_length_pck = buf->output_width + hori_blanking + sh_delay + 4; + dev_dbg(&client->dev, "hori_blanking=%d sh_delay=%d line_length_pck=%d\n", hori_blanking, + sh_delay, buf->line_length_pck); + + /* Getting frame_length_lines */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_BLANKING_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_BLANKING_L, ®_val); + if (ret) + return ret; + vert_blanking = val | (reg_val & 0xFF); + buf->frame_length_lines = buf->output_height + vert_blanking; + dev_dbg(&client->dev, "vert_blanking=%d frame_length_lines=%d\n", vert_blanking, + buf->frame_length_lines); + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static int gc0310_set_gain(struct v4l2_subdev *sd, int gain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 again, dgain; + + if (gain < 0x20) + gain = 0x20; + if (gain > 0x80) + gain = 0x80; + + if (gain >= 0x20 && gain < 0x40) { + again = 0x0; /* sqrt(2) */ + dgain = gain; + } else { + again = 0x2; /* 2 * sqrt(2) */ + dgain = gain / 2; + } + + dev_dbg(&client->dev, "gain=0x%x again=0x%x dgain=0x%x\n", gain, again, dgain); + + /* set analog gain */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AGC_ADJ, again); + if (ret) + return ret; + + /* set digital gain */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_DGC_ADJ, dgain); + if (ret) + return ret; + + return 0; +} + +static int __gc0310_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + dev_dbg(&client->dev, "coarse_itg=%d gain=%d digitgain=%d\n", coarse_itg, gain, digitgain); + + /* set exposure */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_L, + coarse_itg & 0xff); + if (ret) + return ret; + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_H, + (coarse_itg >> 8) & 0x0f); + if (ret) + return ret; + + ret = gc0310_set_gain(sd, gain); + if (ret) + return ret; + + return ret; +} + +static int gc0310_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __gc0310_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long gc0310_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return gc0310_set_exposure(sd, exp, gain, digitgain); +} + +/* TO DO */ +static int gc0310_v_flip(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +/* TO DO */ +static int gc0310_h_flip(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +static long gc0310_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return gc0310_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int gc0310_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 reg_v; + int ret; + + /* get exposure */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_L, + ®_v); + if (ret) + goto err; + + *value = reg_v; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_H, + ®_v); + if (ret) + goto err; + + *value = *value + (reg_v << 8); +err: + return ret; +} + +static int gc0310_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc0310_device *dev = + container_of(ctrl->handler, struct gc0310_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = gc0310_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = gc0310_h_flip(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int gc0310_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc0310_device *dev = + container_of(ctrl->handler, struct gc0310_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = gc0310_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = gc0310_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = gc0310_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = gc0310_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = gc0310_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = gc0310_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = gc0310_s_ctrl, + .g_volatile_ctrl = gc0310_g_volatile_ctrl +}; + +static const struct v4l2_ctrl_config gc0310_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = GC0310_FOCAL_LENGTH_DEFAULT, + .max = GC0310_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = GC0310_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = GC0310_F_NUMBER_DEFAULT, + .max = GC0310_F_NUMBER_DEFAULT, + .step = 0x01, + .def = GC0310_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = GC0310_F_NUMBER_RANGE, + .max = GC0310_F_NUMBER_RANGE, + .step = 0x01, + .def = GC0310_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = GC0310_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = GC0310_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int gc0310_init(struct v4l2_subdev *sd) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct gc0310_device *dev = to_gc0310_sensor(sd); + + mutex_lock(&dev->input_lock); + + /* set initial registers */ + ret = gc0310_write_reg_array(client, gc0310_reset_register); + + /* restore settings */ + gc0310_res = gc0310_res_preview; + N_RES = N_RES_PREVIEW; + + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = 0; + struct gc0310_device *dev = to_gc0310_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + if (flag) { + /* The upstream module driver (written to Crystal + * Cove) had this logic to pulse the rails low first. + * This appears to break things on the MRD7 with the + * X-Powers PMIC... + * + * ret = dev->platform_data->v1p8_ctrl(sd, 0); + * ret |= dev->platform_data->v2p8_ctrl(sd, 0); + * mdelay(50); + */ + ret |= dev->platform_data->v1p8_ctrl(sd, 1); + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + usleep_range(10000, 15000); + } + + if (!flag || ret) { + ret |= dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct gc0310_device *dev = to_gc0310_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* GPIO0 == "reset" (active low), GPIO1 == "power down" */ + if (flag) { + /* Pulse reset, then release power down */ + ret = dev->platform_data->gpio0_ctrl(sd, 0); + usleep_range(5000, 10000); + ret |= dev->platform_data->gpio0_ctrl(sd, 1); + usleep_range(10000, 15000); + ret |= dev->platform_data->gpio1_ctrl(sd, 0); + usleep_range(10000, 15000); + } else { + ret = dev->platform_data->gpio1_ctrl(sd, 1); + ret |= dev->platform_data->gpio0_ctrl(sd, 0); + } + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + if (dev->power_on) + return 0; /* Already on */ + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_gpio; + } + + msleep(100); + + dev->power_on = true; + return 0; + +fail_gpio: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_clk: + power_ctrl(sd, 0); +fail_power: + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + if (!dev->power_on) + return 0; /* Already off */ + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + dev->power_on = false; + return ret; +} + +static int gc0310_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + if (on == 0) + return power_down(sd); + + ret = power_up(sd); + if (ret) + return ret; + + return gc0310_init(sd); +} + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + ret = gc0310_write_reg_array(client, dev->res->regs); + if (ret) { + dev_err(&client->dev, "gc0310 write register err.\n"); + return ret; + } + + return ret; +} + +static int gc0310_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *gc0310_info = NULL; + struct gc0310_resolution *res; + int ret = 0; + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + gc0310_info = v4l2_get_subdev_hostdata(sd); + if (!gc0310_info) + return -EINVAL; + + mutex_lock(&dev->input_lock); + + res = v4l2_find_nearest_size(gc0310_res_preview, + ARRAY_SIZE(gc0310_res_preview), width, + height, fmt->width, fmt->height); + if (!res) + res = &gc0310_res_preview[N_RES - 1]; + + fmt->width = res->width; + fmt->height = res->height; + dev->res = res; + + fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + sd_state->pads->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + /* s_power has not been called yet for std v4l2 clients (camorama) */ + power_up(sd); + + dev_dbg(&client->dev, "%s: before gc0310_write_reg_array %s\n", + __func__, dev->res->desc); + ret = startup(sd); + if (ret) { + dev_err(&client->dev, "gc0310 startup err\n"); + goto err; + } + + ret = gc0310_get_intg_factor(client, gc0310_info, dev->res); + if (ret) { + dev_err(&client->dev, "failed to get integration_factor\n"); + goto err; + } + +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc0310_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc0310_device *dev = to_gc0310_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = dev->res->width; + fmt->height = dev->res->height; + fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; + + return 0; +} + +static int gc0310_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u8 high, low; + int ret; + u16 id; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "read sensor_id_high failed\n"); + return -ENODEV; + } + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SC_CMMN_CHIP_ID_L, &low); + if (ret) { + dev_err(&client->dev, "read sensor_id_low failed\n"); + return -ENODEV; + } + id = ((((u16)high) << 8) | (u16)low); + dev_dbg(&client->dev, "sensor ID = 0x%x\n", id); + + if (id != GC0310_ID) { + dev_err(&client->dev, "sensor ID error, read id = 0x%x, target id = 0x%x\n", id, + GC0310_ID); + return -ENODEV; + } + + dev_dbg(&client->dev, "detect gc0310 success\n"); + + return 0; +} + +static int gc0310_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + dev_dbg(&client->dev, "%s S enable=%d\n", __func__, enable); + mutex_lock(&dev->input_lock); + + if (enable) { + /* enable per frame MIPI and sensor ctrl reset */ + ret = gc0310_write_reg(client, GC0310_8BIT, + 0xFE, 0x30); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + } + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_3); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = gc0310_write_reg(client, GC0310_8BIT, GC0310_SW_STREAM, + enable ? GC0310_START_STREAMING : + GC0310_STOP_STREAMING); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_0); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc0310_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + dev->power_on = true; /* force power_down() to run */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = gc0310_detect(client); + if (ret) { + dev_err(&client->dev, "gc0310_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc0310_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = dev->res->fps; + + return 0; +} + +static int gc0310_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SGRBG8_1X8; + return 0; +} + +static int gc0310_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = gc0310_res[index].width; + fse->min_height = gc0310_res[index].height; + fse->max_width = gc0310_res[index].width; + fse->max_height = gc0310_res[index].height; + + return 0; +} + +static int gc0310_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->res->skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops gc0310_sensor_ops = { + .g_skip_frames = gc0310_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops gc0310_video_ops = { + .s_stream = gc0310_s_stream, + .g_frame_interval = gc0310_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops gc0310_core_ops = { + .s_power = gc0310_s_power, + .ioctl = gc0310_ioctl, +}; + +static const struct v4l2_subdev_pad_ops gc0310_pad_ops = { + .enum_mbus_code = gc0310_enum_mbus_code, + .enum_frame_size = gc0310_enum_frame_size, + .get_fmt = gc0310_get_fmt, + .set_fmt = gc0310_set_fmt, +}; + +static const struct v4l2_subdev_ops gc0310_ops = { + .core = &gc0310_core_ops, + .video = &gc0310_video_ops, + .pad = &gc0310_pad_ops, + .sensor = &gc0310_sensor_ops, +}; + +static void gc0310_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc0310_device *dev = to_gc0310_sensor(sd); + + dev_dbg(&client->dev, "gc0310_remove...\n"); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); +} + +static int gc0310_probe(struct i2c_client *client) +{ + struct gc0310_device *dev; + int ret; + void *pdata; + unsigned int i; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + mutex_init(&dev->input_lock); + + dev->res = &gc0310_res_preview[0]; + v4l2_i2c_subdev_init(&dev->sd, client, &gc0310_ops); + + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_8, + atomisp_bayer_order_grbg); + if (!pdata) { + ret = -EINVAL; + goto out_free; + } + + ret = gc0310_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SGRBG8_1X8; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(gc0310_controls)); + if (ret) { + gc0310_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(gc0310_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &gc0310_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + gc0310_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + gc0310_remove(client); + + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct acpi_device_id gc0310_acpi_match[] = { + {"XXGC0310"}, + {"INT0310"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, gc0310_acpi_match); + +static struct i2c_driver gc0310_driver = { + .driver = { + .name = "gc0310", + .acpi_match_table = gc0310_acpi_match, + }, + .probe_new = gc0310_probe, + .remove = gc0310_remove, +}; +module_i2c_driver(gc0310_driver); + +MODULE_AUTHOR("Lai, Angie "); +MODULE_DESCRIPTION("A low-level driver for GalaxyCore GC0310 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/atomisp-gc2235.c b/drivers/staging/media/atomisp/i2c/atomisp-gc2235.c new file mode 100644 index 000000000..4d5a7e335 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/atomisp-gc2235.c @@ -0,0 +1,1050 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for GalaxyCore GC2235 2M camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../include/linux/atomisp_gmin_platform.h" +#include +#include + +#include "gc2235.h" + +/* i2c read/write stuff */ +static int gc2235_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != GC2235_8BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0, sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == GC2235_8BIT) + *val = (u8)data[0]; + + return 0; +} + +static int gc2235_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int gc2235_write_reg(struct i2c_client *client, u16 data_length, + u8 reg, u8 val) +{ + int ret; + unsigned char data[4] = {0}; + const u16 len = data_length + sizeof(u8); /* 16-bit address + data */ + + if (data_length != GC2235_8BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + data[0] = reg; + data[1] = val; + + ret = gc2235_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +static int __gc2235_flush_reg_array(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u8) + ctrl->index; /* 8-bit address + data */ + ctrl->index = 0; + + return gc2235_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __gc2235_buf_reg_array(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl, + const struct gc2235_reg *next) +{ + int size; + + if (next->type != GC2235_8BIT) + return -EINVAL; + + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u8) >= GC2235_MAX_WRITE_BUF_SIZE) + return __gc2235_flush_reg_array(client, ctrl); + + return 0; +} + +static int __gc2235_write_reg_is_consecutive(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl, + const struct gc2235_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int gc2235_write_reg_array(struct i2c_client *client, + const struct gc2235_reg *reglist) +{ + const struct gc2235_reg *next = reglist; + struct gc2235_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != GC2235_TOK_TERM; next++) { + switch (next->type & GC2235_TOK_MASK) { + case GC2235_TOK_DELAY: + err = __gc2235_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__gc2235_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __gc2235_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __gc2235_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __gc2235_flush_reg_array(client, &ctrl); +} + +static int gc2235_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC2235_FOCAL_LENGTH_NUM << 16) | GC2235_FOCAL_LENGTH_DEM; + return 0; +} + +static int gc2235_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /* const f number for imx */ + *val = (GC2235_F_NUMBER_DEFAULT_NUM << 16) | GC2235_F_NUMBER_DEM; + return 0; +} + +static int gc2235_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC2235_F_NUMBER_DEFAULT_NUM << 24) | + (GC2235_F_NUMBER_DEM << 16) | + (GC2235_F_NUMBER_DEFAULT_NUM << 8) | GC2235_F_NUMBER_DEM; + return 0; +} + +static int gc2235_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct gc2235_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + u16 reg_val, reg_val_h; + int ret; + + if (!info) + return -EINVAL; + + /* pixel clock calculattion */ + buf->vt_pix_clk_freq_mhz = dev->vt_pix_clk_freq_mhz = 30000000; + + /* get integration time */ + buf->coarse_integration_time_min = GC2235_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + GC2235_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = GC2235_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + GC2235_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = GC2235_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_CROP_START_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_CROP_START_L, ®_val); + if (ret) + return ret; + + buf->crop_horizontal_start = (reg_val_h << 8) | reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_CROP_START_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_CROP_START_L, ®_val); + if (ret) + return ret; + + buf->crop_vertical_start = (reg_val_h << 8) | reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_OUTSIZE_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_width = (reg_val_h << 8) | reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_OUTSIZE_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_height = (reg_val_h << 8) | reg_val; + + buf->crop_horizontal_end = buf->crop_horizontal_start + + buf->output_width - 1; + buf->crop_vertical_end = buf->crop_vertical_start + + buf->output_height - 1; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_HB_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_HB_L, ®_val); + if (ret) + return ret; + +#if 0 + u16 dummy = (reg_val_h << 8) | reg_val; +#endif + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SH_DELAY_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SH_DELAY_L, ®_val); + +#if 0 + buf->line_length_pck = buf->output_width + 16 + dummy + + (((u16)reg_val_h << 8) | (u16)reg_val) + 4; +#endif + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_VB_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_VB_L, ®_val); + if (ret) + return ret; + +#if 0 + buf->frame_length_lines = buf->output_height + 32 + + (((u16)reg_val_h << 8) | (u16)reg_val); +#endif + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __gc2235_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 coarse_integration = (u16)coarse_itg; + int ret = 0; + u16 expo_coarse_h, expo_coarse_l, gain_val = 0xF0, gain_val2 = 0xF0; + + expo_coarse_h = coarse_integration >> 8; + expo_coarse_l = coarse_integration & 0xff; + + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_H, expo_coarse_h); + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_L, expo_coarse_l); + + if (gain <= 0x58) { + gain_val = 0x40; + gain_val2 = 0x58; + } else if (gain < 256) { + gain_val = 0x40; + gain_val2 = gain; + } else { + gain_val2 = 64 * gain / 256; + gain_val = 0xff; + } + + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_GLOBAL_GAIN, (u8)gain_val); + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_PRE_GAIN, (u8)gain_val2); + + return ret; +} + +static int gc2235_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __gc2235_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long gc2235_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return gc2235_set_exposure(sd, exp, gain, digitgain); +} + +static long gc2235_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return gc2235_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* + * This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int gc2235_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_L, + ®_v); + if (ret) + goto err; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_H, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + + *value = reg_v; +err: + return ret; +} + +static int gc2235_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc2235_device *dev = + container_of(ctrl->handler, struct gc2235_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = gc2235_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = gc2235_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = gc2235_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = gc2235_g_fnumber_range(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .g_volatile_ctrl = gc2235_g_volatile_ctrl +}; + +static struct v4l2_ctrl_config gc2235_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = GC2235_FOCAL_LENGTH_DEFAULT, + .max = GC2235_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = GC2235_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = GC2235_F_NUMBER_DEFAULT, + .max = GC2235_F_NUMBER_DEFAULT, + .step = 0x01, + .def = GC2235_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = GC2235_F_NUMBER_RANGE, + .max = GC2235_F_NUMBER_RANGE, + .step = 0x01, + .def = GC2235_F_NUMBER_RANGE, + .flags = 0, + }, +}; + +static int __gc2235_init(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + /* restore settings */ + gc2235_res = gc2235_res_preview; + N_RES = N_RES_PREVIEW; + + return gc2235_write_reg_array(client, gc2235_init_settings); +} + +static int is_init; + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = -1; + struct gc2235_device *dev = to_gc2235_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + if (flag) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + usleep_range(60, 90); + if (ret == 0) + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + } else { + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + int ret; + + if (!dev || !dev->platform_data) + return -ENODEV; + + ret = dev->platform_data->gpio1_ctrl(sd, !flag); + usleep_range(60, 90); + ret |= dev->platform_data->gpio0_ctrl(sd, flag); + + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + msleep(5); + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int gc2235_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + if (on == 0) { + ret = power_down(sd); + } else { + ret = power_up(sd); + if (!ret) + ret = __gc2235_init(sd); + is_init = 1; + } + return ret; +} + +static int startup(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (is_init == 0) { + /* + * force gc2235 to do a reset in res change, otherwise it + * can not output normal after switching res. and it is not + * necessary for first time run up after power on, for the sack + * of performance + */ + power_down(sd); + power_up(sd); + gc2235_write_reg_array(client, gc2235_init_settings); + } + + ret = gc2235_write_reg_array(client, dev->res->regs); + if (ret) { + dev_err(&client->dev, "gc2235 write register err.\n"); + return ret; + } + is_init = 0; + + return ret; +} + +static int gc2235_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *gc2235_info = NULL; + struct gc2235_resolution *res; + int ret = 0; + + gc2235_info = v4l2_get_subdev_hostdata(sd); + if (!gc2235_info) + return -EINVAL; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + mutex_lock(&dev->input_lock); + res = v4l2_find_nearest_size(gc2235_res_preview, + ARRAY_SIZE(gc2235_res_preview), width, + height, fmt->width, fmt->height); + if (!res) + res = &gc2235_res_preview[N_RES - 1]; + + fmt->width = res->width; + fmt->height = res->height; + dev->res = res; + + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + sd_state->pads->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + ret = startup(sd); + if (ret) { + dev_err(&client->dev, "gc2235 startup err\n"); + goto err; + } + + ret = gc2235_get_intg_factor(client, gc2235_info, + dev->res); + if (ret) + dev_err(&client->dev, "failed to get integration_factor\n"); + +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc2235_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc2235_device *dev = to_gc2235_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = dev->res->width; + fmt->height = dev->res->height; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int gc2235_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high = 0, low = 0; + u16 id; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + gc2235_read_reg(client, GC2235_8BIT, GC2235_SENSOR_ID_H, &high); + gc2235_read_reg(client, GC2235_8BIT, GC2235_SENSOR_ID_L, &low); + id = ((high << 8) | low); + + if (id != GC2235_ID) { + dev_err(&client->dev, "sensor ID error, 0x%x\n", id); + return -ENODEV; + } + + dev_info(&client->dev, "detect gc2235 success\n"); + return 0; +} + +static int gc2235_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + + if (enable) + ret = gc2235_write_reg_array(client, gc2235_stream_on); + else + ret = gc2235_write_reg_array(client, gc2235_stream_off); + + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc2235_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + /* + * power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = gc2235_detect(client); + if (ret) { + dev_err(&client->dev, "gc2235_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc2235_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = dev->res->fps; + + return 0; +} + +static int gc2235_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int gc2235_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = gc2235_res[index].width; + fse->min_height = gc2235_res[index].height; + fse->max_width = gc2235_res[index].width; + fse->max_height = gc2235_res[index].height; + + return 0; +} + +static int gc2235_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->res->skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops gc2235_sensor_ops = { + .g_skip_frames = gc2235_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops gc2235_video_ops = { + .s_stream = gc2235_s_stream, + .g_frame_interval = gc2235_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops gc2235_core_ops = { + .s_power = gc2235_s_power, + .ioctl = gc2235_ioctl, +}; + +static const struct v4l2_subdev_pad_ops gc2235_pad_ops = { + .enum_mbus_code = gc2235_enum_mbus_code, + .enum_frame_size = gc2235_enum_frame_size, + .get_fmt = gc2235_get_fmt, + .set_fmt = gc2235_set_fmt, +}; + +static const struct v4l2_subdev_ops gc2235_ops = { + .core = &gc2235_core_ops, + .video = &gc2235_video_ops, + .pad = &gc2235_pad_ops, + .sensor = &gc2235_sensor_ops, +}; + +static void gc2235_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc2235_device *dev = to_gc2235_sensor(sd); + + dev_dbg(&client->dev, "gc2235_remove...\n"); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); +} + +static int gc2235_probe(struct i2c_client *client) +{ + struct gc2235_device *dev; + void *gcpdev; + int ret; + unsigned int i; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + mutex_init(&dev->input_lock); + + dev->res = &gc2235_res_preview[0]; + v4l2_i2c_subdev_init(&dev->sd, client, &gc2235_ops); + + gcpdev = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + + ret = gc2235_s_config(&dev->sd, client->irq, gcpdev); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(gc2235_controls)); + if (ret) { + gc2235_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(gc2235_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &gc2235_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + gc2235_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + gc2235_remove(client); + + return atomisp_register_i2c_module(&dev->sd, gcpdev, RAW_CAMERA); + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + + return ret; +} + +static const struct acpi_device_id gc2235_acpi_match[] = { + { "INT33F8" }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, gc2235_acpi_match); + +static struct i2c_driver gc2235_driver = { + .driver = { + .name = "gc2235", + .acpi_match_table = gc2235_acpi_match, + }, + .probe_new = gc2235_probe, + .remove = gc2235_remove, +}; +module_i2c_driver(gc2235_driver); + +MODULE_AUTHOR("Shuguang Gong "); +MODULE_DESCRIPTION("A low-level driver for GC2235 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/atomisp-libmsrlisthelper.c b/drivers/staging/media/atomisp/i2c/atomisp-libmsrlisthelper.c new file mode 100644 index 000000000..7a20d918a --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/atomisp-libmsrlisthelper.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#include +#include +#include +#include +#include "../include/linux/libmsrlisthelper.h" +#include +#include + +/* Tagged binary data container structure definitions. */ +struct tbd_header { + u32 tag; /*!< Tag identifier, also checks endianness */ + u32 size; /*!< Container size including this header */ + u32 version; /*!< Version, format 0xYYMMDDVV */ + u32 revision; /*!< Revision, format 0xYYMMDDVV */ + u32 config_bits; /*!< Configuration flag bits set */ + u32 checksum; /*!< Global checksum, header included */ +} __packed; + +struct tbd_record_header { + u32 size; /*!< Size of record including header */ + u8 format_id; /*!< tbd_format_t enumeration values used */ + u8 packing_key; /*!< Packing method; 0 = no packing */ + u16 class_id; /*!< tbd_class_t enumeration values used */ +} __packed; + +struct tbd_data_record_header { + u16 next_offset; + u16 flags; + u16 data_offset; + u16 data_size; +} __packed; + +#define TBD_CLASS_DRV_ID 2 + +static int set_msr_configuration(struct i2c_client *client, uint8_t *bufptr, + unsigned int size) +{ + /* + * The configuration data contains any number of sequences where + * the first byte (that is, uint8_t) that marks the number of bytes + * in the sequence to follow, is indeed followed by the indicated + * number of bytes of actual data to be written to sensor. + * By convention, the first two bytes of actual data should be + * understood as an address in the sensor address space (hibyte + * followed by lobyte) where the remaining data in the sequence + * will be written. + */ + + u8 *ptr = bufptr; + + while (ptr < bufptr + size) { + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + }; + int ret; + + /* How many bytes */ + msg.len = *ptr++; + /* Where the bytes are located */ + msg.buf = ptr; + ptr += msg.len; + + if (ptr > bufptr + size) + /* Accessing data beyond bounds is not tolerated */ + return -EINVAL; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret < 0) { + dev_err(&client->dev, "i2c write error: %d", ret); + return ret; + } + } + return 0; +} + +static int parse_and_apply(struct i2c_client *client, uint8_t *buffer, + unsigned int size) +{ + u8 *endptr8 = buffer + size; + struct tbd_data_record_header *header = + (struct tbd_data_record_header *)buffer; + + /* There may be any number of datasets present */ + unsigned int dataset = 0; + + do { + /* In below, four variables are read from buffer */ + if ((uint8_t *)header + sizeof(*header) > endptr8) + return -EINVAL; + + /* All data should be located within given buffer */ + if ((uint8_t *)header + header->data_offset + + header->data_size > endptr8) + return -EINVAL; + + /* We have a new valid dataset */ + dataset++; + /* See whether there is MSR data */ + /* If yes, update the reg info */ + if (header->data_size && (header->flags & 1)) { + int ret; + + dev_info(&client->dev, + "New MSR data for sensor driver (dataset %02d) size:%d\n", + dataset, header->data_size); + ret = set_msr_configuration(client, + buffer + header->data_offset, + header->data_size); + if (ret) + return ret; + } + header = (struct tbd_data_record_header *)(buffer + + header->next_offset); + } while (header->next_offset); + + return 0; +} + +int apply_msr_data(struct i2c_client *client, const struct firmware *fw) +{ + struct tbd_header *header; + struct tbd_record_header *record; + + if (!fw) { + dev_warn(&client->dev, "Drv data is not loaded.\n"); + return -EINVAL; + } + + if (sizeof(*header) > fw->size) + return -EINVAL; + + header = (struct tbd_header *)fw->data; + /* Check that we have drvb block. */ + if (memcmp(&header->tag, "DRVB", 4)) + return -EINVAL; + + /* Check the size */ + if (header->size != fw->size) + return -EINVAL; + + if (sizeof(*header) + sizeof(*record) > fw->size) + return -EINVAL; + + record = (struct tbd_record_header *)(header + 1); + /* Check that class id mathes tbd's drv id. */ + if (record->class_id != TBD_CLASS_DRV_ID) + return -EINVAL; + + /* Size 0 shall not be treated as an error */ + if (!record->size) + return 0; + + return parse_and_apply(client, (uint8_t *)(record + 1), record->size); +} +EXPORT_SYMBOL_GPL(apply_msr_data); + +int load_msr_list(struct i2c_client *client, char *name, + const struct firmware **fw) +{ + int ret = request_firmware(fw, name, &client->dev); + + if (ret) { + dev_err(&client->dev, + "Error %d while requesting firmware %s\n", + ret, name); + return ret; + } + dev_info(&client->dev, "Received %lu bytes drv data\n", + (unsigned long)(*fw)->size); + + return 0; +} +EXPORT_SYMBOL_GPL(load_msr_list); + +void release_msr_list(struct i2c_client *client, const struct firmware *fw) +{ + release_firmware(fw); +} +EXPORT_SYMBOL_GPL(release_msr_list); + +static int init_msrlisthelper(void) +{ + return 0; +} + +static void exit_msrlisthelper(void) +{ +} + +module_init(init_msrlisthelper); +module_exit(exit_msrlisthelper); + +MODULE_AUTHOR("Jukka Kaartinen "); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/atomisp-lm3554.c b/drivers/staging/media/atomisp/i2c/atomisp-lm3554.c new file mode 100644 index 000000000..c4ce4cd44 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/atomisp-lm3554.c @@ -0,0 +1,955 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LED flash driver for LM3554 + * + * Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#include +#include +#include +#include +#include +#include + +#include "../include/media/lm3554.h" +#include +#include +#include +#include "../include/linux/atomisp_gmin_platform.h" +#include "../include/linux/atomisp.h" + +/* Registers */ + +#define LM3554_TORCH_BRIGHTNESS_REG 0xA0 +#define LM3554_TORCH_MODE_SHIFT 0 +#define LM3554_TORCH_CURRENT_SHIFT 3 +#define LM3554_INDICATOR_CURRENT_SHIFT 6 + +#define LM3554_FLASH_BRIGHTNESS_REG 0xB0 +#define LM3554_FLASH_MODE_SHIFT 0 +#define LM3554_FLASH_CURRENT_SHIFT 3 +#define LM3554_STROBE_SENSITIVITY_SHIFT 7 + +#define LM3554_FLASH_DURATION_REG 0xC0 +#define LM3554_FLASH_TIMEOUT_SHIFT 0 +#define LM3554_CURRENT_LIMIT_SHIFT 5 + +#define LM3554_FLAGS_REG 0xD0 +#define LM3554_FLAG_TIMEOUT BIT(0) +#define LM3554_FLAG_THERMAL_SHUTDOWN BIT(1) +#define LM3554_FLAG_LED_FAULT BIT(2) +#define LM3554_FLAG_TX1_INTERRUPT BIT(3) +#define LM3554_FLAG_TX2_INTERRUPT BIT(4) +#define LM3554_FLAG_LED_THERMAL_FAULT BIT(5) +#define LM3554_FLAG_UNUSED BIT(6) +#define LM3554_FLAG_INPUT_VOLTAGE_LOW BIT(7) + +#define LM3554_CONFIG_REG_1 0xE0 +#define LM3554_ENVM_TX2_SHIFT 5 +#define LM3554_TX2_POLARITY_SHIFT 6 + +struct lm3554 { + struct v4l2_subdev sd; + + struct mutex power_lock; + struct v4l2_ctrl_handler ctrl_handler; + int power_count; + + unsigned int mode; + int timeout; + u8 torch_current; + u8 indicator_current; + u8 flash_current; + + struct timer_list flash_off_delay; + struct lm3554_platform_data *pdata; +}; + +#define to_lm3554(p_sd) container_of(p_sd, struct lm3554, sd) + +/* Return negative errno else zero on success */ +static int lm3554_write(struct lm3554 *flash, u8 addr, u8 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + ret = i2c_smbus_write_byte_data(client, addr, val); + + dev_dbg(&client->dev, "Write Addr:%02X Val:%02X %s\n", addr, val, + ret < 0 ? "fail" : "ok"); + + return ret; +} + +/* Return negative errno else a data byte received from the device. */ +static int lm3554_read(struct lm3554 *flash, u8 addr) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + ret = i2c_smbus_read_byte_data(client, addr); + + dev_dbg(&client->dev, "Read Addr:%02X Val:%02X %s\n", addr, ret, + ret < 0 ? "fail" : "ok"); + + return ret; +} + +/* ----------------------------------------------------------------------------- + * Hardware configuration + */ + +static int lm3554_set_mode(struct lm3554 *flash, unsigned int mode) +{ + u8 val; + int ret; + + val = (mode << LM3554_FLASH_MODE_SHIFT) | + (flash->flash_current << LM3554_FLASH_CURRENT_SHIFT); + + ret = lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, val); + if (ret == 0) + flash->mode = mode; + return ret; +} + +static int lm3554_set_torch(struct lm3554 *flash) +{ + u8 val; + + val = (flash->mode << LM3554_TORCH_MODE_SHIFT) | + (flash->torch_current << LM3554_TORCH_CURRENT_SHIFT) | + (flash->indicator_current << LM3554_INDICATOR_CURRENT_SHIFT); + + return lm3554_write(flash, LM3554_TORCH_BRIGHTNESS_REG, val); +} + +static int lm3554_set_flash(struct lm3554 *flash) +{ + u8 val; + + val = (flash->mode << LM3554_FLASH_MODE_SHIFT) | + (flash->flash_current << LM3554_FLASH_CURRENT_SHIFT); + + return lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, val); +} + +static int lm3554_set_duration(struct lm3554 *flash) +{ + u8 val; + + val = (flash->timeout << LM3554_FLASH_TIMEOUT_SHIFT) | + (flash->pdata->current_limit << LM3554_CURRENT_LIMIT_SHIFT); + + return lm3554_write(flash, LM3554_FLASH_DURATION_REG, val); +} + +static int lm3554_set_config1(struct lm3554 *flash) +{ + u8 val; + + val = (flash->pdata->envm_tx2 << LM3554_ENVM_TX2_SHIFT) | + (flash->pdata->tx2_polarity << LM3554_TX2_POLARITY_SHIFT); + return lm3554_write(flash, LM3554_CONFIG_REG_1, val); +} + +/* ----------------------------------------------------------------------------- + * Hardware trigger + */ +static void lm3554_flash_off_delay(struct timer_list *t) +{ + struct lm3554 *flash = from_timer(flash, t, flash_off_delay); + struct lm3554_platform_data *pdata = flash->pdata; + + gpiod_set_value(pdata->gpio_strobe, 0); +} + +static int lm3554_hw_strobe(struct i2c_client *client, bool strobe) +{ + int ret, timer_pending; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + + /* + * An abnormal high flash current is observed when strobe off the + * flash. Workaround here is firstly set flash current to lower level, + * wait a short moment, and then strobe off the flash. + */ + + timer_pending = del_timer_sync(&flash->flash_off_delay); + + /* Flash off */ + if (!strobe) { + /* set current to 70mA and wait a while */ + ret = lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, 0); + if (ret < 0) + goto err; + mod_timer(&flash->flash_off_delay, + jiffies + msecs_to_jiffies(LM3554_TIMER_DELAY)); + return 0; + } + + /* Flash on */ + + /* + * If timer is killed before run, flash is not strobe off, + * so must strobe off here + */ + if (timer_pending) + gpiod_set_value(pdata->gpio_strobe, 0); + + /* Restore flash current settings */ + ret = lm3554_set_flash(flash); + if (ret < 0) + goto err; + + /* Strobe on Flash */ + gpiod_set_value(pdata->gpio_strobe, 1); + + return 0; +err: + dev_err(&client->dev, "failed to %s flash strobe (%d)\n", + strobe ? "on" : "off", ret); + return ret; +} + +/* ----------------------------------------------------------------------------- + * V4L2 controls + */ + +static int lm3554_read_status(struct lm3554 *flash) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + + /* NOTE: reading register clear fault status */ + ret = lm3554_read(flash, LM3554_FLAGS_REG); + if (ret < 0) + return ret; + + /* + * Accordingly to datasheet we read back '1' in bit 6. + * Clear it first. + */ + ret &= ~LM3554_FLAG_UNUSED; + + /* + * Do not take TX1/TX2 signal as an error + * because MSIC will not turn off flash, but turn to + * torch mode according to gsm modem signal by hardware. + */ + ret &= ~(LM3554_FLAG_TX1_INTERRUPT | LM3554_FLAG_TX2_INTERRUPT); + + if (ret > 0) + dev_dbg(&client->dev, "LM3554 flag status: %02x\n", ret); + + return ret; +} + +static int lm3554_s_flash_timeout(struct v4l2_subdev *sd, u32 val) +{ + struct lm3554 *flash = to_lm3554(sd); + + val = clamp(val, LM3554_MIN_TIMEOUT, LM3554_MAX_TIMEOUT); + val = val / LM3554_TIMEOUT_STEPSIZE - 1; + + flash->timeout = val; + + return lm3554_set_duration(flash); +} + +static int lm3554_g_flash_timeout(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = (u32)(flash->timeout + 1) * LM3554_TIMEOUT_STEPSIZE; + + return 0; +} + +static int lm3554_s_flash_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_FLASH_STEP); + + flash->flash_current = intensity; + + return lm3554_set_flash(flash); +} + +static int lm3554_g_flash_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->flash_current, + LM3554_FLASH_STEP); + + return 0; +} + +static int lm3554_s_torch_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_TORCH_STEP); + + flash->torch_current = intensity; + + return lm3554_set_torch(flash); +} + +static int lm3554_g_torch_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->torch_current, + LM3554_TORCH_STEP); + + return 0; +} + +static int lm3554_s_indicator_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_INDICATOR_STEP); + + flash->indicator_current = intensity; + + return lm3554_set_torch(flash); +} + +static int lm3554_g_indicator_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->indicator_current, + LM3554_INDICATOR_STEP); + + return 0; +} + +static int lm3554_s_flash_strobe(struct v4l2_subdev *sd, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return lm3554_hw_strobe(client, val); +} + +static int lm3554_s_flash_mode(struct v4l2_subdev *sd, u32 new_mode) +{ + struct lm3554 *flash = to_lm3554(sd); + unsigned int mode; + + switch (new_mode) { + case ATOMISP_FLASH_MODE_OFF: + mode = LM3554_MODE_SHUTDOWN; + break; + case ATOMISP_FLASH_MODE_FLASH: + mode = LM3554_MODE_FLASH; + break; + case ATOMISP_FLASH_MODE_INDICATOR: + mode = LM3554_MODE_INDICATOR; + break; + case ATOMISP_FLASH_MODE_TORCH: + mode = LM3554_MODE_TORCH; + break; + default: + return -EINVAL; + } + + return lm3554_set_mode(flash, mode); +} + +static int lm3554_g_flash_mode(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + *val = flash->mode; + return 0; +} + +static int lm3554_g_flash_status(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + int value; + + value = lm3554_read_status(flash); + if (value < 0) + return value; + + if (value & LM3554_FLAG_TIMEOUT) + *val = ATOMISP_FLASH_STATUS_TIMEOUT; + else if (value > 0) + *val = ATOMISP_FLASH_STATUS_HW_ERROR; + else + *val = ATOMISP_FLASH_STATUS_OK; + + return 0; +} + +static int lm3554_g_flash_status_register(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + int ret; + + ret = lm3554_read(flash, LM3554_FLAGS_REG); + + if (ret < 0) + return ret; + + *val = ret; + return 0; +} + +static int lm3554_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3554 *dev = + container_of(ctrl->handler, struct lm3554, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FLASH_TIMEOUT: + ret = lm3554_s_flash_timeout(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_INTENSITY: + ret = lm3554_s_flash_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_TORCH_INTENSITY: + ret = lm3554_s_torch_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + ret = lm3554_s_indicator_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_STROBE: + ret = lm3554_s_flash_strobe(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_MODE: + ret = lm3554_s_flash_mode(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int lm3554_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3554 *dev = + container_of(ctrl->handler, struct lm3554, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FLASH_TIMEOUT: + ret = lm3554_g_flash_timeout(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_INTENSITY: + ret = lm3554_g_flash_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_TORCH_INTENSITY: + ret = lm3554_g_torch_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + ret = lm3554_g_indicator_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_MODE: + ret = lm3554_g_flash_mode(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_STATUS: + ret = lm3554_g_flash_status(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_STATUS_REGISTER: + ret = lm3554_g_flash_status_register(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = lm3554_s_ctrl, + .g_volatile_ctrl = lm3554_g_volatile_ctrl +}; + +static const struct v4l2_ctrl_config lm3554_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_TIMEOUT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Timeout", + .min = 0x0, + .max = LM3554_MAX_TIMEOUT, + .step = 0x01, + .def = LM3554_DEFAULT_TIMEOUT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_FLASH_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_TORCH_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Torch Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_TORCH_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_INDICATOR_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Indicator Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_INDICATOR_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STROBE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flash Strobe", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Mode", + .min = 0, + .max = 100, + .step = 1, + .def = ATOMISP_FLASH_MODE_OFF, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Status", + .min = ATOMISP_FLASH_STATUS_OK, + .max = ATOMISP_FLASH_STATUS_TIMEOUT, + .step = 1, + .def = ATOMISP_FLASH_STATUS_OK, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STATUS_REGISTER, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Status Register", + .min = 0, + .max = 255, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +/* ----------------------------------------------------------------------------- + * V4L2 subdev core operations + */ + +/* Put device into known state. */ +static int lm3554_setup(struct lm3554 *flash) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + /* clear the flags register */ + ret = lm3554_read(flash, LM3554_FLAGS_REG); + if (ret < 0) + return ret; + + dev_dbg(&client->dev, "Fault info: %02x\n", ret); + + ret = lm3554_set_config1(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_duration(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_torch(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_flash(flash); + if (ret < 0) + return ret; + + /* read status */ + ret = lm3554_read_status(flash); + if (ret < 0) + return ret; + + return ret ? -EIO : 0; +} + +static int __lm3554_s_power(struct lm3554 *flash, int power) +{ + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + /*initialize flash driver*/ + gpiod_set_value(pdata->gpio_reset, power); + usleep_range(100, 100 + 1); + + if (power) { + /* Setup default values. This makes sure that the chip + * is in a known state. + */ + ret = lm3554_setup(flash); + if (ret < 0) { + __lm3554_s_power(flash, 0); + return ret; + } + } + + return 0; +} + +static int lm3554_s_power(struct v4l2_subdev *sd, int power) +{ + struct lm3554 *flash = to_lm3554(sd); + int ret = 0; + + mutex_lock(&flash->power_lock); + + if (flash->power_count == !power) { + ret = __lm3554_s_power(flash, !!power); + if (ret < 0) + goto done; + } + + flash->power_count += power ? 1 : -1; + WARN_ON(flash->power_count < 0); + +done: + mutex_unlock(&flash->power_lock); + return ret; +} + +static const struct v4l2_subdev_core_ops lm3554_core_ops = { + .s_power = lm3554_s_power, +}; + +static const struct v4l2_subdev_ops lm3554_ops = { + .core = &lm3554_core_ops, +}; + +static int lm3554_detect(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct i2c_adapter *adapter = client->adapter; + struct lm3554 *flash = to_lm3554(sd); + int ret; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_err(&client->dev, "lm3554_detect i2c error\n"); + return -ENODEV; + } + + /* Power up the flash driver and reset it */ + ret = lm3554_s_power(&flash->sd, 1); + if (ret < 0) { + dev_err(&client->dev, "Failed to power on lm3554 LED flash\n"); + } else { + dev_dbg(&client->dev, "Successfully detected lm3554 LED flash\n"); + lm3554_s_power(&flash->sd, 0); + } + + return ret; +} + +static int lm3554_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + return lm3554_s_power(sd, 1); +} + +static int lm3554_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + return lm3554_s_power(sd, 0); +} + +static const struct v4l2_subdev_internal_ops lm3554_internal_ops = { + .registered = lm3554_detect, + .open = lm3554_open, + .close = lm3554_close, +}; + +/* ----------------------------------------------------------------------------- + * I2C driver + */ +#ifdef CONFIG_PM + +static int lm3554_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(subdev); + int rval; + + if (flash->power_count == 0) + return 0; + + rval = __lm3554_s_power(flash, 0); + + dev_dbg(&client->dev, "Suspend %s\n", rval < 0 ? "failed" : "ok"); + + return rval; +} + +static int lm3554_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(subdev); + int rval; + + if (flash->power_count == 0) + return 0; + + rval = __lm3554_s_power(flash, 1); + + dev_dbg(&client->dev, "Resume %s\n", rval < 0 ? "fail" : "ok"); + + return rval; +} + +#else + +#define lm3554_suspend NULL +#define lm3554_resume NULL + +#endif /* CONFIG_PM */ + +static int lm3554_gpio_init(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + if (!pdata->gpio_reset) + return -EINVAL; + + ret = gpiod_direction_output(pdata->gpio_reset, 0); + if (ret < 0) + return ret; + + if (!pdata->gpio_strobe) + return -EINVAL; + + ret = gpiod_direction_output(pdata->gpio_strobe, 0); + if (ret < 0) + return ret; + + return 0; +} + +static void lm3554_gpio_uninit(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + ret = gpiod_direction_output(pdata->gpio_strobe, 0); + if (ret < 0) + dev_err(&client->dev, + "gpio request/direction_output fail for gpio_strobe"); + + ret = gpiod_direction_output(pdata->gpio_reset, 0); + if (ret < 0) + dev_err(&client->dev, + "gpio request/direction_output fail for gpio_reset"); +} + +static void *lm3554_platform_data_func(struct i2c_client *client) +{ + static struct lm3554_platform_data platform_data; + + platform_data.gpio_reset = gpiod_get_index(&client->dev, + NULL, 2, GPIOD_OUT_LOW); + if (IS_ERR(platform_data.gpio_reset)) + return ERR_CAST(platform_data.gpio_reset); + platform_data.gpio_strobe = gpiod_get_index(&client->dev, + NULL, 0, GPIOD_OUT_LOW); + if (IS_ERR(platform_data.gpio_strobe)) + return ERR_CAST(platform_data.gpio_strobe); + platform_data.gpio_torch = gpiod_get_index(&client->dev, + NULL, 1, GPIOD_OUT_LOW); + if (IS_ERR(platform_data.gpio_torch)) + return ERR_CAST(platform_data.gpio_torch); + + /* Set to TX2 mode, then ENVM/TX2 pin is a power amplifier sync input: + * ENVM/TX pin asserted, flash forced into torch; + * ENVM/TX pin desserted, flash set back; + */ + platform_data.envm_tx2 = 1; + platform_data.tx2_polarity = 0; + + /* set peak current limit to be 1000mA */ + platform_data.current_limit = 0; + + return &platform_data; +} + +static int lm3554_probe(struct i2c_client *client) +{ + int err = 0; + struct lm3554 *flash; + unsigned int i; + + flash = kzalloc(sizeof(*flash), GFP_KERNEL); + if (!flash) + return -ENOMEM; + + flash->pdata = lm3554_platform_data_func(client); + if (IS_ERR(flash->pdata)) { + err = PTR_ERR(flash->pdata); + goto free_flash; + } + + v4l2_i2c_subdev_init(&flash->sd, client, &lm3554_ops); + flash->sd.internal_ops = &lm3554_internal_ops; + flash->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + flash->mode = ATOMISP_FLASH_MODE_OFF; + flash->timeout = LM3554_MAX_TIMEOUT / LM3554_TIMEOUT_STEPSIZE - 1; + err = + v4l2_ctrl_handler_init(&flash->ctrl_handler, + ARRAY_SIZE(lm3554_controls)); + if (err) { + dev_err(&client->dev, "error initialize a ctrl_handler.\n"); + goto unregister_subdev; + } + + for (i = 0; i < ARRAY_SIZE(lm3554_controls); i++) + v4l2_ctrl_new_custom(&flash->ctrl_handler, &lm3554_controls[i], + NULL); + + if (flash->ctrl_handler.error) { + dev_err(&client->dev, "ctrl_handler error.\n"); + err = flash->ctrl_handler.error; + goto free_handler; + } + + flash->sd.ctrl_handler = &flash->ctrl_handler; + err = media_entity_pads_init(&flash->sd.entity, 0, NULL); + if (err) { + dev_err(&client->dev, "error initialize a media entity.\n"); + goto free_handler; + } + + flash->sd.entity.function = MEDIA_ENT_F_FLASH; + + mutex_init(&flash->power_lock); + + timer_setup(&flash->flash_off_delay, lm3554_flash_off_delay, 0); + + err = lm3554_gpio_init(client); + if (err) { + dev_err(&client->dev, "gpio request/direction_output fail.\n"); + goto cleanup_media; + } + + err = atomisp_register_i2c_module(&flash->sd, NULL, LED_FLASH); + if (err) { + dev_err(&client->dev, "fail to register atomisp i2c module.\n"); + goto uninit_gpio; + } + + return 0; + +uninit_gpio: + lm3554_gpio_uninit(client); +cleanup_media: + media_entity_cleanup(&flash->sd.entity); +free_handler: + v4l2_ctrl_handler_free(&flash->ctrl_handler); +unregister_subdev: + v4l2_device_unregister_subdev(&flash->sd); +free_flash: + kfree(flash); + + return err; +} + +static void lm3554_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + + media_entity_cleanup(&flash->sd.entity); + v4l2_ctrl_handler_free(&flash->ctrl_handler); + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + timer_shutdown_sync(&flash->flash_off_delay); + + lm3554_gpio_uninit(client); + + kfree(flash); +} + +static const struct dev_pm_ops lm3554_pm_ops = { + .suspend = lm3554_suspend, + .resume = lm3554_resume, +}; + +static const struct acpi_device_id lm3554_acpi_match[] = { + { "INTCF1C" }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, lm3554_acpi_match); + +static struct i2c_driver lm3554_driver = { + .driver = { + .name = "lm3554", + .pm = &lm3554_pm_ops, + .acpi_match_table = lm3554_acpi_match, + }, + .probe_new = lm3554_probe, + .remove = lm3554_remove, +}; +module_i2c_driver(lm3554_driver); + +MODULE_AUTHOR("Jing Tao "); +MODULE_DESCRIPTION("LED flash driver for LM3554"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/atomisp-mt9m114.c b/drivers/staging/media/atomisp/i2c/atomisp-mt9m114.c new file mode 100644 index 000000000..a0e8e94b2 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/atomisp-mt9m114.c @@ -0,0 +1,1815 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for mt9m114 Camera Sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../include/linux/atomisp_gmin_platform.h" +#include + +#include "mt9m114.h" + +#define to_mt9m114_sensor(sd) container_of(sd, struct mt9m114_device, sd) + +/* + * TODO: use debug parameter to actually define when debug messages should + * be printed. + */ +static int debug; +static int aaalock; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level (0-1)"); + +static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value); +static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value); +static int mt9m114_wait_state(struct i2c_client *client, int timeout); + +static int +mt9m114_read_reg(struct i2c_client *client, u16 data_length, u32 reg, u32 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[4]; + + if (!client->adapter) { + v4l2_err(client, "%s error, no client->adapter\n", __func__); + return -ENODEV; + } + + if (data_length != MISENSOR_8BIT && data_length != MISENSOR_16BIT + && data_length != MISENSOR_32BIT) { + v4l2_err(client, "%s error, invalid data length\n", __func__); + return -EINVAL; + } + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = MSG_LEN_OFFSET; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u16)(reg >> 8); + data[1] = (u16)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + + if (err >= 0) { + *val = 0; + /* high byte comes first */ + if (data_length == MISENSOR_8BIT) + *val = data[0]; + else if (data_length == MISENSOR_16BIT) + *val = data[1] + (data[0] << 8); + else + *val = data[3] + (data[2] << 8) + + (data[1] << 16) + (data[0] << 24); + + return 0; + } + + dev_err(&client->dev, "read from offset 0x%x error %d", reg, err); + return err; +} + +static int +mt9m114_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u32 val) +{ + int num_msg; + struct i2c_msg msg; + unsigned char data[6] = {0}; + __be16 *wreg; + int retry = 0; + + if (!client->adapter) { + v4l2_err(client, "%s error, no client->adapter\n", __func__); + return -ENODEV; + } + + if (data_length != MISENSOR_8BIT && data_length != MISENSOR_16BIT + && data_length != MISENSOR_32BIT) { + v4l2_err(client, "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + memset(&msg, 0, sizeof(msg)); + +again: + msg.addr = client->addr; + msg.flags = 0; + msg.len = 2 + data_length; + msg.buf = data; + + /* high byte goes out first */ + wreg = (void *)data; + *wreg = cpu_to_be16(reg); + + if (data_length == MISENSOR_8BIT) { + data[2] = (u8)(val); + } else if (data_length == MISENSOR_16BIT) { + u16 *wdata = (void *)&data[2]; + + *wdata = be16_to_cpu(*(__be16 *)&data[2]); + } else { + /* MISENSOR_32BIT */ + u32 *wdata = (void *)&data[2]; + + *wdata = be32_to_cpu(*(__be32 *)&data[2]); + } + + num_msg = i2c_transfer(client->adapter, &msg, 1); + + /* + * HACK: Need some delay here for Rev 2 sensors otherwise some + * registers do not seem to load correctly. + */ + mdelay(1); + + if (num_msg >= 0) + return 0; + + dev_err(&client->dev, "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, num_msg); + if (retry <= I2C_RETRY_COUNT) { + dev_dbg(&client->dev, "retrying... %d", retry); + retry++; + msleep(20); + goto again; + } + + return num_msg; +} + +/** + * misensor_rmw_reg - Read/Modify/Write a value to a register in the sensor + * device + * @client: i2c driver client structure + * @data_length: 8/16/32-bits length + * @reg: register address + * @mask: masked out bits + * @set: bits set + * + * Read/modify/write a value to a register in the sensor device. + * Returns zero if successful, or non-zero otherwise. + */ +static int +misensor_rmw_reg(struct i2c_client *client, u16 data_length, u16 reg, + u32 mask, u32 set) +{ + int err; + u32 val; + + /* Exit when no mask */ + if (mask == 0) + return 0; + + /* @mask must not exceed data length */ + switch (data_length) { + case MISENSOR_8BIT: + if (mask & ~0xff) + return -EINVAL; + break; + case MISENSOR_16BIT: + if (mask & ~0xffff) + return -EINVAL; + break; + case MISENSOR_32BIT: + break; + default: + /* Wrong @data_length */ + return -EINVAL; + } + + err = mt9m114_read_reg(client, data_length, reg, &val); + if (err) { + v4l2_err(client, "%s error exit, read failed\n", __func__); + return -EINVAL; + } + + val &= ~mask; + + /* + * Perform the OR function if the @set exists. + * Shift @set value to target bit location. @set should set only + * bits included in @mask. + * + * REVISIT: This function expects @set to be non-shifted. Its shift + * value is then defined to be equal to mask's LSB position. + * How about to inform values in their right offset position and avoid + * this unneeded shift operation? + */ + set <<= ffs(mask) - 1; + val |= set & mask; + + err = mt9m114_write_reg(client, data_length, reg, val); + if (err) { + v4l2_err(client, "%s error exit, write failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int __mt9m114_flush_reg_array(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + int retry = 0; + __be16 *data16 = (void *)&ctrl->buffer.addr; + + if (ctrl->index == 0) + return 0; + +again: + msg.addr = client->addr; + msg.flags = 0; + msg.len = 2 + ctrl->index; + *data16 = cpu_to_be16(ctrl->buffer.addr); + msg.buf = (u8 *)&ctrl->buffer; + + ret = i2c_transfer(client->adapter, &msg, num_msg); + if (ret != num_msg) { + if (++retry <= I2C_RETRY_COUNT) { + dev_dbg(&client->dev, "retrying... %d\n", retry); + msleep(20); + goto again; + } + dev_err(&client->dev, "%s: i2c transfer error\n", __func__); + return -EIO; + } + + ctrl->index = 0; + + /* + * REVISIT: Previously we had a delay after writing data to sensor. + * But it was removed as our tests have shown it is not necessary + * anymore. + */ + + return 0; +} + +static int __mt9m114_buf_reg_array(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl, + const struct misensor_reg *next) +{ + __be16 *data16; + __be32 *data32; + int err; + + /* Insufficient buffer? Let's flush and get more free space. */ + if (ctrl->index + next->length >= MT9M114_MAX_WRITE_BUF_SIZE) { + err = __mt9m114_flush_reg_array(client, ctrl); + if (err) + return err; + } + + switch (next->length) { + case MISENSOR_8BIT: + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case MISENSOR_16BIT: + data16 = (__be16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + case MISENSOR_32BIT: + data32 = (__be32 *)&ctrl->buffer.data[ctrl->index]; + *data32 = cpu_to_be32(next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += next->length; + + return 0; +} + +static int +__mt9m114_write_reg_is_consecutive(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl, + const struct misensor_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +/* + * mt9m114_write_reg_array - Initializes a list of mt9m114 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * @poll: completion polling requirement + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __mt9m114_flush_reg_array, __mt9m114_buf_reg_array() and + * __mt9m114_write_reg_is_consecutive() are internal functions to + * mt9m114_write_reg_array() and should be not used anywhere else. + * + */ +static int mt9m114_write_reg_array(struct i2c_client *client, + const struct misensor_reg *reglist, + int poll) +{ + const struct misensor_reg *next = reglist; + struct mt9m114_write_ctrl ctrl; + int err; + + if (poll == PRE_POLLING) { + err = mt9m114_wait_state(client, MT9M114_WAIT_STAT_TIMEOUT); + if (err) + return err; + } + + ctrl.index = 0; + for (; next->length != MISENSOR_TOK_TERM; next++) { + switch (next->length & MISENSOR_TOK_MASK) { + case MISENSOR_TOK_DELAY: + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + case MISENSOR_TOK_RMW: + err = __mt9m114_flush_reg_array(client, &ctrl); + err |= misensor_rmw_reg(client, + next->length & + ~MISENSOR_TOK_RMW, + next->reg, next->val, + next->val2); + if (err) { + dev_err(&client->dev, "%s read err. aborted\n", + __func__); + return -EINVAL; + } + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__mt9m114_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __mt9m114_buf_reg_array(client, &ctrl, next); + if (err) { + v4l2_err(client, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + + if (poll == POST_POLLING) + return mt9m114_wait_state(client, MT9M114_WAIT_STAT_TIMEOUT); + + return 0; +} + +static int mt9m114_wait_state(struct i2c_client *client, int timeout) +{ + int ret; + unsigned int val; + + while (timeout-- > 0) { + ret = mt9m114_read_reg(client, MISENSOR_16BIT, 0x0080, &val); + if (ret) + return ret; + if ((val & 0x2) == 0) + return 0; + msleep(20); + } + + return -EINVAL; +} + +static int mt9m114_set_suspend(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return mt9m114_write_reg_array(client, + mt9m114_standby_reg, POST_POLLING); +} + +static int mt9m114_init_common(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return mt9m114_write_reg_array(client, mt9m114_common, PRE_POLLING); +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + if (flag) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret) + ret = dev->platform_data->v2p8_ctrl(sd, 0); + } + } else { + ret = dev->platform_data->v2p8_ctrl(sd, 0); + ret = dev->platform_data->v1p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* + * Note: current modules wire only one GPIO signal (RESET#), + * but the schematic wires up two to the connector. BIOS + * versions have been unfortunately inconsistent with which + * ACPI index RESET# is on, so hit both + */ + + if (flag) { + ret = dev->platform_data->gpio0_ctrl(sd, 0); + ret = dev->platform_data->gpio1_ctrl(sd, 0); + msleep(60); + ret |= dev->platform_data->gpio0_ctrl(sd, 1); + ret |= dev->platform_data->gpio1_ctrl(sd, 1); + } else { + ret = dev->platform_data->gpio0_ctrl(sd, 0); + ret = dev->platform_data->gpio1_ctrl(sd, 0); + } + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) + dev_err(&client->dev, "gpio failed 1\n"); + /* + * according to DS, 44ms is needed between power up and first i2c + * commend + */ + msleep(50); + + return 0; + +fail_clk: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 1\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + /* according to DS, 20ms is needed after power down */ + msleep(20); + + return ret; +} + +static int mt9m114_s_power(struct v4l2_subdev *sd, int power) +{ + if (power == 0) + return power_down(sd); + + if (power_up(sd)) + return -EINVAL; + + return mt9m114_init_common(sd); +} + +static int mt9m114_res2size(struct v4l2_subdev *sd, int *h_size, int *v_size) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + unsigned short hsize; + unsigned short vsize; + + switch (dev->res) { + case MT9M114_RES_736P: + hsize = MT9M114_RES_736P_SIZE_H; + vsize = MT9M114_RES_736P_SIZE_V; + break; + case MT9M114_RES_864P: + hsize = MT9M114_RES_864P_SIZE_H; + vsize = MT9M114_RES_864P_SIZE_V; + break; + case MT9M114_RES_960P: + hsize = MT9M114_RES_960P_SIZE_H; + vsize = MT9M114_RES_960P_SIZE_V; + break; + default: + v4l2_err(sd, "%s: Resolution 0x%08x unknown\n", __func__, + dev->res); + return -EINVAL; + } + + if (h_size) + *h_size = hsize; + if (v_size) + *v_size = vsize; + + return 0; +} + +static int mt9m114_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct mt9m114_res_struct *res) +{ + struct atomisp_sensor_mode_data *buf; + u32 reg_val; + int ret; + + if (!info) + return -EINVAL; + + buf = &info->data; + + ret = mt9m114_read_reg(client, MISENSOR_32BIT, + REG_PIXEL_CLK, ®_val); + if (ret) + return ret; + buf->vt_pix_clk_freq_mhz = reg_val; + + /* get integration time */ + buf->coarse_integration_time_min = MT9M114_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + MT9M114_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = MT9M114_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + MT9M114_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = MT9M114_FINE_INTG_TIME_MIN; + + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_H_START, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_V_START, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_H_END, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_V_END, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_WIDTH, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_HEIGHT, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_TIMING_HTS, ®_val); + if (ret) + return ret; + buf->line_length_pck = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_TIMING_VTS, ®_val); + if (ret) + return ret; + buf->frame_length_lines = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static int mt9m114_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + int width, height; + int ret; + + if (format->pad) + return -EINVAL; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + ret = mt9m114_res2size(sd, &width, &height); + if (ret) + return ret; + fmt->width = width; + fmt->height = height; + + return 0; +} + +static int mt9m114_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct mt9m114_res_struct *res; + u32 width = fmt->width; + u32 height = fmt->height; + struct camera_mipi_info *mt9m114_info = NULL; + + int ret; + + if (format->pad) + return -EINVAL; + dev->streamon = 0; + dev->first_exp = MT9M114_DEFAULT_FIRST_EXP; + + mt9m114_info = v4l2_get_subdev_hostdata(sd); + if (!mt9m114_info) + return -EINVAL; + + res = v4l2_find_nearest_size(mt9m114_res, + ARRAY_SIZE(mt9m114_res), width, + height, fmt->width, fmt->height); + if (!res) + res = &mt9m114_res[N_RES - 1]; + + fmt->width = res->width; + fmt->height = res->height; + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + sd_state->pads->try_fmt = *fmt; + return 0; + } + + switch (res->res) { + case MT9M114_RES_736P: + ret = mt9m114_write_reg_array(c, mt9m114_736P_init, NO_POLLING); + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + case MT9M114_RES_864P: + ret = mt9m114_write_reg_array(c, mt9m114_864P_init, NO_POLLING); + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + case MT9M114_RES_960P: + ret = mt9m114_write_reg_array(c, mt9m114_976P_init, NO_POLLING); + /* set sensor read_mode to Normal */ + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + default: + v4l2_err(sd, "set resolution: %d failed!\n", res->res); + return -EINVAL; + } + + if (ret) + return -EINVAL; + + ret = mt9m114_write_reg_array(c, mt9m114_chgstat_reg, POST_POLLING); + if (ret < 0) + return ret; + + if (mt9m114_set_suspend(sd)) + return -EINVAL; + + if (dev->res != res->res) { + int index; + + /* Switch to different size */ + if (width <= 640) { + dev->nctx = 0x00; /* Set for context A */ + } else { + /* + * Context B is used for resolutions larger than 640x480 + * Using YUV for Context B. + */ + dev->nctx = 0x01; /* set for context B */ + } + + /* + * Marked current sensor res as being "used" + * + * REVISIT: We don't need to use an "used" field on each mode + * list entry to know which mode is selected. If this + * information is really necessary, how about to use a single + * variable on sensor dev struct? + */ + for (index = 0; index < N_RES; index++) { + if ((width == mt9m114_res[index].width) && + (height == mt9m114_res[index].height)) { + mt9m114_res[index].used = true; + continue; + } + mt9m114_res[index].used = false; + } + } + ret = mt9m114_get_intg_factor(c, mt9m114_info, + &mt9m114_res[res->res]); + if (ret) { + dev_err(&c->dev, "failed to get integration_factor\n"); + return -EINVAL; + } + /* + * mt9m114 - we don't poll for context switch + * because it does not happen with streaming disabled. + */ + dev->res = res->res; + + fmt->width = width; + fmt->height = height; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + return 0; +} + +/* TODO: Update to SOC functions, remove exposure and gain */ +static int mt9m114_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (MT9M114_FOCAL_LENGTH_NUM << 16) | MT9M114_FOCAL_LENGTH_DEM; + return 0; +} + +static int mt9m114_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /* const f number for mt9m114 */ + *val = (MT9M114_F_NUMBER_DEFAULT_NUM << 16) | MT9M114_F_NUMBER_DEM; + return 0; +} + +static int mt9m114_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (MT9M114_F_NUMBER_DEFAULT_NUM << 24) | + (MT9M114_F_NUMBER_DEM << 16) | + (MT9M114_F_NUMBER_DEFAULT_NUM << 8) | MT9M114_F_NUMBER_DEM; + return 0; +} + +/* Horizontal flip the image. */ +static int mt9m114_g_hflip(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int ret; + u32 data; + + ret = mt9m114_read_reg(c, MISENSOR_16BIT, + (u32)MISENSOR_READ_MODE, &data); + if (ret) + return ret; + *val = !!(data & MISENSOR_HFLIP_MASK); + + return 0; +} + +static int mt9m114_g_vflip(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int ret; + u32 data; + + ret = mt9m114_read_reg(c, MISENSOR_16BIT, + (u32)MISENSOR_READ_MODE, &data); + if (ret) + return ret; + *val = !!(data & MISENSOR_VFLIP_MASK); + + return 0; +} + +static long mt9m114_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + int ret = 0; + unsigned int coarse_integration = 0; + unsigned int f_lines = 0; + unsigned int frame_len_lines = 0; /* ExposureTime.FrameLengthLines; */ + unsigned int analog_gain, digital_gain; + u32 analog_gain_to_write = 0; + + dev_dbg(&client->dev, "%s(0x%X 0x%X 0x%X)\n", __func__, + exposure->integration_time[0], exposure->gain[0], + exposure->gain[1]); + + coarse_integration = exposure->integration_time[0]; + /* + * fine_integration = ExposureTime.FineIntegrationTime; + * frame_len_lines = ExposureTime.FrameLengthLines; + */ + f_lines = mt9m114_res[dev->res].lines_per_frame; + analog_gain = exposure->gain[0]; + digital_gain = exposure->gain[1]; + if (!dev->streamon) { + /*Save the first exposure values while stream is off*/ + dev->first_exp = coarse_integration; + dev->first_gain = analog_gain; + dev->first_diggain = digital_gain; + } + /* digital_gain = 0x400 * (((u16) digital_gain) >> 8) + */ + /* ((unsigned int)(0x400 * (((u16) digital_gain) & 0xFF)) >>8); */ + + /* set frame length */ + if (f_lines < coarse_integration + 6) + f_lines = coarse_integration + 6; + if (f_lines < frame_len_lines) + f_lines = frame_len_lines; + ret = mt9m114_write_reg(client, MISENSOR_16BIT, 0x300A, f_lines); + if (ret) { + v4l2_err(client, "%s: fail to set f_lines\n", __func__); + return -EINVAL; + } + + /* set coarse integration */ + /* + * 3A provide real exposure time. + * should not translate to any value here. + */ + ret = mt9m114_write_reg(client, MISENSOR_16BIT, + REG_EXPO_COARSE, (u16)(coarse_integration)); + if (ret) { + v4l2_err(client, "%s: fail to set exposure time\n", __func__); + return -EINVAL; + } + + /* + * set analog/digital gain + switch(analog_gain) + { + case 0: + analog_gain_to_write = 0x0; + break; + case 1: + analog_gain_to_write = 0x20; + break; + case 2: + analog_gain_to_write = 0x60; + break; + case 4: + analog_gain_to_write = 0xA0; + break; + case 8: + analog_gain_to_write = 0xE0; + break; + default: + analog_gain_to_write = 0x20; + break; + } + */ + if (digital_gain >= 16 || digital_gain <= 1) + digital_gain = 1; + /* + * analog_gain_to_write = (u16)((digital_gain << 12) + * | analog_gain_to_write); + */ + analog_gain_to_write = (u16)((digital_gain << 12) | (u16)analog_gain); + ret = mt9m114_write_reg(client, MISENSOR_16BIT, + REG_GAIN, analog_gain_to_write); + if (ret) { + v4l2_err(client, "%s: fail to set analog_gain_to_write\n", + __func__); + return -EINVAL; + } + + return ret; +} + +static long mt9m114_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return mt9m114_s_exposure(sd, arg); + default: + return -EINVAL; + } + + return 0; +} + +/* + * This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int mt9m114_g_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u32 coarse; + int ret; + + /* the fine integration time is currently not calculated */ + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_EXPO_COARSE, &coarse); + if (ret) + return ret; + + *value = coarse; + return 0; +} + +/* + * This function will return the sensor supported max exposure zone number. + * the sensor which supports max exposure zone number is 1. + */ +static int mt9m114_g_exposure_zone_num(struct v4l2_subdev *sd, s32 *val) +{ + *val = 1; + + return 0; +} + +/* + * set exposure metering, average/center_weighted/spot/matrix. + */ +static int mt9m114_s_exposure_metering(struct v4l2_subdev *sd, s32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + switch (val) { + case V4L2_EXPOSURE_METERING_SPOT: + ret = mt9m114_write_reg_array(client, mt9m114_exp_average, + NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_average reg err.\n"); + return ret; + } + break; + case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED: + default: + ret = mt9m114_write_reg_array(client, mt9m114_exp_center, + NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_default reg err"); + return ret; + } + } + + return 0; +} + +/* + * This function is for touch exposure feature. + */ +static int mt9m114_s_exposure_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct misensor_reg exp_reg; + int width, height; + int grid_width, grid_height; + int grid_left, grid_top, grid_right, grid_bottom; + int win_left, win_top, win_right, win_bottom; + int i, j; + int ret; + + if (sel->which != V4L2_SUBDEV_FORMAT_TRY && + sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) + return -EINVAL; + + grid_left = sel->r.left; + grid_top = sel->r.top; + grid_right = sel->r.left + sel->r.width - 1; + grid_bottom = sel->r.top + sel->r.height - 1; + + ret = mt9m114_res2size(sd, &width, &height); + if (ret) + return ret; + + grid_width = width / 5; + grid_height = height / 5; + + if (grid_width && grid_height) { + win_left = grid_left / grid_width; + win_top = grid_top / grid_height; + win_right = grid_right / grid_width; + win_bottom = grid_bottom / grid_height; + } else { + dev_err(&client->dev, "Incorrect exp grid.\n"); + return -EINVAL; + } + + win_left = clamp_t(int, win_left, 0, 4); + win_top = clamp_t(int, win_top, 0, 4); + win_right = clamp_t(int, win_right, 0, 4); + win_bottom = clamp_t(int, win_bottom, 0, 4); + + ret = mt9m114_write_reg_array(client, mt9m114_exp_average, NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_average reg err.\n"); + return ret; + } + + for (i = win_top; i <= win_bottom; i++) { + for (j = win_left; j <= win_right; j++) { + exp_reg = mt9m114_exp_win[i][j]; + + ret = mt9m114_write_reg(client, exp_reg.length, + exp_reg.reg, exp_reg.val); + if (ret) { + dev_err(&client->dev, "write exp_reg err.\n"); + return ret; + } + } + } + + return 0; +} + +static int mt9m114_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + *val = mt9m114_res[dev->res].bin_factor_x; + + return 0; +} + +static int mt9m114_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + *val = mt9m114_res[dev->res].bin_factor_y; + + return 0; +} + +static int mt9m114_s_ev(struct v4l2_subdev *sd, s32 val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + s32 luma = 0x37; + int err; + + /* + * EV value only support -2 to 2 + * 0: 0x37, 1:0x47, 2:0x57, -1:0x27, -2:0x17 + */ + if (val < -2 || val > 2) + return -EINVAL; + luma += 0x10 * val; + dev_dbg(&c->dev, "%s val:%d luma:0x%x\n", __func__, val, luma); + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC87A); + if (err) { + dev_err(&c->dev, "%s logic addr access error\n", __func__); + return err; + } + err = mt9m114_write_reg(c, MISENSOR_8BIT, 0xC87A, (u32)luma); + if (err) { + dev_err(&c->dev, "%s write target_average_luma failed\n", + __func__); + return err; + } + udelay(10); + + return 0; +} + +static int mt9m114_g_ev(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int err; + u32 luma; + + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC87A); + if (err) { + dev_err(&c->dev, "%s logic addr access error\n", __func__); + return err; + } + err = mt9m114_read_reg(c, MISENSOR_8BIT, 0xC87A, &luma); + if (err) { + dev_err(&c->dev, "%s read target_average_luma failed\n", + __func__); + return err; + } + luma -= 0x17; + luma /= 0x10; + *val = (s32)luma - 2; + dev_dbg(&c->dev, "%s val:%d\n", __func__, *val); + + return 0; +} + +/* + * Fake interface + * mt9m114 now can not support 3a_lock + */ +static int mt9m114_s_3a_lock(struct v4l2_subdev *sd, s32 val) +{ + aaalock = val; + return 0; +} + +static int mt9m114_g_3a_lock(struct v4l2_subdev *sd, s32 *val) +{ + if (aaalock) + return V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE + | V4L2_LOCK_FOCUS; + return 0; +} + +static int mt9m114_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mt9m114_device *dev = + container_of(ctrl->handler, struct mt9m114_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = mt9m114_t_vflip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = mt9m114_t_hflip(&dev->sd, ctrl->val); + break; + case V4L2_CID_EXPOSURE_METERING: + ret = mt9m114_s_exposure_metering(&dev->sd, ctrl->val); + break; + case V4L2_CID_EXPOSURE: + ret = mt9m114_s_ev(&dev->sd, ctrl->val); + break; + case V4L2_CID_3A_LOCK: + ret = mt9m114_s_3a_lock(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int mt9m114_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mt9m114_device *dev = + container_of(ctrl->handler, struct mt9m114_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + ret = mt9m114_g_vflip(&dev->sd, &ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = mt9m114_g_hflip(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = mt9m114_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = mt9m114_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = mt9m114_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = mt9m114_g_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_EXPOSURE_ZONE_NUM: + ret = mt9m114_g_exposure_zone_num(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = mt9m114_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = mt9m114_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + case V4L2_CID_EXPOSURE: + ret = mt9m114_g_ev(&dev->sd, &ctrl->val); + break; + case V4L2_CID_3A_LOCK: + ret = mt9m114_g_3a_lock(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = mt9m114_s_ctrl, + .g_volatile_ctrl = mt9m114_g_volatile_ctrl +}; + +static struct v4l2_ctrl_config mt9m114_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .name = "Image v-Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .name = "Image h-Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .name = "focal length", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_FOCAL_LENGTH_DEFAULT, + .max = MT9M114_FOCAL_LENGTH_DEFAULT, + .step = 1, + .def = MT9M114_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .name = "f-number", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_F_NUMBER_DEFAULT, + .max = MT9M114_F_NUMBER_DEFAULT, + .step = 1, + .def = MT9M114_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .name = "f-number range", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_F_NUMBER_RANGE, + .max = MT9M114_F_NUMBER_RANGE, + .step = 1, + .def = MT9M114_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .name = "exposure", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ZONE_NUM, + .name = "one-time exposure zone number", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_METERING, + .name = "metering", + .type = V4L2_CTRL_TYPE_MENU, + .min = 0, + .max = 3, + .step = 0, + .def = 1, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .name = "horizontal binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = MT9M114_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .name = "vertical binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = MT9M114_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE, + .name = "exposure biasx", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = -2, + .max = 2, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_3A_LOCK, + .name = "3a lock", + .type = V4L2_CTRL_TYPE_BITMASK, + .min = 0, + .max = V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE | V4L2_LOCK_FOCUS, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int mt9m114_detect(struct mt9m114_device *dev, struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u32 model; + int ret; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) { + dev_err(&client->dev, "%s: i2c error", __func__); + return -ENODEV; + } + ret = mt9m114_read_reg(client, MISENSOR_16BIT, MT9M114_PID, &model); + if (ret) + return ret; + dev->real_model_id = model; + + if (model != MT9M114_MOD_ID) { + dev_err(&client->dev, "%s: failed: client->addr = %x\n", + __func__, client->addr); + return -ENODEV; + } + + return 0; +} + +static int +mt9m114_s_config(struct v4l2_subdev *sd, int irq, void *platform_data) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + ret = power_up(sd); + if (ret) { + v4l2_err(client, "mt9m114 power-up err"); + return ret; + } + + /* config & detect sensor */ + ret = mt9m114_detect(dev, client); + if (ret) { + v4l2_err(client, "mt9m114_detect err s_config.\n"); + goto fail_detect; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + ret = mt9m114_set_suspend(sd); + if (ret) { + v4l2_err(client, "mt9m114 suspend err"); + return ret; + } + + ret = power_down(sd); + if (ret) { + v4l2_err(client, "mt9m114 power down err"); + return ret; + } + + return ret; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_detect: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); + return ret; +} + +/* Horizontal flip the image. */ +static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + int err; + /* set for direct mode */ + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC850); + if (value) { + /* enable H flip ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x01, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x01, 0x01); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x01); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_HFLIP_MASK, MISENSOR_FLIP_EN); + + dev->bpat = MT9M114_BPAT_GRGRBGBG; + } else { + /* disable H flip ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x01, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x01, 0x00); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x00); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_HFLIP_MASK, MISENSOR_FLIP_DIS); + + dev->bpat = MT9M114_BPAT_BGBGGRGR; + } + + err += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06); + udelay(10); + + return !!err; +} + +/* Vertically flip the image */ +static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int err; + /* set for direct mode */ + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC850); + if (value >= 1) { + /* enable H flip - ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x02, 0x01); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x01); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_VFLIP_MASK, MISENSOR_FLIP_EN); + } else { + /* disable H flip - ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x02, 0x00); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x00); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_VFLIP_MASK, MISENSOR_FLIP_DIS); + } + + err += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06); + udelay(10); + + return !!err; +} + +static int mt9m114_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = mt9m114_res[dev->res].fps; + + return 0; +} + +static int mt9m114_s_stream(struct v4l2_subdev *sd, int enable) +{ + int ret; + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct atomisp_exposure exposure; + + if (enable) { + ret = mt9m114_write_reg_array(c, mt9m114_chgstat_reg, + POST_POLLING); + if (ret < 0) + return ret; + + if (dev->first_exp > MT9M114_MAX_FIRST_EXP) { + exposure.integration_time[0] = dev->first_exp; + exposure.gain[0] = dev->first_gain; + exposure.gain[1] = dev->first_diggain; + mt9m114_s_exposure(sd, &exposure); + } + dev->streamon = 1; + + } else { + dev->streamon = 0; + ret = mt9m114_set_suspend(sd); + } + + return ret; +} + +static int mt9m114_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index) + return -EINVAL; + code->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int mt9m114_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + unsigned int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = mt9m114_res[index].width; + fse->min_height = mt9m114_res[index].height; + fse->max_width = mt9m114_res[index].width; + fse->max_height = mt9m114_res[index].height; + + return 0; +} + +static int mt9m114_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + int index; + struct mt9m114_device *snr = to_mt9m114_sensor(sd); + + if (!frames) + return -EINVAL; + + for (index = 0; index < N_RES; index++) { + if (mt9m114_res[index].res == snr->res) + break; + } + + if (index >= N_RES) + return -EINVAL; + + *frames = mt9m114_res[index].skip_frames; + + return 0; +} + +static const struct v4l2_subdev_video_ops mt9m114_video_ops = { + .s_stream = mt9m114_s_stream, + .g_frame_interval = mt9m114_g_frame_interval, +}; + +static const struct v4l2_subdev_sensor_ops mt9m114_sensor_ops = { + .g_skip_frames = mt9m114_g_skip_frames, +}; + +static const struct v4l2_subdev_core_ops mt9m114_core_ops = { + .s_power = mt9m114_s_power, + .ioctl = mt9m114_ioctl, +}; + +/* REVISIT: Do we need pad operations? */ +static const struct v4l2_subdev_pad_ops mt9m114_pad_ops = { + .enum_mbus_code = mt9m114_enum_mbus_code, + .enum_frame_size = mt9m114_enum_frame_size, + .get_fmt = mt9m114_get_fmt, + .set_fmt = mt9m114_set_fmt, + .set_selection = mt9m114_s_exposure_selection, +}; + +static const struct v4l2_subdev_ops mt9m114_ops = { + .core = &mt9m114_core_ops, + .video = &mt9m114_video_ops, + .pad = &mt9m114_pad_ops, + .sensor = &mt9m114_sensor_ops, +}; + +static void mt9m114_remove(struct i2c_client *client) +{ + struct mt9m114_device *dev; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + + dev = container_of(sd, struct mt9m114_device, sd); + dev->platform_data->csi_cfg(sd, 0); + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); +} + +static int mt9m114_probe(struct i2c_client *client) +{ + struct mt9m114_device *dev; + int ret = 0; + unsigned int i; + void *pdata; + + /* Setup sensor configuration structure */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + v4l2_i2c_subdev_init(&dev->sd, client, &mt9m114_ops); + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + if (pdata) + ret = mt9m114_s_config(&dev->sd, client->irq, pdata); + if (!pdata || ret) { + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; + } + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) { + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + /* Coverity CID 298095 - return on error */ + return ret; + } + + /* TODO add format code here */ + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(mt9m114_controls)); + if (ret) { + mt9m114_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(mt9m114_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &mt9m114_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + mt9m114_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + /* REVISIT: Do we need media controller? */ + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + mt9m114_remove(client); + return ret; + } + return 0; +} + +static const struct acpi_device_id mt9m114_acpi_match[] = { + { "INT33F0" }, + { "CRMT1040" }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, mt9m114_acpi_match); + +static struct i2c_driver mt9m114_driver = { + .driver = { + .name = "mt9m114", + .acpi_match_table = mt9m114_acpi_match, + }, + .probe_new = mt9m114_probe, + .remove = mt9m114_remove, +}; +module_i2c_driver(mt9m114_driver); + +MODULE_AUTHOR("Shuguang Gong "); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/atomisp-ov2680.c b/drivers/staging/media/atomisp/i2c/atomisp-ov2680.c new file mode 100644 index 000000000..fa1de45b7 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/atomisp-ov2680.c @@ -0,0 +1,1242 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for OmniVision OV2680 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../include/linux/atomisp_gmin_platform.h" + +#include "ov2680.h" + +static int h_flag; +static int v_flag; +static enum atomisp_bayer_order ov2680_bayer_order_mapping[] = { + atomisp_bayer_order_bggr, + atomisp_bayer_order_grbg, + atomisp_bayer_order_gbrg, + atomisp_bayer_order_rggb, +}; + +/* i2c read/write stuff */ +static int ov2680_read_reg(struct i2c_client *client, + int len, u16 reg, u32 *val) +{ + struct i2c_msg msgs[2]; + u8 addr_buf[2] = { reg >> 8, reg & 0xff }; + u8 data_buf[4] = { 0, }; + int ret; + + if (len > 4) + return -EINVAL; + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = ARRAY_SIZE(addr_buf); + msgs[0].buf = addr_buf; + + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_buf[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&client->dev, "read error: reg=0x%4x: %d\n", reg, ret); + return -EIO; + } + + *val = get_unaligned_be32(data_buf); + + return 0; +} + +static int ov2680_write_reg(struct i2c_client *client, unsigned int len, + u16 reg, u16 val) +{ + u8 buf[6]; + int ret; + + if (len == 2) + put_unaligned_be16(val, buf + 2); + else if (len == 1) + buf[2] = val; + else + return -EINVAL; + + put_unaligned_be16(reg, buf); + + ret = i2c_master_send(client, buf, len + 2); + if (ret != len + 2) { + dev_err(&client->dev, "write error %d reg 0x%04x, val 0x%02x: buf sent: %*ph\n", + ret, reg, val, len + 2, &buf); + return -EIO; + } + + return 0; +} + +static int ov2680_write_reg_array(struct i2c_client *client, + const struct ov2680_reg *reglist) +{ + const struct ov2680_reg *next = reglist; + int ret; + + for (; next->reg != 0; next++) { + ret = ov2680_write_reg(client, 1, next->reg, next->val); + if (ret) + return ret; + } + + return 0; +} + +static int ov2680_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV2680_FOCAL_LENGTH_NUM << 16) | OV2680_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov2680_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /* const f number for ov2680 */ + + *val = (OV2680_F_NUMBER_DEFAULT_NUM << 16) | OV2680_F_NUMBER_DEM; + return 0; +} + +static int ov2680_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV2680_F_NUMBER_DEFAULT_NUM << 24) | + (OV2680_F_NUMBER_DEM << 16) | + (OV2680_F_NUMBER_DEFAULT_NUM << 8) | OV2680_F_NUMBER_DEM; + return 0; +} + +static int ov2680_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + dev_dbg(&client->dev, "++++ov2680_g_bin_factor_x\n"); + *val = dev->res->bin_factor_x; + + return 0; +} + +static int ov2680_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + *val = dev->res->bin_factor_y; + dev_dbg(&client->dev, "++++ov2680_g_bin_factor_y\n"); + return 0; +} + +static int ov2680_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov2680_resolution *res) +{ + struct atomisp_sensor_mode_data *buf = &info->data; + unsigned int pix_clk_freq_hz; + u32 reg_val; + int ret; + + dev_dbg(&client->dev, "++++ov2680_get_intg_factor\n"); + if (!info) + return -EINVAL; + + /* pixel clock */ + pix_clk_freq_hz = res->pix_clk_freq * 1000000; + + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV2680_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV2680_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV2680_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV2680_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV2680_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov2680_read_reg(client, 2, + OV2680_HORIZONTAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov2680_read_reg(client, 2, + OV2680_VERTICAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov2680_read_reg(client, 2, + OV2680_HORIZONTAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov2680_read_reg(client, 2, + OV2680_VERTICAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov2680_read_reg(client, 2, + OV2680_HORIZONTAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov2680_read_reg(client, 2, + OV2680_VERTICAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + (res->bin_factor_x * 2) : 1; + buf->binning_factor_y = res->bin_factor_y ? + (res->bin_factor_y * 2) : 1; + return 0; +} + +static long __ov2680_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2680_device *dev = to_ov2680_sensor(sd); + u16 vts; + int ret, exp_val; + + dev_dbg(&client->dev, + "+++++++__ov2680_set_exposure coarse_itg %d, gain %d, digitgain %d++\n", + coarse_itg, gain, digitgain); + + vts = dev->res->lines_per_frame; + + /* group hold */ + ret = ov2680_write_reg(client, 1, + OV2680_GROUP_ACCESS, 0x00); + if (ret) { + dev_err(&client->dev, "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_GROUP_ACCESS); + return ret; + } + + /* Increase the VTS to match exposure + MARGIN */ + if (coarse_itg > vts - OV2680_INTEGRATION_TIME_MARGIN) + vts = (u16)coarse_itg + OV2680_INTEGRATION_TIME_MARGIN; + + ret = ov2680_write_reg(client, 2, OV2680_TIMING_VTS_H, vts); + if (ret) { + dev_err(&client->dev, "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_TIMING_VTS_H); + return ret; + } + + /* set exposure */ + + /* Lower four bit should be 0*/ + exp_val = coarse_itg << 4; + ret = ov2680_write_reg(client, 1, + OV2680_EXPOSURE_L, exp_val & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_EXPOSURE_L); + return ret; + } + + ret = ov2680_write_reg(client, 1, + OV2680_EXPOSURE_M, (exp_val >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_EXPOSURE_M); + return ret; + } + + ret = ov2680_write_reg(client, 1, + OV2680_EXPOSURE_H, (exp_val >> 16) & 0x0F); + if (ret) { + dev_err(&client->dev, "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_EXPOSURE_H); + return ret; + } + + /* Analog gain */ + ret = ov2680_write_reg(client, 2, OV2680_AGC_H, gain); + if (ret) { + dev_err(&client->dev, "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_AGC_H); + return ret; + } + /* Digital gain */ + if (digitgain) { + ret = ov2680_write_reg(client, 2, + OV2680_MWB_RED_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, + "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + + ret = ov2680_write_reg(client, 2, + OV2680_MWB_GREEN_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, + "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + + ret = ov2680_write_reg(client, 2, + OV2680_MWB_BLUE_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, + "%s: write 0x%02x: error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + } + + /* End group */ + ret = ov2680_write_reg(client, 1, + OV2680_GROUP_ACCESS, 0x10); + if (ret) + return ret; + + /* Delay launch group */ + ret = ov2680_write_reg(client, 1, + OV2680_GROUP_ACCESS, 0xa0); + if (ret) + return ret; + return ret; +} + +static int ov2680_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + int ret = 0; + + mutex_lock(&dev->input_lock); + + dev->exposure = exposure; + dev->gain = gain; + dev->digitgain = digitgain; + + if (dev->power_on) + ret = __ov2680_set_exposure(sd, exposure, gain, digitgain); + + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov2680_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + u16 coarse_itg = exposure->integration_time[0]; + u16 analog_gain = exposure->gain[0]; + u16 digital_gain = exposure->gain[1]; + + /* we should not accept the invalid value below */ + if (analog_gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return ov2680_set_exposure(sd, coarse_itg, analog_gain, digital_gain); +} + +static long ov2680_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov2680_s_exposure(sd, arg); + + default: + return -EINVAL; + } + return 0; +} + +/* + * This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int ov2680_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u32 reg_val; + int ret; + + /* get exposure */ + ret = ov2680_read_reg(client, 3, OV2680_EXPOSURE_H, ®_val); + if (ret) + return ret; + + /* Lower four bits are not part of the exposure val (always 0) */ + *value = reg_val >> 4; + return 0; +} + +static int ov2680_v_flip(struct v4l2_subdev *sd, s32 value) +{ + struct camera_mipi_info *ov2680_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u32 val; + u8 index; + + dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value); + ret = ov2680_read_reg(client, 1, OV2680_FLIP_REG, &val); + if (ret) + return ret; + if (value) + val |= OV2680_FLIP_MIRROR_BIT_ENABLE; + else + val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE; + + ret = ov2680_write_reg(client, 1, + OV2680_FLIP_REG, val); + if (ret) + return ret; + index = (v_flag > 0 ? OV2680_FLIP_BIT : 0) | (h_flag > 0 ? OV2680_MIRROR_BIT : + 0); + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (ov2680_info) { + ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index]; + } + return ret; +} + +static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value) +{ + struct camera_mipi_info *ov2680_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u32 val; + u8 index; + + dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value); + + ret = ov2680_read_reg(client, 1, OV2680_MIRROR_REG, &val); + if (ret) + return ret; + if (value) + val |= OV2680_FLIP_MIRROR_BIT_ENABLE; + else + val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE; + + ret = ov2680_write_reg(client, 1, + OV2680_MIRROR_REG, val); + if (ret) + return ret; + index = (v_flag > 0 ? OV2680_FLIP_BIT : 0) | (h_flag > 0 ? OV2680_MIRROR_BIT : + 0); + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (ov2680_info) { + ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index]; + } + return ret; +} + +static int ov2680_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2680_device *dev = + container_of(ctrl->handler, struct ov2680_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = ov2680_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = ov2680_h_flip(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int ov2680_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2680_device *dev = + container_of(ctrl->handler, struct ov2680_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov2680_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov2680_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov2680_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov2680_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = ov2680_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = ov2680_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ov2680_s_ctrl, + .g_volatile_ctrl = ov2680_g_volatile_ctrl +}; + +static const struct v4l2_ctrl_config ov2680_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV2680_FOCAL_LENGTH_DEFAULT, + .max = OV2680_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV2680_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV2680_F_NUMBER_DEFAULT, + .max = OV2680_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV2680_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV2680_F_NUMBER_RANGE, + .max = OV2680_F_NUMBER_RANGE, + .step = 0x01, + .def = OV2680_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = OV2680_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = OV2680_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, +}; + +static int ov2680_init_registers(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = ov2680_write_reg(client, 1, OV2680_SW_RESET, 0x01); + ret |= ov2680_write_reg_array(client, ov2680_global_setting); + + return ret; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = 0; + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + dev_dbg(&client->dev, "%s: %s", __func__, flag ? "on" : "off"); + + if (flag) { + ret |= dev->platform_data->v1p8_ctrl(sd, 1); + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + usleep_range(10000, 15000); + } + + if (!flag || ret) { + ret |= dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct ov2680_device *dev = to_ov2680_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* + * The OV2680 documents only one GPIO input (#XSHUTDN), but + * existing integrations often wire two (reset/power_down) + * because that is the way other sensors work. There is no + * way to tell how it is wired internally, so existing + * firmwares expose both and we drive them symmetrically. + */ + if (flag) { + ret = dev->platform_data->gpio0_ctrl(sd, 1); + usleep_range(10000, 15000); + /* Ignore return from second gpio, it may not be there */ + dev->platform_data->gpio1_ctrl(sd, 1); + usleep_range(10000, 15000); + } else { + dev->platform_data->gpio1_ctrl(sd, 0); + ret = dev->platform_data->gpio0_ctrl(sd, 0); + } + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + if (dev->power_on) + return 0; /* Already on */ + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* according to DS, 20ms is needed between PWDN and i2c access */ + msleep(20); + + ret = ov2680_init_registers(sd); + if (ret) + goto fail_init_registers; + + ret = __ov2680_set_exposure(sd, dev->exposure, dev->gain, dev->digitgain); + if (ret) + goto fail_init_registers; + + dev->power_on = true; + return 0; + +fail_init_registers: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + h_flag = 0; + v_flag = 0; + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + if (!dev->power_on) + return 0; /* Already off */ + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) { + dev_err(&client->dev, "vprog failed.\n"); + return ret; + } + + dev->power_on = false; + return 0; +} + +static int ov2680_s_power(struct v4l2_subdev *sd, int on) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + + if (on == 0) { + ret = power_down(sd); + } else { + ret = power_up(sd); + } + + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ov2680_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *ov2680_info = NULL; + struct ov2680_resolution *res; + int vts, ret = 0; + + dev_dbg(&client->dev, "%s: %s: pad: %d, fmt: %p\n", + __func__, + (format->which == V4L2_SUBDEV_FORMAT_TRY) ? "try" : "set", + format->pad, fmt); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (!ov2680_info) + return -EINVAL; + + res = v4l2_find_nearest_size(ov2680_res_preview, + ARRAY_SIZE(ov2680_res_preview), width, + height, fmt->width, fmt->height); + if (!res) + res = &ov2680_res_preview[N_RES_PREVIEW - 1]; + + fmt->width = res->width; + fmt->height = res->height; + + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + sd_state->pads->try_fmt = *fmt; + return 0; + } + + dev_dbg(&client->dev, "%s: %dx%d\n", + __func__, fmt->width, fmt->height); + + mutex_lock(&dev->input_lock); + + /* s_power has not been called yet for std v4l2 clients (camorama) */ + power_up(sd); + ret = ov2680_write_reg_array(client, dev->res->regs); + if (ret) { + dev_err(&client->dev, + "ov2680 write resolution register err: %d\n", ret); + goto err; + } + + vts = dev->res->lines_per_frame; + + /* If necessary increase the VTS to match exposure + MARGIN */ + if (dev->exposure > vts - OV2680_INTEGRATION_TIME_MARGIN) + vts = dev->exposure + OV2680_INTEGRATION_TIME_MARGIN; + + ret = ov2680_write_reg(client, 2, OV2680_TIMING_VTS_H, vts); + if (ret) { + dev_err(&client->dev, "ov2680 write vts err: %d\n", ret); + goto err; + } + + ret = ov2680_get_intg_factor(client, ov2680_info, res); + if (ret) { + dev_err(&client->dev, "failed to get integration factor\n"); + goto err; + } + + /* + * recall flip functions to avoid flip registers + * were overridden by default setting + */ + if (h_flag) + ov2680_h_flip(sd, h_flag); + if (v_flag) + ov2680_v_flip(sd, v_flag); + + dev->res = res; +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2680_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2680_device *dev = to_ov2680_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = dev->res->width; + fmt->height = dev->res->height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov2680_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u32 high, low; + int ret; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = ov2680_read_reg(client, 1, + OV2680_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = ov2680_read_reg(client, 1, + OV2680_SC_CMMN_CHIP_ID_L, &low); + id = ((((u16)high) << 8) | (u16)low); + + if (id != OV2680_ID) { + dev_err(&client->dev, "sensor ID error 0x%x\n", id); + return -ENODEV; + } + + ret = ov2680_read_reg(client, 1, + OV2680_SC_CMMN_SUB_ID, &high); + revision = (u8)high & 0x0f; + + dev_info(&client->dev, "sensor_revision id = 0x%x, rev= %d\n", + id, revision); + + return 0; +} + +static int ov2680_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + if (enable) + dev_dbg(&client->dev, "ov2680_s_stream one\n"); + else + dev_dbg(&client->dev, "ov2680_s_stream off\n"); + + ret = ov2680_write_reg(client, 1, OV2680_SW_STREAM, + enable ? OV2680_START_STREAMING : + OV2680_STOP_STREAMING); + + //otp valid at stream on state + //if(!dev->otp_data) + // dev->otp_data = ov2680_otp_read(sd); + + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ov2680_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov2680 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov2680_detect(client); + if (ret) { + dev_err(&client->dev, "ov2680_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2680 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2680_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = dev->res->fps; + + return 0; +} + +static int ov2680_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov2680_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES_PREVIEW) + return -EINVAL; + + fse->min_width = ov2680_res_preview[index].width; + fse->min_height = ov2680_res_preview[index].height; + fse->max_width = ov2680_res_preview[index].width; + fse->max_height = ov2680_res_preview[index].height; + + return 0; +} + +static int ov2680_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_interval_enum *fie) +{ + struct v4l2_fract fract; + + if (fie->index >= N_RES_PREVIEW || + fie->width > ov2680_res_preview[0].width || + fie->height > ov2680_res_preview[0].height || + fie->which > V4L2_SUBDEV_FORMAT_ACTIVE) + return -EINVAL; + + fract.denominator = ov2680_res_preview[fie->index].fps; + fract.numerator = 1; + + fie->interval = fract; + + return 0; +} + +static int ov2680_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->res->skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_video_ops ov2680_video_ops = { + .s_stream = ov2680_s_stream, + .g_frame_interval = ov2680_g_frame_interval, +}; + +static const struct v4l2_subdev_sensor_ops ov2680_sensor_ops = { + .g_skip_frames = ov2680_g_skip_frames, +}; + +static const struct v4l2_subdev_core_ops ov2680_core_ops = { + .s_power = ov2680_s_power, + .ioctl = ov2680_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov2680_pad_ops = { + .enum_mbus_code = ov2680_enum_mbus_code, + .enum_frame_size = ov2680_enum_frame_size, + .enum_frame_interval = ov2680_enum_frame_interval, + .get_fmt = ov2680_get_fmt, + .set_fmt = ov2680_set_fmt, +}; + +static const struct v4l2_subdev_ops ov2680_ops = { + .core = &ov2680_core_ops, + .video = &ov2680_video_ops, + .pad = &ov2680_pad_ops, + .sensor = &ov2680_sensor_ops, +}; + +static void ov2680_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2680_device *dev = to_ov2680_sensor(sd); + + dev_dbg(&client->dev, "ov2680_remove...\n"); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); +} + +static int ov2680_probe(struct i2c_client *client) +{ + struct ov2680_device *dev; + int ret; + void *pdata; + unsigned int i; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + mutex_init(&dev->input_lock); + + dev->res = &ov2680_res_preview[0]; + dev->exposure = dev->res->lines_per_frame - OV2680_INTEGRATION_TIME_MARGIN; + dev->gain = 250; /* 0-2047 */ + v4l2_i2c_subdev_init(&dev->sd, client, &ov2680_ops); + + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_bggr); + if (!pdata) { + ret = -EINVAL; + goto out_free; + } + + ret = ov2680_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(ov2680_controls)); + if (ret) { + ov2680_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ov2680_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov2680_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + ov2680_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + ov2680_remove(client); + dev_dbg(&client->dev, "+++ remove ov2680\n"); + } + return ret; +out_free: + dev_dbg(&client->dev, "+++ out free\n"); + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct acpi_device_id ov2680_acpi_match[] = { + {"XXOV2680"}, + {"OVTI2680"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ov2680_acpi_match); + +static struct i2c_driver ov2680_driver = { + .driver = { + .name = "ov2680", + .acpi_match_table = ov2680_acpi_match, + }, + .probe_new = ov2680_probe, + .remove = ov2680_remove, +}; +module_i2c_driver(ov2680_driver); + +MODULE_AUTHOR("Jacky Wang "); +MODULE_DESCRIPTION("A low-level driver for OmniVision 2680 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/atomisp-ov2722.c b/drivers/staging/media/atomisp/i2c/atomisp-ov2722.c new file mode 100644 index 000000000..887b6f99f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/atomisp-ov2722.c @@ -0,0 +1,1194 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for OmniVision OV2722 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../include/linux/atomisp_gmin_platform.h" +#include +#include + +#include "ov2722.h" + +/* i2c read/write stuff */ +static int ov2722_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != OV2722_8BIT && data_length != OV2722_16BIT && + data_length != OV2722_32BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0, sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg >> 8); + data[1] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == OV2722_8BIT) + *val = (u8)data[0]; + else if (data_length == OV2722_16BIT) + *val = be16_to_cpu(*(__be16 *)&data[0]); + else + *val = be32_to_cpu(*(__be32 *)&data[0]); + + return 0; +} + +static int ov2722_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int ov2722_write_reg(struct i2c_client *client, u16 data_length, + u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + __be16 *wreg = (__be16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != OV2722_8BIT && data_length != OV2722_16BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == OV2722_8BIT) { + data[2] = (u8)(val); + } else { + /* OV2722_16BIT */ + __be16 *wdata = (__be16 *)&data[2]; + + *wdata = cpu_to_be16(val); + } + + ret = ov2722_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov2722_write_reg_array - Initializes a list of OV2722 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov2722_flush_reg_array, __ov2722_buf_reg_array() and + * __ov2722_write_reg_is_consecutive() are internal functions to + * ov2722_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __ov2722_flush_reg_array(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl) +{ + u16 size; + __be16 *data16 = (void *)&ctrl->buffer.addr; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + *data16 = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov2722_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov2722_buf_reg_array(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl, + const struct ov2722_reg *next) +{ + int size; + __be16 *data16; + + switch (next->type) { + case OV2722_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV2722_16BIT: + size = 2; + data16 = (void *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV2722_MAX_WRITE_BUF_SIZE) + return __ov2722_flush_reg_array(client, ctrl); + + return 0; +} + +static int __ov2722_write_reg_is_consecutive(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl, + const struct ov2722_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int ov2722_write_reg_array(struct i2c_client *client, + const struct ov2722_reg *reglist) +{ + const struct ov2722_reg *next = reglist; + struct ov2722_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != OV2722_TOK_TERM; next++) { + switch (next->type & OV2722_TOK_MASK) { + case OV2722_TOK_DELAY: + err = __ov2722_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__ov2722_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __ov2722_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov2722_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __ov2722_flush_reg_array(client, &ctrl); +} + +static int ov2722_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV2722_FOCAL_LENGTH_NUM << 16) | OV2722_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov2722_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (OV2722_F_NUMBER_DEFAULT_NUM << 16) | OV2722_F_NUMBER_DEM; + return 0; +} + +static int ov2722_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV2722_F_NUMBER_DEFAULT_NUM << 24) | + (OV2722_F_NUMBER_DEM << 16) | + (OV2722_F_NUMBER_DEFAULT_NUM << 8) | OV2722_F_NUMBER_DEM; + return 0; +} + +static int ov2722_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov2722_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2722_device *dev = NULL; + struct atomisp_sensor_mode_data *buf = &info->data; + const unsigned int ext_clk_freq_hz = 19200000; + const unsigned int pll_invariant_div = 10; + unsigned int pix_clk_freq_hz; + u16 pre_pll_clk_div; + u16 pll_multiplier; + u16 op_pix_clk_div; + u16 reg_val; + int ret; + + if (!info) + return -EINVAL; + + dev = to_ov2722_sensor(sd); + + /* pixel clock calculattion */ + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_CTRL3, &pre_pll_clk_div); + if (ret) + return ret; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_MULTIPLIER, &pll_multiplier); + if (ret) + return ret; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_DEBUG_OPT, &op_pix_clk_div); + if (ret) + return ret; + + pre_pll_clk_div = (pre_pll_clk_div & 0x70) >> 4; + if (!pre_pll_clk_div) + return -EINVAL; + + pll_multiplier = pll_multiplier & 0x7f; + op_pix_clk_div = op_pix_clk_div & 0x03; + pix_clk_freq_hz = ext_clk_freq_hz / pre_pll_clk_div * pll_multiplier + * op_pix_clk_div / pll_invariant_div; + + dev->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV2722_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV2722_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV2722_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV2722_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV2722_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_CROP_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_CROP_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_CROP_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_CROP_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_OUTSIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_OUTSIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __ov2722_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2722_device *dev = to_ov2722_sensor(sd); + u16 hts, vts; + int ret; + + dev_dbg(&client->dev, "set_exposure without group hold\n"); + + /* clear VTS_DIFF on manual mode */ + ret = ov2722_write_reg(client, OV2722_16BIT, OV2722_VTS_DIFF_H, 0); + if (ret) + return ret; + + hts = dev->pixels_per_line; + vts = dev->lines_per_frame; + + if ((coarse_itg + OV2722_COARSE_INTG_TIME_MAX_MARGIN) > vts) + vts = coarse_itg + OV2722_COARSE_INTG_TIME_MAX_MARGIN; + + coarse_itg <<= 4; + digitgain <<= 2; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_VTS_H, vts); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_HTS_H, hts); + if (ret) + return ret; + + /* set exposure */ + ret = ov2722_write_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_L, + coarse_itg & 0xff); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_AEC_PK_EXPO_H, + (coarse_itg >> 8) & 0xfff); + if (ret) + return ret; + + /* set analog gain */ + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_AGC_ADJ_H, gain); + if (ret) + return ret; + + /* set digital gain */ + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_R_H, digitgain); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_G_H, digitgain); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_B_H, digitgain); + + return ret; +} + +static int ov2722_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov2722_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov2722_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return ov2722_set_exposure(sd, exp, gain, digitgain); +} + +static long ov2722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov2722_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int ov2722_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_L, + ®_v); + if (ret) + goto err; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_M, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_H, + ®_v2); + if (ret) + goto err; + + *value = reg_v + (((u32)reg_v2 << 16)); +err: + return ret; +} + +static int ov2722_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2722_device *dev = + container_of(ctrl->handler, struct ov2722_device, ctrl_handler); + int ret = 0; + unsigned int val; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov2722_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov2722_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov2722_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov2722_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_LINK_FREQ: + val = dev->res->mipi_freq; + if (val == 0) + return -EINVAL; + + ctrl->val = val * 1000; /* To Hz */ + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .g_volatile_ctrl = ov2722_g_volatile_ctrl +}; + +static const struct v4l2_ctrl_config ov2722_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV2722_FOCAL_LENGTH_DEFAULT, + .max = OV2722_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV2722_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV2722_F_NUMBER_DEFAULT, + .max = OV2722_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV2722_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV2722_F_NUMBER_RANGE, + .max = OV2722_F_NUMBER_RANGE, + .step = 0x01, + .def = OV2722_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_LINK_FREQ, + .name = "Link Frequency", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 1, + .max = 1500000 * 1000, + .step = 1, + .def = 1, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + }, +}; + +static int ov2722_init(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + mutex_lock(&dev->input_lock); + + /* restore settings */ + ov2722_res = ov2722_res_preview; + N_RES = N_RES_PREVIEW; + + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = -1; + struct ov2722_device *dev = to_ov2722_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + if (flag) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + if (ret) + dev->platform_data->v1p8_ctrl(sd, 0); + } + } else { + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + int ret = -1; + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Note: the GPIO order is asymmetric: always RESET# + * before PWDN# when turning it on or off. + */ + ret = dev->platform_data->gpio0_ctrl(sd, flag); + /* + *ov2722 PWDN# active high when pull down,opposite to the convention + */ + ret |= dev->platform_data->gpio1_ctrl(sd, !flag); + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* according to DS, 20ms is needed between PWDN and i2c access */ + msleep(20); + + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int ov2722_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + if (on == 0) + return power_down(sd); + + ret = power_up(sd); + if (!ret) + return ov2722_init(sd); + + return ret; +} + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + ret = ov2722_write_reg(client, OV2722_8BIT, + OV2722_SW_RESET, 0x01); + if (ret) { + dev_err(&client->dev, "ov2722 reset err.\n"); + return ret; + } + + ret = ov2722_write_reg_array(client, dev->res->regs); + if (ret) { + dev_err(&client->dev, "ov2722 write register err.\n"); + return ret; + } + + return ret; +} + +static int ov2722_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2722_resolution *res; + struct camera_mipi_info *ov2722_info = NULL; + int ret = 0; + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + ov2722_info = v4l2_get_subdev_hostdata(sd); + if (!ov2722_info) + return -EINVAL; + + mutex_lock(&dev->input_lock); + res = v4l2_find_nearest_size(ov2722_res_preview, + ARRAY_SIZE(ov2722_res_preview), width, + height, fmt->width, fmt->height); + if (!res) + res = &ov2722_res_preview[N_RES - 1]; + + fmt->width = res->width; + fmt->height = res->height; + dev->res = res; + + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + sd_state->pads->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + + dev->pixels_per_line = dev->res->pixels_per_line; + dev->lines_per_frame = dev->res->lines_per_frame; + + ret = startup(sd); + if (ret) { + int i = 0; + + dev_err(&client->dev, "ov2722 startup err, retry to power up\n"); + for (i = 0; i < OV2722_POWER_UP_RETRY_NUM; i++) { + dev_err(&client->dev, + "ov2722 retry to power up %d/%d times, result: ", + i + 1, OV2722_POWER_UP_RETRY_NUM); + power_down(sd); + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "power up failed, continue\n"); + continue; + } + ret = startup(sd); + if (ret) { + dev_err(&client->dev, " startup FAILED!\n"); + } else { + dev_err(&client->dev, " startup SUCCESS!\n"); + break; + } + } + if (ret) { + dev_err(&client->dev, "ov2722 startup err\n"); + goto err; + } + } + + ret = ov2722_get_intg_factor(client, ov2722_info, dev->res); + if (ret) + dev_err(&client->dev, "failed to get integration_factor\n"); + +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2722_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2722_device *dev = to_ov2722_sensor(sd); + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + fmt->width = dev->res->width; + fmt->height = dev->res->height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov2722_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high = 0, low = 0; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_CHIP_ID_H, &high); + ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_CHIP_ID_L, &low); + id = (high << 8) | low; + + if ((id != OV2722_ID) && (id != OV2720_ID)) { + dev_err(&client->dev, "sensor ID error\n"); + return -ENODEV; + } + + high = 0; + ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_SUB_ID, &high); + revision = (u8)high & 0x0f; + + dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision); + dev_dbg(&client->dev, "detect ov2722 success\n"); + return 0; +} + +static int ov2722_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + + ret = ov2722_write_reg(client, OV2722_8BIT, OV2722_SW_STREAM, + enable ? OV2722_START_STREAMING : + OV2722_STOP_STREAMING); + + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2722_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov2722_detect(client); + if (ret) { + dev_err(&client->dev, "ov2722_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2722_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = dev->res->fps; + + return 0; +} + +static int ov2722_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov2722_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = ov2722_res[index].width; + fse->min_height = ov2722_res[index].height; + fse->max_width = ov2722_res[index].width; + fse->max_height = ov2722_res[index].height; + + return 0; +} + +static int ov2722_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->res->skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops ov2722_sensor_ops = { + .g_skip_frames = ov2722_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops ov2722_video_ops = { + .s_stream = ov2722_s_stream, + .g_frame_interval = ov2722_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ov2722_core_ops = { + .s_power = ov2722_s_power, + .ioctl = ov2722_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov2722_pad_ops = { + .enum_mbus_code = ov2722_enum_mbus_code, + .enum_frame_size = ov2722_enum_frame_size, + .get_fmt = ov2722_get_fmt, + .set_fmt = ov2722_set_fmt, +}; + +static const struct v4l2_subdev_ops ov2722_ops = { + .core = &ov2722_core_ops, + .video = &ov2722_video_ops, + .pad = &ov2722_pad_ops, + .sensor = &ov2722_sensor_ops, +}; + +static void ov2722_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2722_device *dev = to_ov2722_sensor(sd); + + dev->platform_data->csi_cfg(sd, 0); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + media_entity_cleanup(&dev->sd.entity); + kfree(dev); +} + +static int __ov2722_init_ctrl_handler(struct ov2722_device *dev) +{ + struct v4l2_ctrl_handler *hdl; + unsigned int i; + + hdl = &dev->ctrl_handler; + v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ov2722_controls)); + for (i = 0; i < ARRAY_SIZE(ov2722_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov2722_controls[i], + NULL); + + dev->link_freq = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_LINK_FREQ); + + if (dev->ctrl_handler.error || !dev->link_freq) + return dev->ctrl_handler.error; + + dev->sd.ctrl_handler = hdl; + + return 0; +} + +static int ov2722_probe(struct i2c_client *client) +{ + struct ov2722_device *dev; + void *ovpdev; + int ret; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + mutex_init(&dev->input_lock); + + dev->res = &ov2722_res_preview[0]; + v4l2_i2c_subdev_init(&dev->sd, client, &ov2722_ops); + + ovpdev = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + + ret = ov2722_s_config(&dev->sd, client->irq, ovpdev); + if (ret) + goto out_free; + + ret = __ov2722_init_ctrl_handler(dev); + if (ret) + goto out_ctrl_handler_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + ov2722_remove(client); + + return atomisp_register_i2c_module(&dev->sd, ovpdev, RAW_CAMERA); + +out_ctrl_handler_free: + v4l2_ctrl_handler_free(&dev->ctrl_handler); + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct acpi_device_id ov2722_acpi_match[] = { + { "INT33FB" }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ov2722_acpi_match); + +static struct i2c_driver ov2722_driver = { + .driver = { + .name = "ov2722", + .acpi_match_table = ov2722_acpi_match, + }, + .probe_new = ov2722_probe, + .remove = ov2722_remove, +}; +module_i2c_driver(ov2722_driver); + +MODULE_AUTHOR("Wei Liu "); +MODULE_DESCRIPTION("A low-level driver for OmniVision 2722 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/gc0310.h b/drivers/staging/media/atomisp/i2c/gc0310.h new file mode 100644 index 000000000..4b9ce681b --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc0310.h @@ -0,0 +1,405 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for GalaxyCore GC0310 VGA camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __GC0310_H__ +#define __GC0310_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../include/linux/atomisp_platform.h" + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 1 +#define I2C_RETRY_COUNT 5 + +#define GC0310_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define GC0310_FOCAL_LENGTH_DEM 100 +#define GC0310_F_NUMBER_DEFAULT_NUM 26 +#define GC0310_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC0310_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC0310_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define GC0310_F_NUMBER_RANGE 0x1a0a1a0a +#define GC0310_ID 0xa310 + +#define GC0310_RESET_RELATED 0xFE +#define GC0310_REGISTER_PAGE_0 0x0 +#define GC0310_REGISTER_PAGE_3 0x3 + +#define GC0310_FINE_INTG_TIME_MIN 0 +#define GC0310_FINE_INTG_TIME_MAX_MARGIN 0 +#define GC0310_COARSE_INTG_TIME_MIN 1 +#define GC0310_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * GC0310 System control registers + */ +#define GC0310_SW_STREAM 0x10 + +#define GC0310_SC_CMMN_CHIP_ID_H 0xf0 +#define GC0310_SC_CMMN_CHIP_ID_L 0xf1 + +#define GC0310_AEC_PK_EXPO_H 0x03 +#define GC0310_AEC_PK_EXPO_L 0x04 +#define GC0310_AGC_ADJ 0x48 +#define GC0310_DGC_ADJ 0x71 +#if 0 +#define GC0310_GROUP_ACCESS 0x3208 +#endif + +#define GC0310_H_CROP_START_H 0x09 +#define GC0310_H_CROP_START_L 0x0A +#define GC0310_V_CROP_START_H 0x0B +#define GC0310_V_CROP_START_L 0x0C +#define GC0310_H_OUTSIZE_H 0x0F +#define GC0310_H_OUTSIZE_L 0x10 +#define GC0310_V_OUTSIZE_H 0x0D +#define GC0310_V_OUTSIZE_L 0x0E +#define GC0310_H_BLANKING_H 0x05 +#define GC0310_H_BLANKING_L 0x06 +#define GC0310_V_BLANKING_H 0x07 +#define GC0310_V_BLANKING_L 0x08 +#define GC0310_SH_DELAY 0x11 + +#define GC0310_START_STREAMING 0x94 /* 8-bit enable */ +#define GC0310_STOP_STREAMING 0x0 /* 8-bit disable */ + +#define GC0310_BIN_FACTOR_MAX 3 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct gc0310_resolution { + u8 *desc; + const struct gc0310_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct gc0310_format { + u8 *desc; + u32 pixelformat; + struct gc0310_reg *regs; +}; + +/* + * gc0310 device structure. + */ +struct gc0310_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + struct gc0310_resolution *res; + u8 type; + bool power_on; +}; + +enum gc0310_tok_type { + GC0310_8BIT = 0x0001, + GC0310_TOK_TERM = 0xf000, /* terminating token for reg list */ + GC0310_TOK_DELAY = 0xfe00, /* delay token for reg list */ + GC0310_TOK_MASK = 0xfff0 +}; + +/** + * struct gc0310_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct gc0310_reg { + enum gc0310_tok_type type; + u8 reg; + u8 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd) + +#define GC0310_MAX_WRITE_BUF_SIZE 30 + +struct gc0310_write_buffer { + u8 addr; + u8 data[GC0310_MAX_WRITE_BUF_SIZE]; +}; + +struct gc0310_write_ctrl { + int index; + struct gc0310_write_buffer buffer; +}; + +/* + * Register settings for various resolution + */ +static const struct gc0310_reg gc0310_reset_register[] = { +///////////////////////////////////////////////// +///////////////// system reg ///////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0xf0}, + {GC0310_8BIT, 0xfe, 0xf0}, + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_8BIT, 0xfc, 0x0e}, //4e + {GC0310_8BIT, 0xfc, 0x0e}, //16//4e // [0]apwd [6]regf_clk_gate + {GC0310_8BIT, 0xf2, 0x80}, //sync output + {GC0310_8BIT, 0xf3, 0x00}, //1f//01 data output + {GC0310_8BIT, 0xf7, 0x33}, //f9 + {GC0310_8BIT, 0xf8, 0x05}, //00 + {GC0310_8BIT, 0xf9, 0x0e}, // 0x8e //0f + {GC0310_8BIT, 0xfa, 0x11}, + +///////////////////////////////////////////////// +/////////////////// MIPI //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0x03}, + {GC0310_8BIT, 0x01, 0x03}, ///mipi 1lane + {GC0310_8BIT, 0x02, 0x22}, // 0x33 + {GC0310_8BIT, 0x03, 0x94}, + {GC0310_8BIT, 0x04, 0x01}, // fifo_prog + {GC0310_8BIT, 0x05, 0x00}, //fifo_prog + {GC0310_8BIT, 0x06, 0x80}, //b0 //YUV ISP data + {GC0310_8BIT, 0x11, 0x2a},//1e //LDI set YUV422 + {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] // + {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8] + {GC0310_8BIT, 0x15, 0x12}, // 0x10 //DPHYY_MODE read_ready + {GC0310_8BIT, 0x17, 0x01}, + {GC0310_8BIT, 0x40, 0x08}, + {GC0310_8BIT, 0x41, 0x00}, + {GC0310_8BIT, 0x42, 0x00}, + {GC0310_8BIT, 0x43, 0x00}, + {GC0310_8BIT, 0x21, 0x02}, // 0x01 + {GC0310_8BIT, 0x22, 0x02}, // 0x01 + {GC0310_8BIT, 0x23, 0x01}, // 0x05 //Nor:0x05 DOU:0x06 + {GC0310_8BIT, 0x29, 0x00}, + {GC0310_8BIT, 0x2A, 0x25}, // 0x05 //data zero 0x7a de + {GC0310_8BIT, 0x2B, 0x02}, + + {GC0310_8BIT, 0xfe, 0x00}, + +///////////////////////////////////////////////// +///////////////// CISCTL reg ///////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x00, 0x2f}, //2f//0f//02//01 + {GC0310_8BIT, 0x01, 0x0f}, //06 + {GC0310_8BIT, 0x02, 0x04}, + {GC0310_8BIT, 0x4f, 0x00}, //AEC 0FF + {GC0310_8BIT, 0x03, 0x01}, // 0x03 //04 + {GC0310_8BIT, 0x04, 0xc0}, // 0xe8 //58 + {GC0310_8BIT, 0x05, 0x00}, + {GC0310_8BIT, 0x06, 0xb2}, // 0x0a //HB + {GC0310_8BIT, 0x07, 0x00}, + {GC0310_8BIT, 0x08, 0x0c}, // 0x89 //VB + {GC0310_8BIT, 0x09, 0x00}, //row start + {GC0310_8BIT, 0x0a, 0x00}, // + {GC0310_8BIT, 0x0b, 0x00}, //col start + {GC0310_8BIT, 0x0c, 0x00}, + {GC0310_8BIT, 0x0d, 0x01}, //height + {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height + {GC0310_8BIT, 0x0f, 0x02}, //width + {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height + {GC0310_8BIT, 0x17, 0x14}, + {GC0310_8BIT, 0x18, 0x1a}, //0a//[4]double reset + {GC0310_8BIT, 0x19, 0x14}, //AD pipeline + {GC0310_8BIT, 0x1b, 0x48}, + {GC0310_8BIT, 0x1e, 0x6b}, //3b//col bias + {GC0310_8BIT, 0x1f, 0x28}, //20//00//08//txlow + {GC0310_8BIT, 0x20, 0x89}, //88//0c//[3:2]DA15 + {GC0310_8BIT, 0x21, 0x49}, //48//[3] txhigh + {GC0310_8BIT, 0x22, 0xb0}, + {GC0310_8BIT, 0x23, 0x04}, //[1:0]vcm_r + {GC0310_8BIT, 0x24, 0x16}, //15 + {GC0310_8BIT, 0x34, 0x20}, //[6:4] rsg high//range + +///////////////////////////////////////////////// +//////////////////// BLK //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x26, 0x23}, //[1]dark_current_en [0]offset_en + {GC0310_8BIT, 0x28, 0xff}, //BLK_limie_value + {GC0310_8BIT, 0x29, 0x00}, //global offset + {GC0310_8BIT, 0x33, 0x18}, //offset_ratio + {GC0310_8BIT, 0x37, 0x20}, //dark_current_ratio + {GC0310_8BIT, 0x2a, 0x00}, + {GC0310_8BIT, 0x2b, 0x00}, + {GC0310_8BIT, 0x2c, 0x00}, + {GC0310_8BIT, 0x2d, 0x00}, + {GC0310_8BIT, 0x2e, 0x00}, + {GC0310_8BIT, 0x2f, 0x00}, + {GC0310_8BIT, 0x30, 0x00}, + {GC0310_8BIT, 0x31, 0x00}, + {GC0310_8BIT, 0x47, 0x80}, //a7 + {GC0310_8BIT, 0x4e, 0x66}, //select_row + {GC0310_8BIT, 0xa8, 0x02}, //win_width_dark, same with crop_win_width + {GC0310_8BIT, 0xa9, 0x80}, + +///////////////////////////////////////////////// +////////////////// ISP reg /////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x40, 0x06}, // 0xff //ff //48 + {GC0310_8BIT, 0x41, 0x00}, // 0x21 //00//[0]curve_en + {GC0310_8BIT, 0x42, 0x04}, // 0xcf //0a//[1]awn_en + {GC0310_8BIT, 0x44, 0x18}, // 0x18 //02 + {GC0310_8BIT, 0x46, 0x02}, // 0x03 //sync + {GC0310_8BIT, 0x49, 0x03}, + {GC0310_8BIT, 0x4c, 0x20}, //00[5]pretect exp + {GC0310_8BIT, 0x50, 0x01}, //crop enable + {GC0310_8BIT, 0x51, 0x00}, + {GC0310_8BIT, 0x52, 0x00}, + {GC0310_8BIT, 0x53, 0x00}, + {GC0310_8BIT, 0x54, 0x01}, + {GC0310_8BIT, 0x55, 0x01}, //crop window height + {GC0310_8BIT, 0x56, 0xf0}, + {GC0310_8BIT, 0x57, 0x02}, //crop window width + {GC0310_8BIT, 0x58, 0x90}, + +///////////////////////////////////////////////// +/////////////////// GAIN //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x70, 0x70}, //70 //80//global gain + {GC0310_8BIT, 0x71, 0x20}, // pregain gain + {GC0310_8BIT, 0x72, 0x40}, // post gain + {GC0310_8BIT, 0x5a, 0x84}, //84//analog gain 0 + {GC0310_8BIT, 0x5b, 0xc9}, //c9 + {GC0310_8BIT, 0x5c, 0xed}, //ed//not use pga gain highest level + {GC0310_8BIT, 0x77, 0x40}, // R gain 0x74 //awb gain + {GC0310_8BIT, 0x78, 0x40}, // G gain + {GC0310_8BIT, 0x79, 0x40}, // B gain 0x5f + + {GC0310_8BIT, 0x48, 0x00}, + {GC0310_8BIT, 0xfe, 0x01}, + {GC0310_8BIT, 0x0a, 0x45}, //[7]col gain mode + + {GC0310_8BIT, 0x3e, 0x40}, + {GC0310_8BIT, 0x3f, 0x5c}, + {GC0310_8BIT, 0x40, 0x7b}, + {GC0310_8BIT, 0x41, 0xbd}, + {GC0310_8BIT, 0x42, 0xf6}, + {GC0310_8BIT, 0x43, 0x63}, + {GC0310_8BIT, 0x03, 0x60}, + {GC0310_8BIT, 0x44, 0x03}, + +///////////////////////////////////////////////// +///////////////// dark sun ////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0x01}, + {GC0310_8BIT, 0x45, 0xa4}, // 0xf7 + {GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun value th + {GC0310_8BIT, 0x48, 0x03}, //sun mode + {GC0310_8BIT, 0x4f, 0x60}, //sun_clamp + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_TOK_TERM, 0, 0}, +}; + +static struct gc0310_reg const gc0310_VGA_30fps[] = { + {GC0310_8BIT, 0xfe, 0x00}, + {GC0310_8BIT, 0x0d, 0x01}, //height + {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height + {GC0310_8BIT, 0x0f, 0x02}, //width + {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height + + {GC0310_8BIT, 0x50, 0x01}, //crop enable + {GC0310_8BIT, 0x51, 0x00}, + {GC0310_8BIT, 0x52, 0x00}, + {GC0310_8BIT, 0x53, 0x00}, + {GC0310_8BIT, 0x54, 0x01}, + {GC0310_8BIT, 0x55, 0x01}, //crop window height + {GC0310_8BIT, 0x56, 0xf0}, + {GC0310_8BIT, 0x57, 0x02}, //crop window width + {GC0310_8BIT, 0x58, 0x90}, + + {GC0310_8BIT, 0xfe, 0x03}, + {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] // + {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8] + + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_TOK_TERM, 0, 0}, +}; + +static struct gc0310_resolution gc0310_res_preview[] = { + { + .desc = "gc0310_VGA_30fps", + .width = 656, // 648, + .height = 496, // 488, + .fps = 30, + //.pix_clk_freq = 73, + .used = 0, +#if 0 + .pixels_per_line = 0x0314, + .lines_per_frame = 0x0213, +#endif + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 2, + .regs = gc0310_VGA_30fps, + }, +}; + +#define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview)) + +static struct gc0310_resolution *gc0310_res = gc0310_res_preview; +static unsigned long N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/gc2235.h b/drivers/staging/media/atomisp/i2c/gc2235.h new file mode 100644 index 000000000..806be5dff --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc2235.h @@ -0,0 +1,680 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for GalaxyCore GC2235 2M camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. + * + */ + +#ifndef __GC2235_H__ +#define __GC2235_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../include/linux/atomisp_platform.h" + +/* + * FIXME: non-preview resolutions are currently broken + */ +#define ENABLE_NON_PREVIEW 0 + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define GC2235_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define GC2235_FOCAL_LENGTH_DEM 100 +#define GC2235_F_NUMBER_DEFAULT_NUM 26 +#define GC2235_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC2235_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC2235_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define GC2235_F_NUMBER_RANGE 0x1a0a1a0a +#define GC2235_ID 0x2235 + +#define GC2235_FINE_INTG_TIME_MIN 0 +#define GC2235_FINE_INTG_TIME_MAX_MARGIN 0 +#define GC2235_COARSE_INTG_TIME_MIN 1 +#define GC2235_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * GC2235 System control registers + */ +/* + * GC2235 System control registers + */ +#define GC2235_SENSOR_ID_H 0xF0 +#define GC2235_SENSOR_ID_L 0xF1 +#define GC2235_RESET_RELATED 0xFE +#define GC2235_SW_RESET 0x8 +#define GC2235_MIPI_RESET 0x3 +#define GC2235_RESET_BIT 0x4 +#define GC2235_REGISTER_PAGE_0 0x0 +#define GC2235_REGISTER_PAGE_3 0x3 + +#define GC2235_V_CROP_START_H 0x91 +#define GC2235_V_CROP_START_L 0x92 +#define GC2235_H_CROP_START_H 0x93 +#define GC2235_H_CROP_START_L 0x94 +#define GC2235_V_OUTSIZE_H 0x95 +#define GC2235_V_OUTSIZE_L 0x96 +#define GC2235_H_OUTSIZE_H 0x97 +#define GC2235_H_OUTSIZE_L 0x98 + +#define GC2235_HB_H 0x5 +#define GC2235_HB_L 0x6 +#define GC2235_VB_H 0x7 +#define GC2235_VB_L 0x8 +#define GC2235_SH_DELAY_H 0x11 +#define GC2235_SH_DELAY_L 0x12 + +#define GC2235_CSI2_MODE 0x10 + +#define GC2235_EXPOSURE_H 0x3 +#define GC2235_EXPOSURE_L 0x4 +#define GC2235_GLOBAL_GAIN 0xB0 +#define GC2235_PRE_GAIN 0xB1 +#define GC2235_AWB_R_GAIN 0xB3 +#define GC2235_AWB_G_GAIN 0xB4 +#define GC2235_AWB_B_GAIN 0xB5 + +#define GC2235_START_STREAMING 0x91 +#define GC2235_STOP_STREAMING 0x0 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct gc2235_resolution { + u8 *desc; + const struct gc2235_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct gc2235_format { + u8 *desc; + u32 pixelformat; + struct gc2235_reg *regs; +}; + +/* + * gc2235 device structure. + */ +struct gc2235_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + struct gc2235_resolution *res; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + u8 type; +}; + +enum gc2235_tok_type { + GC2235_8BIT = 0x0001, + GC2235_16BIT = 0x0002, + GC2235_32BIT = 0x0004, + GC2235_TOK_TERM = 0xf000, /* terminating token for reg list */ + GC2235_TOK_DELAY = 0xfe00, /* delay token for reg list */ + GC2235_TOK_MASK = 0xfff0 +}; + +/** + * struct gc2235_reg - MI sensor register format + * @type: type of the register + * @reg: 8-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct gc2235_reg { + enum gc2235_tok_type type; + u8 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_gc2235_sensor(x) container_of(x, struct gc2235_device, sd) + +#define GC2235_MAX_WRITE_BUF_SIZE 30 + +struct gc2235_write_buffer { + u8 addr; + u8 data[GC2235_MAX_WRITE_BUF_SIZE]; +}; + +struct gc2235_write_ctrl { + int index; + struct gc2235_write_buffer buffer; +}; + +static struct gc2235_reg const gc2235_stream_on[] = { + { GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */ + { GC2235_8BIT, 0x10, 0x91}, /* start mipi */ + { GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_stream_off[] = { + { GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */ + { GC2235_8BIT, 0x10, 0x01}, /* stop mipi */ + { GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_init_settings[] = { + /* System */ + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xf2, 0x00 }, + { GC2235_8BIT, 0xf6, 0x00 }, + { GC2235_8BIT, 0xfc, 0x06 }, + { GC2235_8BIT, 0xf7, 0x15 }, + { GC2235_8BIT, 0xf8, 0x84 }, + { GC2235_8BIT, 0xf9, 0xfe }, + { GC2235_8BIT, 0xfa, 0x00 }, + { GC2235_8BIT, 0xfe, 0x00 }, + /* Analog & cisctl */ + { GC2235_8BIT, 0x03, 0x04 }, + { GC2235_8BIT, 0x04, 0x9E }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x06, 0xfd }, + { GC2235_8BIT, 0x07, 0x00 }, + { GC2235_8BIT, 0x08, 0x14 }, + { GC2235_8BIT, 0x0a, 0x02 }, /* row start */ + { GC2235_8BIT, 0x0c, 0x00 }, /* col start */ + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x60 }, + { GC2235_8BIT, 0x17, 0x15 }, /* mirror flip */ + { GC2235_8BIT, 0x18, 0x1a }, + { GC2235_8BIT, 0x19, 0x06 }, + { GC2235_8BIT, 0x1a, 0x01 }, + { GC2235_8BIT, 0x1b, 0x4d }, + { GC2235_8BIT, 0x1e, 0x88 }, + { GC2235_8BIT, 0x1f, 0x48 }, + { GC2235_8BIT, 0x20, 0x03 }, + { GC2235_8BIT, 0x21, 0x7f }, + { GC2235_8BIT, 0x22, 0x83 }, + { GC2235_8BIT, 0x23, 0x42 }, + { GC2235_8BIT, 0x24, 0x16 }, + { GC2235_8BIT, 0x26, 0x01 }, /*analog gain*/ + { GC2235_8BIT, 0x27, 0x30 }, + { GC2235_8BIT, 0x3f, 0x00 }, /* PRC */ + /* blk */ + { GC2235_8BIT, 0x40, 0xa3 }, + { GC2235_8BIT, 0x41, 0x82 }, + { GC2235_8BIT, 0x43, 0x20 }, + { GC2235_8BIT, 0x5e, 0x18 }, + { GC2235_8BIT, 0x5f, 0x18 }, + { GC2235_8BIT, 0x60, 0x18 }, + { GC2235_8BIT, 0x61, 0x18 }, + { GC2235_8BIT, 0x62, 0x18 }, + { GC2235_8BIT, 0x63, 0x18 }, + { GC2235_8BIT, 0x64, 0x18 }, + { GC2235_8BIT, 0x65, 0x18 }, + { GC2235_8BIT, 0x66, 0x20 }, + { GC2235_8BIT, 0x67, 0x20 }, + { GC2235_8BIT, 0x68, 0x20 }, + { GC2235_8BIT, 0x69, 0x20 }, + /* Gain */ + { GC2235_8BIT, 0xb2, 0x00 }, + { GC2235_8BIT, 0xb3, 0x40 }, + { GC2235_8BIT, 0xb4, 0x40 }, + { GC2235_8BIT, 0xb5, 0x40 }, + /* Dark sun */ + { GC2235_8BIT, 0xbc, 0x00 }, + + { GC2235_8BIT, 0xfe, 0x03 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +/* + * Register settings for various resolution + */ +#if ENABLE_NON_PREVIEW +static struct gc2235_reg const gc2235_1296_736_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x07, 0x01 }, /* VBI */ + { GC2235_8BIT, 0x08, 0x44 }, + { GC2235_8BIT, 0x09, 0x00 }, /* row start */ + { GC2235_8BIT, 0x0a, 0xf0 }, + { GC2235_8BIT, 0x0b, 0x00 }, /* col start */ + { GC2235_8BIT, 0x0c, 0xa0 }, + { GC2235_8BIT, 0x0d, 0x02 }, /* win height 736 */ + { GC2235_8BIT, 0x0e, 0xf0 }, + { GC2235_8BIT, 0x0f, 0x05 }, /* win width: 1296 */ + { GC2235_8BIT, 0x10, 0x20 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x08 }, + { GC2235_8BIT, 0x94, 0x08 }, + { GC2235_8BIT, 0x95, 0x02 }, /* crop win height 736 */ + { GC2235_8BIT, 0x96, 0xe0 }, + { GC2235_8BIT, 0x97, 0x05 }, /* crop win width 1296 */ + { GC2235_8BIT, 0x98, 0x10 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0x54 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x06 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_960_640_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x07, 0x02 }, /* VBI */ + { GC2235_8BIT, 0x08, 0xA4 }, + { GC2235_8BIT, 0x09, 0x01 }, /* row start */ + { GC2235_8BIT, 0x0a, 0x18 }, + { GC2235_8BIT, 0x0b, 0x01 }, /* col start */ + { GC2235_8BIT, 0x0c, 0x40 }, + { GC2235_8BIT, 0x0d, 0x02 }, /* win height 656 */ + { GC2235_8BIT, 0x0e, 0x90 }, + { GC2235_8BIT, 0x0f, 0x03 }, /* win width: 976 */ + { GC2235_8BIT, 0x10, 0xd0 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x06 }, + { GC2235_8BIT, 0x95, 0x02 }, /* crop win height 640 */ + { GC2235_8BIT, 0x96, 0x80 }, + { GC2235_8BIT, 0x97, 0x03 }, /* crop win width 960 */ + { GC2235_8BIT, 0x98, 0xc0 }, + /* mimp init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xb0 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x04 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; +#endif + +static struct gc2235_reg const gc2235_1600_900_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x03 }, /* win height 932 */ + { GC2235_8BIT, 0x0e, 0xa4 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1632 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x06 }, + { GC2235_8BIT, 0x95, 0x03 }, /* crop win height 900 */ + { GC2235_8BIT, 0x96, 0x84 }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1600 */ + { GC2235_8BIT, 0x98, 0x40 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xd0 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_1616_1082_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x4a }, + { GC2235_8BIT, 0x94, 0x00 }, + { GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1082 */ + { GC2235_8BIT, 0x96, 0x3a }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */ + { GC2235_8BIT, 0x98, 0x50 }, + /* mimp init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_1616_1216_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x00 }, + { GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1216 */ + { GC2235_8BIT, 0x96, 0xc0 }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */ + { GC2235_8BIT, 0x98, 0x50 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_resolution gc2235_res_preview[] = { + { + .desc = "gc2235_1600_900_30fps", + .width = 1600, + .height = 900, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1068, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1600_900_30fps, + }, + + { + .desc = "gc2235_1600_1066_30fps", + .width = 1616, + .height = 1082, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1082_30fps, + }, + { + .desc = "gc2235_1600_1200_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1216_30fps, + }, + +}; + +#define N_RES_PREVIEW (ARRAY_SIZE(gc2235_res_preview)) + +/* + * Disable non-preview configurations until the configuration selection is + * improved. + */ +#if ENABLE_NON_PREVIEW +static struct gc2235_resolution gc2235_res_still[] = { + { + .desc = "gc2235_1600_900_30fps", + .width = 1600, + .height = 900, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1068, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1600_900_30fps, + }, + { + .desc = "gc2235_1600_1066_30fps", + .width = 1616, + .height = 1082, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1082_30fps, + }, + { + .desc = "gc2235_1600_1200_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1216_30fps, + }, + +}; + +#define N_RES_STILL (ARRAY_SIZE(gc2235_res_still)) + +static struct gc2235_resolution gc2235_res_video[] = { + { + .desc = "gc2235_1296_736_30fps", + .width = 1296, + .height = 736, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 1828, + .lines_per_frame = 888, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1296_736_30fps, + }, + { + .desc = "gc2235_960_640_30fps", + .width = 960, + .height = 640, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 1492, + .lines_per_frame = 792, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_960_640_30fps, + }, + +}; + +#define N_RES_VIDEO (ARRAY_SIZE(gc2235_res_video)) +#endif + +static struct gc2235_resolution *gc2235_res = gc2235_res_preview; +static unsigned long N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/mt9m114.h b/drivers/staging/media/atomisp/i2c/mt9m114.h new file mode 100644 index 000000000..bcce18b65 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/mt9m114.h @@ -0,0 +1,1794 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for mt9m114 Camera Sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __A1040_H__ +#define __A1040_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../include/linux/atomisp_platform.h" +#include "../include/linux/atomisp.h" + +#define V4L2_IDENT_MT9M114 8245 + +#define MT9P111_REV3 +#define FULLINISUPPORT + +/* #defines for register writes and register array processing */ +#define MISENSOR_8BIT 1 +#define MISENSOR_16BIT 2 +#define MISENSOR_32BIT 4 + +#define MISENSOR_FWBURST0 0x80 +#define MISENSOR_FWBURST1 0x81 +#define MISENSOR_FWBURST4 0x84 +#define MISENSOR_FWBURST 0x88 + +#define MISENSOR_TOK_TERM 0xf000 /* terminating token for reg list */ +#define MISENSOR_TOK_DELAY 0xfe00 /* delay token for reg list */ +#define MISENSOR_TOK_FWLOAD 0xfd00 /* token indicating load FW */ +#define MISENSOR_TOK_POLL 0xfc00 /* token indicating poll instruction */ +#define MISENSOR_TOK_RMW 0x0010 /* RMW operation */ +#define MISENSOR_TOK_MASK 0xfff0 +#define MISENSOR_AWB_STEADY BIT(0) /* awb steady */ +#define MISENSOR_AE_READY BIT(3) /* ae status ready */ + +/* mask to set sensor read_mode via misensor_rmw_reg */ +#define MISENSOR_R_MODE_MASK 0x0330 +/* mask to set sensor vert_flip and horz_mirror */ +#define MISENSOR_VFLIP_MASK 0x0002 +#define MISENSOR_HFLIP_MASK 0x0001 +#define MISENSOR_FLIP_EN 1 +#define MISENSOR_FLIP_DIS 0 + +/* bits set to set sensor read_mode via misensor_rmw_reg */ +#define MISENSOR_SKIPPING_SET 0x0011 +#define MISENSOR_SUMMING_SET 0x0033 +#define MISENSOR_NORMAL_SET 0x0000 + +/* sensor register that control sensor read-mode and mirror */ +#define MISENSOR_READ_MODE 0xC834 +/* sensor ae-track status register */ +#define MISENSOR_AE_TRACK_STATUS 0xA800 +/* sensor awb status register */ +#define MISENSOR_AWB_STATUS 0xAC00 +/* sensor coarse integration time register */ +#define MISENSOR_COARSE_INTEGRATION_TIME 0xC83C + +/* registers */ +#define REG_SW_RESET 0x301A +#define REG_SW_STREAM 0xDC00 +#define REG_SCCB_CTRL 0x3100 +#define REG_SC_CMMN_CHIP_ID 0x0000 +#define REG_V_START 0xc800 /* 16bits */ +#define REG_H_START 0xc802 /* 16bits */ +#define REG_V_END 0xc804 /* 16bits */ +#define REG_H_END 0xc806 /* 16bits */ +#define REG_PIXEL_CLK 0xc808 /* 32bits */ +#define REG_TIMING_VTS 0xc812 /* 16bits */ +#define REG_TIMING_HTS 0xc814 /* 16bits */ +#define REG_WIDTH 0xC868 /* 16bits */ +#define REG_HEIGHT 0xC86A /* 16bits */ +#define REG_EXPO_COARSE 0x3012 /* 16bits */ +#define REG_EXPO_FINE 0x3014 /* 16bits */ +#define REG_GAIN 0x305E +#define REG_ANALOGGAIN 0x305F +#define REG_ADDR_ACESSS 0x098E /* logical_address_access */ +#define REG_COMM_Register 0x0080 /* command_register */ + +#define SENSOR_DETECTED 1 +#define SENSOR_NOT_DETECTED 0 + +#define I2C_RETRY_COUNT 5 +#define MSG_LEN_OFFSET 2 + +#ifndef MIPI_CONTROL +#define MIPI_CONTROL 0x3400 /* MIPI_Control */ +#endif + +/* GPIO pin on Moorestown */ +#define GPIO_SCLK_25 44 +#define GPIO_STB_PIN 47 + +#define GPIO_STDBY_PIN 49 /* ab:new */ +#define GPIO_RESET_PIN 50 + +/* System control register for Aptina A-1040SOC*/ +#define MT9M114_PID 0x0 + +/* MT9P111_DEVICE_ID */ +#define MT9M114_MOD_ID 0x2481 + +#define MT9M114_FINE_INTG_TIME_MIN 0 +#define MT9M114_FINE_INTG_TIME_MAX_MARGIN 0 +#define MT9M114_COARSE_INTG_TIME_MIN 1 +#define MT9M114_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* ulBPat; */ + +#define MT9M114_BPAT_RGRGGBGB BIT(0) +#define MT9M114_BPAT_GRGRBGBG BIT(1) +#define MT9M114_BPAT_GBGBRGRG BIT(2) +#define MT9M114_BPAT_BGBGGRGR BIT(3) + +#define MT9M114_FOCAL_LENGTH_NUM 208 /*2.08mm*/ +#define MT9M114_FOCAL_LENGTH_DEM 100 +#define MT9M114_F_NUMBER_DEFAULT_NUM 24 +#define MT9M114_F_NUMBER_DEM 10 +#define MT9M114_WAIT_STAT_TIMEOUT 100 +#define MT9M114_FLICKER_MODE_50HZ 1 +#define MT9M114_FLICKER_MODE_60HZ 2 +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define MT9M114_FOCAL_LENGTH_DEFAULT 0xD00064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define MT9M114_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define MT9M114_F_NUMBER_RANGE 0x180a180a + +/* Supported resolutions */ +enum { + MT9M114_RES_736P, + MT9M114_RES_864P, + MT9M114_RES_960P, +}; + +#define MT9M114_RES_960P_SIZE_H 1296 +#define MT9M114_RES_960P_SIZE_V 976 +#define MT9M114_RES_720P_SIZE_H 1280 +#define MT9M114_RES_720P_SIZE_V 720 +#define MT9M114_RES_576P_SIZE_H 1024 +#define MT9M114_RES_576P_SIZE_V 576 +#define MT9M114_RES_480P_SIZE_H 768 +#define MT9M114_RES_480P_SIZE_V 480 +#define MT9M114_RES_VGA_SIZE_H 640 +#define MT9M114_RES_VGA_SIZE_V 480 +#define MT9M114_RES_QVGA_SIZE_H 320 +#define MT9M114_RES_QVGA_SIZE_V 240 +#define MT9M114_RES_QCIF_SIZE_H 176 +#define MT9M114_RES_QCIF_SIZE_V 144 + +#define MT9M114_RES_720_480p_768_SIZE_H 736 +#define MT9M114_RES_720_480p_768_SIZE_V 496 +#define MT9M114_RES_736P_SIZE_H 1296 +#define MT9M114_RES_736P_SIZE_V 736 +#define MT9M114_RES_864P_SIZE_H 1296 +#define MT9M114_RES_864P_SIZE_V 864 +#define MT9M114_RES_976P_SIZE_H 1296 +#define MT9M114_RES_976P_SIZE_V 976 + +#define MT9M114_BIN_FACTOR_MAX 3 + +#define MT9M114_DEFAULT_FIRST_EXP 0x10 +#define MT9M114_MAX_FIRST_EXP 0x302 + +/* completion status polling requirements, usage based on Aptina .INI Rev2 */ +enum poll_reg { + NO_POLLING, + PRE_POLLING, + POST_POLLING, +}; + +/* + * struct misensor_reg - MI sensor register format + * @length: length of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * Define a structure for sensor register initialization values + */ +struct misensor_reg { + u32 length; + u32 reg; + u32 val; /* value or for read/mod/write, AND mask */ + u32 val2; /* optional; for rmw, OR mask */ +}; + +/* + * struct misensor_fwreg - Firmware burst command + * @type: FW burst or 8/16 bit register + * @addr: 16-bit offset to register or other values depending on type + * @valx: data value for burst (or other commands) + * + * Define a structure for sensor register initialization values + */ +struct misensor_fwreg { + u32 type; /* type of value, register or FW burst string */ + u32 addr; /* target address */ + u32 val0; + u32 val1; + u32 val2; + u32 val3; + u32 val4; + u32 val5; + u32 val6; + u32 val7; +}; + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct mt9m114_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + struct v4l2_ctrl_handler ctrl_handler; + int real_model_id; + int nctx; + int power; + + unsigned int bus_width; + unsigned int mode; + unsigned int field_inv; + unsigned int field_sel; + unsigned int ycseq; + unsigned int conv422; + unsigned int bpat; + unsigned int hpol; + unsigned int vpol; + unsigned int edge; + unsigned int bls; + unsigned int gamma; + unsigned int cconv; + unsigned int res; + unsigned int dwn_sz; + unsigned int blc; + unsigned int agc; + unsigned int awb; + unsigned int aec; + /* extension SENSOR version 2 */ + unsigned int cie_profile; + + /* extension SENSOR version 3 */ + unsigned int flicker_freq; + + /* extension SENSOR version 4 */ + unsigned int smia_mode; + unsigned int mipi_mode; + + /* Add name here to load shared library */ + unsigned int type; + + /*Number of MIPI lanes*/ + unsigned int mipi_lanes; + /*WA for low light AE*/ + unsigned int first_exp; + unsigned int first_gain; + unsigned int first_diggain; + char name[32]; + + u8 lightfreq; + u8 streamon; +}; + +struct mt9m114_format_struct { + u8 *desc; + u32 pixelformat; + struct regval_list *regs; +}; + +struct mt9m114_res_struct { + u8 *desc; + int res; + int width; + int height; + int fps; + int skip_frames; + bool used; + struct regval_list *regs; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; +}; + +/* 2 bytes used for address: 256 bytes total */ +#define MT9M114_MAX_WRITE_BUF_SIZE 254 +struct mt9m114_write_buffer { + u16 addr; + u8 data[MT9M114_MAX_WRITE_BUF_SIZE]; +}; + +struct mt9m114_write_ctrl { + int index; + struct mt9m114_write_buffer buffer; +}; + +/* + * Modes supported by the mt9m114 driver. + * Please, keep them in ascending order. + */ +static struct mt9m114_res_struct mt9m114_res[] = { + { + .desc = "720P", + .res = MT9M114_RES_736P, + .width = 1296, + .height = 736, + .fps = 30, + .used = false, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0640, + .lines_per_frame = 0x0307, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, + { + .desc = "848P", + .res = MT9M114_RES_864P, + .width = 1296, + .height = 864, + .fps = 30, + .used = false, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0640, + .lines_per_frame = 0x03E8, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, + { + .desc = "960P", + .res = MT9M114_RES_960P, + .width = 1296, + .height = 976, + .fps = 30, + .used = false, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0644, /* consistent with regs arrays */ + .lines_per_frame = 0x03E5, /* consistent with regs arrays */ + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, +}; + +#define N_RES (ARRAY_SIZE(mt9m114_res)) + +#if 0 /* Currently unused */ +static struct misensor_reg const mt9m114_exitstandby[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + /* exit-standby */ + {MISENSOR_8BIT, 0xDC00, 0x54}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; +#endif + +static struct misensor_reg const mt9m114_exp_win[5][5] = { + { + {MISENSOR_8BIT, 0xA407, 0x64}, + {MISENSOR_8BIT, 0xA408, 0x64}, + {MISENSOR_8BIT, 0xA409, 0x64}, + {MISENSOR_8BIT, 0xA40A, 0x64}, + {MISENSOR_8BIT, 0xA40B, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA40C, 0x64}, + {MISENSOR_8BIT, 0xA40D, 0x64}, + {MISENSOR_8BIT, 0xA40E, 0x64}, + {MISENSOR_8BIT, 0xA40F, 0x64}, + {MISENSOR_8BIT, 0xA410, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA411, 0x64}, + {MISENSOR_8BIT, 0xA412, 0x64}, + {MISENSOR_8BIT, 0xA413, 0x64}, + {MISENSOR_8BIT, 0xA414, 0x64}, + {MISENSOR_8BIT, 0xA415, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA416, 0x64}, + {MISENSOR_8BIT, 0xA417, 0x64}, + {MISENSOR_8BIT, 0xA418, 0x64}, + {MISENSOR_8BIT, 0xA419, 0x64}, + {MISENSOR_8BIT, 0xA41A, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA41B, 0x64}, + {MISENSOR_8BIT, 0xA41C, 0x64}, + {MISENSOR_8BIT, 0xA41D, 0x64}, + {MISENSOR_8BIT, 0xA41E, 0x64}, + {MISENSOR_8BIT, 0xA41F, 0x64}, + }, +}; + +static struct misensor_reg const mt9m114_exp_average[] = { + {MISENSOR_8BIT, 0xA407, 0x00}, + {MISENSOR_8BIT, 0xA408, 0x00}, + {MISENSOR_8BIT, 0xA409, 0x00}, + {MISENSOR_8BIT, 0xA40A, 0x00}, + {MISENSOR_8BIT, 0xA40B, 0x00}, + {MISENSOR_8BIT, 0xA40C, 0x00}, + {MISENSOR_8BIT, 0xA40D, 0x00}, + {MISENSOR_8BIT, 0xA40E, 0x00}, + {MISENSOR_8BIT, 0xA40F, 0x00}, + {MISENSOR_8BIT, 0xA410, 0x00}, + {MISENSOR_8BIT, 0xA411, 0x00}, + {MISENSOR_8BIT, 0xA412, 0x00}, + {MISENSOR_8BIT, 0xA413, 0x00}, + {MISENSOR_8BIT, 0xA414, 0x00}, + {MISENSOR_8BIT, 0xA415, 0x00}, + {MISENSOR_8BIT, 0xA416, 0x00}, + {MISENSOR_8BIT, 0xA417, 0x00}, + {MISENSOR_8BIT, 0xA418, 0x00}, + {MISENSOR_8BIT, 0xA419, 0x00}, + {MISENSOR_8BIT, 0xA41A, 0x00}, + {MISENSOR_8BIT, 0xA41B, 0x00}, + {MISENSOR_8BIT, 0xA41C, 0x00}, + {MISENSOR_8BIT, 0xA41D, 0x00}, + {MISENSOR_8BIT, 0xA41E, 0x00}, + {MISENSOR_8BIT, 0xA41F, 0x00}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_exp_center[] = { + {MISENSOR_8BIT, 0xA407, 0x19}, + {MISENSOR_8BIT, 0xA408, 0x19}, + {MISENSOR_8BIT, 0xA409, 0x19}, + {MISENSOR_8BIT, 0xA40A, 0x19}, + {MISENSOR_8BIT, 0xA40B, 0x19}, + {MISENSOR_8BIT, 0xA40C, 0x19}, + {MISENSOR_8BIT, 0xA40D, 0x4B}, + {MISENSOR_8BIT, 0xA40E, 0x4B}, + {MISENSOR_8BIT, 0xA40F, 0x4B}, + {MISENSOR_8BIT, 0xA410, 0x19}, + {MISENSOR_8BIT, 0xA411, 0x19}, + {MISENSOR_8BIT, 0xA412, 0x4B}, + {MISENSOR_8BIT, 0xA413, 0x64}, + {MISENSOR_8BIT, 0xA414, 0x4B}, + {MISENSOR_8BIT, 0xA415, 0x19}, + {MISENSOR_8BIT, 0xA416, 0x19}, + {MISENSOR_8BIT, 0xA417, 0x4B}, + {MISENSOR_8BIT, 0xA418, 0x4B}, + {MISENSOR_8BIT, 0xA419, 0x4B}, + {MISENSOR_8BIT, 0xA41A, 0x19}, + {MISENSOR_8BIT, 0xA41B, 0x19}, + {MISENSOR_8BIT, 0xA41C, 0x19}, + {MISENSOR_8BIT, 0xA41D, 0x19}, + {MISENSOR_8BIT, 0xA41E, 0x19}, + {MISENSOR_8BIT, 0xA41F, 0x19}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +#if 0 /* Currently unused */ +static struct misensor_reg const mt9m114_suspend[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x40}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_streaming[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x34}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; +#endif + +static struct misensor_reg const mt9m114_standby_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x50}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +#if 0 /* Currently unused */ +static struct misensor_reg const mt9m114_wakeup_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x54}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; +#endif + +static struct misensor_reg const mt9m114_chgstat_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x976_30fps] - Intel */ +#if 0 +static struct misensor_reg const mt9m114_960P_init[] = { + {MISENSOR_16BIT, 0x098E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x03CF}, /* cam_sensor_cfg_y_addr_end = 971 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1291 */ + {MISENSOR_16BIT, 0xC808, 0x02DC}, /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_16BIT, 0xC80A, 0x6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* cam_sensor_cfg_frame_length_lines = 1006 */ + {MISENSOR_16BIT, 0xC812, 0x03F6}, + /* cam_sensor_cfg_line_length_pck = 1590 */ + {MISENSOR_16BIT, 0xC814, 0x063E}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 963 */ + {MISENSOR_16BIT, 0xC818, 0x03C3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1280 */ + {MISENSOR_16BIT, 0xC85A, 0x03C8}, /* cam_crop_window_height = 960 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1280 */ + {MISENSOR_16BIT, 0xC86A, 0x03C8}, /* cam_output_height = 960 */ + {MISENSOR_TOK_TERM, 0, 0}, +}; +#endif + +/* [1296x976_30fps_768Mbps] */ +static struct misensor_reg const mt9m114_976P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x03CF}, /* cam_sensor_cfg_y_addr_end = 975 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00},/* cam_sensor_cfg_pixclk = 480000*/ + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 1006 */ + {MISENSOR_16BIT, 0xC812, 0x03E5}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1590 */ + {MISENSOR_16BIT, 0xC814, 0x0644}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 963 */ + {MISENSOR_16BIT, 0xC818, 0x03C3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x03C8}, /* cam_crop_window_height = 968 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x03C8}, /* cam_output_height = 968 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x864_30fps] */ +static struct misensor_reg const mt9m114_864P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0038}, /* cam_sensor_cfg_y_addr_start = 56 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x0397}, /* cam_sensor_cfg_y_addr_end = 919 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* cam_sensor_cfg_fine_integ_time_max = 1469 */ + {MISENSOR_16BIT, 0xC810, 0x05BD}, + /* cam_sensor_cfg_frame_length_lines = 1000 */ + {MISENSOR_16BIT, 0xC812, 0x03E8}, + /* cam_sensor_cfg_line_length_pck = 1600 */ + {MISENSOR_16BIT, 0xC814, 0x0640}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 859 */ + {MISENSOR_16BIT, 0xC818, 0x035B}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x0358}, /* cam_crop_window_height = 856 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x0358}, /* cam_output_height = 856 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x736_30fps] */ +static struct misensor_reg const mt9m114_736P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x011F}, /* cam_sysctl_pll_divider_m_n = 287 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0078}, /* cam_sensor_cfg_y_addr_start = 120*/ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x0357}, /* cam_sensor_cfg_y_addr_end = 855 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + {MISENSOR_32BIT, 0xC808, 0x237A07F}, /* cam_sensor_cfg_pixclk=37199999*/ + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1469 */ + {MISENSOR_16BIT, 0xC810, 0x05BD}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 775 */ + {MISENSOR_16BIT, 0xC812, 0x0307}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1600 */ + {MISENSOR_16BIT, 0xC814, 0x0640}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 731 */ + {MISENSOR_16BIT, 0xC818, 0x02DB}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x02D8}, /* cam_crop_window_height = 728 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x02D8}, /* cam_output_height = 728 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [736x496_30fps_768Mbps] */ +#if 0 /* Currently unused */ +static struct misensor_reg const mt9m114_720_480P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x00F0}, /* cam_sensor_cfg_y_addr_start = 240*/ + {MISENSOR_16BIT, 0xC802, 0x0118}, /* cam_sensor_cfg_x_addr_start = 280*/ + {MISENSOR_16BIT, 0xC804, 0x02DF}, /* cam_sensor_cfg_y_addr_end = 735 */ + {MISENSOR_16BIT, 0xC806, 0x03F7}, /* cam_sensor_cfg_x_addr_end = 1015 */ + /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 997 */ + {MISENSOR_16BIT, 0xC812, 0x03E5}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1604 */ + {MISENSOR_16BIT, 0xC814, 0x0644}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + {MISENSOR_16BIT, 0xC818, 0x03C3}, /* cam_sensor_cfg_cpipe_last_row=963*/ + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0*/ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x02D8}, /* cam_crop_window_width = 728 */ + {MISENSOR_16BIT, 0xC85A, 0x01E8}, /* cam_crop_window_height = 488 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x02D8}, /* cam_output_width = 728 */ + {MISENSOR_16BIT, 0xC86A, 0x01E8}, /* cam_output_height = 488 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; +#endif + +static struct misensor_reg const mt9m114_common[] = { + /* reset */ + {MISENSOR_16BIT, 0x301A, 0x0234}, + /* LOAD = Step2-PLL_Timing //PLL and Timing */ + {MISENSOR_16BIT, 0x098E, 0x1000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 216*/ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 168*/ + {MISENSOR_16BIT, 0xC804, 0x03CD}, /* cam_sensor_cfg_y_addr_end = 761 */ + {MISENSOR_16BIT, 0xC806, 0x050D}, /* cam_sensor_cfg_x_addr_end = 1127 */ + {MISENSOR_16BIT, 0xC808, 0x02DC}, /* cam_sensor_cfg_pixclk = 24000000 */ + {MISENSOR_16BIT, 0xC80A, 0x6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x01C3}, + /* cam_sensor_cfg_fine_integ_time_max = 1149 */ + {MISENSOR_16BIT, 0xC810, 0x03F7}, + /* cam_sensor_cfg_frame_length_lines = 625 */ + {MISENSOR_16BIT, 0xC812, 0x0500}, + /* cam_sensor_cfg_line_length_pck = 1280 */ + {MISENSOR_16BIT, 0xC814, 0x04E2}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x00E0}, + /* cam_sensor_cfg_cpipe_last_row = 541 */ + {MISENSOR_16BIT, 0xC818, 0x01E3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0330}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0280}, /* cam_crop_window_width = 952 */ + {MISENSOR_16BIT, 0xC85A, 0x01E0}, /* cam_crop_window_height = 538 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0280}, /* cam_output_width = 952 */ + {MISENSOR_16BIT, 0xC86A, 0x01E0}, /* cam_output_height = 538 */ + /* + * LOAD = Step3-Recommended + * Patch, Errata and Sensor optimization Setting + */ + {MISENSOR_16BIT, 0x316A, 0x8270}, /* DAC_TXLO_ROW */ + {MISENSOR_16BIT, 0x316C, 0x8270}, /* DAC_TXLO */ + {MISENSOR_16BIT, 0x3ED0, 0x2305}, /* DAC_LD_4_5 */ + {MISENSOR_16BIT, 0x3ED2, 0x77CF}, /* DAC_LD_6_7 */ + {MISENSOR_16BIT, 0x316E, 0x8202}, /* DAC_ECL */ + {MISENSOR_16BIT, 0x3180, 0x87FF}, /* DELTA_DK_CONTROL */ + {MISENSOR_16BIT, 0x30D4, 0x6080}, /* COLUMN_CORRECTION */ + {MISENSOR_16BIT, 0xA802, 0x0008}, /* AE_TRACK_MODE */ + {MISENSOR_16BIT, 0x3E14, 0xFF39}, /* SAMP_COL_PUP2 */ + {MISENSOR_16BIT, 0x31E0, 0x0003}, /* PIX_DEF_ID */ + /* LOAD = Step8-Features //Ports, special features, etc. */ + {MISENSOR_16BIT, 0x098E, 0x0000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_16BIT, 0x001E, 0x0777}, /* PAD_SLEW */ + {MISENSOR_16BIT, 0x098E, 0x0000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_16BIT, 0xC984, 0x8001}, /* CAM_PORT_OUTPUT_CONTROL */ + {MISENSOR_16BIT, 0xC988, 0x0F00}, /* CAM_PORT_MIPI_TIMING_T_HS_ZERO */ + /* CAM_PORT_MIPI_TIMING_T_HS_EXIT_HS_TRAIL */ + {MISENSOR_16BIT, 0xC98A, 0x0B07}, + /* CAM_PORT_MIPI_TIMING_T_CLK_POST_CLK_PRE */ + {MISENSOR_16BIT, 0xC98C, 0x0D01}, + /* CAM_PORT_MIPI_TIMING_T_CLK_TRAIL_CLK_ZERO */ + {MISENSOR_16BIT, 0xC98E, 0x071D}, + {MISENSOR_16BIT, 0xC990, 0x0006}, /* CAM_PORT_MIPI_TIMING_T_LPX */ + {MISENSOR_16BIT, 0xC992, 0x0A0C}, /* CAM_PORT_MIPI_TIMING_INIT_TIMING */ + {MISENSOR_16BIT, 0x3C5A, 0x0009}, /* MIPI_DELAY_TRIM */ + {MISENSOR_16BIT, 0xC86C, 0x0210}, /* CAM_OUTPUT_FORMAT */ + {MISENSOR_16BIT, 0xA804, 0x0000}, /* AE_TRACK_ALGO */ + /* default exposure */ + {MISENSOR_16BIT, 0x3012, 0x0110}, /* COMMAND_REGISTER */ + {MISENSOR_TOK_TERM, 0, 0}, + +}; + +#if 0 /* Currently unused */ +static struct misensor_reg const mt9m114_antiflicker_50hz[] = { + {MISENSOR_16BIT, 0x098E, 0xC88B}, + {MISENSOR_8BIT, 0xC88B, 0x32}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_antiflicker_60hz[] = { + {MISENSOR_16BIT, 0x098E, 0xC88B}, + {MISENSOR_8BIT, 0xC88B, 0x3C}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_iq[] = { + /* [Step3-Recommended] [Sensor optimization] */ + {MISENSOR_16BIT, 0x316A, 0x8270}, + {MISENSOR_16BIT, 0x316C, 0x8270}, + {MISENSOR_16BIT, 0x3ED0, 0x2305}, + {MISENSOR_16BIT, 0x3ED2, 0x77CF}, + {MISENSOR_16BIT, 0x316E, 0x8202}, + {MISENSOR_16BIT, 0x3180, 0x87FF}, + {MISENSOR_16BIT, 0x30D4, 0x6080}, + {MISENSOR_16BIT, 0xA802, 0x0008}, + + /* This register is from vender to avoid low light color noise */ + {MISENSOR_16BIT, 0x31E0, 0x0001}, + + /* LOAD=Errata item 1 */ + {MISENSOR_16BIT, 0x3E14, 0xFF39}, + + /* LOAD=Errata item 2 */ + {MISENSOR_16BIT, 0x301A, 0x8234}, + + /* + * LOAD=Errata item 3 + * LOAD=Patch 0202; + * Feature Recommended; Black level correction fix + */ + {MISENSOR_16BIT, 0x0982, 0x0001}, + {MISENSOR_16BIT, 0x098A, 0x5000}, + {MISENSOR_16BIT, 0xD000, 0x70CF}, + {MISENSOR_16BIT, 0xD002, 0xFFFF}, + {MISENSOR_16BIT, 0xD004, 0xC5D4}, + {MISENSOR_16BIT, 0xD006, 0x903A}, + {MISENSOR_16BIT, 0xD008, 0x2144}, + {MISENSOR_16BIT, 0xD00A, 0x0C00}, + {MISENSOR_16BIT, 0xD00C, 0x2186}, + {MISENSOR_16BIT, 0xD00E, 0x0FF3}, + {MISENSOR_16BIT, 0xD010, 0xB844}, + {MISENSOR_16BIT, 0xD012, 0xB948}, + {MISENSOR_16BIT, 0xD014, 0xE082}, + {MISENSOR_16BIT, 0xD016, 0x20CC}, + {MISENSOR_16BIT, 0xD018, 0x80E2}, + {MISENSOR_16BIT, 0xD01A, 0x21CC}, + {MISENSOR_16BIT, 0xD01C, 0x80A2}, + {MISENSOR_16BIT, 0xD01E, 0x21CC}, + {MISENSOR_16BIT, 0xD020, 0x80E2}, + {MISENSOR_16BIT, 0xD022, 0xF404}, + {MISENSOR_16BIT, 0xD024, 0xD801}, + {MISENSOR_16BIT, 0xD026, 0xF003}, + {MISENSOR_16BIT, 0xD028, 0xD800}, + {MISENSOR_16BIT, 0xD02A, 0x7EE0}, + {MISENSOR_16BIT, 0xD02C, 0xC0F1}, + {MISENSOR_16BIT, 0xD02E, 0x08BA}, + + {MISENSOR_16BIT, 0xD030, 0x0600}, + {MISENSOR_16BIT, 0xD032, 0xC1A1}, + {MISENSOR_16BIT, 0xD034, 0x76CF}, + {MISENSOR_16BIT, 0xD036, 0xFFFF}, + {MISENSOR_16BIT, 0xD038, 0xC130}, + {MISENSOR_16BIT, 0xD03A, 0x6E04}, + {MISENSOR_16BIT, 0xD03C, 0xC040}, + {MISENSOR_16BIT, 0xD03E, 0x71CF}, + {MISENSOR_16BIT, 0xD040, 0xFFFF}, + {MISENSOR_16BIT, 0xD042, 0xC790}, + {MISENSOR_16BIT, 0xD044, 0x8103}, + {MISENSOR_16BIT, 0xD046, 0x77CF}, + {MISENSOR_16BIT, 0xD048, 0xFFFF}, + {MISENSOR_16BIT, 0xD04A, 0xC7C0}, + {MISENSOR_16BIT, 0xD04C, 0xE001}, + {MISENSOR_16BIT, 0xD04E, 0xA103}, + {MISENSOR_16BIT, 0xD050, 0xD800}, + {MISENSOR_16BIT, 0xD052, 0x0C6A}, + {MISENSOR_16BIT, 0xD054, 0x04E0}, + {MISENSOR_16BIT, 0xD056, 0xB89E}, + {MISENSOR_16BIT, 0xD058, 0x7508}, + {MISENSOR_16BIT, 0xD05A, 0x8E1C}, + {MISENSOR_16BIT, 0xD05C, 0x0809}, + {MISENSOR_16BIT, 0xD05E, 0x0191}, + + {MISENSOR_16BIT, 0xD060, 0xD801}, + {MISENSOR_16BIT, 0xD062, 0xAE1D}, + {MISENSOR_16BIT, 0xD064, 0xE580}, + {MISENSOR_16BIT, 0xD066, 0x20CA}, + {MISENSOR_16BIT, 0xD068, 0x0022}, + {MISENSOR_16BIT, 0xD06A, 0x20CF}, + {MISENSOR_16BIT, 0xD06C, 0x0522}, + {MISENSOR_16BIT, 0xD06E, 0x0C5C}, + {MISENSOR_16BIT, 0xD070, 0x04E2}, + {MISENSOR_16BIT, 0xD072, 0x21CA}, + {MISENSOR_16BIT, 0xD074, 0x0062}, + {MISENSOR_16BIT, 0xD076, 0xE580}, + {MISENSOR_16BIT, 0xD078, 0xD901}, + {MISENSOR_16BIT, 0xD07A, 0x79C0}, + {MISENSOR_16BIT, 0xD07C, 0xD800}, + {MISENSOR_16BIT, 0xD07E, 0x0BE6}, + {MISENSOR_16BIT, 0xD080, 0x04E0}, + {MISENSOR_16BIT, 0xD082, 0xB89E}, + {MISENSOR_16BIT, 0xD084, 0x70CF}, + {MISENSOR_16BIT, 0xD086, 0xFFFF}, + {MISENSOR_16BIT, 0xD088, 0xC8D4}, + {MISENSOR_16BIT, 0xD08A, 0x9002}, + {MISENSOR_16BIT, 0xD08C, 0x0857}, + {MISENSOR_16BIT, 0xD08E, 0x025E}, + + {MISENSOR_16BIT, 0xD090, 0xFFDC}, + {MISENSOR_16BIT, 0xD092, 0xE080}, + {MISENSOR_16BIT, 0xD094, 0x25CC}, + {MISENSOR_16BIT, 0xD096, 0x9022}, + {MISENSOR_16BIT, 0xD098, 0xF225}, + {MISENSOR_16BIT, 0xD09A, 0x1700}, + {MISENSOR_16BIT, 0xD09C, 0x108A}, + {MISENSOR_16BIT, 0xD09E, 0x73CF}, + {MISENSOR_16BIT, 0xD0A0, 0xFF00}, + {MISENSOR_16BIT, 0xD0A2, 0x3174}, + {MISENSOR_16BIT, 0xD0A4, 0x9307}, + {MISENSOR_16BIT, 0xD0A6, 0x2A04}, + {MISENSOR_16BIT, 0xD0A8, 0x103E}, + {MISENSOR_16BIT, 0xD0AA, 0x9328}, + {MISENSOR_16BIT, 0xD0AC, 0x2942}, + {MISENSOR_16BIT, 0xD0AE, 0x7140}, + {MISENSOR_16BIT, 0xD0B0, 0x2A04}, + {MISENSOR_16BIT, 0xD0B2, 0x107E}, + {MISENSOR_16BIT, 0xD0B4, 0x9349}, + {MISENSOR_16BIT, 0xD0B6, 0x2942}, + {MISENSOR_16BIT, 0xD0B8, 0x7141}, + {MISENSOR_16BIT, 0xD0BA, 0x2A04}, + {MISENSOR_16BIT, 0xD0BC, 0x10BE}, + {MISENSOR_16BIT, 0xD0BE, 0x934A}, + + {MISENSOR_16BIT, 0xD0C0, 0x2942}, + {MISENSOR_16BIT, 0xD0C2, 0x714B}, + {MISENSOR_16BIT, 0xD0C4, 0x2A04}, + {MISENSOR_16BIT, 0xD0C6, 0x10BE}, + {MISENSOR_16BIT, 0xD0C8, 0x130C}, + {MISENSOR_16BIT, 0xD0CA, 0x010A}, + {MISENSOR_16BIT, 0xD0CC, 0x2942}, + {MISENSOR_16BIT, 0xD0CE, 0x7142}, + {MISENSOR_16BIT, 0xD0D0, 0x2250}, + {MISENSOR_16BIT, 0xD0D2, 0x13CA}, + {MISENSOR_16BIT, 0xD0D4, 0x1B0C}, + {MISENSOR_16BIT, 0xD0D6, 0x0284}, + {MISENSOR_16BIT, 0xD0D8, 0xB307}, + {MISENSOR_16BIT, 0xD0DA, 0xB328}, + {MISENSOR_16BIT, 0xD0DC, 0x1B12}, + {MISENSOR_16BIT, 0xD0DE, 0x02C4}, + {MISENSOR_16BIT, 0xD0E0, 0xB34A}, + {MISENSOR_16BIT, 0xD0E2, 0xED88}, + {MISENSOR_16BIT, 0xD0E4, 0x71CF}, + {MISENSOR_16BIT, 0xD0E6, 0xFF00}, + {MISENSOR_16BIT, 0xD0E8, 0x3174}, + {MISENSOR_16BIT, 0xD0EA, 0x9106}, + {MISENSOR_16BIT, 0xD0EC, 0xB88F}, + {MISENSOR_16BIT, 0xD0EE, 0xB106}, + + {MISENSOR_16BIT, 0xD0F0, 0x210A}, + {MISENSOR_16BIT, 0xD0F2, 0x8340}, + {MISENSOR_16BIT, 0xD0F4, 0xC000}, + {MISENSOR_16BIT, 0xD0F6, 0x21CA}, + {MISENSOR_16BIT, 0xD0F8, 0x0062}, + {MISENSOR_16BIT, 0xD0FA, 0x20F0}, + {MISENSOR_16BIT, 0xD0FC, 0x0040}, + {MISENSOR_16BIT, 0xD0FE, 0x0B02}, + {MISENSOR_16BIT, 0xD100, 0x0320}, + {MISENSOR_16BIT, 0xD102, 0xD901}, + {MISENSOR_16BIT, 0xD104, 0x07F1}, + {MISENSOR_16BIT, 0xD106, 0x05E0}, + {MISENSOR_16BIT, 0xD108, 0xC0A1}, + {MISENSOR_16BIT, 0xD10A, 0x78E0}, + {MISENSOR_16BIT, 0xD10C, 0xC0F1}, + {MISENSOR_16BIT, 0xD10E, 0x71CF}, + {MISENSOR_16BIT, 0xD110, 0xFFFF}, + {MISENSOR_16BIT, 0xD112, 0xC7C0}, + {MISENSOR_16BIT, 0xD114, 0xD840}, + {MISENSOR_16BIT, 0xD116, 0xA900}, + {MISENSOR_16BIT, 0xD118, 0x71CF}, + {MISENSOR_16BIT, 0xD11A, 0xFFFF}, + {MISENSOR_16BIT, 0xD11C, 0xD02C}, + {MISENSOR_16BIT, 0xD11E, 0xD81E}, + + {MISENSOR_16BIT, 0xD120, 0x0A5A}, + {MISENSOR_16BIT, 0xD122, 0x04E0}, + {MISENSOR_16BIT, 0xD124, 0xDA00}, + {MISENSOR_16BIT, 0xD126, 0xD800}, + {MISENSOR_16BIT, 0xD128, 0xC0D1}, + {MISENSOR_16BIT, 0xD12A, 0x7EE0}, + + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xE000, 0x010C}, + {MISENSOR_16BIT, 0xE002, 0x0202}, + {MISENSOR_16BIT, 0xE004, 0x4103}, + {MISENSOR_16BIT, 0xE006, 0x0202}, + {MISENSOR_16BIT, 0x0080, 0xFFF0}, + {MISENSOR_16BIT, 0x0080, 0xFFF1}, + + /* LOAD=Patch 0302; Feature Recommended; Adaptive Sensitivity */ + {MISENSOR_16BIT, 0x0982, 0x0001}, + {MISENSOR_16BIT, 0x098A, 0x512C}, + {MISENSOR_16BIT, 0xD12C, 0x70CF}, + {MISENSOR_16BIT, 0xD12E, 0xFFFF}, + {MISENSOR_16BIT, 0xD130, 0xC5D4}, + {MISENSOR_16BIT, 0xD132, 0x903A}, + {MISENSOR_16BIT, 0xD134, 0x2144}, + {MISENSOR_16BIT, 0xD136, 0x0C00}, + {MISENSOR_16BIT, 0xD138, 0x2186}, + {MISENSOR_16BIT, 0xD13A, 0x0FF3}, + {MISENSOR_16BIT, 0xD13C, 0xB844}, + {MISENSOR_16BIT, 0xD13E, 0x262F}, + {MISENSOR_16BIT, 0xD140, 0xF008}, + {MISENSOR_16BIT, 0xD142, 0xB948}, + {MISENSOR_16BIT, 0xD144, 0x21CC}, + {MISENSOR_16BIT, 0xD146, 0x8021}, + {MISENSOR_16BIT, 0xD148, 0xD801}, + {MISENSOR_16BIT, 0xD14A, 0xF203}, + {MISENSOR_16BIT, 0xD14C, 0xD800}, + {MISENSOR_16BIT, 0xD14E, 0x7EE0}, + {MISENSOR_16BIT, 0xD150, 0xC0F1}, + {MISENSOR_16BIT, 0xD152, 0x71CF}, + {MISENSOR_16BIT, 0xD154, 0xFFFF}, + {MISENSOR_16BIT, 0xD156, 0xC610}, + {MISENSOR_16BIT, 0xD158, 0x910E}, + {MISENSOR_16BIT, 0xD15A, 0x208C}, + {MISENSOR_16BIT, 0xD15C, 0x8014}, + {MISENSOR_16BIT, 0xD15E, 0xF418}, + {MISENSOR_16BIT, 0xD160, 0x910F}, + {MISENSOR_16BIT, 0xD162, 0x208C}, + {MISENSOR_16BIT, 0xD164, 0x800F}, + {MISENSOR_16BIT, 0xD166, 0xF414}, + {MISENSOR_16BIT, 0xD168, 0x9116}, + {MISENSOR_16BIT, 0xD16A, 0x208C}, + {MISENSOR_16BIT, 0xD16C, 0x800A}, + {MISENSOR_16BIT, 0xD16E, 0xF410}, + {MISENSOR_16BIT, 0xD170, 0x9117}, + {MISENSOR_16BIT, 0xD172, 0x208C}, + {MISENSOR_16BIT, 0xD174, 0x8807}, + {MISENSOR_16BIT, 0xD176, 0xF40C}, + {MISENSOR_16BIT, 0xD178, 0x9118}, + {MISENSOR_16BIT, 0xD17A, 0x2086}, + {MISENSOR_16BIT, 0xD17C, 0x0FF3}, + {MISENSOR_16BIT, 0xD17E, 0xB848}, + {MISENSOR_16BIT, 0xD180, 0x080D}, + {MISENSOR_16BIT, 0xD182, 0x0090}, + {MISENSOR_16BIT, 0xD184, 0xFFEA}, + {MISENSOR_16BIT, 0xD186, 0xE081}, + {MISENSOR_16BIT, 0xD188, 0xD801}, + {MISENSOR_16BIT, 0xD18A, 0xF203}, + {MISENSOR_16BIT, 0xD18C, 0xD800}, + {MISENSOR_16BIT, 0xD18E, 0xC0D1}, + {MISENSOR_16BIT, 0xD190, 0x7EE0}, + {MISENSOR_16BIT, 0xD192, 0x78E0}, + {MISENSOR_16BIT, 0xD194, 0xC0F1}, + {MISENSOR_16BIT, 0xD196, 0x71CF}, + {MISENSOR_16BIT, 0xD198, 0xFFFF}, + {MISENSOR_16BIT, 0xD19A, 0xC610}, + {MISENSOR_16BIT, 0xD19C, 0x910E}, + {MISENSOR_16BIT, 0xD19E, 0x208C}, + {MISENSOR_16BIT, 0xD1A0, 0x800A}, + {MISENSOR_16BIT, 0xD1A2, 0xF418}, + {MISENSOR_16BIT, 0xD1A4, 0x910F}, + {MISENSOR_16BIT, 0xD1A6, 0x208C}, + {MISENSOR_16BIT, 0xD1A8, 0x8807}, + {MISENSOR_16BIT, 0xD1AA, 0xF414}, + {MISENSOR_16BIT, 0xD1AC, 0x9116}, + {MISENSOR_16BIT, 0xD1AE, 0x208C}, + {MISENSOR_16BIT, 0xD1B0, 0x800A}, + {MISENSOR_16BIT, 0xD1B2, 0xF410}, + {MISENSOR_16BIT, 0xD1B4, 0x9117}, + {MISENSOR_16BIT, 0xD1B6, 0x208C}, + {MISENSOR_16BIT, 0xD1B8, 0x8807}, + {MISENSOR_16BIT, 0xD1BA, 0xF40C}, + {MISENSOR_16BIT, 0xD1BC, 0x9118}, + {MISENSOR_16BIT, 0xD1BE, 0x2086}, + {MISENSOR_16BIT, 0xD1C0, 0x0FF3}, + {MISENSOR_16BIT, 0xD1C2, 0xB848}, + {MISENSOR_16BIT, 0xD1C4, 0x080D}, + {MISENSOR_16BIT, 0xD1C6, 0x0090}, + {MISENSOR_16BIT, 0xD1C8, 0xFFD9}, + {MISENSOR_16BIT, 0xD1CA, 0xE080}, + {MISENSOR_16BIT, 0xD1CC, 0xD801}, + {MISENSOR_16BIT, 0xD1CE, 0xF203}, + {MISENSOR_16BIT, 0xD1D0, 0xD800}, + {MISENSOR_16BIT, 0xD1D2, 0xF1DF}, + {MISENSOR_16BIT, 0xD1D4, 0x9040}, + {MISENSOR_16BIT, 0xD1D6, 0x71CF}, + {MISENSOR_16BIT, 0xD1D8, 0xFFFF}, + {MISENSOR_16BIT, 0xD1DA, 0xC5D4}, + {MISENSOR_16BIT, 0xD1DC, 0xB15A}, + {MISENSOR_16BIT, 0xD1DE, 0x9041}, + {MISENSOR_16BIT, 0xD1E0, 0x73CF}, + {MISENSOR_16BIT, 0xD1E2, 0xFFFF}, + {MISENSOR_16BIT, 0xD1E4, 0xC7D0}, + {MISENSOR_16BIT, 0xD1E6, 0xB140}, + {MISENSOR_16BIT, 0xD1E8, 0x9042}, + {MISENSOR_16BIT, 0xD1EA, 0xB141}, + {MISENSOR_16BIT, 0xD1EC, 0x9043}, + {MISENSOR_16BIT, 0xD1EE, 0xB142}, + {MISENSOR_16BIT, 0xD1F0, 0x9044}, + {MISENSOR_16BIT, 0xD1F2, 0xB143}, + {MISENSOR_16BIT, 0xD1F4, 0x9045}, + {MISENSOR_16BIT, 0xD1F6, 0xB147}, + {MISENSOR_16BIT, 0xD1F8, 0x9046}, + {MISENSOR_16BIT, 0xD1FA, 0xB148}, + {MISENSOR_16BIT, 0xD1FC, 0x9047}, + {MISENSOR_16BIT, 0xD1FE, 0xB14B}, + {MISENSOR_16BIT, 0xD200, 0x9048}, + {MISENSOR_16BIT, 0xD202, 0xB14C}, + {MISENSOR_16BIT, 0xD204, 0x9049}, + {MISENSOR_16BIT, 0xD206, 0x1958}, + {MISENSOR_16BIT, 0xD208, 0x0084}, + {MISENSOR_16BIT, 0xD20A, 0x904A}, + {MISENSOR_16BIT, 0xD20C, 0x195A}, + {MISENSOR_16BIT, 0xD20E, 0x0084}, + {MISENSOR_16BIT, 0xD210, 0x8856}, + {MISENSOR_16BIT, 0xD212, 0x1B36}, + {MISENSOR_16BIT, 0xD214, 0x8082}, + {MISENSOR_16BIT, 0xD216, 0x8857}, + {MISENSOR_16BIT, 0xD218, 0x1B37}, + {MISENSOR_16BIT, 0xD21A, 0x8082}, + {MISENSOR_16BIT, 0xD21C, 0x904C}, + {MISENSOR_16BIT, 0xD21E, 0x19A7}, + {MISENSOR_16BIT, 0xD220, 0x009C}, + {MISENSOR_16BIT, 0xD222, 0x881A}, + {MISENSOR_16BIT, 0xD224, 0x7FE0}, + {MISENSOR_16BIT, 0xD226, 0x1B54}, + {MISENSOR_16BIT, 0xD228, 0x8002}, + {MISENSOR_16BIT, 0xD22A, 0x78E0}, + {MISENSOR_16BIT, 0xD22C, 0x71CF}, + {MISENSOR_16BIT, 0xD22E, 0xFFFF}, + {MISENSOR_16BIT, 0xD230, 0xC350}, + {MISENSOR_16BIT, 0xD232, 0xD828}, + {MISENSOR_16BIT, 0xD234, 0xA90B}, + {MISENSOR_16BIT, 0xD236, 0x8100}, + {MISENSOR_16BIT, 0xD238, 0x01C5}, + {MISENSOR_16BIT, 0xD23A, 0x0320}, + {MISENSOR_16BIT, 0xD23C, 0xD900}, + {MISENSOR_16BIT, 0xD23E, 0x78E0}, + {MISENSOR_16BIT, 0xD240, 0x220A}, + {MISENSOR_16BIT, 0xD242, 0x1F80}, + {MISENSOR_16BIT, 0xD244, 0xFFFF}, + {MISENSOR_16BIT, 0xD246, 0xD4E0}, + {MISENSOR_16BIT, 0xD248, 0xC0F1}, + {MISENSOR_16BIT, 0xD24A, 0x0811}, + {MISENSOR_16BIT, 0xD24C, 0x0051}, + {MISENSOR_16BIT, 0xD24E, 0x2240}, + {MISENSOR_16BIT, 0xD250, 0x1200}, + {MISENSOR_16BIT, 0xD252, 0xFFE1}, + {MISENSOR_16BIT, 0xD254, 0xD801}, + {MISENSOR_16BIT, 0xD256, 0xF006}, + {MISENSOR_16BIT, 0xD258, 0x2240}, + {MISENSOR_16BIT, 0xD25A, 0x1900}, + {MISENSOR_16BIT, 0xD25C, 0xFFDE}, + {MISENSOR_16BIT, 0xD25E, 0xD802}, + {MISENSOR_16BIT, 0xD260, 0x1A05}, + {MISENSOR_16BIT, 0xD262, 0x1002}, + {MISENSOR_16BIT, 0xD264, 0xFFF2}, + {MISENSOR_16BIT, 0xD266, 0xF195}, + {MISENSOR_16BIT, 0xD268, 0xC0F1}, + {MISENSOR_16BIT, 0xD26A, 0x0E7E}, + {MISENSOR_16BIT, 0xD26C, 0x05C0}, + {MISENSOR_16BIT, 0xD26E, 0x75CF}, + {MISENSOR_16BIT, 0xD270, 0xFFFF}, + {MISENSOR_16BIT, 0xD272, 0xC84C}, + {MISENSOR_16BIT, 0xD274, 0x9502}, + {MISENSOR_16BIT, 0xD276, 0x77CF}, + {MISENSOR_16BIT, 0xD278, 0xFFFF}, + {MISENSOR_16BIT, 0xD27A, 0xC344}, + {MISENSOR_16BIT, 0xD27C, 0x2044}, + {MISENSOR_16BIT, 0xD27E, 0x008E}, + {MISENSOR_16BIT, 0xD280, 0xB8A1}, + {MISENSOR_16BIT, 0xD282, 0x0926}, + {MISENSOR_16BIT, 0xD284, 0x03E0}, + {MISENSOR_16BIT, 0xD286, 0xB502}, + {MISENSOR_16BIT, 0xD288, 0x9502}, + {MISENSOR_16BIT, 0xD28A, 0x952E}, + {MISENSOR_16BIT, 0xD28C, 0x7E05}, + {MISENSOR_16BIT, 0xD28E, 0xB5C2}, + {MISENSOR_16BIT, 0xD290, 0x70CF}, + {MISENSOR_16BIT, 0xD292, 0xFFFF}, + {MISENSOR_16BIT, 0xD294, 0xC610}, + {MISENSOR_16BIT, 0xD296, 0x099A}, + {MISENSOR_16BIT, 0xD298, 0x04A0}, + {MISENSOR_16BIT, 0xD29A, 0xB026}, + {MISENSOR_16BIT, 0xD29C, 0x0E02}, + {MISENSOR_16BIT, 0xD29E, 0x0560}, + {MISENSOR_16BIT, 0xD2A0, 0xDE00}, + {MISENSOR_16BIT, 0xD2A2, 0x0A12}, + {MISENSOR_16BIT, 0xD2A4, 0x0320}, + {MISENSOR_16BIT, 0xD2A6, 0xB7C4}, + {MISENSOR_16BIT, 0xD2A8, 0x0B36}, + {MISENSOR_16BIT, 0xD2AA, 0x03A0}, + {MISENSOR_16BIT, 0xD2AC, 0x70C9}, + {MISENSOR_16BIT, 0xD2AE, 0x9502}, + {MISENSOR_16BIT, 0xD2B0, 0x7608}, + {MISENSOR_16BIT, 0xD2B2, 0xB8A8}, + {MISENSOR_16BIT, 0xD2B4, 0xB502}, + {MISENSOR_16BIT, 0xD2B6, 0x70CF}, + {MISENSOR_16BIT, 0xD2B8, 0x0000}, + {MISENSOR_16BIT, 0xD2BA, 0x5536}, + {MISENSOR_16BIT, 0xD2BC, 0x7860}, + {MISENSOR_16BIT, 0xD2BE, 0x2686}, + {MISENSOR_16BIT, 0xD2C0, 0x1FFB}, + {MISENSOR_16BIT, 0xD2C2, 0x9502}, + {MISENSOR_16BIT, 0xD2C4, 0x78C5}, + {MISENSOR_16BIT, 0xD2C6, 0x0631}, + {MISENSOR_16BIT, 0xD2C8, 0x05E0}, + {MISENSOR_16BIT, 0xD2CA, 0xB502}, + {MISENSOR_16BIT, 0xD2CC, 0x72CF}, + {MISENSOR_16BIT, 0xD2CE, 0xFFFF}, + {MISENSOR_16BIT, 0xD2D0, 0xC5D4}, + {MISENSOR_16BIT, 0xD2D2, 0x923A}, + {MISENSOR_16BIT, 0xD2D4, 0x73CF}, + {MISENSOR_16BIT, 0xD2D6, 0xFFFF}, + {MISENSOR_16BIT, 0xD2D8, 0xC7D0}, + {MISENSOR_16BIT, 0xD2DA, 0xB020}, + {MISENSOR_16BIT, 0xD2DC, 0x9220}, + {MISENSOR_16BIT, 0xD2DE, 0xB021}, + {MISENSOR_16BIT, 0xD2E0, 0x9221}, + {MISENSOR_16BIT, 0xD2E2, 0xB022}, + {MISENSOR_16BIT, 0xD2E4, 0x9222}, + {MISENSOR_16BIT, 0xD2E6, 0xB023}, + {MISENSOR_16BIT, 0xD2E8, 0x9223}, + {MISENSOR_16BIT, 0xD2EA, 0xB024}, + {MISENSOR_16BIT, 0xD2EC, 0x9227}, + {MISENSOR_16BIT, 0xD2EE, 0xB025}, + {MISENSOR_16BIT, 0xD2F0, 0x9228}, + {MISENSOR_16BIT, 0xD2F2, 0xB026}, + {MISENSOR_16BIT, 0xD2F4, 0x922B}, + {MISENSOR_16BIT, 0xD2F6, 0xB027}, + {MISENSOR_16BIT, 0xD2F8, 0x922C}, + {MISENSOR_16BIT, 0xD2FA, 0xB028}, + {MISENSOR_16BIT, 0xD2FC, 0x1258}, + {MISENSOR_16BIT, 0xD2FE, 0x0101}, + {MISENSOR_16BIT, 0xD300, 0xB029}, + {MISENSOR_16BIT, 0xD302, 0x125A}, + {MISENSOR_16BIT, 0xD304, 0x0101}, + {MISENSOR_16BIT, 0xD306, 0xB02A}, + {MISENSOR_16BIT, 0xD308, 0x1336}, + {MISENSOR_16BIT, 0xD30A, 0x8081}, + {MISENSOR_16BIT, 0xD30C, 0xA836}, + {MISENSOR_16BIT, 0xD30E, 0x1337}, + {MISENSOR_16BIT, 0xD310, 0x8081}, + {MISENSOR_16BIT, 0xD312, 0xA837}, + {MISENSOR_16BIT, 0xD314, 0x12A7}, + {MISENSOR_16BIT, 0xD316, 0x0701}, + {MISENSOR_16BIT, 0xD318, 0xB02C}, + {MISENSOR_16BIT, 0xD31A, 0x1354}, + {MISENSOR_16BIT, 0xD31C, 0x8081}, + {MISENSOR_16BIT, 0xD31E, 0x7FE0}, + {MISENSOR_16BIT, 0xD320, 0xA83A}, + {MISENSOR_16BIT, 0xD322, 0x78E0}, + {MISENSOR_16BIT, 0xD324, 0xC0F1}, + {MISENSOR_16BIT, 0xD326, 0x0DC2}, + {MISENSOR_16BIT, 0xD328, 0x05C0}, + {MISENSOR_16BIT, 0xD32A, 0x7608}, + {MISENSOR_16BIT, 0xD32C, 0x09BB}, + {MISENSOR_16BIT, 0xD32E, 0x0010}, + {MISENSOR_16BIT, 0xD330, 0x75CF}, + {MISENSOR_16BIT, 0xD332, 0xFFFF}, + {MISENSOR_16BIT, 0xD334, 0xD4E0}, + {MISENSOR_16BIT, 0xD336, 0x8D21}, + {MISENSOR_16BIT, 0xD338, 0x8D00}, + {MISENSOR_16BIT, 0xD33A, 0x2153}, + {MISENSOR_16BIT, 0xD33C, 0x0003}, + {MISENSOR_16BIT, 0xD33E, 0xB8C0}, + {MISENSOR_16BIT, 0xD340, 0x8D45}, + {MISENSOR_16BIT, 0xD342, 0x0B23}, + {MISENSOR_16BIT, 0xD344, 0x0000}, + {MISENSOR_16BIT, 0xD346, 0xEA8F}, + {MISENSOR_16BIT, 0xD348, 0x0915}, + {MISENSOR_16BIT, 0xD34A, 0x001E}, + {MISENSOR_16BIT, 0xD34C, 0xFF81}, + {MISENSOR_16BIT, 0xD34E, 0xE808}, + {MISENSOR_16BIT, 0xD350, 0x2540}, + {MISENSOR_16BIT, 0xD352, 0x1900}, + {MISENSOR_16BIT, 0xD354, 0xFFDE}, + {MISENSOR_16BIT, 0xD356, 0x8D00}, + {MISENSOR_16BIT, 0xD358, 0xB880}, + {MISENSOR_16BIT, 0xD35A, 0xF004}, + {MISENSOR_16BIT, 0xD35C, 0x8D00}, + {MISENSOR_16BIT, 0xD35E, 0xB8A0}, + {MISENSOR_16BIT, 0xD360, 0xAD00}, + {MISENSOR_16BIT, 0xD362, 0x8D05}, + {MISENSOR_16BIT, 0xD364, 0xE081}, + {MISENSOR_16BIT, 0xD366, 0x20CC}, + {MISENSOR_16BIT, 0xD368, 0x80A2}, + {MISENSOR_16BIT, 0xD36A, 0xDF00}, + {MISENSOR_16BIT, 0xD36C, 0xF40A}, + {MISENSOR_16BIT, 0xD36E, 0x71CF}, + {MISENSOR_16BIT, 0xD370, 0xFFFF}, + {MISENSOR_16BIT, 0xD372, 0xC84C}, + {MISENSOR_16BIT, 0xD374, 0x9102}, + {MISENSOR_16BIT, 0xD376, 0x7708}, + {MISENSOR_16BIT, 0xD378, 0xB8A6}, + {MISENSOR_16BIT, 0xD37A, 0x2786}, + {MISENSOR_16BIT, 0xD37C, 0x1FFE}, + {MISENSOR_16BIT, 0xD37E, 0xB102}, + {MISENSOR_16BIT, 0xD380, 0x0B42}, + {MISENSOR_16BIT, 0xD382, 0x0180}, + {MISENSOR_16BIT, 0xD384, 0x0E3E}, + {MISENSOR_16BIT, 0xD386, 0x0180}, + {MISENSOR_16BIT, 0xD388, 0x0F4A}, + {MISENSOR_16BIT, 0xD38A, 0x0160}, + {MISENSOR_16BIT, 0xD38C, 0x70C9}, + {MISENSOR_16BIT, 0xD38E, 0x8D05}, + {MISENSOR_16BIT, 0xD390, 0xE081}, + {MISENSOR_16BIT, 0xD392, 0x20CC}, + {MISENSOR_16BIT, 0xD394, 0x80A2}, + {MISENSOR_16BIT, 0xD396, 0xF429}, + {MISENSOR_16BIT, 0xD398, 0x76CF}, + {MISENSOR_16BIT, 0xD39A, 0xFFFF}, + {MISENSOR_16BIT, 0xD39C, 0xC84C}, + {MISENSOR_16BIT, 0xD39E, 0x082D}, + {MISENSOR_16BIT, 0xD3A0, 0x0051}, + {MISENSOR_16BIT, 0xD3A2, 0x70CF}, + {MISENSOR_16BIT, 0xD3A4, 0xFFFF}, + {MISENSOR_16BIT, 0xD3A6, 0xC90C}, + {MISENSOR_16BIT, 0xD3A8, 0x8805}, + {MISENSOR_16BIT, 0xD3AA, 0x09B6}, + {MISENSOR_16BIT, 0xD3AC, 0x0360}, + {MISENSOR_16BIT, 0xD3AE, 0xD908}, + {MISENSOR_16BIT, 0xD3B0, 0x2099}, + {MISENSOR_16BIT, 0xD3B2, 0x0802}, + {MISENSOR_16BIT, 0xD3B4, 0x9634}, + {MISENSOR_16BIT, 0xD3B6, 0xB503}, + {MISENSOR_16BIT, 0xD3B8, 0x7902}, + {MISENSOR_16BIT, 0xD3BA, 0x1523}, + {MISENSOR_16BIT, 0xD3BC, 0x1080}, + {MISENSOR_16BIT, 0xD3BE, 0xB634}, + {MISENSOR_16BIT, 0xD3C0, 0xE001}, + {MISENSOR_16BIT, 0xD3C2, 0x1D23}, + {MISENSOR_16BIT, 0xD3C4, 0x1002}, + {MISENSOR_16BIT, 0xD3C6, 0xF00B}, + {MISENSOR_16BIT, 0xD3C8, 0x9634}, + {MISENSOR_16BIT, 0xD3CA, 0x9503}, + {MISENSOR_16BIT, 0xD3CC, 0x6038}, + {MISENSOR_16BIT, 0xD3CE, 0xB614}, + {MISENSOR_16BIT, 0xD3D0, 0x153F}, + {MISENSOR_16BIT, 0xD3D2, 0x1080}, + {MISENSOR_16BIT, 0xD3D4, 0xE001}, + {MISENSOR_16BIT, 0xD3D6, 0x1D3F}, + {MISENSOR_16BIT, 0xD3D8, 0x1002}, + {MISENSOR_16BIT, 0xD3DA, 0xFFA4}, + {MISENSOR_16BIT, 0xD3DC, 0x9602}, + {MISENSOR_16BIT, 0xD3DE, 0x7F05}, + {MISENSOR_16BIT, 0xD3E0, 0xD800}, + {MISENSOR_16BIT, 0xD3E2, 0xB6E2}, + {MISENSOR_16BIT, 0xD3E4, 0xAD05}, + {MISENSOR_16BIT, 0xD3E6, 0x0511}, + {MISENSOR_16BIT, 0xD3E8, 0x05E0}, + {MISENSOR_16BIT, 0xD3EA, 0xD800}, + {MISENSOR_16BIT, 0xD3EC, 0xC0F1}, + {MISENSOR_16BIT, 0xD3EE, 0x0CFE}, + {MISENSOR_16BIT, 0xD3F0, 0x05C0}, + {MISENSOR_16BIT, 0xD3F2, 0x0A96}, + {MISENSOR_16BIT, 0xD3F4, 0x05A0}, + {MISENSOR_16BIT, 0xD3F6, 0x7608}, + {MISENSOR_16BIT, 0xD3F8, 0x0C22}, + {MISENSOR_16BIT, 0xD3FA, 0x0240}, + {MISENSOR_16BIT, 0xD3FC, 0xE080}, + {MISENSOR_16BIT, 0xD3FE, 0x20CA}, + {MISENSOR_16BIT, 0xD400, 0x0F82}, + {MISENSOR_16BIT, 0xD402, 0x0000}, + {MISENSOR_16BIT, 0xD404, 0x190B}, + {MISENSOR_16BIT, 0xD406, 0x0C60}, + {MISENSOR_16BIT, 0xD408, 0x05A2}, + {MISENSOR_16BIT, 0xD40A, 0x21CA}, + {MISENSOR_16BIT, 0xD40C, 0x0022}, + {MISENSOR_16BIT, 0xD40E, 0x0C56}, + {MISENSOR_16BIT, 0xD410, 0x0240}, + {MISENSOR_16BIT, 0xD412, 0xE806}, + {MISENSOR_16BIT, 0xD414, 0x0E0E}, + {MISENSOR_16BIT, 0xD416, 0x0220}, + {MISENSOR_16BIT, 0xD418, 0x70C9}, + {MISENSOR_16BIT, 0xD41A, 0xF048}, + {MISENSOR_16BIT, 0xD41C, 0x0896}, + {MISENSOR_16BIT, 0xD41E, 0x0440}, + {MISENSOR_16BIT, 0xD420, 0x0E96}, + {MISENSOR_16BIT, 0xD422, 0x0400}, + {MISENSOR_16BIT, 0xD424, 0x0966}, + {MISENSOR_16BIT, 0xD426, 0x0380}, + {MISENSOR_16BIT, 0xD428, 0x75CF}, + {MISENSOR_16BIT, 0xD42A, 0xFFFF}, + {MISENSOR_16BIT, 0xD42C, 0xD4E0}, + {MISENSOR_16BIT, 0xD42E, 0x8D00}, + {MISENSOR_16BIT, 0xD430, 0x084D}, + {MISENSOR_16BIT, 0xD432, 0x001E}, + {MISENSOR_16BIT, 0xD434, 0xFF47}, + {MISENSOR_16BIT, 0xD436, 0x080D}, + {MISENSOR_16BIT, 0xD438, 0x0050}, + {MISENSOR_16BIT, 0xD43A, 0xFF57}, + {MISENSOR_16BIT, 0xD43C, 0x0841}, + {MISENSOR_16BIT, 0xD43E, 0x0051}, + {MISENSOR_16BIT, 0xD440, 0x8D04}, + {MISENSOR_16BIT, 0xD442, 0x9521}, + {MISENSOR_16BIT, 0xD444, 0xE064}, + {MISENSOR_16BIT, 0xD446, 0x790C}, + {MISENSOR_16BIT, 0xD448, 0x702F}, + {MISENSOR_16BIT, 0xD44A, 0x0CE2}, + {MISENSOR_16BIT, 0xD44C, 0x05E0}, + {MISENSOR_16BIT, 0xD44E, 0xD964}, + {MISENSOR_16BIT, 0xD450, 0x72CF}, + {MISENSOR_16BIT, 0xD452, 0xFFFF}, + {MISENSOR_16BIT, 0xD454, 0xC700}, + {MISENSOR_16BIT, 0xD456, 0x9235}, + {MISENSOR_16BIT, 0xD458, 0x0811}, + {MISENSOR_16BIT, 0xD45A, 0x0043}, + {MISENSOR_16BIT, 0xD45C, 0xFF3D}, + {MISENSOR_16BIT, 0xD45E, 0x080D}, + {MISENSOR_16BIT, 0xD460, 0x0051}, + {MISENSOR_16BIT, 0xD462, 0xD801}, + {MISENSOR_16BIT, 0xD464, 0xFF77}, + {MISENSOR_16BIT, 0xD466, 0xF025}, + {MISENSOR_16BIT, 0xD468, 0x9501}, + {MISENSOR_16BIT, 0xD46A, 0x9235}, + {MISENSOR_16BIT, 0xD46C, 0x0911}, + {MISENSOR_16BIT, 0xD46E, 0x0003}, + {MISENSOR_16BIT, 0xD470, 0xFF49}, + {MISENSOR_16BIT, 0xD472, 0x080D}, + {MISENSOR_16BIT, 0xD474, 0x0051}, + {MISENSOR_16BIT, 0xD476, 0xD800}, + {MISENSOR_16BIT, 0xD478, 0xFF72}, + {MISENSOR_16BIT, 0xD47A, 0xF01B}, + {MISENSOR_16BIT, 0xD47C, 0x0886}, + {MISENSOR_16BIT, 0xD47E, 0x03E0}, + {MISENSOR_16BIT, 0xD480, 0xD801}, + {MISENSOR_16BIT, 0xD482, 0x0EF6}, + {MISENSOR_16BIT, 0xD484, 0x03C0}, + {MISENSOR_16BIT, 0xD486, 0x0F52}, + {MISENSOR_16BIT, 0xD488, 0x0340}, + {MISENSOR_16BIT, 0xD48A, 0x0DBA}, + {MISENSOR_16BIT, 0xD48C, 0x0200}, + {MISENSOR_16BIT, 0xD48E, 0x0AF6}, + {MISENSOR_16BIT, 0xD490, 0x0440}, + {MISENSOR_16BIT, 0xD492, 0x0C22}, + {MISENSOR_16BIT, 0xD494, 0x0400}, + {MISENSOR_16BIT, 0xD496, 0x0D72}, + {MISENSOR_16BIT, 0xD498, 0x0440}, + {MISENSOR_16BIT, 0xD49A, 0x0DC2}, + {MISENSOR_16BIT, 0xD49C, 0x0200}, + {MISENSOR_16BIT, 0xD49E, 0x0972}, + {MISENSOR_16BIT, 0xD4A0, 0x0440}, + {MISENSOR_16BIT, 0xD4A2, 0x0D3A}, + {MISENSOR_16BIT, 0xD4A4, 0x0220}, + {MISENSOR_16BIT, 0xD4A6, 0xD820}, + {MISENSOR_16BIT, 0xD4A8, 0x0BFA}, + {MISENSOR_16BIT, 0xD4AA, 0x0260}, + {MISENSOR_16BIT, 0xD4AC, 0x70C9}, + {MISENSOR_16BIT, 0xD4AE, 0x0451}, + {MISENSOR_16BIT, 0xD4B0, 0x05C0}, + {MISENSOR_16BIT, 0xD4B2, 0x78E0}, + {MISENSOR_16BIT, 0xD4B4, 0xD900}, + {MISENSOR_16BIT, 0xD4B6, 0xF00A}, + {MISENSOR_16BIT, 0xD4B8, 0x70CF}, + {MISENSOR_16BIT, 0xD4BA, 0xFFFF}, + {MISENSOR_16BIT, 0xD4BC, 0xD520}, + {MISENSOR_16BIT, 0xD4BE, 0x7835}, + {MISENSOR_16BIT, 0xD4C0, 0x8041}, + {MISENSOR_16BIT, 0xD4C2, 0x8000}, + {MISENSOR_16BIT, 0xD4C4, 0xE102}, + {MISENSOR_16BIT, 0xD4C6, 0xA040}, + {MISENSOR_16BIT, 0xD4C8, 0x09F1}, + {MISENSOR_16BIT, 0xD4CA, 0x8114}, + {MISENSOR_16BIT, 0xD4CC, 0x71CF}, + {MISENSOR_16BIT, 0xD4CE, 0xFFFF}, + {MISENSOR_16BIT, 0xD4D0, 0xD4E0}, + {MISENSOR_16BIT, 0xD4D2, 0x70CF}, + {MISENSOR_16BIT, 0xD4D4, 0xFFFF}, + {MISENSOR_16BIT, 0xD4D6, 0xC594}, + {MISENSOR_16BIT, 0xD4D8, 0xB03A}, + {MISENSOR_16BIT, 0xD4DA, 0x7FE0}, + {MISENSOR_16BIT, 0xD4DC, 0xD800}, + {MISENSOR_16BIT, 0xD4DE, 0x0000}, + {MISENSOR_16BIT, 0xD4E0, 0x0000}, + {MISENSOR_16BIT, 0xD4E2, 0x0500}, + {MISENSOR_16BIT, 0xD4E4, 0x0500}, + {MISENSOR_16BIT, 0xD4E6, 0x0200}, + {MISENSOR_16BIT, 0xD4E8, 0x0330}, + {MISENSOR_16BIT, 0xD4EA, 0x0000}, + {MISENSOR_16BIT, 0xD4EC, 0x0000}, + {MISENSOR_16BIT, 0xD4EE, 0x03CD}, + {MISENSOR_16BIT, 0xD4F0, 0x050D}, + {MISENSOR_16BIT, 0xD4F2, 0x01C5}, + {MISENSOR_16BIT, 0xD4F4, 0x03B3}, + {MISENSOR_16BIT, 0xD4F6, 0x00E0}, + {MISENSOR_16BIT, 0xD4F8, 0x01E3}, + {MISENSOR_16BIT, 0xD4FA, 0x0280}, + {MISENSOR_16BIT, 0xD4FC, 0x01E0}, + {MISENSOR_16BIT, 0xD4FE, 0x0109}, + {MISENSOR_16BIT, 0xD500, 0x0080}, + {MISENSOR_16BIT, 0xD502, 0x0500}, + {MISENSOR_16BIT, 0xD504, 0x0000}, + {MISENSOR_16BIT, 0xD506, 0x0000}, + {MISENSOR_16BIT, 0xD508, 0x0000}, + {MISENSOR_16BIT, 0xD50A, 0x0000}, + {MISENSOR_16BIT, 0xD50C, 0x0000}, + {MISENSOR_16BIT, 0xD50E, 0x0000}, + {MISENSOR_16BIT, 0xD510, 0x0000}, + {MISENSOR_16BIT, 0xD512, 0x0000}, + {MISENSOR_16BIT, 0xD514, 0x0000}, + {MISENSOR_16BIT, 0xD516, 0x0000}, + {MISENSOR_16BIT, 0xD518, 0x0000}, + {MISENSOR_16BIT, 0xD51A, 0x0000}, + {MISENSOR_16BIT, 0xD51C, 0x0000}, + {MISENSOR_16BIT, 0xD51E, 0x0000}, + {MISENSOR_16BIT, 0xD520, 0xFFFF}, + {MISENSOR_16BIT, 0xD522, 0xC9B4}, + {MISENSOR_16BIT, 0xD524, 0xFFFF}, + {MISENSOR_16BIT, 0xD526, 0xD324}, + {MISENSOR_16BIT, 0xD528, 0xFFFF}, + {MISENSOR_16BIT, 0xD52A, 0xCA34}, + {MISENSOR_16BIT, 0xD52C, 0xFFFF}, + {MISENSOR_16BIT, 0xD52E, 0xD3EC}, + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xE000, 0x04B4}, + {MISENSOR_16BIT, 0xE002, 0x0302}, + {MISENSOR_16BIT, 0xE004, 0x4103}, + {MISENSOR_16BIT, 0xE006, 0x0202}, + {MISENSOR_16BIT, 0x0080, 0xFFF0}, + {MISENSOR_16BIT, 0x0080, 0xFFF1}, + + /* PGA parameter and APGA + * [Step4-APGA] [TP101_MT9M114_APGA] + */ + {MISENSOR_16BIT, 0x098E, 0x495E}, + {MISENSOR_16BIT, 0xC95E, 0x0000}, + {MISENSOR_16BIT, 0x3640, 0x02B0}, + {MISENSOR_16BIT, 0x3642, 0x8063}, + {MISENSOR_16BIT, 0x3644, 0x78D0}, + {MISENSOR_16BIT, 0x3646, 0x50CC}, + {MISENSOR_16BIT, 0x3648, 0x3511}, + {MISENSOR_16BIT, 0x364A, 0x0110}, + {MISENSOR_16BIT, 0x364C, 0xBD8A}, + {MISENSOR_16BIT, 0x364E, 0x0CD1}, + {MISENSOR_16BIT, 0x3650, 0x24ED}, + {MISENSOR_16BIT, 0x3652, 0x7C11}, + {MISENSOR_16BIT, 0x3654, 0x0150}, + {MISENSOR_16BIT, 0x3656, 0x124C}, + {MISENSOR_16BIT, 0x3658, 0x3130}, + {MISENSOR_16BIT, 0x365A, 0x508C}, + {MISENSOR_16BIT, 0x365C, 0x21F1}, + {MISENSOR_16BIT, 0x365E, 0x0090}, + {MISENSOR_16BIT, 0x3660, 0xBFCA}, + {MISENSOR_16BIT, 0x3662, 0x0A11}, + {MISENSOR_16BIT, 0x3664, 0x4F4B}, + {MISENSOR_16BIT, 0x3666, 0x28B1}, + {MISENSOR_16BIT, 0x3680, 0x50A9}, + {MISENSOR_16BIT, 0x3682, 0xA04B}, + {MISENSOR_16BIT, 0x3684, 0x0E2D}, + {MISENSOR_16BIT, 0x3686, 0x73EC}, + {MISENSOR_16BIT, 0x3688, 0x164F}, + {MISENSOR_16BIT, 0x368A, 0xF829}, + {MISENSOR_16BIT, 0x368C, 0xC1A8}, + {MISENSOR_16BIT, 0x368E, 0xB0EC}, + {MISENSOR_16BIT, 0x3690, 0xE76A}, + {MISENSOR_16BIT, 0x3692, 0x69AF}, + {MISENSOR_16BIT, 0x3694, 0x378C}, + {MISENSOR_16BIT, 0x3696, 0xA70D}, + {MISENSOR_16BIT, 0x3698, 0x884F}, + {MISENSOR_16BIT, 0x369A, 0xEE8B}, + {MISENSOR_16BIT, 0x369C, 0x5DEF}, + {MISENSOR_16BIT, 0x369E, 0x27CC}, + {MISENSOR_16BIT, 0x36A0, 0xCAAC}, + {MISENSOR_16BIT, 0x36A2, 0x840E}, + {MISENSOR_16BIT, 0x36A4, 0xDAA9}, + {MISENSOR_16BIT, 0x36A6, 0xF00C}, + {MISENSOR_16BIT, 0x36C0, 0x1371}, + {MISENSOR_16BIT, 0x36C2, 0x272F}, + {MISENSOR_16BIT, 0x36C4, 0x2293}, + {MISENSOR_16BIT, 0x36C6, 0xE6D0}, + {MISENSOR_16BIT, 0x36C8, 0xEC32}, + {MISENSOR_16BIT, 0x36CA, 0x11B1}, + {MISENSOR_16BIT, 0x36CC, 0x7BAF}, + {MISENSOR_16BIT, 0x36CE, 0x5813}, + {MISENSOR_16BIT, 0x36D0, 0xB871}, + {MISENSOR_16BIT, 0x36D2, 0x8913}, + {MISENSOR_16BIT, 0x36D4, 0x4610}, + {MISENSOR_16BIT, 0x36D6, 0x7EEE}, + {MISENSOR_16BIT, 0x36D8, 0x0DF3}, + {MISENSOR_16BIT, 0x36DA, 0xB84F}, + {MISENSOR_16BIT, 0x36DC, 0xB532}, + {MISENSOR_16BIT, 0x36DE, 0x1171}, + {MISENSOR_16BIT, 0x36E0, 0x13CF}, + {MISENSOR_16BIT, 0x36E2, 0x22F3}, + {MISENSOR_16BIT, 0x36E4, 0xE090}, + {MISENSOR_16BIT, 0x36E6, 0x8133}, + {MISENSOR_16BIT, 0x3700, 0x88AE}, + {MISENSOR_16BIT, 0x3702, 0x00EA}, + {MISENSOR_16BIT, 0x3704, 0x344F}, + {MISENSOR_16BIT, 0x3706, 0xEC88}, + {MISENSOR_16BIT, 0x3708, 0x3E91}, + {MISENSOR_16BIT, 0x370A, 0xF12D}, + {MISENSOR_16BIT, 0x370C, 0xB0EF}, + {MISENSOR_16BIT, 0x370E, 0x77CD}, + {MISENSOR_16BIT, 0x3710, 0x7930}, + {MISENSOR_16BIT, 0x3712, 0x5C12}, + {MISENSOR_16BIT, 0x3714, 0x500C}, + {MISENSOR_16BIT, 0x3716, 0x22CE}, + {MISENSOR_16BIT, 0x3718, 0x2370}, + {MISENSOR_16BIT, 0x371A, 0x258F}, + {MISENSOR_16BIT, 0x371C, 0x3D30}, + {MISENSOR_16BIT, 0x371E, 0x370C}, + {MISENSOR_16BIT, 0x3720, 0x03ED}, + {MISENSOR_16BIT, 0x3722, 0x9AD0}, + {MISENSOR_16BIT, 0x3724, 0x7ECF}, + {MISENSOR_16BIT, 0x3726, 0x1093}, + {MISENSOR_16BIT, 0x3740, 0x2391}, + {MISENSOR_16BIT, 0x3742, 0xAAD0}, + {MISENSOR_16BIT, 0x3744, 0x28F2}, + {MISENSOR_16BIT, 0x3746, 0xBA4F}, + {MISENSOR_16BIT, 0x3748, 0xC536}, + {MISENSOR_16BIT, 0x374A, 0x1472}, + {MISENSOR_16BIT, 0x374C, 0xD110}, + {MISENSOR_16BIT, 0x374E, 0x2933}, + {MISENSOR_16BIT, 0x3750, 0xD0D1}, + {MISENSOR_16BIT, 0x3752, 0x9F37}, + {MISENSOR_16BIT, 0x3754, 0x34D1}, + {MISENSOR_16BIT, 0x3756, 0x1C6C}, + {MISENSOR_16BIT, 0x3758, 0x3FD2}, + {MISENSOR_16BIT, 0x375A, 0xCB72}, + {MISENSOR_16BIT, 0x375C, 0xBA96}, + {MISENSOR_16BIT, 0x375E, 0x1551}, + {MISENSOR_16BIT, 0x3760, 0xB74F}, + {MISENSOR_16BIT, 0x3762, 0x1672}, + {MISENSOR_16BIT, 0x3764, 0x84F1}, + {MISENSOR_16BIT, 0x3766, 0xC2D6}, + {MISENSOR_16BIT, 0x3782, 0x01E0}, + {MISENSOR_16BIT, 0x3784, 0x0280}, + {MISENSOR_16BIT, 0x37C0, 0xA6EA}, + {MISENSOR_16BIT, 0x37C2, 0x874B}, + {MISENSOR_16BIT, 0x37C4, 0x85CB}, + {MISENSOR_16BIT, 0x37C6, 0x968A}, + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xC960, 0x0AF0}, + {MISENSOR_16BIT, 0xC962, 0x79E2}, + {MISENSOR_16BIT, 0xC964, 0x5EC8}, + {MISENSOR_16BIT, 0xC966, 0x791F}, + {MISENSOR_16BIT, 0xC968, 0x76EE}, + {MISENSOR_16BIT, 0xC96A, 0x0FA0}, + {MISENSOR_16BIT, 0xC96C, 0x7DFA}, + {MISENSOR_16BIT, 0xC96E, 0x7DAF}, + {MISENSOR_16BIT, 0xC970, 0x7E02}, + {MISENSOR_16BIT, 0xC972, 0x7E0A}, + {MISENSOR_16BIT, 0xC974, 0x1964}, + {MISENSOR_16BIT, 0xC976, 0x7CDC}, + {MISENSOR_16BIT, 0xC978, 0x7838}, + {MISENSOR_16BIT, 0xC97A, 0x7C2F}, + {MISENSOR_16BIT, 0xC97C, 0x7792}, + {MISENSOR_16BIT, 0xC95E, 0x0003}, + + /* [Step4-APGA] */ + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xC95E, 0x0003}, + + /* [Step5-AWB_CCM]1: LOAD=CCM */ + {MISENSOR_16BIT, 0xC892, 0x0267}, + {MISENSOR_16BIT, 0xC894, 0xFF1A}, + {MISENSOR_16BIT, 0xC896, 0xFFB3}, + {MISENSOR_16BIT, 0xC898, 0xFF80}, + {MISENSOR_16BIT, 0xC89A, 0x0166}, + {MISENSOR_16BIT, 0xC89C, 0x0003}, + {MISENSOR_16BIT, 0xC89E, 0xFF9A}, + {MISENSOR_16BIT, 0xC8A0, 0xFEB4}, + {MISENSOR_16BIT, 0xC8A2, 0x024D}, + {MISENSOR_16BIT, 0xC8A4, 0x01BF}, + {MISENSOR_16BIT, 0xC8A6, 0xFF01}, + {MISENSOR_16BIT, 0xC8A8, 0xFFF3}, + {MISENSOR_16BIT, 0xC8AA, 0xFF75}, + {MISENSOR_16BIT, 0xC8AC, 0x0198}, + {MISENSOR_16BIT, 0xC8AE, 0xFFFD}, + {MISENSOR_16BIT, 0xC8B0, 0xFF9A}, + {MISENSOR_16BIT, 0xC8B2, 0xFEE7}, + {MISENSOR_16BIT, 0xC8B4, 0x02A8}, + {MISENSOR_16BIT, 0xC8B6, 0x01D9}, + {MISENSOR_16BIT, 0xC8B8, 0xFF26}, + {MISENSOR_16BIT, 0xC8BA, 0xFFF3}, + {MISENSOR_16BIT, 0xC8BC, 0xFFB3}, + {MISENSOR_16BIT, 0xC8BE, 0x0132}, + {MISENSOR_16BIT, 0xC8C0, 0xFFE8}, + {MISENSOR_16BIT, 0xC8C2, 0xFFDA}, + {MISENSOR_16BIT, 0xC8C4, 0xFECD}, + {MISENSOR_16BIT, 0xC8C6, 0x02C2}, + {MISENSOR_16BIT, 0xC8C8, 0x0075}, + {MISENSOR_16BIT, 0xC8CA, 0x011C}, + {MISENSOR_16BIT, 0xC8CC, 0x009A}, + {MISENSOR_16BIT, 0xC8CE, 0x0105}, + {MISENSOR_16BIT, 0xC8D0, 0x00A4}, + {MISENSOR_16BIT, 0xC8D2, 0x00AC}, + {MISENSOR_16BIT, 0xC8D4, 0x0A8C}, + {MISENSOR_16BIT, 0xC8D6, 0x0F0A}, + {MISENSOR_16BIT, 0xC8D8, 0x1964}, + + /* LOAD=AWB */ + {MISENSOR_16BIT, 0xC914, 0x0000}, + {MISENSOR_16BIT, 0xC916, 0x0000}, + {MISENSOR_16BIT, 0xC918, 0x04FF}, + {MISENSOR_16BIT, 0xC91A, 0x02CF}, + {MISENSOR_16BIT, 0xC904, 0x0033}, + {MISENSOR_16BIT, 0xC906, 0x0040}, + {MISENSOR_8BIT, 0xC8F2, 0x03}, + {MISENSOR_8BIT, 0xC8F3, 0x02}, + {MISENSOR_16BIT, 0xC906, 0x003C}, + {MISENSOR_16BIT, 0xC8F4, 0x0000}, + {MISENSOR_16BIT, 0xC8F6, 0x0000}, + {MISENSOR_16BIT, 0xC8F8, 0x0000}, + {MISENSOR_16BIT, 0xC8FA, 0xE724}, + {MISENSOR_16BIT, 0xC8FC, 0x1583}, + {MISENSOR_16BIT, 0xC8FE, 0x2045}, + {MISENSOR_16BIT, 0xC900, 0x05DC}, + {MISENSOR_16BIT, 0xC902, 0x007C}, + {MISENSOR_8BIT, 0xC90C, 0x80}, + {MISENSOR_8BIT, 0xC90D, 0x80}, + {MISENSOR_8BIT, 0xC90E, 0x80}, + {MISENSOR_8BIT, 0xC90F, 0x88}, + {MISENSOR_8BIT, 0xC910, 0x80}, + {MISENSOR_8BIT, 0xC911, 0x80}, + + /* LOAD=Step7-CPIPE_Preference */ + {MISENSOR_16BIT, 0xC926, 0x0020}, + {MISENSOR_16BIT, 0xC928, 0x009A}, + {MISENSOR_16BIT, 0xC946, 0x0070}, + {MISENSOR_16BIT, 0xC948, 0x00F3}, + {MISENSOR_16BIT, 0xC952, 0x0020}, + {MISENSOR_16BIT, 0xC954, 0x009A}, + {MISENSOR_8BIT, 0xC92A, 0x80}, + {MISENSOR_8BIT, 0xC92B, 0x4B}, + {MISENSOR_8BIT, 0xC92C, 0x00}, + {MISENSOR_8BIT, 0xC92D, 0xFF}, + {MISENSOR_8BIT, 0xC92E, 0x3C}, + {MISENSOR_8BIT, 0xC92F, 0x02}, + {MISENSOR_8BIT, 0xC930, 0x06}, + {MISENSOR_8BIT, 0xC931, 0x64}, + {MISENSOR_8BIT, 0xC932, 0x01}, + {MISENSOR_8BIT, 0xC933, 0x0C}, + {MISENSOR_8BIT, 0xC934, 0x3C}, + {MISENSOR_8BIT, 0xC935, 0x3C}, + {MISENSOR_8BIT, 0xC936, 0x3C}, + {MISENSOR_8BIT, 0xC937, 0x0F}, + {MISENSOR_8BIT, 0xC938, 0x64}, + {MISENSOR_8BIT, 0xC939, 0x64}, + {MISENSOR_8BIT, 0xC93A, 0x64}, + {MISENSOR_8BIT, 0xC93B, 0x32}, + {MISENSOR_16BIT, 0xC93C, 0x0020}, + {MISENSOR_16BIT, 0xC93E, 0x009A}, + {MISENSOR_16BIT, 0xC940, 0x00DC}, + {MISENSOR_8BIT, 0xC942, 0x38}, + {MISENSOR_8BIT, 0xC943, 0x30}, + {MISENSOR_8BIT, 0xC944, 0x50}, + {MISENSOR_8BIT, 0xC945, 0x19}, + {MISENSOR_16BIT, 0xC94A, 0x0230}, + {MISENSOR_16BIT, 0xC94C, 0x0010}, + {MISENSOR_16BIT, 0xC94E, 0x01CD}, + {MISENSOR_8BIT, 0xC950, 0x05}, + {MISENSOR_8BIT, 0xC951, 0x40}, + {MISENSOR_8BIT, 0xC87B, 0x1B}, + {MISENSOR_8BIT, 0xC878, 0x0E}, + {MISENSOR_16BIT, 0xC890, 0x0080}, + {MISENSOR_16BIT, 0xC886, 0x0100}, + {MISENSOR_16BIT, 0xC87C, 0x005A}, + {MISENSOR_8BIT, 0xB42A, 0x05}, + {MISENSOR_8BIT, 0xA80A, 0x20}, + + /* Speed up AE/AWB */ + {MISENSOR_16BIT, 0x098E, 0x2802}, + {MISENSOR_16BIT, 0xA802, 0x0008}, + {MISENSOR_8BIT, 0xC908, 0x01}, + {MISENSOR_8BIT, 0xC879, 0x01}, + {MISENSOR_8BIT, 0xC909, 0x02}, + {MISENSOR_8BIT, 0xA80A, 0x18}, + {MISENSOR_8BIT, 0xA80B, 0x18}, + {MISENSOR_8BIT, 0xAC16, 0x18}, + {MISENSOR_8BIT, 0xC878, 0x0E}, + + {MISENSOR_TOK_TERM, 0, 0} +}; + +#endif +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov2680.h b/drivers/staging/media/atomisp/i2c/ov2680.h new file mode 100644 index 000000000..7ab337b85 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2680.h @@ -0,0 +1,917 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for OmniVision OV2680 5M camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __OV2680_H__ +#define __OV2680_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../include/linux/atomisp_platform.h" + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV2680_FOCAL_LENGTH_NUM 334 /*3.34mm*/ +#define OV2680_FOCAL_LENGTH_DEM 100 +#define OV2680_F_NUMBER_DEFAULT_NUM 24 +#define OV2680_F_NUMBER_DEM 10 + +#define OV2680_BIN_FACTOR_MAX 4 + +#define MAX_FMTS 1 + +/* sensor_mode_data read_mode adaptation */ +#define OV2680_READ_MODE_BINNING_ON 0x0400 +#define OV2680_READ_MODE_BINNING_OFF 0x00 +#define OV2680_INTEGRATION_TIME_MARGIN 8 + +#define OV2680_MAX_EXPOSURE_VALUE 0xFFF1 +#define OV2680_MAX_GAIN_VALUE 0xFF + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2680_FOCAL_LENGTH_DEFAULT 0x1B70064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2680_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV2680_F_NUMBER_RANGE 0x180a180a +#define OV2680_ID 0x2680 + +#define OV2680_FINE_INTG_TIME_MIN 0 +#define OV2680_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV2680_COARSE_INTG_TIME_MIN 1 +#define OV2680_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * OV2680 System control registers + */ +#define OV2680_SW_SLEEP 0x0100 +#define OV2680_SW_RESET 0x0103 +#define OV2680_SW_STREAM 0x0100 + +#define OV2680_SC_CMMN_CHIP_ID_H 0x300A +#define OV2680_SC_CMMN_CHIP_ID_L 0x300B +#define OV2680_SC_CMMN_SCCB_ID 0x302B /* 0x300C*/ +#define OV2680_SC_CMMN_SUB_ID 0x302A /* process, version*/ + +#define OV2680_GROUP_ACCESS 0x3208 /*Bit[7:4] Group control, Bit[3:0] Group ID*/ + +#define OV2680_EXPOSURE_H 0x3500 /*Bit[3:0] Bit[19:16] of exposure, remaining 16 bits lies in Reg0x3501&Reg0x3502*/ +#define OV2680_EXPOSURE_M 0x3501 +#define OV2680_EXPOSURE_L 0x3502 +#define OV2680_AGC_H 0x350A /*Bit[1:0] means Bit[9:8] of gain*/ +#define OV2680_AGC_L 0x350B /*Bit[7:0] of gain*/ + +#define OV2680_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/ +#define OV2680_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/ +#define OV2680_VERTICAL_START_H 0x3802 /*Bit[11:8]*/ +#define OV2680_VERTICAL_START_L 0x3803 /*Bit[7:0]*/ +#define OV2680_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/ +#define OV2680_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/ +#define OV2680_VERTICAL_END_H 0x3806 /*Bit[11:8]*/ +#define OV2680_VERTICAL_END_L 0x3807 /*Bit[7:0]*/ +#define OV2680_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/ +#define OV2680_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/ +#define OV2680_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/ +#define OV2680_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/ +#define OV2680_TIMING_HTS_H 0x380C /*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV2680_TIMING_HTS_L 0x380D /*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV2680_TIMING_VTS_H 0x380e /*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV2680_TIMING_VTS_L 0x380f /*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV2680_FRAME_OFF_NUM 0x4202 + +/*Flip/Mirror*/ +#define OV2680_FLIP_REG 0x3820 +#define OV2680_MIRROR_REG 0x3821 +#define OV2680_FLIP_BIT 1 +#define OV2680_MIRROR_BIT 2 +#define OV2680_FLIP_MIRROR_BIT_ENABLE 4 + +#define OV2680_MWB_RED_GAIN_H 0x5004/*0x3400*/ +#define OV2680_MWB_GREEN_GAIN_H 0x5006/*0x3402*/ +#define OV2680_MWB_BLUE_GAIN_H 0x5008/*0x3404*/ +#define OV2680_MWB_GAIN_MAX 0x0fff + +#define OV2680_START_STREAMING 0x01 +#define OV2680_STOP_STREAMING 0x00 + +#define OV2680_INVALID_CONFIG 0xffffffff + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov2680_resolution { + const struct ov2680_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; +}; + +struct ov2680_format { + u8 *desc; + u32 pixelformat; + struct ov2680_reg *regs; +}; + +/* + * ov2680 device structure. + */ +struct ov2680_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + struct ov2680_resolution *res; + struct camera_sensor_platform_data *platform_data; + bool power_on; + u16 exposure; + u16 gain; + u16 digitgain; +}; + +/** + * struct ov2680_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov2680_reg { + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_ov2680_sensor(x) container_of(x, struct ov2680_device, sd) + +#define OV2680_MAX_WRITE_BUF_SIZE 30 + +struct ov2680_write_buffer { + u16 addr; + u8 data[OV2680_MAX_WRITE_BUF_SIZE]; +}; + +struct ov2680_write_ctrl { + int index; + struct ov2680_write_buffer buffer; +}; + +static struct ov2680_reg const ov2680_global_setting[] = { + {0x0103, 0x01}, + {0x3002, 0x00}, + {0x3016, 0x1c}, + {0x3018, 0x44}, + {0x3020, 0x00}, + {0x3080, 0x02}, + {0x3082, 0x45}, + {0x3084, 0x09}, + {0x3085, 0x04}, + {0x3503, 0x03}, + {0x350b, 0x36}, + {0x3600, 0xb4}, + {0x3603, 0x39}, + {0x3604, 0x24}, + {0x3605, 0x00}, + {0x3620, 0x26}, + {0x3621, 0x37}, + {0x3622, 0x04}, + {0x3628, 0x00}, + {0x3705, 0x3c}, + {0x370c, 0x50}, + {0x370d, 0xc0}, + {0x3718, 0x88}, + {0x3720, 0x00}, + {0x3721, 0x00}, + {0x3722, 0x00}, + {0x3723, 0x00}, + {0x3738, 0x00}, + {0x3717, 0x58}, + {0x3781, 0x80}, + {0x3789, 0x60}, + {0x3800, 0x00}, + {0x3819, 0x04}, + {0x4000, 0x81}, + {0x4001, 0x40}, + {0x4602, 0x02}, + {0x481f, 0x36}, + {0x4825, 0x36}, + {0x4837, 0x18}, + {0x5002, 0x30}, + {0x5004, 0x04},//manual awb 1x + {0x5005, 0x00}, + {0x5006, 0x04}, + {0x5007, 0x00}, + {0x5008, 0x04}, + {0x5009, 0x00}, + {0x5080, 0x00}, + {0x3701, 0x64}, //add on 14/05/13 + {0x3784, 0x0c}, //based OV2680_R1A_AM10.ovt add on 14/06/13 + {0x5780, 0x3e}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 + {0x5781, 0x0f}, + {0x5782, 0x04}, + {0x5783, 0x02}, + {0x5784, 0x01}, + {0x5785, 0x01}, + {0x5786, 0x00}, + {0x5787, 0x04}, + {0x5788, 0x02}, + {0x5789, 0x00}, + {0x578a, 0x01}, + {0x578b, 0x02}, + {0x578c, 0x03}, + {0x578d, 0x03}, + {0x578e, 0x08}, + {0x578f, 0x0c}, + {0x5790, 0x08}, + {0x5791, 0x04}, + {0x5792, 0x00}, + {0x5793, 0x00}, + {0x5794, 0x03}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 + {0x0100, 0x00}, //stream off + + {} +}; + +/* + * 176x144 30fps VBlanking 1lane 10Bit (binning) + */ +static struct ov2680_reg const ov2680_QCIF_30fps[] = { + {0x3086, 0x01}, + {0x370a, 0x23}, + {0x3801, 0xa0}, + {0x3802, 0x00}, + {0x3803, 0x78}, + {0x3804, 0x05}, + {0x3805, 0xaf}, + {0x3806, 0x04}, + {0x3807, 0x47}, + {0x3808, 0x00}, + {0x3809, 0xC0}, + {0x380a, 0x00}, + {0x380b, 0xa0}, + {0x380c, 0x06}, + {0x380d, 0xb0}, + {0x3810, 0x00}, + {0x3811, 0x04}, + {0x3812, 0x00}, + {0x3813, 0x04}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x4000, 0x81}, + {0x4001, 0x40}, + {0x4008, 0x00}, + {0x4009, 0x03}, + {0x5081, 0x41}, + {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x10}, + {0x5705, 0xa0}, + {0x5706, 0x0c}, + {0x5707, 0x78}, + {0x3820, 0xc2}, + {0x3821, 0x01}, + // {0x5090, 0x0c}, + {} +}; + +/* + * 352x288 30fps VBlanking 1lane 10Bit (binning) + */ +static struct ov2680_reg const ov2680_CIF_30fps[] = { + {0x3086, 0x01}, + {0x370a, 0x23}, + {0x3801, 0xa0}, + {0x3802, 0x00}, + {0x3803, 0x78}, + {0x3804, 0x03}, + {0x3805, 0x8f}, + {0x3806, 0x02}, + {0x3807, 0xe7}, + {0x3808, 0x01}, + {0x3809, 0x70}, + {0x380a, 0x01}, + {0x380b, 0x30}, + {0x380c, 0x06}, + {0x380d, 0xb0}, + {0x3810, 0x00}, + {0x3811, 0x04}, + {0x3812, 0x00}, + {0x3813, 0x04}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x4008, 0x00}, + {0x4009, 0x03}, + {0x5081, 0x41}, + {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x10}, + {0x5705, 0xa0}, + {0x5706, 0x0c}, + {0x5707, 0x78}, + {0x3820, 0xc2}, + {0x3821, 0x01}, + // {0x5090, 0x0c}, + {} +}; + +/* + * 336x256 30fps VBlanking 1lane 10Bit (binning) + */ +static struct ov2680_reg const ov2680_QVGA_30fps[] = { + {0x3086, 0x01}, + {0x370a, 0x23}, + {0x3801, 0xa0}, + {0x3802, 0x00}, + {0x3803, 0x78}, + {0x3804, 0x03}, + {0x3805, 0x4f}, + {0x3806, 0x02}, + {0x3807, 0x87}, + {0x3808, 0x01}, + {0x3809, 0x50}, + {0x380a, 0x01}, + {0x380b, 0x00}, + {0x380c, 0x06}, + {0x380d, 0xb0}, + {0x3810, 0x00}, + {0x3811, 0x04}, + {0x3812, 0x00}, + {0x3813, 0x04}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x4008, 0x00}, + {0x4009, 0x03}, + {0x5081, 0x41}, + {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x10}, + {0x5705, 0xa0}, + {0x5706, 0x0c}, + {0x5707, 0x78}, + {0x3820, 0xc2}, + {0x3821, 0x01}, + // {0x5090, 0x0c}, + {} +}; + +/* + * 656x496 30fps VBlanking 1lane 10Bit (binning) + */ +static struct ov2680_reg const ov2680_656x496_30fps[] = { + {0x3086, 0x01}, + {0x370a, 0x23}, + {0x3801, 0xa0}, + {0x3802, 0x00}, + {0x3803, 0x78}, + {0x3804, 0x05}, + {0x3805, 0xcf}, + {0x3806, 0x04}, + {0x3807, 0x67}, + {0x3808, 0x02}, + {0x3809, 0x90}, + {0x380a, 0x01}, + {0x380b, 0xf0}, + {0x380c, 0x06}, + {0x380d, 0xb0}, + {0x3810, 0x00}, + {0x3811, 0x04}, + {0x3812, 0x00}, + {0x3813, 0x04}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x4008, 0x00}, + {0x4009, 0x03}, + {0x5081, 0x41}, + {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x10}, + {0x5705, 0xa0}, + {0x5706, 0x0c}, + {0x5707, 0x78}, + {0x3820, 0xc2}, + {0x3821, 0x01}, + // {0x5090, 0x0c}, + {} +}; + +/* + * 720x592 30fps VBlanking 1lane 10Bit (binning) + */ +static struct ov2680_reg const ov2680_720x592_30fps[] = { + {0x3086, 0x01}, + {0x370a, 0x23}, + {0x3801, 0x00}, // X_ADDR_START; + {0x3802, 0x00}, + {0x3803, 0x00}, // Y_ADDR_START; + {0x3804, 0x05}, + {0x3805, 0xaf}, // X_ADDR_END; + {0x3806, 0x04}, + {0x3807, 0xaf}, // Y_ADDR_END; + {0x3808, 0x02}, + {0x3809, 0xd0}, // X_OUTPUT_SIZE; + {0x380a, 0x02}, + {0x380b, 0x50}, // Y_OUTPUT_SIZE; + {0x380c, 0x06}, + {0x380d, 0xac}, // HTS; + {0x3810, 0x00}, + {0x3811, 0x00}, + {0x3812, 0x00}, + {0x3813, 0x00}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x4008, 0x00}, + {0x4009, 0x03}, + {0x5708, 0x00}, + {0x5704, 0x02}, + {0x5705, 0xd0}, // X_WIN; + {0x5706, 0x02}, + {0x5707, 0x50}, // Y_WIN; + {0x3820, 0xc2}, // FLIP_FORMAT; + {0x3821, 0x01}, // MIRROR_FORMAT; + {0x5090, 0x00}, // PRE ISP CTRL16, default value is 0x0C; + // BIT[3]: Mirror order, BG or GB; + // BIT[2]: Flip order, BR or RB; + {0x5081, 0x41}, + {} +}; + +/* + * 800x600 30fps VBlanking 1lane 10Bit (binning) + */ +static struct ov2680_reg const ov2680_800x600_30fps[] = { + {0x3086, 0x01}, + {0x370a, 0x23}, + {0x3801, 0x00}, /* hstart 0 */ + {0x3802, 0x00}, + {0x3803, 0x00}, /* vstart 0 */ + {0x3804, 0x06}, + {0x3805, 0x4f}, /* hend 1615 */ + {0x3806, 0x04}, + {0x3807, 0xbf}, /* vend 1215 */ + {0x3808, 0x03}, + {0x3809, 0x20}, /* hsize 800 */ + {0x380a, 0x02}, + {0x380b, 0x58}, /* vsize 600 */ + {0x380c, 0x06}, + {0x380d, 0xac}, /* htotal 1708 */ + {0x3810, 0x00}, + {0x3811, 0x00}, + {0x3812, 0x00}, + {0x3813, 0x00}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x5708, 0x00}, + {0x5704, 0x03}, + {0x5705, 0x20}, + {0x5706, 0x02}, + {0x5707, 0x58}, + {0x3820, 0xc2}, + {0x3821, 0x01}, + {0x5090, 0x00}, + {0x4008, 0x00}, + {0x4009, 0x03}, + {0x5081, 0x41}, + {} +}; + +/* + * 720p=1280*720 30fps VBlanking 1lane 10Bit (no-Scaling) + */ +static struct ov2680_reg const ov2680_720p_30fps[] = { + {0x3086, 0x00}, + {0x370a, 0x21}, + {0x3801, 0xa0}, /* hstart 160 */ + {0x3802, 0x00}, + {0x3803, 0xf2}, /* vstart 242 */ + {0x3804, 0x05}, + {0x3805, 0xbf}, /* hend 1471 */ + {0x3806, 0x03}, + {0x3807, 0xdd}, /* vend 989 */ + {0x3808, 0x05}, + {0x3809, 0x10}, /* hsize 1296 */ + {0x380a, 0x02}, + {0x380b, 0xe0}, /* vsize 736 */ + {0x380c, 0x06}, + {0x380d, 0xa8}, /* htotal 1704 */ + {0x3810, 0x00}, + {0x3811, 0x08}, + {0x3812, 0x00}, + {0x3813, 0x06}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x4008, 0x02}, + {0x4009, 0x09}, + {0x5081, 0x41}, + {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x10}, + {0x5705, 0xa0}, + {0x5706, 0x0c}, + {0x5707, 0x78}, + {0x3820, 0xc0}, + {0x3821, 0x00}, + // {0x5090, 0x0c}, + {} +}; + +/* + * 1296x976 30fps VBlanking 1lane 10Bit(no-scaling) + */ +static struct ov2680_reg const ov2680_1296x976_30fps[] = { + {0x3086, 0x00}, + {0x370a, 0x21}, + {0x3801, 0xa0}, /* hstart 160 */ + {0x3802, 0x00}, + {0x3803, 0x78}, /* vstart 120 */ + {0x3804, 0x05}, + {0x3805, 0xbf}, /* hend 1471 */ + {0x3806, 0x04}, + {0x3807, 0x57}, /* vend 1111 */ + {0x3808, 0x05}, + {0x3809, 0x10}, /* hsize 1296 */ + {0x380a, 0x03}, + {0x380b, 0xd0}, /* vsize 976 */ + {0x380c, 0x06}, + {0x380d, 0xa8}, /* htotal 1704 */ + {0x3810, 0x00}, + {0x3811, 0x08}, + {0x3812, 0x00}, + {0x3813, 0x08}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x4008, 0x02}, + {0x4009, 0x09}, + {0x5081, 0x41}, + {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x10}, + {0x5705, 0xa0}, + {0x5706, 0x0c}, + {0x5707, 0x78}, + {0x3820, 0xc0}, + {0x3821, 0x00}, //mirror/flip + // {0x5090, 0x0c}, + {} +}; + +/* + * 1456*1096 30fps VBlanking 1lane 10bit(no-scaling) + */ +static struct ov2680_reg const ov2680_1456x1096_30fps[] = { + {0x3086, 0x00}, + {0x370a, 0x21}, + {0x3801, 0x90}, + {0x3802, 0x00}, + {0x3803, 0x78}, + {0x3804, 0x06}, + {0x3805, 0x4f}, + {0x3806, 0x04}, + {0x3807, 0xC0}, + {0x3808, 0x05}, + {0x3809, 0xb0}, + {0x380a, 0x04}, + {0x380b, 0x48}, + {0x380c, 0x06}, + {0x380d, 0xa8}, + {0x3810, 0x00}, + {0x3811, 0x08}, + {0x3812, 0x00}, + {0x3813, 0x00}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x4008, 0x02}, + {0x4009, 0x09}, + {0x5081, 0x41}, + {0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x10}, + {0x5705, 0xa0}, + {0x5706, 0x0c}, + {0x5707, 0x78}, + {0x3820, 0xc0}, + {0x3821, 0x00}, + // {0x5090, 0x0c}, + {} +}; + +/* + *1616x916 30fps VBlanking 1lane 10bit + */ + +static struct ov2680_reg const ov2680_1616x916_30fps[] = { + {0x3086, 0x00}, + {0x370a, 0x21}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x96}, + {0x3804, 0x06}, + {0x3805, 0x4f}, + {0x3806, 0x04}, + {0x3807, 0x39}, + {0x3808, 0x06}, + {0x3809, 0x50}, + {0x380a, 0x03}, + {0x380b, 0x94}, + {0x380c, 0x06}, + {0x380d, 0xa8}, + {0x3810, 0x00}, + {0x3811, 0x00}, + {0x3812, 0x00}, + {0x3813, 0x08}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x4008, 0x02}, + {0x4009, 0x09}, + {0x5081, 0x41}, + {0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x06}, + {0x5705, 0x50}, + {0x5706, 0x03}, + {0x5707, 0x94}, + {0x3820, 0xc0}, + {0x3821, 0x00}, + // {0x5090, 0x0C}, + {} +}; + +/* + * 1616x1082 30fps VBlanking 1lane 10Bit + */ +static struct ov2680_reg const ov2680_1616x1082_30fps[] = { + {0x3086, 0x00}, + {0x370a, 0x21}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x86}, + {0x3804, 0x06}, + {0x3805, 0x4f}, + {0x3806, 0x04}, + {0x3807, 0xbf}, + {0x3808, 0x06}, + {0x3809, 0x50}, + {0x380a, 0x04}, + {0x380b, 0x3a}, + {0x380c, 0x06}, + {0x380d, 0xa8}, + {0x3810, 0x00}, + {0x3811, 0x00}, + {0x3812, 0x00}, + {0x3813, 0x00}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x06}, + {0x5705, 0x50}, + {0x5706, 0x04}, + {0x5707, 0x3a}, + {0x3820, 0xc0}, + {0x3821, 0x00}, + // {0x5090, 0x0C}, + {0x4008, 0x02}, + {0x4009, 0x09}, + {0x5081, 0x41}, + {} +}; + +/* + * 1616x1216 30fps VBlanking 1lane 10Bit + */ +static struct ov2680_reg const ov2680_1616x1216_30fps[] = { + {0x3086, 0x00}, + {0x370a, 0x21}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x00}, + {0x3804, 0x06}, + {0x3805, 0x4f}, + {0x3806, 0x04}, + {0x3807, 0xbf}, + {0x3808, 0x06}, + {0x3809, 0x50},//50},//4line for mirror and flip + {0x380a, 0x04}, + {0x380b, 0xc0},//c0}, + {0x380c, 0x06}, + {0x380d, 0xa8}, + {0x3810, 0x00}, + {0x3811, 0x00}, + {0x3812, 0x00}, + {0x3813, 0x00}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x4008, 0x00}, + {0x4009, 0x0b}, + {0x5081, 0x01}, + {0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {0x5704, 0x06}, + {0x5705, 0x50}, + {0x5706, 0x04}, + {0x5707, 0xcc}, + {0x3820, 0xc0}, + {0x3821, 0x00}, + // {0x5090, 0x0C}, + {} +}; + +static struct ov2680_resolution ov2680_res_preview[] = { + { + .width = 1616, + .height = 1216, + .pix_clk_freq = 66, + .fps = 30, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x1216_30fps, + }, + { + .width = 1616, + .height = 1082, + .pix_clk_freq = 66, + .fps = 30, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x1082_30fps, + }, + { + .width = 1616, + .height = 916, + .fps = 30, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x916_30fps, + }, + { + .width = 1456, + .height = 1096, + .fps = 30, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1456x1096_30fps, + }, + { + .width = 1296, + .height = 976, + .fps = 30, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1296x976_30fps, + }, + { + .width = 1296, + .height = 736, + .fps = 60, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_720p_30fps, + }, + { + .width = 800, + .height = 600, + .fps = 60, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_800x600_30fps, + }, + { + .width = 720, + .height = 592, + .fps = 60, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_720x592_30fps, + }, + { + .width = 656, + .height = 496, + .fps = 60, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_656x496_30fps, + }, + { + .width = 336, + .height = 256, + .fps = 60, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_QVGA_30fps, + }, + { + .width = 352, + .height = 288, + .fps = 60, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_CIF_30fps, + }, + { + .width = 176, + .height = 144, + .fps = 60, + .pix_clk_freq = 66, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_QCIF_30fps, + }, +}; + +#define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview)) + +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov2722.h b/drivers/staging/media/atomisp/i2c/ov2722.h new file mode 100644 index 000000000..d6e2510bc --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2722.h @@ -0,0 +1,1272 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for OmniVision OV2722 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __OV2722_H__ +#define __OV2722_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../include/linux/atomisp_platform.h" + +#define OV2722_POWER_UP_RETRY_NUM 5 + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV2722_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define OV2722_FOCAL_LENGTH_DEM 100 +#define OV2722_F_NUMBER_DEFAULT_NUM 26 +#define OV2722_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2722_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV2722_F_NUMBER_RANGE 0x1a0a1a0a +#define OV2720_ID 0x2720 +#define OV2722_ID 0x2722 + +#define OV2722_FINE_INTG_TIME_MIN 0 +#define OV2722_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV2722_COARSE_INTG_TIME_MIN 1 +#define OV2722_COARSE_INTG_TIME_MAX_MARGIN 4 + +/* + * OV2722 System control registers + */ +#define OV2722_SW_SLEEP 0x0100 +#define OV2722_SW_RESET 0x0103 +#define OV2722_SW_STREAM 0x0100 + +#define OV2722_SC_CMMN_CHIP_ID_H 0x300A +#define OV2722_SC_CMMN_CHIP_ID_L 0x300B +#define OV2722_SC_CMMN_SCCB_ID 0x300C +#define OV2722_SC_CMMN_SUB_ID 0x302A /* process, version*/ + +#define OV2722_SC_CMMN_PAD_OEN0 0x3000 +#define OV2722_SC_CMMN_PAD_OEN1 0x3001 +#define OV2722_SC_CMMN_PAD_OEN2 0x3002 +#define OV2722_SC_CMMN_PAD_OUT0 0x3008 +#define OV2722_SC_CMMN_PAD_OUT1 0x3009 +#define OV2722_SC_CMMN_PAD_OUT2 0x300D +#define OV2722_SC_CMMN_PAD_SEL0 0x300E +#define OV2722_SC_CMMN_PAD_SEL1 0x300F +#define OV2722_SC_CMMN_PAD_SEL2 0x3010 + +#define OV2722_SC_CMMN_PAD_PK 0x3011 +#define OV2722_SC_CMMN_A_PWC_PK_O_13 0x3013 +#define OV2722_SC_CMMN_A_PWC_PK_O_14 0x3014 + +#define OV2722_SC_CMMN_CLKRST0 0x301A +#define OV2722_SC_CMMN_CLKRST1 0x301B +#define OV2722_SC_CMMN_CLKRST2 0x301C +#define OV2722_SC_CMMN_CLKRST3 0x301D +#define OV2722_SC_CMMN_CLKRST4 0x301E +#define OV2722_SC_CMMN_CLKRST5 0x3005 +#define OV2722_SC_CMMN_PCLK_DIV_CTRL 0x3007 +#define OV2722_SC_CMMN_CLOCK_SEL 0x3020 +#define OV2722_SC_SOC_CLKRST5 0x3040 + +#define OV2722_SC_CMMN_PLL_CTRL0 0x3034 +#define OV2722_SC_CMMN_PLL_CTRL1 0x3035 +#define OV2722_SC_CMMN_PLL_CTRL2 0x3039 +#define OV2722_SC_CMMN_PLL_CTRL3 0x3037 +#define OV2722_SC_CMMN_PLL_MULTIPLIER 0x3036 +#define OV2722_SC_CMMN_PLL_DEBUG_OPT 0x3038 +#define OV2722_SC_CMMN_PLLS_CTRL0 0x303A +#define OV2722_SC_CMMN_PLLS_CTRL1 0x303B +#define OV2722_SC_CMMN_PLLS_CTRL2 0x303C +#define OV2722_SC_CMMN_PLLS_CTRL3 0x303D + +#define OV2722_SC_CMMN_MIPI_PHY_16 0x3016 +#define OV2722_SC_CMMN_MIPI_PHY_17 0x3017 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_18 0x3018 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_19 0x3019 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_21 0x3021 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_22 0x3022 + +#define OV2722_AEC_PK_EXPO_H 0x3500 +#define OV2722_AEC_PK_EXPO_M 0x3501 +#define OV2722_AEC_PK_EXPO_L 0x3502 +#define OV2722_AEC_MANUAL_CTRL 0x3503 +#define OV2722_AGC_ADJ_H 0x3508 +#define OV2722_AGC_ADJ_L 0x3509 +#define OV2722_VTS_DIFF_H 0x350c +#define OV2722_VTS_DIFF_L 0x350d +#define OV2722_GROUP_ACCESS 0x3208 +#define OV2722_HTS_H 0x380c +#define OV2722_HTS_L 0x380d +#define OV2722_VTS_H 0x380e +#define OV2722_VTS_L 0x380f + +#define OV2722_MWB_GAIN_R_H 0x5186 +#define OV2722_MWB_GAIN_R_L 0x5187 +#define OV2722_MWB_GAIN_G_H 0x5188 +#define OV2722_MWB_GAIN_G_L 0x5189 +#define OV2722_MWB_GAIN_B_H 0x518a +#define OV2722_MWB_GAIN_B_L 0x518b + +#define OV2722_H_CROP_START_H 0x3800 +#define OV2722_H_CROP_START_L 0x3801 +#define OV2722_V_CROP_START_H 0x3802 +#define OV2722_V_CROP_START_L 0x3803 +#define OV2722_H_CROP_END_H 0x3804 +#define OV2722_H_CROP_END_L 0x3805 +#define OV2722_V_CROP_END_H 0x3806 +#define OV2722_V_CROP_END_L 0x3807 +#define OV2722_H_OUTSIZE_H 0x3808 +#define OV2722_H_OUTSIZE_L 0x3809 +#define OV2722_V_OUTSIZE_H 0x380a +#define OV2722_V_OUTSIZE_L 0x380b + +#define OV2722_START_STREAMING 0x01 +#define OV2722_STOP_STREAMING 0x00 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov2722_resolution { + u8 *desc; + const struct ov2722_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; + int mipi_freq; +}; + +struct ov2722_format { + u8 *desc; + u32 pixelformat; + struct ov2722_reg *regs; +}; + +/* + * ov2722 device structure. + */ +struct ov2722_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct ov2722_resolution *res; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + int run_mode; + u16 pixels_per_line; + u16 lines_per_frame; + u8 type; + + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *link_freq; +}; + +enum ov2722_tok_type { + OV2722_8BIT = 0x0001, + OV2722_16BIT = 0x0002, + OV2722_32BIT = 0x0004, + OV2722_TOK_TERM = 0xf000, /* terminating token for reg list */ + OV2722_TOK_DELAY = 0xfe00, /* delay token for reg list */ + OV2722_TOK_MASK = 0xfff0 +}; + +/** + * struct ov2722_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov2722_reg { + enum ov2722_tok_type type; + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_ov2722_sensor(x) container_of(x, struct ov2722_device, sd) + +#define OV2722_MAX_WRITE_BUF_SIZE 30 + +struct ov2722_write_buffer { + u16 addr; + u8 data[OV2722_MAX_WRITE_BUF_SIZE]; +}; + +struct ov2722_write_ctrl { + int index; + struct ov2722_write_buffer buffer; +}; + +/* + * Register settings for various resolution + */ +#if 0 +static struct ov2722_reg const ov2722_QVGA_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x0c}, + {OV2722_8BIT, 0x373a, 0x1c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x0c}, + {OV2722_8BIT, 0x3705, 0x06}, + {OV2722_8BIT, 0x3730, 0x0e}, + {OV2722_8BIT, 0x3704, 0x1c}, + {OV2722_8BIT, 0x3f06, 0x00}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x46}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0x63}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x95}, /* H crop end: 1685 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x27}, /* V crop end: 1063 */ + {OV2722_8BIT, 0x3808, 0x01}, + {OV2722_8BIT, 0x3809, 0x50}, /* H output size: 336 */ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0x00}, /* V output size: 256 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0xc0}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x71}, + {OV2722_8BIT, 0x3815, 0x71}, + {OV2722_8BIT, 0x3612, 0x49}, + {OV2722_8BIT, 0x3618, 0x00}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0xc3}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x77}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x09}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, + +}; + +static struct ov2722_reg const ov2722_480P_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x18}, + {OV2722_8BIT, 0x373a, 0x3c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x1d}, + {OV2722_8BIT, 0x3705, 0x12}, + {OV2722_8BIT, 0x3730, 0x1f}, + {OV2722_8BIT, 0x3704, 0x3f}, + {OV2722_8BIT, 0x3f06, 0x1d}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x83}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0xbd}, + {OV2722_8BIT, 0x3708, 0x63}, + {OV2722_8BIT, 0x3709, 0x52}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0xf2}, /* H crop start: 322 - 80 = 242*/ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xBB}, /* H crop end: 1643 + 80 = 1723*/ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ + {OV2722_8BIT, 0x3808, 0x02}, + {OV2722_8BIT, 0x3809, 0xE0}, /* H output size: 656 +80 = 736*/ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x31}, + {OV2722_8BIT, 0x3815, 0x31}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x02}, + {OV2722_8BIT, 0x3a09, 0x67}, + {OV2722_8BIT, 0x3a0a, 0x02}, + {OV2722_8BIT, 0x3a0b, 0x00}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x0a}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; + +static struct ov2722_reg const ov2722_VGA_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x18}, + {OV2722_8BIT, 0x373a, 0x3c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x1d}, + {OV2722_8BIT, 0x3705, 0x12}, + {OV2722_8BIT, 0x3730, 0x1f}, + {OV2722_8BIT, 0x3704, 0x3f}, + {OV2722_8BIT, 0x3f06, 0x1d}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x83}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0xbd}, + {OV2722_8BIT, 0x3708, 0x63}, + {OV2722_8BIT, 0x3709, 0x52}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x6B}, /* H crop end: 1643*/ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ + {OV2722_8BIT, 0x3808, 0x02}, + {OV2722_8BIT, 0x3809, 0x90}, /* H output size: 656 */ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x31}, + {OV2722_8BIT, 0x3815, 0x31}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x02}, + {OV2722_8BIT, 0x3a09, 0x67}, + {OV2722_8BIT, 0x3a0a, 0x02}, + {OV2722_8BIT, 0x3a0b, 0x00}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x0a}, + {OV2722_8BIT, 0x4837, 0x29}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; +#endif + +static struct ov2722_reg const ov2722_1632_1092_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for + a whole frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0x9E}, /* H crop start: 158 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x07}, + {OV2722_8BIT, 0x3805, 0x05}, /* H crop end: 1797 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + + {OV2722_8BIT, 0x3808, 0x06}, + {OV2722_8BIT, 0x3809, 0x60}, /* H output size: 1632 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; + +static struct ov2722_reg const ov2722_1452_1092_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for + a whole frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0xF8}, /* H crop start: 248 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xab}, /* H crop end: 1707 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0xac}, /* H output size: 1452 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; + +#if 0 +static struct ov2722_reg const ov2722_1M3_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x4a}, /* H crop start: 330 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x03}, /* V crop start: 3 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xe1}, /* H crop end: 1761 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x47}, /* V crop end: 1095 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0x88}, /* H output size: 1416 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x0a}, /* V output size: 1034 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x05}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; +#endif + +static struct ov2722_reg const ov2722_1080p_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for a whole + frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x2b}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x28}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0x08}, /* H crop start: 8 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x07}, + {OV2722_8BIT, 0x3805, 0x9b}, /* H crop end: 1947 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + {OV2722_8BIT, 0x3808, 0x07}, + {OV2722_8BIT, 0x3809, 0x8c}, /* H output size: 1932 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x14}, /* H timing: 2068 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0x5a}, /* V timing: 1114 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcd}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x24}, /* 345.6 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; + +#if 0 /* Currently unused */ +static struct ov2722_reg const ov2722_720p_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x40}, /* H crop start: 320 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0xb1}, /* V crop start: 177 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x55}, /* H crop end: 1621 */ + {OV2722_8BIT, 0x3806, 0x03}, + {OV2722_8BIT, 0x3807, 0x95}, /* V crop end: 918 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0x10}, /* H output size: 0x0788==1928 */ + {OV2722_8BIT, 0x380a, 0x02}, + {OV2722_8BIT, 0x380b, 0xe0}, /* output size: 0x02DE==734 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H timing: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa3}, /* V timing: 1187 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, /* {0x3036, 0x2c}, //422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0}, +}; +#endif + +static struct ov2722_resolution ov2722_res_preview[] = { + { + .desc = "ov2722_1632_1092_30fps", + .width = 1632, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1632_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1452_1092_30fps", + .width = 1452, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1452_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; + +#define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview)) + +/* + * Disable non-preview configurations until the configuration selection is + * improved. + */ +#if 0 +struct ov2722_resolution ov2722_res_still[] = { + { + .desc = "ov2722_480P_30fps", + .width = 1632, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1632_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1452_1092_30fps", + .width = 1452, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1452_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; + +#define N_RES_STILL (ARRAY_SIZE(ov2722_res_still)) + +struct ov2722_resolution ov2722_res_video[] = { + { + .desc = "ov2722_QVGA_30fps", + .width = 336, + .height = 256, + .fps = 30, + .pix_clk_freq = 73, + .used = 0, + .pixels_per_line = 2048, + .lines_per_frame = 1184, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_QVGA_30fps, + .mipi_freq = 364800, + }, + { + .desc = "ov2722_480P_30fps", + .width = 736, + .height = 496, + .fps = 30, + .pix_clk_freq = 73, + .used = 0, + .pixels_per_line = 2048, + .lines_per_frame = 1184, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_480P_30fps, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; + +#define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video)) +#endif + +static struct ov2722_resolution *ov2722_res = ov2722_res_preview; +static unsigned long N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov5693/Makefile b/drivers/staging/media/atomisp/i2c/ov5693/Makefile new file mode 100644 index 000000000..3275f2be2 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_VIDEO_ATOMISP_OV5693) += atomisp-ov5693.o diff --git a/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h b/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h new file mode 100644 index 000000000..f1362cd69 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for AD5823 VCM. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __AD5823_H__ +#define __AD5823_H__ + +#include + +#define AD5823_VCM_ADDR 0x0c + +#define AD5823_REG_RESET 0x01 +#define AD5823_REG_MODE 0x02 +#define AD5823_REG_VCM_MOVE_TIME 0x03 +#define AD5823_REG_VCM_CODE_MSB 0x04 +#define AD5823_REG_VCM_CODE_LSB 0x05 +#define AD5823_REG_VCM_THRESHOLD_MSB 0x06 +#define AD5823_REG_VCM_THRESHOLD_LSB 0x07 + +#define AD5823_REG_LENGTH 0x1 + +#define AD5823_RING_CTRL_ENABLE 0x04 +#define AD5823_RING_CTRL_DISABLE 0x00 + +#define AD5823_RESONANCE_PERIOD 100000 +#define AD5823_RESONANCE_COEF 512 +#define AD5823_HIGH_FREQ_RANGE 0x80 + +#define VCM_CODE_MSB_MASK 0xfc +#define AD5823_INIT_FOCUS_POS 350 + +enum ad5823_tok_type { + AD5823_8BIT = 0x1, + AD5823_16BIT = 0x2, +}; + +enum ad5823_vcm_mode { + AD5823_ARC_RES0 = 0x0, /* Actuator response control RES1 */ + AD5823_ARC_RES1 = 0x1, /* Actuator response control RES0.5 */ + AD5823_ARC_RES2 = 0x2, /* Actuator response control RES2 */ + AD5823_ESRC = 0x3, /* Enhanced slew rate control */ + AD5823_DIRECT = 0x4, /* Direct control */ +}; + +#define AD5823_INVALID_CONFIG 0xffffffff +#define AD5823_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov5693/atomisp-ov5693.c b/drivers/staging/media/atomisp/i2c/ov5693/atomisp-ov5693.c new file mode 100644 index 000000000..c1cd63145 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/atomisp-ov5693.c @@ -0,0 +1,1998 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for OmniVision OV5693 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../include/linux/atomisp_gmin_platform.h" + +#include "ov5693.h" +#include "ad5823.h" + +#define __cci_delay(t) \ + do { \ + if ((t) < 10) { \ + usleep_range((t) * 1000, ((t) + 1) * 1000); \ + } else { \ + msleep((t)); \ + } \ + } while (0) + +/* Value 30ms reached through experimentation on byt ecs. + * The DS specifies a much lower value but when using a smaller value + * the I2C bus sometimes locks up permanently when starting the camera. + * This issue could not be reproduced on cht, so we can reduce the + * delay value to a lower value when insmod. + */ +static uint up_delay = 30; +module_param(up_delay, uint, 0644); +MODULE_PARM_DESC(up_delay, + "Delay prior to the first CCI transaction for ov5693"); + +static int vcm_ad_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + int err; + struct i2c_msg msg; + u8 buf[2]; + + buf[0] = reg; + buf[1] = val; + + msg.addr = VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + + err = i2c_transfer(client->adapter, &msg, 1); + if (err != 1) { + dev_err(&client->dev, "%s: vcm i2c fail, err code = %d\n", + __func__, err); + return -EIO; + } + return 0; +} + +static int ad5823_i2c_write(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + + buf[0] = reg; + buf[1] = val; + msg.addr = AD5823_VCM_ADDR; + msg.flags = 0; + msg.len = 0x02; + msg.buf = &buf[0]; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5823_i2c_read(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = AD5823_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 0x01; + msg[0].buf = &buf[0]; + + msg[1].addr = 0x0c; + msg[1].flags = I2C_M_RD; + msg[1].len = 0x01; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + +static const u32 ov5693_embedded_effective_size = 28; + +/* i2c read/write stuff */ +static int ov5693_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != OV5693_8BIT && data_length != OV5693_16BIT + && data_length != OV5693_32BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0, sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg >> 8); + data[1] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == OV5693_8BIT) + *val = (u8)data[0]; + else if (data_length == OV5693_16BIT) + *val = be16_to_cpu(*(__be16 *)&data[0]); + else + *val = be32_to_cpu(*(__be32 *)&data[0]); + + return 0; +} + +static int ov5693_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int vcm_dw_i2c_write(struct i2c_client *client, u16 data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + __be16 val; + + val = cpu_to_be16(data); + msg.addr = VCM_ADDR; + msg.flags = 0; + msg.len = OV5693_16BIT; + msg.buf = (void *)&val; + + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +/* + * Theory: per datasheet, the two VCMs both allow for a 2-byte read. + * The DW9714 doesn't actually specify what this does (it has a + * two-byte write-only protocol, but specifies the read sequence as + * legal), but it returns the same data (zeroes) always, after an + * undocumented initial NAK. The AD5823 has a one-byte address + * register to which all writes go, and subsequent reads will cycle + * through the 8 bytes of registers. Notably, the default values (the + * device is always power-cycled affirmatively, so we can rely on + * these) in AD5823 are not pairwise repetitions of the same 16 bit + * word. So all we have to do is sequentially read two bytes at a + * time and see if we detect a difference in any of the first four + * pairs. + */ +static int vcm_detect(struct i2c_client *client) +{ + int i, ret; + struct i2c_msg msg; + u16 data0 = 0, data; + + for (i = 0; i < 4; i++) { + msg.addr = VCM_ADDR; + msg.flags = I2C_M_RD; + msg.len = sizeof(data); + msg.buf = (u8 *)&data; + ret = i2c_transfer(client->adapter, &msg, 1); + + /* + * DW9714 always fails the first read and returns + * zeroes for subsequent ones + */ + if (i == 0 && ret == -EREMOTEIO) { + data0 = 0; + continue; + } + + if (i == 0) + data0 = data; + + if (data != data0) + return VCM_AD5823; + } + return ret == 1 ? VCM_DW9714 : ret; +} + +static int ov5693_write_reg(struct i2c_client *client, u16 data_length, + u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + __be16 *wreg = (void *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != OV5693_8BIT && data_length != OV5693_16BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == OV5693_8BIT) { + data[2] = (u8)(val); + } else { + /* OV5693_16BIT */ + __be16 *wdata = (void *)&data[2]; + + *wdata = cpu_to_be16(val); + } + + ret = ov5693_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov5693_write_reg_array - Initializes a list of OV5693 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov5693_flush_reg_array, __ov5693_buf_reg_array() and + * __ov5693_write_reg_is_consecutive() are internal functions to + * ov5693_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __ov5693_flush_reg_array(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl) +{ + u16 size; + __be16 *reg = (void *)&ctrl->buffer.addr; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + + *reg = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov5693_i2c_write(client, size, (u8 *)reg); +} + +static int __ov5693_buf_reg_array(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl, + const struct ov5693_reg *next) +{ + int size; + __be16 *data16; + + switch (next->type) { + case OV5693_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV5693_16BIT: + size = 2; + + data16 = (void *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV5693_MAX_WRITE_BUF_SIZE) + return __ov5693_flush_reg_array(client, ctrl); + + return 0; +} + +static int __ov5693_write_reg_is_consecutive(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl, + const struct ov5693_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int ov5693_write_reg_array(struct i2c_client *client, + const struct ov5693_reg *reglist) +{ + const struct ov5693_reg *next = reglist; + struct ov5693_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != OV5693_TOK_TERM; next++) { + switch (next->type & OV5693_TOK_MASK) { + case OV5693_TOK_DELAY: + err = __ov5693_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__ov5693_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __ov5693_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov5693_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, + "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __ov5693_flush_reg_array(client, &ctrl); +} + +static int ov5693_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV5693_FOCAL_LENGTH_NUM << 16) | OV5693_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov5693_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (OV5693_F_NUMBER_DEFAULT_NUM << 16) | OV5693_F_NUMBER_DEM; + return 0; +} + +static int ov5693_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV5693_F_NUMBER_DEFAULT_NUM << 24) | + (OV5693_F_NUMBER_DEM << 16) | + (OV5693_F_NUMBER_DEFAULT_NUM << 8) | OV5693_F_NUMBER_DEM; + return 0; +} + +static int ov5693_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + *val = ov5693_res[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int ov5693_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + *val = ov5693_res[dev->fmt_idx].bin_factor_y; + + return 0; +} + +static int ov5693_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov5693_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + unsigned int pix_clk_freq_hz; + u16 reg_val; + int ret; + + if (!info) + return -EINVAL; + + /* pixel clock */ + pix_clk_freq_hz = res->pix_clk_freq * 1000000; + + dev->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV5693_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV5693_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV5693_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV5693_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV5693_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __ov5693_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + u16 vts, hts; + int ret, exp_val; + + hts = ov5693_res[dev->fmt_idx].pixels_per_line; + vts = ov5693_res[dev->fmt_idx].lines_per_frame; + /* + * If coarse_itg is larger than 1<<15, can not write to reg directly. + * The way is to write coarse_itg/2 to the reg, meanwhile write 2*hts + * to the reg. + */ + if (coarse_itg > (1 << 15)) { + hts = hts * 2; + coarse_itg = (int)coarse_itg / 2; + } + /* group hold */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0x00); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_GROUP_ACCESS); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_HTS_H, (hts >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_HTS_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_HTS_L, hts & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_HTS_L); + return ret; + } + /* Increase the VTS to match exposure + MARGIN */ + if (coarse_itg > vts - OV5693_INTEGRATION_TIME_MARGIN) + vts = (u16)coarse_itg + OV5693_INTEGRATION_TIME_MARGIN; + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_VTS_H, (vts >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_VTS_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_VTS_L, vts & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_VTS_L); + return ret; + } + + /* set exposure */ + + /* Lower four bit should be 0*/ + exp_val = coarse_itg << 4; + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_L, exp_val & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_L); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_M, (exp_val >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_M); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_H, (exp_val >> 16) & 0x0F); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_H); + return ret; + } + + /* Analog gain */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_AGC_L, gain & 0xff); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_AGC_L); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_AGC_H, (gain >> 8) & 0xff); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_AGC_H); + return ret; + } + + /* Digital gain */ + if (digitgain) { + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_RED_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_GREEN_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_BLUE_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + } + + /* End group */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0x10); + if (ret) + return ret; + + /* Delay launch group */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0xa0); + if (ret) + return ret; + return ret; +} + +static int ov5693_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov5693_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov5693_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + u16 coarse_itg = exposure->integration_time[0]; + u16 analog_gain = exposure->gain[0]; + u16 digital_gain = exposure->gain[1]; + + /* we should not accept the invalid value below */ + if (analog_gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + return ov5693_set_exposure(sd, coarse_itg, analog_gain, digital_gain); +} + +static int ov5693_read_otp_reg_array(struct i2c_client *client, u16 size, + u16 addr, u8 *buf) +{ + u16 index; + int ret; + u16 *pVal = NULL; + + for (index = 0; index <= size; index++) { + pVal = (u16 *)(buf + index); + ret = + ov5693_read_reg(client, OV5693_8BIT, addr + index, + pVal); + if (ret) + return ret; + } + + return 0; +} + +static int __ov5693_otp_read(struct v4l2_subdev *sd, u8 *buf) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + int ret; + int i; + u8 *b = buf; + + dev->otp_size = 0; + for (i = 1; i < OV5693_OTP_BANK_MAX; i++) { + /*set bank NO and OTP read mode. */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_OTP_BANK_REG, + (i | 0xc0)); //[7:6] 2'b11 [5:0] bank no + if (ret) { + dev_err(&client->dev, "failed to prepare OTP page\n"); + return ret; + } + //pr_debug("write 0x%x->0x%x\n",OV5693_OTP_BANK_REG,(i|0xc0)); + + /*enable read */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_OTP_READ_REG, + OV5693_OTP_MODE_READ); // enable :1 + if (ret) { + dev_err(&client->dev, + "failed to set OTP reading mode page"); + return ret; + } + //pr_debug("write 0x%x->0x%x\n",OV5693_OTP_READ_REG,OV5693_OTP_MODE_READ); + + /* Reading the OTP data array */ + ret = ov5693_read_otp_reg_array(client, OV5693_OTP_BANK_SIZE, + OV5693_OTP_START_ADDR, + b); + if (ret) { + dev_err(&client->dev, "failed to read OTP data\n"); + return ret; + } + + //pr_debug("BANK[%2d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", i, *b, *(b+1), *(b+2), *(b+3), *(b+4), *(b+5), *(b+6), *(b+7), *(b+8), *(b+9), *(b+10), *(b+11), *(b+12), *(b+13), *(b+14), *(b+15)); + + //Intel OTP map, try to read 320byts first. + if (i == 21) { + if ((*b) == 0) { + dev->otp_size = 320; + break; + } else { + b = buf; + continue; + } + } else if (i == + 24) { //if the first 320bytes data doesn't not exist, try to read the next 32bytes data. + if ((*b) == 0) { + dev->otp_size = 32; + break; + } else { + b = buf; + continue; + } + } else if (i == + 27) { //if the prvious 32bytes data doesn't exist, try to read the next 32bytes data again. + if ((*b) == 0) { + dev->otp_size = 32; + break; + } else { + dev->otp_size = 0; // no OTP data. + break; + } + } + + b = b + OV5693_OTP_BANK_SIZE; + } + return 0; +} + +/* + * Read otp data and store it into a kmalloced buffer. + * The caller must kfree the buffer when no more needed. + * @size: set to the size of the returned otp data. + */ +static void *ov5693_otp_read(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + + buf = devm_kzalloc(&client->dev, (OV5693_OTP_DATA_SIZE + 16), GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + //otp valid after mipi on and sw stream on + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_FRAME_OFF_NUM, 0x00); + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_STREAM, OV5693_START_STREAMING); + + ret = __ov5693_otp_read(sd, buf); + + //mipi off and sw stream off after otp read + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_FRAME_OFF_NUM, 0x0f); + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_STREAM, OV5693_STOP_STREAMING); + + /* Driver has failed to find valid data */ + if (ret) { + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); + } + + return buf; +} + +static int ov5693_g_priv_int_data(struct v4l2_subdev *sd, + struct v4l2_private_int_data *priv) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + u8 __user *to = priv->data; + u32 read_size = priv->size; + int ret; + + /* No need to copy data if size is 0 */ + if (!read_size) + goto out; + + if (IS_ERR(dev->otp_data)) { + dev_err(&client->dev, "OTP data not available"); + return PTR_ERR(dev->otp_data); + } + + /* Correct read_size value only if bigger than maximum */ + if (read_size > OV5693_OTP_DATA_SIZE) + read_size = OV5693_OTP_DATA_SIZE; + + ret = copy_to_user(to, dev->otp_data, read_size); + if (ret) { + dev_err(&client->dev, "%s: failed to copy OTP data to user\n", + __func__); + return -EFAULT; + } + + pr_debug("%s read_size:%d\n", __func__, read_size); + +out: + /* Return correct size */ + priv->size = dev->otp_size; + + return 0; +} + +static long ov5693_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov5693_s_exposure(sd, arg); + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + return ov5693_g_priv_int_data(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* + * This returns the exposure time being used. This should only be used + * for filling in EXIF data, not for actual image processing. + */ +static int ov5693_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_L, + ®_v); + if (ret) + goto err; + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_M, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_H, + ®_v2); + if (ret) + goto err; + + *value = reg_v + (((u32)reg_v2 << 16)); +err: + return ret; +} + +static int ad5823_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 vcm_code; + + ret = ad5823_i2c_read(client, AD5823_REG_VCM_CODE_MSB, &vcm_code); + if (ret) + return ret; + + /* set reg VCM_CODE_MSB Bit[1:0] */ + vcm_code = (vcm_code & VCM_CODE_MSB_MASK) | + ((val >> 8) & ~VCM_CODE_MSB_MASK); + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_MSB, vcm_code); + if (ret) + return ret; + + /* set reg VCM_CODE_LSB Bit[7:0] */ + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_LSB, (val & 0xff)); + if (ret) + return ret; + + /* set required vcm move time */ + vcm_code = AD5823_RESONANCE_PERIOD / AD5823_RESONANCE_COEF + - AD5823_HIGH_FREQ_RANGE; + ret = ad5823_i2c_write(client, AD5823_REG_VCM_MOVE_TIME, vcm_code); + + return ret; +} + +static int ad5823_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + value = min(value, AD5823_MAX_FOCUS_POS); + return ad5823_t_focus_vcm(sd, value); +} + +static int ov5693_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + dev_dbg(&client->dev, "%s: FOCUS_POS: 0x%x\n", __func__, value); + value = clamp(value, 0, OV5693_VCM_MAX_FOCUS_POS); + if (dev->vcm == VCM_DW9714) { + if (dev->vcm_update) { + ret = vcm_dw_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = vcm_dw_i2c_write(client, DIRECT_VCM); + if (ret) + return ret; + ret = vcm_dw_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dev->vcm_update = false; + } + ret = vcm_dw_i2c_write(client, + vcm_val(value, VCM_DEFAULT_S)); + } else if (dev->vcm == VCM_AD5823) { + ad5823_t_focus_abs(sd, value); + } + if (ret == 0) { + dev->number_of_steps = value - dev->focus; + dev->focus = value; + dev->timestamp_t_focus_abs = ktime_get(); + } else + dev_err(&client->dev, + "%s: i2c failed. ret %d\n", __func__, ret); + + return ret; +} + +static int ov5693_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + return ov5693_t_focus_abs(sd, dev->focus + value); +} + +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) +static int ov5693_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct ov5693_device *dev = to_ov5693_sensor(sd); + ktime_t temptime; + ktime_t timedelay = ns_to_ktime(min_t(u32, + abs(dev->number_of_steps) * DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS)); + + temptime = ktime_sub(ktime_get(), (dev->timestamp_t_focus_abs)); + if (ktime_compare(temptime, timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + + *value = status; + + return 0; +} + +static int ov5693_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + s32 val; + + ov5693_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = dev->focus - dev->number_of_steps; + else + *value = dev->focus; + + return 0; +} + +static int ov5693_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + dev->number_of_steps = value; + dev->vcm_update = true; + return 0; +} + +static int ov5693_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + dev->number_of_steps = value; + dev->vcm_update = true; + return 0; +} + +static int ov5693_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov5693_device *dev = + container_of(ctrl->handler, struct ov5693_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FOCUS_ABSOLUTE: + dev_dbg(&client->dev, "%s: CID_FOCUS_ABSOLUTE:%d.\n", + __func__, ctrl->val); + ret = ov5693_t_focus_abs(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_RELATIVE: + dev_dbg(&client->dev, "%s: CID_FOCUS_RELATIVE:%d.\n", + __func__, ctrl->val); + ret = ov5693_t_focus_rel(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_SLEW: + ret = ov5693_t_vcm_slew(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_TIMING: + ret = ov5693_t_vcm_timing(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int ov5693_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov5693_device *dev = + container_of(ctrl->handler, struct ov5693_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov5693_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov5693_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov5693_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov5693_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = ov5693_q_focus_abs(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_STATUS: + ret = ov5693_q_focus_status(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = ov5693_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = ov5693_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ov5693_s_ctrl, + .g_volatile_ctrl = ov5693_g_volatile_ctrl +}; + +static const struct v4l2_ctrl_config ov5693_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV5693_FOCAL_LENGTH_DEFAULT, + .max = OV5693_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV5693_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV5693_F_NUMBER_DEFAULT, + .max = OV5693_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV5693_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV5693_F_NUMBER_RANGE, + .max = OV5693_F_NUMBER_RANGE, + .step = 0x01, + .def = OV5693_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move absolute", + .min = 0, + .max = OV5693_VCM_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_RELATIVE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move relative", + .min = OV5693_VCM_MAX_FOCUS_NEG, + .max = OV5693_VCM_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus status", + .min = 0, + .max = 100, /* allow enum to grow in the future */ + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_SLEW, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm slew", + .min = 0, + .max = OV5693_VCM_SLEW_STEP_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_TIMING, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm step time", + .min = 0, + .max = OV5693_VCM_SLEW_TIME_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = OV5693_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = OV5693_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int ov5693_init(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("%s\n", __func__); + mutex_lock(&dev->input_lock); + dev->vcm_update = false; + + if (dev->vcm == VCM_AD5823) { + ret = vcm_ad_i2c_wr8(client, 0x01, 0x01); /* vcm init test */ + if (ret) + dev_err(&client->dev, + "vcm reset failed\n"); + /*change the mode*/ + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_MSB, + AD5823_RING_CTRL_ENABLE); + if (ret) + dev_err(&client->dev, + "vcm enable ringing failed\n"); + ret = ad5823_i2c_write(client, AD5823_REG_MODE, + AD5823_ARC_RES1); + if (ret) + dev_err(&client->dev, + "vcm change mode failed\n"); + } + + /*change initial focus value for ad5823*/ + if (dev->vcm == VCM_AD5823) { + dev->focus = AD5823_INIT_FOCUS_POS; + ov5693_t_focus_abs(sd, AD5823_INIT_FOCUS_POS); + } else { + dev->focus = 0; + ov5693_t_focus_abs(sd, 0); + } + + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct ov5693_device *dev = to_ov5693_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* + * This driver assumes "internal DVDD, PWDNB tied to DOVDD". + * In this set up only gpio0 (XSHUTDN) should be available + * but in some products (for example ECS) gpio1 (PWDNB) is + * also available. If gpio1 is available we emulate it being + * tied to DOVDD here. + */ + if (flag) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + dev->platform_data->gpio1_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret) { + dev->platform_data->gpio1_ctrl(sd, 0); + ret = dev->platform_data->v2p8_ctrl(sd, 0); + } + } + } else { + dev->platform_data->gpio1_ctrl(sd, 0); + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + return dev->platform_data->gpio0_ctrl(sd, flag); +} + +static int __power_up(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + /* add this delay time to 10~11ms*/ + usleep_range(10000, 11000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + __cci_delay(up_delay); + + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + dev->focus = OV5693_INVALID_CONFIG; + if (!dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + static const int retry_count = 4; + int i, ret; + + for (i = 0; i < retry_count; i++) { + ret = __power_up(sd); + if (!ret) + return 0; + + power_down(sd); + } + return ret; +} + +static int ov5693_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + pr_info("%s: on %d\n", __func__, on); + if (on == 0) + return power_down(sd); + else { + ret = power_up(sd); + if (!ret) { + ret = ov5693_init(sd); + /* restore settings */ + ov5693_res = ov5693_res_preview; + N_RES = N_RES_PREVIEW; + } + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between res_w/res_h and w/h. + * distance = (res_w/res_h - w/h) / (w/h) * 8192 + * res->width/height smaller than w/h wouldn't be considered. + * The gap of ratio larger than 1/8 wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 1024 +static int distance(struct ov5693_resolution *res, u32 w, u32 h) +{ + int ratio; + int distance; + + if (w == 0 || h == 0 || + res->width < w || res->height < h) + return -1; + + ratio = res->width << 13; + ratio /= w; + ratio *= h; + ratio /= res->height; + + distance = abs(ratio - 8192); + + if (distance > LARGEST_ALLOWED_RATIO_MISMATCH) + return -1; + + return distance; +} + +/* Return the nearest higher resolution index + * Firstly try to find the approximate aspect ratio resolution + * If we find multiple same AR resolutions, choose the + * minimal size. + */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + int min_res_w = INT_MAX; + struct ov5693_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &ov5693_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + min_res_w = ov5693_res[i].width; + continue; + } + if (dist == min_dist && ov5693_res[i].width < min_res_w) + idx = i; + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != ov5693_res[i].width) + continue; + if (h != ov5693_res[i].height) + continue; + + return i; + } + + return -1; +} + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_RESET, 0x01); + if (ret) { + dev_err(&client->dev, "ov5693 reset err.\n"); + return ret; + } + + ret = ov5693_write_reg_array(client, ov5693_global_setting); + if (ret) { + dev_err(&client->dev, "ov5693 write register err.\n"); + return ret; + } + + ret = ov5693_write_reg_array(client, ov5693_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "ov5693 write register err.\n"); + return ret; + } + + return ret; +} + +static int ov5693_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *ov5693_info = NULL; + int ret = 0; + int idx; + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + ov5693_info = v4l2_get_subdev_hostdata(sd); + if (!ov5693_info) + return -EINVAL; + + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = ov5693_res[N_RES - 1].width; + fmt->height = ov5693_res[N_RES - 1].height; + } else { + fmt->width = ov5693_res[idx].width; + fmt->height = ov5693_res[idx].height; + } + + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + sd_state->pads->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + ret = startup(sd); + if (ret) { + int i = 0; + + dev_err(&client->dev, "ov5693 startup err, retry to power up\n"); + for (i = 0; i < OV5693_POWER_UP_RETRY_NUM; i++) { + dev_err(&client->dev, + "ov5693 retry to power up %d/%d times, result: ", + i + 1, OV5693_POWER_UP_RETRY_NUM); + power_down(sd); + ret = power_up(sd); + if (!ret) { + mutex_unlock(&dev->input_lock); + ov5693_init(sd); + mutex_lock(&dev->input_lock); + } else { + dev_err(&client->dev, "power up failed, continue\n"); + continue; + } + ret = startup(sd); + if (ret) { + dev_err(&client->dev, " startup FAILED!\n"); + } else { + dev_err(&client->dev, " startup SUCCESS!\n"); + break; + } + } + } + + /* + * After sensor settings are set to HW, sometimes stream is started. + * This would cause ISP timeout because ISP is not ready to receive + * data yet. So add stop streaming here. + */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_SW_STREAM, + OV5693_STOP_STREAMING); + if (ret) + dev_warn(&client->dev, "ov5693 stream off err\n"); + + ret = ov5693_get_intg_factor(client, ov5693_info, + &ov5693_res[dev->fmt_idx]); + if (ret) { + dev_err(&client->dev, "failed to get integration_factor\n"); + goto err; + } + + ov5693_info->metadata_width = fmt->width * 10 / 8; + ov5693_info->metadata_height = 1; + ov5693_info->metadata_effective_width = &ov5693_embedded_effective_size; + +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov5693_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov5693_device *dev = to_ov5693_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = ov5693_res[dev->fmt_idx].width; + fmt->height = ov5693_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov5693_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_CHIP_ID_L, &low); + if (ret) + return ret; + id = ((((u16)high) << 8) | (u16)low); + + if (id != OV5693_ID) { + dev_err(&client->dev, "sensor ID error 0x%x\n", id); + return -ENODEV; + } + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_SUB_ID, &high); + revision = (u8)high & 0x0f; + + dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision); + dev_dbg(&client->dev, "detect ov5693 success\n"); + return 0; +} + +static int ov5693_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_SW_STREAM, + enable ? OV5693_START_STREAMING : + OV5693_STOP_STREAMING); + + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ov5693_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (!platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-up err.\n"); + goto fail_power_on; + } + + if (!dev->vcm) + dev->vcm = vcm_detect(client); + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov5693_detect(client); + if (ret) { + dev_err(&client->dev, "ov5693_detect err s_config.\n"); + goto fail_csi_cfg; + } + + dev->otp_data = ov5693_otp_read(sd); + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return ret; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov5693_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = ov5693_res[dev->fmt_idx].fps; + + return 0; +} + +static int ov5693_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov5693_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = ov5693_res[index].width; + fse->min_height = ov5693_res[index].height; + fse->max_width = ov5693_res[index].width; + fse->max_height = ov5693_res[index].height; + + return 0; +} + +static const struct v4l2_subdev_video_ops ov5693_video_ops = { + .s_stream = ov5693_s_stream, + .g_frame_interval = ov5693_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ov5693_core_ops = { + .s_power = ov5693_s_power, + .ioctl = ov5693_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov5693_pad_ops = { + .enum_mbus_code = ov5693_enum_mbus_code, + .enum_frame_size = ov5693_enum_frame_size, + .get_fmt = ov5693_get_fmt, + .set_fmt = ov5693_set_fmt, +}; + +static const struct v4l2_subdev_ops ov5693_ops = { + .core = &ov5693_core_ops, + .video = &ov5693_video_ops, + .pad = &ov5693_pad_ops, +}; + +static void ov5693_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5693_device *dev = to_ov5693_sensor(sd); + + dev_dbg(&client->dev, "ov5693_remove...\n"); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); +} + +static int ov5693_probe(struct i2c_client *client) +{ + struct ov5693_device *dev; + int i2c; + int ret; + void *pdata; + unsigned int i; + + /* + * Firmware workaround: Some modules use a "secondary default" + * address of 0x10 which doesn't appear on schematics, and + * some BIOS versions haven't gotten the memo. Work around + * via config. + */ + i2c = gmin_get_var_int(&client->dev, false, "I2CAddr", -1); + if (i2c != -1) { + dev_info(&client->dev, + "Overriding firmware-provided I2C address (0x%x) with 0x%x\n", + client->addr, i2c); + client->addr = i2c; + } + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&dev->sd, client, &ov5693_ops); + + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_bggr); + if (!pdata) { + ret = -EINVAL; + goto out_free; + } + + ret = ov5693_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(ov5693_controls)); + if (ret) { + ov5693_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ov5693_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov5693_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + ov5693_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + ov5693_remove(client); + + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct acpi_device_id ov5693_acpi_match[] = { + {"INT33BE"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ov5693_acpi_match); + +static struct i2c_driver ov5693_driver = { + .driver = { + .name = "ov5693", + .acpi_match_table = ov5693_acpi_match, + }, + .probe_new = ov5693_probe, + .remove = ov5693_remove, +}; +module_i2c_driver(ov5693_driver); + +MODULE_DESCRIPTION("A low-level driver for OmniVision 5693 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h new file mode 100644 index 000000000..a1366666f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h @@ -0,0 +1,1392 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for OmniVision OV5693 5M camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __OV5693_H__ +#define __OV5693_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../include/linux/atomisp_platform.h" + +/* + * FIXME: non-preview resolutions are currently broken + */ +#define ENABLE_NON_PREVIEW 0 + +#define OV5693_POWER_UP_RETRY_NUM 5 + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV5693_FOCAL_LENGTH_NUM 334 /*3.34mm*/ +#define OV5693_FOCAL_LENGTH_DEM 100 +#define OV5693_F_NUMBER_DEFAULT_NUM 24 +#define OV5693_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* sensor_mode_data read_mode adaptation */ +#define OV5693_READ_MODE_BINNING_ON 0x0400 +#define OV5693_READ_MODE_BINNING_OFF 0x00 +#define OV5693_INTEGRATION_TIME_MARGIN 8 + +#define OV5693_MAX_EXPOSURE_VALUE 0xFFF1 +#define OV5693_MAX_GAIN_VALUE 0xFF + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV5693_FOCAL_LENGTH_DEFAULT 0x1B70064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV5693_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV5693_F_NUMBER_RANGE 0x180a180a +#define OV5693_ID 0x5690 + +#define OV5693_FINE_INTG_TIME_MIN 0 +#define OV5693_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV5693_COARSE_INTG_TIME_MIN 1 +#define OV5693_COARSE_INTG_TIME_MAX_MARGIN 6 + +#define OV5693_BIN_FACTOR_MAX 4 +/* + * OV5693 System control registers + */ +#define OV5693_SW_SLEEP 0x0100 +#define OV5693_SW_RESET 0x0103 +#define OV5693_SW_STREAM 0x0100 + +#define OV5693_SC_CMMN_CHIP_ID_H 0x300A +#define OV5693_SC_CMMN_CHIP_ID_L 0x300B +#define OV5693_SC_CMMN_SCCB_ID 0x300C +#define OV5693_SC_CMMN_SUB_ID 0x302A /* process, version*/ +/*Bit[7:4] Group control, Bit[3:0] Group ID*/ +#define OV5693_GROUP_ACCESS 0x3208 +/* +*Bit[3:0] Bit[19:16] of exposure, +*remaining 16 bits lies in Reg0x3501&Reg0x3502 +*/ +#define OV5693_EXPOSURE_H 0x3500 +#define OV5693_EXPOSURE_M 0x3501 +#define OV5693_EXPOSURE_L 0x3502 +/*Bit[1:0] means Bit[9:8] of gain*/ +#define OV5693_AGC_H 0x350A +#define OV5693_AGC_L 0x350B /*Bit[7:0] of gain*/ + +#define OV5693_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/ +#define OV5693_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/ +#define OV5693_VERTICAL_START_H 0x3802 /*Bit[11:8]*/ +#define OV5693_VERTICAL_START_L 0x3803 /*Bit[7:0]*/ +#define OV5693_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/ +#define OV5693_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/ +#define OV5693_VERTICAL_END_H 0x3806 /*Bit[11:8]*/ +#define OV5693_VERTICAL_END_L 0x3807 /*Bit[7:0]*/ +#define OV5693_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/ +#define OV5693_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/ +#define OV5693_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/ +#define OV5693_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/ +/*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV5693_TIMING_HTS_H 0x380C +/*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV5693_TIMING_HTS_L 0x380D +/*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV5693_TIMING_VTS_H 0x380e +/*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV5693_TIMING_VTS_L 0x380f + +#define OV5693_MWB_RED_GAIN_H 0x3400 +#define OV5693_MWB_GREEN_GAIN_H 0x3402 +#define OV5693_MWB_BLUE_GAIN_H 0x3404 +#define OV5693_MWB_GAIN_MAX 0x0fff + +#define OV5693_START_STREAMING 0x01 +#define OV5693_STOP_STREAMING 0x00 + +#define VCM_ADDR 0x0c +#define VCM_CODE_MSB 0x04 + +#define OV5693_INVALID_CONFIG 0xffffffff + +#define OV5693_VCM_SLEW_STEP 0x30F0 +#define OV5693_VCM_SLEW_STEP_MAX 0x7 +#define OV5693_VCM_SLEW_STEP_MASK 0x7 +#define OV5693_VCM_CODE 0x30F2 +#define OV5693_VCM_SLEW_TIME 0x30F4 +#define OV5693_VCM_SLEW_TIME_MAX 0xffff +#define OV5693_VCM_ENABLE 0x8000 + +#define OV5693_VCM_MAX_FOCUS_NEG -1023 +#define OV5693_VCM_MAX_FOCUS_POS 1023 + +#define DLC_ENABLE 1 +#define DLC_DISABLE 0 +#define VCM_PROTECTION_OFF 0xeca3 +#define VCM_PROTECTION_ON 0xdc51 +#define VCM_DEFAULT_S 0x0 +#define vcm_step_s(a) (u8)(a & 0xf) +#define vcm_step_mclk(a) (u8)((a >> 4) & 0x3) +#define vcm_dlc_mclk(dlc, mclk) (u16)((dlc << 3) | mclk | 0xa104) +#define vcm_tsrc(tsrc) (u16)(tsrc << 3 | 0xf200) +#define vcm_val(data, s) (u16)(data << 4 | s) +#define DIRECT_VCM vcm_dlc_mclk(0, 0) + +/* Defines for OTP Data Registers */ +#define OV5693_FRAME_OFF_NUM 0x4202 +#define OV5693_OTP_BYTE_MAX 32 //change to 32 as needed by otpdata +#define OV5693_OTP_SHORT_MAX 16 +#define OV5693_OTP_START_ADDR 0x3D00 +#define OV5693_OTP_END_ADDR 0x3D0F +#define OV5693_OTP_DATA_SIZE 320 +#define OV5693_OTP_PROGRAM_REG 0x3D80 +#define OV5693_OTP_READ_REG 0x3D81 // 1:Enable 0:disable +#define OV5693_OTP_BANK_REG 0x3D84 //otp bank and mode +#define OV5693_OTP_READY_REG_DONE 1 +#define OV5693_OTP_BANK_MAX 28 +#define OV5693_OTP_BANK_SIZE 16 //16 bytes per bank +#define OV5693_OTP_READ_ONETIME 16 +#define OV5693_OTP_MODE_READ 1 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov5693_resolution { + u8 *desc; + const struct ov5693_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct ov5693_format { + u8 *desc; + u32 pixelformat; + struct ov5693_reg *regs; +}; + +enum vcm_type { + VCM_UNKNOWN, + VCM_AD5823, + VCM_DW9714, +}; + +/* + * ov5693 device structure. + */ +struct ov5693_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + + struct camera_sensor_platform_data *platform_data; + ktime_t timestamp_t_focus_abs; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + int otp_size; + u8 *otp_data; + u32 focus; + s16 number_of_steps; + u8 res; + u8 type; + bool vcm_update; + enum vcm_type vcm; +}; + +enum ov5693_tok_type { + OV5693_8BIT = 0x0001, + OV5693_16BIT = 0x0002, + OV5693_32BIT = 0x0004, + OV5693_TOK_TERM = 0xf000, /* terminating token for reg list */ + OV5693_TOK_DELAY = 0xfe00, /* delay token for reg list */ + OV5693_TOK_MASK = 0xfff0 +}; + +/** + * struct ov5693_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov5693_reg { + enum ov5693_tok_type type; + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_ov5693_sensor(x) container_of(x, struct ov5693_device, sd) + +#define OV5693_MAX_WRITE_BUF_SIZE 30 + +struct ov5693_write_buffer { + u16 addr; + u8 data[OV5693_MAX_WRITE_BUF_SIZE]; +}; + +struct ov5693_write_ctrl { + int index; + struct ov5693_write_buffer buffer; +}; + +static struct ov5693_reg const ov5693_global_setting[] = { + {OV5693_8BIT, 0x0103, 0x01}, + {OV5693_8BIT, 0x3001, 0x0a}, + {OV5693_8BIT, 0x3002, 0x80}, + {OV5693_8BIT, 0x3006, 0x00}, + {OV5693_8BIT, 0x3011, 0x21}, + {OV5693_8BIT, 0x3012, 0x09}, + {OV5693_8BIT, 0x3013, 0x10}, + {OV5693_8BIT, 0x3014, 0x00}, + {OV5693_8BIT, 0x3015, 0x08}, + {OV5693_8BIT, 0x3016, 0xf0}, + {OV5693_8BIT, 0x3017, 0xf0}, + {OV5693_8BIT, 0x3018, 0xf0}, + {OV5693_8BIT, 0x301b, 0xb4}, + {OV5693_8BIT, 0x301d, 0x02}, + {OV5693_8BIT, 0x3021, 0x00}, + {OV5693_8BIT, 0x3022, 0x01}, + {OV5693_8BIT, 0x3028, 0x44}, + {OV5693_8BIT, 0x3098, 0x02}, + {OV5693_8BIT, 0x3099, 0x19}, + {OV5693_8BIT, 0x309a, 0x02}, + {OV5693_8BIT, 0x309b, 0x01}, + {OV5693_8BIT, 0x309c, 0x00}, + {OV5693_8BIT, 0x30a0, 0xd2}, + {OV5693_8BIT, 0x30a2, 0x01}, + {OV5693_8BIT, 0x30b2, 0x00}, + {OV5693_8BIT, 0x30b3, 0x7d}, + {OV5693_8BIT, 0x30b4, 0x03}, + {OV5693_8BIT, 0x30b5, 0x04}, + {OV5693_8BIT, 0x30b6, 0x01}, + {OV5693_8BIT, 0x3104, 0x21}, + {OV5693_8BIT, 0x3106, 0x00}, + {OV5693_8BIT, 0x3400, 0x04}, + {OV5693_8BIT, 0x3401, 0x00}, + {OV5693_8BIT, 0x3402, 0x04}, + {OV5693_8BIT, 0x3403, 0x00}, + {OV5693_8BIT, 0x3404, 0x04}, + {OV5693_8BIT, 0x3405, 0x00}, + {OV5693_8BIT, 0x3406, 0x01}, + {OV5693_8BIT, 0x3500, 0x00}, + {OV5693_8BIT, 0x3503, 0x07}, + {OV5693_8BIT, 0x3504, 0x00}, + {OV5693_8BIT, 0x3505, 0x00}, + {OV5693_8BIT, 0x3506, 0x00}, + {OV5693_8BIT, 0x3507, 0x02}, + {OV5693_8BIT, 0x3508, 0x00}, + {OV5693_8BIT, 0x3509, 0x10}, + {OV5693_8BIT, 0x350a, 0x00}, + {OV5693_8BIT, 0x350b, 0x40}, + {OV5693_8BIT, 0x3601, 0x0a}, + {OV5693_8BIT, 0x3602, 0x38}, + {OV5693_8BIT, 0x3612, 0x80}, + {OV5693_8BIT, 0x3620, 0x54}, + {OV5693_8BIT, 0x3621, 0xc7}, + {OV5693_8BIT, 0x3622, 0x0f}, + {OV5693_8BIT, 0x3625, 0x10}, + {OV5693_8BIT, 0x3630, 0x55}, + {OV5693_8BIT, 0x3631, 0xf4}, + {OV5693_8BIT, 0x3632, 0x00}, + {OV5693_8BIT, 0x3633, 0x34}, + {OV5693_8BIT, 0x3634, 0x02}, + {OV5693_8BIT, 0x364d, 0x0d}, + {OV5693_8BIT, 0x364f, 0xdd}, + {OV5693_8BIT, 0x3660, 0x04}, + {OV5693_8BIT, 0x3662, 0x10}, + {OV5693_8BIT, 0x3663, 0xf1}, + {OV5693_8BIT, 0x3665, 0x00}, + {OV5693_8BIT, 0x3666, 0x20}, + {OV5693_8BIT, 0x3667, 0x00}, + {OV5693_8BIT, 0x366a, 0x80}, + {OV5693_8BIT, 0x3680, 0xe0}, + {OV5693_8BIT, 0x3681, 0x00}, + {OV5693_8BIT, 0x3700, 0x42}, + {OV5693_8BIT, 0x3701, 0x14}, + {OV5693_8BIT, 0x3702, 0xa0}, + {OV5693_8BIT, 0x3703, 0xd8}, + {OV5693_8BIT, 0x3704, 0x78}, + {OV5693_8BIT, 0x3705, 0x02}, + {OV5693_8BIT, 0x370a, 0x00}, + {OV5693_8BIT, 0x370b, 0x20}, + {OV5693_8BIT, 0x370c, 0x0c}, + {OV5693_8BIT, 0x370d, 0x11}, + {OV5693_8BIT, 0x370e, 0x00}, + {OV5693_8BIT, 0x370f, 0x40}, + {OV5693_8BIT, 0x3710, 0x00}, + {OV5693_8BIT, 0x371a, 0x1c}, + {OV5693_8BIT, 0x371b, 0x05}, + {OV5693_8BIT, 0x371c, 0x01}, + {OV5693_8BIT, 0x371e, 0xa1}, + {OV5693_8BIT, 0x371f, 0x0c}, + {OV5693_8BIT, 0x3721, 0x00}, + {OV5693_8BIT, 0x3724, 0x10}, + {OV5693_8BIT, 0x3726, 0x00}, + {OV5693_8BIT, 0x372a, 0x01}, + {OV5693_8BIT, 0x3730, 0x10}, + {OV5693_8BIT, 0x3738, 0x22}, + {OV5693_8BIT, 0x3739, 0xe5}, + {OV5693_8BIT, 0x373a, 0x50}, + {OV5693_8BIT, 0x373b, 0x02}, + {OV5693_8BIT, 0x373c, 0x41}, + {OV5693_8BIT, 0x373f, 0x02}, + {OV5693_8BIT, 0x3740, 0x42}, + {OV5693_8BIT, 0x3741, 0x02}, + {OV5693_8BIT, 0x3742, 0x18}, + {OV5693_8BIT, 0x3743, 0x01}, + {OV5693_8BIT, 0x3744, 0x02}, + {OV5693_8BIT, 0x3747, 0x10}, + {OV5693_8BIT, 0x374c, 0x04}, + {OV5693_8BIT, 0x3751, 0xf0}, + {OV5693_8BIT, 0x3752, 0x00}, + {OV5693_8BIT, 0x3753, 0x00}, + {OV5693_8BIT, 0x3754, 0xc0}, + {OV5693_8BIT, 0x3755, 0x00}, + {OV5693_8BIT, 0x3756, 0x1a}, + {OV5693_8BIT, 0x3758, 0x00}, + {OV5693_8BIT, 0x3759, 0x0f}, + {OV5693_8BIT, 0x376b, 0x44}, + {OV5693_8BIT, 0x375c, 0x04}, + {OV5693_8BIT, 0x3774, 0x10}, + {OV5693_8BIT, 0x3776, 0x00}, + {OV5693_8BIT, 0x377f, 0x08}, + {OV5693_8BIT, 0x3780, 0x22}, + {OV5693_8BIT, 0x3781, 0x0c}, + {OV5693_8BIT, 0x3784, 0x2c}, + {OV5693_8BIT, 0x3785, 0x1e}, + {OV5693_8BIT, 0x378f, 0xf5}, + {OV5693_8BIT, 0x3791, 0xb0}, + {OV5693_8BIT, 0x3795, 0x00}, + {OV5693_8BIT, 0x3796, 0x64}, + {OV5693_8BIT, 0x3797, 0x11}, + {OV5693_8BIT, 0x3798, 0x30}, + {OV5693_8BIT, 0x3799, 0x41}, + {OV5693_8BIT, 0x379a, 0x07}, + {OV5693_8BIT, 0x379b, 0xb0}, + {OV5693_8BIT, 0x379c, 0x0c}, + {OV5693_8BIT, 0x37c5, 0x00}, + {OV5693_8BIT, 0x37c6, 0x00}, + {OV5693_8BIT, 0x37c7, 0x00}, + {OV5693_8BIT, 0x37c9, 0x00}, + {OV5693_8BIT, 0x37ca, 0x00}, + {OV5693_8BIT, 0x37cb, 0x00}, + {OV5693_8BIT, 0x37de, 0x00}, + {OV5693_8BIT, 0x37df, 0x00}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3810, 0x00}, + {OV5693_8BIT, 0x3812, 0x00}, + {OV5693_8BIT, 0x3823, 0x00}, + {OV5693_8BIT, 0x3824, 0x00}, + {OV5693_8BIT, 0x3825, 0x00}, + {OV5693_8BIT, 0x3826, 0x00}, + {OV5693_8BIT, 0x3827, 0x00}, + {OV5693_8BIT, 0x382a, 0x04}, + {OV5693_8BIT, 0x3a04, 0x06}, + {OV5693_8BIT, 0x3a05, 0x14}, + {OV5693_8BIT, 0x3a06, 0x00}, + {OV5693_8BIT, 0x3a07, 0xfe}, + {OV5693_8BIT, 0x3b00, 0x00}, + {OV5693_8BIT, 0x3b02, 0x00}, + {OV5693_8BIT, 0x3b03, 0x00}, + {OV5693_8BIT, 0x3b04, 0x00}, + {OV5693_8BIT, 0x3b05, 0x00}, + {OV5693_8BIT, 0x3e07, 0x20}, + {OV5693_8BIT, 0x4000, 0x08}, + {OV5693_8BIT, 0x4001, 0x04}, + {OV5693_8BIT, 0x4002, 0x45}, + {OV5693_8BIT, 0x4004, 0x08}, + {OV5693_8BIT, 0x4005, 0x18}, + {OV5693_8BIT, 0x4006, 0x20}, + {OV5693_8BIT, 0x4008, 0x24}, + {OV5693_8BIT, 0x4009, 0x10}, + {OV5693_8BIT, 0x400c, 0x00}, + {OV5693_8BIT, 0x400d, 0x00}, + {OV5693_8BIT, 0x4058, 0x00}, + {OV5693_8BIT, 0x404e, 0x37}, + {OV5693_8BIT, 0x404f, 0x8f}, + {OV5693_8BIT, 0x4058, 0x00}, + {OV5693_8BIT, 0x4101, 0xb2}, + {OV5693_8BIT, 0x4303, 0x00}, + {OV5693_8BIT, 0x4304, 0x08}, + {OV5693_8BIT, 0x4307, 0x31}, + {OV5693_8BIT, 0x4311, 0x04}, + {OV5693_8BIT, 0x4315, 0x01}, + {OV5693_8BIT, 0x4511, 0x05}, + {OV5693_8BIT, 0x4512, 0x01}, + {OV5693_8BIT, 0x4806, 0x00}, + {OV5693_8BIT, 0x4816, 0x52}, + {OV5693_8BIT, 0x481f, 0x30}, + {OV5693_8BIT, 0x4826, 0x2c}, + {OV5693_8BIT, 0x4831, 0x64}, + {OV5693_8BIT, 0x4d00, 0x04}, + {OV5693_8BIT, 0x4d01, 0x71}, + {OV5693_8BIT, 0x4d02, 0xfd}, + {OV5693_8BIT, 0x4d03, 0xf5}, + {OV5693_8BIT, 0x4d04, 0x0c}, + {OV5693_8BIT, 0x4d05, 0xcc}, + {OV5693_8BIT, 0x4837, 0x0a}, + {OV5693_8BIT, 0x5000, 0x06}, + {OV5693_8BIT, 0x5001, 0x01}, + {OV5693_8BIT, 0x5003, 0x20}, + {OV5693_8BIT, 0x5046, 0x0a}, + {OV5693_8BIT, 0x5013, 0x00}, + {OV5693_8BIT, 0x5046, 0x0a}, + {OV5693_8BIT, 0x5780, 0x1c}, + {OV5693_8BIT, 0x5786, 0x20}, + {OV5693_8BIT, 0x5787, 0x10}, + {OV5693_8BIT, 0x5788, 0x18}, + {OV5693_8BIT, 0x578a, 0x04}, + {OV5693_8BIT, 0x578b, 0x02}, + {OV5693_8BIT, 0x578c, 0x02}, + {OV5693_8BIT, 0x578e, 0x06}, + {OV5693_8BIT, 0x578f, 0x02}, + {OV5693_8BIT, 0x5790, 0x02}, + {OV5693_8BIT, 0x5791, 0xff}, + {OV5693_8BIT, 0x5842, 0x01}, + {OV5693_8BIT, 0x5843, 0x2b}, + {OV5693_8BIT, 0x5844, 0x01}, + {OV5693_8BIT, 0x5845, 0x92}, + {OV5693_8BIT, 0x5846, 0x01}, + {OV5693_8BIT, 0x5847, 0x8f}, + {OV5693_8BIT, 0x5848, 0x01}, + {OV5693_8BIT, 0x5849, 0x0c}, + {OV5693_8BIT, 0x5e00, 0x00}, + {OV5693_8BIT, 0x5e10, 0x0c}, + {OV5693_8BIT, 0x0100, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; + +#if ENABLE_NON_PREVIEW +/* + * 654x496 30fps 17ms VBlanking 2lane 10Bit (Scaling) + */ +static struct ov5693_reg const ov5693_654x496[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0x90}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 1296x976 30fps 17ms VBlanking 2lane 10Bit (Scaling) +*DS from 2592x1952 +*/ +static struct ov5693_reg const ov5693_1296x976[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0x00}, + + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + + {OV5693_8BIT, 0x3808, 0x05}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x03}, + {OV5693_8BIT, 0x380b, 0xD0}, + + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + + {OV5693_8BIT, 0x3810, 0x00}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3812, 0x00}, + {OV5693_8BIT, 0x3813, 0x02}, + + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} + +}; + +/* + * 336x256 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2564x1956 + */ +static struct ov5693_reg const ov5693_336x256[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x01}, + {OV5693_8BIT, 0x3809, 0x50}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0x00}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x1E}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 336x256 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2368x1956 + */ +static struct ov5693_reg const ov5693_368x304[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3808, 0x01}, + {OV5693_8BIT, 0x3809, 0x70}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0x30}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x80}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * ov5693_192x160 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2460x1956 + */ +static struct ov5693_reg const ov5693_192x160[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x80}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + {OV5693_8BIT, 0x3808, 0x00}, + {OV5693_8BIT, 0x3809, 0xC0}, + {OV5693_8BIT, 0x380a, 0x00}, + {OV5693_8BIT, 0x380b, 0xA0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x40}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_736x496[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3803, 0x68}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0x3b}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0xe0}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0a}, /*hts*/ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /*vts*/ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; +#endif + +/* +static struct ov5693_reg const ov5693_736x496[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0xe0}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0d}, + {OV5693_8BIT, 0x380d, 0xb0}, + {OV5693_8BIT, 0x380e, 0x05}, + {OV5693_8BIT, 0x380f, 0xf2}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x01}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; +*/ +/* + * 976x556 30fps 8.8ms VBlanking 2lane 10Bit (Scaling) + */ +#if ENABLE_NON_PREVIEW +static struct ov5693_reg const ov5693_976x556[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x03}, + {OV5693_8BIT, 0x3809, 0xd0}, + {OV5693_8BIT, 0x380a, 0x02}, + {OV5693_8BIT, 0x380b, 0x2C}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/*DS from 2624x1492*/ +static struct ov5693_reg const ov5693_1296x736[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0x00}, + + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + + {OV5693_8BIT, 0x3808, 0x05}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x02}, + {OV5693_8BIT, 0x380b, 0xe0}, + + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + + {OV5693_8BIT, 0x3813, 0xE8}, + + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_1636p_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x06}, + {OV5693_8BIT, 0x3809, 0x64}, + {OV5693_8BIT, 0x380a, 0x04}, + {OV5693_8BIT, 0x380b, 0x48}, + {OV5693_8BIT, 0x380c, 0x0a}, /*hts*/ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /*vts*/ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x02}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; +#endif + +static struct ov5693_reg const ov5693_1616x1216_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x80}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /*{3800,3801} Array X start*/ + {OV5693_8BIT, 0x3801, 0x08}, /* 04 //{3800,3801} Array X start*/ + {OV5693_8BIT, 0x3802, 0x00}, /*{3802,3803} Array Y start*/ + {OV5693_8BIT, 0x3803, 0x04}, /* 00 //{3802,3803} Array Y start*/ + {OV5693_8BIT, 0x3804, 0x0a}, /*{3804,3805} Array X end*/ + {OV5693_8BIT, 0x3805, 0x37}, /* 3b //{3804,3805} Array X end*/ + {OV5693_8BIT, 0x3806, 0x07}, /*{3806,3807} Array Y end*/ + {OV5693_8BIT, 0x3807, 0x9f}, /* a3 //{3806,3807} Array Y end*/ + {OV5693_8BIT, 0x3808, 0x06}, /*{3808,3809} Final output H size*/ + {OV5693_8BIT, 0x3809, 0x50}, /*{3808,3809} Final output H size*/ + {OV5693_8BIT, 0x380a, 0x04}, /*{380a,380b} Final output V size*/ + {OV5693_8BIT, 0x380b, 0xc0}, /*{380a,380b} Final output V size*/ + {OV5693_8BIT, 0x380c, 0x0a}, /*{380c,380d} HTS*/ + {OV5693_8BIT, 0x380d, 0x80}, /*{380c,380d} HTS*/ + {OV5693_8BIT, 0x380e, 0x07}, /*{380e,380f} VTS*/ + {OV5693_8BIT, 0x380f, 0xc0}, /* bc //{380e,380f} VTS*/ + {OV5693_8BIT, 0x3810, 0x00}, /*{3810,3811} windowing X offset*/ + {OV5693_8BIT, 0x3811, 0x10}, /*{3810,3811} windowing X offset*/ + {OV5693_8BIT, 0x3812, 0x00}, /*{3812,3813} windowing Y offset*/ + {OV5693_8BIT, 0x3813, 0x06}, /*{3812,3813} windowing Y offset*/ + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, /*FLIP/Binning control*/ + {OV5693_8BIT, 0x3821, 0x1e}, /*MIRROR control*/ + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 1940x1096 30fps 8.8ms VBlanking 2lane 10bit (Scaling) + */ +#if ENABLE_NON_PREVIEW +static struct ov5693_reg const ov5693_1940x1096[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x07}, + {OV5693_8BIT, 0x3809, 0x94}, + {OV5693_8BIT, 0x380a, 0x04}, + {OV5693_8BIT, 0x380b, 0x48}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x02}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_2592x1456_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa4}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x20}, + {OV5693_8BIT, 0x380a, 0x05}, + {OV5693_8BIT, 0x380b, 0xb0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; +#endif + +static struct ov5693_reg const ov5693_2576x1456_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa4}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x05}, + {OV5693_8BIT, 0x380b, 0xb0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x18}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 2592x1944 30fps 0.6ms VBlanking 2lane 10Bit + */ +#if ENABLE_NON_PREVIEW +static struct ov5693_reg const ov5693_2592x1944_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x20}, + {OV5693_8BIT, 0x380a, 0x07}, + {OV5693_8BIT, 0x380b, 0x98}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; +#endif + +/* + * 11:9 Full FOV Output, expected FOV Res: 2346x1920 + * ISP Effect Res: 1408x1152 + * Sensor out: 1424x1168, DS From: 2380x1952 + * + * WA: Left Offset: 8, Hor scal: 64 + */ +#if ENABLE_NON_PREVIEW +static struct ov5693_reg const ov5693_1424x1168_30fps[] = { + {OV5693_8BIT, 0x3501, 0x3b}, /* long exposure[15:8] */ + {OV5693_8BIT, 0x3502, 0x80}, /* long exposure[7:0] */ + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /* TIMING_X_ADDR_START */ + {OV5693_8BIT, 0x3801, 0x50}, /* 80 */ + {OV5693_8BIT, 0x3802, 0x00}, /* TIMING_Y_ADDR_START */ + {OV5693_8BIT, 0x3803, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3804, 0x09}, /* TIMING_X_ADDR_END */ + {OV5693_8BIT, 0x3805, 0xdd}, /* 2525 */ + {OV5693_8BIT, 0x3806, 0x07}, /* TIMING_Y_ADDR_END */ + {OV5693_8BIT, 0x3807, 0xa1}, /* 1953 */ + {OV5693_8BIT, 0x3808, 0x05}, /* TIMING_X_OUTPUT_SIZE */ + {OV5693_8BIT, 0x3809, 0x90}, /* 1424 */ + {OV5693_8BIT, 0x380a, 0x04}, /* TIMING_Y_OUTPUT_SIZE */ + {OV5693_8BIT, 0x380b, 0x90}, /* 1168 */ + {OV5693_8BIT, 0x380c, 0x0a}, /* TIMING_HTS */ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /* TIMING_VTS */ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3810, 0x00}, /* TIMING_ISP_X_WIN */ + {OV5693_8BIT, 0x3811, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3812, 0x00}, /* TIMING_ISP_Y_WIN */ + {OV5693_8BIT, 0x3813, 0x00}, /* 0 */ + {OV5693_8BIT, 0x3814, 0x11}, /* TIME_X_INC */ + {OV5693_8BIT, 0x3815, 0x11}, /* TIME_Y_INC */ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; +#endif + +/* + * 3:2 Full FOV Output, expected FOV Res: 2560x1706 + * ISP Effect Res: 720x480 + * Sensor out: 736x496, DS From 2616x1764 + */ +static struct ov5693_reg const ov5693_736x496_30fps[] = { + {OV5693_8BIT, 0x3501, 0x3b}, /* long exposure[15:8] */ + {OV5693_8BIT, 0x3502, 0x80}, /* long exposure[7:0] */ + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /* TIMING_X_ADDR_START */ + {OV5693_8BIT, 0x3801, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3802, 0x00}, /* TIMING_Y_ADDR_START */ + {OV5693_8BIT, 0x3803, 0x62}, /* 98 */ + {OV5693_8BIT, 0x3804, 0x0a}, /* TIMING_X_ADDR_END */ + {OV5693_8BIT, 0x3805, 0x3b}, /* 2619 */ + {OV5693_8BIT, 0x3806, 0x07}, /* TIMING_Y_ADDR_END */ + {OV5693_8BIT, 0x3807, 0x43}, /* 1859 */ + {OV5693_8BIT, 0x3808, 0x02}, /* TIMING_X_OUTPUT_SIZE */ + {OV5693_8BIT, 0x3809, 0xe0}, /* 736 */ + {OV5693_8BIT, 0x380a, 0x01}, /* TIMING_Y_OUTPUT_SIZE */ + {OV5693_8BIT, 0x380b, 0xf0}, /* 496 */ + {OV5693_8BIT, 0x380c, 0x0a}, /* TIMING_HTS */ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /* TIMING_VTS */ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3810, 0x00}, /* TIMING_ISP_X_WIN */ + {OV5693_8BIT, 0x3811, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3812, 0x00}, /* TIMING_ISP_Y_WIN */ + {OV5693_8BIT, 0x3813, 0x00}, /* 0 */ + {OV5693_8BIT, 0x3814, 0x11}, /* TIME_X_INC */ + {OV5693_8BIT, 0x3815, 0x11}, /* TIME_Y_INC */ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_2576x1936_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x07}, + {OV5693_8BIT, 0x380b, 0x90}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x18}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_resolution ov5693_res_preview[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_736x496_30fps, + }, + { + .desc = "ov5693_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1616x1216_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2576, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2576x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2576, + .height = 1936, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2576x1936_30fps, + }, +}; + +#define N_RES_PREVIEW (ARRAY_SIZE(ov5693_res_preview)) + +/* + * Disable non-preview configurations until the configuration selection is + * improved. + */ +#if ENABLE_NON_PREVIEW +struct ov5693_resolution ov5693_res_still[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_736x496_30fps, + }, + { + .desc = "ov5693_1424x1168_30fps", + .width = 1424, + .height = 1168, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1424x1168_30fps, + }, + { + .desc = "ov5693_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1616x1216_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1944, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1944_30fps, + }, +}; + +#define N_RES_STILL (ARRAY_SIZE(ov5693_res_still)) + +struct ov5693_resolution ov5693_res_video[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_736x496, + }, + { + .desc = "ov5693_336x256_30fps", + .width = 336, + .height = 256, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_336x256, + }, + { + .desc = "ov5693_368x304_30fps", + .width = 368, + .height = 304, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_368x304, + }, + { + .desc = "ov5693_192x160_30fps", + .width = 192, + .height = 160, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_192x160, + }, + { + .desc = "ov5693_1296x736_30fps", + .width = 1296, + .height = 736, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 0, + .regs = ov5693_1296x736, + }, + { + .desc = "ov5693_1296x976_30fps", + .width = 1296, + .height = 976, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 0, + .regs = ov5693_1296x976, + }, + { + .desc = "ov5693_1636P_30fps", + .width = 1636, + .height = 1096, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1636p_30fps, + }, + { + .desc = "ov5693_1080P_30fps", + .width = 1940, + .height = 1096, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1940x1096, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1944, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1944_30fps, + }, +}; + +#define N_RES_VIDEO (ARRAY_SIZE(ov5693_res_video)) +#endif + +static struct ov5693_resolution *ov5693_res = ov5693_res_preview; +static unsigned long N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/include/hmm/hmm.h b/drivers/staging/media/atomisp/include/hmm/hmm.h new file mode 100644 index 000000000..2bc323b34 --- /dev/null +++ b/drivers/staging/media/atomisp/include/hmm/hmm.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __HMM_H__ +#define __HMM_H__ + +#include +#include +#include +#include + +#include "hmm_common.h" +#include "hmm/hmm_bo.h" +#include "ia_css_types.h" + +#define mmgr_NULL ((ia_css_ptr)0) +#define mmgr_EXCEPTION ((ia_css_ptr) - 1) + +int hmm_init(void); +void hmm_cleanup(void); + +ia_css_ptr hmm_alloc(size_t bytes); +ia_css_ptr hmm_create_from_vmalloc_buf(size_t bytes, void *vmalloc_addr); + +void hmm_free(ia_css_ptr ptr); +int hmm_load(ia_css_ptr virt, void *data, unsigned int bytes); +int hmm_store(ia_css_ptr virt, const void *data, unsigned int bytes); +int hmm_set(ia_css_ptr virt, int c, unsigned int bytes); +int hmm_flush(ia_css_ptr virt, unsigned int bytes); + +/* + * get kernel memory physical address from ISP virtual address. + */ +phys_addr_t hmm_virt_to_phys(ia_css_ptr virt); + +/* + * map ISP memory starts with virt to kernel virtual address + * by using vmap. return NULL if failed. + * + * virt must be the start address of ISP memory (return by hmm_alloc), + * do not pass any other address. + */ +void *hmm_vmap(ia_css_ptr virt, bool cached); +void hmm_vunmap(ia_css_ptr virt); + +/* + * flush the cache for the vmapped buffer. + * if the buffer has not been vmapped, return directly. + */ +void hmm_flush_vmap(ia_css_ptr virt); + +/* + * map ISP memory starts with virt to specific vma. + * + * used for mmap operation. + * + * virt must be the start address of ISP memory (return by hmm_alloc), + * do not pass any other address. + */ +int hmm_mmap(struct vm_area_struct *vma, ia_css_ptr virt); + +extern struct hmm_bo_device bo_device; + +#endif diff --git a/drivers/staging/media/atomisp/include/hmm/hmm_bo.h b/drivers/staging/media/atomisp/include/hmm/hmm_bo.h new file mode 100644 index 000000000..b4c03e0ca --- /dev/null +++ b/drivers/staging/media/atomisp/include/hmm/hmm_bo.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __HMM_BO_H__ +#define __HMM_BO_H__ + +#include +#include +#include +#include +#include +#include "mmu/isp_mmu.h" +#include "hmm/hmm_common.h" +#include "ia_css_types.h" + +#define check_bodev_null_return(bdev, exp) \ + check_null_return(bdev, exp, \ + "NULL hmm_bo_device.\n") + +#define check_bodev_null_return_void(bdev) \ + check_null_return_void(bdev, \ + "NULL hmm_bo_device.\n") + +#define check_bo_status_yes_goto(bo, _status, label) \ + var_not_equal_goto((bo->status & (_status)), (_status), \ + label, \ + "HMM buffer status not contain %s.\n", \ + #_status) + +#define check_bo_status_no_goto(bo, _status, label) \ + var_equal_goto((bo->status & (_status)), (_status), \ + label, \ + "HMM buffer status contains %s.\n", \ + #_status) + +#define rbtree_node_to_hmm_bo(root_node) \ + container_of((root_node), struct hmm_buffer_object, node) + +#define list_to_hmm_bo(list_ptr) \ + list_entry((list_ptr), struct hmm_buffer_object, list) + +#define kref_to_hmm_bo(kref_ptr) \ + list_entry((kref_ptr), struct hmm_buffer_object, kref) + +#define check_bo_null_return(bo, exp) \ + check_null_return(bo, exp, "NULL hmm buffer object.\n") + +#define check_bo_null_return_void(bo) \ + check_null_return_void(bo, "NULL hmm buffer object.\n") + +#define ISP_VM_START 0x0 +#define ISP_VM_SIZE (0x7FFFFFFF) /* 2G address space */ +#define ISP_PTR_NULL NULL + +#define HMM_BO_DEVICE_INITED 0x1 + +enum hmm_bo_type { + HMM_BO_PRIVATE, + HMM_BO_VMALLOC, + HMM_BO_LAST, +}; + +#define HMM_BO_MASK 0x1 +#define HMM_BO_FREE 0x0 +#define HMM_BO_ALLOCED 0x1 +#define HMM_BO_PAGE_ALLOCED 0x2 +#define HMM_BO_BINDED 0x4 +#define HMM_BO_MMAPED 0x8 +#define HMM_BO_VMAPED 0x10 +#define HMM_BO_VMAPED_CACHED 0x20 +#define HMM_BO_ACTIVE 0x1000 + +struct hmm_bo_device { + struct isp_mmu mmu; + + /* start/pgnr/size is used to record the virtual memory of this bo */ + unsigned int start; + unsigned int pgnr; + unsigned int size; + + /* list lock is used to protect the entire_bo_list */ + spinlock_t list_lock; + int flag; + + /* linked list for entire buffer object */ + struct list_head entire_bo_list; + /* rbtree for maintain entire allocated vm */ + struct rb_root allocated_rbtree; + /* rbtree for maintain entire free vm */ + struct rb_root free_rbtree; + struct mutex rbtree_mutex; + struct kmem_cache *bo_cache; +}; + +struct hmm_buffer_object { + struct hmm_bo_device *bdev; + struct list_head list; + struct kref kref; + + struct page **pages; + + /* mutex protecting this BO */ + struct mutex mutex; + enum hmm_bo_type type; + int mmap_count; + int status; + void *vmap_addr; /* kernel virtual address by vmap */ + + struct rb_node node; + unsigned int start; + unsigned int end; + unsigned int pgnr; + /* + * When insert a bo which has the same pgnr with an existed + * bo node in the free_rbtree, using "prev & next" pointer + * to maintain a bo linked list instead of insert this bo + * into free_rbtree directly, it will make sure each node + * in free_rbtree has different pgnr. + * "prev & next" default is NULL. + */ + struct hmm_buffer_object *prev; + struct hmm_buffer_object *next; +}; + +struct hmm_buffer_object *hmm_bo_alloc(struct hmm_bo_device *bdev, + unsigned int pgnr); + +void hmm_bo_release(struct hmm_buffer_object *bo); + +int hmm_bo_device_init(struct hmm_bo_device *bdev, + struct isp_mmu_client *mmu_driver, + unsigned int vaddr_start, unsigned int size); + +/* + * clean up all hmm_bo_device related things. + */ +void hmm_bo_device_exit(struct hmm_bo_device *bdev); + +/* + * whether the bo device is inited or not. + */ +int hmm_bo_device_inited(struct hmm_bo_device *bdev); + +/* + * increse buffer object reference. + */ +void hmm_bo_ref(struct hmm_buffer_object *bo); + +/* + * decrese buffer object reference. if reference reaches 0, + * release function of the buffer object will be called. + * + * this call is also used to release hmm_buffer_object or its + * upper level object with it embedded in. you need to call + * this function when it is no longer used. + * + * Note: + * + * user dont need to care about internal resource release of + * the buffer object in the release callback, it will be + * handled internally. + * + * this call will only release internal resource of the buffer + * object but will not free the buffer object itself, as the + * buffer object can be both pre-allocated statically or + * dynamically allocated. so user need to deal with the release + * of the buffer object itself manually. below example shows + * the normal case of using the buffer object. + * + * struct hmm_buffer_object *bo = hmm_bo_create(bdev, pgnr); + * ...... + * hmm_bo_unref(bo); + * + * or: + * + * struct hmm_buffer_object bo; + * + * hmm_bo_init(bdev, &bo, pgnr, NULL); + * ... + * hmm_bo_unref(&bo); + */ +void hmm_bo_unref(struct hmm_buffer_object *bo); + +int hmm_bo_allocated(struct hmm_buffer_object *bo); + +/* + * Allocate/Free physical pages for the bo. Type indicates if the + * pages will be allocated by using video driver (for share buffer) + * or by ISP driver itself. + */ +int hmm_bo_alloc_pages(struct hmm_buffer_object *bo, + enum hmm_bo_type type, + void *vmalloc_addr); +void hmm_bo_free_pages(struct hmm_buffer_object *bo); +int hmm_bo_page_allocated(struct hmm_buffer_object *bo); + +/* + * bind/unbind the physical pages to a virtual address space. + */ +int hmm_bo_bind(struct hmm_buffer_object *bo); +void hmm_bo_unbind(struct hmm_buffer_object *bo); +int hmm_bo_binded(struct hmm_buffer_object *bo); + +/* + * vmap buffer object's pages to contiguous kernel virtual address. + * if the buffer has been vmaped, return the virtual address directly. + */ +void *hmm_bo_vmap(struct hmm_buffer_object *bo, bool cached); + +/* + * flush the cache for the vmapped buffer object's pages, + * if the buffer has not been vmapped, return directly. + */ +void hmm_bo_flush_vmap(struct hmm_buffer_object *bo); + +/* + * vunmap buffer object's kernel virtual address. + */ +void hmm_bo_vunmap(struct hmm_buffer_object *bo); + +/* + * mmap the bo's physical pages to specific vma. + * + * vma's address space size must be the same as bo's size, + * otherwise it will return -EINVAL. + * + * vma->vm_flags will be set to (VM_RESERVED | VM_IO). + */ +int hmm_bo_mmap(struct vm_area_struct *vma, + struct hmm_buffer_object *bo); + +/* + * find the buffer object by its virtual address vaddr. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_start( + struct hmm_bo_device *bdev, ia_css_ptr vaddr); + +/* + * find the buffer object by its virtual address. + * it does not need to be the start address of one bo, + * it can be an address within the range of one bo. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_in_range( + struct hmm_bo_device *bdev, ia_css_ptr vaddr); + +/* + * find the buffer object with kernel virtual address vaddr. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_vmap_start( + struct hmm_bo_device *bdev, const void *vaddr); + +#endif diff --git a/drivers/staging/media/atomisp/include/hmm/hmm_common.h b/drivers/staging/media/atomisp/include/hmm/hmm_common.h new file mode 100644 index 000000000..d8610b135 --- /dev/null +++ b/drivers/staging/media/atomisp/include/hmm/hmm_common.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __HMM_BO_COMMON_H__ +#define __HMM_BO_COMMON_H__ + +#define HMM_BO_NAME "HMM" + +/* + * some common use micros + */ +#define var_equal_return(var1, var2, exp, fmt, arg ...) \ + do { \ + if ((var1) == (var2)) { \ + dev_err(atomisp_dev, \ + fmt, ## arg); \ + return exp;\ + } \ + } while (0) + +#define var_equal_return_void(var1, var2, fmt, arg ...) \ + do { \ + if ((var1) == (var2)) { \ + dev_err(atomisp_dev, \ + fmt, ## arg); \ + return;\ + } \ + } while (0) + +#define var_equal_goto(var1, var2, label, fmt, arg ...) \ + do { \ + if ((var1) == (var2)) { \ + dev_err(atomisp_dev, \ + fmt, ## arg); \ + goto label;\ + } \ + } while (0) + +#define var_not_equal_goto(var1, var2, label, fmt, arg ...) \ + do { \ + if ((var1) != (var2)) { \ + dev_err(atomisp_dev, \ + fmt, ## arg); \ + goto label;\ + } \ + } while (0) + +#define check_null_return(ptr, exp, fmt, arg ...) \ + var_equal_return(ptr, NULL, exp, fmt, ## arg) + +#define check_null_return_void(ptr, fmt, arg ...) \ + var_equal_return_void(ptr, NULL, fmt, ## arg) + +#endif diff --git a/drivers/staging/media/atomisp/include/linux/atomisp.h b/drivers/staging/media/atomisp/include/linux/atomisp.h new file mode 100644 index 000000000..3f602b5aa --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/atomisp.h @@ -0,0 +1,1199 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef _ATOM_ISP_H +#define _ATOM_ISP_H + +#include +#include + +/* struct media_device_info.hw_revision */ +#define ATOMISP_HW_REVISION_MASK 0x0000ff00 +#define ATOMISP_HW_REVISION_SHIFT 8 +#define ATOMISP_HW_REVISION_ISP2300 0x00 +#define ATOMISP_HW_REVISION_ISP2400 0x10 +#define ATOMISP_HW_REVISION_ISP2401_LEGACY 0x11 +#define ATOMISP_HW_REVISION_ISP2401 0x20 + +#define ATOMISP_HW_STEPPING_MASK 0x000000ff +#define ATOMISP_HW_STEPPING_A0 0x00 +#define ATOMISP_HW_STEPPING_B0 0x10 + +/*ISP binary running mode*/ +#define CI_MODE_PREVIEW 0x8000 +#define CI_MODE_VIDEO 0x4000 +#define CI_MODE_STILL_CAPTURE 0x2000 +#define CI_MODE_CONTINUOUS 0x1000 +#define CI_MODE_NONE 0x0000 + +#define OUTPUT_MODE_FILE 0x0100 +#define OUTPUT_MODE_TEXT 0x0200 + +/* + * Camera HAL sets this flag in v4l2_buffer reserved2 to indicate this + * buffer has a per-frame parameter. + */ +#define ATOMISP_BUFFER_HAS_PER_FRAME_SETTING 0x80000000 + +/* Custom format for RAW capture from M10MO 0x3130314d */ +#define V4L2_PIX_FMT_CUSTOM_M10MO_RAW v4l2_fourcc('M', '1', '0', '1') + +/* Custom media bus formats being used in atomisp */ +#define V4L2_MBUS_FMT_CUSTOM_YUV420 0x8001 +#define V4L2_MBUS_FMT_CUSTOM_YVU420 0x8002 +#define V4L2_MBUS_FMT_CUSTOM_YUV422P 0x8003 +#define V4L2_MBUS_FMT_CUSTOM_YUV444 0x8004 +#define V4L2_MBUS_FMT_CUSTOM_NV12 0x8005 +#define V4L2_MBUS_FMT_CUSTOM_NV21 0x8006 +#define V4L2_MBUS_FMT_CUSTOM_NV16 0x8007 +#define V4L2_MBUS_FMT_CUSTOM_YUYV 0x8008 +#define V4L2_MBUS_FMT_CUSTOM_SBGGR16 0x8009 +#define V4L2_MBUS_FMT_CUSTOM_RGB32 0x800a + +/* Custom media bus format for M10MO RAW capture */ +#if 0 +#define V4L2_MBUS_FMT_CUSTOM_M10MO_RAW 0x800b +#endif + +/* Configuration used by Bayer noise reduction and YCC noise reduction */ +struct atomisp_nr_config { + /* [gain] Strength of noise reduction for Bayer NR (Used by Bayer NR) */ + unsigned int bnr_gain; + /* [gain] Strength of noise reduction for YCC NR (Used by YCC NR) */ + unsigned int ynr_gain; + /* [intensity] Sensitivity of Edge (Used by Bayer NR) */ + unsigned int direction; + /* [intensity] coring threshold for Cb (Used by YCC NR) */ + unsigned int threshold_cb; + /* [intensity] coring threshold for Cr (Used by YCC NR) */ + unsigned int threshold_cr; +}; + +/* Temporal noise reduction configuration */ +struct atomisp_tnr_config { + unsigned int gain; /* [gain] Strength of NR */ + unsigned int threshold_y;/* [intensity] Motion sensitivity for Y */ + unsigned int threshold_uv;/* [intensity] Motion sensitivity for U/V */ +}; + +/* Histogram. This contains num_elements values of type unsigned int. + * The data pointer is a DDR pointer (virtual address). + */ +struct atomisp_histogram { + unsigned int num_elements; + void __user *data; +}; + +enum atomisp_ob_mode { + atomisp_ob_mode_none, + atomisp_ob_mode_fixed, + atomisp_ob_mode_raster +}; + +/* Optical black level configuration */ +struct atomisp_ob_config { + /* Obtical black level mode (Fixed / Raster) */ + enum atomisp_ob_mode mode; + /* [intensity] optical black level for GR (relevant for fixed mode) */ + unsigned int level_gr; + /* [intensity] optical black level for R (relevant for fixed mode) */ + unsigned int level_r; + /* [intensity] optical black level for B (relevant for fixed mode) */ + unsigned int level_b; + /* [intensity] optical black level for GB (relevant for fixed mode) */ + unsigned int level_gb; + /* [BQ] 0..63 start position of OB area (relevant for raster mode) */ + unsigned short start_position; + /* [BQ] start..63 end position of OB area (relevant for raster mode) */ + unsigned short end_position; +}; + +/* Edge enhancement (sharpen) configuration */ +struct atomisp_ee_config { + /* [gain] The strength of sharpness. u5_11 */ + unsigned int gain; + /* [intensity] The threshold that divides noises from edge. u8_8 */ + unsigned int threshold; + /* [gain] The strength of sharpness in pell-mell area. u5_11 */ + unsigned int detail_gain; +}; + +struct atomisp_3a_output { + int ae_y; + int awb_cnt; + int awb_gr; + int awb_r; + int awb_b; + int awb_gb; + int af_hpf1; + int af_hpf2; +}; + +enum atomisp_calibration_type { + calibration_type1, + calibration_type2, + calibration_type3 +}; + +struct atomisp_calibration_group { + unsigned int size; + unsigned int type; + unsigned short *calb_grp_values; +}; + +struct atomisp_gc_config { + __u16 gain_k1; + __u16 gain_k2; +}; + +struct atomisp_3a_config { + unsigned int ae_y_coef_r; /* [gain] Weight of R for Y */ + unsigned int ae_y_coef_g; /* [gain] Weight of G for Y */ + unsigned int ae_y_coef_b; /* [gain] Weight of B for Y */ + unsigned int awb_lg_high_raw; /* [intensity] + AWB level gate high for raw */ + unsigned int awb_lg_low; /* [intensity] AWB level gate low */ + unsigned int awb_lg_high; /* [intensity] AWB level gate high */ + int af_fir1_coef[7]; /* [factor] AF FIR coefficients of fir1 */ + int af_fir2_coef[7]; /* [factor] AF FIR coefficients of fir2 */ +}; + +struct atomisp_dvs_grid_info { + u32 enable; + u32 width; + u32 aligned_width; + u32 height; + u32 aligned_height; + u32 bqs_per_grid_cell; + u32 num_hor_coefs; + u32 num_ver_coefs; +}; + +struct atomisp_dvs_envelop { + unsigned int width; + unsigned int height; +}; + +struct atomisp_grid_info { + u32 enable; + u32 use_dmem; + u32 has_histogram; + u32 s3a_width; + u32 s3a_height; + u32 aligned_width; + u32 aligned_height; + u32 s3a_bqs_per_grid_cell; + u32 deci_factor_log2; + u32 elem_bit_depth; +}; + +struct atomisp_dis_vector { + int x; + int y; +}; + +/* DVS 2.0 Coefficient types. This structure contains 4 pointers to + * arrays that contain the coeffients for each type. + */ +struct atomisp_dvs2_coef_types { + short __user *odd_real; /** real part of the odd coefficients*/ + short __user *odd_imag; /** imaginary part of the odd coefficients*/ + short __user *even_real;/** real part of the even coefficients*/ + short __user *even_imag;/** imaginary part of the even coefficients*/ +}; + +/* + * DVS 2.0 Statistic types. This structure contains 4 pointers to + * arrays that contain the statistics for each type. + */ +struct atomisp_dvs2_stat_types { + int __user *odd_real; /** real part of the odd statistics*/ + int __user *odd_imag; /** imaginary part of the odd statistics*/ + int __user *even_real;/** real part of the even statistics*/ + int __user *even_imag;/** imaginary part of the even statistics*/ +}; + +struct atomisp_dis_coefficients { + struct atomisp_dvs_grid_info grid_info; + struct atomisp_dvs2_coef_types hor_coefs; + struct atomisp_dvs2_coef_types ver_coefs; +}; + +struct atomisp_dvs2_statistics { + struct atomisp_dvs_grid_info grid_info; + struct atomisp_dvs2_stat_types hor_prod; + struct atomisp_dvs2_stat_types ver_prod; +}; + +struct atomisp_dis_statistics { + struct atomisp_dvs2_statistics dvs2_stat; + u32 exp_id; +}; + +struct atomisp_3a_rgby_output { + u32 r; + u32 g; + u32 b; + u32 y; +}; + +/* + * Because we have 2 pipes at max to output metadata, therefore driver will use + * ATOMISP_MAIN_METADATA to specify the metadata from the pipe which keeps + * streaming always and use ATOMISP_SEC_METADATA to specify the metadata from + * the pipe which is streaming by request like capture pipe of ZSL or SDV mode + * as secondary metadata. And for the use case which has only one pipe + * streaming like online capture, ATOMISP_MAIN_METADATA will be used. + */ +enum atomisp_metadata_type { + ATOMISP_MAIN_METADATA = 0, + ATOMISP_SEC_METADATA, + ATOMISP_METADATA_TYPE_NUM, +}; + +struct atomisp_metadata_with_type { + /* to specify which type of metadata to get */ + enum atomisp_metadata_type type; + void __user *data; + u32 width; + u32 height; + u32 stride; /* in bytes */ + u32 exp_id; /* exposure ID */ + u32 *effective_width; /* mipi packets valid data size */ +}; + +struct atomisp_metadata { + void __user *data; + u32 width; + u32 height; + u32 stride; /* in bytes */ + u32 exp_id; /* exposure ID */ + u32 *effective_width; /* mipi packets valid data size */ +}; + +struct atomisp_ext_isp_ctrl { + u32 id; + u32 data; +}; + +struct atomisp_3a_statistics { + struct atomisp_grid_info grid_info; + struct atomisp_3a_output __user *data; + struct atomisp_3a_rgby_output __user *rgby_data; + u32 exp_id; /* exposure ID */ + u32 isp_config_id; /* isp config ID */ +}; + +/** + * struct atomisp_cont_capture_conf - continuous capture parameters + * @num_captures: number of still images to capture + * @skip_frames: number of frames to skip between 2 captures + * @offset: offset in ring buffer to start capture + * + * For example, to capture 1 frame from past, current, and 1 from future + * and skip one frame between each capture, parameters would be: + * num_captures:3 + * skip_frames:1 + * offset:-2 + */ + +struct atomisp_cont_capture_conf { + int num_captures; + unsigned int skip_frames; + int offset; + __u32 reserved[5]; +}; + +struct atomisp_ae_window { + int x_left; + int x_right; + int y_top; + int y_bottom; + int weight; +}; + +/* White Balance (Gain Adjust) */ +struct atomisp_wb_config { + unsigned int integer_bits; + unsigned int gr; /* unsigned .<16-integer_bits> */ + unsigned int r; /* unsigned .<16-integer_bits> */ + unsigned int b; /* unsigned .<16-integer_bits> */ + unsigned int gb; /* unsigned .<16-integer_bits> */ +}; + +/* Color Space Conversion settings */ +struct atomisp_cc_config { + unsigned int fraction_bits; + int matrix[3 * 3]; /* RGB2YUV Color matrix, signed + <13-fraction_bits>. */ +}; + +/* De pixel noise configuration */ +struct atomisp_de_config { + unsigned int pixelnoise; + unsigned int c1_coring_threshold; + unsigned int c2_coring_threshold; +}; + +/* Chroma enhancement */ +struct atomisp_ce_config { + unsigned char uv_level_min; + unsigned char uv_level_max; +}; + +/* Defect pixel correction configuration */ +struct atomisp_dp_config { + /* [intensity] The threshold of defect Pixel Correction, representing + * the permissible difference of intensity between one pixel and its + * surrounding pixels. Smaller values result in more frequent pixel + * corrections. u0_16 + */ + unsigned int threshold; + /* [gain] The sensitivity of mis-correction. ISP will miss a lot of + * defects if the value is set too large. u8_8 + */ + unsigned int gain; + unsigned int gr; + unsigned int r; + unsigned int b; + unsigned int gb; +}; + +/* XNR threshold */ +struct atomisp_xnr_config { + __u16 threshold; +}; + +/* metadata config */ +struct atomisp_metadata_config { + u32 metadata_height; + u32 metadata_stride; +}; + +/* + * Generic resolution structure. + */ +struct atomisp_resolution { + u32 width; /** Width */ + u32 height; /** Height */ +}; + +/* + * This specifies the coordinates (x,y) + */ +struct atomisp_zoom_point { + s32 x; /** x coordinate */ + s32 y; /** y coordinate */ +}; + +/* + * This specifies the region + */ +struct atomisp_zoom_region { + struct atomisp_zoom_point + origin; /* Starting point coordinates for the region */ + struct atomisp_resolution resolution; /* Region resolution */ +}; + +struct atomisp_dz_config { + u32 dx; /** Horizontal zoom factor */ + u32 dy; /** Vertical zoom factor */ + struct atomisp_zoom_region zoom_region; /** region for zoom */ +}; + +struct atomisp_parm { + struct atomisp_grid_info info; + struct atomisp_dvs_grid_info dvs_grid; + struct atomisp_dvs_envelop dvs_envelop; + struct atomisp_wb_config wb_config; + struct atomisp_cc_config cc_config; + struct atomisp_ob_config ob_config; + struct atomisp_de_config de_config; + struct atomisp_dz_config dz_config; + struct atomisp_ce_config ce_config; + struct atomisp_dp_config dp_config; + struct atomisp_nr_config nr_config; + struct atomisp_ee_config ee_config; + struct atomisp_tnr_config tnr_config; + struct atomisp_metadata_config metadata_config; +}; + +struct dvs2_bq_resolution { + int width_bq; /* width [BQ] */ + int height_bq; /* height [BQ] */ +}; + +struct atomisp_dvs2_bq_resolutions { + /* GDC source image size [BQ] */ + struct dvs2_bq_resolution source_bq; + /* GDC output image size [BQ] */ + struct dvs2_bq_resolution output_bq; + /* GDC effective envelope size [BQ] */ + struct dvs2_bq_resolution envelope_bq; + /* isp pipe filter size [BQ] */ + struct dvs2_bq_resolution ispfilter_bq; + /* GDC shit size [BQ] */ + struct dvs2_bq_resolution gdc_shift_bq; +}; + +struct atomisp_dvs_6axis_config { + u32 exp_id; + u32 width_y; + u32 height_y; + u32 width_uv; + u32 height_uv; + u32 *xcoords_y; + u32 *ycoords_y; + u32 *xcoords_uv; + u32 *ycoords_uv; +}; + +struct atomisp_formats_config { + u32 video_full_range_flag; +}; + +struct atomisp_parameters { + struct atomisp_wb_config *wb_config; /* White Balance config */ + struct atomisp_cc_config *cc_config; /* Color Correction config */ + struct atomisp_tnr_config *tnr_config; /* Temporal Noise Reduction */ + struct atomisp_ecd_config *ecd_config; /* Eigen Color Demosaicing */ + struct atomisp_ynr_config *ynr_config; /* Y(Luma) Noise Reduction */ + struct atomisp_fc_config *fc_config; /* Fringe Control */ + struct atomisp_formats_config *formats_config; /* Formats Control */ + struct atomisp_cnr_config *cnr_config; /* Chroma Noise Reduction */ + struct atomisp_macc_config *macc_config; /* MACC */ + struct atomisp_ctc_config *ctc_config; /* Chroma Tone Control */ + struct atomisp_aa_config *aa_config; /* Anti-Aliasing */ + struct atomisp_aa_config *baa_config; /* Anti-Aliasing */ + struct atomisp_ce_config *ce_config; + struct atomisp_dvs_6axis_config *dvs_6axis_config; + struct atomisp_ob_config *ob_config; /* Objective Black config */ + struct atomisp_dp_config *dp_config; /* Dead Pixel config */ + struct atomisp_nr_config *nr_config; /* Noise Reduction config */ + struct atomisp_ee_config *ee_config; /* Edge Enhancement config */ + struct atomisp_de_config *de_config; /* Demosaic config */ + struct atomisp_gc_config *gc_config; /* Gamma Correction config */ + struct atomisp_anr_config *anr_config; /* Advanced Noise Reduction */ + struct atomisp_3a_config *a3a_config; /* 3A Statistics config */ + struct atomisp_xnr_config *xnr_config; /* eXtra Noise Reduction */ + struct atomisp_dz_config *dz_config; /* Digital Zoom */ + struct atomisp_cc_config *yuv2rgb_cc_config; /* Color + Correction config */ + struct atomisp_cc_config *rgb2yuv_cc_config; /* Color + Correction config */ + struct atomisp_macc_table *macc_table; + struct atomisp_gamma_table *gamma_table; + struct atomisp_ctc_table *ctc_table; + struct atomisp_xnr_table *xnr_table; + struct atomisp_rgb_gamma_table *r_gamma_table; + struct atomisp_rgb_gamma_table *g_gamma_table; + struct atomisp_rgb_gamma_table *b_gamma_table; + struct atomisp_vector *motion_vector; /* For 2-axis DVS */ + struct atomisp_shading_table *shading_table; + struct atomisp_morph_table *morph_table; + struct atomisp_dvs_coefficients *dvs_coefs; /* DVS 1.0 coefficients */ + struct atomisp_dis_coefficients *dvs2_coefs; /* DVS 2.0 coefficients */ + struct atomisp_capture_config *capture_config; + struct atomisp_anr_thres *anr_thres; + + void *lin_2500_config; /* Skylake: Linearization config */ + void *obgrid_2500_config; /* Skylake: OBGRID config */ + void *bnr_2500_config; /* Skylake: bayer denoise config */ + void *shd_2500_config; /* Skylake: shading config */ + void *dm_2500_config; /* Skylake: demosaic config */ + void *rgbpp_2500_config; /* Skylake: RGBPP config */ + void *dvs_stat_2500_config; /* Skylake: DVS STAT config */ + void *lace_stat_2500_config; /* Skylake: LACE STAT config */ + void *yuvp1_2500_config; /* Skylake: yuvp1 config */ + void *yuvp2_2500_config; /* Skylake: yuvp2 config */ + void *tnr_2500_config; /* Skylake: TNR config */ + void *dpc_2500_config; /* Skylake: DPC config */ + void *awb_2500_config; /* Skylake: auto white balance config */ + void *awb_fr_2500_config; /* Skylake: auto white balance filter response config */ + void *anr_2500_config; /* Skylake: ANR config */ + void *af_2500_config; /* Skylake: auto focus config */ + void *ae_2500_config; /* Skylake: auto exposure config */ + void *bds_2500_config; /* Skylake: bayer downscaler config */ + void *dvs_2500_config; /* Skylake: digital video stabilization config */ + void *res_mgr_2500_config; + + /* + * Output frame pointer the config is to be applied to (optional), + * set to NULL to make this config is applied as global. + */ + void *output_frame; + /* + * Unique ID to track which config was actually applied to a particular + * frame, driver will send this id back with output frame together. + */ + u32 isp_config_id; + + /* + * Switch to control per_frame setting: + * 0: this is a global setting + * 1: this is a per_frame setting + * PLEASE KEEP THIS AT THE END OF THE STRUCTURE!! + */ + u32 per_frame_setting; +}; + +#define ATOMISP_GAMMA_TABLE_SIZE 1024 +struct atomisp_gamma_table { + unsigned short data[ATOMISP_GAMMA_TABLE_SIZE]; +}; + +/* Morphing table for advanced ISP. + * Each line of width elements takes up COORD_TABLE_EXT_WIDTH elements + * in memory. + */ +#define ATOMISP_MORPH_TABLE_NUM_PLANES 6 +struct atomisp_morph_table { + unsigned int enabled; + + unsigned int height; + unsigned int width; /* number of valid elements per line */ + unsigned short __user *coordinates_x[ATOMISP_MORPH_TABLE_NUM_PLANES]; + unsigned short __user *coordinates_y[ATOMISP_MORPH_TABLE_NUM_PLANES]; +}; + +#define ATOMISP_NUM_SC_COLORS 4 +#define ATOMISP_SC_FLAG_QUERY BIT(0) + +struct atomisp_shading_table { + __u32 enable; + + __u32 sensor_width; + __u32 sensor_height; + __u32 width; + __u32 height; + __u32 fraction_bits; + + __u16 *data[ATOMISP_NUM_SC_COLORS]; +}; + +struct atomisp_makernote_info { + /* bits 31-16: numerator, bits 15-0: denominator */ + unsigned int focal_length; + /* bits 31-16: numerator, bits 15-0: denominator*/ + unsigned int f_number_curr; + /* + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ + unsigned int f_number_range; +}; + +/* parameter for MACC */ +#define ATOMISP_NUM_MACC_AXES 16 +struct atomisp_macc_table { + short data[4 * ATOMISP_NUM_MACC_AXES]; +}; + +struct atomisp_macc_config { + int color_effect; + struct atomisp_macc_table table; +}; + +/* Parameter for ctc parameter control */ +#define ATOMISP_CTC_TABLE_SIZE 1024 +struct atomisp_ctc_table { + unsigned short data[ATOMISP_CTC_TABLE_SIZE]; +}; + +/* Parameter for overlay image loading */ +struct atomisp_overlay { + /* the frame containing the overlay data The overlay frame width should + * be the multiples of 2*ISP_VEC_NELEMS. The overlay frame height + * should be the multiples of 2. + */ + struct v4l2_framebuffer *frame; + /* Y value of overlay background */ + unsigned char bg_y; + /* U value of overlay background */ + char bg_u; + /* V value of overlay background */ + char bg_v; + /* the blending percent of input data for Y subpixels */ + unsigned char blend_input_perc_y; + /* the blending percent of input data for U subpixels */ + unsigned char blend_input_perc_u; + /* the blending percent of input data for V subpixels */ + unsigned char blend_input_perc_v; + /* the blending percent of overlay data for Y subpixels */ + unsigned char blend_overlay_perc_y; + /* the blending percent of overlay data for U subpixels */ + unsigned char blend_overlay_perc_u; + /* the blending percent of overlay data for V subpixels */ + unsigned char blend_overlay_perc_v; + /* the overlay start x pixel position on output frame It should be the + multiples of 2*ISP_VEC_NELEMS. */ + unsigned int overlay_start_x; + /* the overlay start y pixel position on output frame It should be the + multiples of 2. */ + unsigned int overlay_start_y; +}; + +/* Sensor resolution specific data for AE calculation.*/ +struct atomisp_sensor_mode_data { + unsigned int coarse_integration_time_min; + unsigned int coarse_integration_time_max_margin; + unsigned int fine_integration_time_min; + unsigned int fine_integration_time_max_margin; + unsigned int fine_integration_time_def; + unsigned int frame_length_lines; + unsigned int line_length_pck; + unsigned int read_mode; + unsigned int vt_pix_clk_freq_mhz; + unsigned int crop_horizontal_start; /* Sensor crop start cord. (x0,y0)*/ + unsigned int crop_vertical_start; + unsigned int crop_horizontal_end; /* Sensor crop end cord. (x1,y1)*/ + unsigned int crop_vertical_end; + unsigned int output_width; /* input size to ISP after binning/scaling */ + unsigned int output_height; + u8 binning_factor_x; /* horizontal binning factor used */ + u8 binning_factor_y; /* vertical binning factor used */ + u16 hts; +}; + +struct atomisp_exposure { + unsigned int integration_time[8]; + unsigned int shutter_speed[8]; + unsigned int gain[4]; + unsigned int aperture; +}; + +/* For texture streaming. */ +struct atomisp_bc_video_package { + int ioctl_cmd; + int device_id; + int inputparam; + int outputparam; +}; + +enum atomisp_focus_hp { + ATOMISP_FOCUS_HP_IN_PROGRESS = (1U << 2), + ATOMISP_FOCUS_HP_COMPLETE = (2U << 2), + ATOMISP_FOCUS_HP_FAILED = (3U << 2) +}; + +/* Masks */ +#define ATOMISP_FOCUS_STATUS_MOVING BIT(0) +#define ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE BIT(1) +#define ATOMISP_FOCUS_STATUS_HOME_POSITION (3U << 2) + +enum atomisp_camera_port { + ATOMISP_CAMERA_PORT_SECONDARY, + ATOMISP_CAMERA_PORT_PRIMARY, + ATOMISP_CAMERA_PORT_TERTIARY, + ATOMISP_CAMERA_NR_PORTS +}; + +/* Flash modes. Default is off. + * Setting a flash to TORCH or INDICATOR mode will automatically + * turn it on. Setting it to FLASH mode will not turn on the flash + * until the FLASH_STROBE command is sent. */ +enum atomisp_flash_mode { + ATOMISP_FLASH_MODE_OFF, + ATOMISP_FLASH_MODE_FLASH, + ATOMISP_FLASH_MODE_TORCH, + ATOMISP_FLASH_MODE_INDICATOR, +}; + +/* Flash statuses, used by atomisp driver to check before starting + * flash and after having started flash. */ +enum atomisp_flash_status { + ATOMISP_FLASH_STATUS_OK, + ATOMISP_FLASH_STATUS_HW_ERROR, + ATOMISP_FLASH_STATUS_INTERRUPTED, + ATOMISP_FLASH_STATUS_TIMEOUT, +}; + +/* Frame status. This is used to detect corrupted frames and flash + * exposed frames. Usually, the first 2 frames coming out of the sensor + * are corrupted. When using flash, the frame before and the frame after + * the flash exposed frame may be partially exposed by flash. The ISP + * statistics for these frames should not be used by the 3A library. + * The frame status value can be found in the "reserved" field in the + * v4l2_buffer struct. */ +enum atomisp_frame_status { + ATOMISP_FRAME_STATUS_OK, + ATOMISP_FRAME_STATUS_CORRUPTED, + ATOMISP_FRAME_STATUS_FLASH_EXPOSED, + ATOMISP_FRAME_STATUS_FLASH_PARTIAL, + ATOMISP_FRAME_STATUS_FLASH_FAILED, +}; + +enum atomisp_ext_isp_id { + EXT_ISP_CID_ISO = 0, + EXT_ISP_CID_CAPTURE_HDR, + EXT_ISP_CID_CAPTURE_LLS, + EXT_ISP_CID_FOCUS_MODE, + EXT_ISP_CID_FOCUS_EXECUTION, + EXT_ISP_CID_TOUCH_POSX, + EXT_ISP_CID_TOUCH_POSY, + EXT_ISP_CID_CAF_STATUS, + EXT_ISP_CID_AF_STATUS, + EXT_ISP_CID_GET_AF_MODE, + EXT_ISP_CID_CAPTURE_BURST, + EXT_ISP_CID_FLASH_MODE, + EXT_ISP_CID_ZOOM, + EXT_ISP_CID_SHOT_MODE +}; + +#define EXT_ISP_FOCUS_MODE_NORMAL 0 +#define EXT_ISP_FOCUS_MODE_MACRO 1 +#define EXT_ISP_FOCUS_MODE_TOUCH_AF 2 +#define EXT_ISP_FOCUS_MODE_PREVIEW_CAF 3 +#define EXT_ISP_FOCUS_MODE_MOVIE_CAF 4 +#define EXT_ISP_FOCUS_MODE_FACE_CAF 5 +#define EXT_ISP_FOCUS_MODE_TOUCH_MACRO 6 +#define EXT_ISP_FOCUS_MODE_TOUCH_CAF 7 + +#define EXT_ISP_FOCUS_STOP 0 +#define EXT_ISP_FOCUS_SEARCH 1 +#define EXT_ISP_PAN_FOCUSING 2 + +#define EXT_ISP_CAF_RESTART_CHECK 1 +#define EXT_ISP_CAF_STATUS_FOCUSING 2 +#define EXT_ISP_CAF_STATUS_SUCCESS 3 +#define EXT_ISP_CAF_STATUS_FAIL 4 + +#define EXT_ISP_AF_STATUS_INVALID 1 +#define EXT_ISP_AF_STATUS_FOCUSING 2 +#define EXT_ISP_AF_STATUS_SUCCESS 3 +#define EXT_ISP_AF_STATUS_FAIL 4 + +enum atomisp_burst_capture_options { + EXT_ISP_BURST_CAPTURE_CTRL_START = 0, + EXT_ISP_BURST_CAPTURE_CTRL_STOP +}; + +#define EXT_ISP_FLASH_MODE_OFF 0 +#define EXT_ISP_FLASH_MODE_ON 1 +#define EXT_ISP_FLASH_MODE_AUTO 2 +#define EXT_ISP_LED_TORCH_OFF 3 +#define EXT_ISP_LED_TORCH_ON 4 + +#define EXT_ISP_SHOT_MODE_AUTO 0 +#define EXT_ISP_SHOT_MODE_BEAUTY_FACE 1 +#define EXT_ISP_SHOT_MODE_BEST_PHOTO 2 +#define EXT_ISP_SHOT_MODE_DRAMA 3 +#define EXT_ISP_SHOT_MODE_BEST_FACE 4 +#define EXT_ISP_SHOT_MODE_ERASER 5 +#define EXT_ISP_SHOT_MODE_PANORAMA 6 +#define EXT_ISP_SHOT_MODE_RICH_TONE_HDR 7 +#define EXT_ISP_SHOT_MODE_NIGHT 8 +#define EXT_ISP_SHOT_MODE_SOUND_SHOT 9 +#define EXT_ISP_SHOT_MODE_ANIMATED_PHOTO 10 +#define EXT_ISP_SHOT_MODE_SPORTS 11 + +/* + * Set Senor run mode + */ +struct atomisp_s_runmode { + __u32 mode; +}; + +struct atomisp_update_exposure { + unsigned int gain; + unsigned int digi_gain; + unsigned int update_gain; + unsigned int update_digi_gain; +}; + +/* + * V4L2 private internal data interface. + * ----------------------------------------------------------------------------- + * struct v4l2_private_int_data - request private data stored in video device + * internal memory. + * @size: sanity check to ensure userspace's buffer fits whole private data. + * If not, kernel will make partial copy (or nothing if @size == 0). + * @size is always corrected for the minimum necessary if IOCTL returns + * no error. + * @data: pointer to userspace buffer. + */ +struct v4l2_private_int_data { + __u32 size; + void __user *data; + __u32 reserved[2]; +}; + +enum atomisp_sensor_ae_bracketing_mode { + SENSOR_AE_BRACKETING_MODE_OFF = 0, + SENSOR_AE_BRACKETING_MODE_SINGLE, /* back to SW standby after bracketing */ + SENSOR_AE_BRACKETING_MODE_SINGLE_TO_STREAMING, /* back to normal streaming after bracketing */ + SENSOR_AE_BRACKETING_MODE_LOOP, /* continue AE bracketing in loop mode */ +}; + +struct atomisp_sensor_ae_bracketing_info { + unsigned int modes; /* bit mask to indicate supported modes */ + unsigned int lut_depth; +}; + +struct atomisp_sensor_ae_bracketing_lut_entry { + __u16 coarse_integration_time; + __u16 analog_gain; + __u16 digital_gain; +}; + +struct atomisp_sensor_ae_bracketing_lut { + struct atomisp_sensor_ae_bracketing_lut_entry *lut; + unsigned int lut_size; +}; + +/*Private IOCTLs for ISP */ +#define ATOMISP_IOC_G_XNR \ + _IOR('v', BASE_VIDIOC_PRIVATE + 0, int) +#define ATOMISP_IOC_S_XNR \ + _IOW('v', BASE_VIDIOC_PRIVATE + 0, int) +#define ATOMISP_IOC_G_NR \ + _IOR('v', BASE_VIDIOC_PRIVATE + 1, struct atomisp_nr_config) +#define ATOMISP_IOC_S_NR \ + _IOW('v', BASE_VIDIOC_PRIVATE + 1, struct atomisp_nr_config) +#define ATOMISP_IOC_G_TNR \ + _IOR('v', BASE_VIDIOC_PRIVATE + 2, struct atomisp_tnr_config) +#define ATOMISP_IOC_S_TNR \ + _IOW('v', BASE_VIDIOC_PRIVATE + 2, struct atomisp_tnr_config) +#define ATOMISP_IOC_G_HISTOGRAM \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram) +#define ATOMISP_IOC_S_HISTOGRAM \ + _IOW('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram) +#define ATOMISP_IOC_G_BLACK_LEVEL_COMP \ + _IOR('v', BASE_VIDIOC_PRIVATE + 4, struct atomisp_ob_config) +#define ATOMISP_IOC_S_BLACK_LEVEL_COMP \ + _IOW('v', BASE_VIDIOC_PRIVATE + 4, struct atomisp_ob_config) +#define ATOMISP_IOC_G_EE \ + _IOR('v', BASE_VIDIOC_PRIVATE + 5, struct atomisp_ee_config) +#define ATOMISP_IOC_S_EE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 5, struct atomisp_ee_config) +/* Digital Image Stabilization: + * 1. get dis statistics: reads DIS statistics from ISP (every frame) + * 2. set dis coefficients: set DIS filter coefficients (one time) + * 3. set dis motion vecotr: set motion vector (result of DIS, every frame) + */ +#define ATOMISP_IOC_G_DIS_STAT \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_statistics) + +#define ATOMISP_IOC_G_DVS2_BQ_RESOLUTIONS \ + _IOR('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dvs2_bq_resolutions) + +#define ATOMISP_IOC_S_DIS_COEFS \ + _IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_coefficients) + +#define ATOMISP_IOC_S_DIS_VECTOR \ + _IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dvs_6axis_config) + +#define ATOMISP_IOC_G_3A_STAT \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 7, struct atomisp_3a_statistics) +#define ATOMISP_IOC_G_ISP_PARM \ + _IOR('v', BASE_VIDIOC_PRIVATE + 8, struct atomisp_parm) +#define ATOMISP_IOC_S_ISP_PARM \ + _IOW('v', BASE_VIDIOC_PRIVATE + 8, struct atomisp_parm) +#define ATOMISP_IOC_G_ISP_GAMMA \ + _IOR('v', BASE_VIDIOC_PRIVATE + 9, struct atomisp_gamma_table) +#define ATOMISP_IOC_S_ISP_GAMMA \ + _IOW('v', BASE_VIDIOC_PRIVATE + 9, struct atomisp_gamma_table) +#define ATOMISP_IOC_G_ISP_GDC_TAB \ + _IOR('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table) +#define ATOMISP_IOC_S_ISP_GDC_TAB \ + _IOW('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table) +#define ATOMISP_IOC_ISP_MAKERNOTE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 11, struct atomisp_makernote_info) + +/* macc parameter control*/ +#define ATOMISP_IOC_G_ISP_MACC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 12, struct atomisp_macc_config) +#define ATOMISP_IOC_S_ISP_MACC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 12, struct atomisp_macc_config) + +/* Defect pixel detection & Correction */ +#define ATOMISP_IOC_G_ISP_BAD_PIXEL_DETECTION \ + _IOR('v', BASE_VIDIOC_PRIVATE + 13, struct atomisp_dp_config) +#define ATOMISP_IOC_S_ISP_BAD_PIXEL_DETECTION \ + _IOW('v', BASE_VIDIOC_PRIVATE + 13, struct atomisp_dp_config) + +/* False Color Correction */ +#define ATOMISP_IOC_G_ISP_FALSE_COLOR_CORRECTION \ + _IOR('v', BASE_VIDIOC_PRIVATE + 14, struct atomisp_de_config) +#define ATOMISP_IOC_S_ISP_FALSE_COLOR_CORRECTION \ + _IOW('v', BASE_VIDIOC_PRIVATE + 14, struct atomisp_de_config) + +/* ctc parameter control */ +#define ATOMISP_IOC_G_ISP_CTC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 15, struct atomisp_ctc_table) +#define ATOMISP_IOC_S_ISP_CTC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 15, struct atomisp_ctc_table) + +/* white balance Correction */ +#define ATOMISP_IOC_G_ISP_WHITE_BALANCE \ + _IOR('v', BASE_VIDIOC_PRIVATE + 16, struct atomisp_wb_config) +#define ATOMISP_IOC_S_ISP_WHITE_BALANCE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 16, struct atomisp_wb_config) + +/* fpn table loading */ +#define ATOMISP_IOC_S_ISP_FPN_TABLE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 17, struct v4l2_framebuffer) + +/* overlay image loading */ +#define ATOMISP_IOC_G_ISP_OVERLAY \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay) +#define ATOMISP_IOC_S_ISP_OVERLAY \ + _IOW('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay) + +/* bcd driver bridge */ +#define ATOMISP_IOC_CAMERA_BRIDGE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 19, struct atomisp_bc_video_package) + +/* Sensor resolution specific info for AE */ +#define ATOMISP_IOC_G_SENSOR_MODE_DATA \ + _IOR('v', BASE_VIDIOC_PRIVATE + 20, struct atomisp_sensor_mode_data) + +#define ATOMISP_IOC_S_EXPOSURE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 21, struct atomisp_exposure) + +/* sensor calibration registers group */ +#define ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 22, struct atomisp_calibration_group) + +/* white balance Correction */ +#define ATOMISP_IOC_G_3A_CONFIG \ + _IOR('v', BASE_VIDIOC_PRIVATE + 23, struct atomisp_3a_config) +#define ATOMISP_IOC_S_3A_CONFIG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 23, struct atomisp_3a_config) + +/* sensor OTP memory read */ +#define ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 26, struct v4l2_private_int_data) + +/* LCS (shading) table write */ +#define ATOMISP_IOC_S_ISP_SHD_TAB \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 27, struct atomisp_shading_table) + +/* Gamma Correction */ +#define ATOMISP_IOC_G_ISP_GAMMA_CORRECTION \ + _IOR('v', BASE_VIDIOC_PRIVATE + 28, struct atomisp_gc_config) + +#define ATOMISP_IOC_S_ISP_GAMMA_CORRECTION \ + _IOW('v', BASE_VIDIOC_PRIVATE + 28, struct atomisp_gc_config) + +/* motor internal memory read */ +#define ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 29, struct v4l2_private_int_data) + +#define ATOMISP_IOC_S_PARAMETERS \ + _IOW('v', BASE_VIDIOC_PRIVATE + 32, struct atomisp_parameters) + +#define ATOMISP_IOC_S_CONT_CAPTURE_CONFIG \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 33, struct atomisp_cont_capture_conf) + +#define ATOMISP_IOC_G_METADATA \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata) + +#define ATOMISP_IOC_G_METADATA_BY_TYPE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata_with_type) + +#define ATOMISP_IOC_EXT_ISP_CTRL \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 35, struct atomisp_ext_isp_ctrl) + +#define ATOMISP_IOC_EXP_ID_UNLOCK \ + _IOW('v', BASE_VIDIOC_PRIVATE + 36, int) + +#define ATOMISP_IOC_EXP_ID_CAPTURE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 37, int) + +#define ATOMISP_IOC_S_ENABLE_DZ_CAPT_PIPE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 38, unsigned int) + +#define ATOMISP_IOC_G_FORMATS_CONFIG \ + _IOR('v', BASE_VIDIOC_PRIVATE + 39, struct atomisp_formats_config) + +#define ATOMISP_IOC_S_FORMATS_CONFIG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 39, struct atomisp_formats_config) + +#define ATOMISP_IOC_S_EXPOSURE_WINDOW \ + _IOW('v', BASE_VIDIOC_PRIVATE + 40, struct atomisp_ae_window) + +#define ATOMISP_IOC_INJECT_A_FAKE_EVENT \ + _IOW('v', BASE_VIDIOC_PRIVATE + 42, int) + +#define ATOMISP_IOC_G_SENSOR_AE_BRACKETING_INFO \ + _IOR('v', BASE_VIDIOC_PRIVATE + 43, struct atomisp_sensor_ae_bracketing_info) + +#define ATOMISP_IOC_S_SENSOR_AE_BRACKETING_MODE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 43, unsigned int) + +#define ATOMISP_IOC_G_SENSOR_AE_BRACKETING_MODE \ + _IOR('v', BASE_VIDIOC_PRIVATE + 43, unsigned int) + +#define ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT \ + _IOW('v', BASE_VIDIOC_PRIVATE + 43, struct atomisp_sensor_ae_bracketing_lut) + +#define ATOMISP_IOC_G_INVALID_FRAME_NUM \ + _IOR('v', BASE_VIDIOC_PRIVATE + 44, unsigned int) + +#define ATOMISP_IOC_S_ARRAY_RESOLUTION \ + _IOW('v', BASE_VIDIOC_PRIVATE + 45, struct atomisp_resolution) + +/* for depth mode sensor frame sync compensation */ +#define ATOMISP_IOC_G_DEPTH_SYNC_COMP \ + _IOR('v', BASE_VIDIOC_PRIVATE + 46, unsigned int) + +#define ATOMISP_IOC_S_SENSOR_EE_CONFIG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 47, unsigned int) + +#define ATOMISP_IOC_S_SENSOR_RUNMODE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 48, struct atomisp_s_runmode) + +#define ATOMISP_IOC_G_UPDATE_EXPOSURE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 49, struct atomisp_update_exposure) + +/* + * Reserved ioctls. We have customer implementing it internally. + * We can't use both numbers to not cause ABI conflict. + * Anyway, those ioctls are hacks and not implemented by us: + * + * #define ATOMISP_IOC_G_SENSOR_REG \ + * _IOW('v', BASE_VIDIOC_PRIVATE + 55, struct atomisp_sensor_regs) + * #define ATOMISP_IOC_S_SENSOR_REG \ + * _IOW('v', BASE_VIDIOC_PRIVATE + 56, struct atomisp_sensor_regs) + */ + +/* ISP Private control IDs */ +#define V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION \ + (V4L2_CID_PRIVATE_BASE + 0) +#define V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC \ + (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_ATOMISP_VIDEO_STABLIZATION \ + (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_ATOMISP_FIXED_PATTERN_NR \ + (V4L2_CID_PRIVATE_BASE + 3) +#define V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION \ + (V4L2_CID_PRIVATE_BASE + 4) +#define V4L2_CID_ATOMISP_LOW_LIGHT \ + (V4L2_CID_PRIVATE_BASE + 5) + +/* Camera class: + * Exposure, Flash and privacy (indicator) light controls, to be upstreamed */ +#define V4L2_CID_CAMERA_LASTP1 (V4L2_CID_CAMERA_CLASS_BASE + 1024) + +#define V4L2_CID_FOCAL_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 0) +#define V4L2_CID_FNUMBER_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 1) +#define V4L2_CID_FNUMBER_RANGE (V4L2_CID_CAMERA_LASTP1 + 2) + +/* Flash related CIDs, see also: + * http://linuxtv.org/downloads/v4l-dvb-apis/extended-controls.html\ + * #flash-controls */ + +/* Request a number of flash-exposed frames. The frame status can be + * found in the reserved field in the v4l2_buffer struct. */ +#define V4L2_CID_REQUEST_FLASH (V4L2_CID_CAMERA_LASTP1 + 3) +/* Query flash driver status. See enum atomisp_flash_status above. */ +#define V4L2_CID_FLASH_STATUS (V4L2_CID_CAMERA_LASTP1 + 5) +/* Set the flash mode (see enum atomisp_flash_mode) */ +#define V4L2_CID_FLASH_MODE (V4L2_CID_CAMERA_LASTP1 + 10) + +/* VCM slew control */ +#define V4L2_CID_VCM_SLEW (V4L2_CID_CAMERA_LASTP1 + 11) +/* VCM step time */ +#define V4L2_CID_VCM_TIMING (V4L2_CID_CAMERA_LASTP1 + 12) + +/* Query Focus Status */ +#define V4L2_CID_FOCUS_STATUS (V4L2_CID_CAMERA_LASTP1 + 14) + +/* Query sensor's binning factor */ +#define V4L2_CID_BIN_FACTOR_HORZ (V4L2_CID_CAMERA_LASTP1 + 15) +#define V4L2_CID_BIN_FACTOR_VERT (V4L2_CID_CAMERA_LASTP1 + 16) + +/* number of frames to skip at stream start */ +#define V4L2_CID_G_SKIP_FRAMES (V4L2_CID_CAMERA_LASTP1 + 17) + +/* Query sensor's 2A status */ +#define V4L2_CID_2A_STATUS (V4L2_CID_CAMERA_LASTP1 + 18) +#define V4L2_2A_STATUS_AE_READY BIT(0) +#define V4L2_2A_STATUS_AWB_READY BIT(1) + +#define V4L2_CID_FMT_AUTO (V4L2_CID_CAMERA_LASTP1 + 19) + +#define V4L2_CID_RUN_MODE (V4L2_CID_CAMERA_LASTP1 + 20) +#define ATOMISP_RUN_MODE_VIDEO 1 +#define ATOMISP_RUN_MODE_STILL_CAPTURE 2 +#define ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE 3 +#define ATOMISP_RUN_MODE_PREVIEW 4 +#define ATOMISP_RUN_MODE_SDV 5 + +#define V4L2_CID_ENABLE_VFPP (V4L2_CID_CAMERA_LASTP1 + 21) +#define V4L2_CID_ATOMISP_CONTINUOUS_MODE (V4L2_CID_CAMERA_LASTP1 + 22) +#define V4L2_CID_ATOMISP_CONTINUOUS_RAW_BUFFER_SIZE \ + (V4L2_CID_CAMERA_LASTP1 + 23) +#define V4L2_CID_ATOMISP_CONTINUOUS_VIEWFINDER \ + (V4L2_CID_CAMERA_LASTP1 + 24) + +#define V4L2_CID_VFPP (V4L2_CID_CAMERA_LASTP1 + 25) +#define ATOMISP_VFPP_ENABLE 0 +#define ATOMISP_VFPP_DISABLE_SCALER 1 +#define ATOMISP_VFPP_DISABLE_LOWLAT 2 + +/* Query real flash status register value */ +#define V4L2_CID_FLASH_STATUS_REGISTER (V4L2_CID_CAMERA_LASTP1 + 26) + +#define V4L2_CID_START_ZSL_CAPTURE (V4L2_CID_CAMERA_LASTP1 + 28) +/* Lock and unlock raw buffer */ +#define V4L2_CID_ENABLE_RAW_BUFFER_LOCK (V4L2_CID_CAMERA_LASTP1 + 29) + +#define V4L2_CID_DEPTH_MODE (V4L2_CID_CAMERA_LASTP1 + 30) + +#define V4L2_CID_EXPOSURE_ZONE_NUM (V4L2_CID_CAMERA_LASTP1 + 31) +/* Disable digital zoom */ +#define V4L2_CID_DISABLE_DZ (V4L2_CID_CAMERA_LASTP1 + 32) + +#define V4L2_CID_TEST_PATTERN_COLOR_R (V4L2_CID_CAMERA_LASTP1 + 33) +#define V4L2_CID_TEST_PATTERN_COLOR_GR (V4L2_CID_CAMERA_LASTP1 + 34) +#define V4L2_CID_TEST_PATTERN_COLOR_GB (V4L2_CID_CAMERA_LASTP1 + 35) +#define V4L2_CID_TEST_PATTERN_COLOR_B (V4L2_CID_CAMERA_LASTP1 + 36) + +#define V4L2_CID_ATOMISP_SELECT_ISP_VERSION (V4L2_CID_CAMERA_LASTP1 + 38) + +#define V4L2_BUF_FLAG_BUFFER_INVALID 0x0400 +#define V4L2_BUF_FLAG_BUFFER_VALID 0x0800 + +#define V4L2_BUF_TYPE_VIDEO_CAPTURE_ION (V4L2_BUF_TYPE_PRIVATE + 1024) + +#define V4L2_EVENT_ATOMISP_3A_STATS_READY (V4L2_EVENT_PRIVATE_START + 1) +#define V4L2_EVENT_ATOMISP_METADATA_READY (V4L2_EVENT_PRIVATE_START + 2) +#define V4L2_EVENT_ATOMISP_RAW_BUFFERS_ALLOC_DONE (V4L2_EVENT_PRIVATE_START + 3) +#define V4L2_EVENT_ATOMISP_ACC_COMPLETE (V4L2_EVENT_PRIVATE_START + 4) +#define V4L2_EVENT_ATOMISP_PAUSE_BUFFER (V4L2_EVENT_PRIVATE_START + 5) +#define V4L2_EVENT_ATOMISP_CSS_RESET (V4L2_EVENT_PRIVATE_START + 6) +/* Nonstandard color effects for V4L2_CID_COLORFX */ +enum { + V4L2_COLORFX_SKIN_WHITEN_LOW = 1001, + V4L2_COLORFX_SKIN_WHITEN_HIGH = 1002, + V4L2_COLORFX_WARM = 1003, + V4L2_COLORFX_COLD = 1004, + V4L2_COLORFX_WASHED = 1005, + V4L2_COLORFX_RED = 1006, + V4L2_COLORFX_GREEN = 1007, + V4L2_COLORFX_BLUE = 1008, + V4L2_COLORFX_PINK = 1009, + V4L2_COLORFX_YELLOW = 1010, + V4L2_COLORFX_PURPLE = 1011, +}; + +#endif /* _ATOM_ISP_H */ diff --git a/drivers/staging/media/atomisp/include/linux/atomisp_gmin_platform.h b/drivers/staging/media/atomisp/include/linux/atomisp_gmin_platform.h new file mode 100644 index 000000000..5463d11d4 --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/atomisp_gmin_platform.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel MID SoC Camera Imaging ISP subsystem. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef ATOMISP_GMIN_PLATFORM_H_ +#define ATOMISP_GMIN_PLATFORM_H_ + +#include "atomisp_platform.h" + +int atomisp_register_i2c_module(struct v4l2_subdev *subdev, + struct camera_sensor_platform_data *plat_data, + enum intel_v4l2_subdev_type type); +struct v4l2_subdev *atomisp_gmin_find_subdev(struct i2c_adapter *adapter, + struct i2c_board_info *board_info); +int atomisp_gmin_remove_subdev(struct v4l2_subdev *sd); +int gmin_get_var_int(struct device *dev, bool is_gmin, + const char *var, int def); +struct camera_sensor_platform_data * +gmin_camera_platform_data( + struct v4l2_subdev *subdev, + enum atomisp_input_format csi_format, + enum atomisp_bayer_order csi_bayer); + +int atomisp_gmin_register_vcm_control(struct camera_vcm_control *); + +#endif diff --git a/drivers/staging/media/atomisp/include/linux/atomisp_platform.h b/drivers/staging/media/atomisp/include/linux/atomisp_platform.h new file mode 100644 index 000000000..0253661d4 --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/atomisp_platform.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef ATOMISP_PLATFORM_H_ +#define ATOMISP_PLATFORM_H_ + +#include +#include + +#include +#include +#include "atomisp.h" + +#define MAX_SENSORS_PER_PORT 4 +#define MAX_STREAMS_PER_CHANNEL 2 + +#define CAMERA_MODULE_ID_LEN 64 + +enum atomisp_bayer_order { + atomisp_bayer_order_grbg, + atomisp_bayer_order_rggb, + atomisp_bayer_order_bggr, + atomisp_bayer_order_gbrg +}; + +enum atomisp_input_stream_id { + ATOMISP_INPUT_STREAM_GENERAL = 0, + ATOMISP_INPUT_STREAM_CAPTURE = 0, + ATOMISP_INPUT_STREAM_POSTVIEW, + ATOMISP_INPUT_STREAM_PREVIEW, + ATOMISP_INPUT_STREAM_VIDEO, + ATOMISP_INPUT_STREAM_NUM +}; + +enum atomisp_input_format { + ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY,/* 8 bits per subpixel (legacy) */ + ATOMISP_INPUT_FORMAT_YUV420_8, /* 8 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV420_10,/* 10 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV420_16,/* 16 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV422_8, /* UYVY..UVYV, 8 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV422_10,/* UYVY..UVYV, 10 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV422_16,/* UYVY..UVYV, 16 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RGB_444, /* BGR..BGR, 4 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RGB_555, /* BGR..BGR, 5 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RGB_565, /* BGR..BGR, 5 bits B and R, 6 bits G */ + ATOMISP_INPUT_FORMAT_RGB_666, /* BGR..BGR, 6 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RGB_888, /* BGR..BGR, 8 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RAW_6, /* RAW data, 6 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_7, /* RAW data, 7 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_8, /* RAW data, 8 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_10, /* RAW data, 10 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_12, /* RAW data, 12 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_14, /* RAW data, 14 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_16, /* RAW data, 16 bits per pixel */ + ATOMISP_INPUT_FORMAT_BINARY_8, /* Binary byte stream. */ + + /* CSI2-MIPI specific format: Generic short packet data. It is used to + * keep the timing information for the opening/closing of shutters, + * triggering of flashes and etc. + */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT1, /* Generic Short Packet Code 1 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT2, /* Generic Short Packet Code 2 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT3, /* Generic Short Packet Code 3 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT4, /* Generic Short Packet Code 4 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT5, /* Generic Short Packet Code 5 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT6, /* Generic Short Packet Code 6 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT7, /* Generic Short Packet Code 7 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT8, /* Generic Short Packet Code 8 */ + + /* CSI2-MIPI specific format: YUV data. + */ + ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT, /* YUV420 8-bit (Chroma Shifted + Pixel Sampling) */ + ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT, /* YUV420 8-bit (Chroma Shifted + Pixel Sampling) */ + + /* CSI2-MIPI specific format: Generic long packet data + */ + ATOMISP_INPUT_FORMAT_EMBEDDED, /* Embedded 8-bit non Image Data */ + + /* CSI2-MIPI specific format: User defined byte-based data. For example, + * the data transmitter (e.g. the SoC sensor) can keep the JPEG data as + * the User Defined Data Type 4 and the MPEG data as the + * User Defined Data Type 7. + */ + ATOMISP_INPUT_FORMAT_USER_DEF1, /* User defined 8-bit data type 1 */ + ATOMISP_INPUT_FORMAT_USER_DEF2, /* User defined 8-bit data type 2 */ + ATOMISP_INPUT_FORMAT_USER_DEF3, /* User defined 8-bit data type 3 */ + ATOMISP_INPUT_FORMAT_USER_DEF4, /* User defined 8-bit data type 4 */ + ATOMISP_INPUT_FORMAT_USER_DEF5, /* User defined 8-bit data type 5 */ + ATOMISP_INPUT_FORMAT_USER_DEF6, /* User defined 8-bit data type 6 */ + ATOMISP_INPUT_FORMAT_USER_DEF7, /* User defined 8-bit data type 7 */ + ATOMISP_INPUT_FORMAT_USER_DEF8, /* User defined 8-bit data type 8 */ +}; + +#define N_ATOMISP_INPUT_FORMAT (ATOMISP_INPUT_FORMAT_USER_DEF8 + 1) + +enum intel_v4l2_subdev_type { + RAW_CAMERA = 1, + SOC_CAMERA = 2, + CAMERA_MOTOR = 3, + LED_FLASH = 4, + XENON_FLASH = 5, + FILE_INPUT = 6, + TEST_PATTERN = 7, +}; + +struct intel_v4l2_subdev_id { + char name[17]; + enum intel_v4l2_subdev_type type; + enum atomisp_camera_port port; +}; + +struct intel_v4l2_subdev_i2c_board_info { + struct i2c_board_info board_info; + int i2c_adapter_id; +}; + +struct intel_v4l2_subdev_table { + struct intel_v4l2_subdev_i2c_board_info v4l2_subdev; + enum intel_v4l2_subdev_type type; + enum atomisp_camera_port port; + struct v4l2_subdev *subdev; +}; + +struct atomisp_platform_data { + struct intel_v4l2_subdev_table *subdevs; +}; + +/* + * Sensor of external ISP can send multiple steams with different mipi data + * type in the same virtual channel. This information needs to come from the + * sensor or external ISP + */ +struct atomisp_isys_config_info { + u8 input_format; + u16 width; + u16 height; +}; + +struct atomisp_input_stream_info { + enum atomisp_input_stream_id stream; + u8 enable; + /* Sensor driver fills ch_id with the id + of the virtual channel. */ + u8 ch_id; + /* Tells how many streams in this virtual channel. If 0 ignore rest + * and the input format will be from mipi_info */ + u8 isys_configs; + /* + * if more isys_configs is more than 0, sensor needs to configure the + * input format differently. width and height can be 0. If width and + * height is not zero, then the corresponsing data needs to be set + */ + struct atomisp_isys_config_info isys_info[MAX_STREAMS_PER_CHANNEL]; +}; + +struct camera_vcm_control; +struct camera_vcm_ops { + int (*power_up)(struct v4l2_subdev *sd, struct camera_vcm_control *vcm); + int (*power_down)(struct v4l2_subdev *sd, + struct camera_vcm_control *vcm); + int (*queryctrl)(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc, + struct camera_vcm_control *vcm); + int (*g_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl, + struct camera_vcm_control *vcm); + int (*s_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl, + struct camera_vcm_control *vcm); +}; + +struct camera_vcm_control { + char camera_module[CAMERA_MODULE_ID_LEN]; + struct camera_vcm_ops *ops; + struct list_head list; +}; + +struct camera_sensor_platform_data { + int (*flisclk_ctrl)(struct v4l2_subdev *subdev, int flag); + int (*csi_cfg)(struct v4l2_subdev *subdev, int flag); + + /* + * New G-Min power and GPIO interface to control individual + * lines as implemented on all known camera modules. + */ + int (*gpio0_ctrl)(struct v4l2_subdev *subdev, int on); + int (*gpio1_ctrl)(struct v4l2_subdev *subdev, int on); + int (*v1p8_ctrl)(struct v4l2_subdev *subdev, int on); + int (*v2p8_ctrl)(struct v4l2_subdev *subdev, int on); + int (*v1p2_ctrl)(struct v4l2_subdev *subdev, int on); + struct camera_vcm_control *(*get_vcm_ctrl)(struct v4l2_subdev *subdev, + char *module_id); +}; + +struct camera_mipi_info { + enum atomisp_camera_port port; + unsigned int num_lanes; + enum atomisp_input_format input_format; + enum atomisp_bayer_order raw_bayer_order; + struct atomisp_sensor_mode_data data; + enum atomisp_input_format metadata_format; + u32 metadata_width; + u32 metadata_height; + const u32 *metadata_effective_width; +}; + +const struct atomisp_platform_data *atomisp_get_platform_data(void); + +/* API from old platform_camera.h, new CPUID implementation */ +#define __IS_SOC(x) (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && \ + boot_cpu_data.x86 == 6 && \ + boot_cpu_data.x86_model == (x)) +#define __IS_SOCS(x,y) (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && \ + boot_cpu_data.x86 == 6 && \ + (boot_cpu_data.x86_model == (x) || \ + boot_cpu_data.x86_model == (y))) + +#define IS_MFLD __IS_SOC(INTEL_FAM6_ATOM_SALTWELL_MID) +#define IS_BYT __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT) +#define IS_CHT __IS_SOC(INTEL_FAM6_ATOM_AIRMONT) +#define IS_MRFD __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT_MID) +#define IS_MOFD __IS_SOC(INTEL_FAM6_ATOM_AIRMONT_MID) + +/* Both CHT and MOFD come with ISP2401 */ +#define IS_ISP2401 __IS_SOCS(INTEL_FAM6_ATOM_AIRMONT, \ + INTEL_FAM6_ATOM_AIRMONT_MID) + +#endif /* ATOMISP_PLATFORM_H_ */ diff --git a/drivers/staging/media/atomisp/include/linux/libmsrlisthelper.h b/drivers/staging/media/atomisp/include/linux/libmsrlisthelper.h new file mode 100644 index 000000000..abc8fa809 --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/libmsrlisthelper.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef __LIBMSRLISTHELPER_H__ +#define __LIBMSRLISTHELPER_H__ + +struct i2c_client; +struct firmware; + +int load_msr_list(struct i2c_client *client, char *path, + const struct firmware **fw); +int apply_msr_data(struct i2c_client *client, const struct firmware *fw); +void release_msr_list(struct i2c_client *client, + const struct firmware *fw); + +#endif /* ifndef __LIBMSRLISTHELPER_H__ */ diff --git a/drivers/staging/media/atomisp/include/media/lm3554.h b/drivers/staging/media/atomisp/include/media/lm3554.h new file mode 100644 index 000000000..711b7d7c9 --- /dev/null +++ b/drivers/staging/media/atomisp/include/media/lm3554.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/media/lm3554.h + * + * Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef _LM3554_H_ +#define _LM3554_H_ + +#include +#include +#include + +#define LM3554_ID 3554 + +#define v4l2_queryctrl_entry_integer(_id, _name,\ + _minimum, _maximum, _step, \ + _default_value, _flags) \ + {\ + .id = (_id), \ + .type = V4L2_CTRL_TYPE_INTEGER, \ + .name = _name, \ + .minimum = (_minimum), \ + .maximum = (_maximum), \ + .step = (_step), \ + .default_value = (_default_value),\ + .flags = (_flags),\ + } +#define v4l2_queryctrl_entry_boolean(_id, _name,\ + _default_value, _flags) \ + {\ + .id = (_id), \ + .type = V4L2_CTRL_TYPE_BOOLEAN, \ + .name = _name, \ + .minimum = 0, \ + .maximum = 1, \ + .step = 1, \ + .default_value = (_default_value),\ + .flags = (_flags),\ + } + +#define s_ctrl_id_entry_integer(_id, _name, \ + _minimum, _maximum, _step, \ + _default_value, _flags, \ + _s_ctrl, _g_ctrl) \ + {\ + .qc = v4l2_queryctrl_entry_integer(_id, _name,\ + _minimum, _maximum, _step,\ + _default_value, _flags), \ + .s_ctrl = _s_ctrl, \ + .g_ctrl = _g_ctrl, \ + } + +#define s_ctrl_id_entry_boolean(_id, _name, \ + _default_value, _flags, \ + _s_ctrl, _g_ctrl) \ + {\ + .qc = v4l2_queryctrl_entry_boolean(_id, _name,\ + _default_value, _flags), \ + .s_ctrl = _s_ctrl, \ + .g_ctrl = _g_ctrl, \ + } + +/* Value settings for Flash Time-out Duration*/ +#define LM3554_DEFAULT_TIMEOUT 512U +#define LM3554_MIN_TIMEOUT 32U +#define LM3554_MAX_TIMEOUT 1024U +#define LM3554_TIMEOUT_STEPSIZE 32U + +/* Flash modes */ +#define LM3554_MODE_SHUTDOWN 0 +#define LM3554_MODE_INDICATOR 1 +#define LM3554_MODE_TORCH 2 +#define LM3554_MODE_FLASH 3 + +/* timer delay time */ +#define LM3554_TIMER_DELAY 5 + +/* Percentage <-> value macros */ +#define LM3554_MIN_PERCENT 0U +#define LM3554_MAX_PERCENT 100U +#define LM3554_CLAMP_PERCENTAGE(val) \ + clamp(val, LM3554_MIN_PERCENT, LM3554_MAX_PERCENT) + +#define LM3554_VALUE_TO_PERCENT(v, step) (((((unsigned long)(v)) * (step)) + 50) / 100) +#define LM3554_PERCENT_TO_VALUE(p, step) (((((unsigned long)(p)) * 100) + (step >> 1)) / (step)) + +/* Product specific limits + * TODO: get these from platform data */ +#define LM3554_FLASH_MAX_LVL 0x0F /* 1191mA */ + +/* Flash brightness, input is percentage, output is [0..15] */ +#define LM3554_FLASH_STEP \ + ((100ul * (LM3554_MAX_PERCENT) + ((LM3554_FLASH_MAX_LVL) >> 1)) / ((LM3554_FLASH_MAX_LVL))) +#define LM3554_FLASH_DEFAULT_BRIGHTNESS \ + LM3554_VALUE_TO_PERCENT(13, LM3554_FLASH_STEP) + +/* Torch brightness, input is percentage, output is [0..7] */ +#define LM3554_TORCH_STEP 1250 +#define LM3554_TORCH_DEFAULT_BRIGHTNESS \ + LM3554_VALUE_TO_PERCENT(2, LM3554_TORCH_STEP) + +/* Indicator brightness, input is percentage, output is [0..3] */ +#define LM3554_INDICATOR_STEP 2500 +#define LM3554_INDICATOR_DEFAULT_BRIGHTNESS \ + LM3554_VALUE_TO_PERCENT(1, LM3554_INDICATOR_STEP) + +/* + * lm3554_platform_data - Flash controller platform data + */ +struct lm3554_platform_data { + struct gpio_desc *gpio_torch; + struct gpio_desc *gpio_strobe; + struct gpio_desc *gpio_reset; + + unsigned int current_limit; + unsigned int envm_tx2; + unsigned int tx2_polarity; +}; + +#endif /* _LM3554_H_ */ diff --git a/drivers/staging/media/atomisp/include/mmu/isp_mmu.h b/drivers/staging/media/atomisp/include/mmu/isp_mmu.h new file mode 100644 index 000000000..268560954 --- /dev/null +++ b/drivers/staging/media/atomisp/include/mmu/isp_mmu.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +/* + * ISP MMU driver for classic two-level page tables + */ +#ifndef __ISP_MMU_H__ +#define __ISP_MMU_H__ + +#include +#include +#include + +/* + * do not change these values, the page size for ISP must be the + * same as kernel's page size. + */ +#define ISP_PAGE_OFFSET 12 +#define ISP_PAGE_SIZE BIT(ISP_PAGE_OFFSET) +#define ISP_PAGE_MASK (~(phys_addr_t)(ISP_PAGE_SIZE - 1)) + +#define ISP_L1PT_OFFSET 22 +#define ISP_L1PT_MASK (~((1U << ISP_L1PT_OFFSET) - 1)) + +#define ISP_L2PT_OFFSET 12 +#define ISP_L2PT_MASK (~(ISP_L1PT_MASK | (~(ISP_PAGE_MASK)))) + +#define ISP_L1PT_PTES 1024 +#define ISP_L2PT_PTES 1024 + +#define ISP_PTR_TO_L1_IDX(x) ((((x) & ISP_L1PT_MASK)) \ + >> ISP_L1PT_OFFSET) + +#define ISP_PTR_TO_L2_IDX(x) ((((x) & ISP_L2PT_MASK)) \ + >> ISP_L2PT_OFFSET) + +#define ISP_PAGE_ALIGN(x) (((x) + (ISP_PAGE_SIZE - 1)) \ + & ISP_PAGE_MASK) + +#define ISP_PT_TO_VIRT(l1_idx, l2_idx, offset) do {\ + ((l1_idx) << ISP_L1PT_OFFSET) | \ + ((l2_idx) << ISP_L2PT_OFFSET) | \ + (offset)\ +} while (0) + +#define pgnr_to_size(pgnr) ((pgnr) << ISP_PAGE_OFFSET) +#define size_to_pgnr_ceil(size) (((size) + (1 << ISP_PAGE_OFFSET) - 1)\ + >> ISP_PAGE_OFFSET) +#define size_to_pgnr_bottom(size) ((size) >> ISP_PAGE_OFFSET) + +struct isp_mmu; + +struct isp_mmu_client { + /* + * const value + * + * @name: + * driver name + * @pte_valid_mask: + * should be 1 bit valid data, meaning the value should + * be power of 2. + */ + char *name; + unsigned int pte_valid_mask; + unsigned int null_pte; + + /* + * get page directory base address (physical address). + * + * must be provided. + */ + unsigned int (*get_pd_base)(struct isp_mmu *mmu, phys_addr_t pd_base); + /* + * callback to flush tlb. + * + * tlb_flush_range will at least flush TLBs containing + * address mapping from addr to addr + size. + * + * tlb_flush_all will flush all TLBs. + * + * tlb_flush_all is must be provided. if tlb_flush_range is + * not valid, it will set to tlb_flush_all by default. + */ + void (*tlb_flush_range)(struct isp_mmu *mmu, + unsigned int addr, unsigned int size); + void (*tlb_flush_all)(struct isp_mmu *mmu); + unsigned int (*phys_to_pte)(struct isp_mmu *mmu, + phys_addr_t phys); + phys_addr_t (*pte_to_phys)(struct isp_mmu *mmu, + unsigned int pte); + +}; + +struct isp_mmu { + struct isp_mmu_client *driver; + unsigned int l1_pte; + int l2_pgt_refcount[ISP_L1PT_PTES]; + phys_addr_t base_address; + + struct mutex pt_mutex; +}; + +/* flags for PDE and PTE */ +#define ISP_PTE_VALID_MASK(mmu) \ + ((mmu)->driver->pte_valid_mask) + +#define ISP_PTE_VALID(mmu, pte) \ + ((pte) & ISP_PTE_VALID_MASK(mmu)) + +#define NULL_PAGE ((phys_addr_t)(-1) & ISP_PAGE_MASK) +#define PAGE_VALID(page) ((page) != NULL_PAGE) + +/* + * init mmu with specific mmu driver. + */ +int isp_mmu_init(struct isp_mmu *mmu, struct isp_mmu_client *driver); +/* + * cleanup all mmu related things. + */ +void isp_mmu_exit(struct isp_mmu *mmu); + +/* + * setup/remove address mapping for pgnr continuous physical pages + * and isp_virt. + * + * map/unmap is mutex lock protected, and caller does not have + * to do lock/unlock operation. + * + * map/unmap will not flush tlb, and caller needs to deal with + * this itself. + */ +int isp_mmu_map(struct isp_mmu *mmu, unsigned int isp_virt, + phys_addr_t phys, unsigned int pgnr); + +void isp_mmu_unmap(struct isp_mmu *mmu, unsigned int isp_virt, + unsigned int pgnr); + +static inline void isp_mmu_flush_tlb_all(struct isp_mmu *mmu) +{ + if (mmu->driver && mmu->driver->tlb_flush_all) + mmu->driver->tlb_flush_all(mmu); +} + +#define isp_mmu_flush_tlb isp_mmu_flush_tlb_all + +static inline void isp_mmu_flush_tlb_range(struct isp_mmu *mmu, + unsigned int start, unsigned int size) +{ + if (mmu->driver && mmu->driver->tlb_flush_range) + mmu->driver->tlb_flush_range(mmu, start, size); +} + +#endif /* ISP_MMU_H_ */ diff --git a/drivers/staging/media/atomisp/include/mmu/sh_mmu_mrfld.h b/drivers/staging/media/atomisp/include/mmu/sh_mmu_mrfld.h new file mode 100644 index 000000000..84fe7a368 --- /dev/null +++ b/drivers/staging/media/atomisp/include/mmu/sh_mmu_mrfld.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Merrifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __SH_MMU_MRFLD_H__ +#define __SH_MMU_MRFLD_H__ + +extern struct isp_mmu_client sh_mmu_mrfld; +#endif diff --git a/drivers/staging/media/atomisp/notes.txt b/drivers/staging/media/atomisp/notes.txt new file mode 100644 index 000000000..d3cf6ed54 --- /dev/null +++ b/drivers/staging/media/atomisp/notes.txt @@ -0,0 +1,49 @@ +Some notes about the working of the atomisp drivers (learned while working +on cleaning it up). + +The atomisp seems to be a generic DSP(ISP) like processor without a fixed +pipeline. It does not have its own memory, but instead uses main memory. +The ISP has its own address-space and main memory needs to be mapped into +its address space through the ISP's MMU. + +Memory is allocated by the hmm code. hmm_alloc() returns an ISP virtual +address. The hmm code keeps a list of all allocations and when necessary +the hmm code finds the backing hmm-buffer-object (hmm_bo) by looking +up the hmm_bo based on the ISP virtual address. + +The actual processing pipeline is made by loading one or more programs, +called binaries. The shisp_240??0_v21.bin firmware file contains many +different binaries. Binaries are picked by filling a ia_css_binary_descr +struct with various input and output parameters and then calling +ia_css_binary_find(). Some binaries support creating multiple outputs +(preview + video frame?) at the same time. + +For example for the /dev/video0 preview node load_preview_binaries() +from atomisp/pci/sh_css.c is called and then loads a preview and +optionally a scalar binary. Note when digital zoom is disabled +(it is enabled by default) only the preview binary is loaded. +So in this case a single binary handles the entire pipeline. + +Since getting a picture requires multiple processing steps, +this means that unlike in fixed pipelines the soft pipelines +on the ISP can do multiple processing steps in a single pipeline +element (in a single binary). + +### + +The sensor drivers use of v4l2_get_subdev_hostdata(), which returns +a camera_mipi_info struct. This struct is allocated/managed by +the core atomisp code. The most important parts of the struct +are filled by the atomisp core itself, like e.g. the port number. + +The sensor drivers on a set_fmt call do fill in camera_mipi_info.data +which is a atomisp_sensor_mode_data struct. This gets filled from +a function called _get_intg_factor(). This struct is not +used by the atomisp code at all. It is returned to userspace by +a ATOMISP_IOC_G_SENSOR_MODE_DATA and the Android userspace does use this. + +Other members of camera_mipi_info which are set by some drivers are: +-metadata_width, metadata_height, metadata_effective_width, set by + the ov5693 driver (and used by the atomisp core) +-raw_bayer_order, adjusted by the ov2680 driver when flipping since + flipping can change the bayer order diff --git a/drivers/staging/media/atomisp/pci/atomisp-regs.h b/drivers/staging/media/atomisp/pci/atomisp-regs.h new file mode 100644 index 000000000..022997f47 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp-regs.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef ATOMISP_REGS_H +#define ATOMISP_REGS_H + +/* common register definitions */ +#define PCICMDSTS 0x01 +#define INTR 0x0f +#define MSI_CAPID 0x24 +#define MSI_ADDRESS 0x25 +#define MSI_DATA 0x26 +#define INTR_CTL 0x27 + +#define PCI_MSI_CAPID 0x90 +#define PCI_MSI_ADDR 0x94 +#define PCI_MSI_DATA 0x98 +#define PCI_INTERRUPT_CTRL 0x9C +#define PCI_I_CONTROL 0xfc + +/* MRFLD specific register definitions */ +#define MRFLD_CSI_AFE 0x39 +#define MRFLD_CSI_CONTROL 0x3a +#define MRFLD_CSI_RCOMP 0x3d + +#define MRFLD_PCI_PMCS 0x84 +#define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL 0xd4 +#define MRFLD_PCI_CSI_AFE_HS_CONTROL 0xdc +#define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL 0xe0 +#define MRFLD_PCI_CSI_CONTROL 0xe8 +#define MRFLD_PCI_CSI_AFE_TRIM_CONTROL 0xe4 +#define MRFLD_PCI_CSI_DEADLINE_CONTROL 0xec +#define MRFLD_PCI_CSI_RCOMP_CONTROL 0xf4 + +/* Select Arasan (legacy)/Intel input system */ +#define MRFLD_PCI_CSI_CONTROL_PARPATHEN BIT(24) +/* Enable CSI interface (ANN B0/K0) */ +#define MRFLD_PCI_CSI_CONTROL_CSI_READY BIT(25) + +/* + * Enables the combining of adjacent 32-byte read requests to the same + * cache line. When cleared, each 32-byte read request is sent as a + * separate request on the IB interface. + */ +#define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING 0x1 + +/* + * Register: MRFLD_PCI_CSI_RCOMP_CONTROL + * If cleared, the high speed clock going to the digital logic is gated when + * RCOMP update is happening. The clock is gated for a minimum of 100 nsec. + * If this bit is set, then the high speed clock is not gated during the + * update cycle. + */ +#define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE 0x800000 + +/* + * Enables the combining of adjacent 32-byte write requests to the same + * cache line. When cleared, each 32-byte write request is sent as a + * separate request on the IB interface. + */ +#define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING 0x2 + +#define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK 0xc + +#define MRFLD_PCI_CSI1_HSRXCLKTRIM 0x2 +#define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT 16 +#define MRFLD_PCI_CSI2_HSRXCLKTRIM 0x3 +#define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT 24 +#define MRFLD_PCI_CSI3_HSRXCLKTRIM 0x2 +#define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT 28 +#define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK 0xf + +/* + * This register is IUINT MMIO register, it is used to select the CSI + * receiver backend. + * 1: SH CSI backend + * 0: Arasan CSI backend + */ +#define MRFLD_CSI_RECEIVER_SELECTION_REG 0x8081c + +#define MRFLD_INTR_CLEAR_REG 0x50c +#define MRFLD_INTR_STATUS_REG 0x508 +#define MRFLD_INTR_ENABLE_REG 0x510 + +#define MRFLD_MAX_ZOOM_FACTOR 1024 + +/* MRFLD ISP POWER related */ +#define MRFLD_ISPSSPM0 0x39 +#define MRFLD_ISPSSPM0_ISPSSC_OFFSET 0 +#define MRFLD_ISPSSPM0_ISPSSS_OFFSET 24 +#define MRFLD_ISPSSPM0_ISPSSC_MASK 0x3 +#define MRFLD_ISPSSPM0_IUNIT_POWER_ON 0 +#define MRFLD_ISPSSPM0_IUNIT_POWER_OFF 0x3 +#define MRFLD_ISPSSDVFS 0x13F +#define MRFLD_BIT0 0x0001 +#define MRFLD_BIT1 0x0002 + +/* MRFLD CSI lane configuration related */ +#define MRFLD_PORT_CONFIG_NUM 8 +#define MRFLD_PORT_NUM 3 +#define MRFLD_PORT1_ENABLE_SHIFT 0 +#define MRFLD_PORT2_ENABLE_SHIFT 1 +#define MRFLD_PORT3_ENABLE_SHIFT 2 +#define MRFLD_PORT1_LANES_SHIFT 3 +#define MRFLD_PORT2_LANES_SHIFT 7 +#define MRFLD_PORT3_LANES_SHIFT 8 +#define MRFLD_PORT_CONFIG_MASK 0x000f03ff +#define MRFLD_PORT_CONFIGCODE_SHIFT 16 +#define MRFLD_ALL_CSI_PORTS_OFF_MASK 0x7 + +#define CHV_PORT3_LANES_SHIFT 9 +#define CHV_PORT_CONFIG_MASK 0x1f07ff + +#define ISPSSPM1 0x3a +#define ISP_FREQ_STAT_MASK (0x1f << ISP_FREQ_STAT_OFFSET) +#define ISP_REQ_FREQ_MASK 0x1f +#define ISP_FREQ_VALID_MASK (0x1 << ISP_FREQ_VALID_OFFSET) +#define ISP_FREQ_STAT_OFFSET 0x18 +#define ISP_REQ_GUAR_FREQ_OFFSET 0x8 +#define ISP_REQ_FREQ_OFFSET 0x0 +#define ISP_FREQ_VALID_OFFSET 0x7 +#define ISP_FREQ_RULE_ANY 0x0 + +#define ISP_FREQ_457MHZ 0x1C9 +#define ISP_FREQ_400MHZ 0x190 +#define ISP_FREQ_356MHZ 0x164 +#define ISP_FREQ_320MHZ 0x140 +#define ISP_FREQ_266MHZ 0x10a +#define ISP_FREQ_200MHZ 0xc8 +#define ISP_FREQ_100MHZ 0x64 + +#define HPLL_FREQ_800MHZ 0x320 +#define HPLL_FREQ_1600MHZ 0x640 +#define HPLL_FREQ_2000MHZ 0x7D0 + +#define CCK_FUSE_REG_0 0x08 +#define CCK_FUSE_HPLL_FREQ_MASK 0x03 + +/* ISP2401 CSI2+ receiver delay settings */ +#define CSI2_PORT_A_BASE 0xC0000 +#define CSI2_PORT_B_BASE 0xC2000 +#define CSI2_PORT_C_BASE 0xC4000 + +#define CSI2_LANE_CL_BASE 0x418 +#define CSI2_LANE_D0_BASE 0x420 +#define CSI2_LANE_D1_BASE 0x428 +#define CSI2_LANE_D2_BASE 0x430 +#define CSI2_LANE_D3_BASE 0x438 + +#define CSI2_REG_RX_CSI_DLY_CNT_TERMEN 0 +#define CSI2_REG_RX_CSI_DLY_CNT_SETTLE 0x4 + +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC0418 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC041C +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC0420 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC0424 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC0428 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC042C +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE2 0xC0430 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE2 0xC0434 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE3 0xC0438 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE3 0xC043C + +#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC2418 +#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC241C +#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC2420 +#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC2424 +#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC2428 +#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC242C + +#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC4418 +#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC441C +#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC4420 +#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC4424 +#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC4428 +#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC442C + +#define DMA_BURST_SIZE_REG 0xCD408 + +#define ISP_DFS_TRY_TIMES 2 + +#endif /* ATOMISP_REGS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_cmd.c b/drivers/staging/media/atomisp/pci/atomisp_cmd.c new file mode 100644 index 000000000..d8c7e7367 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_cmd.c @@ -0,0 +1,5933 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define CREATE_TRACE_POINTS +#include "atomisp_trace_event.h" + +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_fops.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" +#include "atomisp-regs.h" +#include "atomisp_tables.h" +#include "atomisp_compat.h" +#include "atomisp_subdev.h" +#include "atomisp_dfs_tables.h" + +#include + +#include "sh_css_hrt.h" +#include "sh_css_defs.h" +#include "system_global.h" +#include "sh_css_internal.h" +#include "sh_css_sp.h" +#include "gp_device.h" +#include "device_access.h" +#include "irq.h" + +#include "ia_css_types.h" +#include "ia_css_stream.h" +#include "ia_css_debug.h" +#include "bits.h" + +/* We should never need to run the flash for more than 2 frames. + * At 15fps this means 133ms. We set the timeout a bit longer. + * Each flash driver is supposed to set its own timeout, but + * just in case someone else changed the timeout, we set it + * here to make sure we don't damage the flash hardware. */ +#define FLASH_TIMEOUT 800 /* ms */ + +union host { + struct { + void *kernel_ptr; + void __user *user_ptr; + int size; + } scalar; + struct { + void *hmm_ptr; + } ptr; +}; + +static int atomisp_set_raw_buffer_bitmap(struct atomisp_sub_device *asd, int exp_id); + +/* + * get sensor:dis71430/ov2720 related info from v4l2_subdev->priv data field. + * subdev->priv is set in mrst.c + */ +struct camera_mipi_info *atomisp_to_sensor_mipi_info(struct v4l2_subdev *sd) +{ + return (struct camera_mipi_info *)v4l2_get_subdev_hostdata(sd); +} + +/* + * get struct atomisp_video_pipe from v4l2 video_device + */ +struct atomisp_video_pipe *atomisp_to_video_pipe(struct video_device *dev) +{ + return (struct atomisp_video_pipe *) + container_of(dev, struct atomisp_video_pipe, vdev); +} + +static unsigned short atomisp_get_sensor_fps(struct atomisp_sub_device *asd) +{ + struct v4l2_subdev_frame_interval fi = { 0 }; + struct atomisp_device *isp = asd->isp; + + unsigned short fps = 0; + int ret; + + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, g_frame_interval, &fi); + + if (!ret && fi.interval.numerator) + fps = fi.interval.denominator / fi.interval.numerator; + + return fps; +} + +/* + * DFS progress is shown as follows: + * 1. Target frequency is calculated according to FPS/Resolution/ISP running + * mode. + * 2. Ratio is calculated using formula: 2 * HPLL / target frequency - 1 + * with proper rounding. + * 3. Set ratio to ISPFREQ40, 1 to FREQVALID and ISPFREQGUAR40 + * to 200MHz in ISPSSPM1. + * 4. Wait for FREQVALID to be cleared by P-Unit. + * 5. Wait for field ISPFREQSTAT40 in ISPSSPM1 turn to ratio set in 3. + */ +static int write_target_freq_to_hw(struct atomisp_device *isp, + unsigned int new_freq) +{ + unsigned int ratio, timeout, guar_ratio; + u32 isp_sspm1 = 0; + int i; + + if (!isp->hpll_freq) { + dev_err(isp->dev, "failed to get hpll_freq. no change to freq\n"); + return -EINVAL; + } + + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM1, &isp_sspm1); + if (isp_sspm1 & ISP_FREQ_VALID_MASK) { + dev_dbg(isp->dev, "clearing ISPSSPM1 valid bit.\n"); + iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, ISPSSPM1, + isp_sspm1 & ~(1 << ISP_FREQ_VALID_OFFSET)); + } + + ratio = (2 * isp->hpll_freq + new_freq / 2) / new_freq - 1; + guar_ratio = (2 * isp->hpll_freq + 200 / 2) / 200 - 1; + + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM1, &isp_sspm1); + isp_sspm1 &= ~(0x1F << ISP_REQ_FREQ_OFFSET); + + for (i = 0; i < ISP_DFS_TRY_TIMES; i++) { + iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, ISPSSPM1, + isp_sspm1 + | ratio << ISP_REQ_FREQ_OFFSET + | 1 << ISP_FREQ_VALID_OFFSET + | guar_ratio << ISP_REQ_GUAR_FREQ_OFFSET); + + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM1, &isp_sspm1); + timeout = 20; + while ((isp_sspm1 & ISP_FREQ_VALID_MASK) && timeout) { + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM1, &isp_sspm1); + dev_dbg(isp->dev, "waiting for ISPSSPM1 valid bit to be 0.\n"); + udelay(100); + timeout--; + } + + if (timeout != 0) + break; + } + + if (timeout == 0) { + dev_err(isp->dev, "DFS failed due to HW error.\n"); + return -EINVAL; + } + + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM1, &isp_sspm1); + timeout = 10; + while (((isp_sspm1 >> ISP_FREQ_STAT_OFFSET) != ratio) && timeout) { + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM1, &isp_sspm1); + dev_dbg(isp->dev, "waiting for ISPSSPM1 status bit to be 0x%x.\n", + new_freq); + udelay(100); + timeout--; + } + if (timeout == 0) { + dev_err(isp->dev, "DFS target freq is rejected by HW.\n"); + return -EINVAL; + } + + return 0; +} + +int atomisp_freq_scaling(struct atomisp_device *isp, + enum atomisp_dfs_mode mode, + bool force) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + /* FIXME! Only use subdev[0] status yet */ + struct atomisp_sub_device *asd = &isp->asd[0]; + const struct atomisp_dfs_config *dfs; + unsigned int new_freq; + struct atomisp_freq_scaling_rule curr_rules; + int i, ret; + unsigned short fps = 0; + + if ((pdev->device & ATOMISP_PCI_DEVICE_SOC_MASK) == + ATOMISP_PCI_DEVICE_SOC_CHT && ATOMISP_USE_YUVPP(asd)) + isp->dfs = &dfs_config_cht_soc; + + dfs = isp->dfs; + + if (dfs->lowest_freq == 0 || dfs->max_freq_at_vmin == 0 || + dfs->highest_freq == 0 || dfs->dfs_table_size == 0 || + !dfs->dfs_table) { + dev_err(isp->dev, "DFS configuration is invalid.\n"); + return -EINVAL; + } + + if (mode == ATOMISP_DFS_MODE_LOW) { + new_freq = dfs->lowest_freq; + goto done; + } + + if (mode == ATOMISP_DFS_MODE_MAX) { + new_freq = dfs->highest_freq; + goto done; + } + + fps = atomisp_get_sensor_fps(asd); + if (fps == 0) { + dev_info(isp->dev, + "Sensor didn't report FPS. Using DFS max mode.\n"); + new_freq = dfs->highest_freq; + goto done; + } + + curr_rules.width = asd->fmt[asd->capture_pad].fmt.width; + curr_rules.height = asd->fmt[asd->capture_pad].fmt.height; + curr_rules.fps = fps; + curr_rules.run_mode = asd->run_mode->val; + /* + * For continuous mode, we need to make the capture setting applied + * since preview mode, because there is no chance to do this when + * starting image capture. + */ + if (asd->continuous_mode->val) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + curr_rules.run_mode = ATOMISP_RUN_MODE_SDV; + else + curr_rules.run_mode = + ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE; + } + + /* search for the target frequency by looping freq rules*/ + for (i = 0; i < dfs->dfs_table_size; i++) { + if (curr_rules.width != dfs->dfs_table[i].width && + dfs->dfs_table[i].width != ISP_FREQ_RULE_ANY) + continue; + if (curr_rules.height != dfs->dfs_table[i].height && + dfs->dfs_table[i].height != ISP_FREQ_RULE_ANY) + continue; + if (curr_rules.fps != dfs->dfs_table[i].fps && + dfs->dfs_table[i].fps != ISP_FREQ_RULE_ANY) + continue; + if (curr_rules.run_mode != dfs->dfs_table[i].run_mode && + dfs->dfs_table[i].run_mode != ISP_FREQ_RULE_ANY) + continue; + break; + } + + if (i == dfs->dfs_table_size) + new_freq = dfs->max_freq_at_vmin; + else + new_freq = dfs->dfs_table[i].isp_freq; + +done: + dev_dbg(isp->dev, "DFS target frequency=%d.\n", new_freq); + + if ((new_freq == isp->sw_contex.running_freq) && !force) + return 0; + + dev_dbg(isp->dev, "Programming DFS frequency to %d\n", new_freq); + + ret = write_target_freq_to_hw(isp, new_freq); + if (!ret) { + isp->sw_contex.running_freq = new_freq; + trace_ipu_pstate(new_freq, -1); + } + return ret; +} + +/* + * reset and restore ISP + */ +int atomisp_reset(struct atomisp_device *isp) +{ + /* Reset ISP by power-cycling it */ + int ret = 0; + + dev_dbg(isp->dev, "%s\n", __func__); + + ret = atomisp_power_off(isp->dev); + if (ret < 0) + dev_err(isp->dev, "atomisp_power_off failed, %d\n", ret); + + ret = atomisp_power_on(isp->dev); + if (ret < 0) { + dev_err(isp->dev, "atomisp_power_on failed, %d\n", ret); + isp->isp_fatal_error = true; + } + + return ret; +} + +/* + * interrupt disable functions + */ +static void disable_isp_irq(enum hrt_isp_css_irq irq) +{ + irq_disable_channel(IRQ0_ID, irq); + + if (irq != hrt_isp_css_irq_sp) + return; + + cnd_sp_irq_enable(SP0_ID, false); +} + +/* + * interrupt clean function + */ +static void clear_isp_irq(enum hrt_isp_css_irq irq) +{ + irq_clear_all(IRQ0_ID); +} + +void atomisp_msi_irq_init(struct atomisp_device *isp) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + u32 msg32; + u16 msg16; + + pci_read_config_dword(pdev, PCI_MSI_CAPID, &msg32); + msg32 |= 1 << MSI_ENABLE_BIT; + pci_write_config_dword(pdev, PCI_MSI_CAPID, msg32); + + msg32 = (1 << INTR_IER) | (1 << INTR_IIR); + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg32); + + pci_read_config_word(pdev, PCI_COMMAND, &msg16); + msg16 |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_INTX_DISABLE); + pci_write_config_word(pdev, PCI_COMMAND, msg16); +} + +void atomisp_msi_irq_uninit(struct atomisp_device *isp) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + u32 msg32; + u16 msg16; + + pci_read_config_dword(pdev, PCI_MSI_CAPID, &msg32); + msg32 &= ~(1 << MSI_ENABLE_BIT); + pci_write_config_dword(pdev, PCI_MSI_CAPID, msg32); + + msg32 = 0x0; + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg32); + + pci_read_config_word(pdev, PCI_COMMAND, &msg16); + msg16 &= ~(PCI_COMMAND_MASTER); + pci_write_config_word(pdev, PCI_COMMAND, msg16); +} + +static void atomisp_sof_event(struct atomisp_sub_device *asd) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_FRAME_SYNC; + event.u.frame_sync.frame_sequence = atomic_read(&asd->sof_count); + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +void atomisp_eof_event(struct atomisp_sub_device *asd, uint8_t exp_id) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_FRAME_END; + event.u.frame_sync.frame_sequence = exp_id; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +static void atomisp_3a_stats_ready_event(struct atomisp_sub_device *asd, + uint8_t exp_id) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_ATOMISP_3A_STATS_READY; + event.u.frame_sync.frame_sequence = exp_id; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +static void atomisp_metadata_ready_event(struct atomisp_sub_device *asd, + enum atomisp_metadata_type md_type) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_ATOMISP_METADATA_READY; + event.u.data[0] = md_type; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +static void atomisp_reset_event(struct atomisp_sub_device *asd) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_ATOMISP_CSS_RESET; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +static void print_csi_rx_errors(enum mipi_port_id port, + struct atomisp_device *isp) +{ + u32 infos = 0; + + atomisp_css_rx_get_irq_info(port, &infos); + + dev_err(isp->dev, "CSI Receiver port %d errors:\n", port); + if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN) + dev_err(isp->dev, " buffer overrun"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT) + dev_err(isp->dev, " start-of-transmission error"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC) + dev_err(isp->dev, " start-of-transmission sync error"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL) + dev_err(isp->dev, " control error"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) + dev_err(isp->dev, " 2 or more ECC errors"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC) + dev_err(isp->dev, " CRC mismatch"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) + dev_err(isp->dev, " unknown error"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) + dev_err(isp->dev, " frame sync error"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA) + dev_err(isp->dev, " frame data error"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) + dev_err(isp->dev, " data timeout"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) + dev_err(isp->dev, " unknown escape command entry"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC) + dev_err(isp->dev, " line sync error"); +} + +/* Clear irq reg */ +static void clear_irq_reg(struct atomisp_device *isp) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + u32 msg_ret; + + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &msg_ret); + msg_ret |= 1 << INTR_IIR; + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg_ret); +} + +static struct atomisp_sub_device * +__get_asd_from_port(struct atomisp_device *isp, enum mipi_port_id port) +{ + int i; + + /* Check which isp subdev to send eof */ + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + struct camera_mipi_info *mipi_info; + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED && + __get_mipi_port(isp, mipi_info->port) == port) { + return asd; + } + } + + return NULL; +} + +/* interrupt handling function*/ +irqreturn_t atomisp_isr(int irq, void *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *)dev; + struct atomisp_sub_device *asd; + struct atomisp_css_event eof_event; + unsigned int irq_infos = 0; + unsigned long flags; + unsigned int i; + int err; + + spin_lock_irqsave(&isp->lock, flags); + + if (!isp->css_initialized) { + spin_unlock_irqrestore(&isp->lock, flags); + return IRQ_HANDLED; + } + err = atomisp_css_irq_translate(isp, &irq_infos); + if (err) { + spin_unlock_irqrestore(&isp->lock, flags); + return IRQ_NONE; + } + + clear_irq_reg(isp); + + if (!atomisp_streaming_count(isp)) + goto out_nowake; + + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + continue; + /* + * Current SOF only support one stream, so the SOF only valid + * either solely one stream is running + */ + if (irq_infos & IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF) { + atomic_inc(&asd->sof_count); + atomisp_sof_event(asd); + + /* If sequence_temp and sequence are the same + * there where no frames lost so we can increase + * sequence_temp. + * If not then processing of frame is still in progress + * and driver needs to keep old sequence_temp value. + * NOTE: There is assumption here that ISP will not + * start processing next frame from sensor before old + * one is completely done. */ + if (atomic_read(&asd->sequence) == atomic_read( + &asd->sequence_temp)) + atomic_set(&asd->sequence_temp, + atomic_read(&asd->sof_count)); + } + if (irq_infos & IA_CSS_IRQ_INFO_EVENTS_READY) + atomic_set(&asd->sequence, + atomic_read(&asd->sequence_temp)); + } + + if (irq_infos & IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF) { + dev_dbg_ratelimited(isp->dev, + "irq:0x%x (SOF)\n", + irq_infos); + irq_infos &= ~IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF; + } + + if ((irq_infos & IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR) || + (irq_infos & IA_CSS_IRQ_INFO_IF_ERROR)) { + /* handle mipi receiver error */ + u32 rx_infos; + enum mipi_port_id port; + + for (port = MIPI_PORT0_ID; port <= MIPI_PORT2_ID; + port++) { + print_csi_rx_errors(port, isp); + atomisp_css_rx_get_irq_info(port, &rx_infos); + atomisp_css_rx_clear_irq_info(port, rx_infos); + } + } + + if (irq_infos & IA_CSS_IRQ_INFO_ISYS_EVENTS_READY) { + while (ia_css_dequeue_isys_event(&eof_event.event) == + 0) { + /* EOF Event does not have the css_pipe returned */ + asd = __get_asd_from_port(isp, eof_event.event.port); + if (!asd) { + dev_err(isp->dev, "%s: ISYS event, but no subdev.event:%d", + __func__, eof_event.event.type); + continue; + } + + atomisp_eof_event(asd, eof_event.event.exp_id); + dev_dbg_ratelimited(isp->dev, + "%s ISYS event: EOF exp_id %d, asd %d\n", + __func__, eof_event.event.exp_id, + asd->index); + } + + irq_infos &= ~IA_CSS_IRQ_INFO_ISYS_EVENTS_READY; + if (irq_infos == 0) + goto out_nowake; + } + + spin_unlock_irqrestore(&isp->lock, flags); + + dev_dbg_ratelimited(isp->dev, "irq:0x%x (unhandled)\n", irq_infos); + + return IRQ_WAKE_THREAD; + +out_nowake: + spin_unlock_irqrestore(&isp->lock, flags); + + if (irq_infos) + dev_dbg_ratelimited(isp->dev, "irq:0x%x (ignored, as not streaming anymore)\n", + irq_infos); + + return IRQ_HANDLED; +} + +void atomisp_clear_css_buffer_counters(struct atomisp_sub_device *asd) +{ + int i; + + memset(asd->s3a_bufs_in_css, 0, sizeof(asd->s3a_bufs_in_css)); + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) + memset(asd->metadata_bufs_in_css[i], 0, + sizeof(asd->metadata_bufs_in_css[i])); + asd->dis_bufs_in_css = 0; +} + +/* 0x100000 is the start of dmem inside SP */ +#define SP_DMEM_BASE 0x100000 + +void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr, + unsigned int size) +{ + unsigned int data = 0; + unsigned int size32 = DIV_ROUND_UP(size, sizeof(u32)); + + dev_dbg(isp->dev, "atomisp mmio base: %p\n", isp->base); + dev_dbg(isp->dev, "%s, addr:0x%x, size: %d, size32: %d\n", __func__, + addr, size, size32); + if (size32 * 4 + addr > 0x4000) { + dev_err(isp->dev, "illegal size (%d) or addr (0x%x)\n", + size32, addr); + return; + } + addr += SP_DMEM_BASE; + addr &= 0x003FFFFF; + do { + data = readl(isp->base + addr); + dev_dbg(isp->dev, "%s, \t [0x%x]:0x%x\n", __func__, addr, data); + addr += sizeof(u32); + } while (--size32); +} + +int atomisp_buffers_in_css(struct atomisp_video_pipe *pipe) +{ + unsigned long irqflags; + struct list_head *pos; + int buffers_in_css = 0; + + spin_lock_irqsave(&pipe->irq_lock, irqflags); + + list_for_each(pos, &pipe->buffers_in_css) + buffers_in_css++; + + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + + return buffers_in_css; +} + +void atomisp_buffer_done(struct ia_css_frame *frame, enum vb2_buffer_state state) +{ + struct atomisp_video_pipe *pipe = vb_to_pipe(&frame->vb.vb2_buf); + + lockdep_assert_held(&pipe->irq_lock); + + frame->vb.vb2_buf.timestamp = ktime_get_ns(); + frame->vb.field = pipe->pix.field; + frame->vb.sequence = atomic_read(&pipe->asd->sequence); + list_del(&frame->queue); + if (state == VB2_BUF_STATE_DONE) + vb2_set_plane_payload(&frame->vb.vb2_buf, 0, pipe->pix.sizeimage); + vb2_buffer_done(&frame->vb.vb2_buf, state); +} + +void atomisp_flush_video_pipe(struct atomisp_video_pipe *pipe, bool warn_on_css_frames) +{ + struct ia_css_frame *frame, *_frame; + unsigned long irqflags; + + spin_lock_irqsave(&pipe->irq_lock, irqflags); + + list_for_each_entry_safe(frame, _frame, &pipe->buffers_in_css, queue) { + if (warn_on_css_frames) + dev_warn(pipe->isp->dev, "Warning: CSS frames queued on flush\n"); + atomisp_buffer_done(frame, VB2_BUF_STATE_ERROR); + } + + list_for_each_entry_safe(frame, _frame, &pipe->activeq, queue) + atomisp_buffer_done(frame, VB2_BUF_STATE_ERROR); + + list_for_each_entry_safe(frame, _frame, &pipe->buffers_waiting_for_param, queue) { + pipe->frame_request_config_id[frame->vb.vb2_buf.index] = 0; + atomisp_buffer_done(frame, VB2_BUF_STATE_ERROR); + } + + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); +} + +/* Returns queued buffers back to video-core */ +void atomisp_flush_bufs_and_wakeup(struct atomisp_sub_device *asd) +{ + atomisp_flush_video_pipe(&asd->video_out_capture, false); + atomisp_flush_video_pipe(&asd->video_out_vf, false); + atomisp_flush_video_pipe(&asd->video_out_preview, false); + atomisp_flush_video_pipe(&asd->video_out_video_capture, false); +} + +/* clean out the parameters that did not apply */ +void atomisp_flush_params_queue(struct atomisp_video_pipe *pipe) +{ + struct atomisp_css_params_with_list *param; + + while (!list_empty(&pipe->per_frame_params)) { + param = list_entry(pipe->per_frame_params.next, + struct atomisp_css_params_with_list, list); + list_del(¶m->list); + atomisp_free_css_parameters(¶m->params); + kvfree(param); + } +} + +/* Re-queue per-frame parameters */ +static void atomisp_recover_params_queue(struct atomisp_video_pipe *pipe) +{ + struct atomisp_css_params_with_list *param; + int i; + + for (i = 0; i < VIDEO_MAX_FRAME; i++) { + param = pipe->frame_params[i]; + if (param) + list_add_tail(¶m->list, &pipe->per_frame_params); + pipe->frame_params[i] = NULL; + } + atomisp_handle_parameter_and_buffer(pipe); +} + +enum atomisp_metadata_type +atomisp_get_metadata_type(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id) +{ + if (!asd->continuous_mode->val) + return ATOMISP_MAIN_METADATA; + + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) /* online capture pipe */ + return ATOMISP_SEC_METADATA; + else + return ATOMISP_MAIN_METADATA; +} + +void atomisp_buf_done(struct atomisp_sub_device *asd, int error, + enum ia_css_buffer_type buf_type, + enum ia_css_pipe_id css_pipe_id, + bool q_buffers, enum atomisp_input_stream_id stream_id) +{ + struct atomisp_video_pipe *pipe = NULL; + struct atomisp_css_buffer buffer; + bool requeue = false; + unsigned long irqflags; + struct ia_css_frame *frame = NULL; + struct atomisp_s3a_buf *s3a_buf = NULL, *_s3a_buf_tmp, *s3a_iter; + struct atomisp_dis_buf *dis_buf = NULL, *_dis_buf_tmp, *dis_iter; + struct atomisp_metadata_buf *md_buf = NULL, *_md_buf_tmp, *md_iter; + enum atomisp_metadata_type md_type; + struct atomisp_device *isp = asd->isp; + struct v4l2_control ctrl; + int i, err; + + lockdep_assert_held(&isp->mutex); + + if ( + buf_type != IA_CSS_BUFFER_TYPE_METADATA && + buf_type != IA_CSS_BUFFER_TYPE_3A_STATISTICS && + buf_type != IA_CSS_BUFFER_TYPE_DIS_STATISTICS && + buf_type != IA_CSS_BUFFER_TYPE_OUTPUT_FRAME && + buf_type != IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME && + buf_type != IA_CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME && + buf_type != IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME && + buf_type != IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) { + dev_err(isp->dev, "%s, unsupported buffer type: %d\n", + __func__, buf_type); + return; + } + + memset(&buffer, 0, sizeof(struct atomisp_css_buffer)); + buffer.css_buffer.type = buf_type; + err = atomisp_css_dequeue_buffer(asd, stream_id, css_pipe_id, + buf_type, &buffer); + if (err) { + dev_err(isp->dev, + "atomisp_css_dequeue_buffer failed: 0x%x\n", err); + return; + } + + switch (buf_type) { + case IA_CSS_BUFFER_TYPE_3A_STATISTICS: + list_for_each_entry_safe(s3a_iter, _s3a_buf_tmp, + &asd->s3a_stats_in_css, list) { + if (s3a_iter->s3a_data == + buffer.css_buffer.data.stats_3a) { + list_del_init(&s3a_iter->list); + list_add_tail(&s3a_iter->list, + &asd->s3a_stats_ready); + s3a_buf = s3a_iter; + break; + } + } + + asd->s3a_bufs_in_css[css_pipe_id]--; + atomisp_3a_stats_ready_event(asd, buffer.css_buffer.exp_id); + if (s3a_buf) + dev_dbg(isp->dev, "%s: s3a stat with exp_id %d is ready\n", + __func__, s3a_buf->s3a_data->exp_id); + else + dev_dbg(isp->dev, "%s: s3a stat is ready with no exp_id found\n", + __func__); + break; + case IA_CSS_BUFFER_TYPE_METADATA: + if (error) + break; + + md_type = atomisp_get_metadata_type(asd, css_pipe_id); + list_for_each_entry_safe(md_iter, _md_buf_tmp, + &asd->metadata_in_css[md_type], list) { + if (md_iter->metadata == + buffer.css_buffer.data.metadata) { + list_del_init(&md_iter->list); + list_add_tail(&md_iter->list, + &asd->metadata_ready[md_type]); + md_buf = md_iter; + break; + } + } + asd->metadata_bufs_in_css[stream_id][css_pipe_id]--; + atomisp_metadata_ready_event(asd, md_type); + if (md_buf) + dev_dbg(isp->dev, "%s: metadata with exp_id %d is ready\n", + __func__, md_buf->metadata->exp_id); + else + dev_dbg(isp->dev, "%s: metadata is ready with no exp_id found\n", + __func__); + break; + case IA_CSS_BUFFER_TYPE_DIS_STATISTICS: + list_for_each_entry_safe(dis_iter, _dis_buf_tmp, + &asd->dis_stats_in_css, list) { + if (dis_iter->dis_data == + buffer.css_buffer.data.stats_dvs) { + spin_lock_irqsave(&asd->dis_stats_lock, + irqflags); + list_del_init(&dis_iter->list); + list_add(&dis_iter->list, &asd->dis_stats); + asd->params.dis_proj_data_valid = true; + spin_unlock_irqrestore(&asd->dis_stats_lock, + irqflags); + dis_buf = dis_iter; + break; + } + } + asd->dis_bufs_in_css--; + if (dis_buf) + dev_dbg(isp->dev, "%s: dis stat with exp_id %d is ready\n", + __func__, dis_buf->dis_data->exp_id); + else + dev_dbg(isp->dev, "%s: dis stat is ready with no exp_id found\n", + __func__); + break; + case IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME: + case IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME: + frame = buffer.css_buffer.data.frame; + if (!frame) { + WARN_ON(1); + break; + } + if (!frame->valid) + error = true; + + pipe = vb_to_pipe(&frame->vb.vb2_buf); + + /* FIXME: + * YUVPP doesn't set postview exp_id correctlly in SDV mode. + * This is a WORKAROUND to set exp_id. see HSDES-1503911606. + */ + if (IS_BYT && buf_type == IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME && + asd->continuous_mode->val && ATOMISP_USE_YUVPP(asd)) + frame->exp_id = (asd->postview_exp_id++) % + (ATOMISP_MAX_EXP_ID + 1); + + dev_dbg(isp->dev, "%s: vf frame with exp_id %d is ready\n", + __func__, frame->exp_id); + if (asd->params.flash_state == ATOMISP_FLASH_ONGOING) { + if (frame->flash_state + == IA_CSS_FRAME_FLASH_STATE_PARTIAL) + dev_dbg(isp->dev, "%s thumb partially flashed\n", + __func__); + else if (frame->flash_state + == IA_CSS_FRAME_FLASH_STATE_FULL) + dev_dbg(isp->dev, "%s thumb completely flashed\n", + __func__); + else + dev_dbg(isp->dev, "%s thumb no flash in this frame\n", + __func__); + } + pipe->frame_config_id[frame->vb.vb2_buf.index] = frame->isp_config_id; + if (css_pipe_id == IA_CSS_PIPE_ID_CAPTURE && + asd->pending_capture_request > 0) { + err = atomisp_css_offline_capture_configure(asd, + asd->params.offline_parm.num_captures, + asd->params.offline_parm.skip_frames, + asd->params.offline_parm.offset); + + asd->pending_capture_request--; + + dev_dbg(isp->dev, "Trigger capture again for new buffer. err=%d\n", + err); + } + break; + case IA_CSS_BUFFER_TYPE_OUTPUT_FRAME: + case IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME: + frame = buffer.css_buffer.data.frame; + if (!frame) { + WARN_ON(1); + break; + } + + if (!frame->valid) + error = true; + + pipe = vb_to_pipe(&frame->vb.vb2_buf); + + /* FIXME: + * YUVPP doesn't set preview exp_id correctlly in ZSL mode. + * This is a WORKAROUND to set exp_id. see HSDES-1503911606. + */ + if (IS_BYT && buf_type == IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME && + asd->continuous_mode->val && ATOMISP_USE_YUVPP(asd)) + frame->exp_id = (asd->preview_exp_id++) % + (ATOMISP_MAX_EXP_ID + 1); + + dev_dbg(isp->dev, "%s: main frame with exp_id %d is ready\n", + __func__, frame->exp_id); + + i = frame->vb.vb2_buf.index; + + /* free the parameters */ + if (pipe->frame_params[i]) { + if (asd->params.dvs_6axis == pipe->frame_params[i]->params.dvs_6axis) + asd->params.dvs_6axis = NULL; + atomisp_free_css_parameters(&pipe->frame_params[i]->params); + kvfree(pipe->frame_params[i]); + pipe->frame_params[i] = NULL; + } + + pipe->frame_config_id[i] = frame->isp_config_id; + ctrl.id = V4L2_CID_FLASH_MODE; + if (asd->params.flash_state == ATOMISP_FLASH_ONGOING) { + if (frame->flash_state == IA_CSS_FRAME_FLASH_STATE_PARTIAL) { + asd->frame_status[i] = ATOMISP_FRAME_STATUS_FLASH_PARTIAL; + dev_dbg(isp->dev, "%s partially flashed\n", __func__); + } else if (frame->flash_state == IA_CSS_FRAME_FLASH_STATE_FULL) { + asd->frame_status[i] = ATOMISP_FRAME_STATUS_FLASH_EXPOSED; + asd->params.num_flash_frames--; + dev_dbg(isp->dev, "%s completely flashed\n", __func__); + } else { + asd->frame_status[i] = ATOMISP_FRAME_STATUS_OK; + dev_dbg(isp->dev, "%s no flash in this frame\n", __func__); + } + + /* Check if flashing sequence is done */ + if (asd->frame_status[i] == ATOMISP_FRAME_STATUS_FLASH_EXPOSED) + asd->params.flash_state = ATOMISP_FLASH_DONE; + } else if (isp->flash) { + if (v4l2_g_ctrl(isp->flash->ctrl_handler, &ctrl) == 0 && + ctrl.value == ATOMISP_FLASH_MODE_TORCH) { + ctrl.id = V4L2_CID_FLASH_TORCH_INTENSITY; + if (v4l2_g_ctrl(isp->flash->ctrl_handler, &ctrl) == 0 && + ctrl.value > 0) + asd->frame_status[i] = ATOMISP_FRAME_STATUS_FLASH_EXPOSED; + else + asd->frame_status[i] = ATOMISP_FRAME_STATUS_OK; + } else { + asd->frame_status[i] = ATOMISP_FRAME_STATUS_OK; + } + } else { + asd->frame_status[i] = ATOMISP_FRAME_STATUS_OK; + } + + asd->params.last_frame_status = asd->frame_status[i]; + + if (asd->continuous_mode->val) { + if (css_pipe_id == IA_CSS_PIPE_ID_PREVIEW || + css_pipe_id == IA_CSS_PIPE_ID_VIDEO) { + asd->latest_preview_exp_id = frame->exp_id; + } else if (css_pipe_id == + IA_CSS_PIPE_ID_CAPTURE) { + if (asd->run_mode->val == + ATOMISP_RUN_MODE_VIDEO) + dev_dbg(isp->dev, "SDV capture raw buffer id: %u\n", + frame->exp_id); + else + dev_dbg(isp->dev, "ZSL capture raw buffer id: %u\n", + frame->exp_id); + } + } + /* + * Only after enabled the raw buffer lock + * and in continuous mode. + * in preview/video pipe, each buffer will + * be locked automatically, so record it here. + */ + if (((css_pipe_id == IA_CSS_PIPE_ID_PREVIEW) || + (css_pipe_id == IA_CSS_PIPE_ID_VIDEO)) && + asd->enable_raw_buffer_lock->val && + asd->continuous_mode->val) { + atomisp_set_raw_buffer_bitmap(asd, frame->exp_id); + WARN_ON(frame->exp_id > ATOMISP_MAX_EXP_ID); + } + + if (asd->params.css_update_params_needed) { + atomisp_apply_css_parameters(asd, + &asd->params.css_param); + if (asd->params.css_param.update_flag.dz_config) + asd->params.config.dz_config = &asd->params.css_param.dz_config; + /* New global dvs 6axis config should be blocked + * here if there's a buffer with per-frame parameters + * pending in CSS frame buffer queue. + * This is to aviod zooming vibration since global + * parameters take effect immediately while + * per-frame parameters are taken after previous + * buffers in CSS got processed. + */ + if (asd->params.dvs_6axis) + atomisp_css_set_dvs_6axis(asd, + asd->params.dvs_6axis); + else + asd->params.css_update_params_needed = false; + /* The update flag should not be cleaned here + * since it is still going to be used to make up + * following per-frame parameters. + * This will introduce more copy work since each + * time when updating global parameters, the whole + * parameter set are applied. + * FIXME: A new set of parameter copy functions can + * be added to make up per-frame parameters based on + * solid structures stored in asd->params.css_param + * instead of using shadow pointers in update flag. + */ + atomisp_css_update_isp_params(asd); + } + break; + default: + break; + } + if (frame) { + spin_lock_irqsave(&pipe->irq_lock, irqflags); + atomisp_buffer_done(frame, error ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + } + + /* + * Requeue should only be done for 3a and dis buffers. + * Queue/dequeue order will change if driver recycles image buffers. + */ + if (requeue) { + err = atomisp_css_queue_buffer(asd, + stream_id, css_pipe_id, + buf_type, &buffer); + if (err) + dev_err(isp->dev, "%s, q to css fails: %d\n", + __func__, err); + return; + } + if (!error && q_buffers) + atomisp_qbuffers_to_css(asd); +} + +void atomisp_delayed_init_work(struct work_struct *work) +{ + struct atomisp_sub_device *asd = container_of(work, + struct atomisp_sub_device, + delayed_init_work); + /* + * to SOC camera, use yuvpp pipe and no support continuous mode. + */ + if (!ATOMISP_USE_YUVPP(asd)) { + struct v4l2_event event = {0}; + struct ia_css_stream *stream; + + stream = asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream; + + + if (ia_css_alloc_continuous_frame_remain(stream)) + return; + + ia_css_update_continuous_frames(stream); + + event.type = V4L2_EVENT_ATOMISP_RAW_BUFFERS_ALLOC_DONE; + v4l2_event_queue(asd->subdev.devnode, &event); + } + + /* signal streamon after delayed init is done */ + asd->delayed_init = ATOMISP_DELAYED_INIT_DONE; + complete(&asd->init_done); +} + +static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + enum ia_css_pipe_id css_pipe_id; + bool stream_restart[MAX_STREAM_NUM] = {0}; + bool depth_mode = false; + int i, ret, depth_cnt = 0; + unsigned long flags; + + lockdep_assert_held(&isp->mutex); + + if (!atomisp_streaming_count(isp)) + return; + + atomisp_css_irq_enable(isp, IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF, false); + + BUG_ON(isp->num_of_streams > MAX_STREAM_NUM); + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED && + !asd->stream_prepared) + continue; + + depth_cnt++; + + if (asd->delayed_init == ATOMISP_DELAYED_INIT_QUEUED) + cancel_work_sync(&asd->delayed_init_work); + + complete(&asd->init_done); + asd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED; + + stream_restart[asd->index] = true; + + spin_lock_irqsave(&isp->lock, flags); + asd->streaming = ATOMISP_DEVICE_STREAMING_STOPPING; + spin_unlock_irqrestore(&isp->lock, flags); + + /* stream off sensor */ + ret = v4l2_subdev_call( + isp->inputs[asd->input_curr]. + camera, video, s_stream, 0); + if (ret) + dev_warn(isp->dev, + "can't stop streaming on sensor!\n"); + + atomisp_clear_css_buffer_counters(asd); + + css_pipe_id = atomisp_get_css_pipe_id(asd); + atomisp_css_stop(asd, css_pipe_id, true); + + spin_lock_irqsave(&isp->lock, flags); + asd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED; + spin_unlock_irqrestore(&isp->lock, flags); + + asd->preview_exp_id = 1; + asd->postview_exp_id = 1; + /* notify HAL the CSS reset */ + dev_dbg(isp->dev, + "send reset event to %s\n", asd->subdev.devnode->name); + atomisp_reset_event(asd); + } + + /* clear irq */ + disable_isp_irq(hrt_isp_css_irq_sp); + clear_isp_irq(hrt_isp_css_irq_sp); + + /* Set the SRSE to 3 before resetting */ + pci_write_config_dword(pdev, PCI_I_CONTROL, + isp->saved_regs.i_control | MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK); + + /* reset ISP and restore its state */ + isp->isp_timeout = true; + atomisp_reset(isp); + isp->isp_timeout = false; + + if (!isp_timeout) { + for (i = 0; i < isp->num_of_streams; i++) { + if (isp->asd[i].depth_mode->val) + return; + } + } + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + if (!stream_restart[i]) + continue; + + if (isp->inputs[asd->input_curr].type != FILE_INPUT) + atomisp_css_input_set_mode(asd, + IA_CSS_INPUT_MODE_BUFFERED_SENSOR); + + css_pipe_id = atomisp_get_css_pipe_id(asd); + if (atomisp_css_start(asd, css_pipe_id, true)) { + dev_warn(isp->dev, + "start SP failed, so do not set streaming to be enable!\n"); + } else { + spin_lock_irqsave(&isp->lock, flags); + asd->streaming = ATOMISP_DEVICE_STREAMING_ENABLED; + spin_unlock_irqrestore(&isp->lock, flags); + } + + atomisp_csi2_configure(asd); + } + + atomisp_css_irq_enable(isp, IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF, + atomisp_css_valid_sof(isp)); + + if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_AUTO, true) < 0) + dev_dbg(isp->dev, "DFS auto failed while recovering!\n"); + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd; + + asd = &isp->asd[i]; + + if (!stream_restart[i]) + continue; + + if (asd->continuous_mode->val && + asd->delayed_init == ATOMISP_DELAYED_INIT_NOT_QUEUED) { + reinit_completion(&asd->init_done); + asd->delayed_init = ATOMISP_DELAYED_INIT_QUEUED; + queue_work(asd->delayed_init_workq, + &asd->delayed_init_work); + } + /* + * dequeueing buffers is not needed. CSS will recycle + * buffers that it has. + */ + atomisp_flush_bufs_and_wakeup(asd); + + /* Requeue unprocessed per-frame parameters. */ + atomisp_recover_params_queue(&asd->video_out_capture); + atomisp_recover_params_queue(&asd->video_out_preview); + atomisp_recover_params_queue(&asd->video_out_video_capture); + + if ((asd->depth_mode->val) && + (depth_cnt == ATOMISP_DEPTH_SENSOR_STREAMON_COUNT)) { + depth_mode = true; + continue; + } + + ret = v4l2_subdev_call( + isp->inputs[asd->input_curr].camera, video, + s_stream, 1); + if (ret) + dev_warn(isp->dev, + "can't start streaming on sensor!\n"); + } + + if (depth_mode) { + if (atomisp_stream_on_master_slave_sensor(isp, true)) + dev_warn(isp->dev, + "master slave sensor stream on failed!\n"); + } +} + +void atomisp_assert_recovery_work(struct work_struct *work) +{ + struct atomisp_device *isp = container_of(work, struct atomisp_device, + assert_recovery_work); + + mutex_lock(&isp->mutex); + __atomisp_css_recover(isp, true); + mutex_unlock(&isp->mutex); +} + +void atomisp_css_flush(struct atomisp_device *isp) +{ + /* Start recover */ + __atomisp_css_recover(isp, false); + + dev_dbg(isp->dev, "atomisp css flush done\n"); +} + +void atomisp_setup_flash(struct atomisp_sub_device *asd) +{ + struct atomisp_device *isp = asd->isp; + struct v4l2_control ctrl; + + if (!isp->flash) + return; + + if (asd->params.flash_state != ATOMISP_FLASH_REQUESTED && + asd->params.flash_state != ATOMISP_FLASH_DONE) + return; + + if (asd->params.num_flash_frames) { + /* make sure the timeout is set before setting flash mode */ + ctrl.id = V4L2_CID_FLASH_TIMEOUT; + ctrl.value = FLASH_TIMEOUT; + + if (v4l2_s_ctrl(NULL, isp->flash->ctrl_handler, &ctrl)) { + dev_err(isp->dev, "flash timeout configure failed\n"); + return; + } + + ia_css_stream_request_flash(asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream); + + asd->params.flash_state = ATOMISP_FLASH_ONGOING; + } else { + asd->params.flash_state = ATOMISP_FLASH_IDLE; + } +} + +irqreturn_t atomisp_isr_thread(int irq, void *isp_ptr) +{ + struct atomisp_device *isp = isp_ptr; + unsigned long flags; + bool frame_done_found[MAX_STREAM_NUM] = {0}; + bool css_pipe_done[MAX_STREAM_NUM] = {0}; + unsigned int i; + struct atomisp_sub_device *asd; + + dev_dbg(isp->dev, ">%s\n", __func__); + + spin_lock_irqsave(&isp->lock, flags); + + if (!atomisp_streaming_count(isp)) { + spin_unlock_irqrestore(&isp->lock, flags); + return IRQ_HANDLED; + } + + spin_unlock_irqrestore(&isp->lock, flags); + + /* + * The standard CSS2.0 API tells the following calling sequence of + * dequeue ready buffers: + * while (ia_css_dequeue_psys_event(...)) { + * switch (event.type) { + * ... + * ia_css_pipe_dequeue_buffer() + * } + * } + * That is, dequeue event and buffer are one after another. + * + * But the following implementation is to first deuque all the event + * to a FIFO, then process the event in the FIFO. + * This will not have issue in single stream mode, but it do have some + * issue in multiple stream case. The issue is that + * ia_css_pipe_dequeue_buffer() will not return the corrent buffer in + * a specific pipe. + * + * This is due to ia_css_pipe_dequeue_buffer() does not take the + * ia_css_pipe parameter. + * + * So: + * For CSS2.0: we change the way to not dequeue all the event at one + * time, instead, dequue one and process one, then another + */ + mutex_lock(&isp->mutex); + if (atomisp_css_isr_thread(isp, frame_done_found, css_pipe_done)) + goto out; + + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + continue; + atomisp_setup_flash(asd); + } +out: + mutex_unlock(&isp->mutex); + dev_dbg(isp->dev, "<%s\n", __func__); + + return IRQ_HANDLED; +} + +/* + * Get internal fmt according to V4L2 fmt + */ +static enum ia_css_frame_format +v4l2_fmt_to_sh_fmt(u32 fmt) +{ + switch (fmt) { + case V4L2_PIX_FMT_YUV420: + return IA_CSS_FRAME_FORMAT_YUV420; + case V4L2_PIX_FMT_YVU420: + return IA_CSS_FRAME_FORMAT_YV12; + case V4L2_PIX_FMT_YUV422P: + return IA_CSS_FRAME_FORMAT_YUV422; + case V4L2_PIX_FMT_YUV444: + return IA_CSS_FRAME_FORMAT_YUV444; + case V4L2_PIX_FMT_NV12: + return IA_CSS_FRAME_FORMAT_NV12; + case V4L2_PIX_FMT_NV21: + return IA_CSS_FRAME_FORMAT_NV21; + case V4L2_PIX_FMT_NV16: + return IA_CSS_FRAME_FORMAT_NV16; + case V4L2_PIX_FMT_NV61: + return IA_CSS_FRAME_FORMAT_NV61; + case V4L2_PIX_FMT_UYVY: + return IA_CSS_FRAME_FORMAT_UYVY; + case V4L2_PIX_FMT_YUYV: + return IA_CSS_FRAME_FORMAT_YUYV; + case V4L2_PIX_FMT_RGB24: + return IA_CSS_FRAME_FORMAT_PLANAR_RGB888; + case V4L2_PIX_FMT_RGB32: + return IA_CSS_FRAME_FORMAT_RGBA888; + case V4L2_PIX_FMT_RGB565: + return IA_CSS_FRAME_FORMAT_RGB565; +#if 0 + case V4L2_PIX_FMT_JPEG: + case V4L2_PIX_FMT_CUSTOM_M10MO_RAW: + return IA_CSS_FRAME_FORMAT_BINARY_8; +#endif + case V4L2_PIX_FMT_SBGGR16: + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + return IA_CSS_FRAME_FORMAT_RAW; + default: + return -EINVAL; + } +} + +/* + * raw format match between SH format and V4L2 format + */ +static int raw_output_format_match_input(u32 input, u32 output) +{ + if ((input == ATOMISP_INPUT_FORMAT_RAW_12) && + ((output == V4L2_PIX_FMT_SRGGB12) || + (output == V4L2_PIX_FMT_SGRBG12) || + (output == V4L2_PIX_FMT_SBGGR12) || + (output == V4L2_PIX_FMT_SGBRG12))) + return 0; + + if ((input == ATOMISP_INPUT_FORMAT_RAW_10) && + ((output == V4L2_PIX_FMT_SRGGB10) || + (output == V4L2_PIX_FMT_SGRBG10) || + (output == V4L2_PIX_FMT_SBGGR10) || + (output == V4L2_PIX_FMT_SGBRG10))) + return 0; + + if ((input == ATOMISP_INPUT_FORMAT_RAW_8) && + ((output == V4L2_PIX_FMT_SRGGB8) || + (output == V4L2_PIX_FMT_SGRBG8) || + (output == V4L2_PIX_FMT_SBGGR8) || + (output == V4L2_PIX_FMT_SGBRG8))) + return 0; + + if ((input == ATOMISP_INPUT_FORMAT_RAW_16) && (output == V4L2_PIX_FMT_SBGGR16)) + return 0; + + return -EINVAL; +} + +u32 atomisp_get_pixel_depth(u32 pixelformat) +{ + switch (pixelformat) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_YVU420: + return 12; + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_SBGGR16: + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + return 16; + case V4L2_PIX_FMT_RGB24: + case V4L2_PIX_FMT_YUV444: + return 24; + case V4L2_PIX_FMT_RGB32: + return 32; + case V4L2_PIX_FMT_JPEG: + case V4L2_PIX_FMT_CUSTOM_M10MO_RAW: + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + return 8; + default: + return 8 * 2; /* raw type now */ + } +} + +bool atomisp_is_mbuscode_raw(uint32_t code) +{ + return code >= 0x3000 && code < 0x4000; +} + +/* + * ISP features control function + */ + +/* + * Set ISP capture mode based on current settings + */ +static void atomisp_update_capture_mode(struct atomisp_sub_device *asd) +{ + if (asd->params.gdc_cac_en) + atomisp_css_capture_set_mode(asd, IA_CSS_CAPTURE_MODE_ADVANCED); + else if (asd->params.low_light) + atomisp_css_capture_set_mode(asd, IA_CSS_CAPTURE_MODE_LOW_LIGHT); + else if (asd->video_out_capture.sh_fmt == IA_CSS_FRAME_FORMAT_RAW) + atomisp_css_capture_set_mode(asd, IA_CSS_CAPTURE_MODE_RAW); + else + atomisp_css_capture_set_mode(asd, IA_CSS_CAPTURE_MODE_PRIMARY); +} + +/* ISP2401 */ +int atomisp_set_sensor_runmode(struct atomisp_sub_device *asd, + struct atomisp_s_runmode *runmode) +{ + struct atomisp_device *isp = asd->isp; + struct v4l2_ctrl *c; + int ret = 0; + + if (!(runmode && (runmode->mode & RUNMODE_MASK))) + return -EINVAL; + + mutex_lock(asd->ctrl_handler.lock); + c = v4l2_ctrl_find(isp->inputs[asd->input_curr].camera->ctrl_handler, + V4L2_CID_RUN_MODE); + + if (c) + ret = v4l2_ctrl_s_ctrl(c, runmode->mode); + + mutex_unlock(asd->ctrl_handler.lock); + return ret; +} + +/* + * Function to enable/disable lens geometry distortion correction (GDC) and + * chromatic aberration correction (CAC) + */ +int atomisp_gdc_cac(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + if (flag == 0) { + *value = asd->params.gdc_cac_en; + return 0; + } + + asd->params.gdc_cac_en = !!*value; + if (asd->params.gdc_cac_en) { + asd->params.config.morph_table = asd->params.css_param.morph_table; + } else { + asd->params.config.morph_table = NULL; + } + asd->params.css_update_params_needed = true; + atomisp_update_capture_mode(asd); + return 0; +} + +/* + * Function to enable/disable low light mode including ANR + */ +int atomisp_low_light(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + if (flag == 0) { + *value = asd->params.low_light; + return 0; + } + + asd->params.low_light = (*value != 0); + atomisp_update_capture_mode(asd); + return 0; +} + +/* + * Function to enable/disable extra noise reduction (XNR) in low light + * condition + */ +int atomisp_xnr(struct atomisp_sub_device *asd, int flag, + int *xnr_enable) +{ + if (flag == 0) { + *xnr_enable = asd->params.xnr_en; + return 0; + } + + atomisp_css_capture_enable_xnr(asd, !!*xnr_enable); + + return 0; +} + +/* + * Function to configure bayer noise reduction + */ +int atomisp_nr(struct atomisp_sub_device *asd, int flag, + struct atomisp_nr_config *arg) +{ + if (flag == 0) { + /* Get nr config from current setup */ + if (atomisp_css_get_nr_config(asd, arg)) + return -EINVAL; + } else { + /* Set nr config to isp parameters */ + memcpy(&asd->params.css_param.nr_config, arg, + sizeof(struct ia_css_nr_config)); + asd->params.config.nr_config = &asd->params.css_param.nr_config; + asd->params.css_update_params_needed = true; + } + return 0; +} + +/* + * Function to configure temporal noise reduction (TNR) + */ +int atomisp_tnr(struct atomisp_sub_device *asd, int flag, + struct atomisp_tnr_config *config) +{ + /* Get tnr config from current setup */ + if (flag == 0) { + /* Get tnr config from current setup */ + if (atomisp_css_get_tnr_config(asd, config)) + return -EINVAL; + } else { + /* Set tnr config to isp parameters */ + memcpy(&asd->params.css_param.tnr_config, config, + sizeof(struct ia_css_tnr_config)); + asd->params.config.tnr_config = &asd->params.css_param.tnr_config; + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to configure black level compensation + */ +int atomisp_black_level(struct atomisp_sub_device *asd, int flag, + struct atomisp_ob_config *config) +{ + if (flag == 0) { + /* Get ob config from current setup */ + if (atomisp_css_get_ob_config(asd, config)) + return -EINVAL; + } else { + /* Set ob config to isp parameters */ + memcpy(&asd->params.css_param.ob_config, config, + sizeof(struct ia_css_ob_config)); + asd->params.config.ob_config = &asd->params.css_param.ob_config; + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to configure edge enhancement + */ +int atomisp_ee(struct atomisp_sub_device *asd, int flag, + struct atomisp_ee_config *config) +{ + if (flag == 0) { + /* Get ee config from current setup */ + if (atomisp_css_get_ee_config(asd, config)) + return -EINVAL; + } else { + /* Set ee config to isp parameters */ + memcpy(&asd->params.css_param.ee_config, config, + sizeof(asd->params.css_param.ee_config)); + asd->params.config.ee_config = &asd->params.css_param.ee_config; + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to update Gamma table for gamma, brightness and contrast config + */ +int atomisp_gamma(struct atomisp_sub_device *asd, int flag, + struct atomisp_gamma_table *config) +{ + if (flag == 0) { + /* Get gamma table from current setup */ + if (atomisp_css_get_gamma_table(asd, config)) + return -EINVAL; + } else { + /* Set gamma table to isp parameters */ + memcpy(&asd->params.css_param.gamma_table, config, + sizeof(asd->params.css_param.gamma_table)); + asd->params.config.gamma_table = &asd->params.css_param.gamma_table; + } + + return 0; +} + +/* + * Function to update Ctc table for Chroma Enhancement + */ +int atomisp_ctc(struct atomisp_sub_device *asd, int flag, + struct atomisp_ctc_table *config) +{ + if (flag == 0) { + /* Get ctc table from current setup */ + if (atomisp_css_get_ctc_table(asd, config)) + return -EINVAL; + } else { + /* Set ctc table to isp parameters */ + memcpy(&asd->params.css_param.ctc_table, config, + sizeof(asd->params.css_param.ctc_table)); + atomisp_css_set_ctc_table(asd, &asd->params.css_param.ctc_table); + } + + return 0; +} + +/* + * Function to update gamma correction parameters + */ +int atomisp_gamma_correction(struct atomisp_sub_device *asd, int flag, + struct atomisp_gc_config *config) +{ + if (flag == 0) { + /* Get gamma correction params from current setup */ + if (atomisp_css_get_gc_config(asd, config)) + return -EINVAL; + } else { + /* Set gamma correction params to isp parameters */ + memcpy(&asd->params.css_param.gc_config, config, + sizeof(asd->params.css_param.gc_config)); + asd->params.config.gc_config = &asd->params.css_param.gc_config; + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to update narrow gamma flag + */ +int atomisp_formats(struct atomisp_sub_device *asd, int flag, + struct atomisp_formats_config *config) +{ + if (flag == 0) { + /* Get narrow gamma flag from current setup */ + if (atomisp_css_get_formats_config(asd, config)) + return -EINVAL; + } else { + /* Set narrow gamma flag to isp parameters */ + memcpy(&asd->params.css_param.formats_config, config, + sizeof(asd->params.css_param.formats_config)); + asd->params.config.formats_config = &asd->params.css_param.formats_config; + } + + return 0; +} + +void atomisp_free_internal_buffers(struct atomisp_sub_device *asd) +{ + atomisp_free_css_parameters(&asd->params.css_param); + + if (asd->raw_output_frame) { + ia_css_frame_free(asd->raw_output_frame); + asd->raw_output_frame = NULL; + } +} + +static void atomisp_update_grid_info(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id, + int source_pad) +{ + struct atomisp_device *isp = asd->isp; + int err; + + if (atomisp_css_get_grid_info(asd, pipe_id, source_pad)) + return; + + /* We must free all buffers because they no longer match + the grid size. */ + atomisp_css_free_stat_buffers(asd); + + err = atomisp_alloc_css_stat_bufs(asd, ATOMISP_INPUT_STREAM_GENERAL); + if (err) { + dev_err(isp->dev, "stat_buf allocate error\n"); + goto err; + } + + if (atomisp_alloc_3a_output_buf(asd)) { + /* Failure for 3A buffers does not influence DIS buffers */ + if (asd->params.s3a_output_bytes != 0) { + /* For SOC sensor happens s3a_output_bytes == 0, + * using if condition to exclude false error log */ + dev_err(isp->dev, "Failed to allocate memory for 3A statistics\n"); + } + goto err; + } + + if (atomisp_alloc_dis_coef_buf(asd)) { + dev_err(isp->dev, + "Failed to allocate memory for DIS statistics\n"); + goto err; + } + + if (atomisp_alloc_metadata_output_buf(asd)) { + dev_err(isp->dev, "Failed to allocate memory for metadata\n"); + goto err; + } + + return; + +err: + atomisp_css_free_stat_buffers(asd); + return; +} + +static void atomisp_curr_user_grid_info(struct atomisp_sub_device *asd, + struct atomisp_grid_info *info) +{ + memcpy(info, &asd->params.curr_grid_info.s3a_grid, + sizeof(struct ia_css_3a_grid_info)); +} + +int atomisp_compare_grid(struct atomisp_sub_device *asd, + struct atomisp_grid_info *atomgrid) +{ + struct atomisp_grid_info tmp = {0}; + + atomisp_curr_user_grid_info(asd, &tmp); + return memcmp(atomgrid, &tmp, sizeof(tmp)); +} + +/* + * Function to update Gdc table for gdc + */ +int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag, + struct atomisp_morph_table *config) +{ + int ret; + int i; + struct atomisp_device *isp = asd->isp; + + if (flag == 0) { + /* Get gdc table from current setup */ + struct ia_css_morph_table tab = {0}; + + atomisp_css_get_morph_table(asd, &tab); + + config->width = tab.width; + config->height = tab.height; + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + ret = copy_to_user(config->coordinates_x[i], + tab.coordinates_x[i], tab.height * + tab.width * sizeof(*tab.coordinates_x[i])); + if (ret) { + dev_err(isp->dev, + "Failed to copy to User for x\n"); + return -EFAULT; + } + ret = copy_to_user(config->coordinates_y[i], + tab.coordinates_y[i], tab.height * + tab.width * sizeof(*tab.coordinates_y[i])); + if (ret) { + dev_err(isp->dev, + "Failed to copy to User for y\n"); + return -EFAULT; + } + } + } else { + struct ia_css_morph_table *tab = + asd->params.css_param.morph_table; + + /* free first if we have one */ + if (tab) { + atomisp_css_morph_table_free(tab); + asd->params.css_param.morph_table = NULL; + } + + /* allocate new one */ + tab = atomisp_css_morph_table_allocate(config->width, + config->height); + + if (!tab) { + dev_err(isp->dev, "out of memory\n"); + return -EINVAL; + } + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + ret = copy_from_user(tab->coordinates_x[i], + config->coordinates_x[i], + config->height * config->width * + sizeof(*config->coordinates_x[i])); + if (ret) { + dev_err(isp->dev, + "Failed to copy from User for x, ret %d\n", + ret); + atomisp_css_morph_table_free(tab); + return -EFAULT; + } + ret = copy_from_user(tab->coordinates_y[i], + config->coordinates_y[i], + config->height * config->width * + sizeof(*config->coordinates_y[i])); + if (ret) { + dev_err(isp->dev, + "Failed to copy from User for y, ret is %d\n", + ret); + atomisp_css_morph_table_free(tab); + return -EFAULT; + } + } + asd->params.css_param.morph_table = tab; + if (asd->params.gdc_cac_en) + asd->params.config.morph_table = tab; + } + + return 0; +} + +int atomisp_macc_table(struct atomisp_sub_device *asd, int flag, + struct atomisp_macc_config *config) +{ + struct ia_css_macc_table *macc_table; + + switch (config->color_effect) { + case V4L2_COLORFX_NONE: + macc_table = &asd->params.css_param.macc_table; + break; + case V4L2_COLORFX_SKY_BLUE: + macc_table = &blue_macc_table; + break; + case V4L2_COLORFX_GRASS_GREEN: + macc_table = &green_macc_table; + break; + case V4L2_COLORFX_SKIN_WHITEN_LOW: + macc_table = &skin_low_macc_table; + break; + case V4L2_COLORFX_SKIN_WHITEN: + macc_table = &skin_medium_macc_table; + break; + case V4L2_COLORFX_SKIN_WHITEN_HIGH: + macc_table = &skin_high_macc_table; + break; + default: + return -EINVAL; + } + + if (flag == 0) { + /* Get macc table from current setup */ + memcpy(&config->table, macc_table, + sizeof(struct ia_css_macc_table)); + } else { + memcpy(macc_table, &config->table, + sizeof(struct ia_css_macc_table)); + if (config->color_effect == asd->params.color_effect) + asd->params.config.macc_table = macc_table; + } + + return 0; +} + +int atomisp_set_dis_vector(struct atomisp_sub_device *asd, + struct atomisp_dis_vector *vector) +{ + atomisp_css_video_set_dis_vector(asd, vector); + + asd->params.dis_proj_data_valid = false; + asd->params.css_update_params_needed = true; + return 0; +} + +/* + * Function to set/get image stablization statistics + */ +int atomisp_get_dis_stat(struct atomisp_sub_device *asd, + struct atomisp_dis_statistics *stats) +{ + return atomisp_css_get_dis_stat(asd, stats); +} + +/* + * Function set camrea_prefiles.xml current sensor pixel array size + */ +int atomisp_set_array_res(struct atomisp_sub_device *asd, + struct atomisp_resolution *config) +{ + dev_dbg(asd->isp->dev, ">%s start\n", __func__); + if (!config) { + dev_err(asd->isp->dev, "Set sensor array size is not valid\n"); + return -EINVAL; + } + + asd->sensor_array_res.width = config->width; + asd->sensor_array_res.height = config->height; + return 0; +} + +/* + * Function to get DVS2 BQ resolution settings + */ +int atomisp_get_dvs2_bq_resolutions(struct atomisp_sub_device *asd, + struct atomisp_dvs2_bq_resolutions *bq_res) +{ + struct ia_css_pipe_config *pipe_cfg = NULL; + struct ia_css_stream_config *stream_cfg = NULL; + struct ia_css_stream_input_config *input_config = NULL; + + struct ia_css_stream *stream = + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream; + if (!stream) { + dev_warn(asd->isp->dev, "stream is not created"); + return -EAGAIN; + } + + pipe_cfg = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[IA_CSS_PIPE_ID_VIDEO]; + stream_cfg = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config; + input_config = &stream_cfg->input_config; + + if (!bq_res) + return -EINVAL; + + /* the GDC output resolution */ + bq_res->output_bq.width_bq = pipe_cfg->output_info[0].res.width / 2; + bq_res->output_bq.height_bq = pipe_cfg->output_info[0].res.height / 2; + + bq_res->envelope_bq.width_bq = 0; + bq_res->envelope_bq.height_bq = 0; + /* the GDC input resolution */ + if (!asd->continuous_mode->val) { + bq_res->source_bq.width_bq = bq_res->output_bq.width_bq + + pipe_cfg->dvs_envelope.width / 2; + bq_res->source_bq.height_bq = bq_res->output_bq.height_bq + + pipe_cfg->dvs_envelope.height / 2; + /* + * Bad pixels caused by spatial filter processing + * ISP filter resolution should be given by CSS/FW, but for now + * there is not such API to query, and it is fixed value, so + * hardcoded here. + */ + bq_res->ispfilter_bq.width_bq = 12 / 2; + bq_res->ispfilter_bq.height_bq = 12 / 2; + /* spatial filter shift, always 4 pixels */ + bq_res->gdc_shift_bq.width_bq = 4 / 2; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + + if (asd->params.video_dis_en) { + bq_res->envelope_bq.width_bq = pipe_cfg->dvs_envelope.width + / 2 - bq_res->ispfilter_bq.width_bq; + bq_res->envelope_bq.height_bq = pipe_cfg->dvs_envelope.height + / 2 - bq_res->ispfilter_bq.height_bq; + } + } else { + unsigned int w_padding; + unsigned int gdc_effective_input = 0; + + /* For GDC: + * gdc_effective_input = effective_input + envelope + * + * From the comment and formula in BZ1786, + * we see the source_bq should be: + * effective_input / bayer_ds_ratio + */ + bq_res->source_bq.width_bq = + (input_config->effective_res.width * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width + 1) / 2; + bq_res->source_bq.height_bq = + (input_config->effective_res.height * + pipe_cfg->bayer_ds_out_res.height / + input_config->effective_res.height + 1) / 2; + + if (!asd->params.video_dis_en) { + /* + * We adjust the ispfilter_bq to: + * ispfilter_bq = 128/BDS + * we still need firmware team to provide an offical + * formula for SDV. + */ + bq_res->ispfilter_bq.width_bq = 128 * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width / 2; + bq_res->ispfilter_bq.height_bq = 128 * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width / 2; + + if (IS_HWREVISION(asd->isp, ATOMISP_HW_REVISION_ISP2401)) { + /* No additional left padding for ISYS2401 */ + bq_res->gdc_shift_bq.width_bq = 4 / 2; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + } else { + /* + * For the w_padding and gdc_shift_bq cacluation + * Please see the BZ 1786 and 4358 for more info. + * Just test that this formula can work now, + * but we still have no offical formula. + * + * w_padding = ceiling(gdc_effective_input + * /128, 1) * 128 - effective_width + * gdc_shift_bq = w_padding/BDS/2 + ispfilter_bq/2 + */ + gdc_effective_input = + input_config->effective_res.width + + pipe_cfg->dvs_envelope.width; + w_padding = roundup(gdc_effective_input, 128) - + input_config->effective_res.width; + w_padding = w_padding * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width + 1; + w_padding = roundup(w_padding / 2, 1); + + bq_res->gdc_shift_bq.width_bq = bq_res->ispfilter_bq.width_bq / 2 + + w_padding; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + } + } else { + unsigned int dvs_w, dvs_h, dvs_w_max, dvs_h_max; + + bq_res->ispfilter_bq.width_bq = 8 / 2; + bq_res->ispfilter_bq.height_bq = 8 / 2; + + if (IS_HWREVISION(asd->isp, ATOMISP_HW_REVISION_ISP2401)) { + /* No additional left padding for ISYS2401 */ + bq_res->gdc_shift_bq.width_bq = 4 / 2; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + } else { + w_padding = + roundup(input_config->effective_res.width, 128) - + input_config->effective_res.width; + if (w_padding < 12) + w_padding = 12; + bq_res->gdc_shift_bq.width_bq = 4 / 2 + + ((w_padding - 12) * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width + 1) / 2; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + } + + dvs_w = pipe_cfg->bayer_ds_out_res.width - + pipe_cfg->output_info[0].res.width; + dvs_h = pipe_cfg->bayer_ds_out_res.height - + pipe_cfg->output_info[0].res.height; + dvs_w_max = rounddown( + pipe_cfg->output_info[0].res.width / 5, + ATOM_ISP_STEP_WIDTH); + dvs_h_max = rounddown( + pipe_cfg->output_info[0].res.height / 5, + ATOM_ISP_STEP_HEIGHT); + bq_res->envelope_bq.width_bq = + min((dvs_w / 2), (dvs_w_max / 2)) - + bq_res->ispfilter_bq.width_bq; + bq_res->envelope_bq.height_bq = + min((dvs_h / 2), (dvs_h_max / 2)) - + bq_res->ispfilter_bq.height_bq; + } + } + + dev_dbg(asd->isp->dev, + "source_bq.width_bq %d, source_bq.height_bq %d,\nispfilter_bq.width_bq %d, ispfilter_bq.height_bq %d,\ngdc_shift_bq.width_bq %d, gdc_shift_bq.height_bq %d,\nenvelope_bq.width_bq %d, envelope_bq.height_bq %d,\noutput_bq.width_bq %d, output_bq.height_bq %d\n", + bq_res->source_bq.width_bq, bq_res->source_bq.height_bq, + bq_res->ispfilter_bq.width_bq, bq_res->ispfilter_bq.height_bq, + bq_res->gdc_shift_bq.width_bq, bq_res->gdc_shift_bq.height_bq, + bq_res->envelope_bq.width_bq, bq_res->envelope_bq.height_bq, + bq_res->output_bq.width_bq, bq_res->output_bq.height_bq); + + return 0; +} + +int atomisp_set_dis_coefs(struct atomisp_sub_device *asd, + struct atomisp_dis_coefficients *coefs) +{ + return atomisp_css_set_dis_coefs(asd, coefs); +} + +/* + * Function to set/get 3A stat from isp + */ +int atomisp_3a_stat(struct atomisp_sub_device *asd, int flag, + struct atomisp_3a_statistics *config) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_s3a_buf *s3a_buf; + unsigned long ret; + + if (flag != 0) + return -EINVAL; + + /* sanity check to avoid writing into unallocated memory. */ + if (asd->params.s3a_output_bytes == 0) + return -EINVAL; + + if (atomisp_compare_grid(asd, &config->grid_info) != 0) { + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + } + + if (list_empty(&asd->s3a_stats_ready)) { + dev_err(isp->dev, "3a statistics is not valid.\n"); + return -EAGAIN; + } + + s3a_buf = list_entry(asd->s3a_stats_ready.next, + struct atomisp_s3a_buf, list); + if (s3a_buf->s3a_map) + ia_css_translate_3a_statistics( + asd->params.s3a_user_stat, s3a_buf->s3a_map); + else + ia_css_get_3a_statistics(asd->params.s3a_user_stat, + s3a_buf->s3a_data); + + config->exp_id = s3a_buf->s3a_data->exp_id; + config->isp_config_id = s3a_buf->s3a_data->isp_config_id; + + ret = copy_to_user(config->data, asd->params.s3a_user_stat->data, + asd->params.s3a_output_bytes); + if (ret) { + dev_err(isp->dev, "copy to user failed: copied %lu bytes\n", + ret); + return -EFAULT; + } + + /* Move to free buffer list */ + list_del_init(&s3a_buf->list); + list_add_tail(&s3a_buf->list, &asd->s3a_stats); + dev_dbg(isp->dev, "%s: finish getting exp_id %d 3a stat, isp_config_id %d\n", + __func__, + config->exp_id, config->isp_config_id); + return 0; +} + +int atomisp_get_metadata(struct atomisp_sub_device *asd, int flag, + struct atomisp_metadata *md) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_stream_info *stream_info; + struct camera_mipi_info *mipi_info; + struct atomisp_metadata_buf *md_buf; + enum atomisp_metadata_type md_type = ATOMISP_MAIN_METADATA; + int ret, i; + + if (flag != 0) + return -EINVAL; + + stream_info = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_info; + + /* We always return the resolution and stride even if there is + * no valid metadata. This allows the caller to get the information + * needed to allocate user-space buffers. */ + md->width = stream_info->metadata_info.resolution.width; + md->height = stream_info->metadata_info.resolution.height; + md->stride = stream_info->metadata_info.stride; + + /* sanity check to avoid writing into unallocated memory. + * This does not return an error because it is a valid way + * for applications to detect that metadata is not enabled. */ + if (md->width == 0 || md->height == 0 || !md->data) + return 0; + + /* This is done in the atomisp_buf_done() */ + if (list_empty(&asd->metadata_ready[md_type])) { + dev_warn(isp->dev, "Metadata queue is empty now!\n"); + return -EAGAIN; + } + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (!mipi_info) + return -EINVAL; + + if (mipi_info->metadata_effective_width) { + for (i = 0; i < md->height; i++) + md->effective_width[i] = + mipi_info->metadata_effective_width[i]; + } + + md_buf = list_entry(asd->metadata_ready[md_type].next, + struct atomisp_metadata_buf, list); + md->exp_id = md_buf->metadata->exp_id; + if (md_buf->md_vptr) { + ret = copy_to_user(md->data, + md_buf->md_vptr, + stream_info->metadata_info.size); + } else { + hmm_load(md_buf->metadata->address, + asd->params.metadata_user[md_type], + stream_info->metadata_info.size); + + ret = copy_to_user(md->data, + asd->params.metadata_user[md_type], + stream_info->metadata_info.size); + } + if (ret) { + dev_err(isp->dev, "copy to user failed: copied %d bytes\n", + ret); + return -EFAULT; + } + + list_del_init(&md_buf->list); + list_add_tail(&md_buf->list, &asd->metadata[md_type]); + + dev_dbg(isp->dev, "%s: HAL de-queued metadata type %d with exp_id %d\n", + __func__, md_type, md->exp_id); + return 0; +} + +int atomisp_get_metadata_by_type(struct atomisp_sub_device *asd, int flag, + struct atomisp_metadata_with_type *md) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_stream_info *stream_info; + struct camera_mipi_info *mipi_info; + struct atomisp_metadata_buf *md_buf; + enum atomisp_metadata_type md_type; + int ret, i; + + if (flag != 0) + return -EINVAL; + + stream_info = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_info; + + /* We always return the resolution and stride even if there is + * no valid metadata. This allows the caller to get the information + * needed to allocate user-space buffers. */ + md->width = stream_info->metadata_info.resolution.width; + md->height = stream_info->metadata_info.resolution.height; + md->stride = stream_info->metadata_info.stride; + + /* sanity check to avoid writing into unallocated memory. + * This does not return an error because it is a valid way + * for applications to detect that metadata is not enabled. */ + if (md->width == 0 || md->height == 0 || !md->data) + return 0; + + md_type = md->type; + if (md_type < 0 || md_type >= ATOMISP_METADATA_TYPE_NUM) + return -EINVAL; + + /* This is done in the atomisp_buf_done() */ + if (list_empty(&asd->metadata_ready[md_type])) { + dev_warn(isp->dev, "Metadata queue is empty now!\n"); + return -EAGAIN; + } + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (!mipi_info) + return -EINVAL; + + if (mipi_info->metadata_effective_width) { + for (i = 0; i < md->height; i++) + md->effective_width[i] = + mipi_info->metadata_effective_width[i]; + } + + md_buf = list_entry(asd->metadata_ready[md_type].next, + struct atomisp_metadata_buf, list); + md->exp_id = md_buf->metadata->exp_id; + if (md_buf->md_vptr) { + ret = copy_to_user(md->data, + md_buf->md_vptr, + stream_info->metadata_info.size); + } else { + hmm_load(md_buf->metadata->address, + asd->params.metadata_user[md_type], + stream_info->metadata_info.size); + + ret = copy_to_user(md->data, + asd->params.metadata_user[md_type], + stream_info->metadata_info.size); + } + if (ret) { + dev_err(isp->dev, "copy to user failed: copied %d bytes\n", + ret); + return -EFAULT; + } else { + list_del_init(&md_buf->list); + list_add_tail(&md_buf->list, &asd->metadata[md_type]); + } + dev_dbg(isp->dev, "%s: HAL de-queued metadata type %d with exp_id %d\n", + __func__, md_type, md->exp_id); + return 0; +} + +/* + * Function to calculate real zoom region for every pipe + */ +int atomisp_calculate_real_zoom_region(struct atomisp_sub_device *asd, + struct ia_css_dz_config *dz_config, + enum ia_css_pipe_id css_pipe_id) + +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct atomisp_resolution eff_res, out_res; + int w_offset, h_offset; + + memset(&eff_res, 0, sizeof(eff_res)); + memset(&out_res, 0, sizeof(out_res)); + + if (dz_config->dx || dz_config->dy) + return 0; + + if (css_pipe_id != IA_CSS_PIPE_ID_PREVIEW + && css_pipe_id != IA_CSS_PIPE_ID_CAPTURE) { + dev_err(asd->isp->dev, "%s the set pipe no support crop region" + , __func__); + return -EINVAL; + } + + eff_res.width = + stream_env->stream_config.input_config.effective_res.width; + eff_res.height = + stream_env->stream_config.input_config.effective_res.height; + if (eff_res.width == 0 || eff_res.height == 0) { + dev_err(asd->isp->dev, "%s err effective resolution" + , __func__); + return -EINVAL; + } + + if (dz_config->zoom_region.resolution.width + == asd->sensor_array_res.width + || dz_config->zoom_region.resolution.height + == asd->sensor_array_res.height) { + /*no need crop region*/ + dz_config->zoom_region.origin.x = 0; + dz_config->zoom_region.origin.y = 0; + dz_config->zoom_region.resolution.width = eff_res.width; + dz_config->zoom_region.resolution.height = eff_res.height; + return 0; + } + + /* FIXME: + * This is not the correct implementation with Google's definition, due + * to firmware limitation. + * map real crop region base on above calculating base max crop region. + */ + + if (!IS_ISP2401) { + dz_config->zoom_region.origin.x = dz_config->zoom_region.origin.x + * eff_res.width + / asd->sensor_array_res.width; + dz_config->zoom_region.origin.y = dz_config->zoom_region.origin.y + * eff_res.height + / asd->sensor_array_res.height; + dz_config->zoom_region.resolution.width = dz_config->zoom_region.resolution.width + * eff_res.width + / asd->sensor_array_res.width; + dz_config->zoom_region.resolution.height = dz_config->zoom_region.resolution.height + * eff_res.height + / asd->sensor_array_res.height; + /* + * Set same ratio of crop region resolution and current pipe output + * resolution + */ + out_res.width = stream_env->pipe_configs[css_pipe_id].output_info[0].res.width; + out_res.height = stream_env->pipe_configs[css_pipe_id].output_info[0].res.height; + if (out_res.width == 0 || out_res.height == 0) { + dev_err(asd->isp->dev, "%s err current pipe output resolution" + , __func__); + return -EINVAL; + } + } else { + out_res.width = stream_env->pipe_configs[css_pipe_id].output_info[0].res.width; + out_res.height = stream_env->pipe_configs[css_pipe_id].output_info[0].res.height; + if (out_res.width == 0 || out_res.height == 0) { + dev_err(asd->isp->dev, "%s err current pipe output resolution" + , __func__); + return -EINVAL; + } + + if (asd->sensor_array_res.width * out_res.height + < out_res.width * asd->sensor_array_res.height) { + h_offset = asd->sensor_array_res.height + - asd->sensor_array_res.width + * out_res.height / out_res.width; + h_offset = h_offset / 2; + if (dz_config->zoom_region.origin.y < h_offset) + dz_config->zoom_region.origin.y = 0; + else + dz_config->zoom_region.origin.y = dz_config->zoom_region.origin.y - h_offset; + w_offset = 0; + } else { + w_offset = asd->sensor_array_res.width + - asd->sensor_array_res.height + * out_res.width / out_res.height; + w_offset = w_offset / 2; + if (dz_config->zoom_region.origin.x < w_offset) + dz_config->zoom_region.origin.x = 0; + else + dz_config->zoom_region.origin.x = dz_config->zoom_region.origin.x - w_offset; + h_offset = 0; + } + dz_config->zoom_region.origin.x = dz_config->zoom_region.origin.x + * eff_res.width + / (asd->sensor_array_res.width - 2 * w_offset); + dz_config->zoom_region.origin.y = dz_config->zoom_region.origin.y + * eff_res.height + / (asd->sensor_array_res.height - 2 * h_offset); + dz_config->zoom_region.resolution.width = dz_config->zoom_region.resolution.width + * eff_res.width + / (asd->sensor_array_res.width - 2 * w_offset); + dz_config->zoom_region.resolution.height = dz_config->zoom_region.resolution.height + * eff_res.height + / (asd->sensor_array_res.height - 2 * h_offset); + } + + if (out_res.width * dz_config->zoom_region.resolution.height + > dz_config->zoom_region.resolution.width * out_res.height) { + dz_config->zoom_region.resolution.height = + dz_config->zoom_region.resolution.width + * out_res.height / out_res.width; + } else { + dz_config->zoom_region.resolution.width = + dz_config->zoom_region.resolution.height + * out_res.width / out_res.height; + } + dev_dbg(asd->isp->dev, + "%s crop region:(%d,%d),(%d,%d) eff_res(%d, %d) array_size(%d,%d) out_res(%d, %d)\n", + __func__, dz_config->zoom_region.origin.x, + dz_config->zoom_region.origin.y, + dz_config->zoom_region.resolution.width, + dz_config->zoom_region.resolution.height, + eff_res.width, eff_res.height, + asd->sensor_array_res.width, + asd->sensor_array_res.height, + out_res.width, out_res.height); + + if ((dz_config->zoom_region.origin.x + + dz_config->zoom_region.resolution.width + > eff_res.width) || + (dz_config->zoom_region.origin.y + + dz_config->zoom_region.resolution.height + > eff_res.height)) + return -EINVAL; + + return 0; +} + +/* + * Function to check the zoom region whether is effective + */ +static bool atomisp_check_zoom_region( + struct atomisp_sub_device *asd, + struct ia_css_dz_config *dz_config) +{ + struct atomisp_resolution config; + bool flag = false; + unsigned int w, h; + + memset(&config, 0, sizeof(struct atomisp_resolution)); + + if (dz_config->dx && dz_config->dy) + return true; + + config.width = asd->sensor_array_res.width; + config.height = asd->sensor_array_res.height; + w = dz_config->zoom_region.origin.x + + dz_config->zoom_region.resolution.width; + h = dz_config->zoom_region.origin.y + + dz_config->zoom_region.resolution.height; + + if ((w <= config.width) && (h <= config.height) && w > 0 && h > 0) + flag = true; + else + /* setting error zoom region */ + dev_err(asd->isp->dev, + "%s zoom region ERROR:dz_config:(%d,%d),(%d,%d)array_res(%d, %d)\n", + __func__, dz_config->zoom_region.origin.x, + dz_config->zoom_region.origin.y, + dz_config->zoom_region.resolution.width, + dz_config->zoom_region.resolution.height, + config.width, config.height); + + return flag; +} + +void atomisp_apply_css_parameters( + struct atomisp_sub_device *asd, + struct atomisp_css_params *css_param) +{ + if (css_param->update_flag.wb_config) + asd->params.config.wb_config = &css_param->wb_config; + + if (css_param->update_flag.ob_config) + asd->params.config.ob_config = &css_param->ob_config; + + if (css_param->update_flag.dp_config) + asd->params.config.dp_config = &css_param->dp_config; + + if (css_param->update_flag.nr_config) + asd->params.config.nr_config = &css_param->nr_config; + + if (css_param->update_flag.ee_config) + asd->params.config.ee_config = &css_param->ee_config; + + if (css_param->update_flag.tnr_config) + asd->params.config.tnr_config = &css_param->tnr_config; + + if (css_param->update_flag.a3a_config) + asd->params.config.s3a_config = &css_param->s3a_config; + + if (css_param->update_flag.ctc_config) + asd->params.config.ctc_config = &css_param->ctc_config; + + if (css_param->update_flag.cnr_config) + asd->params.config.cnr_config = &css_param->cnr_config; + + if (css_param->update_flag.ecd_config) + asd->params.config.ecd_config = &css_param->ecd_config; + + if (css_param->update_flag.ynr_config) + asd->params.config.ynr_config = &css_param->ynr_config; + + if (css_param->update_flag.fc_config) + asd->params.config.fc_config = &css_param->fc_config; + + if (css_param->update_flag.macc_config) + asd->params.config.macc_config = &css_param->macc_config; + + if (css_param->update_flag.aa_config) + asd->params.config.aa_config = &css_param->aa_config; + + if (css_param->update_flag.anr_config) + asd->params.config.anr_config = &css_param->anr_config; + + if (css_param->update_flag.xnr_config) + asd->params.config.xnr_config = &css_param->xnr_config; + + if (css_param->update_flag.yuv2rgb_cc_config) + asd->params.config.yuv2rgb_cc_config = &css_param->yuv2rgb_cc_config; + + if (css_param->update_flag.rgb2yuv_cc_config) + asd->params.config.rgb2yuv_cc_config = &css_param->rgb2yuv_cc_config; + + if (css_param->update_flag.macc_table) + asd->params.config.macc_table = &css_param->macc_table; + + if (css_param->update_flag.xnr_table) + asd->params.config.xnr_table = &css_param->xnr_table; + + if (css_param->update_flag.r_gamma_table) + asd->params.config.r_gamma_table = &css_param->r_gamma_table; + + if (css_param->update_flag.g_gamma_table) + asd->params.config.g_gamma_table = &css_param->g_gamma_table; + + if (css_param->update_flag.b_gamma_table) + asd->params.config.b_gamma_table = &css_param->b_gamma_table; + + if (css_param->update_flag.anr_thres) + atomisp_css_set_anr_thres(asd, &css_param->anr_thres); + + if (css_param->update_flag.shading_table) + asd->params.config.shading_table = css_param->shading_table; + + if (css_param->update_flag.morph_table && asd->params.gdc_cac_en) + asd->params.config.morph_table = css_param->morph_table; + + if (css_param->update_flag.dvs2_coefs) { + struct ia_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info( + &asd->params.curr_grid_info); + + if (dvs_grid_info && dvs_grid_info->enable) + atomisp_css_set_dvs2_coefs(asd, css_param->dvs2_coeff); + } + + if (css_param->update_flag.dvs_6axis_config) + atomisp_css_set_dvs_6axis(asd, css_param->dvs_6axis); + + atomisp_css_set_isp_config_id(asd, css_param->isp_config_id); + /* + * These configurations are on used by ISP1.x, not for ISP2.x, + * so do not handle them. see comments of ia_css_isp_config. + * 1 cc_config + * 2 ce_config + * 3 de_config + * 4 gc_config + * 5 gamma_table + * 6 ctc_table + * 7 dvs_coefs + */ +} + +static unsigned int long copy_from_compatible(void *to, const void *from, + unsigned long n, bool from_user) +{ + if (from_user) + return copy_from_user(to, (void __user *)from, n); + else + memcpy(to, from, n); + return 0; +} + +int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd, + struct atomisp_parameters *arg, + struct atomisp_css_params *css_param, + bool from_user) +{ + struct atomisp_parameters *cur_config = &css_param->update_flag; + + if (!arg || !asd || !css_param) + return -EINVAL; + + if (arg->wb_config && (from_user || !cur_config->wb_config)) { + if (copy_from_compatible(&css_param->wb_config, arg->wb_config, + sizeof(struct ia_css_wb_config), + from_user)) + return -EFAULT; + css_param->update_flag.wb_config = + (struct atomisp_wb_config *)&css_param->wb_config; + } + + if (arg->ob_config && (from_user || !cur_config->ob_config)) { + if (copy_from_compatible(&css_param->ob_config, arg->ob_config, + sizeof(struct ia_css_ob_config), + from_user)) + return -EFAULT; + css_param->update_flag.ob_config = + (struct atomisp_ob_config *)&css_param->ob_config; + } + + if (arg->dp_config && (from_user || !cur_config->dp_config)) { + if (copy_from_compatible(&css_param->dp_config, arg->dp_config, + sizeof(struct ia_css_dp_config), + from_user)) + return -EFAULT; + css_param->update_flag.dp_config = + (struct atomisp_dp_config *)&css_param->dp_config; + } + + if (asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO) { + if (arg->dz_config && (from_user || !cur_config->dz_config)) { + if (copy_from_compatible(&css_param->dz_config, + arg->dz_config, + sizeof(struct ia_css_dz_config), + from_user)) + return -EFAULT; + if (!atomisp_check_zoom_region(asd, + &css_param->dz_config)) { + dev_err(asd->isp->dev, "crop region error!"); + return -EINVAL; + } + css_param->update_flag.dz_config = + (struct atomisp_dz_config *) + &css_param->dz_config; + } + } + + if (arg->nr_config && (from_user || !cur_config->nr_config)) { + if (copy_from_compatible(&css_param->nr_config, arg->nr_config, + sizeof(struct ia_css_nr_config), + from_user)) + return -EFAULT; + css_param->update_flag.nr_config = + (struct atomisp_nr_config *)&css_param->nr_config; + } + + if (arg->ee_config && (from_user || !cur_config->ee_config)) { + if (copy_from_compatible(&css_param->ee_config, arg->ee_config, + sizeof(struct ia_css_ee_config), + from_user)) + return -EFAULT; + css_param->update_flag.ee_config = + (struct atomisp_ee_config *)&css_param->ee_config; + } + + if (arg->tnr_config && (from_user || !cur_config->tnr_config)) { + if (copy_from_compatible(&css_param->tnr_config, + arg->tnr_config, + sizeof(struct ia_css_tnr_config), + from_user)) + return -EFAULT; + css_param->update_flag.tnr_config = + (struct atomisp_tnr_config *) + &css_param->tnr_config; + } + + if (arg->a3a_config && (from_user || !cur_config->a3a_config)) { + if (copy_from_compatible(&css_param->s3a_config, + arg->a3a_config, + sizeof(struct ia_css_3a_config), + from_user)) + return -EFAULT; + css_param->update_flag.a3a_config = + (struct atomisp_3a_config *)&css_param->s3a_config; + } + + if (arg->ctc_config && (from_user || !cur_config->ctc_config)) { + if (copy_from_compatible(&css_param->ctc_config, + arg->ctc_config, + sizeof(struct ia_css_ctc_config), + from_user)) + return -EFAULT; + css_param->update_flag.ctc_config = + (struct atomisp_ctc_config *) + &css_param->ctc_config; + } + + if (arg->cnr_config && (from_user || !cur_config->cnr_config)) { + if (copy_from_compatible(&css_param->cnr_config, + arg->cnr_config, + sizeof(struct ia_css_cnr_config), + from_user)) + return -EFAULT; + css_param->update_flag.cnr_config = + (struct atomisp_cnr_config *) + &css_param->cnr_config; + } + + if (arg->ecd_config && (from_user || !cur_config->ecd_config)) { + if (copy_from_compatible(&css_param->ecd_config, + arg->ecd_config, + sizeof(struct ia_css_ecd_config), + from_user)) + return -EFAULT; + css_param->update_flag.ecd_config = + (struct atomisp_ecd_config *) + &css_param->ecd_config; + } + + if (arg->ynr_config && (from_user || !cur_config->ynr_config)) { + if (copy_from_compatible(&css_param->ynr_config, + arg->ynr_config, + sizeof(struct ia_css_ynr_config), + from_user)) + return -EFAULT; + css_param->update_flag.ynr_config = + (struct atomisp_ynr_config *) + &css_param->ynr_config; + } + + if (arg->fc_config && (from_user || !cur_config->fc_config)) { + if (copy_from_compatible(&css_param->fc_config, + arg->fc_config, + sizeof(struct ia_css_fc_config), + from_user)) + return -EFAULT; + css_param->update_flag.fc_config = + (struct atomisp_fc_config *)&css_param->fc_config; + } + + if (arg->macc_config && (from_user || !cur_config->macc_config)) { + if (copy_from_compatible(&css_param->macc_config, + arg->macc_config, + sizeof(struct ia_css_macc_config), + from_user)) + return -EFAULT; + css_param->update_flag.macc_config = + (struct atomisp_macc_config *) + &css_param->macc_config; + } + + if (arg->aa_config && (from_user || !cur_config->aa_config)) { + if (copy_from_compatible(&css_param->aa_config, arg->aa_config, + sizeof(struct ia_css_aa_config), + from_user)) + return -EFAULT; + css_param->update_flag.aa_config = + (struct atomisp_aa_config *)&css_param->aa_config; + } + + if (arg->anr_config && (from_user || !cur_config->anr_config)) { + if (copy_from_compatible(&css_param->anr_config, + arg->anr_config, + sizeof(struct ia_css_anr_config), + from_user)) + return -EFAULT; + css_param->update_flag.anr_config = + (struct atomisp_anr_config *) + &css_param->anr_config; + } + + if (arg->xnr_config && (from_user || !cur_config->xnr_config)) { + if (copy_from_compatible(&css_param->xnr_config, + arg->xnr_config, + sizeof(struct ia_css_xnr_config), + from_user)) + return -EFAULT; + css_param->update_flag.xnr_config = + (struct atomisp_xnr_config *) + &css_param->xnr_config; + } + + if (arg->yuv2rgb_cc_config && + (from_user || !cur_config->yuv2rgb_cc_config)) { + if (copy_from_compatible(&css_param->yuv2rgb_cc_config, + arg->yuv2rgb_cc_config, + sizeof(struct ia_css_cc_config), + from_user)) + return -EFAULT; + css_param->update_flag.yuv2rgb_cc_config = + (struct atomisp_cc_config *) + &css_param->yuv2rgb_cc_config; + } + + if (arg->rgb2yuv_cc_config && + (from_user || !cur_config->rgb2yuv_cc_config)) { + if (copy_from_compatible(&css_param->rgb2yuv_cc_config, + arg->rgb2yuv_cc_config, + sizeof(struct ia_css_cc_config), + from_user)) + return -EFAULT; + css_param->update_flag.rgb2yuv_cc_config = + (struct atomisp_cc_config *) + &css_param->rgb2yuv_cc_config; + } + + if (arg->macc_table && (from_user || !cur_config->macc_table)) { + if (copy_from_compatible(&css_param->macc_table, + arg->macc_table, + sizeof(struct ia_css_macc_table), + from_user)) + return -EFAULT; + css_param->update_flag.macc_table = + (struct atomisp_macc_table *) + &css_param->macc_table; + } + + if (arg->xnr_table && (from_user || !cur_config->xnr_table)) { + if (copy_from_compatible(&css_param->xnr_table, + arg->xnr_table, + sizeof(struct ia_css_xnr_table), + from_user)) + return -EFAULT; + css_param->update_flag.xnr_table = + (struct atomisp_xnr_table *)&css_param->xnr_table; + } + + if (arg->r_gamma_table && (from_user || !cur_config->r_gamma_table)) { + if (copy_from_compatible(&css_param->r_gamma_table, + arg->r_gamma_table, + sizeof(struct ia_css_rgb_gamma_table), + from_user)) + return -EFAULT; + css_param->update_flag.r_gamma_table = + (struct atomisp_rgb_gamma_table *) + &css_param->r_gamma_table; + } + + if (arg->g_gamma_table && (from_user || !cur_config->g_gamma_table)) { + if (copy_from_compatible(&css_param->g_gamma_table, + arg->g_gamma_table, + sizeof(struct ia_css_rgb_gamma_table), + from_user)) + return -EFAULT; + css_param->update_flag.g_gamma_table = + (struct atomisp_rgb_gamma_table *) + &css_param->g_gamma_table; + } + + if (arg->b_gamma_table && (from_user || !cur_config->b_gamma_table)) { + if (copy_from_compatible(&css_param->b_gamma_table, + arg->b_gamma_table, + sizeof(struct ia_css_rgb_gamma_table), + from_user)) + return -EFAULT; + css_param->update_flag.b_gamma_table = + (struct atomisp_rgb_gamma_table *) + &css_param->b_gamma_table; + } + + if (arg->anr_thres && (from_user || !cur_config->anr_thres)) { + if (copy_from_compatible(&css_param->anr_thres, arg->anr_thres, + sizeof(struct ia_css_anr_thres), + from_user)) + return -EFAULT; + css_param->update_flag.anr_thres = + (struct atomisp_anr_thres *)&css_param->anr_thres; + } + + if (from_user) + css_param->isp_config_id = arg->isp_config_id; + /* + * These configurations are on used by ISP1.x, not for ISP2.x, + * so do not handle them. see comments of ia_css_isp_config. + * 1 cc_config + * 2 ce_config + * 3 de_config + * 4 gc_config + * 5 gamma_table + * 6 ctc_table + * 7 dvs_coefs + */ + return 0; +} + +int atomisp_cp_lsc_table(struct atomisp_sub_device *asd, + struct atomisp_shading_table *source_st, + struct atomisp_css_params *css_param, + bool from_user) +{ + unsigned int i; + unsigned int len_table; + struct ia_css_shading_table *shading_table; + struct ia_css_shading_table *old_table; + struct atomisp_shading_table *st, dest_st; + + if (!source_st) + return 0; + + if (!css_param) + return -EINVAL; + + if (!from_user && css_param->update_flag.shading_table) + return 0; + + if (IS_ISP2401) { + if (copy_from_compatible(&dest_st, source_st, + sizeof(struct atomisp_shading_table), + from_user)) { + dev_err(asd->isp->dev, "copy shading table failed!"); + return -EFAULT; + } + st = &dest_st; + } else { + st = source_st; + } + + old_table = css_param->shading_table; + + /* user config is to disable the shading table. */ + if (!st->enable) { + /* Generate a minimum table with enable = 0. */ + shading_table = atomisp_css_shading_table_alloc(1, 1); + if (!shading_table) + return -ENOMEM; + shading_table->enable = 0; + goto set_lsc; + } + + /* Setting a new table. Validate first - all tables must be set */ + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + if (!st->data[i]) { + dev_err(asd->isp->dev, "shading table validate failed"); + return -EINVAL; + } + } + + /* Shading table size per color */ + if (st->width > SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR || + st->height > SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR) { + dev_err(asd->isp->dev, "shading table w/h validate failed!"); + return -EINVAL; + } + + shading_table = atomisp_css_shading_table_alloc(st->width, st->height); + if (!shading_table) + return -ENOMEM; + + len_table = st->width * st->height * ATOMISP_SC_TYPE_SIZE; + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + if (copy_from_compatible(shading_table->data[i], + st->data[i], len_table, from_user)) { + atomisp_css_shading_table_free(shading_table); + return -EFAULT; + } + } + shading_table->sensor_width = st->sensor_width; + shading_table->sensor_height = st->sensor_height; + shading_table->fraction_bits = st->fraction_bits; + shading_table->enable = st->enable; + + /* No need to update shading table if it is the same */ + if (old_table && + old_table->sensor_width == shading_table->sensor_width && + old_table->sensor_height == shading_table->sensor_height && + old_table->width == shading_table->width && + old_table->height == shading_table->height && + old_table->fraction_bits == shading_table->fraction_bits && + old_table->enable == shading_table->enable) { + bool data_is_same = true; + + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + if (memcmp(shading_table->data[i], old_table->data[i], + len_table) != 0) { + data_is_same = false; + break; + } + } + + if (data_is_same) { + atomisp_css_shading_table_free(shading_table); + return 0; + } + } + +set_lsc: + /* set LSC to CSS */ + css_param->shading_table = shading_table; + css_param->update_flag.shading_table = (struct atomisp_shading_table *)shading_table; + asd->params.sc_en = shading_table; + + if (old_table) + atomisp_css_shading_table_free(old_table); + + return 0; +} + +int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd, + struct ia_css_dvs2_coefficients *coefs, + struct atomisp_css_params *css_param, + bool from_user) +{ + struct ia_css_dvs_grid_info *cur = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + int dvs_hor_coef_bytes, dvs_ver_coef_bytes; + struct ia_css_dvs2_coefficients dvs2_coefs; + + if (!coefs || !cur) + return 0; + + if (!from_user && css_param->update_flag.dvs2_coefs) + return 0; + + if (!IS_ISP2401) { + if (sizeof(*cur) != sizeof(coefs->grid) || + memcmp(&coefs->grid, cur, sizeof(coefs->grid))) { + dev_err(asd->isp->dev, "dvs grid mismatch!\n"); + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + } + + if (!coefs->hor_coefs.odd_real || + !coefs->hor_coefs.odd_imag || + !coefs->hor_coefs.even_real || + !coefs->hor_coefs.even_imag || + !coefs->ver_coefs.odd_real || + !coefs->ver_coefs.odd_imag || + !coefs->ver_coefs.even_real || + !coefs->ver_coefs.even_imag) + return -EINVAL; + + if (!css_param->dvs2_coeff) { + /* DIS coefficients. */ + css_param->dvs2_coeff = ia_css_dvs2_coefficients_allocate(cur); + if (!css_param->dvs2_coeff) + return -ENOMEM; + } + + dvs_hor_coef_bytes = asd->params.dvs_hor_coef_bytes; + dvs_ver_coef_bytes = asd->params.dvs_ver_coef_bytes; + if (copy_from_compatible(css_param->dvs2_coeff->hor_coefs.odd_real, + coefs->hor_coefs.odd_real, dvs_hor_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.odd_imag, + coefs->hor_coefs.odd_imag, dvs_hor_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.even_real, + coefs->hor_coefs.even_real, dvs_hor_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.even_imag, + coefs->hor_coefs.even_imag, dvs_hor_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.odd_real, + coefs->ver_coefs.odd_real, dvs_ver_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.odd_imag, + coefs->ver_coefs.odd_imag, dvs_ver_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.even_real, + coefs->ver_coefs.even_real, dvs_ver_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.even_imag, + coefs->ver_coefs.even_imag, dvs_ver_coef_bytes, from_user)) { + ia_css_dvs2_coefficients_free(css_param->dvs2_coeff); + css_param->dvs2_coeff = NULL; + return -EFAULT; + } + } else { + if (copy_from_compatible(&dvs2_coefs, coefs, + sizeof(struct ia_css_dvs2_coefficients), + from_user)) { + dev_err(asd->isp->dev, "copy dvs2 coef failed"); + return -EFAULT; + } + + if (sizeof(*cur) != sizeof(dvs2_coefs.grid) || + memcmp(&dvs2_coefs.grid, cur, sizeof(dvs2_coefs.grid))) { + dev_err(asd->isp->dev, "dvs grid mismatch!\n"); + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + } + + if (!dvs2_coefs.hor_coefs.odd_real || + !dvs2_coefs.hor_coefs.odd_imag || + !dvs2_coefs.hor_coefs.even_real || + !dvs2_coefs.hor_coefs.even_imag || + !dvs2_coefs.ver_coefs.odd_real || + !dvs2_coefs.ver_coefs.odd_imag || + !dvs2_coefs.ver_coefs.even_real || + !dvs2_coefs.ver_coefs.even_imag) + return -EINVAL; + + if (!css_param->dvs2_coeff) { + /* DIS coefficients. */ + css_param->dvs2_coeff = ia_css_dvs2_coefficients_allocate(cur); + if (!css_param->dvs2_coeff) + return -ENOMEM; + } + + dvs_hor_coef_bytes = asd->params.dvs_hor_coef_bytes; + dvs_ver_coef_bytes = asd->params.dvs_ver_coef_bytes; + if (copy_from_compatible(css_param->dvs2_coeff->hor_coefs.odd_real, + dvs2_coefs.hor_coefs.odd_real, dvs_hor_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.odd_imag, + dvs2_coefs.hor_coefs.odd_imag, dvs_hor_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.even_real, + dvs2_coefs.hor_coefs.even_real, dvs_hor_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.even_imag, + dvs2_coefs.hor_coefs.even_imag, dvs_hor_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.odd_real, + dvs2_coefs.ver_coefs.odd_real, dvs_ver_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.odd_imag, + dvs2_coefs.ver_coefs.odd_imag, dvs_ver_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.even_real, + dvs2_coefs.ver_coefs.even_real, dvs_ver_coef_bytes, from_user) || + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.even_imag, + dvs2_coefs.ver_coefs.even_imag, dvs_ver_coef_bytes, from_user)) { + ia_css_dvs2_coefficients_free(css_param->dvs2_coeff); + css_param->dvs2_coeff = NULL; + return -EFAULT; + } + } + + css_param->update_flag.dvs2_coefs = + (struct atomisp_dis_coefficients *)css_param->dvs2_coeff; + return 0; +} + +int atomisp_cp_dvs_6axis_config(struct atomisp_sub_device *asd, + struct atomisp_dvs_6axis_config *source_6axis_config, + struct atomisp_css_params *css_param, + bool from_user) +{ + struct ia_css_dvs_6axis_config *dvs_6axis_config; + struct ia_css_dvs_6axis_config *old_6axis_config; + struct ia_css_stream *stream = + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream; + struct ia_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + int ret = -EFAULT; + + if (!stream) { + dev_err(asd->isp->dev, "%s: internal error!", __func__); + return -EINVAL; + } + + if (!source_6axis_config || !dvs_grid_info) + return 0; + + if (!dvs_grid_info->enable) + return 0; + + if (!from_user && css_param->update_flag.dvs_6axis_config) + return 0; + + /* check whether need to reallocate for 6 axis config */ + old_6axis_config = css_param->dvs_6axis; + dvs_6axis_config = old_6axis_config; + + if (IS_ISP2401) { + struct ia_css_dvs_6axis_config t_6axis_config; + + if (copy_from_compatible(&t_6axis_config, source_6axis_config, + sizeof(struct atomisp_dvs_6axis_config), + from_user)) { + dev_err(asd->isp->dev, "copy morph table failed!"); + return -EFAULT; + } + + if (old_6axis_config && + (old_6axis_config->width_y != t_6axis_config.width_y || + old_6axis_config->height_y != t_6axis_config.height_y || + old_6axis_config->width_uv != t_6axis_config.width_uv || + old_6axis_config->height_uv != t_6axis_config.height_uv)) { + ia_css_dvs2_6axis_config_free(css_param->dvs_6axis); + css_param->dvs_6axis = NULL; + + dvs_6axis_config = ia_css_dvs2_6axis_config_allocate(stream); + if (!dvs_6axis_config) + return -ENOMEM; + } else if (!dvs_6axis_config) { + dvs_6axis_config = ia_css_dvs2_6axis_config_allocate(stream); + if (!dvs_6axis_config) + return -ENOMEM; + } + + dvs_6axis_config->exp_id = t_6axis_config.exp_id; + + if (copy_from_compatible(dvs_6axis_config->xcoords_y, + t_6axis_config.xcoords_y, + t_6axis_config.width_y * + t_6axis_config.height_y * + sizeof(*dvs_6axis_config->xcoords_y), + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->ycoords_y, + t_6axis_config.ycoords_y, + t_6axis_config.width_y * + t_6axis_config.height_y * + sizeof(*dvs_6axis_config->ycoords_y), + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->xcoords_uv, + t_6axis_config.xcoords_uv, + t_6axis_config.width_uv * + t_6axis_config.height_uv * + sizeof(*dvs_6axis_config->xcoords_uv), + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->ycoords_uv, + t_6axis_config.ycoords_uv, + t_6axis_config.width_uv * + t_6axis_config.height_uv * + sizeof(*dvs_6axis_config->ycoords_uv), + from_user)) + goto error; + } else { + if (old_6axis_config && + (old_6axis_config->width_y != source_6axis_config->width_y || + old_6axis_config->height_y != source_6axis_config->height_y || + old_6axis_config->width_uv != source_6axis_config->width_uv || + old_6axis_config->height_uv != source_6axis_config->height_uv)) { + ia_css_dvs2_6axis_config_free(css_param->dvs_6axis); + css_param->dvs_6axis = NULL; + + dvs_6axis_config = ia_css_dvs2_6axis_config_allocate(stream); + if (!dvs_6axis_config) + return -ENOMEM; + } else if (!dvs_6axis_config) { + dvs_6axis_config = ia_css_dvs2_6axis_config_allocate(stream); + if (!dvs_6axis_config) + return -ENOMEM; + } + + dvs_6axis_config->exp_id = source_6axis_config->exp_id; + + if (copy_from_compatible(dvs_6axis_config->xcoords_y, + source_6axis_config->xcoords_y, + source_6axis_config->width_y * + source_6axis_config->height_y * + sizeof(*source_6axis_config->xcoords_y), + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->ycoords_y, + source_6axis_config->ycoords_y, + source_6axis_config->width_y * + source_6axis_config->height_y * + sizeof(*source_6axis_config->ycoords_y), + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->xcoords_uv, + source_6axis_config->xcoords_uv, + source_6axis_config->width_uv * + source_6axis_config->height_uv * + sizeof(*source_6axis_config->xcoords_uv), + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->ycoords_uv, + source_6axis_config->ycoords_uv, + source_6axis_config->width_uv * + source_6axis_config->height_uv * + sizeof(*source_6axis_config->ycoords_uv), + from_user)) + goto error; + } + css_param->dvs_6axis = dvs_6axis_config; + css_param->update_flag.dvs_6axis_config = + (struct atomisp_dvs_6axis_config *)dvs_6axis_config; + return 0; + +error: + if (dvs_6axis_config) + ia_css_dvs2_6axis_config_free(dvs_6axis_config); + return ret; +} + +int atomisp_cp_morph_table(struct atomisp_sub_device *asd, + struct atomisp_morph_table *source_morph_table, + struct atomisp_css_params *css_param, + bool from_user) +{ + int ret = -EFAULT; + unsigned int i; + struct ia_css_morph_table *morph_table; + struct ia_css_morph_table *old_morph_table; + + if (!source_morph_table) + return 0; + + if (!from_user && css_param->update_flag.morph_table) + return 0; + + old_morph_table = css_param->morph_table; + + if (IS_ISP2401) { + struct ia_css_morph_table mtbl; + + if (copy_from_compatible(&mtbl, source_morph_table, + sizeof(struct atomisp_morph_table), + from_user)) { + dev_err(asd->isp->dev, "copy morph table failed!"); + return -EFAULT; + } + + morph_table = atomisp_css_morph_table_allocate( + mtbl.width, + mtbl.height); + if (!morph_table) + return -ENOMEM; + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + if (copy_from_compatible(morph_table->coordinates_x[i], + (__force void *)source_morph_table->coordinates_x[i], + mtbl.height * mtbl.width * + sizeof(*morph_table->coordinates_x[i]), + from_user)) + goto error; + + if (copy_from_compatible(morph_table->coordinates_y[i], + (__force void *)source_morph_table->coordinates_y[i], + mtbl.height * mtbl.width * + sizeof(*morph_table->coordinates_y[i]), + from_user)) + goto error; + } + } else { + morph_table = atomisp_css_morph_table_allocate( + source_morph_table->width, + source_morph_table->height); + if (!morph_table) + return -ENOMEM; + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + if (copy_from_compatible(morph_table->coordinates_x[i], + (__force void *)source_morph_table->coordinates_x[i], + source_morph_table->height * source_morph_table->width * + sizeof(*source_morph_table->coordinates_x[i]), + from_user)) + goto error; + + if (copy_from_compatible(morph_table->coordinates_y[i], + (__force void *)source_morph_table->coordinates_y[i], + source_morph_table->height * source_morph_table->width * + sizeof(*source_morph_table->coordinates_y[i]), + from_user)) + goto error; + } + } + + css_param->morph_table = morph_table; + if (old_morph_table) + atomisp_css_morph_table_free(old_morph_table); + css_param->update_flag.morph_table = + (struct atomisp_morph_table *)morph_table; + return 0; + +error: + if (morph_table) + atomisp_css_morph_table_free(morph_table); + return ret; +} + +int atomisp_makeup_css_parameters(struct atomisp_sub_device *asd, + struct atomisp_parameters *arg, + struct atomisp_css_params *css_param) +{ + int ret; + + ret = atomisp_cp_general_isp_parameters(asd, arg, css_param, false); + if (ret) + return ret; + ret = atomisp_cp_lsc_table(asd, arg->shading_table, css_param, false); + if (ret) + return ret; + ret = atomisp_cp_morph_table(asd, arg->morph_table, css_param, false); + if (ret) + return ret; + ret = atomisp_css_cp_dvs2_coefs(asd, + (struct ia_css_dvs2_coefficients *)arg->dvs2_coefs, + css_param, false); + if (ret) + return ret; + ret = atomisp_cp_dvs_6axis_config(asd, arg->dvs_6axis_config, + css_param, false); + return ret; +} + +void atomisp_free_css_parameters(struct atomisp_css_params *css_param) +{ + if (css_param->dvs_6axis) { + ia_css_dvs2_6axis_config_free(css_param->dvs_6axis); + css_param->dvs_6axis = NULL; + } + if (css_param->dvs2_coeff) { + ia_css_dvs2_coefficients_free(css_param->dvs2_coeff); + css_param->dvs2_coeff = NULL; + } + if (css_param->shading_table) { + ia_css_shading_table_free(css_param->shading_table); + css_param->shading_table = NULL; + } + if (css_param->morph_table) { + ia_css_morph_table_free(css_param->morph_table); + css_param->morph_table = NULL; + } +} + +static void atomisp_move_frame_to_activeq(struct ia_css_frame *frame, + struct atomisp_css_params_with_list *param) +{ + struct atomisp_video_pipe *pipe = vb_to_pipe(&frame->vb.vb2_buf); + unsigned long irqflags; + + pipe->frame_params[frame->vb.vb2_buf.index] = param; + spin_lock_irqsave(&pipe->irq_lock, irqflags); + list_move_tail(&frame->queue, &pipe->activeq); + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); +} + +/* + * Check parameter queue list and buffer queue list to find out if matched items + * and then set parameter to CSS and enqueue buffer to CSS. + * Of course, if the buffer in buffer waiting list is not bound to a per-frame + * parameter, it will be enqueued into CSS as long as the per-frame setting + * buffers before it get enqueued. + */ +void atomisp_handle_parameter_and_buffer(struct atomisp_video_pipe *pipe) +{ + struct atomisp_sub_device *asd = pipe->asd; + struct ia_css_frame *frame = NULL, *frame_tmp; + struct atomisp_css_params_with_list *param = NULL, *param_tmp; + bool need_to_enqueue_buffer = false; + int i; + + if (!asd) { + dev_err(pipe->isp->dev, "%s(): asd is NULL, device is %s\n", + __func__, pipe->vdev.name); + return; + } + + lockdep_assert_held(&asd->isp->mutex); + + if (atomisp_is_vf_pipe(pipe)) + return; + + /* + * CSS/FW requires set parameter and enqueue buffer happen after ISP + * is streamon. + */ + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + return; + + if (list_empty(&pipe->per_frame_params) || + list_empty(&pipe->buffers_waiting_for_param)) + return; + + list_for_each_entry_safe(frame, frame_tmp, + &pipe->buffers_waiting_for_param, queue) { + i = frame->vb.vb2_buf.index; + if (pipe->frame_request_config_id[i]) { + list_for_each_entry_safe(param, param_tmp, + &pipe->per_frame_params, list) { + if (pipe->frame_request_config_id[i] != param->params.isp_config_id) + continue; + + list_del(¶m->list); + + /* + * clear the request config id as the buffer + * will be handled and enqueued into CSS soon + */ + pipe->frame_request_config_id[i] = 0; + atomisp_move_frame_to_activeq(frame, param); + need_to_enqueue_buffer = true; + break; + } + + /* If this is the end, stop further loop */ + if (list_entry_is_head(param, &pipe->per_frame_params, list)) + break; + } else { + atomisp_move_frame_to_activeq(frame, NULL); + need_to_enqueue_buffer = true; + } + } + + if (!need_to_enqueue_buffer) + return; + + atomisp_qbuffers_to_css(asd); +} + +/* +* Function to configure ISP parameters +*/ +int atomisp_set_parameters(struct video_device *vdev, + struct atomisp_parameters *arg) +{ + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_css_params_with_list *param = NULL; + struct atomisp_css_params *css_param = &asd->params.css_param; + int ret; + + if (!asd) { + dev_err(pipe->isp->dev, "%s(): asd is NULL, device is %s\n", + __func__, vdev->name); + return -EINVAL; + } + + lockdep_assert_held(&asd->isp->mutex); + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(asd->isp->dev, "%s: internal error!\n", __func__); + return -EINVAL; + } + + dev_dbg(asd->isp->dev, + "%s: set parameter(per_frame_setting %d) for asd%d with isp_config_id %d of %s\n", + __func__, arg->per_frame_setting, asd->index, + arg->isp_config_id, vdev->name); + + if (IS_ISP2401) { + if (atomisp_is_vf_pipe(pipe) && arg->per_frame_setting) { + dev_err(asd->isp->dev, "%s: vf pipe not support per_frame_setting", + __func__); + return -EINVAL; + } + } + + if (arg->per_frame_setting && !atomisp_is_vf_pipe(pipe)) { + /* + * Per-frame setting enabled, we allocate a new parameter + * buffer to cache the parameters and only when frame buffers + * are ready, the parameters will be set to CSS. + * per-frame setting only works for the main output frame. + */ + param = kvzalloc(sizeof(*param), GFP_KERNEL); + if (!param) { + dev_err(asd->isp->dev, "%s: failed to alloc params buffer\n", + __func__); + return -ENOMEM; + } + css_param = ¶m->params; + } + + ret = atomisp_cp_general_isp_parameters(asd, arg, css_param, true); + if (ret) + goto apply_parameter_failed; + + ret = atomisp_cp_lsc_table(asd, arg->shading_table, css_param, true); + if (ret) + goto apply_parameter_failed; + + ret = atomisp_cp_morph_table(asd, arg->morph_table, css_param, true); + if (ret) + goto apply_parameter_failed; + + ret = atomisp_css_cp_dvs2_coefs(asd, + (struct ia_css_dvs2_coefficients *)arg->dvs2_coefs, + css_param, true); + if (ret) + goto apply_parameter_failed; + + ret = atomisp_cp_dvs_6axis_config(asd, arg->dvs_6axis_config, + css_param, true); + if (ret) + goto apply_parameter_failed; + + if (!(arg->per_frame_setting && !atomisp_is_vf_pipe(pipe))) { + /* indicate to CSS that we have parameters to be updated */ + asd->params.css_update_params_needed = true; + } else { + list_add_tail(¶m->list, &pipe->per_frame_params); + atomisp_handle_parameter_and_buffer(pipe); + } + + return 0; + +apply_parameter_failed: + if (css_param) + atomisp_free_css_parameters(css_param); + kvfree(param); + + return ret; +} + +/* + * Function to set/get isp parameters to isp + */ +int atomisp_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_parm *config) +{ + struct ia_css_pipe_config *vp_cfg = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + pipe_configs[IA_CSS_PIPE_ID_VIDEO]; + + /* Read parameter for 3A binary info */ + if (flag == 0) { + struct ia_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info( + &asd->params.curr_grid_info); + + atomisp_curr_user_grid_info(asd, &config->info); + + /* We always return the resolution and stride even if there is + * no valid metadata. This allows the caller to get the + * information needed to allocate user-space buffers. */ + config->metadata_config.metadata_height = asd-> + stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream_info. + metadata_info.resolution.height; + config->metadata_config.metadata_stride = asd-> + stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream_info. + metadata_info.stride; + + /* update dvs grid info */ + if (dvs_grid_info) + memcpy(&config->dvs_grid, + dvs_grid_info, + sizeof(struct ia_css_dvs_grid_info)); + + if (asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO) { + config->dvs_envelop.width = 0; + config->dvs_envelop.height = 0; + return 0; + } + + /* update dvs envelop info */ + if (!asd->continuous_mode->val) { + config->dvs_envelop.width = vp_cfg->dvs_envelope.width; + config->dvs_envelop.height = + vp_cfg->dvs_envelope.height; + } else { + unsigned int dvs_w, dvs_h, dvs_w_max, dvs_h_max; + + dvs_w = vp_cfg->bayer_ds_out_res.width - + vp_cfg->output_info[0].res.width; + dvs_h = vp_cfg->bayer_ds_out_res.height - + vp_cfg->output_info[0].res.height; + dvs_w_max = rounddown( + vp_cfg->output_info[0].res.width / 5, + ATOM_ISP_STEP_WIDTH); + dvs_h_max = rounddown( + vp_cfg->output_info[0].res.height / 5, + ATOM_ISP_STEP_HEIGHT); + + config->dvs_envelop.width = min(dvs_w, dvs_w_max); + config->dvs_envelop.height = min(dvs_h, dvs_h_max); + } + + return 0; + } + + memcpy(&asd->params.css_param.wb_config, &config->wb_config, + sizeof(struct ia_css_wb_config)); + memcpy(&asd->params.css_param.ob_config, &config->ob_config, + sizeof(struct ia_css_ob_config)); + memcpy(&asd->params.css_param.dp_config, &config->dp_config, + sizeof(struct ia_css_dp_config)); + memcpy(&asd->params.css_param.de_config, &config->de_config, + sizeof(struct ia_css_de_config)); + memcpy(&asd->params.css_param.dz_config, &config->dz_config, + sizeof(struct ia_css_dz_config)); + memcpy(&asd->params.css_param.ce_config, &config->ce_config, + sizeof(struct ia_css_ce_config)); + memcpy(&asd->params.css_param.nr_config, &config->nr_config, + sizeof(struct ia_css_nr_config)); + memcpy(&asd->params.css_param.ee_config, &config->ee_config, + sizeof(struct ia_css_ee_config)); + memcpy(&asd->params.css_param.tnr_config, &config->tnr_config, + sizeof(struct ia_css_tnr_config)); + + if (asd->params.color_effect == V4L2_COLORFX_NEGATIVE) { + asd->params.css_param.cc_config.matrix[3] = -config->cc_config.matrix[3]; + asd->params.css_param.cc_config.matrix[4] = -config->cc_config.matrix[4]; + asd->params.css_param.cc_config.matrix[5] = -config->cc_config.matrix[5]; + asd->params.css_param.cc_config.matrix[6] = -config->cc_config.matrix[6]; + asd->params.css_param.cc_config.matrix[7] = -config->cc_config.matrix[7]; + asd->params.css_param.cc_config.matrix[8] = -config->cc_config.matrix[8]; + } + + if (asd->params.color_effect != V4L2_COLORFX_SEPIA && + asd->params.color_effect != V4L2_COLORFX_BW) { + memcpy(&asd->params.css_param.cc_config, &config->cc_config, + sizeof(struct ia_css_cc_config)); + asd->params.config.cc_config = &asd->params.css_param.cc_config; + } + + asd->params.config.wb_config = &asd->params.css_param.wb_config; + asd->params.config.ob_config = &asd->params.css_param.ob_config; + asd->params.config.de_config = &asd->params.css_param.de_config; + asd->params.config.dz_config = &asd->params.css_param.dz_config; + asd->params.config.ce_config = &asd->params.css_param.ce_config; + asd->params.config.dp_config = &asd->params.css_param.dp_config; + asd->params.config.nr_config = &asd->params.css_param.nr_config; + asd->params.config.ee_config = &asd->params.css_param.ee_config; + asd->params.config.tnr_config = &asd->params.css_param.tnr_config; + asd->params.css_update_params_needed = true; + + return 0; +} + +/* + * Function to configure color effect of the image + */ +int atomisp_color_effect(struct atomisp_sub_device *asd, int flag, + __s32 *effect) +{ + struct ia_css_cc_config *cc_config = NULL; + struct ia_css_macc_table *macc_table = NULL; + struct ia_css_ctc_table *ctc_table = NULL; + int ret = 0; + struct v4l2_control control; + struct atomisp_device *isp = asd->isp; + + if (flag == 0) { + *effect = asd->params.color_effect; + return 0; + } + + control.id = V4L2_CID_COLORFX; + control.value = *effect; + ret = + v4l2_s_ctrl(NULL, isp->inputs[asd->input_curr].camera->ctrl_handler, + &control); + /* + * if set color effect to sensor successfully, return + * 0 directly. + */ + if (!ret) { + asd->params.color_effect = (u32)*effect; + return 0; + } + + if (*effect == asd->params.color_effect) + return 0; + + /* + * isp_subdev->params.macc_en should be set to false. + */ + asd->params.macc_en = false; + + switch (*effect) { + case V4L2_COLORFX_NONE: + macc_table = &asd->params.css_param.macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_SEPIA: + cc_config = &sepia_cc_config; + break; + case V4L2_COLORFX_NEGATIVE: + cc_config = &nega_cc_config; + break; + case V4L2_COLORFX_BW: + cc_config = &mono_cc_config; + break; + case V4L2_COLORFX_SKY_BLUE: + macc_table = &blue_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_GRASS_GREEN: + macc_table = &green_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_SKIN_WHITEN_LOW: + macc_table = &skin_low_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_SKIN_WHITEN: + macc_table = &skin_medium_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_SKIN_WHITEN_HIGH: + macc_table = &skin_high_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_VIVID: + ctc_table = &vivid_ctc_table; + break; + default: + return -EINVAL; + } + atomisp_update_capture_mode(asd); + + if (cc_config) + asd->params.config.cc_config = cc_config; + if (macc_table) + asd->params.config.macc_table = macc_table; + if (ctc_table) + atomisp_css_set_ctc_table(asd, ctc_table); + asd->params.color_effect = (u32)*effect; + asd->params.css_update_params_needed = true; + return 0; +} + +/* + * Function to configure bad pixel correction + */ +int atomisp_bad_pixel(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + if (flag == 0) { + *value = asd->params.bad_pixel_en; + return 0; + } + asd->params.bad_pixel_en = !!*value; + + return 0; +} + +/* + * Function to configure bad pixel correction params + */ +int atomisp_bad_pixel_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_dp_config *config) +{ + if (flag == 0) { + /* Get bad pixel from current setup */ + if (atomisp_css_get_dp_config(asd, config)) + return -EINVAL; + } else { + /* Set bad pixel to isp parameters */ + memcpy(&asd->params.css_param.dp_config, config, + sizeof(asd->params.css_param.dp_config)); + asd->params.config.dp_config = &asd->params.css_param.dp_config; + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to enable/disable video image stablization + */ +int atomisp_video_stable(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + if (flag == 0) + *value = asd->params.video_dis_en; + else + asd->params.video_dis_en = !!*value; + + return 0; +} + +/* + * Function to configure fixed pattern noise + */ +int atomisp_fixed_pattern(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + if (flag == 0) { + *value = asd->params.fpn_en; + return 0; + } + + if (*value == 0) { + asd->params.fpn_en = false; + return 0; + } + + /* Add function to get black from from sensor with shutter off */ + return 0; +} + +static unsigned int +atomisp_bytesperline_to_padded_width(unsigned int bytesperline, + enum ia_css_frame_format format) +{ + switch (format) { + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_RAW: + case IA_CSS_FRAME_FORMAT_RGB565: + return bytesperline / 2; + case IA_CSS_FRAME_FORMAT_RGBA888: + return bytesperline / 4; + /* The following cases could be removed, but we leave them + in to document the formats that are included. */ + case IA_CSS_FRAME_FORMAT_NV11: + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV61: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_YV16: + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_YUV422: + case IA_CSS_FRAME_FORMAT_YUV422_16: + case IA_CSS_FRAME_FORMAT_YUV444: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + case IA_CSS_FRAME_FORMAT_QPLANE6: + case IA_CSS_FRAME_FORMAT_BINARY_8: + default: + return bytesperline; + } +} + +static int +atomisp_v4l2_framebuffer_to_css_frame(const struct v4l2_framebuffer *arg, + struct ia_css_frame **result) +{ + struct ia_css_frame *res = NULL; + unsigned int padded_width; + enum ia_css_frame_format sh_format; + char *tmp_buf = NULL; + int ret = 0; + + sh_format = v4l2_fmt_to_sh_fmt(arg->fmt.pixelformat); + padded_width = atomisp_bytesperline_to_padded_width( + arg->fmt.bytesperline, sh_format); + + /* Note: the padded width on an ia_css_frame is in elements, not in + bytes. The RAW frame we use here should always be a 16bit RAW + frame. This is why we bytesperline/2 is equal to the padded with */ + if (ia_css_frame_allocate(&res, arg->fmt.width, arg->fmt.height, + sh_format, padded_width, 0)) { + ret = -ENOMEM; + goto err; + } + + tmp_buf = vmalloc(arg->fmt.sizeimage); + if (!tmp_buf) { + ret = -ENOMEM; + goto err; + } + if (copy_from_user(tmp_buf, (void __user __force *)arg->base, + arg->fmt.sizeimage)) { + ret = -EFAULT; + goto err; + } + + if (hmm_store(res->data, tmp_buf, arg->fmt.sizeimage)) { + ret = -EINVAL; + goto err; + } + +err: + if (ret && res) + ia_css_frame_free(res); + vfree(tmp_buf); + if (ret == 0) + *result = res; + return ret; +} + +/* + * Function to configure fixed pattern noise table + */ +int atomisp_fixed_pattern_table(struct atomisp_sub_device *asd, + struct v4l2_framebuffer *arg) +{ + struct ia_css_frame *raw_black_frame = NULL; + int ret; + + if (!arg) + return -EINVAL; + + ret = atomisp_v4l2_framebuffer_to_css_frame(arg, &raw_black_frame); + if (ret) + return ret; + + if (sh_css_set_black_frame(asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + raw_black_frame) != 0) + return -ENOMEM; + + ia_css_frame_free(raw_black_frame); + return ret; +} + +/* + * Function to configure false color correction + */ +int atomisp_false_color(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + /* Get nr config from current setup */ + if (flag == 0) { + *value = asd->params.false_color; + return 0; + } + + /* Set nr config to isp parameters */ + if (*value) { + asd->params.config.de_config = NULL; + } else { + asd->params.css_param.de_config.pixelnoise = 0; + asd->params.config.de_config = &asd->params.css_param.de_config; + } + asd->params.css_update_params_needed = true; + asd->params.false_color = *value; + return 0; +} + +/* + * Function to configure bad pixel correction params + */ +int atomisp_false_color_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_de_config *config) +{ + if (flag == 0) { + /* Get false color from current setup */ + if (atomisp_css_get_de_config(asd, config)) + return -EINVAL; + } else { + /* Set false color to isp parameters */ + memcpy(&asd->params.css_param.de_config, config, + sizeof(asd->params.css_param.de_config)); + asd->params.config.de_config = &asd->params.css_param.de_config; + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to configure white balance params + */ +int atomisp_white_balance_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_wb_config *config) +{ + if (flag == 0) { + /* Get white balance from current setup */ + if (atomisp_css_get_wb_config(asd, config)) + return -EINVAL; + } else { + /* Set white balance to isp parameters */ + memcpy(&asd->params.css_param.wb_config, config, + sizeof(asd->params.css_param.wb_config)); + asd->params.config.wb_config = &asd->params.css_param.wb_config; + asd->params.css_update_params_needed = true; + } + + return 0; +} + +int atomisp_3a_config_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_3a_config *config) +{ + struct atomisp_device *isp = asd->isp; + + dev_dbg(isp->dev, ">%s %d\n", __func__, flag); + + if (flag == 0) { + /* Get white balance from current setup */ + if (atomisp_css_get_3a_config(asd, config)) + return -EINVAL; + } else { + /* Set white balance to isp parameters */ + memcpy(&asd->params.css_param.s3a_config, config, + sizeof(asd->params.css_param.s3a_config)); + asd->params.config.s3a_config = &asd->params.css_param.s3a_config; + asd->params.css_update_params_needed = true; + } + + dev_dbg(isp->dev, "<%s %d\n", __func__, flag); + return 0; +} + +/* + * Function to setup digital zoom + */ +int atomisp_digital_zoom(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + u32 zoom; + struct atomisp_device *isp = asd->isp; + + unsigned int max_zoom = MRFLD_MAX_ZOOM_FACTOR; + + if (flag == 0) { + atomisp_css_get_zoom_factor(asd, &zoom); + *value = max_zoom - zoom; + } else { + if (*value < 0) + return -EINVAL; + + zoom = max_zoom - min_t(u32, max_zoom - 1, *value); + atomisp_css_set_zoom_factor(asd, zoom); + + dev_dbg(isp->dev, "%s, zoom: %d\n", __func__, zoom); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to get sensor specific info for current resolution, + * which will be used for auto exposure conversion. + */ +int atomisp_get_sensor_mode_data(struct atomisp_sub_device *asd, + struct atomisp_sensor_mode_data *config) +{ + struct camera_mipi_info *mipi_info; + struct atomisp_device *isp = asd->isp; + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (!mipi_info) + return -EINVAL; + + memcpy(config, &mipi_info->data, sizeof(*config)); + return 0; +} + +static void __atomisp_update_stream_env(struct atomisp_sub_device *asd, + u16 stream_index, struct atomisp_input_stream_info *stream_info) +{ + int i; + + /* assign virtual channel id return from sensor driver query */ + asd->stream_env[stream_index].ch_id = stream_info->ch_id; + asd->stream_env[stream_index].isys_configs = stream_info->isys_configs; + for (i = 0; i < stream_info->isys_configs; i++) { + asd->stream_env[stream_index].isys_info[i].input_format = + stream_info->isys_info[i].input_format; + asd->stream_env[stream_index].isys_info[i].width = + stream_info->isys_info[i].width; + asd->stream_env[stream_index].isys_info[i].height = + stream_info->isys_info[i].height; + } +} + +static void __atomisp_init_stream_info(u16 stream_index, + struct atomisp_input_stream_info *stream_info) +{ + int i; + + stream_info->enable = 1; + stream_info->stream = stream_index; + stream_info->ch_id = 0; + stream_info->isys_configs = 0; + for (i = 0; i < MAX_STREAMS_PER_CHANNEL; i++) { + stream_info->isys_info[i].input_format = 0; + stream_info->isys_info[i].width = 0; + stream_info->isys_info[i].height = 0; + } +} + +/* This function looks up the closest available resolution. */ +int atomisp_try_fmt(struct video_device *vdev, struct v4l2_pix_format *f, + bool *res_overflow) +{ + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct v4l2_subdev_pad_config pad_cfg; + struct v4l2_subdev_state pad_state = { + .pads = &pad_cfg + }; + struct v4l2_subdev_format format = { + .which = V4L2_SUBDEV_FORMAT_TRY, + }; + + struct v4l2_mbus_framefmt *snr_mbus_fmt = &format.format; + const struct atomisp_format_bridge *fmt; + struct atomisp_input_stream_info *stream_info = + (struct atomisp_input_stream_info *)snr_mbus_fmt->reserved; + int ret; + + if (!asd) { + dev_err(isp->dev, "%s(): asd is NULL, device is %s\n", + __func__, vdev->name); + return -EINVAL; + } + + if (!isp->inputs[asd->input_curr].camera) + return -EINVAL; + + fmt = atomisp_get_format_bridge(f->pixelformat); + if (!fmt) { + dev_err(isp->dev, "unsupported pixelformat!\n"); + fmt = atomisp_output_fmts; + } + + if (f->width <= 0 || f->height <= 0) + return -EINVAL; + + snr_mbus_fmt->code = fmt->mbus_code; + snr_mbus_fmt->width = f->width; + snr_mbus_fmt->height = f->height; + + __atomisp_init_stream_info(ATOMISP_INPUT_STREAM_GENERAL, stream_info); + + dev_dbg(isp->dev, "try_mbus_fmt: asking for %ux%u\n", + snr_mbus_fmt->width, snr_mbus_fmt->height); + + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + pad, set_fmt, &pad_state, &format); + if (ret) + return ret; + + dev_dbg(isp->dev, "try_mbus_fmt: got %ux%u\n", + snr_mbus_fmt->width, snr_mbus_fmt->height); + + fmt = atomisp_get_format_bridge_from_mbus(snr_mbus_fmt->code); + if (!fmt) { + dev_err(isp->dev, "unknown sensor format 0x%8.8x\n", + snr_mbus_fmt->code); + return -EINVAL; + } + + f->pixelformat = fmt->pixelformat; + + /* + * If the format is jpeg or custom RAW, then the width and height will + * not satisfy the normal atomisp requirements and no need to check + * the below conditions. So just assign to what is being returned from + * the sensor driver. + */ + if (f->pixelformat == V4L2_PIX_FMT_JPEG || + f->pixelformat == V4L2_PIX_FMT_CUSTOM_M10MO_RAW) { + f->width = snr_mbus_fmt->width; + f->height = snr_mbus_fmt->height; + return 0; + } + + if (!res_overflow || (snr_mbus_fmt->width < f->width && + snr_mbus_fmt->height < f->height)) { + f->width = snr_mbus_fmt->width; + f->height = snr_mbus_fmt->height; + /* Set the flag when resolution requested is + * beyond the max value supported by sensor + */ + if (res_overflow) + *res_overflow = true; + } + + /* app vs isp */ + f->width = rounddown(clamp_t(u32, f->width, ATOM_ISP_MIN_WIDTH, + ATOM_ISP_MAX_WIDTH), ATOM_ISP_STEP_WIDTH); + f->height = rounddown(clamp_t(u32, f->height, ATOM_ISP_MIN_HEIGHT, + ATOM_ISP_MAX_HEIGHT), ATOM_ISP_STEP_HEIGHT); + + return 0; +} + +enum mipi_port_id __get_mipi_port(struct atomisp_device *isp, + enum atomisp_camera_port port) +{ + switch (port) { + case ATOMISP_CAMERA_PORT_PRIMARY: + return MIPI_PORT0_ID; + case ATOMISP_CAMERA_PORT_SECONDARY: + return MIPI_PORT1_ID; + case ATOMISP_CAMERA_PORT_TERTIARY: + if (MIPI_PORT1_ID + 1 != N_MIPI_PORT_ID) + return MIPI_PORT1_ID + 1; + fallthrough; + default: + dev_err(isp->dev, "unsupported port: %d\n", port); + return MIPI_PORT0_ID; + } +} + +static inline int atomisp_set_sensor_mipi_to_isp( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct camera_mipi_info *mipi_info) +{ + struct v4l2_control ctrl; + struct atomisp_device *isp = asd->isp; + const struct atomisp_in_fmt_conv *fc; + int mipi_freq = 0; + unsigned int input_format, bayer_order; + + ctrl.id = V4L2_CID_LINK_FREQ; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl) == 0) + mipi_freq = ctrl.value; + + if (asd->stream_env[stream_id].isys_configs == 1) { + input_format = + asd->stream_env[stream_id].isys_info[0].input_format; + atomisp_css_isys_set_format(asd, stream_id, + input_format, IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + } else if (asd->stream_env[stream_id].isys_configs == 2) { + atomisp_css_isys_two_stream_cfg_update_stream1( + asd, stream_id, + asd->stream_env[stream_id].isys_info[0].input_format, + asd->stream_env[stream_id].isys_info[0].width, + asd->stream_env[stream_id].isys_info[0].height); + + atomisp_css_isys_two_stream_cfg_update_stream2( + asd, stream_id, + asd->stream_env[stream_id].isys_info[1].input_format, + asd->stream_env[stream_id].isys_info[1].width, + asd->stream_env[stream_id].isys_info[1].height); + } + + /* Compatibility for sensors which provide no media bus code + * in s_mbus_framefmt() nor support pad formats. */ + if (mipi_info->input_format != -1) { + bayer_order = mipi_info->raw_bayer_order; + + /* Input stream config is still needs configured */ + /* TODO: Check if this is necessary */ + fc = atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + mipi_info->input_format); + if (!fc) + return -EINVAL; + input_format = fc->atomisp_in_fmt; + } else { + struct v4l2_mbus_framefmt *sink; + + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + fc = atomisp_find_in_fmt_conv(sink->code); + if (!fc) + return -EINVAL; + input_format = fc->atomisp_in_fmt; + bayer_order = fc->bayer_order; + } + + atomisp_css_input_set_format(asd, stream_id, input_format); + atomisp_css_input_set_bayer_order(asd, stream_id, bayer_order); + + fc = atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + mipi_info->metadata_format); + if (!fc) + return -EINVAL; + input_format = fc->atomisp_in_fmt; + atomisp_css_input_configure_port(asd, + __get_mipi_port(asd->isp, mipi_info->port), + mipi_info->num_lanes, + 0xffff4, mipi_freq, + input_format, + mipi_info->metadata_width, + mipi_info->metadata_height); + return 0; +} + +static int __enable_continuous_mode(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_device *isp = asd->isp; + + dev_dbg(isp->dev, + "continuous mode %d, raw buffers %d, stop preview %d\n", + enable, asd->continuous_raw_buffer_size->val, + !asd->continuous_viewfinder->val); + + if (!IS_ISP2401) + atomisp_css_capture_set_mode(asd, IA_CSS_CAPTURE_MODE_PRIMARY); + else + atomisp_update_capture_mode(asd); + + /* in case of ANR, force capture pipe to offline mode */ + atomisp_css_capture_enable_online(asd, ATOMISP_INPUT_STREAM_GENERAL, + asd->params.low_light ? false : !enable); + atomisp_css_preview_enable_online(asd, ATOMISP_INPUT_STREAM_GENERAL, + !enable); + atomisp_css_enable_continuous(asd, enable); + atomisp_css_enable_cvf(asd, asd->continuous_viewfinder->val); + + atomisp_css_continuous_set_num_raw_frames(asd, + asd->continuous_raw_buffer_size->val); + + if (!enable) { + atomisp_css_enable_raw_binning(asd, false); + atomisp_css_input_set_two_pixels_per_clock(asd, false); + } + + if (isp->inputs[asd->input_curr].type != FILE_INPUT) + atomisp_css_input_set_mode(asd, IA_CSS_INPUT_MODE_BUFFERED_SENSOR); + + return atomisp_update_run_mode(asd); +} + +static int configure_pp_input_nop(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) +{ + return 0; +} + +static int configure_output_nop(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format sh_fmt) +{ + return 0; +} + +static int get_frame_info_nop(struct atomisp_sub_device *asd, + struct ia_css_frame_info *finfo) +{ + return 0; +} + +/* + * Resets CSS parameters that depend on input resolution. + * + * Update params like CSS RAW binning, 2ppc mode and pp_input + * which depend on input size, but are not automatically + * handled in CSS when the input resolution is changed. + */ +static int css_input_resolution_changed(struct atomisp_sub_device *asd, + struct v4l2_mbus_framefmt *ffmt) +{ + struct atomisp_metadata_buf *md_buf = NULL, *_md_buf; + unsigned int i; + + dev_dbg(asd->isp->dev, "css_input_resolution_changed to %ux%u\n", + ffmt->width, ffmt->height); + + if (IS_ISP2401) + atomisp_css_input_set_two_pixels_per_clock(asd, false); + else + atomisp_css_input_set_two_pixels_per_clock(asd, true); + + if (asd->continuous_mode->val) { + /* Note for all checks: ffmt includes pad_w+pad_h */ + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO || + (ffmt->width >= 2048 || ffmt->height >= 1536)) { + /* + * For preview pipe, enable only if resolution + * is >= 3M for ISP2400. + */ + atomisp_css_enable_raw_binning(asd, true); + } + } + /* + * If sensor input changed, which means metadata resolution changed + * together. Release all metadata buffers here to let it re-allocated + * next time in reqbufs. + */ + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + list_for_each_entry_safe(md_buf, _md_buf, &asd->metadata[i], + list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + } + return 0; + + /* + * TODO: atomisp_css_preview_configure_pp_input() not + * reset due to CSS bug tracked as PSI BZ 115124 + */ +} + +static int atomisp_set_fmt_to_isp(struct video_device *vdev, + struct ia_css_frame_info *output_info, + struct ia_css_frame_info *raw_output_info, + struct v4l2_pix_format *pix, + unsigned int source_pad) +{ + struct camera_mipi_info *mipi_info; + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + const struct atomisp_format_bridge *format; + struct v4l2_rect *isp_sink_crop; + enum ia_css_pipe_id pipe_id; + struct v4l2_subdev_fh fh; + int (*configure_output)(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format sh_fmt) = + configure_output_nop; + int (*get_frame_info)(struct atomisp_sub_device *asd, + struct ia_css_frame_info *finfo) = + get_frame_info_nop; + int (*configure_pp_input)(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) = + configure_pp_input_nop; + const struct atomisp_in_fmt_conv *fc; + int ret, i; + + if (!asd) { + dev_err(isp->dev, "%s(): asd is NULL, device is %s\n", + __func__, vdev->name); + return -EINVAL; + } + + v4l2_fh_init(&fh.vfh, vdev); + + isp_sink_crop = atomisp_subdev_get_rect( + &asd->subdev, NULL, V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, V4L2_SEL_TGT_CROP); + + format = atomisp_get_format_bridge(pix->pixelformat); + if (!format) + return -EINVAL; + + if (isp->inputs[asd->input_curr].type != TEST_PATTERN && + isp->inputs[asd->input_curr].type != FILE_INPUT) { + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (!mipi_info) { + dev_err(isp->dev, "mipi_info is NULL\n"); + return -EINVAL; + } + if (atomisp_set_sensor_mipi_to_isp(asd, ATOMISP_INPUT_STREAM_GENERAL, + mipi_info)) + return -EINVAL; + fc = atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + mipi_info->input_format); + if (!fc) + fc = atomisp_find_in_fmt_conv( + atomisp_subdev_get_ffmt(&asd->subdev, + NULL, V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK)->code); + if (!fc) + return -EINVAL; + if (format->sh_fmt == IA_CSS_FRAME_FORMAT_RAW && + raw_output_format_match_input(fc->atomisp_in_fmt, + pix->pixelformat)) + return -EINVAL; + } + + /* + * Configure viewfinder also when vfpp is disabled: the + * CSS still requires viewfinder configuration. + */ + if (asd->fmt_auto->val || + asd->vfpp->val != ATOMISP_VFPP_ENABLE) { + struct v4l2_rect vf_size = {0}; + struct v4l2_mbus_framefmt vf_ffmt = {0}; + + if (pix->width < 640 || pix->height < 480) { + vf_size.width = pix->width; + vf_size.height = pix->height; + } else { + vf_size.width = 640; + vf_size.height = 480; + } + + /* FIXME: proper format name for this one. See + atomisp_output_fmts[] in atomisp_v4l2.c */ + vf_ffmt.code = V4L2_MBUS_FMT_CUSTOM_YUV420; + + atomisp_subdev_set_selection(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_VF, + V4L2_SEL_TGT_COMPOSE, 0, &vf_size); + atomisp_subdev_set_ffmt(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_VF, &vf_ffmt); + asd->video_out_vf.sh_fmt = IA_CSS_FRAME_FORMAT_NV12; + + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + atomisp_css_video_configure_viewfinder(asd, + vf_size.width, vf_size.height, 0, + asd->video_out_vf.sh_fmt); + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) + atomisp_css_video_configure_viewfinder(asd, + vf_size.width, vf_size.height, 0, + asd->video_out_vf.sh_fmt); + else + atomisp_css_capture_configure_viewfinder(asd, + vf_size.width, vf_size.height, 0, + asd->video_out_vf.sh_fmt); + } else if (source_pad != ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW || + asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + atomisp_css_capture_configure_viewfinder(asd, + vf_size.width, vf_size.height, 0, + asd->video_out_vf.sh_fmt); + } + } + + if (asd->continuous_mode->val) { + ret = __enable_continuous_mode(asd, true); + if (ret) + return -EINVAL; + } + + atomisp_css_input_set_mode(asd, IA_CSS_INPUT_MODE_BUFFERED_SENSOR); + + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].pipe_extra_configs[i].disable_vf_pp = asd->vfpp->val != ATOMISP_VFPP_ENABLE; + + /* ISP2401 new input system need to use copy pipe */ + if (asd->copy_mode) { + pipe_id = IA_CSS_PIPE_ID_COPY; + atomisp_css_capture_enable_online(asd, ATOMISP_INPUT_STREAM_GENERAL, false); + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + /* video same in continuouscapture and online modes */ + configure_output = atomisp_css_video_configure_output; + get_frame_info = atomisp_css_video_get_output_frame_info; + pipe_id = IA_CSS_PIPE_ID_VIDEO; + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + if (!asd->continuous_mode->val) { + configure_output = atomisp_css_video_configure_output; + get_frame_info = + atomisp_css_video_get_output_frame_info; + pipe_id = IA_CSS_PIPE_ID_VIDEO; + } else { + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) { + configure_output = + atomisp_css_video_configure_output; + get_frame_info = + atomisp_css_video_get_output_frame_info; + configure_pp_input = + atomisp_css_video_configure_pp_input; + pipe_id = IA_CSS_PIPE_ID_VIDEO; + } else { + configure_output = + atomisp_css_capture_configure_output; + get_frame_info = + atomisp_css_capture_get_output_frame_info; + configure_pp_input = + atomisp_css_capture_configure_pp_input; + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + atomisp_update_capture_mode(asd); + atomisp_css_capture_enable_online(asd, + ATOMISP_INPUT_STREAM_GENERAL, + false); + } + } + } else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) { + configure_output = atomisp_css_preview_configure_output; + get_frame_info = atomisp_css_preview_get_output_frame_info; + configure_pp_input = atomisp_css_preview_configure_pp_input; + pipe_id = IA_CSS_PIPE_ID_PREVIEW; + } else { + /* CSS doesn't support low light mode on SOC cameras, so disable + * it. FIXME: if this is done elsewhere, it gives corrupted + * colors into thumbnail image. + */ + if (isp->inputs[asd->input_curr].type == SOC_CAMERA) + asd->params.low_light = false; + + if (format->sh_fmt == IA_CSS_FRAME_FORMAT_RAW) { + atomisp_css_capture_set_mode(asd, IA_CSS_CAPTURE_MODE_RAW); + atomisp_css_enable_dz(asd, false); + } else { + atomisp_update_capture_mode(asd); + } + + if (!asd->continuous_mode->val) + /* in case of ANR, force capture pipe to offline mode */ + atomisp_css_capture_enable_online(asd, ATOMISP_INPUT_STREAM_GENERAL, + asd->params.low_light ? + false : asd->params.online_process); + + configure_output = atomisp_css_capture_configure_output; + get_frame_info = atomisp_css_capture_get_output_frame_info; + configure_pp_input = atomisp_css_capture_configure_pp_input; + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + if (!asd->params.online_process && + !asd->continuous_mode->val) { + ret = atomisp_css_capture_get_output_raw_frame_info(asd, + raw_output_info); + if (ret) + return ret; + } + if (!asd->continuous_mode->val && asd->run_mode->val + != ATOMISP_RUN_MODE_STILL_CAPTURE) { + dev_err(isp->dev, + "Need to set the running mode first\n"); + asd->run_mode->val = ATOMISP_RUN_MODE_STILL_CAPTURE; + } + } + + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + + if (asd->copy_mode) + ret = atomisp_css_copy_configure_output(asd, ATOMISP_INPUT_STREAM_GENERAL, + pix->width, pix->height, + format->planar ? pix->bytesperline : + pix->bytesperline * 8 / format->depth, + format->sh_fmt); + else + ret = configure_output(asd, pix->width, pix->height, + format->planar ? pix->bytesperline : + pix->bytesperline * 8 / format->depth, + format->sh_fmt); + if (ret) { + dev_err(isp->dev, "configure_output %ux%u, format %8.8x\n", + pix->width, pix->height, format->sh_fmt); + return -EINVAL; + } + + ret = configure_pp_input(asd, isp_sink_crop->width, isp_sink_crop->height); + if (ret) { + dev_err(isp->dev, "configure_pp_input %ux%u\n", + isp_sink_crop->width, + isp_sink_crop->height); + return -EINVAL; + } + if (asd->copy_mode) + ret = atomisp_css_copy_get_output_frame_info(asd, + ATOMISP_INPUT_STREAM_GENERAL, + output_info); + else + ret = get_frame_info(asd, output_info); + if (ret) { + dev_err(isp->dev, "__get_frame_info %ux%u (padded to %u) returned %d\n", + pix->width, pix->height, pix->bytesperline, ret); + return ret; + } + + atomisp_update_grid_info(asd, pipe_id, source_pad); + + /* Free the raw_dump buffer first */ + ia_css_frame_free(asd->raw_output_frame); + asd->raw_output_frame = NULL; + + if (!asd->continuous_mode->val && !asd->params.online_process && + ia_css_frame_allocate_from_info(&asd->raw_output_frame, + raw_output_info)) + return -ENOMEM; + + return 0; +} + +static void atomisp_get_dis_envelop(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int *dvs_env_w, unsigned int *dvs_env_h) +{ + struct atomisp_device *isp = asd->isp; + + /* if subdev type is SOC camera,we do not need to set DVS */ + if (isp->inputs[asd->input_curr].type == SOC_CAMERA) + asd->params.video_dis_en = false; + + if (asd->params.video_dis_en && + asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + /* envelope is 20% of the output resolution */ + /* + * dvs envelope cannot be round up. + * it would cause ISP timeout and color switch issue + */ + *dvs_env_w = rounddown(width / 5, ATOM_ISP_STEP_WIDTH); + *dvs_env_h = rounddown(height / 5, ATOM_ISP_STEP_HEIGHT); + } + + asd->params.dis_proj_data_valid = false; + asd->params.css_update_params_needed = true; +} + +static void atomisp_check_copy_mode(struct atomisp_sub_device *asd, + int source_pad, struct v4l2_pix_format *f) +{ + struct v4l2_mbus_framefmt *sink, *src; + + if (!IS_ISP2401) { + /* Only used for the new input system */ + asd->copy_mode = false; + return; + } + + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, ATOMISP_SUBDEV_PAD_SINK); + src = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, source_pad); + + if (sink->code == src->code && sink->width == f->width && sink->height == f->height) + asd->copy_mode = true; + else + asd->copy_mode = false; + + dev_dbg(asd->isp->dev, "copy_mode: %d\n", asd->copy_mode); +} + +static int atomisp_set_fmt_to_snr(struct video_device *vdev, + struct v4l2_pix_format *f, unsigned int pixelformat, + unsigned int padding_w, unsigned int padding_h, + unsigned int dvs_env_w, unsigned int dvs_env_h) +{ + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + const struct atomisp_format_bridge *format; + struct v4l2_subdev_pad_config pad_cfg; + struct v4l2_subdev_state pad_state = { + .pads = &pad_cfg + }; + struct v4l2_subdev_format vformat = { + .which = V4L2_SUBDEV_FORMAT_TRY, + }; + struct v4l2_mbus_framefmt *ffmt = &vformat.format; + struct v4l2_mbus_framefmt *req_ffmt; + struct atomisp_device *isp; + struct atomisp_input_stream_info *stream_info = + (struct atomisp_input_stream_info *)ffmt->reserved; + int source_pad = atomisp_subdev_source_pad(vdev); + struct v4l2_subdev_fh fh; + int ret; + + if (!asd) { + dev_err(pipe->isp->dev, "%s(): asd is NULL, device is %s\n", + __func__, vdev->name); + return -EINVAL; + } + + isp = asd->isp; + + v4l2_fh_init(&fh.vfh, vdev); + + format = atomisp_get_format_bridge(pixelformat); + if (!format) + return -EINVAL; + + v4l2_fill_mbus_format(ffmt, f, format->mbus_code); + ffmt->height += padding_h + dvs_env_h; + ffmt->width += padding_w + dvs_env_w; + + dev_dbg(isp->dev, "s_mbus_fmt: ask %ux%u (padding %ux%u, dvs %ux%u)\n", + ffmt->width, ffmt->height, padding_w, padding_h, + dvs_env_w, dvs_env_h); + + __atomisp_init_stream_info(ATOMISP_INPUT_STREAM_GENERAL, stream_info); + + req_ffmt = ffmt; + + /* Disable dvs if resolution can't be supported by sensor */ + if (asd->params.video_dis_en && + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) { + vformat.which = V4L2_SUBDEV_FORMAT_TRY; + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + pad, set_fmt, &pad_state, &vformat); + if (ret) + return ret; + + dev_dbg(isp->dev, "video dis: sensor width: %d, height: %d\n", + ffmt->width, ffmt->height); + + if (ffmt->width < req_ffmt->width || + ffmt->height < req_ffmt->height) { + req_ffmt->height -= dvs_env_h; + req_ffmt->width -= dvs_env_w; + ffmt = req_ffmt; + dev_warn(isp->dev, + "can not enable video dis due to sensor limitation."); + asd->params.video_dis_en = false; + } + } + vformat.which = V4L2_SUBDEV_FORMAT_ACTIVE; + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, pad, + set_fmt, NULL, &vformat); + if (ret) + return ret; + + __atomisp_update_stream_env(asd, ATOMISP_INPUT_STREAM_GENERAL, stream_info); + + dev_dbg(isp->dev, "sensor width: %d, height: %d\n", + ffmt->width, ffmt->height); + + if (ffmt->width < ATOM_ISP_STEP_WIDTH || + ffmt->height < ATOM_ISP_STEP_HEIGHT) + return -EINVAL; + + if (asd->params.video_dis_en && + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO && + (ffmt->width < req_ffmt->width || ffmt->height < req_ffmt->height)) { + dev_warn(isp->dev, + "can not enable video dis due to sensor limitation."); + asd->params.video_dis_en = false; + } + + atomisp_subdev_set_ffmt(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, ffmt); + + return css_input_resolution_changed(asd, ffmt); +} + +int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f) +{ + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + const struct atomisp_format_bridge *format_bridge; + const struct atomisp_format_bridge *snr_format_bridge; + struct ia_css_frame_info output_info, raw_output_info; + struct v4l2_pix_format snr_fmt; + struct v4l2_pix_format backup_fmt, s_fmt; + unsigned int dvs_env_w = 0, dvs_env_h = 0; + unsigned int padding_w = pad_w, padding_h = pad_h; + bool res_overflow = false, crop_needs_override = false; + struct v4l2_mbus_framefmt *isp_sink_fmt; + struct v4l2_mbus_framefmt isp_source_fmt = {0}; + struct v4l2_subdev_format vformat = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + struct v4l2_mbus_framefmt *ffmt = &vformat.format; + struct v4l2_rect isp_sink_crop; + u16 source_pad = atomisp_subdev_source_pad(vdev); + struct v4l2_subdev_fh fh; + int ret; + + ret = atomisp_pipe_check(pipe, true); + if (ret) + return ret; + + if (source_pad >= ATOMISP_SUBDEV_PADS_NUM) + return -EINVAL; + + dev_dbg(isp->dev, + "setting resolution %ux%u on pad %u for asd%d, bytesperline %u\n", + f->fmt.pix.width, f->fmt.pix.height, source_pad, + asd->index, f->fmt.pix.bytesperline); + + v4l2_fh_init(&fh.vfh, vdev); + + format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat); + if (!format_bridge) + return -EINVAL; + + /* Currently, raw formats are broken!!! */ + + if (format_bridge->sh_fmt == IA_CSS_FRAME_FORMAT_RAW) { + f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420; + + format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat); + if (!format_bridge) + return -EINVAL; + } + pipe->sh_fmt = format_bridge->sh_fmt; + pipe->pix.pixelformat = f->fmt.pix.pixelformat; + + /* Ensure that the resolution is equal or below the maximum supported */ + + vformat.which = V4L2_SUBDEV_FORMAT_ACTIVE; + v4l2_fill_mbus_format(ffmt, &f->fmt.pix, format_bridge->mbus_code); + ffmt->height += padding_h; + ffmt->width += padding_w; + + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, pad, + set_fmt, NULL, &vformat); + if (ret) + return ret; + + f->fmt.pix.width = ffmt->width - padding_w; + f->fmt.pix.height = ffmt->height - padding_h; + + snr_fmt = f->fmt.pix; + backup_fmt = snr_fmt; + + /**********************************************************************/ + + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VF || + (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW + && asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO)) { + if (asd->fmt_auto->val) { + struct v4l2_rect *capture_comp; + struct v4l2_rect r = {0}; + + r.width = f->fmt.pix.width; + r.height = f->fmt.pix.height; + + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) + capture_comp = atomisp_subdev_get_rect( + &asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_VIDEO, + V4L2_SEL_TGT_COMPOSE); + else + capture_comp = atomisp_subdev_get_rect( + &asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE, + V4L2_SEL_TGT_COMPOSE); + + if (capture_comp->width < r.width + || capture_comp->height < r.height) { + r.width = capture_comp->width; + r.height = capture_comp->height; + } + + atomisp_subdev_set_selection( + &asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, source_pad, + V4L2_SEL_TGT_COMPOSE, 0, &r); + + f->fmt.pix.width = r.width; + f->fmt.pix.height = r.height; + } + + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) { + atomisp_css_video_configure_viewfinder(asd, + f->fmt.pix.width, f->fmt.pix.height, + format_bridge->planar ? f->fmt.pix.bytesperline + : f->fmt.pix.bytesperline * 8 + / format_bridge->depth, format_bridge->sh_fmt); + atomisp_css_video_get_viewfinder_frame_info(asd, + &output_info); + asd->copy_mode = false; + } else { + atomisp_css_capture_configure_viewfinder(asd, + f->fmt.pix.width, f->fmt.pix.height, + format_bridge->planar ? f->fmt.pix.bytesperline + : f->fmt.pix.bytesperline * 8 + / format_bridge->depth, format_bridge->sh_fmt); + atomisp_css_capture_get_viewfinder_frame_info(asd, + &output_info); + asd->copy_mode = false; + } + + goto done; + } + /* + * Check whether main resolution configured smaller + * than snapshot resolution. If so, force main resolution + * to be the same as snapshot resolution + */ + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) { + struct v4l2_rect *r; + + r = atomisp_subdev_get_rect( + &asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_VF, V4L2_SEL_TGT_COMPOSE); + + if (r->width && r->height + && (r->width > f->fmt.pix.width + || r->height > f->fmt.pix.height)) + dev_warn(isp->dev, + "Main Resolution config smaller then Vf Resolution. Force to be equal with Vf Resolution."); + } + + /* Pipeline configuration done through subdevs. Bail out now. */ + if (!asd->fmt_auto->val) + goto set_fmt_to_isp; + + /* get sensor resolution and format */ + ret = atomisp_try_fmt(vdev, &snr_fmt, &res_overflow); + if (ret) { + dev_warn(isp->dev, "Try format failed with error %d\n", ret); + return ret; + } + f->fmt.pix.width = snr_fmt.width; + f->fmt.pix.height = snr_fmt.height; + + snr_format_bridge = atomisp_get_format_bridge(snr_fmt.pixelformat); + if (!snr_format_bridge) { + dev_warn(isp->dev, "Can't find bridge format\n"); + return -EINVAL; + } + + atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK)->code = + snr_format_bridge->mbus_code; + + isp_sink_fmt = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + + isp_source_fmt.code = format_bridge->mbus_code; + atomisp_subdev_set_ffmt(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + source_pad, &isp_source_fmt); + + if (!atomisp_subdev_format_conversion(asd, source_pad)) { + padding_w = 0; + padding_h = 0; + } else if (IS_BYT) { + padding_w = 12; + padding_h = 12; + } + + /* construct resolution supported by isp */ + if (res_overflow && !asd->continuous_mode->val) { + f->fmt.pix.width = rounddown( + clamp_t(u32, f->fmt.pix.width - padding_w, + ATOM_ISP_MIN_WIDTH, + ATOM_ISP_MAX_WIDTH), ATOM_ISP_STEP_WIDTH); + f->fmt.pix.height = rounddown( + clamp_t(u32, f->fmt.pix.height - padding_h, + ATOM_ISP_MIN_HEIGHT, + ATOM_ISP_MAX_HEIGHT), ATOM_ISP_STEP_HEIGHT); + } + + atomisp_get_dis_envelop(asd, f->fmt.pix.width, f->fmt.pix.height, + &dvs_env_w, &dvs_env_h); + + if (asd->continuous_mode->val) { + struct v4l2_rect *r; + + r = atomisp_subdev_get_rect( + &asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE, + V4L2_SEL_TGT_COMPOSE); + /* + * The ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE should get resolutions + * properly set otherwise, it should not be the capture_pad. + */ + if (r->width && r->height) + asd->capture_pad = ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE; + else + asd->capture_pad = source_pad; + } else { + asd->capture_pad = source_pad; + } + /* + * set format info to sensor + * In continuous mode, resolution is set only if it is higher than + * existing value. This because preview pipe will be configured after + * capture pipe and usually has lower resolution than capture pipe. + */ + if (!asd->continuous_mode->val || + isp_sink_fmt->width < (f->fmt.pix.width + padding_w + dvs_env_w) || + isp_sink_fmt->height < (f->fmt.pix.height + padding_h + + dvs_env_h)) { + /* + * For jpeg or custom raw format the sensor will return constant + * width and height. Because we already had quried try_mbus_fmt, + * f->fmt.pix.width and f->fmt.pix.height has been changed to + * this fixed width and height. So we cannot select the correct + * resolution with that information. So use the original width + * and height while set_mbus_fmt() so actual resolutions are + * being used in while set media bus format. + */ + s_fmt = f->fmt.pix; + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_JPEG || + f->fmt.pix.pixelformat == V4L2_PIX_FMT_CUSTOM_M10MO_RAW) { + s_fmt.width = backup_fmt.width; + s_fmt.height = backup_fmt.height; + } + ret = atomisp_set_fmt_to_snr(vdev, &s_fmt, + f->fmt.pix.pixelformat, padding_w, + padding_h, dvs_env_w, dvs_env_h); + if (ret) { + dev_warn(isp->dev, + "Set format to sensor failed with %d\n", ret); + return -EINVAL; + } + + atomisp_csi_lane_config(isp); + crop_needs_override = true; + } + + atomisp_check_copy_mode(asd, source_pad, &backup_fmt); + asd->yuvpp_mode = false; /* Reset variable */ + + isp_sink_crop = *atomisp_subdev_get_rect(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, + V4L2_SEL_TGT_CROP); + + /* Try to enable YUV downscaling if ISP input is 10 % (either + * width or height) bigger than the desired result. */ + if (isp_sink_crop.width * 9 / 10 < f->fmt.pix.width || + isp_sink_crop.height * 9 / 10 < f->fmt.pix.height || + (atomisp_subdev_format_conversion(asd, source_pad) && + ((asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + !asd->continuous_mode->val) || + asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER))) { + /* for continuous mode, preview size might be smaller than + * still capture size. if preview size still needs crop, + * pick the larger one between crop size of preview and + * still capture. + */ + if (asd->continuous_mode->val + && source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW + && !crop_needs_override) { + isp_sink_crop.width = + max_t(unsigned int, f->fmt.pix.width, + isp_sink_crop.width); + isp_sink_crop.height = + max_t(unsigned int, f->fmt.pix.height, + isp_sink_crop.height); + } else { + isp_sink_crop.width = f->fmt.pix.width; + isp_sink_crop.height = f->fmt.pix.height; + } + + atomisp_subdev_set_selection(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, + V4L2_SEL_TGT_CROP, + V4L2_SEL_FLAG_KEEP_CONFIG, + &isp_sink_crop); + atomisp_subdev_set_selection(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + source_pad, V4L2_SEL_TGT_COMPOSE, + 0, &isp_sink_crop); + } else if (IS_MOFD) { + struct v4l2_rect main_compose = {0}; + + main_compose.width = isp_sink_crop.width; + main_compose.height = + DIV_ROUND_UP(main_compose.width * f->fmt.pix.height, + f->fmt.pix.width); + if (main_compose.height > isp_sink_crop.height) { + main_compose.height = isp_sink_crop.height; + main_compose.width = + DIV_ROUND_UP(main_compose.height * + f->fmt.pix.width, + f->fmt.pix.height); + } + + atomisp_subdev_set_selection(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + source_pad, + V4L2_SEL_TGT_COMPOSE, 0, + &main_compose); + } else { + struct v4l2_rect sink_crop = {0}; + struct v4l2_rect main_compose = {0}; + + main_compose.width = f->fmt.pix.width; + main_compose.height = f->fmt.pix.height; + + /* WORKAROUND: this override is universally enabled in + * GMIN to work around a CTS failures (GMINL-539) + * which appears to be related by a hardware + * performance limitation. It's unclear why this + * particular code triggers the issue. */ + if (crop_needs_override) { + if (isp_sink_crop.width * main_compose.height > + isp_sink_crop.height * main_compose.width) { + sink_crop.height = isp_sink_crop.height; + sink_crop.width = DIV_NEAREST_STEP( + sink_crop.height * + f->fmt.pix.width, + f->fmt.pix.height, + ATOM_ISP_STEP_WIDTH); + } else { + sink_crop.width = isp_sink_crop.width; + sink_crop.height = DIV_NEAREST_STEP( + sink_crop.width * + f->fmt.pix.height, + f->fmt.pix.width, + ATOM_ISP_STEP_HEIGHT); + } + atomisp_subdev_set_selection(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, + V4L2_SEL_TGT_CROP, + V4L2_SEL_FLAG_KEEP_CONFIG, + &sink_crop); + } + atomisp_subdev_set_selection(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + source_pad, + V4L2_SEL_TGT_COMPOSE, 0, + &main_compose); + } + +set_fmt_to_isp: + ret = atomisp_set_fmt_to_isp(vdev, &output_info, &raw_output_info, + &f->fmt.pix, source_pad); + if (ret) { + dev_warn(isp->dev, "Can't set format on ISP. Error %d\n", ret); + return -EINVAL; + } +done: + pipe->pix.width = f->fmt.pix.width; + pipe->pix.height = f->fmt.pix.height; + pipe->pix.pixelformat = f->fmt.pix.pixelformat; + /* + * FIXME: do we need to setup this differently, depending on the + * sensor or the pipeline? + */ + pipe->pix.colorspace = V4L2_COLORSPACE_REC709; + pipe->pix.ycbcr_enc = V4L2_YCBCR_ENC_709; + pipe->pix.xfer_func = V4L2_XFER_FUNC_709; + + if (format_bridge->planar) { + pipe->pix.bytesperline = output_info.padded_width; + pipe->pix.sizeimage = PAGE_ALIGN(f->fmt.pix.height * + DIV_ROUND_UP(format_bridge->depth * + output_info.padded_width, 8)); + } else { + pipe->pix.bytesperline = + DIV_ROUND_UP(format_bridge->depth * + output_info.padded_width, 8); + pipe->pix.sizeimage = + PAGE_ALIGN(f->fmt.pix.height * pipe->pix.bytesperline); + } + dev_dbg(isp->dev, "%s: image size: %d, %d bytes per line\n", + __func__, pipe->pix.sizeimage, pipe->pix.bytesperline); + + if (f->fmt.pix.field == V4L2_FIELD_ANY) + f->fmt.pix.field = V4L2_FIELD_NONE; + pipe->pix.field = f->fmt.pix.field; + + f->fmt.pix = pipe->pix; + f->fmt.pix.priv = PAGE_ALIGN(pipe->pix.width * + pipe->pix.height * 2); + + /* + * If in video 480P case, no GFX throttle + */ + if (asd->run_mode->val == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO && + f->fmt.pix.width == 720 && f->fmt.pix.height == 480) + isp->need_gfx_throttle = false; + else + isp->need_gfx_throttle = true; + + /* Report the needed sizes */ + f->fmt.pix.sizeimage = pipe->pix.sizeimage; + f->fmt.pix.bytesperline = pipe->pix.bytesperline; + + dev_dbg(isp->dev, "%s: %dx%d, image size: %d, %d bytes per line\n", + __func__, + f->fmt.pix.width, f->fmt.pix.height, + f->fmt.pix.sizeimage, f->fmt.pix.bytesperline); + + return 0; +} + +int atomisp_set_shading_table(struct atomisp_sub_device *asd, + struct atomisp_shading_table *user_shading_table) +{ + struct ia_css_shading_table *shading_table; + struct ia_css_shading_table *free_table; + unsigned int len_table; + int i; + int ret = 0; + + if (!user_shading_table) + return -EINVAL; + + if (!user_shading_table->enable) { + asd->params.config.shading_table = NULL; + asd->params.sc_en = false; + return 0; + } + + /* If enabling, all tables must be set */ + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + if (!user_shading_table->data[i]) + return -EINVAL; + } + + /* Shading table size per color */ + if (user_shading_table->width > SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR || + user_shading_table->height > SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR) + return -EINVAL; + + shading_table = atomisp_css_shading_table_alloc( + user_shading_table->width, user_shading_table->height); + if (!shading_table) + return -ENOMEM; + + len_table = user_shading_table->width * user_shading_table->height * + ATOMISP_SC_TYPE_SIZE; + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + ret = copy_from_user(shading_table->data[i], + (void __user *)user_shading_table->data[i], + len_table); + if (ret) { + free_table = shading_table; + ret = -EFAULT; + goto out; + } + } + shading_table->sensor_width = user_shading_table->sensor_width; + shading_table->sensor_height = user_shading_table->sensor_height; + shading_table->fraction_bits = user_shading_table->fraction_bits; + + free_table = asd->params.css_param.shading_table; + asd->params.css_param.shading_table = shading_table; + asd->params.config.shading_table = shading_table; + asd->params.sc_en = true; + +out: + if (free_table) + atomisp_css_shading_table_free(free_table); + + return ret; +} + +int atomisp_exif_makernote(struct atomisp_sub_device *asd, + struct atomisp_makernote_info *config) +{ + struct v4l2_control ctrl; + struct atomisp_device *isp = asd->isp; + + ctrl.id = V4L2_CID_FOCAL_ABSOLUTE; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl)) { + dev_warn(isp->dev, "failed to g_ctrl for focal length\n"); + return -EINVAL; + } else { + config->focal_length = ctrl.value; + } + + ctrl.id = V4L2_CID_FNUMBER_ABSOLUTE; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl)) { + dev_warn(isp->dev, "failed to g_ctrl for f-number\n"); + return -EINVAL; + } else { + config->f_number_curr = ctrl.value; + } + + ctrl.id = V4L2_CID_FNUMBER_RANGE; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl)) { + dev_warn(isp->dev, "failed to g_ctrl for f number range\n"); + return -EINVAL; + } else { + config->f_number_range = ctrl.value; + } + + return 0; +} + +int atomisp_offline_capture_configure(struct atomisp_sub_device *asd, + struct atomisp_cont_capture_conf *cvf_config) +{ + struct v4l2_ctrl *c; + + lockdep_assert_held(&asd->isp->mutex); + + /* + * In case of M10MO ZSL capture case, we need to issue a separate + * capture request to M10MO which will output captured jpeg image + */ + c = v4l2_ctrl_find( + asd->isp->inputs[asd->input_curr].camera->ctrl_handler, + V4L2_CID_START_ZSL_CAPTURE); + if (c) { + int ret; + + dev_dbg(asd->isp->dev, "%s trigger ZSL capture request\n", + __func__); + /* TODO: use the cvf_config */ + ret = v4l2_ctrl_s_ctrl(c, 1); + if (ret) + return ret; + + return v4l2_ctrl_s_ctrl(c, 0); + } + + asd->params.offline_parm = *cvf_config; + + if (asd->params.offline_parm.num_captures) { + if (asd->streaming == ATOMISP_DEVICE_STREAMING_DISABLED) { + unsigned int init_raw_num; + + if (asd->enable_raw_buffer_lock->val) { + init_raw_num = + ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES_LOCK_EN; + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + asd->params.video_dis_en) + init_raw_num += + ATOMISP_CSS2_NUM_DVS_FRAME_DELAY; + } else { + init_raw_num = + ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES; + } + + /* TODO: this can be removed once user-space + * has been updated to use control API */ + asd->continuous_raw_buffer_size->val = + max_t(int, + asd->continuous_raw_buffer_size->val, + asd->params.offline_parm. + num_captures + init_raw_num); + asd->continuous_raw_buffer_size->val = + min_t(int, ATOMISP_CONT_RAW_FRAMES, + asd->continuous_raw_buffer_size->val); + } + asd->continuous_mode->val = true; + } else { + asd->continuous_mode->val = false; + __enable_continuous_mode(asd, false); + } + + return 0; +} + +/* + * set auto exposure metering window to camera sensor + */ +int atomisp_s_ae_window(struct atomisp_sub_device *asd, + struct atomisp_ae_window *arg) +{ + struct atomisp_device *isp = asd->isp; + /* Coverity CID 298071 - initialzize struct */ + struct v4l2_subdev_selection sel = { 0 }; + + sel.r.left = arg->x_left; + sel.r.top = arg->y_top; + sel.r.width = arg->x_right - arg->x_left + 1; + sel.r.height = arg->y_bottom - arg->y_top + 1; + + if (v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + pad, set_selection, NULL, &sel)) { + dev_err(isp->dev, "failed to call sensor set_selection.\n"); + return -EINVAL; + } + + return 0; +} + +int atomisp_flash_enable(struct atomisp_sub_device *asd, int num_frames) +{ + struct atomisp_device *isp = asd->isp; + + if (num_frames < 0) { + dev_dbg(isp->dev, "%s ERROR: num_frames: %d\n", __func__, + num_frames); + return -EINVAL; + } + /* a requested flash is still in progress. */ + if (num_frames && asd->params.flash_state != ATOMISP_FLASH_IDLE) { + dev_dbg(isp->dev, "%s flash busy: %d frames left: %d\n", + __func__, asd->params.flash_state, + asd->params.num_flash_frames); + return -EBUSY; + } + + asd->params.num_flash_frames = num_frames; + asd->params.flash_state = ATOMISP_FLASH_REQUESTED; + return 0; +} + +bool atomisp_is_vf_pipe(struct atomisp_video_pipe *pipe) +{ + struct atomisp_sub_device *asd = pipe->asd; + + if (!asd) { + dev_err(pipe->isp->dev, "%s(): asd is NULL, device is %s\n", + __func__, pipe->vdev.name); + return false; + } + + if (pipe == &asd->video_out_vf) + return true; + + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + pipe == &asd->video_out_preview) + return true; + + return false; +} + +static int __checking_exp_id(struct atomisp_sub_device *asd, int exp_id) +{ + struct atomisp_device *isp = asd->isp; + + if (!asd->enable_raw_buffer_lock->val) { + dev_warn(isp->dev, "%s Raw Buffer Lock is disable.\n", __func__); + return -EINVAL; + } + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) { + dev_err(isp->dev, "%s streaming %d invalid exp_id %d.\n", + __func__, exp_id, asd->streaming); + return -EINVAL; + } + if ((exp_id > ATOMISP_MAX_EXP_ID) || (exp_id <= 0)) { + dev_err(isp->dev, "%s exp_id %d invalid.\n", __func__, exp_id); + return -EINVAL; + } + return 0; +} + +void atomisp_init_raw_buffer_bitmap(struct atomisp_sub_device *asd) +{ + unsigned long flags; + + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + memset(asd->raw_buffer_bitmap, 0, sizeof(asd->raw_buffer_bitmap)); + asd->raw_buffer_locked_count = 0; + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); +} + +static int atomisp_set_raw_buffer_bitmap(struct atomisp_sub_device *asd, int exp_id) +{ + int *bitmap, bit; + unsigned long flags; + + if (__checking_exp_id(asd, exp_id)) + return -EINVAL; + + bitmap = asd->raw_buffer_bitmap + exp_id / 32; + bit = exp_id % 32; + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + (*bitmap) |= (1 << bit); + asd->raw_buffer_locked_count++; + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); + + dev_dbg(asd->isp->dev, "%s: exp_id %d, raw_buffer_locked_count %d\n", + __func__, exp_id, asd->raw_buffer_locked_count); + + /* Check if the raw buffer after next is still locked!!! */ + exp_id += 2; + if (exp_id > ATOMISP_MAX_EXP_ID) + exp_id -= ATOMISP_MAX_EXP_ID; + bitmap = asd->raw_buffer_bitmap + exp_id / 32; + bit = exp_id % 32; + if ((*bitmap) & (1 << bit)) { + int ret; + + /* WORKAROUND unlock the raw buffer compulsively */ + ret = atomisp_css_exp_id_unlock(asd, exp_id); + if (ret) { + dev_err(asd->isp->dev, + "%s exp_id is wrapping back to %d but force unlock failed, err %d.\n", + __func__, exp_id, ret); + return ret; + } + + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + (*bitmap) &= ~(1 << bit); + asd->raw_buffer_locked_count--; + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); + dev_warn(asd->isp->dev, + "%s exp_id is wrapping back to %d but it is still locked so force unlock it, raw_buffer_locked_count %d\n", + __func__, exp_id, asd->raw_buffer_locked_count); + } + return 0; +} + +static int __is_raw_buffer_locked(struct atomisp_sub_device *asd, int exp_id) +{ + int *bitmap, bit; + unsigned long flags; + int ret; + + if (__checking_exp_id(asd, exp_id)) + return -EINVAL; + + bitmap = asd->raw_buffer_bitmap + exp_id / 32; + bit = exp_id % 32; + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + ret = ((*bitmap) & (1 << bit)); + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); + return !ret; +} + +static int __clear_raw_buffer_bitmap(struct atomisp_sub_device *asd, int exp_id) +{ + int *bitmap, bit; + unsigned long flags; + + if (__is_raw_buffer_locked(asd, exp_id)) + return -EINVAL; + + bitmap = asd->raw_buffer_bitmap + exp_id / 32; + bit = exp_id % 32; + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + (*bitmap) &= ~(1 << bit); + asd->raw_buffer_locked_count--; + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); + + dev_dbg(asd->isp->dev, "%s: exp_id %d, raw_buffer_locked_count %d\n", + __func__, exp_id, asd->raw_buffer_locked_count); + return 0; +} + +int atomisp_exp_id_capture(struct atomisp_sub_device *asd, int *exp_id) +{ + struct atomisp_device *isp = asd->isp; + int value = *exp_id; + int ret; + + lockdep_assert_held(&isp->mutex); + + ret = __is_raw_buffer_locked(asd, value); + if (ret) { + dev_err(isp->dev, "%s exp_id %d invalid %d.\n", __func__, value, ret); + return -EINVAL; + } + + dev_dbg(isp->dev, "%s exp_id %d\n", __func__, value); + ret = atomisp_css_exp_id_capture(asd, value); + if (ret) { + dev_err(isp->dev, "%s exp_id %d failed.\n", __func__, value); + return -EIO; + } + return 0; +} + +int atomisp_exp_id_unlock(struct atomisp_sub_device *asd, int *exp_id) +{ + struct atomisp_device *isp = asd->isp; + int value = *exp_id; + int ret; + + lockdep_assert_held(&isp->mutex); + + ret = __clear_raw_buffer_bitmap(asd, value); + if (ret) { + dev_err(isp->dev, "%s exp_id %d invalid %d.\n", __func__, value, ret); + return -EINVAL; + } + + dev_dbg(isp->dev, "%s exp_id %d\n", __func__, value); + ret = atomisp_css_exp_id_unlock(asd, value); + if (ret) + dev_err(isp->dev, "%s exp_id %d failed, err %d.\n", + __func__, value, ret); + + return ret; +} + +int atomisp_enable_dz_capt_pipe(struct atomisp_sub_device *asd, + unsigned int *enable) +{ + bool value; + + if (!enable) + return -EINVAL; + + value = *enable > 0; + + atomisp_en_dz_capt_pipe(asd, value); + + return 0; +} + +int atomisp_inject_a_fake_event(struct atomisp_sub_device *asd, int *event) +{ + if (!event || asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + return -EINVAL; + + lockdep_assert_held(&asd->isp->mutex); + + dev_dbg(asd->isp->dev, "%s: trying to inject a fake event 0x%x\n", + __func__, *event); + + switch (*event) { + case V4L2_EVENT_FRAME_SYNC: + atomisp_sof_event(asd); + break; + case V4L2_EVENT_FRAME_END: + atomisp_eof_event(asd, 0); + break; + case V4L2_EVENT_ATOMISP_3A_STATS_READY: + atomisp_3a_stats_ready_event(asd, 0); + break; + case V4L2_EVENT_ATOMISP_METADATA_READY: + atomisp_metadata_ready_event(asd, 0); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int atomisp_get_pipe_id(struct atomisp_video_pipe *pipe) +{ + struct atomisp_sub_device *asd = pipe->asd; + + if (!asd) { + dev_err(pipe->isp->dev, "%s(): asd is NULL, device is %s\n", + __func__, pipe->vdev.name); + return -EINVAL; + } + + if (ATOMISP_USE_YUVPP(asd)) { + return IA_CSS_PIPE_ID_YUVPP; + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + return IA_CSS_PIPE_ID_VIDEO; + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + return IA_CSS_PIPE_ID_CAPTURE; + } else if (pipe == &asd->video_out_video_capture) { + return IA_CSS_PIPE_ID_VIDEO; + } else if (pipe == &asd->video_out_vf) { + return IA_CSS_PIPE_ID_CAPTURE; + } else if (pipe == &asd->video_out_preview) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + return IA_CSS_PIPE_ID_VIDEO; + else + return IA_CSS_PIPE_ID_PREVIEW; + } else if (pipe == &asd->video_out_capture) { + if (asd->copy_mode) + return IA_CSS_PIPE_ID_COPY; + else + return IA_CSS_PIPE_ID_CAPTURE; + } + + /* fail through */ + dev_warn(asd->isp->dev, "%s failed to find proper pipe\n", + __func__); + return IA_CSS_PIPE_ID_CAPTURE; +} + +int atomisp_get_invalid_frame_num(struct video_device *vdev, + int *invalid_frame_num) +{ + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + enum ia_css_pipe_id pipe_id; + struct ia_css_pipe_info p_info; + int ret; + + pipe_id = atomisp_get_pipe_id(pipe); + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].pipes[pipe_id]) { + dev_warn(asd->isp->dev, + "%s pipe %d has not been created yet, do SET_FMT first!\n", + __func__, pipe_id); + return -EINVAL; + } + + ret = ia_css_pipe_get_info( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipes[pipe_id], &p_info); + if (!ret) { + *invalid_frame_num = p_info.num_invalid_frames; + return 0; + } else { + dev_warn(asd->isp->dev, "%s get pipe infor failed %d\n", + __func__, ret); + return -EINVAL; + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp_cmd.h b/drivers/staging/media/atomisp/pci/atomisp_cmd.h new file mode 100644 index 000000000..b89114915 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_cmd.h @@ -0,0 +1,344 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_CMD_H__ +#define __ATOMISP_CMD_H__ + +#include "../../include/linux/atomisp.h" +#include +#include + +#include + +#include "atomisp_internal.h" + +#include "ia_css_types.h" +#include "ia_css.h" + +struct atomisp_device; +struct ia_css_frame; + +#define MSI_ENABLE_BIT 16 +#define INTR_DISABLE_BIT 10 +#define BUS_MASTER_ENABLE 2 +#define MEMORY_SPACE_ENABLE 1 +#define INTR_IER 24 +#define INTR_IIR 16 + +/* ISP2401 */ +#define RUNMODE_MASK (ATOMISP_RUN_MODE_VIDEO | ATOMISP_RUN_MODE_STILL_CAPTURE \ + | ATOMISP_RUN_MODE_PREVIEW) + +/* FIXME: check if can go */ +extern int atomisp_punit_hpll_freq; + +/* Helper function */ +void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr, + unsigned int size); +struct camera_mipi_info *atomisp_to_sensor_mipi_info(struct v4l2_subdev *sd); +struct atomisp_video_pipe *atomisp_to_video_pipe(struct video_device *dev); +int atomisp_reset(struct atomisp_device *isp); +int atomisp_buffers_in_css(struct atomisp_video_pipe *pipe); +void atomisp_buffer_done(struct ia_css_frame *frame, enum vb2_buffer_state state); +void atomisp_flush_video_pipe(struct atomisp_video_pipe *pipe, bool warn_on_css_frames); +void atomisp_flush_bufs_and_wakeup(struct atomisp_sub_device *asd); +void atomisp_clear_css_buffer_counters(struct atomisp_sub_device *asd); + +/* Interrupt functions */ +void atomisp_msi_irq_init(struct atomisp_device *isp); +void atomisp_msi_irq_uninit(struct atomisp_device *isp); +void atomisp_assert_recovery_work(struct work_struct *work); +void atomisp_setup_flash(struct atomisp_sub_device *asd); +irqreturn_t atomisp_isr(int irq, void *dev); +irqreturn_t atomisp_isr_thread(int irq, void *isp_ptr); +const struct atomisp_format_bridge *get_atomisp_format_bridge_from_mbus( + u32 mbus_code); +bool atomisp_is_mbuscode_raw(uint32_t code); +void atomisp_delayed_init_work(struct work_struct *work); + +/* Get internal fmt according to V4L2 fmt */ +bool atomisp_is_viewfinder_support(struct atomisp_device *isp); + +/* ISP features control function */ + +/* + * Function to set sensor runmode by user when + * ATOMISP_IOC_S_SENSOR_RUNMODE ioctl was called + */ +int atomisp_set_sensor_runmode(struct atomisp_sub_device *asd, + struct atomisp_s_runmode *runmode); +/* + * Function to enable/disable lens geometry distortion correction (GDC) and + * chromatic aberration correction (CAC) + */ +int atomisp_gdc_cac(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* Function to enable/disable low light mode (including ANR) */ +int atomisp_low_light(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* + * Function to enable/disable extra noise reduction (XNR) in low light + * condition + */ +int atomisp_xnr(struct atomisp_sub_device *asd, int flag, int *arg); + +int atomisp_formats(struct atomisp_sub_device *asd, int flag, + struct atomisp_formats_config *config); + +/* Function to configure noise reduction */ +int atomisp_nr(struct atomisp_sub_device *asd, int flag, + struct atomisp_nr_config *config); + +/* Function to configure temporal noise reduction (TNR) */ +int atomisp_tnr(struct atomisp_sub_device *asd, int flag, + struct atomisp_tnr_config *config); + +/* Function to configure black level compensation */ +int atomisp_black_level(struct atomisp_sub_device *asd, int flag, + struct atomisp_ob_config *config); + +/* Function to configure edge enhancement */ +int atomisp_ee(struct atomisp_sub_device *asd, int flag, + struct atomisp_ee_config *config); + +/* Function to update Gamma table for gamma, brightness and contrast config */ +int atomisp_gamma(struct atomisp_sub_device *asd, int flag, + struct atomisp_gamma_table *config); + +/* Function to update Ctc table for Chroma Enhancement */ +int atomisp_ctc(struct atomisp_sub_device *asd, int flag, + struct atomisp_ctc_table *config); + +/* Function to update gamma correction parameters */ +int atomisp_gamma_correction(struct atomisp_sub_device *asd, int flag, + struct atomisp_gc_config *config); + +/* Function to update Gdc table for gdc */ +int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag, + struct atomisp_morph_table *config); + +/* Function to update table for macc */ +int atomisp_macc_table(struct atomisp_sub_device *asd, int flag, + struct atomisp_macc_config *config); + +/* Function to get DIS statistics. */ +int atomisp_get_dis_stat(struct atomisp_sub_device *asd, + struct atomisp_dis_statistics *stats); + +/* Function to get DVS2 BQ resolution settings */ +int atomisp_get_dvs2_bq_resolutions(struct atomisp_sub_device *asd, + struct atomisp_dvs2_bq_resolutions *bq_res); + +/* Function to set the DIS coefficients. */ +int atomisp_set_dis_coefs(struct atomisp_sub_device *asd, + struct atomisp_dis_coefficients *coefs); + +/* Function to set the DIS motion vector. */ +int atomisp_set_dis_vector(struct atomisp_sub_device *asd, + struct atomisp_dis_vector *vector); + +/* Function to set/get 3A stat from isp */ +int atomisp_3a_stat(struct atomisp_sub_device *asd, int flag, + struct atomisp_3a_statistics *config); + +/* Function to get metadata from isp */ +int atomisp_get_metadata(struct atomisp_sub_device *asd, int flag, + struct atomisp_metadata *config); + +int atomisp_get_metadata_by_type(struct atomisp_sub_device *asd, int flag, + struct atomisp_metadata_with_type *config); + +int atomisp_set_parameters(struct video_device *vdev, + struct atomisp_parameters *arg); + +/* Function to set/get isp parameters to isp */ +int atomisp_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_parm *config); + +/* Function to configure color effect of the image */ +int atomisp_color_effect(struct atomisp_sub_device *asd, int flag, + __s32 *effect); + +/* Function to configure bad pixel correction */ +int atomisp_bad_pixel(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* Function to configure bad pixel correction params */ +int atomisp_bad_pixel_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_dp_config *config); + +/* Function to enable/disable video image stablization */ +int atomisp_video_stable(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* Function to configure fixed pattern noise */ +int atomisp_fixed_pattern(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* Function to configure fixed pattern noise table */ +int atomisp_fixed_pattern_table(struct atomisp_sub_device *asd, + struct v4l2_framebuffer *config); + +/* Function to configure false color correction */ +int atomisp_false_color(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* Function to configure false color correction params */ +int atomisp_false_color_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_de_config *config); + +/* Function to configure white balance params */ +int atomisp_white_balance_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_wb_config *config); + +int atomisp_3a_config_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_3a_config *config); + +/* Function to setup digital zoom */ +int atomisp_digital_zoom(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* Function set camera_prefiles.xml current sensor pixel array size */ +int atomisp_set_array_res(struct atomisp_sub_device *asd, + struct atomisp_resolution *config); + +/* Function to calculate real zoom region for every pipe */ +int atomisp_calculate_real_zoom_region(struct atomisp_sub_device *asd, + struct ia_css_dz_config *dz_config, + enum ia_css_pipe_id css_pipe_id); + +int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd, + struct atomisp_parameters *arg, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_cp_lsc_table(struct atomisp_sub_device *asd, + struct atomisp_shading_table *source_st, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd, + struct ia_css_dvs2_coefficients *coefs, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_cp_morph_table(struct atomisp_sub_device *asd, + struct atomisp_morph_table *source_morph_table, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_cp_dvs_6axis_config(struct atomisp_sub_device *asd, + struct atomisp_dvs_6axis_config *user_6axis_config, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_makeup_css_parameters(struct atomisp_sub_device *asd, + struct atomisp_parameters *arg, + struct atomisp_css_params *css_param); + +int atomisp_compare_grid(struct atomisp_sub_device *asd, + struct atomisp_grid_info *atomgrid); + +int atomisp_get_sensor_mode_data(struct atomisp_sub_device *asd, + struct atomisp_sensor_mode_data *config); + +/* This function looks up the closest available resolution. */ +int atomisp_try_fmt(struct video_device *vdev, struct v4l2_pix_format *f, + bool *res_overflow); + +int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f); + +int atomisp_set_shading_table(struct atomisp_sub_device *asd, + struct atomisp_shading_table *shading_table); + +int atomisp_offline_capture_configure(struct atomisp_sub_device *asd, + struct atomisp_cont_capture_conf *cvf_config); + +int atomisp_exif_makernote(struct atomisp_sub_device *asd, + struct atomisp_makernote_info *config); + +void atomisp_free_internal_buffers(struct atomisp_sub_device *asd); + +int atomisp_s_ae_window(struct atomisp_sub_device *asd, + struct atomisp_ae_window *arg); + +int atomisp_flash_enable(struct atomisp_sub_device *asd, + int num_frames); + +int atomisp_freq_scaling(struct atomisp_device *vdev, + enum atomisp_dfs_mode mode, + bool force); + +void atomisp_buf_done(struct atomisp_sub_device *asd, int error, + enum ia_css_buffer_type buf_type, + enum ia_css_pipe_id css_pipe_id, + bool q_buffers, enum atomisp_input_stream_id stream_id); + +void atomisp_css_flush(struct atomisp_device *isp); + +/* Events. Only one event has to be exported for now. */ +void atomisp_eof_event(struct atomisp_sub_device *asd, uint8_t exp_id); + +enum mipi_port_id __get_mipi_port(struct atomisp_device *isp, + enum atomisp_camera_port port); + +bool atomisp_is_vf_pipe(struct atomisp_video_pipe *pipe); + +void atomisp_apply_css_parameters( + struct atomisp_sub_device *asd, + struct atomisp_css_params *css_param); +void atomisp_free_css_parameters(struct atomisp_css_params *css_param); + +void atomisp_handle_parameter_and_buffer(struct atomisp_video_pipe *pipe); + +void atomisp_flush_params_queue(struct atomisp_video_pipe *asd); + +/* Function to do Raw Buffer related operation, after enable Lock Unlock Raw Buffer */ +int atomisp_exp_id_unlock(struct atomisp_sub_device *asd, int *exp_id); +int atomisp_exp_id_capture(struct atomisp_sub_device *asd, int *exp_id); + +void atomisp_init_raw_buffer_bitmap(struct atomisp_sub_device *asd); + +/* Function to enable/disable zoom for capture pipe */ +int atomisp_enable_dz_capt_pipe(struct atomisp_sub_device *asd, + unsigned int *enable); + +/* Function to get metadata type bu pipe id */ +enum atomisp_metadata_type +atomisp_get_metadata_type(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id); + +u32 atomisp_get_pixel_depth(u32 pixelformat); + +/* Function for HAL to inject a fake event to wake up poll thread */ +int atomisp_inject_a_fake_event(struct atomisp_sub_device *asd, int *event); + +/* + * Function for HAL to query how many invalid frames at the beginning of ISP + * pipeline output + */ +int atomisp_get_invalid_frame_num(struct video_device *vdev, + int *invalid_frame_num); + +int atomisp_power_off(struct device *dev); +int atomisp_power_on(struct device *dev); +#endif /* __ATOMISP_CMD_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_common.h b/drivers/staging/media/atomisp/pci/atomisp_common.h new file mode 100644 index 000000000..07c38e487 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_common.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_COMMON_H__ +#define __ATOMISP_COMMON_H__ + +#include "../../include/linux/atomisp.h" + +#include + +#include + +#include "atomisp_compat.h" + +#include "ia_css.h" + +extern int dbg_level; +extern int dbg_func; +extern int mipicsi_flag; +extern int pad_w; +extern int pad_h; + +#define CSS_DTRACE_VERBOSITY_LEVEL 5 /* Controls trace verbosity */ +#define CSS_DTRACE_VERBOSITY_TIMEOUT 9 /* Verbosity on ISP timeout */ +#define MRFLD_MAX_ZOOM_FACTOR 1024 + +/* ISP2401 */ +#define ATOMISP_CSS_ISP_PIPE_VERSION_2_7 1 + +struct atomisp_format_bridge { + unsigned int pixelformat; + unsigned int depth; + u32 mbus_code; + enum ia_css_frame_format sh_fmt; + unsigned char description[32]; /* the same as struct v4l2_fmtdesc */ + bool planar; +}; + +struct atomisp_fmt { + u32 pixelformat; + u32 depth; + u32 bytesperline; + u32 framesize; + u32 imagesize; + u32 width; + u32 height; + u32 bayer_order; +}; + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp_compat.h b/drivers/staging/media/atomisp/pci/atomisp_compat.h new file mode 100644 index 000000000..7316eb9f9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_compat.h @@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Clovertrail PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_COMPAT_H__ +#define __ATOMISP_COMPAT_H__ + +#include "atomisp_compat_css20.h" + +#include "../../include/linux/atomisp.h" + +struct atomisp_device; +struct atomisp_sub_device; +struct video_device; +enum atomisp_input_stream_id; + +struct atomisp_metadata_buf { + struct ia_css_metadata *metadata; + void *md_vptr; + struct list_head list; +}; + +void atomisp_css2_hw_store_32(hrt_address addr, uint32_t data); +void atomisp_load_uint32(hrt_address addr, uint32_t *data); + +int atomisp_css_init(struct atomisp_device *isp); + +void atomisp_css_uninit(struct atomisp_device *isp); + +void atomisp_css_init_struct(struct atomisp_sub_device *asd); + +int atomisp_css_irq_translate(struct atomisp_device *isp, + unsigned int *infos); + +void atomisp_css_rx_get_irq_info(enum mipi_port_id port, + unsigned int *infos); + +void atomisp_css_rx_clear_irq_info(enum mipi_port_id port, + unsigned int infos); + +int atomisp_css_irq_enable(struct atomisp_device *isp, + enum ia_css_irq_info info, bool enable); + +int atomisp_q_video_buffer_to_css(struct atomisp_sub_device *asd, + struct ia_css_frame *frame, + enum atomisp_input_stream_id stream_id, + enum ia_css_buffer_type css_buf_type, + enum ia_css_pipe_id css_pipe_id); + +int atomisp_q_s3a_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_s3a_buf *s3a_buf, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id); + +int atomisp_q_metadata_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_metadata_buf *metadata_buf, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id); + +int atomisp_q_dis_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_dis_buf *dis_buf, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id); + +void ia_css_mmu_invalidate_cache(void); + +int atomisp_css_start(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id, bool in_reset); + +void atomisp_css_update_isp_params(struct atomisp_sub_device *asd); +void atomisp_css_update_isp_params_on_pipe(struct atomisp_sub_device *asd, + struct ia_css_pipe *pipe); + +int atomisp_css_queue_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id pipe_id, + enum ia_css_buffer_type buf_type, + struct atomisp_css_buffer *isp_css_buffer); + +int atomisp_css_dequeue_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id pipe_id, + enum ia_css_buffer_type buf_type, + struct atomisp_css_buffer *isp_css_buffer); + +int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd, + u16 stream_id, + struct atomisp_s3a_buf *s3a_buf, + struct atomisp_dis_buf *dis_buf, + struct atomisp_metadata_buf *md_buf); + +void atomisp_css_free_stat_buffers(struct atomisp_sub_device *asd); + +void atomisp_css_free_3a_buffer(struct atomisp_s3a_buf *s3a_buf); + +void atomisp_css_free_dis_buffer(struct atomisp_dis_buf *dis_buf); + +void atomisp_css_free_metadata_buffer(struct atomisp_metadata_buf + *metadata_buf); + +int atomisp_css_get_grid_info(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id, + int source_pad); + +int atomisp_alloc_3a_output_buf(struct atomisp_sub_device *asd); + +int atomisp_alloc_dis_coef_buf(struct atomisp_sub_device *asd); + +int atomisp_alloc_metadata_output_buf(struct atomisp_sub_device *asd); + +void atomisp_free_metadata_output_buf(struct atomisp_sub_device *asd); + +void atomisp_css_temp_pipe_to_pipe_id(struct atomisp_sub_device *asd, + struct atomisp_css_event *current_event); + +int atomisp_css_isys_set_resolution(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt, + int isys_stream); + +void atomisp_css_isys_set_link(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + int link, + int isys_stream); + +void atomisp_css_isys_set_valid(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + bool valid, + int isys_stream); + +void atomisp_css_isys_set_format(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format format, + int isys_stream); + +int atomisp_css_set_default_isys_config(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt); + +int atomisp_css_isys_two_stream_cfg(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format input_format); + +void atomisp_css_isys_two_stream_cfg_update_stream1( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format input_format, + unsigned int width, unsigned int height); + +void atomisp_css_isys_two_stream_cfg_update_stream2( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format input_format, + unsigned int width, unsigned int height); + +int atomisp_css_input_set_resolution(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt); + +void atomisp_css_input_set_binning_factor(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + unsigned int bin_factor); + +void atomisp_css_input_set_bayer_order(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_bayer_order bayer_order); + +void atomisp_css_input_set_format(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format format); + +int atomisp_css_input_set_effective_resolution( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + unsigned int width, + unsigned int height); + +void atomisp_css_video_set_dis_envelope(struct atomisp_sub_device *asd, + unsigned int dvs_w, unsigned int dvs_h); + +void atomisp_css_input_set_two_pixels_per_clock( + struct atomisp_sub_device *asd, + bool two_ppc); + +void atomisp_css_enable_raw_binning(struct atomisp_sub_device *asd, + bool enable); + +void atomisp_css_enable_dz(struct atomisp_sub_device *asd, bool enable); + +void atomisp_css_capture_set_mode(struct atomisp_sub_device *asd, + enum ia_css_capture_mode mode); + +void atomisp_css_input_set_mode(struct atomisp_sub_device *asd, + enum ia_css_input_mode mode); + +void atomisp_css_capture_enable_online(struct atomisp_sub_device *asd, + unsigned short stream_index, bool enable); + +void atomisp_css_preview_enable_online(struct atomisp_sub_device *asd, + unsigned short stream_index, bool enable); + +void atomisp_css_video_enable_online(struct atomisp_sub_device *asd, + bool enable); + +void atomisp_css_enable_continuous(struct atomisp_sub_device *asd, + bool enable); + +void atomisp_css_enable_cvf(struct atomisp_sub_device *asd, + bool enable); + +int atomisp_css_input_configure_port(struct atomisp_sub_device *asd, + enum mipi_port_id port, + unsigned int num_lanes, + unsigned int timeout, + unsigned int mipi_freq, + enum atomisp_input_format metadata_format, + unsigned int metadata_width, + unsigned int metadata_height); + +int atomisp_create_pipes_stream(struct atomisp_sub_device *asd); +void atomisp_destroy_pipes_stream_force(struct atomisp_sub_device *asd); + +void atomisp_css_stop(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id, bool in_reset); + +void atomisp_css_continuous_set_num_raw_frames( + struct atomisp_sub_device *asd, + int num_frames); + +int atomisp_css_copy_configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int padded_width, + enum ia_css_frame_format format); + +int atomisp_css_yuvpp_configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int padded_width, + enum ia_css_frame_format format); + +int atomisp_css_yuvpp_get_output_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct ia_css_frame_info *info); + +int atomisp_css_yuvpp_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct ia_css_frame_info *info); + +int atomisp_css_preview_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format); + +int atomisp_css_capture_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format); + +int atomisp_css_video_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format); + +int atomisp_get_css_frame_info(struct atomisp_sub_device *asd, + u16 source_pad, + struct ia_css_frame_info *frame_info); + +int atomisp_css_video_configure_viewfinder(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format); + +int atomisp_css_capture_configure_viewfinder( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format); + +int atomisp_css_video_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info); + +int atomisp_css_capture_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info); + +int atomisp_css_copy_get_output_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct ia_css_frame_info *info); + +int atomisp_css_capture_get_output_raw_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info); + +int atomisp_css_preview_get_output_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info); + +int atomisp_css_capture_get_output_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info); + +int atomisp_css_video_get_output_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info); + +int atomisp_css_preview_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height); + +int atomisp_css_capture_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height); + +int atomisp_css_video_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height); + +int atomisp_css_offline_capture_configure(struct atomisp_sub_device *asd, + int num_captures, unsigned int skip, int offset); +int atomisp_css_exp_id_capture(struct atomisp_sub_device *asd, int exp_id); +int atomisp_css_exp_id_unlock(struct atomisp_sub_device *asd, int exp_id); + +int atomisp_css_capture_enable_xnr(struct atomisp_sub_device *asd, + bool enable); + +void atomisp_css_set_ctc_table(struct atomisp_sub_device *asd, + struct ia_css_ctc_table *ctc_table); + +void atomisp_css_video_set_dis_vector(struct atomisp_sub_device *asd, + struct atomisp_dis_vector *vector); + +void atomisp_css_set_dvs2_coefs(struct atomisp_sub_device *asd, + struct ia_css_dvs2_coefficients *coefs); + +int atomisp_css_set_dis_coefs(struct atomisp_sub_device *asd, + struct atomisp_dis_coefficients *coefs); + +void atomisp_css_set_zoom_factor(struct atomisp_sub_device *asd, + unsigned int zoom); + +int atomisp_css_get_wb_config(struct atomisp_sub_device *asd, + struct atomisp_wb_config *config); + +int atomisp_css_get_ob_config(struct atomisp_sub_device *asd, + struct atomisp_ob_config *config); + +int atomisp_css_get_dp_config(struct atomisp_sub_device *asd, + struct atomisp_dp_config *config); + +int atomisp_css_get_de_config(struct atomisp_sub_device *asd, + struct atomisp_de_config *config); + +int atomisp_css_get_nr_config(struct atomisp_sub_device *asd, + struct atomisp_nr_config *config); + +int atomisp_css_get_ee_config(struct atomisp_sub_device *asd, + struct atomisp_ee_config *config); + +int atomisp_css_get_tnr_config(struct atomisp_sub_device *asd, + struct atomisp_tnr_config *config); + +int atomisp_css_get_ctc_table(struct atomisp_sub_device *asd, + struct atomisp_ctc_table *config); + +int atomisp_css_get_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_gamma_table *config); + +int atomisp_css_get_gc_config(struct atomisp_sub_device *asd, + struct atomisp_gc_config *config); + +int atomisp_css_get_3a_config(struct atomisp_sub_device *asd, + struct atomisp_3a_config *config); + +int atomisp_css_get_formats_config(struct atomisp_sub_device *asd, + struct atomisp_formats_config *formats_config); + +void atomisp_css_set_formats_config(struct atomisp_sub_device *asd, + struct ia_css_formats_config *formats_config); + +int atomisp_css_get_zoom_factor(struct atomisp_sub_device *asd, + unsigned int *zoom); + +struct ia_css_shading_table *atomisp_css_shading_table_alloc( + unsigned int width, unsigned int height); + +void atomisp_css_set_shading_table(struct atomisp_sub_device *asd, + struct ia_css_shading_table *table); + +void atomisp_css_shading_table_free(struct ia_css_shading_table *table); + +struct ia_css_morph_table *atomisp_css_morph_table_allocate( + unsigned int width, unsigned int height); + +void atomisp_css_set_morph_table(struct atomisp_sub_device *asd, + struct ia_css_morph_table *table); + +void atomisp_css_get_morph_table(struct atomisp_sub_device *asd, + struct ia_css_morph_table *table); + +void atomisp_css_morph_table_free(struct ia_css_morph_table *table); + +int atomisp_css_get_dis_stat(struct atomisp_sub_device *asd, + struct atomisp_dis_statistics *stats); + +int atomisp_css_update_stream(struct atomisp_sub_device *asd); + +int atomisp_css_isr_thread(struct atomisp_device *isp, + bool *frame_done_found, + bool *css_pipe_done); + +bool atomisp_css_valid_sof(struct atomisp_device *isp); + +void atomisp_en_dz_capt_pipe(struct atomisp_sub_device *asd, bool enable); + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp_compat_css20.c b/drivers/staging/media/atomisp/pci/atomisp_compat_css20.c new file mode 100644 index 000000000..61e2e63a0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_compat_css20.c @@ -0,0 +1,3932 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Clovertrail PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include + +#include "mmu/isp_mmu.h" +#include "mmu/sh_mmu_mrfld.h" +#include "hmm/hmm_bo.h" +#include "hmm/hmm.h" + +#include "atomisp_compat.h" +#include "atomisp_internal.h" +#include "atomisp_cmd.h" +#include "atomisp-regs.h" +#include "atomisp_fops.h" +#include "atomisp_ioctl.h" + +#include "ia_css_debug.h" +#include "ia_css_isp_param.h" +#include "sh_css_hrt.h" +#include "ia_css_isys.h" + +#include +#include + +/* Assume max number of ACC stages */ +#define MAX_ACC_STAGES 20 + +/* Ideally, this should come from CSS headers */ +#define NO_LINK -1 + +/* + * to serialize MMIO access , this is due to ISP2400 silicon issue Sighting + * #4684168, if concurrency access happened, system may hard hang. + */ +static DEFINE_SPINLOCK(mmio_lock); + +enum frame_info_type { + ATOMISP_CSS_VF_FRAME, + ATOMISP_CSS_SECOND_VF_FRAME, + ATOMISP_CSS_OUTPUT_FRAME, + ATOMISP_CSS_SECOND_OUTPUT_FRAME, + ATOMISP_CSS_RAW_FRAME, +}; + +struct bayer_ds_factor { + unsigned int numerator; + unsigned int denominator; +}; + +static void atomisp_css2_hw_store_8(hrt_address addr, uint8_t data) +{ + struct atomisp_device *isp = dev_get_drvdata(atomisp_dev); + unsigned long flags; + + spin_lock_irqsave(&mmio_lock, flags); + writeb(data, isp->base + (addr & 0x003FFFFF)); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static void atomisp_css2_hw_store_16(hrt_address addr, uint16_t data) +{ + struct atomisp_device *isp = dev_get_drvdata(atomisp_dev); + unsigned long flags; + + spin_lock_irqsave(&mmio_lock, flags); + writew(data, isp->base + (addr & 0x003FFFFF)); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +void atomisp_css2_hw_store_32(hrt_address addr, uint32_t data) +{ + struct atomisp_device *isp = dev_get_drvdata(atomisp_dev); + unsigned long flags; + + spin_lock_irqsave(&mmio_lock, flags); + writel(data, isp->base + (addr & 0x003FFFFF)); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static uint8_t atomisp_css2_hw_load_8(hrt_address addr) +{ + struct atomisp_device *isp = dev_get_drvdata(atomisp_dev); + unsigned long flags; + u8 ret; + + spin_lock_irqsave(&mmio_lock, flags); + ret = readb(isp->base + (addr & 0x003FFFFF)); + spin_unlock_irqrestore(&mmio_lock, flags); + return ret; +} + +static uint16_t atomisp_css2_hw_load_16(hrt_address addr) +{ + struct atomisp_device *isp = dev_get_drvdata(atomisp_dev); + unsigned long flags; + u16 ret; + + spin_lock_irqsave(&mmio_lock, flags); + ret = readw(isp->base + (addr & 0x003FFFFF)); + spin_unlock_irqrestore(&mmio_lock, flags); + return ret; +} + +static uint32_t atomisp_css2_hw_load_32(hrt_address addr) +{ + struct atomisp_device *isp = dev_get_drvdata(atomisp_dev); + unsigned long flags; + u32 ret; + + spin_lock_irqsave(&mmio_lock, flags); + ret = readl(isp->base + (addr & 0x003FFFFF)); + spin_unlock_irqrestore(&mmio_lock, flags); + return ret; +} + +static void atomisp_css2_hw_store(hrt_address addr, const void *from, uint32_t n) +{ + struct atomisp_device *isp = dev_get_drvdata(atomisp_dev); + unsigned long flags; + unsigned int i; + + addr &= 0x003FFFFF; + spin_lock_irqsave(&mmio_lock, flags); + for (i = 0; i < n; i++, from++) + writeb(*(s8 *)from, isp->base + addr + i); + + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static void atomisp_css2_hw_load(hrt_address addr, void *to, uint32_t n) +{ + struct atomisp_device *isp = dev_get_drvdata(atomisp_dev); + unsigned long flags; + unsigned int i; + + addr &= 0x003FFFFF; + spin_lock_irqsave(&mmio_lock, flags); + for (i = 0; i < n; i++, to++) + *(s8 *)to = readb(isp->base + addr + i); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static int __printf(1, 0) atomisp_css2_dbg_ftrace_print(const char *fmt, + va_list args) +{ + ftrace_vprintk(fmt, args); + return 0; +} + +static int __printf(1, 0) atomisp_vprintk(const char *fmt, va_list args) +{ + vprintk(fmt, args); + return 0; +} + +void atomisp_load_uint32(hrt_address addr, uint32_t *data) +{ + *data = atomisp_css2_hw_load_32(addr); +} + +static int hmm_get_mmu_base_addr(struct device *dev, unsigned int *mmu_base_addr) +{ + if (!sh_mmu_mrfld.get_pd_base) { + dev_err(dev, "get mmu base address failed.\n"); + return -EINVAL; + } + + *mmu_base_addr = sh_mmu_mrfld.get_pd_base(&bo_device.mmu, + bo_device.mmu.base_address); + return 0; +} + +static void __dump_pipe_config(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env, + unsigned int pipe_id) +{ + struct atomisp_device *isp = asd->isp; + + if (stream_env->pipes[pipe_id]) { + struct ia_css_pipe_config *p_config; + struct ia_css_pipe_extra_config *pe_config; + + p_config = &stream_env->pipe_configs[pipe_id]; + pe_config = &stream_env->pipe_extra_configs[pipe_id]; + dev_dbg(isp->dev, "dumping pipe[%d] config:\n", pipe_id); + dev_dbg(isp->dev, + "pipe_config.pipe_mode:%d.\n", p_config->mode); + dev_dbg(isp->dev, + "pipe_config.output_info[0] w=%d, h=%d.\n", + p_config->output_info[0].res.width, + p_config->output_info[0].res.height); + dev_dbg(isp->dev, + "pipe_config.vf_pp_in_res w=%d, h=%d.\n", + p_config->vf_pp_in_res.width, + p_config->vf_pp_in_res.height); + dev_dbg(isp->dev, + "pipe_config.capt_pp_in_res w=%d, h=%d.\n", + p_config->capt_pp_in_res.width, + p_config->capt_pp_in_res.height); + dev_dbg(isp->dev, + "pipe_config.output.padded w=%d.\n", + p_config->output_info[0].padded_width); + dev_dbg(isp->dev, + "pipe_config.vf_output_info[0] w=%d, h=%d.\n", + p_config->vf_output_info[0].res.width, + p_config->vf_output_info[0].res.height); + dev_dbg(isp->dev, + "pipe_config.bayer_ds_out_res w=%d, h=%d.\n", + p_config->bayer_ds_out_res.width, + p_config->bayer_ds_out_res.height); + dev_dbg(isp->dev, + "pipe_config.envelope w=%d, h=%d.\n", + p_config->dvs_envelope.width, + p_config->dvs_envelope.height); + dev_dbg(isp->dev, + "pipe_config.dvs_frame_delay=%d.\n", + p_config->dvs_frame_delay); + dev_dbg(isp->dev, + "pipe_config.isp_pipe_version:%d.\n", + p_config->isp_pipe_version); + dev_dbg(isp->dev, + "pipe_config.default_capture_config.capture_mode=%d.\n", + p_config->default_capture_config.mode); + dev_dbg(isp->dev, + "pipe_config.enable_dz=%d.\n", + p_config->enable_dz); + dev_dbg(isp->dev, + "pipe_config.default_capture_config.enable_xnr=%d.\n", + p_config->default_capture_config.enable_xnr); + dev_dbg(isp->dev, + "dumping pipe[%d] extra config:\n", pipe_id); + dev_dbg(isp->dev, + "pipe_extra_config.enable_raw_binning:%d.\n", + pe_config->enable_raw_binning); + dev_dbg(isp->dev, + "pipe_extra_config.enable_yuv_ds:%d.\n", + pe_config->enable_yuv_ds); + dev_dbg(isp->dev, + "pipe_extra_config.enable_high_speed:%d.\n", + pe_config->enable_high_speed); + dev_dbg(isp->dev, + "pipe_extra_config.enable_dvs_6axis:%d.\n", + pe_config->enable_dvs_6axis); + dev_dbg(isp->dev, + "pipe_extra_config.enable_reduced_pipe:%d.\n", + pe_config->enable_reduced_pipe); + dev_dbg(isp->dev, + "pipe_(extra_)config.enable_dz:%d.\n", + p_config->enable_dz); + dev_dbg(isp->dev, + "pipe_extra_config.disable_vf_pp:%d.\n", + pe_config->disable_vf_pp); + } +} + +static void __dump_stream_config(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_stream_config *s_config; + int j; + bool valid_stream = false; + + for (j = 0; j < IA_CSS_PIPE_ID_NUM; j++) { + if (stream_env->pipes[j]) { + __dump_pipe_config(asd, stream_env, j); + valid_stream = true; + } + } + if (!valid_stream) + return; + s_config = &stream_env->stream_config; + dev_dbg(isp->dev, "stream_config.mode=%d.\n", s_config->mode); + + if (s_config->mode == IA_CSS_INPUT_MODE_SENSOR || + s_config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + dev_dbg(isp->dev, "stream_config.source.port.port=%d.\n", + s_config->source.port.port); + dev_dbg(isp->dev, "stream_config.source.port.num_lanes=%d.\n", + s_config->source.port.num_lanes); + dev_dbg(isp->dev, "stream_config.source.port.timeout=%d.\n", + s_config->source.port.timeout); + dev_dbg(isp->dev, "stream_config.source.port.rxcount=0x%x.\n", + s_config->source.port.rxcount); + dev_dbg(isp->dev, "stream_config.source.port.compression.type=%d.\n", + s_config->source.port.compression.type); + dev_dbg(isp->dev, + "stream_config.source.port.compression.compressed_bits_per_pixel=%d.\n", + s_config->source.port.compression. + compressed_bits_per_pixel); + dev_dbg(isp->dev, + "stream_config.source.port.compression.uncompressed_bits_per_pixel=%d.\n", + s_config->source.port.compression. + uncompressed_bits_per_pixel); + } else if (s_config->mode == IA_CSS_INPUT_MODE_TPG) { + dev_dbg(isp->dev, "stream_config.source.tpg.id=%d.\n", + s_config->source.tpg.id); + dev_dbg(isp->dev, "stream_config.source.tpg.mode=%d.\n", + s_config->source.tpg.mode); + dev_dbg(isp->dev, "stream_config.source.tpg.x_mask=%d.\n", + s_config->source.tpg.x_mask); + dev_dbg(isp->dev, "stream_config.source.tpg.x_delta=%d.\n", + s_config->source.tpg.x_delta); + dev_dbg(isp->dev, "stream_config.source.tpg.y_mask=%d.\n", + s_config->source.tpg.y_mask); + dev_dbg(isp->dev, "stream_config.source.tpg.y_delta=%d.\n", + s_config->source.tpg.y_delta); + dev_dbg(isp->dev, "stream_config.source.tpg.xy_mask=%d.\n", + s_config->source.tpg.xy_mask); + } else if (s_config->mode == IA_CSS_INPUT_MODE_PRBS) { + dev_dbg(isp->dev, "stream_config.source.prbs.id=%d.\n", + s_config->source.prbs.id); + dev_dbg(isp->dev, "stream_config.source.prbs.h_blank=%d.\n", + s_config->source.prbs.h_blank); + dev_dbg(isp->dev, "stream_config.source.prbs.v_blank=%d.\n", + s_config->source.prbs.v_blank); + dev_dbg(isp->dev, "stream_config.source.prbs.seed=%d.\n", + s_config->source.prbs.seed); + dev_dbg(isp->dev, "stream_config.source.prbs.seed1=%d.\n", + s_config->source.prbs.seed1); + } + + for (j = 0; j < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; j++) { + dev_dbg(isp->dev, "stream_configisys_config[%d].input_res w=%d, h=%d.\n", + j, + s_config->isys_config[j].input_res.width, + s_config->isys_config[j].input_res.height); + + dev_dbg(isp->dev, "stream_configisys_config[%d].linked_isys_stream_id=%d\n", + j, + s_config->isys_config[j].linked_isys_stream_id); + + dev_dbg(isp->dev, "stream_configisys_config[%d].format=%d\n", + j, + s_config->isys_config[j].format); + + dev_dbg(isp->dev, "stream_configisys_config[%d].valid=%d.\n", + j, + s_config->isys_config[j].valid); + } + + dev_dbg(isp->dev, "stream_config.input_config.input_res w=%d, h=%d.\n", + s_config->input_config.input_res.width, + s_config->input_config.input_res.height); + + dev_dbg(isp->dev, "stream_config.input_config.effective_res w=%d, h=%d.\n", + s_config->input_config.effective_res.width, + s_config->input_config.effective_res.height); + + dev_dbg(isp->dev, "stream_config.input_config.format=%d\n", + s_config->input_config.format); + + dev_dbg(isp->dev, "stream_config.input_config.bayer_order=%d.\n", + s_config->input_config.bayer_order); + + dev_dbg(isp->dev, "stream_config.pixels_per_clock=%d.\n", + s_config->pixels_per_clock); + dev_dbg(isp->dev, "stream_config.online=%d.\n", s_config->online); + dev_dbg(isp->dev, "stream_config.continuous=%d.\n", + s_config->continuous); + dev_dbg(isp->dev, "stream_config.disable_cont_viewfinder=%d.\n", + s_config->disable_cont_viewfinder); + dev_dbg(isp->dev, "stream_config.channel_id=%d.\n", + s_config->channel_id); + dev_dbg(isp->dev, "stream_config.init_num_cont_raw_buf=%d.\n", + s_config->init_num_cont_raw_buf); + dev_dbg(isp->dev, "stream_config.target_num_cont_raw_buf=%d.\n", + s_config->target_num_cont_raw_buf); + dev_dbg(isp->dev, "stream_config.left_padding=%d.\n", + s_config->left_padding); + dev_dbg(isp->dev, "stream_config.sensor_binning_factor=%d.\n", + s_config->sensor_binning_factor); + dev_dbg(isp->dev, "stream_config.pixels_per_clock=%d.\n", + s_config->pixels_per_clock); + dev_dbg(isp->dev, "stream_config.pack_raw_pixels=%d.\n", + s_config->pack_raw_pixels); + dev_dbg(isp->dev, "stream_config.flash_gpio_pin=%d.\n", + s_config->flash_gpio_pin); + dev_dbg(isp->dev, "stream_config.mipi_buffer_config.size_mem_words=%d.\n", + s_config->mipi_buffer_config.size_mem_words); + dev_dbg(isp->dev, "stream_config.mipi_buffer_config.contiguous=%d.\n", + s_config->mipi_buffer_config.contiguous); + dev_dbg(isp->dev, "stream_config.metadata_config.data_type=%d.\n", + s_config->metadata_config.data_type); + dev_dbg(isp->dev, "stream_config.metadata_config.resolution w=%d, h=%d.\n", + s_config->metadata_config.resolution.width, + s_config->metadata_config.resolution.height); +} + +static int __destroy_stream(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env) +{ + struct atomisp_device *isp = asd->isp; + unsigned long timeout; + + if (!stream_env->stream) + return 0; + + if (stream_env->stream_state == CSS_STREAM_STARTED + && ia_css_stream_stop(stream_env->stream) != 0) { + dev_err(isp->dev, "stop stream failed.\n"); + return -EINVAL; + } + + if (stream_env->stream_state == CSS_STREAM_STARTED) { + timeout = jiffies + msecs_to_jiffies(40); + while (1) { + if (ia_css_stream_has_stopped(stream_env->stream)) + break; + + if (time_after(jiffies, timeout)) { + dev_warn(isp->dev, "stop stream timeout.\n"); + break; + } + + usleep_range(100, 200); + } + } + + stream_env->stream_state = CSS_STREAM_STOPPED; + + if (ia_css_stream_destroy(stream_env->stream)) { + dev_err(isp->dev, "destroy stream failed.\n"); + return -EINVAL; + } + stream_env->stream_state = CSS_STREAM_UNINIT; + stream_env->stream = NULL; + + return 0; +} + +static int __destroy_streams(struct atomisp_sub_device *asd) +{ + int ret, i; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + ret = __destroy_stream(asd, &asd->stream_env[i]); + if (ret) + return ret; + } + asd->stream_prepared = false; + return 0; +} + +static int __create_stream(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env) +{ + int pipe_index = 0, i; + struct ia_css_pipe *multi_pipes[IA_CSS_PIPE_ID_NUM]; + + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + if (stream_env->pipes[i]) + multi_pipes[pipe_index++] = stream_env->pipes[i]; + } + if (pipe_index == 0) + return 0; + + stream_env->stream_config.target_num_cont_raw_buf = + asd->continuous_raw_buffer_size->val; + stream_env->stream_config.channel_id = stream_env->ch_id; + stream_env->stream_config.ia_css_enable_raw_buffer_locking = + asd->enable_raw_buffer_lock->val; + + __dump_stream_config(asd, stream_env); + if (ia_css_stream_create(&stream_env->stream_config, + pipe_index, multi_pipes, &stream_env->stream) != 0) + return -EINVAL; + if (ia_css_stream_get_info(stream_env->stream, + &stream_env->stream_info) != 0) { + ia_css_stream_destroy(stream_env->stream); + stream_env->stream = NULL; + return -EINVAL; + } + + stream_env->stream_state = CSS_STREAM_CREATED; + return 0; +} + +static int __create_streams(struct atomisp_sub_device *asd) +{ + int ret, i; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + ret = __create_stream(asd, &asd->stream_env[i]); + if (ret) + goto rollback; + } + asd->stream_prepared = true; + return 0; +rollback: + for (i--; i >= 0; i--) + __destroy_stream(asd, &asd->stream_env[i]); + return ret; +} + +static int __destroy_stream_pipes(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env) +{ + struct atomisp_device *isp = asd->isp; + int ret = 0; + int i; + + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + if (!stream_env->pipes[i]) + continue; + if (ia_css_pipe_destroy(stream_env->pipes[i]) + != 0) { + dev_err(isp->dev, + "destroy pipe[%d]failed.cannot recover.\n", i); + ret = -EINVAL; + } + stream_env->pipes[i] = NULL; + stream_env->update_pipe[i] = false; + } + return ret; +} + +static int __destroy_pipes(struct atomisp_sub_device *asd) +{ + struct atomisp_device *isp = asd->isp; + int i; + int ret = 0; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + if (asd->stream_env[i].stream) { + dev_err(isp->dev, + "cannot destroy css pipes for stream[%d].\n", + i); + continue; + } + + ret = __destroy_stream_pipes(asd, &asd->stream_env[i]); + if (ret) + return ret; + } + + return 0; +} + +void atomisp_destroy_pipes_stream_force(struct atomisp_sub_device *asd) +{ + if (__destroy_streams(asd)) + dev_warn(asd->isp->dev, "destroy stream failed.\n"); + + if (__destroy_pipes(asd)) + dev_warn(asd->isp->dev, "destroy pipe failed.\n"); +} + +static void __apply_additional_pipe_config( + struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + + if (pipe_id < 0 || pipe_id >= IA_CSS_PIPE_ID_NUM) { + dev_err(isp->dev, + "wrong pipe_id for additional pipe config.\n"); + return; + } + + /* apply default pipe config */ + stream_env->pipe_configs[pipe_id].isp_pipe_version = 2; + stream_env->pipe_configs[pipe_id].enable_dz = + asd->disable_dz->val ? false : true; + /* apply isp 2.2 specific config for baytrail*/ + switch (pipe_id) { + case IA_CSS_PIPE_ID_CAPTURE: + /* enable capture pp/dz manually or digital zoom would + * fail*/ + if (stream_env->pipe_configs[pipe_id]. + default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW) + stream_env->pipe_configs[pipe_id].enable_dz = false; + break; + case IA_CSS_PIPE_ID_VIDEO: + /* enable reduced pipe to have binary + * video_dz_2_min selected*/ + stream_env->pipe_extra_configs[pipe_id] + .enable_reduced_pipe = true; + stream_env->pipe_configs[pipe_id] + .enable_dz = false; + if (ATOMISP_SOC_CAMERA(asd)) + stream_env->pipe_configs[pipe_id].enable_dz = true; + + if (asd->params.video_dis_en) { + stream_env->pipe_extra_configs[pipe_id] + .enable_dvs_6axis = true; + stream_env->pipe_configs[pipe_id] + .dvs_frame_delay = + ATOMISP_CSS2_NUM_DVS_FRAME_DELAY; + } + break; + case IA_CSS_PIPE_ID_PREVIEW: + break; + case IA_CSS_PIPE_ID_YUVPP: + case IA_CSS_PIPE_ID_COPY: + if (ATOMISP_SOC_CAMERA(asd)) + stream_env->pipe_configs[pipe_id].enable_dz = true; + else + stream_env->pipe_configs[pipe_id].enable_dz = false; + break; + default: + break; + } +} + +static bool is_pipe_valid_to_current_run_mode(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id) +{ + if (!asd) + return false; + + if (pipe_id == IA_CSS_PIPE_ID_YUVPP) + return true; + + if (asd->vfpp) { + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + if (pipe_id == IA_CSS_PIPE_ID_VIDEO) + return true; + else + return false; + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) + return true; + else + return false; + } + } + + if (!asd->run_mode) + return false; + + if (asd->copy_mode && pipe_id == IA_CSS_PIPE_ID_COPY) + return true; + + switch (asd->run_mode->val) { + case ATOMISP_RUN_MODE_STILL_CAPTURE: + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) + return true; + + return false; + case ATOMISP_RUN_MODE_PREVIEW: + if (!asd->continuous_mode->val) { + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) + return true; + + return false; + } + fallthrough; + case ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE: + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE || + pipe_id == IA_CSS_PIPE_ID_PREVIEW) + return true; + + return false; + case ATOMISP_RUN_MODE_VIDEO: + if (!asd->continuous_mode->val) { + if (pipe_id == IA_CSS_PIPE_ID_VIDEO || + pipe_id == IA_CSS_PIPE_ID_YUVPP) + return true; + else + return false; + } + fallthrough; + case ATOMISP_RUN_MODE_SDV: + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE || + pipe_id == IA_CSS_PIPE_ID_VIDEO) + return true; + + return false; + } + + return false; +} + +static int __create_pipe(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_pipe_extra_config extra_config; + int ret; + + if (pipe_id >= IA_CSS_PIPE_ID_NUM) + return -EINVAL; + + if (!stream_env->pipe_configs[pipe_id].output_info[0].res.width) + return 0; + + if (!is_pipe_valid_to_current_run_mode(asd, pipe_id)) + return 0; + + ia_css_pipe_extra_config_defaults(&extra_config); + + __apply_additional_pipe_config(asd, stream_env, pipe_id); + if (!memcmp(&extra_config, + &stream_env->pipe_extra_configs[pipe_id], + sizeof(extra_config))) + ret = ia_css_pipe_create( + &stream_env->pipe_configs[pipe_id], + &stream_env->pipes[pipe_id]); + else + ret = ia_css_pipe_create_extra( + &stream_env->pipe_configs[pipe_id], + &stream_env->pipe_extra_configs[pipe_id], + &stream_env->pipes[pipe_id]); + if (ret) + dev_err(isp->dev, "create pipe[%d] error.\n", pipe_id); + return ret; +} + +static int __create_pipes(struct atomisp_sub_device *asd) +{ + int ret; + int i, j; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + for (j = 0; j < IA_CSS_PIPE_ID_NUM; j++) { + ret = __create_pipe(asd, &asd->stream_env[i], j); + if (ret) + break; + } + if (j < IA_CSS_PIPE_ID_NUM) + goto pipe_err; + } + return 0; +pipe_err: + for (; i >= 0; i--) { + for (j--; j >= 0; j--) { + if (asd->stream_env[i].pipes[j]) { + ia_css_pipe_destroy(asd->stream_env[i].pipes[j]); + asd->stream_env[i].pipes[j] = NULL; + } + } + j = IA_CSS_PIPE_ID_NUM; + } + return -EINVAL; +} + +int atomisp_create_pipes_stream(struct atomisp_sub_device *asd) +{ + int ret; + + ret = __create_pipes(asd); + if (ret) { + dev_err(asd->isp->dev, "create pipe failed %d.\n", ret); + return ret; + } + + ret = __create_streams(asd); + if (ret) { + dev_warn(asd->isp->dev, "create stream failed %d.\n", ret); + __destroy_pipes(asd); + return ret; + } + + return 0; +} + +int atomisp_css_update_stream(struct atomisp_sub_device *asd) +{ + atomisp_destroy_pipes_stream_force(asd); + return atomisp_create_pipes_stream(asd); +} + +int atomisp_css_init(struct atomisp_device *isp) +{ + unsigned int mmu_base_addr; + int ret; + int err; + + ret = hmm_get_mmu_base_addr(isp->dev, &mmu_base_addr); + if (ret) + return ret; + + /* Init ISP */ + err = ia_css_init(isp->dev, &isp->css_env.isp_css_env, NULL, + (uint32_t)mmu_base_addr, IA_CSS_IRQ_TYPE_PULSE); + if (err) { + dev_err(isp->dev, "css init failed --- bad firmware?\n"); + return -EINVAL; + } + ia_css_enable_isys_event_queue(true); + + isp->css_initialized = true; + dev_dbg(isp->dev, "sh_css_init success\n"); + + return 0; +} + +static inline int __set_css_print_env(struct atomisp_device *isp, int opt) +{ + int ret = 0; + + if (opt == 0) + isp->css_env.isp_css_env.print_env.debug_print = NULL; + else if (opt == 1) + isp->css_env.isp_css_env.print_env.debug_print = + atomisp_css2_dbg_ftrace_print; + else if (opt == 2) + isp->css_env.isp_css_env.print_env.debug_print = atomisp_vprintk; + else + ret = -EINVAL; + + return ret; +} + +int atomisp_css_load_firmware(struct atomisp_device *isp) +{ + int err; + + /* set css env */ + isp->css_env.isp_css_fw.data = (void *)isp->firmware->data; + isp->css_env.isp_css_fw.bytes = isp->firmware->size; + + isp->css_env.isp_css_env.hw_access_env.store_8 = + atomisp_css2_hw_store_8; + isp->css_env.isp_css_env.hw_access_env.store_16 = + atomisp_css2_hw_store_16; + isp->css_env.isp_css_env.hw_access_env.store_32 = + atomisp_css2_hw_store_32; + + isp->css_env.isp_css_env.hw_access_env.load_8 = atomisp_css2_hw_load_8; + isp->css_env.isp_css_env.hw_access_env.load_16 = + atomisp_css2_hw_load_16; + isp->css_env.isp_css_env.hw_access_env.load_32 = + atomisp_css2_hw_load_32; + + isp->css_env.isp_css_env.hw_access_env.load = atomisp_css2_hw_load; + isp->css_env.isp_css_env.hw_access_env.store = atomisp_css2_hw_store; + + __set_css_print_env(isp, dbg_func); + + isp->css_env.isp_css_env.print_env.error_print = atomisp_vprintk; + + /* load isp fw into ISP memory */ + err = ia_css_load_firmware(isp->dev, &isp->css_env.isp_css_env, + &isp->css_env.isp_css_fw); + if (err) { + dev_err(isp->dev, "css load fw failed.\n"); + return -EINVAL; + } + + return 0; +} + +void atomisp_css_uninit(struct atomisp_device *isp) +{ + isp->css_initialized = false; + ia_css_uninit(); +} + +int atomisp_css_irq_translate(struct atomisp_device *isp, + unsigned int *infos) +{ + int err; + + err = ia_css_irq_translate(infos); + if (err) { + dev_warn(isp->dev, + "%s:failed to translate irq (err = %d,infos = %d)\n", + __func__, err, *infos); + return -EINVAL; + } + + return 0; +} + +void atomisp_css_rx_get_irq_info(enum mipi_port_id port, + unsigned int *infos) +{ +#ifndef ISP2401 + ia_css_isys_rx_get_irq_info(port, infos); +#else + *infos = 0; +#endif +} + +void atomisp_css_rx_clear_irq_info(enum mipi_port_id port, + unsigned int infos) +{ +#ifndef ISP2401 + ia_css_isys_rx_clear_irq_info(port, infos); +#endif +} + +int atomisp_css_irq_enable(struct atomisp_device *isp, + enum ia_css_irq_info info, bool enable) +{ + dev_dbg(isp->dev, "%s: css irq info 0x%08x: %s (%d).\n", + __func__, info, + enable ? "enable" : "disable", enable); + if (ia_css_irq_enable(info, enable)) { + dev_warn(isp->dev, "%s:Invalid irq info: 0x%08x when %s.\n", + __func__, info, + enable ? "enabling" : "disabling"); + return -EINVAL; + } + + return 0; +} + +void atomisp_css_init_struct(struct atomisp_sub_device *asd) +{ + int i, j; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + asd->stream_env[i].stream = NULL; + for (j = 0; j < IA_CSS_PIPE_MODE_NUM; j++) { + asd->stream_env[i].pipes[j] = NULL; + asd->stream_env[i].update_pipe[j] = false; + ia_css_pipe_config_defaults( + &asd->stream_env[i].pipe_configs[j]); + ia_css_pipe_extra_config_defaults( + &asd->stream_env[i].pipe_extra_configs[j]); + } + ia_css_stream_config_defaults(&asd->stream_env[i].stream_config); + } +} + +int atomisp_q_video_buffer_to_css(struct atomisp_sub_device *asd, + struct ia_css_frame *frame, + enum atomisp_input_stream_id stream_id, + enum ia_css_buffer_type css_buf_type, + enum ia_css_pipe_id css_pipe_id) +{ + struct atomisp_stream_env *stream_env = &asd->stream_env[stream_id]; + struct ia_css_buffer css_buf = {0}; + int err; + + css_buf.type = css_buf_type; + css_buf.data.frame = frame; + + err = ia_css_pipe_enqueue_buffer( + stream_env->pipes[css_pipe_id], &css_buf); + if (err) + return -EINVAL; + + return 0; +} + +int atomisp_q_metadata_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_metadata_buf *metadata_buf, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id) +{ + struct atomisp_stream_env *stream_env = &asd->stream_env[stream_id]; + struct ia_css_buffer buffer = {0}; + struct atomisp_device *isp = asd->isp; + + buffer.type = IA_CSS_BUFFER_TYPE_METADATA; + buffer.data.metadata = metadata_buf->metadata; + if (ia_css_pipe_enqueue_buffer(stream_env->pipes[css_pipe_id], + &buffer)) { + dev_err(isp->dev, "failed to q meta data buffer\n"); + return -EINVAL; + } + + return 0; +} + +int atomisp_q_s3a_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_s3a_buf *s3a_buf, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id) +{ + struct atomisp_stream_env *stream_env = &asd->stream_env[stream_id]; + struct ia_css_buffer buffer = {0}; + struct atomisp_device *isp = asd->isp; + + buffer.type = IA_CSS_BUFFER_TYPE_3A_STATISTICS; + buffer.data.stats_3a = s3a_buf->s3a_data; + if (ia_css_pipe_enqueue_buffer( + stream_env->pipes[css_pipe_id], + &buffer)) { + dev_dbg(isp->dev, "failed to q s3a stat buffer\n"); + return -EINVAL; + } + + return 0; +} + +int atomisp_q_dis_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_dis_buf *dis_buf, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id) +{ + struct atomisp_stream_env *stream_env = &asd->stream_env[stream_id]; + struct ia_css_buffer buffer = {0}; + struct atomisp_device *isp = asd->isp; + + buffer.type = IA_CSS_BUFFER_TYPE_DIS_STATISTICS; + buffer.data.stats_dvs = dis_buf->dis_data; + if (ia_css_pipe_enqueue_buffer( + stream_env->pipes[css_pipe_id], + &buffer)) { + dev_dbg(isp->dev, "failed to q dvs stat buffer\n"); + return -EINVAL; + } + + return 0; +} + +int atomisp_css_start(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id, bool in_reset) +{ + struct atomisp_device *isp = asd->isp; + bool sp_is_started = false; + int ret = 0, i = 0; + + if (in_reset) { + ret = atomisp_css_update_stream(asd); + if (ret) + return ret; + + /* Invalidate caches. FIXME: should flush only necessary buffers */ + wbinvd(); + } + + /* + * For dual steam case, it is possible that: + * 1: for this stream, it is at the stage that: + * - after set_fmt is called + * - before stream on is called + * 2: for the other stream, the stream off is called which css reset + * has been done. + * + * Thus the stream created in set_fmt get destroyed and need to be + * recreated in the next stream on. + */ + if (!asd->stream_prepared) { + ret = atomisp_create_pipes_stream(asd); + if (ret) + return ret; + } + /* + * SP can only be started one time + * if atomisp_subdev_streaming_count() tell there already has some + * subdev at streamming, then SP should already be started previously, + * so need to skip start sp procedure + */ + if (atomisp_streaming_count(isp)) { + dev_dbg(isp->dev, "skip start sp\n"); + } else { + if (!sh_css_hrt_system_is_idle()) + dev_err(isp->dev, "CSS HW not idle before starting SP\n"); + if (ia_css_start_sp()) { + dev_err(isp->dev, "start sp error.\n"); + ret = -EINVAL; + goto start_err; + } else { + sp_is_started = true; + } + } + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + if (asd->stream_env[i].stream) { + if (ia_css_stream_start(asd->stream_env[i] + .stream) != 0) { + dev_err(isp->dev, "stream[%d] start error.\n", i); + ret = -EINVAL; + goto start_err; + } else { + asd->stream_env[i].stream_state = CSS_STREAM_STARTED; + dev_dbg(isp->dev, "stream[%d] started.\n", i); + } + } + } + + return 0; + +start_err: + atomisp_destroy_pipes_stream_force(asd); + + /* css 2.0 API limitation: ia_css_stop_sp() could be only called after + * destroy all pipes + */ + /* + * SP can not be stop if other streams are in use + */ + if ((atomisp_streaming_count(isp) == 0) && sp_is_started) + ia_css_stop_sp(); + + return ret; +} + +void atomisp_css_update_isp_params(struct atomisp_sub_device *asd) +{ + /* + * FIXME! + * for ISP2401 new input system, this api is under development. + * Calling it would cause kernel panic. + * + * VIED BZ: 1458 + * + * Check if it is Cherry Trail and also new input system + */ + if (asd->copy_mode) { + dev_warn(asd->isp->dev, + "%s: ia_css_stream_set_isp_config() not supported in copy mode!.\n", + __func__); + return; + } + + ia_css_stream_set_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &asd->params.config); + memset(&asd->params.config, 0, sizeof(asd->params.config)); +} + +void atomisp_css_update_isp_params_on_pipe(struct atomisp_sub_device *asd, + struct ia_css_pipe *pipe) +{ + int ret; + + if (!pipe) { + atomisp_css_update_isp_params(asd); + return; + } + + dev_dbg(asd->isp->dev, + "%s: apply parameter for ia_css_frame %p with isp_config_id %d on pipe %p.\n", + __func__, asd->params.config.output_frame, + asd->params.config.isp_config_id, pipe); + + ret = ia_css_stream_set_isp_config_on_pipe( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &asd->params.config, pipe); + if (ret) + dev_warn(asd->isp->dev, "%s: ia_css_stream_set_isp_config_on_pipe failed %d\n", + __func__, ret); + memset(&asd->params.config, 0, sizeof(asd->params.config)); +} + +int atomisp_css_queue_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id pipe_id, + enum ia_css_buffer_type buf_type, + struct atomisp_css_buffer *isp_css_buffer) +{ + if (ia_css_pipe_enqueue_buffer( + asd->stream_env[stream_id].pipes[pipe_id], + &isp_css_buffer->css_buffer) + != 0) + return -EINVAL; + + return 0; +} + +int atomisp_css_dequeue_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id pipe_id, + enum ia_css_buffer_type buf_type, + struct atomisp_css_buffer *isp_css_buffer) +{ + struct atomisp_device *isp = asd->isp; + int err; + + err = ia_css_pipe_dequeue_buffer( + asd->stream_env[stream_id].pipes[pipe_id], + &isp_css_buffer->css_buffer); + if (err) { + dev_err(isp->dev, + "ia_css_pipe_dequeue_buffer failed: 0x%x\n", err); + return -EINVAL; + } + + return 0; +} + +int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd, + u16 stream_id, + struct atomisp_s3a_buf *s3a_buf, + struct atomisp_dis_buf *dis_buf, + struct atomisp_metadata_buf *md_buf) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + + if (s3a_buf && asd->params.curr_grid_info.s3a_grid.enable) { + void *s3a_ptr; + + s3a_buf->s3a_data = ia_css_isp_3a_statistics_allocate( + &asd->params.curr_grid_info.s3a_grid); + if (!s3a_buf->s3a_data) { + dev_err(isp->dev, "3a buf allocation failed.\n"); + return -EINVAL; + } + + s3a_ptr = hmm_vmap(s3a_buf->s3a_data->data_ptr, true); + s3a_buf->s3a_map = ia_css_isp_3a_statistics_map_allocate( + s3a_buf->s3a_data, s3a_ptr); + } + + if (dis_buf && dvs_grid_info && dvs_grid_info->enable) { + void *dvs_ptr; + + dis_buf->dis_data = ia_css_isp_dvs2_statistics_allocate( + dvs_grid_info); + if (!dis_buf->dis_data) { + dev_err(isp->dev, "dvs buf allocation failed.\n"); + if (s3a_buf) + ia_css_isp_3a_statistics_free(s3a_buf->s3a_data); + return -EINVAL; + } + + dvs_ptr = hmm_vmap(dis_buf->dis_data->data_ptr, true); + dis_buf->dvs_map = ia_css_isp_dvs_statistics_map_allocate( + dis_buf->dis_data, dvs_ptr); + } + + if (asd->stream_env[stream_id].stream_info. + metadata_info.size && md_buf) { + md_buf->metadata = ia_css_metadata_allocate( + &asd->stream_env[stream_id].stream_info.metadata_info); + if (!md_buf->metadata) { + if (s3a_buf) + ia_css_isp_3a_statistics_free(s3a_buf->s3a_data); + if (dis_buf) + ia_css_isp_dvs2_statistics_free(dis_buf->dis_data); + dev_err(isp->dev, "metadata buf allocation failed.\n"); + return -EINVAL; + } + md_buf->md_vptr = hmm_vmap(md_buf->metadata->address, false); + } + + return 0; +} + +void atomisp_css_free_3a_buffer(struct atomisp_s3a_buf *s3a_buf) +{ + if (s3a_buf->s3a_data) + hmm_vunmap(s3a_buf->s3a_data->data_ptr); + + ia_css_isp_3a_statistics_map_free(s3a_buf->s3a_map); + s3a_buf->s3a_map = NULL; + ia_css_isp_3a_statistics_free(s3a_buf->s3a_data); +} + +void atomisp_css_free_dis_buffer(struct atomisp_dis_buf *dis_buf) +{ + if (dis_buf->dis_data) + hmm_vunmap(dis_buf->dis_data->data_ptr); + + ia_css_isp_dvs_statistics_map_free(dis_buf->dvs_map); + dis_buf->dvs_map = NULL; + ia_css_isp_dvs2_statistics_free(dis_buf->dis_data); +} + +void atomisp_css_free_metadata_buffer(struct atomisp_metadata_buf *metadata_buf) +{ + if (metadata_buf->md_vptr) { + hmm_vunmap(metadata_buf->metadata->address); + metadata_buf->md_vptr = NULL; + } + ia_css_metadata_free(metadata_buf->metadata); +} + +void atomisp_css_free_stat_buffers(struct atomisp_sub_device *asd) +{ + struct atomisp_s3a_buf *s3a_buf, *_s3a_buf; + struct atomisp_dis_buf *dis_buf, *_dis_buf; + struct atomisp_metadata_buf *md_buf, *_md_buf; + struct ia_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + unsigned int i; + + /* 3A statistics use vmalloc, DIS use kmalloc */ + if (dvs_grid_info && dvs_grid_info->enable) { + ia_css_dvs2_coefficients_free(asd->params.css_param.dvs2_coeff); + ia_css_dvs2_statistics_free(asd->params.dvs_stat); + asd->params.css_param.dvs2_coeff = NULL; + asd->params.dvs_stat = NULL; + asd->params.dvs_hor_proj_bytes = 0; + asd->params.dvs_ver_proj_bytes = 0; + asd->params.dvs_hor_coef_bytes = 0; + asd->params.dvs_ver_coef_bytes = 0; + asd->params.dis_proj_data_valid = false; + list_for_each_entry_safe(dis_buf, _dis_buf, + &asd->dis_stats, list) { + atomisp_css_free_dis_buffer(dis_buf); + list_del(&dis_buf->list); + kfree(dis_buf); + } + list_for_each_entry_safe(dis_buf, _dis_buf, + &asd->dis_stats_in_css, list) { + atomisp_css_free_dis_buffer(dis_buf); + list_del(&dis_buf->list); + kfree(dis_buf); + } + } + if (asd->params.curr_grid_info.s3a_grid.enable) { + ia_css_3a_statistics_free(asd->params.s3a_user_stat); + asd->params.s3a_user_stat = NULL; + asd->params.s3a_output_bytes = 0; + list_for_each_entry_safe(s3a_buf, _s3a_buf, + &asd->s3a_stats, list) { + atomisp_css_free_3a_buffer(s3a_buf); + list_del(&s3a_buf->list); + kfree(s3a_buf); + } + list_for_each_entry_safe(s3a_buf, _s3a_buf, + &asd->s3a_stats_in_css, list) { + atomisp_css_free_3a_buffer(s3a_buf); + list_del(&s3a_buf->list); + kfree(s3a_buf); + } + list_for_each_entry_safe(s3a_buf, _s3a_buf, + &asd->s3a_stats_ready, list) { + atomisp_css_free_3a_buffer(s3a_buf); + list_del(&s3a_buf->list); + kfree(s3a_buf); + } + } + + if (asd->params.css_param.dvs_6axis) { + ia_css_dvs2_6axis_config_free(asd->params.css_param.dvs_6axis); + asd->params.css_param.dvs_6axis = NULL; + } + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + list_for_each_entry_safe(md_buf, _md_buf, + &asd->metadata[i], list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + list_for_each_entry_safe(md_buf, _md_buf, + &asd->metadata_in_css[i], list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + list_for_each_entry_safe(md_buf, _md_buf, + &asd->metadata_ready[i], list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + } + asd->params.metadata_width_size = 0; + atomisp_free_metadata_output_buf(asd); +} + +int atomisp_css_get_grid_info(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id, + int source_pad) +{ + struct ia_css_pipe_info p_info; + struct ia_css_grid_info old_info; + struct atomisp_device *isp = asd->isp; + int md_width = asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_config.metadata_config.resolution.width; + + memset(&p_info, 0, sizeof(struct ia_css_pipe_info)); + memset(&old_info, 0, sizeof(struct ia_css_grid_info)); + + if (ia_css_pipe_get_info( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].pipes[pipe_id], + &p_info) != 0) { + dev_err(isp->dev, "ia_css_pipe_get_info failed\n"); + return -EINVAL; + } + + memcpy(&old_info, &asd->params.curr_grid_info, + sizeof(struct ia_css_grid_info)); + memcpy(&asd->params.curr_grid_info, &p_info.grid_info, + sizeof(struct ia_css_grid_info)); + /* + * Record which css pipe enables s3a_grid. + * Currently would have one css pipe that need it + */ + if (asd->params.curr_grid_info.s3a_grid.enable) { + if (asd->params.s3a_enabled_pipe != IA_CSS_PIPE_ID_NUM) + dev_dbg(isp->dev, "css pipe %d enabled s3a grid replaced by: %d.\n", + asd->params.s3a_enabled_pipe, pipe_id); + asd->params.s3a_enabled_pipe = pipe_id; + } + + /* If the grid info has not changed and the buffers for 3A and + * DIS statistics buffers are allocated or buffer size would be zero + * then no need to do anything. */ + if (((!memcmp(&old_info, &asd->params.curr_grid_info, sizeof(old_info)) + && asd->params.s3a_user_stat && asd->params.dvs_stat) + || asd->params.curr_grid_info.s3a_grid.width == 0 + || asd->params.curr_grid_info.s3a_grid.height == 0) + && asd->params.metadata_width_size == md_width) { + dev_dbg(isp->dev, + "grid info change escape. memcmp=%d, s3a_user_stat=%d,dvs_stat=%d, s3a.width=%d, s3a.height=%d, metadata width =%d\n", + !memcmp(&old_info, &asd->params.curr_grid_info, + sizeof(old_info)), + !!asd->params.s3a_user_stat, !!asd->params.dvs_stat, + asd->params.curr_grid_info.s3a_grid.width, + asd->params.curr_grid_info.s3a_grid.height, + asd->params.metadata_width_size); + return -EINVAL; + } + asd->params.metadata_width_size = md_width; + + return 0; +} + +int atomisp_alloc_3a_output_buf(struct atomisp_sub_device *asd) +{ + if (!asd->params.curr_grid_info.s3a_grid.width || + !asd->params.curr_grid_info.s3a_grid.height) + return 0; + + asd->params.s3a_user_stat = ia_css_3a_statistics_allocate( + &asd->params.curr_grid_info.s3a_grid); + if (!asd->params.s3a_user_stat) + return -ENOMEM; + /* 3A statistics. These can be big, so we use vmalloc. */ + asd->params.s3a_output_bytes = + asd->params.curr_grid_info.s3a_grid.width * + asd->params.curr_grid_info.s3a_grid.height * + sizeof(*asd->params.s3a_user_stat->data); + + return 0; +} + +int atomisp_alloc_dis_coef_buf(struct atomisp_sub_device *asd) +{ + struct ia_css_dvs_grid_info *dvs_grid = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + + if (!dvs_grid) + return 0; + + if (!dvs_grid->enable) { + dev_dbg(asd->isp->dev, "%s: dvs_grid not enabled.\n", __func__); + return 0; + } + + /* DIS coefficients. */ + asd->params.css_param.dvs2_coeff = ia_css_dvs2_coefficients_allocate( + dvs_grid); + if (!asd->params.css_param.dvs2_coeff) + return -ENOMEM; + + asd->params.dvs_hor_coef_bytes = dvs_grid->num_hor_coefs * + sizeof(*asd->params.css_param.dvs2_coeff->hor_coefs.odd_real); + + asd->params.dvs_ver_coef_bytes = dvs_grid->num_ver_coefs * + sizeof(*asd->params.css_param.dvs2_coeff->ver_coefs.odd_real); + + /* DIS projections. */ + asd->params.dis_proj_data_valid = false; + asd->params.dvs_stat = ia_css_dvs2_statistics_allocate(dvs_grid); + if (!asd->params.dvs_stat) + return -ENOMEM; + + asd->params.dvs_hor_proj_bytes = + dvs_grid->aligned_height * dvs_grid->aligned_width * + sizeof(*asd->params.dvs_stat->hor_prod.odd_real); + + asd->params.dvs_ver_proj_bytes = + dvs_grid->aligned_height * dvs_grid->aligned_width * + sizeof(*asd->params.dvs_stat->ver_prod.odd_real); + + return 0; +} + +int atomisp_alloc_metadata_output_buf(struct atomisp_sub_device *asd) +{ + int i; + + /* We allocate the cpu-side buffer used for communication with user + * space */ + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + asd->params.metadata_user[i] = kvmalloc( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_info.metadata_info.size, GFP_KERNEL); + if (!asd->params.metadata_user[i]) { + while (--i >= 0) { + kvfree(asd->params.metadata_user[i]); + asd->params.metadata_user[i] = NULL; + } + return -ENOMEM; + } + } + + return 0; +} + +void atomisp_free_metadata_output_buf(struct atomisp_sub_device *asd) +{ + unsigned int i; + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + if (asd->params.metadata_user[i]) { + kvfree(asd->params.metadata_user[i]); + asd->params.metadata_user[i] = NULL; + } + } +} + +void atomisp_css_temp_pipe_to_pipe_id(struct atomisp_sub_device *asd, + struct atomisp_css_event *current_event) +{ + /* + * FIXME! + * Pipe ID reported in CSS event is not correct for new system's + * copy pipe. + * VIED BZ: 1463 + */ + ia_css_temp_pipe_to_pipe_id(current_event->event.pipe, + ¤t_event->pipe); + if (asd && asd->copy_mode && + current_event->pipe == IA_CSS_PIPE_ID_CAPTURE) + current_event->pipe = IA_CSS_PIPE_ID_COPY; +} + +int atomisp_css_isys_set_resolution(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt, + int isys_stream) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + if (isys_stream >= IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH) + return -EINVAL; + + s_config->isys_config[isys_stream].input_res.width = ffmt->width; + s_config->isys_config[isys_stream].input_res.height = ffmt->height; + return 0; +} + +int atomisp_css_input_set_resolution(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->input_config.input_res.width = ffmt->width; + s_config->input_config.input_res.height = ffmt->height; + return 0; +} + +void atomisp_css_input_set_binning_factor(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + unsigned int bin_factor) +{ + asd->stream_env[stream_id] + .stream_config.sensor_binning_factor = bin_factor; +} + +void atomisp_css_input_set_bayer_order(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_bayer_order bayer_order) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + s_config->input_config.bayer_order = bayer_order; +} + +void atomisp_css_isys_set_link(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + int link, + int isys_stream) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[isys_stream].linked_isys_stream_id = link; +} + +void atomisp_css_isys_set_valid(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + bool valid, + int isys_stream) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[isys_stream].valid = valid; +} + +void atomisp_css_isys_set_format(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format format, + int isys_stream) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[isys_stream].format = format; +} + +void atomisp_css_input_set_format(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format format) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->input_config.format = format; +} + +int atomisp_css_set_default_isys_config(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt) +{ + int i; + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + /* + * Set all isys configs to not valid. + * Currently we support only one stream per channel + */ + for (i = IA_CSS_STREAM_ISYS_STREAM_0; + i < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; i++) + s_config->isys_config[i].valid = false; + + atomisp_css_isys_set_resolution(asd, stream_id, ffmt, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + atomisp_css_isys_set_format(asd, stream_id, + s_config->input_config.format, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + atomisp_css_isys_set_link(asd, stream_id, NO_LINK, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + atomisp_css_isys_set_valid(asd, stream_id, true, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + + return 0; +} + +int atomisp_css_isys_two_stream_cfg(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format input_format) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].input_res.width = + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].input_res.width; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].input_res.height = + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].input_res.height / 2; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].linked_isys_stream_id + = IA_CSS_STREAM_ISYS_STREAM_0; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].format = + ATOMISP_INPUT_FORMAT_USER_DEF1; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].format = + ATOMISP_INPUT_FORMAT_USER_DEF2; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].valid = true; + return 0; +} + +void atomisp_css_isys_two_stream_cfg_update_stream1( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format input_format, + unsigned int width, unsigned int height) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].input_res.width = + width; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].input_res.height = + height; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].format = + input_format; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].valid = true; +} + +void atomisp_css_isys_two_stream_cfg_update_stream2( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_input_format input_format, + unsigned int width, unsigned int height) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].input_res.width = + width; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].input_res.height = + height; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].linked_isys_stream_id + = IA_CSS_STREAM_ISYS_STREAM_0; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].format = + input_format; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].valid = true; +} + +int atomisp_css_input_set_effective_resolution( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + unsigned int width, unsigned int height) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + s_config->input_config.effective_res.width = width; + s_config->input_config.effective_res.height = height; + return 0; +} + +void atomisp_css_video_set_dis_envelope(struct atomisp_sub_device *asd, + unsigned int dvs_w, unsigned int dvs_h) +{ + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[IA_CSS_PIPE_ID_VIDEO].dvs_envelope.width = dvs_w; + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[IA_CSS_PIPE_ID_VIDEO].dvs_envelope.height = dvs_h; +} + +void atomisp_css_input_set_two_pixels_per_clock( + struct atomisp_sub_device *asd, + bool two_ppc) +{ + int i; + + if (asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.pixels_per_clock == (two_ppc ? 2 : 1)) + return; + + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.pixels_per_clock = (two_ppc ? 2 : 1); + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .update_pipe[i] = true; +} + +void atomisp_css_enable_raw_binning(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + unsigned int pipe; + + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + pipe = IA_CSS_PIPE_ID_VIDEO; + else + pipe = IA_CSS_PIPE_ID_PREVIEW; + + stream_env->pipe_extra_configs[pipe].enable_raw_binning = enable; + stream_env->update_pipe[pipe] = true; + if (enable) + stream_env->pipe_configs[pipe].output_info[0].padded_width = + stream_env->stream_config.input_config.effective_res.width; +} + +void atomisp_css_enable_dz(struct atomisp_sub_device *asd, bool enable) +{ + int i; + + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[i].enable_dz = enable; +} + +void atomisp_css_capture_set_mode(struct atomisp_sub_device *asd, + enum ia_css_capture_mode mode) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + + if (stream_env->pipe_configs[IA_CSS_PIPE_ID_CAPTURE] + .default_capture_config.mode == mode) + return; + + stream_env->pipe_configs[IA_CSS_PIPE_ID_CAPTURE]. + default_capture_config.mode = mode; + stream_env->update_pipe[IA_CSS_PIPE_ID_CAPTURE] = true; +} + +void atomisp_css_input_set_mode(struct atomisp_sub_device *asd, + enum ia_css_input_mode mode) +{ + int i; + struct atomisp_device *isp = asd->isp; + unsigned int size_mem_words; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) + asd->stream_env[i].stream_config.mode = mode; + + if (isp->inputs[asd->input_curr].type == TEST_PATTERN) { + struct ia_css_stream_config *s_config = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream_config; + s_config->mode = IA_CSS_INPUT_MODE_TPG; + s_config->source.tpg.mode = IA_CSS_TPG_MODE_CHECKERBOARD; + s_config->source.tpg.x_mask = (1 << 4) - 1; + s_config->source.tpg.x_delta = -2; + s_config->source.tpg.y_mask = (1 << 4) - 1; + s_config->source.tpg.y_delta = 3; + s_config->source.tpg.xy_mask = (1 << 8) - 1; + return; + } + + if (mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) + return; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + /* + * TODO: sensor needs to export the embedded_data_size_words + * information to atomisp for each setting. + * Here using a large safe value. + */ + struct ia_css_stream_config *s_config = + &asd->stream_env[i].stream_config; + + if (s_config->input_config.input_res.width == 0) + continue; + + if (ia_css_mipi_frame_calculate_size( + s_config->input_config.input_res.width, + s_config->input_config.input_res.height, + s_config->input_config.format, + true, + 0x13000, + &size_mem_words) != 0) { + if (IS_MRFD) + size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_2; + else + size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_1; + dev_warn(asd->isp->dev, + "ia_css_mipi_frame_calculate_size failed,applying pre-defined MIPI buffer size %u.\n", + size_mem_words); + } + s_config->mipi_buffer_config.size_mem_words = size_mem_words; + s_config->mipi_buffer_config.nof_mipi_buffers = 2; + } +} + +void atomisp_css_capture_enable_online(struct atomisp_sub_device *asd, + unsigned short stream_index, bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + + if (stream_env->stream_config.online == !!enable) + return; + + stream_env->stream_config.online = !!enable; + stream_env->update_pipe[IA_CSS_PIPE_ID_CAPTURE] = true; +} + +void atomisp_css_preview_enable_online(struct atomisp_sub_device *asd, + unsigned short stream_index, bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + int i; + + if (stream_env->stream_config.online != !!enable) { + stream_env->stream_config.online = !!enable; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + stream_env->update_pipe[i] = true; + } +} + +void atomisp_css_video_enable_online(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_VIDEO]; + int i; + + if (stream_env->stream_config.online != enable) { + stream_env->stream_config.online = enable; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + stream_env->update_pipe[i] = true; + } +} + +void atomisp_css_enable_continuous(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + int i; + + /* + * To SOC camera, there is only one YUVPP pipe in any case + * including ZSL/SDV/continuous viewfinder, so always set + * stream_config.continuous to 0. + */ + if (ATOMISP_USE_YUVPP(asd)) { + stream_env->stream_config.continuous = 0; + stream_env->stream_config.online = 1; + return; + } + + if (stream_env->stream_config.continuous != !!enable) { + stream_env->stream_config.continuous = !!enable; + stream_env->stream_config.pack_raw_pixels = true; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + stream_env->update_pipe[i] = true; + } +} + +void atomisp_css_enable_cvf(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + int i; + + if (stream_env->stream_config.disable_cont_viewfinder != !enable) { + stream_env->stream_config.disable_cont_viewfinder = !enable; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + stream_env->update_pipe[i] = true; + } +} + +int atomisp_css_input_configure_port( + struct atomisp_sub_device *asd, + enum mipi_port_id port, + unsigned int num_lanes, + unsigned int timeout, + unsigned int mipi_freq, + enum atomisp_input_format metadata_format, + unsigned int metadata_width, + unsigned int metadata_height) +{ + int i; + struct atomisp_stream_env *stream_env; + /* + * Calculate rx_count as follows: + * Input: mipi_freq : CSI-2 bus frequency in Hz + * UI = 1 / (2 * mipi_freq) : period of one bit on the bus + * min = 85e-9 + 6 * UI : Limits for rx_count in seconds + * max = 145e-9 + 10 * UI + * rxcount0 = min / (4 / mipi_freq) : convert seconds to byte clocks + * rxcount = rxcount0 - 2 : adjust for better results + * The formula below is simplified version of the above with + * 10-bit fixed points for improved accuracy. + */ + const unsigned int rxcount = + min(((mipi_freq / 46000) - 1280) >> 10, 0xffU) * 0x01010101U; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + stream_env = &asd->stream_env[i]; + stream_env->stream_config.source.port.port = port; + stream_env->stream_config.source.port.num_lanes = num_lanes; + stream_env->stream_config.source.port.timeout = timeout; + if (mipi_freq) + stream_env->stream_config.source.port.rxcount = rxcount; + stream_env->stream_config. + metadata_config.data_type = metadata_format; + stream_env->stream_config. + metadata_config.resolution.width = metadata_width; + stream_env->stream_config. + metadata_config.resolution.height = metadata_height; + } + + return 0; +} + +void atomisp_css_stop(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id, bool in_reset) +{ + struct atomisp_device *isp = asd->isp; + unsigned long irqflags; + unsigned int i; + + /* if is called in atomisp_reset(), force destroy streams and pipes */ + atomisp_destroy_pipes_stream_force(asd); + + atomisp_init_raw_buffer_bitmap(asd); + + /* + * SP can not be stop if other streams are in use + */ + if (atomisp_streaming_count(isp) == 0) + ia_css_stop_sp(); + + if (!in_reset) { + struct atomisp_stream_env *stream_env; + int i, j; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + stream_env = &asd->stream_env[i]; + for (j = 0; j < IA_CSS_PIPE_ID_NUM; j++) { + ia_css_pipe_config_defaults( + &stream_env->pipe_configs[j]); + ia_css_pipe_extra_config_defaults( + &stream_env->pipe_extra_configs[j]); + } + ia_css_stream_config_defaults( + &stream_env->stream_config); + } + memset(&asd->params.config, 0, sizeof(asd->params.config)); + asd->params.css_update_params_needed = false; + } + + /* move stats buffers to free queue list */ + list_splice_init(&asd->s3a_stats_in_css, &asd->s3a_stats); + list_splice_init(&asd->s3a_stats_ready, &asd->s3a_stats); + + spin_lock_irqsave(&asd->dis_stats_lock, irqflags); + list_splice_init(&asd->dis_stats_in_css, &asd->dis_stats); + asd->params.dis_proj_data_valid = false; + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + list_splice_init(&asd->metadata_in_css[i], &asd->metadata[i]); + list_splice_init(&asd->metadata_ready[i], &asd->metadata[i]); + } + + atomisp_flush_params_queue(&asd->video_out_capture); + atomisp_flush_params_queue(&asd->video_out_vf); + atomisp_flush_params_queue(&asd->video_out_preview); + atomisp_flush_params_queue(&asd->video_out_video_capture); + atomisp_free_css_parameters(&asd->params.css_param); + memset(&asd->params.css_param, 0, sizeof(asd->params.css_param)); +} + +void atomisp_css_continuous_set_num_raw_frames( + struct atomisp_sub_device *asd, + int num_frames) +{ + if (asd->enable_raw_buffer_lock->val) { + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.init_num_cont_raw_buf = + ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES_LOCK_EN; + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + asd->params.video_dis_en) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.init_num_cont_raw_buf += + ATOMISP_CSS2_NUM_DVS_FRAME_DELAY; + } else { + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.init_num_cont_raw_buf = + ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES; + } + + if (asd->params.video_dis_en) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.init_num_cont_raw_buf += + ATOMISP_CSS2_NUM_DVS_FRAME_DELAY; + + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.target_num_cont_raw_buf = num_frames; +} + +static enum ia_css_pipe_mode __pipe_id_to_pipe_mode( + struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct camera_mipi_info *mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + + switch (pipe_id) { + case IA_CSS_PIPE_ID_COPY: + /* Currently only YUVPP mode supports YUV420_Legacy format. + * Revert this when other pipe modes can support + * YUV420_Legacy format. + */ + if (mipi_info && mipi_info->input_format == + ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY) + return IA_CSS_PIPE_MODE_YUVPP; + return IA_CSS_PIPE_MODE_COPY; + case IA_CSS_PIPE_ID_PREVIEW: + return IA_CSS_PIPE_MODE_PREVIEW; + case IA_CSS_PIPE_ID_CAPTURE: + return IA_CSS_PIPE_MODE_CAPTURE; + case IA_CSS_PIPE_ID_VIDEO: + return IA_CSS_PIPE_MODE_VIDEO; + case IA_CSS_PIPE_ID_YUVPP: + return IA_CSS_PIPE_MODE_YUVPP; + default: + WARN_ON(1); + return IA_CSS_PIPE_MODE_PREVIEW; + } +} + +static void __configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + struct ia_css_stream_config *s_config = &stream_env->stream_config; + + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + stream_env->pipe_configs[pipe_id].output_info[0].res.width = width; + stream_env->pipe_configs[pipe_id].output_info[0].res.height = height; + stream_env->pipe_configs[pipe_id].output_info[0].format = format; + stream_env->pipe_configs[pipe_id].output_info[0].padded_width = min_width; + + /* isp binary 2.2 specific setting*/ + if (width > s_config->input_config.effective_res.width || + height > s_config->input_config.effective_res.height) { + s_config->input_config.effective_res.width = width; + s_config->input_config.effective_res.height = height; + } + + dev_dbg(isp->dev, "configuring pipe[%d] output info w=%d.h=%d.f=%d.\n", + pipe_id, width, height, format); +} + +static void __configure_video_preview_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + struct ia_css_frame_info *css_output_info; + struct ia_css_stream_config *stream_config = &stream_env->stream_config; + + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + /* + * second_output will be as video main output in SDV mode + * with SOC camera. output will be as video main output in + * normal video mode. + */ + if (asd->continuous_mode->val) + css_output_info = &stream_env->pipe_configs[pipe_id]. + output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + css_output_info = &stream_env->pipe_configs[pipe_id]. + output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + + css_output_info->res.width = width; + css_output_info->res.height = height; + css_output_info->format = format; + css_output_info->padded_width = min_width; + + /* isp binary 2.2 specific setting*/ + if (width > stream_config->input_config.effective_res.width || + height > stream_config->input_config.effective_res.height) { + stream_config->input_config.effective_res.width = width; + stream_config->input_config.effective_res.height = height; + } + + dev_dbg(isp->dev, "configuring pipe[%d] output info w=%d.h=%d.f=%d.\n", + pipe_id, width, height, format); +} + +/* + * For CSS2.1, capture pipe uses capture_pp_in_res to configure yuv + * downscaling input resolution. + */ +static void __configure_capture_pp_input(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_stream_config *stream_config = &stream_env->stream_config; + struct ia_css_pipe_config *pipe_configs = + &stream_env->pipe_configs[pipe_id]; + struct ia_css_pipe_extra_config *pipe_extra_configs = + &stream_env->pipe_extra_configs[pipe_id]; + unsigned int hor_ds_factor = 0, ver_ds_factor = 0; + + if (width == 0 && height == 0) + return; + + if (width * 9 / 10 < pipe_configs->output_info[0].res.width || + height * 9 / 10 < pipe_configs->output_info[0].res.height) + return; + /* here just copy the calculation in css */ + hor_ds_factor = CEIL_DIV(width >> 1, + pipe_configs->output_info[0].res.width); + ver_ds_factor = CEIL_DIV(height >> 1, + pipe_configs->output_info[0].res.height); + + if ((asd->isp->media_dev.hw_revision < + (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT) || + IS_CHT) && hor_ds_factor != ver_ds_factor) { + dev_warn(asd->isp->dev, + "Cropping for capture due to FW limitation"); + return; + } + + pipe_configs->mode = __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + pipe_extra_configs->enable_yuv_ds = true; + + pipe_configs->capt_pp_in_res.width = + stream_config->input_config.effective_res.width; + pipe_configs->capt_pp_in_res.height = + stream_config->input_config.effective_res.height; + + dev_dbg(isp->dev, "configuring pipe[%d]capture pp input w=%d.h=%d.\n", + pipe_id, width, height); +} + +/* + * For CSS2.1, preview pipe could support bayer downscaling, yuv decimation and + * yuv downscaling, which needs addtional configurations. + */ +static void __configure_preview_pp_input(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + int out_width, out_height, yuv_ds_in_width, yuv_ds_in_height; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_stream_config *stream_config = &stream_env->stream_config; + struct ia_css_pipe_config *pipe_configs = + &stream_env->pipe_configs[pipe_id]; + struct ia_css_pipe_extra_config *pipe_extra_configs = + &stream_env->pipe_extra_configs[pipe_id]; + struct ia_css_resolution *bayer_ds_out_res = + &pipe_configs->bayer_ds_out_res; + struct ia_css_resolution *vf_pp_in_res = + &pipe_configs->vf_pp_in_res; + struct ia_css_resolution *effective_res = + &stream_config->input_config.effective_res; + + static const struct bayer_ds_factor bds_fct[] = {{2, 1}, {3, 2}, {5, 4} }; + /* + * BZ201033: YUV decimation factor of 4 causes couple of rightmost + * columns to be shaded. Remove this factor to work around the CSS bug. + * const unsigned int yuv_dec_fct[] = {4, 2}; + */ + static const unsigned int yuv_dec_fct[] = { 2 }; + unsigned int i; + + if (width == 0 && height == 0) + return; + + pipe_configs->mode = __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + out_width = pipe_configs->output_info[0].res.width; + out_height = pipe_configs->output_info[0].res.height; + + /* + * The ISP could do bayer downscaling, yuv decimation and yuv + * downscaling: + * 1: Bayer Downscaling: between effective resolution and + * bayer_ds_res_out; + * 2: YUV Decimation: between bayer_ds_res_out and vf_pp_in_res; + * 3: YUV Downscaling: between vf_pp_in_res and final vf output + * + * Rule for Bayer Downscaling: support factor 2, 1.5 and 1.25 + * Rule for YUV Decimation: support factor 2, 4 + * Rule for YUV Downscaling: arbitrary value below 2 + * + * General rule of factor distribution among these stages: + * 1: try to do Bayer downscaling first if not in online mode. + * 2: try to do maximum of 2 for YUV downscaling + * 3: the remainling for YUV decimation + * + * Note: + * Do not configure bayer_ds_out_res if: + * online == 1 or continuous == 0 or raw_binning = 0 + */ + if (stream_config->online || !stream_config->continuous || + !pipe_extra_configs->enable_raw_binning) { + bayer_ds_out_res->width = 0; + bayer_ds_out_res->height = 0; + } else { + bayer_ds_out_res->width = effective_res->width; + bayer_ds_out_res->height = effective_res->height; + + for (i = 0; i < ARRAY_SIZE(bds_fct); i++) { + if (effective_res->width >= out_width * + bds_fct[i].numerator / bds_fct[i].denominator && + effective_res->height >= out_height * + bds_fct[i].numerator / bds_fct[i].denominator) { + bayer_ds_out_res->width = + effective_res->width * + bds_fct[i].denominator / + bds_fct[i].numerator; + bayer_ds_out_res->height = + effective_res->height * + bds_fct[i].denominator / + bds_fct[i].numerator; + break; + } + } + } + /* + * calculate YUV Decimation, YUV downscaling facor: + * YUV Downscaling factor must not exceed 2. + * YUV Decimation factor could be 2, 4. + */ + /* first decide the yuv_ds input resolution */ + if (bayer_ds_out_res->width == 0) { + yuv_ds_in_width = effective_res->width; + yuv_ds_in_height = effective_res->height; + } else { + yuv_ds_in_width = bayer_ds_out_res->width; + yuv_ds_in_height = bayer_ds_out_res->height; + } + + vf_pp_in_res->width = yuv_ds_in_width; + vf_pp_in_res->height = yuv_ds_in_height; + + /* find out the yuv decimation factor */ + for (i = 0; i < ARRAY_SIZE(yuv_dec_fct); i++) { + if (yuv_ds_in_width >= out_width * yuv_dec_fct[i] && + yuv_ds_in_height >= out_height * yuv_dec_fct[i]) { + vf_pp_in_res->width = yuv_ds_in_width / yuv_dec_fct[i]; + vf_pp_in_res->height = yuv_ds_in_height / yuv_dec_fct[i]; + break; + } + } + + if (vf_pp_in_res->width == out_width && + vf_pp_in_res->height == out_height) { + pipe_extra_configs->enable_yuv_ds = false; + vf_pp_in_res->width = 0; + vf_pp_in_res->height = 0; + } else { + pipe_extra_configs->enable_yuv_ds = true; + } + + dev_dbg(isp->dev, "configuring pipe[%d]preview pp input w=%d.h=%d.\n", + pipe_id, width, height); +} + +/* + * For CSS2.1, offline video pipe could support bayer decimation, and + * yuv downscaling, which needs addtional configurations. + */ +static void __configure_video_pp_input(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + int out_width, out_height; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_stream_config *stream_config = &stream_env->stream_config; + struct ia_css_pipe_config *pipe_configs = + &stream_env->pipe_configs[pipe_id]; + struct ia_css_pipe_extra_config *pipe_extra_configs = + &stream_env->pipe_extra_configs[pipe_id]; + struct ia_css_resolution *bayer_ds_out_res = + &pipe_configs->bayer_ds_out_res; + struct ia_css_resolution *effective_res = + &stream_config->input_config.effective_res; + + static const struct bayer_ds_factor bds_factors[] = { + {8, 1}, {6, 1}, {4, 1}, {3, 1}, {2, 1}, {3, 2} + }; + unsigned int i; + + if (width == 0 && height == 0) + return; + + pipe_configs->mode = __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + pipe_extra_configs->enable_yuv_ds = false; + + /* + * If DVS is enabled, video binary will take care the dvs envelope + * and usually the bayer_ds_out_res should be larger than 120% of + * destination resolution, the extra 20% will be cropped as DVS + * envelope. But, if the bayer_ds_out_res is less than 120% of the + * destination. The ISP can still work, but DVS quality is not good. + */ + /* taking at least 10% as envelope */ + if (asd->params.video_dis_en) { + out_width = pipe_configs->output_info[0].res.width * 110 / 100; + out_height = pipe_configs->output_info[0].res.height * 110 / 100; + } else { + out_width = pipe_configs->output_info[0].res.width; + out_height = pipe_configs->output_info[0].res.height; + } + + /* + * calculate bayer decimate factor: + * 1: only 1.5, 2, 4 and 8 get supported + * 2: Do not configure bayer_ds_out_res if: + * online == 1 or continuous == 0 or raw_binning = 0 + */ + if (stream_config->online || !stream_config->continuous) { + bayer_ds_out_res->width = 0; + bayer_ds_out_res->height = 0; + goto done; + } + + pipe_extra_configs->enable_raw_binning = true; + bayer_ds_out_res->width = effective_res->width; + bayer_ds_out_res->height = effective_res->height; + + for (i = 0; i < sizeof(bds_factors) / sizeof(struct bayer_ds_factor); + i++) { + if (effective_res->width >= out_width * + bds_factors[i].numerator / bds_factors[i].denominator && + effective_res->height >= out_height * + bds_factors[i].numerator / bds_factors[i].denominator) { + bayer_ds_out_res->width = effective_res->width * + bds_factors[i].denominator / + bds_factors[i].numerator; + bayer_ds_out_res->height = effective_res->height * + bds_factors[i].denominator / + bds_factors[i].numerator; + break; + } + } + + /* + * DVS is cropped from BDS output, so we do not really need to set the + * envelope to 20% of output resolution here. always set it to 12x12 + * per firmware requirement. + */ + pipe_configs->dvs_envelope.width = 12; + pipe_configs->dvs_envelope.height = 12; + +done: + if (pipe_id == IA_CSS_PIPE_ID_YUVPP) + stream_config->left_padding = -1; + else + stream_config->left_padding = 12; + dev_dbg(isp->dev, "configuring pipe[%d]video pp input w=%d.h=%d.\n", + pipe_id, width, height); +} + +static void __configure_vf_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + stream_env->pipe_configs[pipe_id].vf_output_info[0].res.width = width; + stream_env->pipe_configs[pipe_id].vf_output_info[0].res.height = height; + stream_env->pipe_configs[pipe_id].vf_output_info[0].format = format; + stream_env->pipe_configs[pipe_id].vf_output_info[0].padded_width = + min_width; + dev_dbg(isp->dev, + "configuring pipe[%d] vf output info w=%d.h=%d.f=%d.\n", + pipe_id, width, height, format); +} + +static void __configure_video_vf_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_frame_info *css_output_info; + + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + /* + * second_vf_output will be as video viewfinder in SDV mode + * with SOC camera. vf_output will be as video viewfinder in + * normal video mode. + */ + if (asd->continuous_mode->val) + css_output_info = &stream_env->pipe_configs[pipe_id]. + vf_output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + css_output_info = &stream_env->pipe_configs[pipe_id]. + vf_output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + + css_output_info->res.width = width; + css_output_info->res.height = height; + css_output_info->format = format; + css_output_info->padded_width = min_width; + dev_dbg(isp->dev, + "configuring pipe[%d] vf output info w=%d.h=%d.f=%d.\n", + pipe_id, width, height, format); +} + +static int __get_frame_info(struct atomisp_sub_device *asd, + unsigned int stream_index, + struct ia_css_frame_info *info, + enum frame_info_type type, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + int ret; + struct ia_css_pipe_info p_info; + + /* FIXME! No need to destroy/recreate all streams */ + ret = atomisp_css_update_stream(asd); + if (ret) + return ret; + + ret = ia_css_pipe_get_info(asd->stream_env[stream_index].pipes[pipe_id], + &p_info); + if (ret) { + dev_err(isp->dev, "can't get info from pipe\n"); + goto get_info_err; + } + + switch (type) { + case ATOMISP_CSS_VF_FRAME: + *info = p_info.vf_output_info[0]; + dev_dbg(isp->dev, "getting vf frame info.\n"); + break; + case ATOMISP_CSS_SECOND_VF_FRAME: + *info = p_info.vf_output_info[1]; + dev_dbg(isp->dev, "getting second vf frame info.\n"); + break; + case ATOMISP_CSS_OUTPUT_FRAME: + *info = p_info.output_info[0]; + dev_dbg(isp->dev, "getting main frame info.\n"); + break; + case ATOMISP_CSS_SECOND_OUTPUT_FRAME: + *info = p_info.output_info[1]; + dev_dbg(isp->dev, "getting second main frame info.\n"); + break; + default: + case ATOMISP_CSS_RAW_FRAME: + *info = p_info.raw_output_info; + dev_dbg(isp->dev, "getting raw frame info.\n"); + break; + } + dev_dbg(isp->dev, "get frame info: w=%d, h=%d, num_invalid_frames %d.\n", + info->res.width, info->res.height, p_info.num_invalid_frames); + + return 0; + +get_info_err: + atomisp_destroy_pipes_stream_force(asd); + return -EINVAL; +} + +static unsigned int atomisp_get_pipe_index(struct atomisp_sub_device *asd, + uint16_t source_pad) +{ + struct atomisp_device *isp = asd->isp; + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + return IA_CSS_PIPE_ID_YUVPP; + + switch (source_pad) { + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: + if (asd->yuvpp_mode) + return IA_CSS_PIPE_ID_YUVPP; + if (asd->copy_mode) + return IA_CSS_PIPE_ID_COPY; + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO + || asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) + return IA_CSS_PIPE_ID_VIDEO; + + return IA_CSS_PIPE_ID_CAPTURE; + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + if (asd->copy_mode) + return IA_CSS_PIPE_ID_COPY; + + return IA_CSS_PIPE_ID_CAPTURE; + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + if (!atomisp_is_mbuscode_raw(asd->fmt[asd->capture_pad].fmt.code)) { + return IA_CSS_PIPE_ID_CAPTURE; + } + fallthrough; + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + if (asd->yuvpp_mode) + return IA_CSS_PIPE_ID_YUVPP; + if (asd->copy_mode) + return IA_CSS_PIPE_ID_COPY; + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + return IA_CSS_PIPE_ID_VIDEO; + + return IA_CSS_PIPE_ID_PREVIEW; + } + dev_warn(isp->dev, + "invalid source pad:%d, return default preview pipe index.\n", + source_pad); + return IA_CSS_PIPE_ID_PREVIEW; +} + +int atomisp_get_css_frame_info(struct atomisp_sub_device *asd, + u16 source_pad, + struct ia_css_frame_info *frame_info) +{ + struct ia_css_pipe_info info; + int pipe_index = atomisp_get_pipe_index(asd, source_pad); + int stream_index; + struct atomisp_device *isp = asd->isp; + + if (ATOMISP_SOC_CAMERA(asd)) { + stream_index = ATOMISP_INPUT_STREAM_GENERAL; + } else { + stream_index = (pipe_index == IA_CSS_PIPE_ID_YUVPP) ? + ATOMISP_INPUT_STREAM_VIDEO : + ATOMISP_INPUT_STREAM_GENERAL; + } + + if (0 != ia_css_pipe_get_info(asd->stream_env[stream_index] + .pipes[pipe_index], &info)) { + dev_dbg(isp->dev, "ia_css_pipe_get_info FAILED"); + return -EINVAL; + } + + switch (source_pad) { + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + *frame_info = info.output_info[0]; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: + if (ATOMISP_USE_YUVPP(asd) && asd->continuous_mode->val) + *frame_info = info. + output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + *frame_info = info. + output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + if (stream_index == ATOMISP_INPUT_STREAM_POSTVIEW) + *frame_info = info.output_info[0]; + else + *frame_info = info.vf_output_info[0]; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + (pipe_index == IA_CSS_PIPE_ID_VIDEO || + pipe_index == IA_CSS_PIPE_ID_YUVPP)) + if (ATOMISP_USE_YUVPP(asd) && asd->continuous_mode->val) + *frame_info = info. + vf_output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + *frame_info = info. + vf_output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + else if (ATOMISP_USE_YUVPP(asd) && asd->continuous_mode->val) + *frame_info = + info.output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + *frame_info = + info.output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + + break; + default: + frame_info = NULL; + break; + } + return frame_info ? 0 : -EINVAL; +} + +int atomisp_css_copy_configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int padded_width, + enum ia_css_frame_format format) +{ + asd->stream_env[stream_index].pipe_configs[IA_CSS_PIPE_ID_COPY]. + default_capture_config.mode = + IA_CSS_CAPTURE_MODE_RAW; + + __configure_output(asd, stream_index, width, height, padded_width, + format, IA_CSS_PIPE_ID_COPY); + return 0; +} + +int atomisp_css_yuvpp_configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int padded_width, + enum ia_css_frame_format format) +{ + asd->stream_env[stream_index].pipe_configs[IA_CSS_PIPE_ID_YUVPP]. + default_capture_config.mode = + IA_CSS_CAPTURE_MODE_RAW; + + __configure_output(asd, stream_index, width, height, padded_width, + format, IA_CSS_PIPE_ID_YUVPP); + return 0; +} + +int atomisp_css_yuvpp_get_output_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct ia_css_frame_info *info) +{ + return __get_frame_info(asd, stream_index, info, + ATOMISP_CSS_OUTPUT_FRAME, IA_CSS_PIPE_ID_YUVPP); +} + +int atomisp_css_yuvpp_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct ia_css_frame_info *info) +{ + return __get_frame_info(asd, stream_index, info, + ATOMISP_CSS_VF_FRAME, IA_CSS_PIPE_ID_YUVPP); +} + +int atomisp_css_preview_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format) +{ + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + __configure_video_preview_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, + height, + min_width, format, IA_CSS_PIPE_ID_YUVPP); + else + __configure_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, height, + min_width, format, IA_CSS_PIPE_ID_PREVIEW); + return 0; +} + +int atomisp_css_capture_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format) +{ + enum ia_css_pipe_id pipe_id; + + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + else + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + __configure_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, height, + min_width, format, pipe_id); + return 0; +} + +int atomisp_css_video_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format) +{ + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + __configure_video_preview_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, + height, + min_width, format, IA_CSS_PIPE_ID_YUVPP); + else + __configure_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, height, + min_width, format, IA_CSS_PIPE_ID_VIDEO); + return 0; +} + +int atomisp_css_video_configure_viewfinder( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format) +{ + /* + * to SOC camera, video will use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + __configure_video_vf_output(asd, width, height, min_width, format, + IA_CSS_PIPE_ID_YUVPP); + else + __configure_vf_output(asd, width, height, min_width, format, + IA_CSS_PIPE_ID_VIDEO); + return 0; +} + +int atomisp_css_capture_configure_viewfinder( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format) +{ + enum ia_css_pipe_id pipe_id; + + /* + * to SOC camera, video will use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + else + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + __configure_vf_output(asd, width, height, min_width, format, + pipe_id); + return 0; +} + +int atomisp_css_video_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + enum frame_info_type frame_type = ATOMISP_CSS_VF_FRAME; + + if (ATOMISP_USE_YUVPP(asd)) { + pipe_id = IA_CSS_PIPE_ID_YUVPP; + if (asd->continuous_mode->val) + frame_type = ATOMISP_CSS_SECOND_VF_FRAME; + } else { + pipe_id = IA_CSS_PIPE_ID_VIDEO; + } + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + frame_type, pipe_id); +} + +int atomisp_css_capture_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + else + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + ATOMISP_CSS_VF_FRAME, pipe_id); +} + +int atomisp_css_capture_get_output_raw_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info) +{ + if (ATOMISP_USE_YUVPP(asd)) + return 0; + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + ATOMISP_CSS_RAW_FRAME, IA_CSS_PIPE_ID_CAPTURE); +} + +int atomisp_css_copy_get_output_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct ia_css_frame_info *info) +{ + return __get_frame_info(asd, stream_index, info, + ATOMISP_CSS_OUTPUT_FRAME, IA_CSS_PIPE_ID_COPY); +} + +int atomisp_css_preview_get_output_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + enum frame_info_type frame_type = ATOMISP_CSS_OUTPUT_FRAME; + + if (ATOMISP_USE_YUVPP(asd)) { + pipe_id = IA_CSS_PIPE_ID_YUVPP; + if (asd->continuous_mode->val) + frame_type = ATOMISP_CSS_SECOND_OUTPUT_FRAME; + } else { + pipe_id = IA_CSS_PIPE_ID_PREVIEW; + } + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + frame_type, pipe_id); +} + +int atomisp_css_capture_get_output_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + else + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + ATOMISP_CSS_OUTPUT_FRAME, pipe_id); +} + +int atomisp_css_video_get_output_frame_info( + struct atomisp_sub_device *asd, + struct ia_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + enum frame_info_type frame_type = ATOMISP_CSS_OUTPUT_FRAME; + + if (ATOMISP_USE_YUVPP(asd)) { + pipe_id = IA_CSS_PIPE_ID_YUVPP; + if (asd->continuous_mode->val) + frame_type = ATOMISP_CSS_SECOND_OUTPUT_FRAME; + } else { + pipe_id = IA_CSS_PIPE_ID_VIDEO; + } + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + frame_type, pipe_id); +} + +int atomisp_css_preview_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + __configure_preview_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_PREVIEW); + + if (width > stream_env->pipe_configs[IA_CSS_PIPE_ID_CAPTURE]. + capt_pp_in_res.width) + __configure_capture_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_CAPTURE); + return 0; +} + +int atomisp_css_capture_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) +{ + __configure_capture_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_CAPTURE); + return 0; +} + +int atomisp_css_video_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + + __configure_video_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_VIDEO); + + if (width > stream_env->pipe_configs[IA_CSS_PIPE_ID_CAPTURE]. + capt_pp_in_res.width) + __configure_capture_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_CAPTURE); + return 0; +} + +int atomisp_css_offline_capture_configure(struct atomisp_sub_device *asd, + int num_captures, unsigned int skip, int offset) +{ + int ret; + + dev_dbg(asd->isp->dev, "%s num_capture:%d skip:%d offset:%d\n", + __func__, num_captures, skip, offset); + + ret = ia_css_stream_capture( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + num_captures, skip, offset); + if (ret) + return -EINVAL; + + return 0; +} + +int atomisp_css_exp_id_capture(struct atomisp_sub_device *asd, int exp_id) +{ + int ret; + + ret = ia_css_stream_capture_frame( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + exp_id); + if (ret == -ENOBUFS) { + /* capture cmd queue is full */ + return -EBUSY; + } else if (ret) { + return -EIO; + } + + return 0; +} + +int atomisp_css_exp_id_unlock(struct atomisp_sub_device *asd, int exp_id) +{ + int ret; + + ret = ia_css_unlock_raw_frame( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + exp_id); + if (ret == -ENOBUFS) + return -EAGAIN; + else if (ret) + return -EIO; + + return 0; +} + +int atomisp_css_capture_enable_xnr(struct atomisp_sub_device *asd, + bool enable) +{ + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[IA_CSS_PIPE_ID_CAPTURE] + .default_capture_config.enable_xnr = enable; + asd->params.capture_config.enable_xnr = enable; + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .update_pipe[IA_CSS_PIPE_ID_CAPTURE] = true; + + return 0; +} + +void atomisp_css_set_ctc_table(struct atomisp_sub_device *asd, + struct ia_css_ctc_table *ctc_table) +{ + int i; + u16 *vamem_ptr = ctc_table->data.vamem_1; + int data_size = IA_CSS_VAMEM_1_CTC_TABLE_SIZE; + bool valid = false; + + /* workaround: if ctc_table is all 0, do not apply it */ + if (ctc_table->vamem_type == IA_CSS_VAMEM_TYPE_2) { + vamem_ptr = ctc_table->data.vamem_2; + data_size = IA_CSS_VAMEM_2_CTC_TABLE_SIZE; + } + + for (i = 0; i < data_size; i++) { + if (*(vamem_ptr + i)) { + valid = true; + break; + } + } + + if (valid) + asd->params.config.ctc_table = ctc_table; + else + dev_warn(asd->isp->dev, "Bypass the invalid ctc_table.\n"); +} + +void atomisp_css_set_anr_thres(struct atomisp_sub_device *asd, + struct ia_css_anr_thres *anr_thres) +{ + asd->params.config.anr_thres = anr_thres; +} + +void atomisp_css_set_dvs_6axis(struct atomisp_sub_device *asd, + struct ia_css_dvs_6axis_config *dvs_6axis) +{ + asd->params.config.dvs_6axis_config = dvs_6axis; +} + +void atomisp_css_video_set_dis_vector(struct atomisp_sub_device *asd, + struct atomisp_dis_vector *vector) +{ + if (!asd->params.config.motion_vector) + asd->params.config.motion_vector = &asd->params.css_param.motion_vector; + + memset(asd->params.config.motion_vector, + 0, sizeof(struct ia_css_vector)); + asd->params.css_param.motion_vector.x = vector->x; + asd->params.css_param.motion_vector.y = vector->y; +} + +static int atomisp_compare_dvs_grid(struct atomisp_sub_device *asd, + struct atomisp_dvs_grid_info *atomgrid) +{ + struct ia_css_dvs_grid_info *cur = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + + if (!cur) { + dev_err(asd->isp->dev, "dvs grid not available!\n"); + return -EINVAL; + } + + if (sizeof(*cur) != sizeof(*atomgrid)) { + dev_err(asd->isp->dev, "dvs grid mismatch!\n"); + return -EINVAL; + } + + if (!cur->enable) { + dev_err(asd->isp->dev, "dvs not enabled!\n"); + return -EINVAL; + } + + return memcmp(atomgrid, cur, sizeof(*cur)); +} + +void atomisp_css_set_dvs2_coefs(struct atomisp_sub_device *asd, + struct ia_css_dvs2_coefficients *coefs) +{ + asd->params.config.dvs2_coefs = coefs; +} + +int atomisp_css_set_dis_coefs(struct atomisp_sub_device *asd, + struct atomisp_dis_coefficients *coefs) +{ + if (atomisp_compare_dvs_grid(asd, &coefs->grid_info) != 0) + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + + if (!coefs->hor_coefs.odd_real || + !coefs->hor_coefs.odd_imag || + !coefs->hor_coefs.even_real || + !coefs->hor_coefs.even_imag || + !coefs->ver_coefs.odd_real || + !coefs->ver_coefs.odd_imag || + !coefs->ver_coefs.even_real || + !coefs->ver_coefs.even_imag || + !asd->params.css_param.dvs2_coeff->hor_coefs.odd_real || + !asd->params.css_param.dvs2_coeff->hor_coefs.odd_imag || + !asd->params.css_param.dvs2_coeff->hor_coefs.even_real || + !asd->params.css_param.dvs2_coeff->hor_coefs.even_imag || + !asd->params.css_param.dvs2_coeff->ver_coefs.odd_real || + !asd->params.css_param.dvs2_coeff->ver_coefs.odd_imag || + !asd->params.css_param.dvs2_coeff->ver_coefs.even_real || + !asd->params.css_param.dvs2_coeff->ver_coefs.even_imag) + return -EINVAL; + + if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.odd_real, + coefs->hor_coefs.odd_real, asd->params.dvs_hor_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.odd_imag, + coefs->hor_coefs.odd_imag, asd->params.dvs_hor_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.even_real, + coefs->hor_coefs.even_real, asd->params.dvs_hor_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.even_imag, + coefs->hor_coefs.even_imag, asd->params.dvs_hor_coef_bytes)) + return -EFAULT; + + if (copy_from_user(asd->params.css_param.dvs2_coeff->ver_coefs.odd_real, + coefs->ver_coefs.odd_real, asd->params.dvs_ver_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->ver_coefs.odd_imag, + coefs->ver_coefs.odd_imag, asd->params.dvs_ver_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->ver_coefs.even_real, + coefs->ver_coefs.even_real, asd->params.dvs_ver_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->ver_coefs.even_imag, + coefs->ver_coefs.even_imag, asd->params.dvs_ver_coef_bytes)) + return -EFAULT; + + asd->params.css_param.update_flag.dvs2_coefs = + (struct atomisp_dis_coefficients *) + asd->params.css_param.dvs2_coeff; + /* FIXME! */ + /* asd->params.dis_proj_data_valid = false; */ + asd->params.css_update_params_needed = true; + + return 0; +} + +void atomisp_css_set_zoom_factor(struct atomisp_sub_device *asd, + unsigned int zoom) +{ + struct atomisp_device *isp = asd->isp; + + if (zoom == asd->params.css_param.dz_config.dx && + zoom == asd->params.css_param.dz_config.dy) { + dev_dbg(isp->dev, "same zoom scale. skipped.\n"); + return; + } + + memset(&asd->params.css_param.dz_config, 0, + sizeof(struct ia_css_dz_config)); + asd->params.css_param.dz_config.dx = zoom; + asd->params.css_param.dz_config.dy = zoom; + + asd->params.css_param.update_flag.dz_config = + (struct atomisp_dz_config *)&asd->params.css_param.dz_config; + asd->params.css_update_params_needed = true; +} + +void atomisp_css_set_formats_config(struct atomisp_sub_device *asd, + struct ia_css_formats_config *formats_config) +{ + asd->params.config.formats_config = formats_config; +} + +int atomisp_css_get_wb_config(struct atomisp_sub_device *asd, + struct atomisp_wb_config *config) +{ + struct ia_css_wb_config wb_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&wb_config, 0, sizeof(struct ia_css_wb_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.wb_config = &wb_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &wb_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_ob_config(struct atomisp_sub_device *asd, + struct atomisp_ob_config *config) +{ + struct ia_css_ob_config ob_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&ob_config, 0, sizeof(struct ia_css_ob_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.ob_config = &ob_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &ob_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_dp_config(struct atomisp_sub_device *asd, + struct atomisp_dp_config *config) +{ + struct ia_css_dp_config dp_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&dp_config, 0, sizeof(struct ia_css_dp_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.dp_config = &dp_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &dp_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_de_config(struct atomisp_sub_device *asd, + struct atomisp_de_config *config) +{ + struct ia_css_de_config de_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&de_config, 0, sizeof(struct ia_css_de_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.de_config = &de_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &de_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_nr_config(struct atomisp_sub_device *asd, + struct atomisp_nr_config *config) +{ + struct ia_css_nr_config nr_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&nr_config, 0, sizeof(struct ia_css_nr_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + + isp_config.nr_config = &nr_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &nr_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_ee_config(struct atomisp_sub_device *asd, + struct atomisp_ee_config *config) +{ + struct ia_css_ee_config ee_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&ee_config, 0, sizeof(struct ia_css_ee_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.ee_config = &ee_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &ee_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_tnr_config(struct atomisp_sub_device *asd, + struct atomisp_tnr_config *config) +{ + struct ia_css_tnr_config tnr_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&tnr_config, 0, sizeof(struct ia_css_tnr_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.tnr_config = &tnr_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &tnr_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_ctc_table(struct atomisp_sub_device *asd, + struct atomisp_ctc_table *config) +{ + struct ia_css_ctc_table *tab; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + + tab = vzalloc(sizeof(struct ia_css_ctc_table)); + if (!tab) + return -ENOMEM; + + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.ctc_table = tab; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, tab, sizeof(*tab)); + vfree(tab); + + return 0; +} + +int atomisp_css_get_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_gamma_table *config) +{ + struct ia_css_gamma_table *tab; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + + tab = vzalloc(sizeof(struct ia_css_gamma_table)); + if (!tab) + return -ENOMEM; + + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.gamma_table = tab; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, tab, sizeof(*tab)); + vfree(tab); + + return 0; +} + +int atomisp_css_get_gc_config(struct atomisp_sub_device *asd, + struct atomisp_gc_config *config) +{ + struct ia_css_gc_config gc_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&gc_config, 0, sizeof(struct ia_css_gc_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.gc_config = &gc_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + /* Get gamma correction params from current setup */ + memcpy(config, &gc_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_3a_config(struct atomisp_sub_device *asd, + struct atomisp_3a_config *config) +{ + struct ia_css_3a_config s3a_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&s3a_config, 0, sizeof(struct ia_css_3a_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.s3a_config = &s3a_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + /* Get white balance from current setup */ + memcpy(config, &s3a_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_formats_config(struct atomisp_sub_device *asd, + struct atomisp_formats_config *config) +{ + struct ia_css_formats_config formats_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&formats_config, 0, sizeof(formats_config)); + memset(&isp_config, 0, sizeof(isp_config)); + isp_config.formats_config = &formats_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + /* Get narrow gamma from current setup */ + memcpy(config, &formats_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_zoom_factor(struct atomisp_sub_device *asd, + unsigned int *zoom) +{ + struct ia_css_dz_config dz_config; /** Digital Zoom */ + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&dz_config, 0, sizeof(struct ia_css_dz_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.dz_config = &dz_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + *zoom = dz_config.dx; + + return 0; +} + +/* + * Function to set/get image stablization statistics + */ +int atomisp_css_get_dis_stat(struct atomisp_sub_device *asd, + struct atomisp_dis_statistics *stats) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_dis_buf *dis_buf; + unsigned long flags; + + lockdep_assert_held(&isp->mutex); + + if (!asd->params.dvs_stat->hor_prod.odd_real || + !asd->params.dvs_stat->hor_prod.odd_imag || + !asd->params.dvs_stat->hor_prod.even_real || + !asd->params.dvs_stat->hor_prod.even_imag || + !asd->params.dvs_stat->ver_prod.odd_real || + !asd->params.dvs_stat->ver_prod.odd_imag || + !asd->params.dvs_stat->ver_prod.even_real || + !asd->params.dvs_stat->ver_prod.even_imag) + return -EINVAL; + + /* isp needs to be streaming to get DIS statistics */ + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + return -EINVAL; + + if (atomisp_compare_dvs_grid(asd, &stats->dvs2_stat.grid_info) != 0) + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + + spin_lock_irqsave(&asd->dis_stats_lock, flags); + if (!asd->params.dis_proj_data_valid || list_empty(&asd->dis_stats)) { + spin_unlock_irqrestore(&asd->dis_stats_lock, flags); + dev_err(isp->dev, "dis statistics is not valid.\n"); + return -EAGAIN; + } + + dis_buf = list_entry(asd->dis_stats.next, + struct atomisp_dis_buf, list); + list_del_init(&dis_buf->list); + spin_unlock_irqrestore(&asd->dis_stats_lock, flags); + + if (dis_buf->dvs_map) + ia_css_translate_dvs2_statistics( + asd->params.dvs_stat, dis_buf->dvs_map); + else + ia_css_get_dvs2_statistics(asd->params.dvs_stat, + dis_buf->dis_data); + stats->exp_id = dis_buf->dis_data->exp_id; + + spin_lock_irqsave(&asd->dis_stats_lock, flags); + list_add_tail(&dis_buf->list, &asd->dis_stats); + spin_unlock_irqrestore(&asd->dis_stats_lock, flags); + + if (copy_to_user(stats->dvs2_stat.ver_prod.odd_real, + asd->params.dvs_stat->ver_prod.odd_real, + asd->params.dvs_ver_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.ver_prod.odd_imag, + asd->params.dvs_stat->ver_prod.odd_imag, + asd->params.dvs_ver_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.ver_prod.even_real, + asd->params.dvs_stat->ver_prod.even_real, + asd->params.dvs_ver_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.ver_prod.even_imag, + asd->params.dvs_stat->ver_prod.even_imag, + asd->params.dvs_ver_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.hor_prod.odd_real, + asd->params.dvs_stat->hor_prod.odd_real, + asd->params.dvs_hor_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.hor_prod.odd_imag, + asd->params.dvs_stat->hor_prod.odd_imag, + asd->params.dvs_hor_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.hor_prod.even_real, + asd->params.dvs_stat->hor_prod.even_real, + asd->params.dvs_hor_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.hor_prod.even_imag, + asd->params.dvs_stat->hor_prod.even_imag, + asd->params.dvs_hor_proj_bytes)) + return -EFAULT; + + return 0; +} + +struct ia_css_shading_table *atomisp_css_shading_table_alloc( + unsigned int width, unsigned int height) +{ + return ia_css_shading_table_alloc(width, height); +} + +void atomisp_css_set_shading_table(struct atomisp_sub_device *asd, + struct ia_css_shading_table *table) +{ + asd->params.config.shading_table = table; +} + +void atomisp_css_shading_table_free(struct ia_css_shading_table *table) +{ + ia_css_shading_table_free(table); +} + +struct ia_css_morph_table *atomisp_css_morph_table_allocate( + unsigned int width, unsigned int height) +{ + return ia_css_morph_table_allocate(width, height); +} + +void atomisp_css_set_morph_table(struct atomisp_sub_device *asd, + struct ia_css_morph_table *table) +{ + asd->params.config.morph_table = table; +} + +void atomisp_css_get_morph_table(struct atomisp_sub_device *asd, + struct ia_css_morph_table *table) +{ + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, + "%s called after streamoff, skipping.\n", __func__); + return; + } + memset(table, 0, sizeof(struct ia_css_morph_table)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.morph_table = table; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); +} + +void atomisp_css_morph_table_free(struct ia_css_morph_table *table) +{ + ia_css_morph_table_free(table); +} + +static struct atomisp_sub_device *__get_atomisp_subdev( + struct ia_css_pipe *css_pipe, + struct atomisp_device *isp, + enum atomisp_input_stream_id *stream_id) +{ + int i, j, k; + struct atomisp_sub_device *asd; + struct atomisp_stream_env *stream_env; + + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + if (asd->streaming == ATOMISP_DEVICE_STREAMING_DISABLED) + continue; + for (j = 0; j < ATOMISP_INPUT_STREAM_NUM; j++) { + stream_env = &asd->stream_env[j]; + for (k = 0; k < IA_CSS_PIPE_ID_NUM; k++) { + if (stream_env->pipes[k] && + stream_env->pipes[k] == css_pipe) { + *stream_id = j; + return asd; + } + } + } + } + + return NULL; +} + +int atomisp_css_isr_thread(struct atomisp_device *isp, + bool *frame_done_found, + bool *css_pipe_done) +{ + enum atomisp_input_stream_id stream_id = 0; + struct atomisp_css_event current_event; + struct atomisp_sub_device *asd; + + lockdep_assert_held(&isp->mutex); + + while (!ia_css_dequeue_psys_event(¤t_event.event)) { + if (current_event.event.type == + IA_CSS_EVENT_TYPE_FW_ASSERT) { + /* + * Received FW assertion signal, + * trigger WDT to recover + */ + dev_err(isp->dev, + "%s: ISP reports FW_ASSERT event! fw_assert_module_id %d fw_assert_line_no %d\n", + __func__, + current_event.event.fw_assert_module_id, + current_event.event.fw_assert_line_no); + + queue_work(system_long_wq, &isp->assert_recovery_work); + return -EINVAL; + } else if (current_event.event.type == IA_CSS_EVENT_TYPE_FW_WARNING) { + dev_warn(isp->dev, "%s: ISP reports warning, code is %d, exp_id %d\n", + __func__, current_event.event.fw_warning, + current_event.event.exp_id); + continue; + } + + asd = __get_atomisp_subdev(current_event.event.pipe, + isp, &stream_id); + if (!asd) { + if (current_event.event.type == IA_CSS_EVENT_TYPE_TIMER) + dev_dbg(isp->dev, + "event: Timer event."); + else + dev_warn(isp->dev, "%s:no subdev.event:%d", + __func__, + current_event.event.type); + continue; + } + + atomisp_css_temp_pipe_to_pipe_id(asd, ¤t_event); + switch (current_event.event.type) { + case IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE: + dev_dbg(isp->dev, "event: Output frame done"); + frame_done_found[asd->index] = true; + atomisp_buf_done(asd, 0, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, + current_event.pipe, true, stream_id); + break; + case IA_CSS_EVENT_TYPE_SECOND_OUTPUT_FRAME_DONE: + dev_dbg(isp->dev, "event: Second output frame done"); + frame_done_found[asd->index] = true; + atomisp_buf_done(asd, 0, IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME, + current_event.pipe, true, stream_id); + break; + case IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE: + dev_dbg(isp->dev, "event: 3A stats frame done"); + atomisp_buf_done(asd, 0, + IA_CSS_BUFFER_TYPE_3A_STATISTICS, + current_event.pipe, + false, stream_id); + break; + case IA_CSS_EVENT_TYPE_METADATA_DONE: + dev_dbg(isp->dev, "event: metadata frame done"); + atomisp_buf_done(asd, 0, + IA_CSS_BUFFER_TYPE_METADATA, + current_event.pipe, + false, stream_id); + break; + case IA_CSS_EVENT_TYPE_VF_OUTPUT_FRAME_DONE: + dev_dbg(isp->dev, "event: VF output frame done"); + atomisp_buf_done(asd, 0, + IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME, + current_event.pipe, true, stream_id); + break; + case IA_CSS_EVENT_TYPE_SECOND_VF_OUTPUT_FRAME_DONE: + dev_dbg(isp->dev, "event: second VF output frame done"); + atomisp_buf_done(asd, 0, + IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME, + current_event.pipe, true, stream_id); + break; + case IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE: + dev_dbg(isp->dev, "event: dis stats frame done"); + atomisp_buf_done(asd, 0, + IA_CSS_BUFFER_TYPE_DIS_STATISTICS, + current_event.pipe, + false, stream_id); + break; + case IA_CSS_EVENT_TYPE_PIPELINE_DONE: + dev_dbg(isp->dev, "event: pipeline done"); + css_pipe_done[asd->index] = true; + break; + case IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE: + dev_warn(isp->dev, "unexpected event: acc stage done"); + break; + default: + dev_dbg(isp->dev, "unhandled css stored event: 0x%x\n", + current_event.event.type); + break; + } + } + + return 0; +} + +bool atomisp_css_valid_sof(struct atomisp_device *isp) +{ + unsigned int i, j; + + /* Loop for each css stream */ + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + /* Loop for each css vc stream */ + for (j = 0; j < ATOMISP_INPUT_STREAM_NUM; j++) { + if (!asd->stream_env[j].stream) + continue; + + dev_dbg(isp->dev, + "stream #%d: mode: %d\n", j, + asd->stream_env[j].stream_config.mode); + if (asd->stream_env[j].stream_config.mode == + IA_CSS_INPUT_MODE_BUFFERED_SENSOR) + return false; + } + } + + return true; +} + +int atomisp_css_debug_dump_isp_binary(void) +{ + ia_css_debug_dump_isp_binary(); + return 0; +} + +int atomisp_css_dump_sp_raw_copy_linecount(bool reduced) +{ + sh_css_dump_sp_raw_copy_linecount(reduced); + return 0; +} + +static const char * const fw_type_name[] = { + [ia_css_sp_firmware] = "SP", + [ia_css_isp_firmware] = "ISP", + [ia_css_bootloader_firmware] = "BootLoader", + [ia_css_acc_firmware] = "accel", +}; + +static const char * const fw_acc_type_name[] = { + [IA_CSS_ACC_NONE] = "Normal", + [IA_CSS_ACC_OUTPUT] = "Accel stage on output", + [IA_CSS_ACC_VIEWFINDER] = "Accel stage on viewfinder", + [IA_CSS_ACC_STANDALONE] = "Stand-alone acceleration", +}; + +int atomisp_css_dump_blob_infor(struct atomisp_device *isp) +{ + struct ia_css_blob_descr *bd = sh_css_blob_info; + unsigned int i, nm = sh_css_num_binaries; + + if (nm == 0) + return -EPERM; + if (!bd) + return -EPERM; + + /* + * The sh_css_load_firmware function discard the initial + * "SPS" binaries + */ + for (i = 0; i < sh_css_num_binaries - NUM_OF_SPS; i++) { + switch (bd[i].header.type) { + case ia_css_isp_firmware: + dev_dbg(isp->dev, "Num%2d type %s (%s), binary id is %2d, name is %s\n", + i + NUM_OF_SPS, + fw_type_name[bd[i].header.type], + fw_acc_type_name[bd[i].header.info.isp.type], + bd[i].header.info.isp.sp.id, + bd[i].name); + break; + default: + dev_dbg(isp->dev, "Num%2d type %s, name is %s\n", + i + NUM_OF_SPS, fw_type_name[bd[i].header.type], + bd[i].name); + } + } + + return 0; +} + +void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd, + uint32_t isp_config_id) +{ + asd->params.config.isp_config_id = isp_config_id; +} + +void atomisp_css_set_isp_config_applied_frame(struct atomisp_sub_device *asd, + struct ia_css_frame *output_frame) +{ + asd->params.config.output_frame = output_frame; +} + +int atomisp_get_css_dbgfunc(void) +{ + return dbg_func; +} + +int atomisp_set_css_dbgfunc(struct atomisp_device *isp, int opt) +{ + int ret; + + ret = __set_css_print_env(isp, opt); + if (ret == 0) + dbg_func = opt; + + return ret; +} + +void atomisp_en_dz_capt_pipe(struct atomisp_sub_device *asd, bool enable) +{ + ia_css_en_dz_capt_pipe( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + enable); +} + +struct ia_css_dvs_grid_info *atomisp_css_get_dvs_grid_info( + struct ia_css_grid_info *grid_info) +{ + if (!grid_info) + return NULL; + +#ifdef IA_CSS_DVS_STAT_GRID_INFO_SUPPORTED + return &grid_info->dvs_grid.dvs_grid_info; +#else + return &grid_info->dvs_grid; +#endif +} diff --git a/drivers/staging/media/atomisp/pci/atomisp_compat_css20.h b/drivers/staging/media/atomisp/pci/atomisp_compat_css20.h new file mode 100644 index 000000000..e06015343 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_compat_css20.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Clovertrail PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_COMPAT_CSS20_H__ +#define __ATOMISP_COMPAT_CSS20_H__ + +#include + +#include "ia_css.h" +#include "ia_css_types.h" +#include "ia_css_acc_types.h" +#include "sh_css_legacy.h" + +#define ATOMISP_CSS2_PIPE_MAX 2 +#define ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES 3 +#define ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES_LOCK_EN 4 +#define ATOMISP_CSS2_NUM_DVS_FRAME_DELAY 2 + +#define CSS_MIPI_FRAME_BUFFER_SIZE_1 0x60000 +#define CSS_MIPI_FRAME_BUFFER_SIZE_2 0x80000 + +struct atomisp_device; +struct atomisp_sub_device; + +#define MAX_STREAMS_PER_CHANNEL 2 + +/* + * These are used to indicate the css stream state, corresponding + * stream handling can be done via judging the different state. + */ +enum atomisp_css_stream_state { + CSS_STREAM_UNINIT, + CSS_STREAM_CREATED, + CSS_STREAM_STARTED, + CSS_STREAM_STOPPED, +}; + +/* + * Sensor of external ISP can send multiple steams with different mipi data + * type in the same virtual channel. This information needs to come from the + * sensor or external ISP + */ +struct atomisp_css_isys_config_info { + unsigned int input_format; + unsigned int width; + unsigned int height; +}; + +struct atomisp_stream_env { + struct ia_css_stream *stream; + struct ia_css_stream_config stream_config; + struct ia_css_stream_info stream_info; + struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM]; + struct ia_css_pipe *multi_pipes[IA_CSS_PIPE_ID_NUM]; + struct ia_css_pipe_config pipe_configs[IA_CSS_PIPE_ID_NUM]; + struct ia_css_pipe_extra_config pipe_extra_configs[IA_CSS_PIPE_ID_NUM]; + bool update_pipe[IA_CSS_PIPE_ID_NUM]; + enum atomisp_css_stream_state stream_state; + struct ia_css_stream *acc_stream; + enum atomisp_css_stream_state acc_stream_state; + struct ia_css_stream_config acc_stream_config; + unsigned int ch_id; /* virtual channel ID */ + unsigned int isys_configs; + struct atomisp_css_isys_config_info isys_info[MAX_STREAMS_PER_CHANNEL]; +}; + +struct atomisp_css_env { + struct ia_css_env isp_css_env; + struct ia_css_fw isp_css_fw; +}; + +struct atomisp_s3a_buf { + struct ia_css_isp_3a_statistics *s3a_data; + struct ia_css_isp_3a_statistics_map *s3a_map; + struct list_head list; +}; + +struct atomisp_dis_buf { + struct ia_css_isp_dvs_statistics *dis_data; + struct ia_css_isp_dvs_statistics_map *dvs_map; + struct list_head list; +}; + +struct atomisp_css_buffer { + struct ia_css_buffer css_buffer; +}; + +struct atomisp_css_event { + enum ia_css_pipe_id pipe; + struct ia_css_event event; +}; + +void atomisp_css_set_macc_config(struct atomisp_sub_device *asd, + struct ia_css_macc_config *macc_config); + +void atomisp_css_set_ecd_config(struct atomisp_sub_device *asd, + struct ia_css_ecd_config *ecd_config); + +void atomisp_css_set_ynr_config(struct atomisp_sub_device *asd, + struct ia_css_ynr_config *ynr_config); + +void atomisp_css_set_fc_config(struct atomisp_sub_device *asd, + struct ia_css_fc_config *fc_config); + +void atomisp_css_set_aa_config(struct atomisp_sub_device *asd, + struct ia_css_aa_config *aa_config); + +void atomisp_css_set_baa_config(struct atomisp_sub_device *asd, + struct ia_css_aa_config *baa_config); + +void atomisp_css_set_anr_config(struct atomisp_sub_device *asd, + struct ia_css_anr_config *anr_config); + +void atomisp_css_set_xnr_config(struct atomisp_sub_device *asd, + struct ia_css_xnr_config *xnr_config); + +void atomisp_css_set_cnr_config(struct atomisp_sub_device *asd, + struct ia_css_cnr_config *cnr_config); + +void atomisp_css_set_ctc_config(struct atomisp_sub_device *asd, + struct ia_css_ctc_config *ctc_config); + +void atomisp_css_set_yuv2rgb_cc_config(struct atomisp_sub_device *asd, + struct ia_css_cc_config *yuv2rgb_cc_config); + +void atomisp_css_set_rgb2yuv_cc_config(struct atomisp_sub_device *asd, + struct ia_css_cc_config *rgb2yuv_cc_config); + +void atomisp_css_set_anr_thres(struct atomisp_sub_device *asd, + struct ia_css_anr_thres *anr_thres); + +int atomisp_css_load_firmware(struct atomisp_device *isp); + +void atomisp_css_set_dvs_6axis(struct atomisp_sub_device *asd, + struct ia_css_dvs_6axis_config *dvs_6axis); + +int atomisp_css_debug_dump_isp_binary(void); + +int atomisp_css_dump_sp_raw_copy_linecount(bool reduced); + +int atomisp_css_dump_blob_infor(struct atomisp_device *isp); + +void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd, + uint32_t isp_config_id); + +void atomisp_css_set_isp_config_applied_frame(struct atomisp_sub_device *asd, + struct ia_css_frame *output_frame); + +int atomisp_get_css_dbgfunc(void); + +int atomisp_set_css_dbgfunc(struct atomisp_device *isp, int opt); +struct ia_css_dvs_grid_info *atomisp_css_get_dvs_grid_info( + struct ia_css_grid_info *grid_info); +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp_compat_ioctl32.h b/drivers/staging/media/atomisp/pci/atomisp_compat_ioctl32.h new file mode 100644 index 000000000..33821b51d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_compat_ioctl32.h @@ -0,0 +1,310 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef __ATOMISP_COMPAT_IOCTL32_H__ +#define __ATOMISP_COMPAT_IOCTL32_H__ + +#include +#include + +#include "atomisp_compat.h" + +struct atomisp_histogram32 { + unsigned int num_elements; + compat_uptr_t data; +}; + +struct atomisp_dvs2_stat_types32 { + compat_uptr_t odd_real; /** real part of the odd statistics*/ + compat_uptr_t odd_imag; /** imaginary part of the odd statistics*/ + compat_uptr_t even_real;/** real part of the even statistics*/ + compat_uptr_t even_imag;/** imaginary part of the even statistics*/ +}; + +struct atomisp_dvs2_coef_types32 { + compat_uptr_t odd_real; /** real part of the odd coefficients*/ + compat_uptr_t odd_imag; /** imaginary part of the odd coefficients*/ + compat_uptr_t even_real;/** real part of the even coefficients*/ + compat_uptr_t even_imag;/** imaginary part of the even coefficients*/ +}; + +struct atomisp_dvs2_statistics32 { + struct atomisp_dvs_grid_info grid_info; + struct atomisp_dvs2_stat_types32 hor_prod; + struct atomisp_dvs2_stat_types32 ver_prod; +}; + +struct atomisp_dis_statistics32 { + struct atomisp_dvs2_statistics32 dvs2_stat; + u32 exp_id; +}; + +struct atomisp_dis_coefficients32 { + struct atomisp_dvs_grid_info grid_info; + struct atomisp_dvs2_coef_types32 hor_coefs; + struct atomisp_dvs2_coef_types32 ver_coefs; +}; + +struct atomisp_3a_statistics32 { + struct atomisp_grid_info grid_info; + compat_uptr_t data; + compat_uptr_t rgby_data; + u32 exp_id; + u32 isp_config_id; +}; + +struct atomisp_metadata_with_type32 { + /* to specify which type of metadata to get */ + enum atomisp_metadata_type type; + compat_uptr_t data; + u32 width; + u32 height; + u32 stride; /* in bytes */ + u32 exp_id; /* exposure ID */ + compat_uptr_t effective_width; +}; + +struct atomisp_metadata32 { + compat_uptr_t data; + u32 width; + u32 height; + u32 stride; + u32 exp_id; + compat_uptr_t effective_width; +}; + +struct atomisp_morph_table32 { + unsigned int enabled; + unsigned int height; + unsigned int width; /* number of valid elements per line */ + compat_uptr_t coordinates_x[ATOMISP_MORPH_TABLE_NUM_PLANES]; + compat_uptr_t coordinates_y[ATOMISP_MORPH_TABLE_NUM_PLANES]; +}; + +struct v4l2_framebuffer32 { + __u32 capability; + __u32 flags; + compat_uptr_t base; + struct v4l2_pix_format fmt; +}; + +struct atomisp_overlay32 { + /* the frame containing the overlay data The overlay frame width should + * be the multiples of 2*ISP_VEC_NELEMS. The overlay frame height + * should be the multiples of 2. + */ + compat_uptr_t frame; + /* Y value of overlay background */ + unsigned char bg_y; + /* U value of overlay background */ + char bg_u; + /* V value of overlay background */ + char bg_v; + /* the blending percent of input data for Y subpixels */ + unsigned char blend_input_perc_y; + /* the blending percent of input data for U subpixels */ + unsigned char blend_input_perc_u; + /* the blending percent of input data for V subpixels */ + unsigned char blend_input_perc_v; + /* the blending percent of overlay data for Y subpixels */ + unsigned char blend_overlay_perc_y; + /* the blending percent of overlay data for U subpixels */ + unsigned char blend_overlay_perc_u; + /* the blending percent of overlay data for V subpixels */ + unsigned char blend_overlay_perc_v; + /* the overlay start x pixel position on output frame It should be the + multiples of 2*ISP_VEC_NELEMS. */ + unsigned int overlay_start_x; + /* the overlay start y pixel position on output frame It should be the + multiples of 2. */ + unsigned int overlay_start_y; +}; + +struct atomisp_calibration_group32 { + unsigned int size; + unsigned int type; + compat_uptr_t calb_grp_values; +}; + +struct v4l2_private_int_data32 { + __u32 size; + compat_uptr_t data; + __u32 reserved[2]; +}; + +struct atomisp_shading_table32 { + __u32 enable; + __u32 sensor_width; + __u32 sensor_height; + __u32 width; + __u32 height; + __u32 fraction_bits; + + compat_uptr_t data[ATOMISP_NUM_SC_COLORS]; +}; + +struct atomisp_parameters32 { + compat_uptr_t wb_config; /* White Balance config */ + compat_uptr_t cc_config; /* Color Correction config */ + compat_uptr_t tnr_config; /* Temporal Noise Reduction */ + compat_uptr_t ecd_config; /* Eigen Color Demosaicing */ + compat_uptr_t ynr_config; /* Y(Luma) Noise Reduction */ + compat_uptr_t fc_config; /* Fringe Control */ + compat_uptr_t formats_config; /* Formats Control */ + compat_uptr_t cnr_config; /* Chroma Noise Reduction */ + compat_uptr_t macc_config; /* MACC */ + compat_uptr_t ctc_config; /* Chroma Tone Control */ + compat_uptr_t aa_config; /* Anti-Aliasing */ + compat_uptr_t baa_config; /* Anti-Aliasing */ + compat_uptr_t ce_config; + compat_uptr_t dvs_6axis_config; + compat_uptr_t ob_config; /* Objective Black config */ + compat_uptr_t dp_config; /* Dead Pixel config */ + compat_uptr_t nr_config; /* Noise Reduction config */ + compat_uptr_t ee_config; /* Edge Enhancement config */ + compat_uptr_t de_config; /* Demosaic config */ + compat_uptr_t gc_config; /* Gamma Correction config */ + compat_uptr_t anr_config; /* Advanced Noise Reduction */ + compat_uptr_t a3a_config; /* 3A Statistics config */ + compat_uptr_t xnr_config; /* eXtra Noise Reduction */ + compat_uptr_t dz_config; /* Digital Zoom */ + compat_uptr_t yuv2rgb_cc_config; /* Color + Correction config */ + compat_uptr_t rgb2yuv_cc_config; /* Color + Correction config */ + compat_uptr_t macc_table; + compat_uptr_t gamma_table; + compat_uptr_t ctc_table; + compat_uptr_t xnr_table; + compat_uptr_t r_gamma_table; + compat_uptr_t g_gamma_table; + compat_uptr_t b_gamma_table; + compat_uptr_t motion_vector; /* For 2-axis DVS */ + compat_uptr_t shading_table; + compat_uptr_t morph_table; + compat_uptr_t dvs_coefs; /* DVS 1.0 coefficients */ + compat_uptr_t dvs2_coefs; /* DVS 2.0 coefficients */ + compat_uptr_t capture_config; + compat_uptr_t anr_thres; + + compat_uptr_t lin_2500_config; /* Skylake: Linearization config */ + compat_uptr_t obgrid_2500_config; /* Skylake: OBGRID config */ + compat_uptr_t bnr_2500_config; /* Skylake: bayer denoise config */ + compat_uptr_t shd_2500_config; /* Skylake: shading config */ + compat_uptr_t dm_2500_config; /* Skylake: demosaic config */ + compat_uptr_t rgbpp_2500_config; /* Skylake: RGBPP config */ + compat_uptr_t dvs_stat_2500_config; /* Skylake: DVS STAT config */ + compat_uptr_t lace_stat_2500_config; /* Skylake: LACE STAT config */ + compat_uptr_t yuvp1_2500_config; /* Skylake: yuvp1 config */ + compat_uptr_t yuvp2_2500_config; /* Skylake: yuvp2 config */ + compat_uptr_t tnr_2500_config; /* Skylake: TNR config */ + compat_uptr_t dpc_2500_config; /* Skylake: DPC config */ + compat_uptr_t awb_2500_config; /* Skylake: auto white balance config */ + compat_uptr_t + awb_fr_2500_config; /* Skylake: auto white balance filter response config */ + compat_uptr_t anr_2500_config; /* Skylake: ANR config */ + compat_uptr_t af_2500_config; /* Skylake: auto focus config */ + compat_uptr_t ae_2500_config; /* Skylake: auto exposure config */ + compat_uptr_t bds_2500_config; /* Skylake: bayer downscaler config */ + compat_uptr_t + dvs_2500_config; /* Skylake: digital video stabilization config */ + compat_uptr_t res_mgr_2500_config; + + /* + * Output frame pointer the config is to be applied to (optional), + * set to NULL to make this config is applied as global. + */ + compat_uptr_t output_frame; + /* + * Unique ID to track which config was actually applied to a particular + * frame, driver will send this id back with output frame together. + */ + u32 isp_config_id; + u32 per_frame_setting; +}; + +struct atomisp_dvs_6axis_config32 { + u32 exp_id; + u32 width_y; + u32 height_y; + u32 width_uv; + u32 height_uv; + compat_uptr_t xcoords_y; + compat_uptr_t ycoords_y; + compat_uptr_t xcoords_uv; + compat_uptr_t ycoords_uv; +}; + +struct atomisp_sensor_ae_bracketing_lut32 { + compat_uptr_t lut; + unsigned int lut_size; +}; + +#define ATOMISP_IOC_G_HISTOGRAM32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram32) +#define ATOMISP_IOC_S_HISTOGRAM32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram32) + +#define ATOMISP_IOC_G_DIS_STAT32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_statistics32) +#define ATOMISP_IOC_S_DIS_COEFS32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_coefficients32) + +#define ATOMISP_IOC_S_DIS_VECTOR32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dvs_6axis_config32) + +#define ATOMISP_IOC_G_3A_STAT32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 7, struct atomisp_3a_statistics32) + +#define ATOMISP_IOC_G_ISP_GDC_TAB32 \ + _IOR('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table32) +#define ATOMISP_IOC_S_ISP_GDC_TAB32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table32) + +#define ATOMISP_IOC_S_ISP_FPN_TABLE32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 17, struct v4l2_framebuffer32) + +#define ATOMISP_IOC_G_ISP_OVERLAY32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay32) +#define ATOMISP_IOC_S_ISP_OVERLAY32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay32) + +#define ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 22, struct atomisp_calibration_group32) + +#define ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 26, struct v4l2_private_int_data32) + +#define ATOMISP_IOC_S_ISP_SHD_TAB32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 27, struct atomisp_shading_table32) + +#define ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 29, struct v4l2_private_int_data32) + +#define ATOMISP_IOC_S_PARAMETERS32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 32, struct atomisp_parameters32) + +#define ATOMISP_IOC_G_METADATA32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata32) + +#define ATOMISP_IOC_G_METADATA_BY_TYPE32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata_with_type32) + +#define ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 43, struct atomisp_sensor_ae_bracketing_lut32) + +#endif /* __ATOMISP_COMPAT_IOCTL32_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_csi2.c b/drivers/staging/media/atomisp/pci/atomisp_csi2.c new file mode 100644 index 000000000..4a9268bac --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_csi2.c @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include "atomisp_cmd.h" +#include "atomisp_internal.h" +#include "atomisp-regs.h" + +static struct +v4l2_mbus_framefmt *__csi2_get_format(struct atomisp_mipi_csi2_device *csi2, + struct v4l2_subdev_state *sd_state, + enum v4l2_subdev_format_whence which, + unsigned int pad) +{ + if (which == V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_get_try_format(&csi2->subdev, sd_state, + pad); + else + return &csi2->formats[pad]; +} + +/* + * csi2_enum_mbus_code - Handle pixel format enumeration + * @sd : pointer to v4l2 subdev structure + * @fh : V4L2 subdev file handle + * @code : pointer to v4l2_subdev_pad_mbus_code_enum structure + * return -EINVAL or zero on success + */ +static int csi2_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + const struct atomisp_in_fmt_conv *ic = atomisp_in_fmt_conv; + unsigned int i = 0; + + while (ic->code) { + if (i == code->index) { + code->code = ic->code; + return 0; + } + i++, ic++; + } + + return -EINVAL; +} + +/* + * csi2_get_format - Handle get format by pads subdev method + * @sd : pointer to v4l2 subdev structure + * @fh : V4L2 subdev file handle + * @pad: pad num + * @fmt: pointer to v4l2 format structure + * return -EINVAL or zero on success + */ +static int csi2_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format = __csi2_get_format(csi2, sd_state, fmt->which, fmt->pad); + + fmt->format = *format; + + return 0; +} + +int atomisp_csi2_set_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + unsigned int which, uint16_t pad, + struct v4l2_mbus_framefmt *ffmt) +{ + struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *actual_ffmt = __csi2_get_format(csi2, + sd_state, + which, pad); + + if (pad == CSI2_PAD_SINK) { + const struct atomisp_in_fmt_conv *ic; + struct v4l2_mbus_framefmt tmp_ffmt; + + ic = atomisp_find_in_fmt_conv(ffmt->code); + if (ic) + actual_ffmt->code = ic->code; + else + actual_ffmt->code = atomisp_in_fmt_conv[0].code; + + actual_ffmt->width = clamp_t(u32, ffmt->width, + ATOM_ISP_MIN_WIDTH, + ATOM_ISP_MAX_WIDTH); + actual_ffmt->height = clamp_t(u32, ffmt->height, + ATOM_ISP_MIN_HEIGHT, + ATOM_ISP_MAX_HEIGHT); + + tmp_ffmt = *ffmt = *actual_ffmt; + + return atomisp_csi2_set_ffmt(sd, sd_state, which, + CSI2_PAD_SOURCE, + &tmp_ffmt); + } + + /* FIXME: DPCM decompression */ + *actual_ffmt = *ffmt = *__csi2_get_format(csi2, sd_state, which, + CSI2_PAD_SINK); + + return 0; +} + +/* + * csi2_set_format - Handle set format by pads subdev method + * @sd : pointer to v4l2 subdev structure + * @fh : V4L2 subdev file handle + * @pad: pad num + * @fmt: pointer to v4l2 format structure + * return -EINVAL or zero on success + */ +static int csi2_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + return atomisp_csi2_set_ffmt(sd, sd_state, fmt->which, fmt->pad, + &fmt->format); +} + +/* + * csi2_set_stream - Enable/Disable streaming on the CSI2 module + * @sd: ISP CSI2 V4L2 subdevice + * @enable: Enable/disable stream (1/0) + * + * Return 0 on success or a negative error code otherwise. + */ +static int csi2_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +/* subdev core operations */ +static const struct v4l2_subdev_core_ops csi2_core_ops = { +}; + +/* subdev video operations */ +static const struct v4l2_subdev_video_ops csi2_video_ops = { + .s_stream = csi2_set_stream, +}; + +/* subdev pad operations */ +static const struct v4l2_subdev_pad_ops csi2_pad_ops = { + .enum_mbus_code = csi2_enum_mbus_code, + .get_fmt = csi2_get_format, + .set_fmt = csi2_set_format, + .link_validate = v4l2_subdev_link_validate_default, +}; + +/* subdev operations */ +static const struct v4l2_subdev_ops csi2_ops = { + .core = &csi2_core_ops, + .video = &csi2_video_ops, + .pad = &csi2_pad_ops, +}; + +/* + * csi2_link_setup - Setup CSI2 connections. + * @entity : Pointer to media entity structure + * @local : Pointer to local pad array + * @remote : Pointer to remote pad array + * @flags : Link flags + * return -EINVAL or zero on success + */ +static int csi2_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); + struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd); + u32 result = local->index | is_media_entity_v4l2_subdev(remote->entity); + + switch (result) { + case CSI2_PAD_SOURCE | MEDIA_ENT_F_OLD_BASE: + /* not supported yet */ + return -EINVAL; + + case CSI2_PAD_SOURCE | MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN: + if (flags & MEDIA_LNK_FL_ENABLED) { + if (csi2->output & ~CSI2_OUTPUT_ISP_SUBDEV) + return -EBUSY; + csi2->output |= CSI2_OUTPUT_ISP_SUBDEV; + } else { + csi2->output &= ~CSI2_OUTPUT_ISP_SUBDEV; + } + break; + + default: + /* Link from camera to CSI2 is fixed... */ + return -EINVAL; + } + return 0; +} + +/* media operations */ +static const struct media_entity_operations csi2_media_ops = { + .link_setup = csi2_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +/* + * ispcsi2_init_entities - Initialize subdev and media entity. + * @csi2: Pointer to ispcsi2 structure. + * return -ENOMEM or zero on success + */ +static int mipi_csi2_init_entities(struct atomisp_mipi_csi2_device *csi2, + int port) +{ + struct v4l2_subdev *sd = &csi2->subdev; + struct media_pad *pads = csi2->pads; + struct media_entity *me = &sd->entity; + int ret; + + v4l2_subdev_init(sd, &csi2_ops); + snprintf(sd->name, sizeof(sd->name), "ATOM ISP CSI2-port%d", port); + + v4l2_set_subdevdata(sd, csi2); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + + pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + + me->ops = &csi2_media_ops; + me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; + ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads); + if (ret < 0) + return ret; + + csi2->formats[CSI2_PAD_SINK].code = atomisp_in_fmt_conv[0].code; + csi2->formats[CSI2_PAD_SOURCE].code = atomisp_in_fmt_conv[0].code; + + return 0; +} + +void +atomisp_mipi_csi2_unregister_entities(struct atomisp_mipi_csi2_device *csi2) +{ + media_entity_cleanup(&csi2->subdev.entity); + v4l2_device_unregister_subdev(&csi2->subdev); +} + +int atomisp_mipi_csi2_register_entities(struct atomisp_mipi_csi2_device *csi2, + struct v4l2_device *vdev) +{ + int ret; + + /* Register the subdev and video nodes. */ + ret = v4l2_device_register_subdev(vdev, &csi2->subdev); + if (ret < 0) + goto error; + + return 0; + +error: + atomisp_mipi_csi2_unregister_entities(csi2); + return ret; +} + +static const int LIMIT_SHIFT = 6; /* Limit numeric range into 31 bits */ + +static int +atomisp_csi2_configure_calc(const short int coeffs[2], int mipi_freq, int def) +{ + /* Delay counter accuracy, 1/0.0625 for ANN/CHT, 1/0.125 for BXT */ + static const int accinv = 16; /* 1 / COUNT_ACC */ + int r; + + if (mipi_freq >> LIMIT_SHIFT <= 0) + return def; + + r = accinv * coeffs[1] * (500000000 >> LIMIT_SHIFT); + r /= mipi_freq >> LIMIT_SHIFT; + r += accinv * coeffs[0]; + + return r; +} + +static void atomisp_csi2_configure_isp2401(struct atomisp_sub_device *asd) +{ + /* + * The ISP2401 new input system CSI2+ receiver has several + * parameters affecting the receiver timings. These depend + * on the MIPI bus frequency F in Hz (sensor transmitter rate) + * as follows: + * register value = (A/1e9 + B * UI) / COUNT_ACC + * where + * UI = 1 / (2 * F) in seconds + * COUNT_ACC = counter accuracy in seconds + * For ANN and CHV, COUNT_ACC = 0.0625 ns + * For BXT, COUNT_ACC = 0.125 ns + * A and B are coefficients from the table below, + * depending whether the register minimum or maximum value is + * calculated. + * Minimum Maximum + * Clock lane A B A B + * reg_rx_csi_dly_cnt_termen_clane 0 0 38 0 + * reg_rx_csi_dly_cnt_settle_clane 95 -8 300 -16 + * Data lanes + * reg_rx_csi_dly_cnt_termen_dlane0 0 0 35 4 + * reg_rx_csi_dly_cnt_settle_dlane0 85 -2 145 -6 + * reg_rx_csi_dly_cnt_termen_dlane1 0 0 35 4 + * reg_rx_csi_dly_cnt_settle_dlane1 85 -2 145 -6 + * reg_rx_csi_dly_cnt_termen_dlane2 0 0 35 4 + * reg_rx_csi_dly_cnt_settle_dlane2 85 -2 145 -6 + * reg_rx_csi_dly_cnt_termen_dlane3 0 0 35 4 + * reg_rx_csi_dly_cnt_settle_dlane3 85 -2 145 -6 + * + * We use the minimum values in the calculations below. + */ + static const short int coeff_clk_termen[] = { 0, 0 }; + static const short int coeff_clk_settle[] = { 95, -8 }; + static const short int coeff_dat_termen[] = { 0, 0 }; + static const short int coeff_dat_settle[] = { 85, -2 }; + static const int TERMEN_DEFAULT = 0 * 0; + static const int SETTLE_DEFAULT = 0x480; + + static const hrt_address csi2_port_base[] = { + [ATOMISP_CAMERA_PORT_PRIMARY] = CSI2_PORT_A_BASE, + [ATOMISP_CAMERA_PORT_SECONDARY] = CSI2_PORT_B_BASE, + [ATOMISP_CAMERA_PORT_TERTIARY] = CSI2_PORT_C_BASE, + }; + /* Number of lanes on each port, excluding clock lane */ + static const unsigned char csi2_port_lanes[] = { + [ATOMISP_CAMERA_PORT_PRIMARY] = 4, + [ATOMISP_CAMERA_PORT_SECONDARY] = 2, + [ATOMISP_CAMERA_PORT_TERTIARY] = 2, + }; + static const hrt_address csi2_lane_base[] = { + CSI2_LANE_CL_BASE, + CSI2_LANE_D0_BASE, + CSI2_LANE_D1_BASE, + CSI2_LANE_D2_BASE, + CSI2_LANE_D3_BASE, + }; + + int clk_termen; + int clk_settle; + int dat_termen; + int dat_settle; + + struct v4l2_control ctrl; + struct atomisp_device *isp = asd->isp; + struct camera_mipi_info *mipi_info; + int mipi_freq = 0; + enum atomisp_camera_port port; + + int n; + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + port = mipi_info->port; + + ctrl.id = V4L2_CID_LINK_FREQ; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl) == 0) + mipi_freq = ctrl.value; + + clk_termen = atomisp_csi2_configure_calc(coeff_clk_termen, mipi_freq, + TERMEN_DEFAULT); + clk_settle = atomisp_csi2_configure_calc(coeff_clk_settle, mipi_freq, + SETTLE_DEFAULT); + dat_termen = atomisp_csi2_configure_calc(coeff_dat_termen, mipi_freq, + TERMEN_DEFAULT); + dat_settle = atomisp_csi2_configure_calc(coeff_dat_settle, mipi_freq, + SETTLE_DEFAULT); + + for (n = 0; n < csi2_port_lanes[port] + 1; n++) { + hrt_address base = csi2_port_base[port] + csi2_lane_base[n]; + + atomisp_css2_hw_store_32(base + CSI2_REG_RX_CSI_DLY_CNT_TERMEN, + n == 0 ? clk_termen : dat_termen); + atomisp_css2_hw_store_32(base + CSI2_REG_RX_CSI_DLY_CNT_SETTLE, + n == 0 ? clk_settle : dat_settle); + } +} + +void atomisp_csi2_configure(struct atomisp_sub_device *asd) +{ + if (IS_HWREVISION(asd->isp, ATOMISP_HW_REVISION_ISP2401)) + atomisp_csi2_configure_isp2401(asd); +} + +/* + * atomisp_mipi_csi2_cleanup - Routine for module driver cleanup + */ +void atomisp_mipi_csi2_cleanup(struct atomisp_device *isp) +{ +} + +int atomisp_mipi_csi2_init(struct atomisp_device *isp) +{ + struct atomisp_mipi_csi2_device *csi2_port; + unsigned int i; + int ret; + + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { + csi2_port = &isp->csi2_port[i]; + csi2_port->isp = isp; + ret = mipi_csi2_init_entities(csi2_port, i); + if (ret < 0) + goto fail; + } + + return 0; + +fail: + atomisp_mipi_csi2_cleanup(isp); + return ret; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp_csi2.h b/drivers/staging/media/atomisp/pci/atomisp_csi2.h new file mode 100644 index 000000000..e35711be8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_csi2.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef __ATOMISP_CSI2_H__ +#define __ATOMISP_CSI2_H__ + +#include +#include + +#define CSI2_PAD_SINK 0 +#define CSI2_PAD_SOURCE 1 +#define CSI2_PADS_NUM 2 + +#define CSI2_OUTPUT_ISP_SUBDEV BIT(0) +#define CSI2_OUTPUT_MEMORY BIT(1) + +struct atomisp_device; +struct v4l2_device; +struct atomisp_sub_device; + +struct atomisp_mipi_csi2_device { + struct v4l2_subdev subdev; + struct media_pad pads[CSI2_PADS_NUM]; + struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM]; + + struct v4l2_ctrl_handler ctrls; + struct atomisp_device *isp; + + u32 output; /* output direction */ +}; + +int atomisp_csi2_set_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + unsigned int which, uint16_t pad, + struct v4l2_mbus_framefmt *ffmt); +int atomisp_mipi_csi2_init(struct atomisp_device *isp); +void atomisp_mipi_csi2_cleanup(struct atomisp_device *isp); +void atomisp_mipi_csi2_unregister_entities( + struct atomisp_mipi_csi2_device *csi2); +int atomisp_mipi_csi2_register_entities(struct atomisp_mipi_csi2_device *csi2, + struct v4l2_device *vdev); + +void atomisp_csi2_configure(struct atomisp_sub_device *asd); + +#endif /* __ATOMISP_CSI2_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_dfs_tables.h b/drivers/staging/media/atomisp/pci/atomisp_dfs_tables.h new file mode 100644 index 000000000..8f1cc3fca --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_dfs_tables.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef __ATOMISP_DFS_TABLES_H__ +#define __ATOMISP_DFS_TABLES_H__ + +#include + +struct atomisp_freq_scaling_rule { + unsigned int width; + unsigned int height; + unsigned short fps; + unsigned int isp_freq; + unsigned int run_mode; +}; + +struct atomisp_dfs_config { + unsigned int lowest_freq; + unsigned int max_freq_at_vmin; + unsigned int highest_freq; + const struct atomisp_freq_scaling_rule *dfs_table; + unsigned int dfs_table_size; +}; + +extern const struct atomisp_dfs_config dfs_config_cht_soc; + +#endif /* __ATOMISP_DFS_TABLES_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_drvfs.c b/drivers/staging/media/atomisp/pci/atomisp_drvfs.c new file mode 100644 index 000000000..3ddc935ec --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_drvfs.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for atomisp driver sysfs interface + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include + +#include "atomisp_compat.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" +#include "atomisp_drvfs.h" +#include "hmm/hmm.h" +#include "ia_css_debug.h" + +/* + * _iunit_debug: + * dbglvl: iunit css driver trace level + * dbgopt: iunit debug option: + * bit 0: binary list + * bit 1: running binary + * bit 2: memory statistic +*/ +struct _iunit_debug { + struct device_driver *drv; + struct atomisp_device *isp; + unsigned int dbglvl; + unsigned int dbgfun; + unsigned int dbgopt; +}; + +#define OPTION_BIN_LIST BIT(0) +#define OPTION_BIN_RUN BIT(1) +#define OPTION_VALID (OPTION_BIN_LIST \ + | OPTION_BIN_RUN) + +static struct _iunit_debug iunit_debug = { + .dbglvl = 0, + .dbgopt = OPTION_BIN_LIST, +}; + +static inline int iunit_dump_dbgopt(struct atomisp_device *isp, + unsigned int opt) +{ + int ret = 0; + + if (opt & OPTION_VALID) { + if (opt & OPTION_BIN_LIST) { + ret = atomisp_css_dump_blob_infor(isp); + if (ret) { + dev_err(isp->dev, "%s dump blob infor err[ret:%d]\n", + __func__, ret); + goto opt_err; + } + } + + if (opt & OPTION_BIN_RUN) { + if (atomisp_streaming_count(isp)) { + atomisp_css_dump_sp_raw_copy_linecount(true); + atomisp_css_debug_dump_isp_binary(); + } else { + ret = -EPERM; + dev_err(isp->dev, "%s dump running bin err[ret:%d]\n", + __func__, ret); + goto opt_err; + } + } + } else { + ret = -EINVAL; + dev_err(isp->dev, "%s dump nothing[ret=%d]\n", __func__, ret); + } + +opt_err: + return ret; +} + +static ssize_t iunit_dbglvl_show(struct device_driver *drv, char *buf) +{ + iunit_debug.dbglvl = dbg_level; + return sysfs_emit(buf, "dtrace level:%u\n", iunit_debug.dbglvl); +} + +static ssize_t iunit_dbglvl_store(struct device_driver *drv, const char *buf, + size_t size) +{ + if (kstrtouint(buf, 10, &iunit_debug.dbglvl) + || iunit_debug.dbglvl < 1 + || iunit_debug.dbglvl > 9) { + return -ERANGE; + } + ia_css_debug_set_dtrace_level(iunit_debug.dbglvl); + + return size; +} + +static ssize_t iunit_dbgfun_show(struct device_driver *drv, char *buf) +{ + iunit_debug.dbgfun = atomisp_get_css_dbgfunc(); + return sysfs_emit(buf, "dbgfun opt:%u\n", iunit_debug.dbgfun); +} + +static ssize_t iunit_dbgfun_store(struct device_driver *drv, const char *buf, + size_t size) +{ + unsigned int opt; + int ret; + + ret = kstrtouint(buf, 10, &opt); + if (ret) + return ret; + + ret = atomisp_set_css_dbgfunc(iunit_debug.isp, opt); + if (ret) + return ret; + + iunit_debug.dbgfun = opt; + + return size; +} + +static ssize_t iunit_dbgopt_show(struct device_driver *drv, char *buf) +{ + return sysfs_emit(buf, "option:0x%x\n", iunit_debug.dbgopt); +} + +static ssize_t iunit_dbgopt_store(struct device_driver *drv, const char *buf, + size_t size) +{ + unsigned int opt; + int ret; + + ret = kstrtouint(buf, 10, &opt); + if (ret) + return ret; + + iunit_debug.dbgopt = opt; + ret = iunit_dump_dbgopt(iunit_debug.isp, iunit_debug.dbgopt); + if (ret) + return ret; + + return size; +} + +static const struct driver_attribute iunit_drvfs_attrs[] = { + __ATTR(dbglvl, 0644, iunit_dbglvl_show, iunit_dbglvl_store), + __ATTR(dbgfun, 0644, iunit_dbgfun_show, iunit_dbgfun_store), + __ATTR(dbgopt, 0644, iunit_dbgopt_show, iunit_dbgopt_store), +}; + +static int iunit_drvfs_create_files(struct device_driver *drv) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(iunit_drvfs_attrs); i++) + ret |= driver_create_file(drv, &iunit_drvfs_attrs[i]); + + return ret; +} + +static void iunit_drvfs_remove_files(struct device_driver *drv) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(iunit_drvfs_attrs); i++) + driver_remove_file(drv, &iunit_drvfs_attrs[i]); +} + +int atomisp_drvfs_init(struct atomisp_device *isp) +{ + struct device_driver *drv = isp->dev->driver; + int ret; + + iunit_debug.isp = isp; + iunit_debug.drv = drv; + + ret = iunit_drvfs_create_files(iunit_debug.drv); + if (ret) { + dev_err(isp->dev, "drvfs_create_files error: %d\n", ret); + iunit_drvfs_remove_files(iunit_debug.drv); + } + + return ret; +} + +void atomisp_drvfs_exit(void) +{ + iunit_drvfs_remove_files(iunit_debug.drv); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp_drvfs.h b/drivers/staging/media/atomisp/pci/atomisp_drvfs.h new file mode 100644 index 000000000..8f4cc722b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_drvfs.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for atomisp driver sysfs interface. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_DRVFS_H__ +#define __ATOMISP_DRVFS_H__ + +int atomisp_drvfs_init(struct atomisp_device *isp); +void atomisp_drvfs_exit(void); + +#endif /* __ATOMISP_DRVFS_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_fops.c b/drivers/staging/media/atomisp/pci/atomisp_fops.c new file mode 100644 index 000000000..acea74928 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_fops.c @@ -0,0 +1,941 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include + +#include +#include + +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_fops.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" +#include "atomisp_compat.h" +#include "atomisp_subdev.h" +#include "atomisp_v4l2.h" +#include "atomisp-regs.h" +#include "hmm/hmm.h" + +#include "ia_css_frame.h" +#include "type_support.h" +#include "device_access/device_access.h" + +/* + * Videobuf2 ops + */ +static int atomisp_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct atomisp_video_pipe *pipe = container_of(vq, struct atomisp_video_pipe, vb_queue); + u16 source_pad = atomisp_subdev_source_pad(&pipe->vdev); + int ret; + + mutex_lock(&pipe->asd->isp->mutex); /* for get_css_frame_info() / set_fmt() */ + + /* + * When VIDIOC_S_FMT has not been called before VIDIOC_REQBUFS, then + * this will fail. Call atomisp_set_fmt() ourselves and try again. + */ + ret = atomisp_get_css_frame_info(pipe->asd, source_pad, &pipe->frame_info); + if (ret) { + struct v4l2_format f = { + .fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420, + .fmt.pix.width = 10000, + .fmt.pix.height = 10000, + }; + + ret = atomisp_set_fmt(&pipe->vdev, &f); + if (ret) + goto out; + + ret = atomisp_get_css_frame_info(pipe->asd, source_pad, &pipe->frame_info); + if (ret) + goto out; + } + + atomisp_alloc_css_stat_bufs(pipe->asd, ATOMISP_INPUT_STREAM_GENERAL); + + *nplanes = 1; + sizes[0] = PAGE_ALIGN(pipe->pix.sizeimage); + +out: + mutex_unlock(&pipe->asd->isp->mutex); + return 0; +} + +static int atomisp_buf_init(struct vb2_buffer *vb) +{ + struct atomisp_video_pipe *pipe = vb_to_pipe(vb); + struct ia_css_frame *frame = vb_to_frame(vb); + int ret; + + ret = ia_css_frame_init_from_info(frame, &pipe->frame_info); + if (ret) + return ret; + + if (frame->data_bytes > vb2_plane_size(vb, 0)) { + dev_err(pipe->asd->isp->dev, "Internal error frame.data_bytes(%u) > vb.length(%lu)\n", + frame->data_bytes, vb2_plane_size(vb, 0)); + return -EIO; + } + + frame->data = hmm_create_from_vmalloc_buf(vb2_plane_size(vb, 0), + vb2_plane_vaddr(vb, 0)); + if (frame->data == mmgr_NULL) + return -ENOMEM; + + return 0; +} + +static int atomisp_q_one_metadata_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id) +{ + struct atomisp_metadata_buf *metadata_buf; + enum atomisp_metadata_type md_type = + atomisp_get_metadata_type(asd, css_pipe_id); + struct list_head *metadata_list; + + if (asd->metadata_bufs_in_css[stream_id][css_pipe_id] >= + ATOMISP_CSS_Q_DEPTH) + return 0; /* we have reached CSS queue depth */ + + if (!list_empty(&asd->metadata[md_type])) { + metadata_list = &asd->metadata[md_type]; + } else if (!list_empty(&asd->metadata_ready[md_type])) { + metadata_list = &asd->metadata_ready[md_type]; + } else { + dev_warn(asd->isp->dev, "%s: No metadata buffers available for type %d!\n", + __func__, md_type); + return -EINVAL; + } + + metadata_buf = list_entry(metadata_list->next, + struct atomisp_metadata_buf, list); + list_del_init(&metadata_buf->list); + + if (atomisp_q_metadata_buffer_to_css(asd, metadata_buf, + stream_id, css_pipe_id)) { + list_add(&metadata_buf->list, metadata_list); + return -EINVAL; + } else { + list_add_tail(&metadata_buf->list, + &asd->metadata_in_css[md_type]); + } + asd->metadata_bufs_in_css[stream_id][css_pipe_id]++; + + return 0; +} + +static int atomisp_q_one_s3a_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id) +{ + struct atomisp_s3a_buf *s3a_buf; + struct list_head *s3a_list; + unsigned int exp_id; + + if (asd->s3a_bufs_in_css[css_pipe_id] >= ATOMISP_CSS_Q_DEPTH) + return 0; /* we have reached CSS queue depth */ + + if (!list_empty(&asd->s3a_stats)) { + s3a_list = &asd->s3a_stats; + } else if (!list_empty(&asd->s3a_stats_ready)) { + s3a_list = &asd->s3a_stats_ready; + } else { + dev_warn(asd->isp->dev, "%s: No s3a buffers available!\n", + __func__); + return -EINVAL; + } + + s3a_buf = list_entry(s3a_list->next, struct atomisp_s3a_buf, list); + list_del_init(&s3a_buf->list); + exp_id = s3a_buf->s3a_data->exp_id; + + hmm_flush_vmap(s3a_buf->s3a_data->data_ptr); + if (atomisp_q_s3a_buffer_to_css(asd, s3a_buf, + stream_id, css_pipe_id)) { + /* got from head, so return back to the head */ + list_add(&s3a_buf->list, s3a_list); + return -EINVAL; + } else { + list_add_tail(&s3a_buf->list, &asd->s3a_stats_in_css); + if (s3a_list == &asd->s3a_stats_ready) + dev_dbg(asd->isp->dev, "drop one s3a stat with exp_id %d\n", exp_id); + } + + asd->s3a_bufs_in_css[css_pipe_id]++; + return 0; +} + +static int atomisp_q_one_dis_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum ia_css_pipe_id css_pipe_id) +{ + struct atomisp_dis_buf *dis_buf; + unsigned long irqflags; + + if (asd->dis_bufs_in_css >= ATOMISP_CSS_Q_DEPTH) + return 0; /* we have reached CSS queue depth */ + + spin_lock_irqsave(&asd->dis_stats_lock, irqflags); + if (list_empty(&asd->dis_stats)) { + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + dev_warn(asd->isp->dev, "%s: No dis buffers available!\n", + __func__); + return -EINVAL; + } + + dis_buf = list_entry(asd->dis_stats.prev, + struct atomisp_dis_buf, list); + list_del_init(&dis_buf->list); + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + + hmm_flush_vmap(dis_buf->dis_data->data_ptr); + if (atomisp_q_dis_buffer_to_css(asd, dis_buf, + stream_id, css_pipe_id)) { + spin_lock_irqsave(&asd->dis_stats_lock, irqflags); + /* got from tail, so return back to the tail */ + list_add_tail(&dis_buf->list, &asd->dis_stats); + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + return -EINVAL; + } else { + spin_lock_irqsave(&asd->dis_stats_lock, irqflags); + list_add_tail(&dis_buf->list, &asd->dis_stats_in_css); + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + } + + asd->dis_bufs_in_css++; + + return 0; +} + +static int atomisp_q_video_buffers_to_css(struct atomisp_sub_device *asd, + struct atomisp_video_pipe *pipe, + enum atomisp_input_stream_id stream_id, + enum ia_css_buffer_type css_buf_type, + enum ia_css_pipe_id css_pipe_id) +{ + struct atomisp_css_params_with_list *param; + struct ia_css_dvs_grid_info *dvs_grid = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + unsigned long irqflags; + int space, err = 0; + + lockdep_assert_held(&asd->isp->mutex); + + if (WARN_ON(css_pipe_id >= IA_CSS_PIPE_ID_NUM)) + return -EINVAL; + + if (pipe->stopping) + return -EINVAL; + + space = ATOMISP_CSS_Q_DEPTH - atomisp_buffers_in_css(pipe); + while (space--) { + struct ia_css_frame *frame; + + spin_lock_irqsave(&pipe->irq_lock, irqflags); + frame = list_first_entry_or_null(&pipe->activeq, struct ia_css_frame, queue); + if (frame) + list_move_tail(&frame->queue, &pipe->buffers_in_css); + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + + if (!frame) + return -EINVAL; + + /* + * If there is a per_frame setting to apply on the buffer, + * do it before buffer en-queueing. + */ + param = pipe->frame_params[frame->vb.vb2_buf.index]; + if (param) { + atomisp_makeup_css_parameters(asd, + &asd->params.css_param.update_flag, + ¶m->params); + atomisp_apply_css_parameters(asd, ¶m->params); + + if (param->params.update_flag.dz_config && + asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO) { + err = atomisp_calculate_real_zoom_region(asd, + ¶m->params.dz_config, css_pipe_id); + if (!err) + asd->params.config.dz_config = ¶m->params.dz_config; + } + atomisp_css_set_isp_config_applied_frame(asd, frame); + atomisp_css_update_isp_params_on_pipe(asd, + asd->stream_env[stream_id].pipes[css_pipe_id]); + asd->params.dvs_6axis = (struct ia_css_dvs_6axis_config *) + param->params.dvs_6axis; + + /* + * WORKAROUND: + * Because the camera halv3 can't ensure to set zoom + * region to per_frame setting and global setting at + * same time and only set zoom region to pre_frame + * setting now.so when the pre_frame setting include + * zoom region,I will set it to global setting. + */ + if (param->params.update_flag.dz_config && + asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO + && !err) { + memcpy(&asd->params.css_param.dz_config, + ¶m->params.dz_config, + sizeof(struct ia_css_dz_config)); + asd->params.css_param.update_flag.dz_config = + (struct atomisp_dz_config *) + &asd->params.css_param.dz_config; + asd->params.css_update_params_needed = true; + } + pipe->frame_params[frame->vb.vb2_buf.index] = NULL; + } + /* Enqueue buffer */ + err = atomisp_q_video_buffer_to_css(asd, frame, stream_id, + css_buf_type, css_pipe_id); + if (err) { + spin_lock_irqsave(&pipe->irq_lock, irqflags); + list_move_tail(&frame->queue, &pipe->activeq); + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + dev_err(asd->isp->dev, "%s, css q fails: %d\n", + __func__, err); + return -EINVAL; + } + + /* enqueue 3A/DIS/metadata buffers */ + if (asd->params.curr_grid_info.s3a_grid.enable && + css_pipe_id == asd->params.s3a_enabled_pipe && + css_buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) + atomisp_q_one_s3a_buffer(asd, stream_id, + css_pipe_id); + + if (asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream_info. + metadata_info.size && + css_buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) + atomisp_q_one_metadata_buffer(asd, stream_id, + css_pipe_id); + + if (dvs_grid && dvs_grid->enable && + css_pipe_id == IA_CSS_PIPE_ID_VIDEO && + css_buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) + atomisp_q_one_dis_buffer(asd, stream_id, + css_pipe_id); + } + + return 0; +} + +static int atomisp_get_css_buf_type(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id, + uint16_t source_pad) +{ + if (ATOMISP_USE_YUVPP(asd)) { + /* when run ZSL case */ + if (asd->continuous_mode->val && + asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW) { + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) + return IA_CSS_BUFFER_TYPE_OUTPUT_FRAME; + else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) + return IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME; + else + return IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME; + } + + /*when run SDV case*/ + if (asd->continuous_mode->val && + asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) + return IA_CSS_BUFFER_TYPE_OUTPUT_FRAME; + else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) + return IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME; + else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) + return IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME; + else + return IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME; + } + + /*other case: default setting*/ + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO || + (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW && + asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO)) + return IA_CSS_BUFFER_TYPE_OUTPUT_FRAME; + else + return IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME; + } + + if (pipe_id == IA_CSS_PIPE_ID_COPY || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO || + (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW && + asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO)) + return IA_CSS_BUFFER_TYPE_OUTPUT_FRAME; + else + return IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME; +} + +/* queue all available buffers to css */ +int atomisp_qbuffers_to_css(struct atomisp_sub_device *asd) +{ + enum ia_css_buffer_type buf_type; + enum ia_css_pipe_id css_capture_pipe_id = IA_CSS_PIPE_ID_NUM; + enum ia_css_pipe_id css_preview_pipe_id = IA_CSS_PIPE_ID_NUM; + enum ia_css_pipe_id css_video_pipe_id = IA_CSS_PIPE_ID_NUM; + enum atomisp_input_stream_id input_stream_id; + struct atomisp_video_pipe *capture_pipe = NULL; + struct atomisp_video_pipe *vf_pipe = NULL; + struct atomisp_video_pipe *preview_pipe = NULL; + struct atomisp_video_pipe *video_pipe = NULL; + bool raw_mode = atomisp_is_mbuscode_raw( + asd->fmt[asd->capture_pad].fmt.code); + + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + video_pipe = &asd->video_out_video_capture; + css_video_pipe_id = IA_CSS_PIPE_ID_VIDEO; + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + preview_pipe = &asd->video_out_capture; + css_preview_pipe_id = IA_CSS_PIPE_ID_CAPTURE; + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + if (asd->continuous_mode->val) { + capture_pipe = &asd->video_out_capture; + vf_pipe = &asd->video_out_vf; + css_capture_pipe_id = IA_CSS_PIPE_ID_CAPTURE; + } + video_pipe = &asd->video_out_video_capture; + preview_pipe = &asd->video_out_preview; + css_video_pipe_id = IA_CSS_PIPE_ID_VIDEO; + css_preview_pipe_id = IA_CSS_PIPE_ID_VIDEO; + } else if (asd->continuous_mode->val) { + capture_pipe = &asd->video_out_capture; + vf_pipe = &asd->video_out_vf; + preview_pipe = &asd->video_out_preview; + + css_preview_pipe_id = IA_CSS_PIPE_ID_PREVIEW; + css_capture_pipe_id = IA_CSS_PIPE_ID_CAPTURE; + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW) { + preview_pipe = &asd->video_out_preview; + css_preview_pipe_id = IA_CSS_PIPE_ID_PREVIEW; + } else { + /* ATOMISP_RUN_MODE_STILL_CAPTURE */ + capture_pipe = &asd->video_out_capture; + if (!raw_mode) + vf_pipe = &asd->video_out_vf; + css_capture_pipe_id = IA_CSS_PIPE_ID_CAPTURE; + } + + if (IS_ISP2401 && asd->copy_mode) { + css_capture_pipe_id = IA_CSS_PIPE_ID_COPY; + css_preview_pipe_id = IA_CSS_PIPE_ID_COPY; + css_video_pipe_id = IA_CSS_PIPE_ID_COPY; + } + + if (asd->yuvpp_mode) { + capture_pipe = &asd->video_out_capture; + video_pipe = &asd->video_out_video_capture; + preview_pipe = &asd->video_out_preview; + css_capture_pipe_id = IA_CSS_PIPE_ID_COPY; + css_video_pipe_id = IA_CSS_PIPE_ID_YUVPP; + css_preview_pipe_id = IA_CSS_PIPE_ID_YUVPP; + } + + if (capture_pipe) { + buf_type = atomisp_get_css_buf_type( + asd, css_capture_pipe_id, + atomisp_subdev_source_pad(&capture_pipe->vdev)); + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + + /* + * use yuvpp pipe for SOC camera. + */ + if (ATOMISP_USE_YUVPP(asd)) + css_capture_pipe_id = IA_CSS_PIPE_ID_YUVPP; + + atomisp_q_video_buffers_to_css(asd, capture_pipe, + input_stream_id, + buf_type, css_capture_pipe_id); + } + + if (vf_pipe) { + buf_type = atomisp_get_css_buf_type( + asd, css_capture_pipe_id, + atomisp_subdev_source_pad(&vf_pipe->vdev)); + if (asd->stream_env[ATOMISP_INPUT_STREAM_POSTVIEW].stream) + input_stream_id = ATOMISP_INPUT_STREAM_POSTVIEW; + else + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + + /* + * use yuvpp pipe for SOC camera. + */ + if (ATOMISP_USE_YUVPP(asd)) + css_capture_pipe_id = IA_CSS_PIPE_ID_YUVPP; + atomisp_q_video_buffers_to_css(asd, vf_pipe, + input_stream_id, + buf_type, css_capture_pipe_id); + } + + if (preview_pipe) { + buf_type = atomisp_get_css_buf_type( + asd, css_preview_pipe_id, + atomisp_subdev_source_pad(&preview_pipe->vdev)); + if (ATOMISP_SOC_CAMERA(asd) && css_preview_pipe_id == IA_CSS_PIPE_ID_YUVPP) + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + /* else for ext isp use case */ + else if (css_preview_pipe_id == IA_CSS_PIPE_ID_YUVPP) + input_stream_id = ATOMISP_INPUT_STREAM_VIDEO; + else if (asd->stream_env[ATOMISP_INPUT_STREAM_PREVIEW].stream) + input_stream_id = ATOMISP_INPUT_STREAM_PREVIEW; + else + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + + /* + * use yuvpp pipe for SOC camera. + */ + if (ATOMISP_USE_YUVPP(asd)) + css_preview_pipe_id = IA_CSS_PIPE_ID_YUVPP; + + atomisp_q_video_buffers_to_css(asd, preview_pipe, + input_stream_id, + buf_type, css_preview_pipe_id); + } + + if (video_pipe) { + buf_type = atomisp_get_css_buf_type( + asd, css_video_pipe_id, + atomisp_subdev_source_pad(&video_pipe->vdev)); + if (asd->stream_env[ATOMISP_INPUT_STREAM_VIDEO].stream) + input_stream_id = ATOMISP_INPUT_STREAM_VIDEO; + else + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + + /* + * use yuvpp pipe for SOC camera. + */ + if (ATOMISP_USE_YUVPP(asd)) + css_video_pipe_id = IA_CSS_PIPE_ID_YUVPP; + + atomisp_q_video_buffers_to_css(asd, video_pipe, + input_stream_id, + buf_type, css_video_pipe_id); + } + + return 0; +} + +static void atomisp_buf_queue(struct vb2_buffer *vb) +{ + struct atomisp_video_pipe *pipe = vb_to_pipe(vb); + struct ia_css_frame *frame = vb_to_frame(vb); + struct atomisp_sub_device *asd = pipe->asd; + u16 source_pad = atomisp_subdev_source_pad(&pipe->vdev); + unsigned long irqflags; + int ret; + + mutex_lock(&asd->isp->mutex); + + ret = atomisp_pipe_check(pipe, false); + if (ret || pipe->stopping) { + spin_lock_irqsave(&pipe->irq_lock, irqflags); + atomisp_buffer_done(frame, VB2_BUF_STATE_ERROR); + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + goto out_unlock; + } + + /* FIXME this ugliness comes from the original atomisp buffer handling */ + if (!(vb->skip_cache_sync_on_finish && vb->skip_cache_sync_on_prepare)) + wbinvd(); + + pipe->frame_params[vb->index] = NULL; + + spin_lock_irqsave(&pipe->irq_lock, irqflags); + /* + * when a frame buffer meets following conditions, it should be put into + * the waiting list: + * 1. It is not a main output frame, and it has a per-frame parameter + * to go with it. + * 2. It is not a main output frame, and the waiting buffer list is not + * empty, to keep the FIFO sequence of frame buffer processing, it + * is put to waiting list until previous per-frame parameter buffers + * get enqueued. + */ + if (!atomisp_is_vf_pipe(pipe) && + (pipe->frame_request_config_id[vb->index] || + !list_empty(&pipe->buffers_waiting_for_param))) + list_add_tail(&frame->queue, &pipe->buffers_waiting_for_param); + else + list_add_tail(&frame->queue, &pipe->activeq); + + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + + /* TODO: do this better, not best way to queue to css */ + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED) { + if (!list_empty(&pipe->buffers_waiting_for_param)) + atomisp_handle_parameter_and_buffer(pipe); + else + atomisp_qbuffers_to_css(asd); + } + + /* + * Workaround: Due to the design of HALv3, + * sometimes in ZSL or SDV mode HAL needs to + * capture multiple images within one streaming cycle. + * But the capture number cannot be determined by HAL. + * So HAL only sets the capture number to be 1 and queue multiple + * buffers. Atomisp driver needs to check this case and re-trigger + * CSS to do capture when new buffer is queued. + */ + if (asd->continuous_mode->val && source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE && + !asd->enable_raw_buffer_lock->val && asd->params.offline_parm.num_captures == 1) { + asd->pending_capture_request++; + dev_dbg(asd->isp->dev, "Add one pending capture request.\n"); + } + +out_unlock: + mutex_unlock(&asd->isp->mutex); +} + +static void atomisp_buf_cleanup(struct vb2_buffer *vb) +{ + struct atomisp_video_pipe *pipe = vb_to_pipe(vb); + struct ia_css_frame *frame = vb_to_frame(vb); + int index = frame->vb.vb2_buf.index; + + pipe->frame_request_config_id[index] = 0; + pipe->frame_params[index] = NULL; + + hmm_free(frame->data); +} + +static const struct vb2_ops atomisp_vb2_ops = { + .queue_setup = atomisp_queue_setup, + .buf_init = atomisp_buf_init, + .buf_cleanup = atomisp_buf_cleanup, + .buf_queue = atomisp_buf_queue, + .start_streaming = atomisp_start_streaming, + .stop_streaming = atomisp_stop_streaming, +}; + +static int atomisp_init_pipe(struct atomisp_video_pipe *pipe) +{ + int ret; + + /* init locks */ + spin_lock_init(&pipe->irq_lock); + mutex_init(&pipe->vb_queue_mutex); + + /* Init videobuf2 queue structure */ + pipe->vb_queue.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + pipe->vb_queue.io_modes = VB2_MMAP | VB2_USERPTR; + pipe->vb_queue.buf_struct_size = sizeof(struct ia_css_frame); + pipe->vb_queue.ops = &atomisp_vb2_ops; + pipe->vb_queue.mem_ops = &vb2_vmalloc_memops; + pipe->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + ret = vb2_queue_init(&pipe->vb_queue); + if (ret) + return ret; + + pipe->vdev.queue = &pipe->vb_queue; + pipe->vdev.queue->lock = &pipe->vb_queue_mutex; + + INIT_LIST_HEAD(&pipe->activeq); + INIT_LIST_HEAD(&pipe->buffers_waiting_for_param); + INIT_LIST_HEAD(&pipe->per_frame_params); + memset(pipe->frame_request_config_id, 0, + VIDEO_MAX_FRAME * sizeof(unsigned int)); + memset(pipe->frame_params, 0, + VIDEO_MAX_FRAME * + sizeof(struct atomisp_css_params_with_list *)); + + return 0; +} + +static void atomisp_dev_init_struct(struct atomisp_device *isp) +{ + unsigned int i; + + isp->need_gfx_throttle = true; + isp->isp_fatal_error = false; + isp->mipi_frame_size = 0; + + for (i = 0; i < isp->input_cnt; i++) + isp->inputs[i].asd = NULL; + /* + * For Merrifield, frequency is scalable. + * After boot-up, the default frequency is 200MHz. + */ + isp->sw_contex.running_freq = ISP_FREQ_200MHZ; +} + +static void atomisp_subdev_init_struct(struct atomisp_sub_device *asd) +{ + v4l2_ctrl_s_ctrl(asd->run_mode, ATOMISP_RUN_MODE_STILL_CAPTURE); + memset(&asd->params.css_param, 0, sizeof(asd->params.css_param)); + asd->params.color_effect = V4L2_COLORFX_NONE; + asd->params.bad_pixel_en = true; + asd->params.gdc_cac_en = false; + asd->params.video_dis_en = false; + asd->params.sc_en = false; + asd->params.fpn_en = false; + asd->params.xnr_en = false; + asd->params.false_color = 0; + asd->params.online_process = 1; + asd->params.yuv_ds_en = 0; + /* s3a grid not enabled for any pipe */ + asd->params.s3a_enabled_pipe = IA_CSS_PIPE_ID_NUM; + + asd->params.offline_parm.num_captures = 1; + asd->params.offline_parm.skip_frames = 0; + asd->params.offline_parm.offset = 0; + asd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED; + /* Add for channel */ + asd->input_curr = 0; + + asd->mipi_frame_size = 0; + asd->copy_mode = false; + asd->yuvpp_mode = false; + + asd->stream_prepared = false; + asd->high_speed_mode = false; + asd->sensor_array_res.height = 0; + asd->sensor_array_res.width = 0; + atomisp_css_init_struct(asd); +} + +/* + * file operation functions + */ +static unsigned int atomisp_subdev_users(struct atomisp_sub_device *asd) +{ + return asd->video_out_preview.users + + asd->video_out_vf.users + + asd->video_out_capture.users + + asd->video_out_video_capture.users; +} + +unsigned int atomisp_dev_users(struct atomisp_device *isp) +{ + unsigned int i, sum; + + for (i = 0, sum = 0; i < isp->num_of_streams; i++) + sum += atomisp_subdev_users(&isp->asd[i]); + + return sum; +} + +static int atomisp_open(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + int ret; + + dev_dbg(isp->dev, "open device %s\n", vdev->name); + + ret = v4l2_fh_open(file); + if (ret) + return ret; + + mutex_lock(&isp->mutex); + + asd->subdev.devnode = vdev; + /* Deferred firmware loading case. */ + if (isp->css_env.isp_css_fw.bytes == 0) { + dev_err(isp->dev, "Deferred firmware load.\n"); + isp->firmware = atomisp_load_firmware(isp); + if (!isp->firmware) { + dev_err(isp->dev, "Failed to load ISP firmware.\n"); + ret = -ENOENT; + goto error; + } + ret = atomisp_css_load_firmware(isp); + if (ret) { + dev_err(isp->dev, "Failed to init css.\n"); + goto error; + } + /* No need to keep FW in memory anymore. */ + release_firmware(isp->firmware); + isp->firmware = NULL; + isp->css_env.isp_css_fw.data = NULL; + } + + if (!isp->input_cnt) { + dev_err(isp->dev, "no camera attached\n"); + ret = -EINVAL; + goto error; + } + + /* + * atomisp does not allow multiple open + */ + if (pipe->users) { + dev_dbg(isp->dev, "video node already opened\n"); + mutex_unlock(&isp->mutex); + return -EBUSY; + } + + ret = atomisp_init_pipe(pipe); + if (ret) + goto error; + + if (atomisp_dev_users(isp)) { + dev_dbg(isp->dev, "skip init isp in open\n"); + goto init_subdev; + } + + /* runtime power management, turn on ISP */ + ret = pm_runtime_resume_and_get(vdev->v4l2_dev->dev); + if (ret < 0) { + dev_err(isp->dev, "Failed to power on device\n"); + goto error; + } + + atomisp_dev_init_struct(isp); + + ret = v4l2_subdev_call(isp->flash, core, s_power, 1); + if (ret < 0 && ret != -ENODEV && ret != -ENOIOCTLCMD) { + dev_err(isp->dev, "Failed to power-on flash\n"); + goto css_error; + } + +init_subdev: + if (atomisp_subdev_users(asd)) + goto done; + + atomisp_subdev_init_struct(asd); + +done: + pipe->users++; + mutex_unlock(&isp->mutex); + + /* Ensure that a mode is set */ + v4l2_ctrl_s_ctrl(asd->run_mode, pipe->default_run_mode); + + return 0; + +css_error: + pm_runtime_put(vdev->v4l2_dev->dev); +error: + mutex_unlock(&isp->mutex); + v4l2_fh_release(file); + return ret; +} + +static int atomisp_release(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct v4l2_subdev_fh fh; + struct v4l2_rect clear_compose = {0}; + unsigned long flags; + int ret; + + v4l2_fh_init(&fh.vfh, vdev); + + dev_dbg(isp->dev, "release device %s\n", vdev->name); + + asd->subdev.devnode = vdev; + + /* Note file must not be used after this! */ + vb2_fop_release(file); + + mutex_lock(&isp->mutex); + + pipe->users--; + if (pipe->users) + goto done; + + /* + * A little trick here: + * file injection input resolution is recorded in the sink pad, + * therefore can not be cleared when releaseing one device node. + * The sink pad setting can only be cleared when all device nodes + * get released. + */ + if (asd->fmt_auto->val) { + struct v4l2_mbus_framefmt isp_sink_fmt = { 0 }; + + atomisp_subdev_set_ffmt(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, &isp_sink_fmt); + } + + if (atomisp_subdev_users(asd)) + goto done; + + atomisp_css_free_stat_buffers(asd); + atomisp_free_internal_buffers(asd); + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, s_power, 0); + if (ret) + dev_warn(isp->dev, "Failed to power-off sensor\n"); + + /* clear the asd field to show this camera is not used */ + isp->inputs[asd->input_curr].asd = NULL; + spin_lock_irqsave(&isp->lock, flags); + asd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED; + spin_unlock_irqrestore(&isp->lock, flags); + + if (atomisp_dev_users(isp)) + goto done; + + atomisp_destroy_pipes_stream_force(asd); + + if (defer_fw_load) { + ia_css_unload_firmware(); + isp->css_env.isp_css_fw.data = NULL; + isp->css_env.isp_css_fw.bytes = 0; + } + + ret = v4l2_subdev_call(isp->flash, core, s_power, 0); + if (ret < 0 && ret != -ENODEV && ret != -ENOIOCTLCMD) + dev_warn(isp->dev, "Failed to power-off flash\n"); + + if (pm_runtime_put_sync(vdev->v4l2_dev->dev) < 0) + dev_err(isp->dev, "Failed to power off device\n"); + +done: + atomisp_subdev_set_selection(&asd->subdev, fh.state, + V4L2_SUBDEV_FORMAT_ACTIVE, + atomisp_subdev_source_pad(vdev), + V4L2_SEL_TGT_COMPOSE, 0, + &clear_compose); + mutex_unlock(&isp->mutex); + return 0; +} + +const struct v4l2_file_operations atomisp_fops = { + .owner = THIS_MODULE, + .open = atomisp_open, + .release = atomisp_release, + .mmap = vb2_fop_mmap, + .poll = vb2_fop_poll, + .unlocked_ioctl = video_ioctl2, +#ifdef CONFIG_COMPAT + /* + * this was removed because of bugs, the interface + * needs to be made safe for compat tasks instead. + .compat_ioctl32 = atomisp_compat_ioctl32, + */ +#endif +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp_fops.h b/drivers/staging/media/atomisp/pci/atomisp_fops.h new file mode 100644 index 000000000..10e43126b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_fops.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_FOPS_H__ +#define __ATOMISP_FOPS_H__ +#include "atomisp_subdev.h" + +unsigned int atomisp_dev_users(struct atomisp_device *isp); +unsigned int atomisp_sub_dev_users(struct atomisp_sub_device *asd); + +/* + * Memory help functions for image frame and private parameters + */ + +int atomisp_qbuffers_to_css(struct atomisp_sub_device *asd); + +extern const struct v4l2_file_operations atomisp_fops; + +extern bool defer_fw_load; + +#endif /* __ATOMISP_FOPS_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_gmin_platform.c b/drivers/staging/media/atomisp/pci/atomisp_gmin_platform.c new file mode 100644 index 000000000..3d41fab66 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_gmin_platform.c @@ -0,0 +1,1391 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../include/linux/atomisp_platform.h" +#include "../../include/linux/atomisp_gmin_platform.h" + +#define MAX_SUBDEVS 8 + +enum clock_rate { + VLV2_CLK_XTAL_25_0MHz = 0, + VLV2_CLK_PLL_19P2MHZ = 1 +}; + +#define CLK_RATE_19_2MHZ 19200000 +#define CLK_RATE_25_0MHZ 25000000 + +/* Valid clock number range from 0 to 5 */ +#define MAX_CLK_COUNT 5 + +/* X-Powers AXP288 register set */ +#define ALDO1_SEL_REG 0x28 +#define ALDO1_CTRL3_REG 0x13 +#define ALDO1_2P8V 0x16 +#define ALDO1_CTRL3_SHIFT 0x05 + +#define ELDO_CTRL_REG 0x12 + +#define ELDO1_SEL_REG 0x19 +#define ELDO1_1P6V 0x12 +#define ELDO1_CTRL_SHIFT 0x00 + +#define ELDO2_SEL_REG 0x1a +#define ELDO2_1P8V 0x16 +#define ELDO2_CTRL_SHIFT 0x01 + +/* TI SND9039 PMIC register set */ +#define LDO9_REG 0x49 +#define LDO10_REG 0x4a +#define LDO11_REG 0x4b + +#define LDO_2P8V_ON 0x2f /* 0x2e selects 2.85V ... */ +#define LDO_2P8V_OFF 0x2e /* ... bottom bit is "enabled" */ + +#define LDO_1P8V_ON 0x59 /* 0x58 selects 1.80V ... */ +#define LDO_1P8V_OFF 0x58 /* ... bottom bit is "enabled" */ + +/* CRYSTAL COVE PMIC register set */ +#define CRYSTAL_1P8V_REG 0x57 +#define CRYSTAL_2P8V_REG 0x5d +#define CRYSTAL_ON 0x63 +#define CRYSTAL_OFF 0x62 + +struct gmin_subdev { + struct v4l2_subdev *subdev; + enum clock_rate clock_src; + struct clk *pmc_clk; + struct gpio_desc *gpio0; + struct gpio_desc *gpio1; + struct regulator *v1p8_reg; + struct regulator *v2p8_reg; + struct regulator *v1p2_reg; + struct regulator *v2p8_vcm_reg; + enum atomisp_camera_port csi_port; + unsigned int csi_lanes; + enum atomisp_input_format csi_fmt; + enum atomisp_bayer_order csi_bayer; + + bool clock_on; + bool v1p8_on; + bool v2p8_on; + bool v1p2_on; + bool v2p8_vcm_on; + + int v1p8_gpio; + int v2p8_gpio; + + u8 pwm_i2c_addr; + + /* For PMIC AXP */ + int eldo1_sel_reg, eldo1_1p6v, eldo1_ctrl_shift; + int eldo2_sel_reg, eldo2_1p8v, eldo2_ctrl_shift; +}; + +static struct gmin_subdev gmin_subdevs[MAX_SUBDEVS]; + +/* ACPI HIDs for the PMICs that could be used by this driver */ +#define PMIC_ACPI_AXP "INT33F4" /* XPower AXP288 PMIC */ +#define PMIC_ACPI_TI "INT33F5" /* Dollar Cove TI PMIC */ +#define PMIC_ACPI_CRYSTALCOVE "INT33FD" /* Crystal Cove PMIC */ + +#define PMIC_PLATFORM_TI "intel_soc_pmic_chtdc_ti" + +static enum { + PMIC_UNSET = 0, + PMIC_REGULATOR, + PMIC_AXP, + PMIC_TI, + PMIC_CRYSTALCOVE +} pmic_id; + +static const char *pmic_name[] = { + [PMIC_UNSET] = "ACPI device PM", + [PMIC_REGULATOR] = "regulator driver", + [PMIC_AXP] = "XPower AXP288 PMIC", + [PMIC_TI] = "Dollar Cove TI PMIC", + [PMIC_CRYSTALCOVE] = "Crystal Cove PMIC", +}; + +static DEFINE_MUTEX(gmin_regulator_mutex); +static int gmin_v1p8_enable_count; +static int gmin_v2p8_enable_count; + +/* The atomisp uses type==0 for the end-of-list marker, so leave space. */ +static struct intel_v4l2_subdev_table pdata_subdevs[MAX_SUBDEVS + 1]; + +static const struct atomisp_platform_data pdata = { + .subdevs = pdata_subdevs, +}; + +static LIST_HEAD(vcm_devices); +static DEFINE_MUTEX(vcm_lock); + +static struct gmin_subdev *find_gmin_subdev(struct v4l2_subdev *subdev); + +const struct atomisp_platform_data *atomisp_get_platform_data(void) +{ + return &pdata; +} +EXPORT_SYMBOL_GPL(atomisp_get_platform_data); + +int atomisp_register_i2c_module(struct v4l2_subdev *subdev, + struct camera_sensor_platform_data *plat_data, + enum intel_v4l2_subdev_type type) +{ + int i; + struct i2c_board_info *bi; + struct gmin_subdev *gs; + struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct acpi_device *adev = ACPI_COMPANION(&client->dev); + + dev_info(&client->dev, "register atomisp i2c module type %d\n", type); + + /* The windows driver model (and thus most BIOSes by default) + * uses ACPI runtime power management for camera devices, but + * we don't. Disable it, or else the rails will be needlessly + * tickled during suspend/resume. This has caused power and + * performance issues on multiple devices. + */ + adev->power.flags.power_resources = 0; + + for (i = 0; i < MAX_SUBDEVS; i++) + if (!pdata.subdevs[i].type) + break; + + if (pdata.subdevs[i].type) + return -ENOMEM; + + /* Note subtlety of initialization order: at the point where + * this registration API gets called, the platform data + * callbacks have probably already been invoked, so the + * gmin_subdev struct is already initialized for us. + */ + gs = find_gmin_subdev(subdev); + if (!gs) + return -ENODEV; + + pdata.subdevs[i].type = type; + pdata.subdevs[i].port = gs->csi_port; + pdata.subdevs[i].subdev = subdev; + pdata.subdevs[i].v4l2_subdev.i2c_adapter_id = client->adapter->nr; + + /* Convert i2c_client to i2c_board_info */ + bi = &pdata.subdevs[i].v4l2_subdev.board_info; + memcpy(bi->type, client->name, I2C_NAME_SIZE); + bi->flags = client->flags; + bi->addr = client->addr; + bi->irq = client->irq; + bi->platform_data = plat_data; + + return 0; +} +EXPORT_SYMBOL_GPL(atomisp_register_i2c_module); + +struct v4l2_subdev *atomisp_gmin_find_subdev(struct i2c_adapter *adapter, + struct i2c_board_info *board_info) +{ + int i; + + for (i = 0; i < MAX_SUBDEVS && pdata.subdevs[i].type; i++) { + struct intel_v4l2_subdev_table *sd = &pdata.subdevs[i]; + + if (sd->v4l2_subdev.i2c_adapter_id == adapter->nr && + sd->v4l2_subdev.board_info.addr == board_info->addr) + return sd->subdev; + } + return NULL; +} +EXPORT_SYMBOL_GPL(atomisp_gmin_find_subdev); + +int atomisp_gmin_remove_subdev(struct v4l2_subdev *sd) +{ + int i, j; + + if (!sd) + return 0; + + for (i = 0; i < MAX_SUBDEVS; i++) { + if (pdata.subdevs[i].subdev == sd) { + for (j = i + 1; j <= MAX_SUBDEVS; j++) + pdata.subdevs[j - 1] = pdata.subdevs[j]; + } + if (gmin_subdevs[i].subdev == sd) { + if (gmin_subdevs[i].gpio0) + gpiod_put(gmin_subdevs[i].gpio0); + gmin_subdevs[i].gpio0 = NULL; + if (gmin_subdevs[i].gpio1) + gpiod_put(gmin_subdevs[i].gpio1); + gmin_subdevs[i].gpio1 = NULL; + if (pmic_id == PMIC_REGULATOR) { + regulator_put(gmin_subdevs[i].v1p8_reg); + regulator_put(gmin_subdevs[i].v2p8_reg); + regulator_put(gmin_subdevs[i].v1p2_reg); + regulator_put(gmin_subdevs[i].v2p8_vcm_reg); + } + gmin_subdevs[i].subdev = NULL; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(atomisp_gmin_remove_subdev); + +struct gmin_cfg_var { + const char *name, *val; +}; + +static struct gmin_cfg_var ffrd8_vars[] = { + { "INTCF1B:00_ImxId", "0x134" }, + { "INTCF1B:00_CsiPort", "1" }, + { "INTCF1B:00_CsiLanes", "4" }, + { "INTCF1B:00_CamClk", "0" }, + {}, +}; + +/* Cribbed from MCG defaults in the mt9m114 driver, not actually verified + * vs. T100 hardware + */ +static struct gmin_cfg_var t100_vars[] = { + { "INT33F0:00_CsiPort", "0" }, + { "INT33F0:00_CsiLanes", "1" }, + { "INT33F0:00_CamClk", "1" }, + {}, +}; + +static struct gmin_cfg_var mrd7_vars[] = { + {"INT33F8:00_CamType", "1"}, + {"INT33F8:00_CsiPort", "1"}, + {"INT33F8:00_CsiLanes", "2"}, + {"INT33F8:00_CsiFmt", "13"}, + {"INT33F8:00_CsiBayer", "0"}, + {"INT33F8:00_CamClk", "0"}, + + {"INT33F9:00_CamType", "1"}, + {"INT33F9:00_CsiPort", "0"}, + {"INT33F9:00_CsiLanes", "1"}, + {"INT33F9:00_CsiFmt", "13"}, + {"INT33F9:00_CsiBayer", "0"}, + {"INT33F9:00_CamClk", "1"}, + {}, +}; + +static struct gmin_cfg_var ecs7_vars[] = { + {"INT33BE:00_CsiPort", "1"}, + {"INT33BE:00_CsiLanes", "2"}, + {"INT33BE:00_CsiFmt", "13"}, + {"INT33BE:00_CsiBayer", "2"}, + {"INT33BE:00_CamClk", "0"}, + + {"INT33F0:00_CsiPort", "0"}, + {"INT33F0:00_CsiLanes", "1"}, + {"INT33F0:00_CsiFmt", "13"}, + {"INT33F0:00_CsiBayer", "0"}, + {"INT33F0:00_CamClk", "1"}, + {"gmin_V2P8GPIO", "402"}, + {}, +}; + +static struct gmin_cfg_var i8880_vars[] = { + {"XXOV2680:00_CsiPort", "1"}, + {"XXOV2680:00_CsiLanes", "1"}, + {"XXOV2680:00_CamClk", "0"}, + + {"XXGC0310:00_CsiPort", "0"}, + {"XXGC0310:00_CsiLanes", "1"}, + {"XXGC0310:00_CamClk", "1"}, + {}, +}; + +/* + * Surface 3 does not describe CsiPort/CsiLanes in both DSDT and EFI. + */ +static struct gmin_cfg_var surface3_vars[] = { + {"APTA0330:00_CsiPort", "0"}, + {"APTA0330:00_CsiLanes", "2"}, + + {"OVTI8835:00_CsiPort", "1"}, + {"OVTI8835:00_CsiLanes", "4"}, + {}, +}; + +static const struct dmi_system_id gmin_vars[] = { + { + .ident = "BYT-T FFD8", + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"), + }, + .driver_data = ffrd8_vars, + }, + { + .ident = "T100TA", + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "T100TA"), + }, + .driver_data = t100_vars, + }, + { + .ident = "MRD7", + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "TABLET"), + DMI_MATCH(DMI_BOARD_VERSION, "MRD 7"), + }, + .driver_data = mrd7_vars, + }, + { + .ident = "ST70408", + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "ST70408"), + }, + .driver_data = ecs7_vars, + }, + { + .ident = "VTA0803", + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VTA0803"), + }, + .driver_data = i8880_vars, + }, + { + .ident = "Surface 3", + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "Surface 3"), + }, + .driver_data = surface3_vars, + }, + {} +}; + +#define GMIN_CFG_VAR_EFI_GUID EFI_GUID(0xecb54cd9, 0xe5ae, 0x4fdc, \ + 0xa9, 0x71, 0xe8, 0x77, \ + 0x75, 0x60, 0x68, 0xf7) + +static const guid_t atomisp_dsm_guid = GUID_INIT(0xdc2f6c4f, 0x045b, 0x4f1d, + 0x97, 0xb9, 0x88, 0x2a, + 0x68, 0x60, 0xa4, 0xbe); + +#define CFG_VAR_NAME_MAX 64 + +#define GMIN_PMC_CLK_NAME 14 /* "pmc_plt_clk_[0..5]" */ +static char gmin_pmc_clk_name[GMIN_PMC_CLK_NAME]; + +static struct i2c_client *gmin_i2c_dev_exists(struct device *dev, char *name, + struct i2c_client **client) +{ + struct acpi_device *adev; + struct device *d; + + adev = acpi_dev_get_first_match_dev(name, NULL, -1); + if (!adev) + return NULL; + + d = bus_find_device_by_acpi_dev(&i2c_bus_type, adev); + acpi_dev_put(adev); + if (!d) + return NULL; + + *client = i2c_verify_client(d); + put_device(d); + + dev_dbg(dev, "found '%s' at address 0x%02x, adapter %d\n", + (*client)->name, (*client)->addr, (*client)->adapter->nr); + return *client; +} + +static int gmin_i2c_write(struct device *dev, u16 i2c_addr, u8 reg, + u32 value, u32 mask) +{ + int ret; + + /* + * FIXME: Right now, the intel_pmic driver just write values + * directly at the regmap, instead of properly implementing + * i2c_transfer() mechanism. Let's use the same interface here, + * as otherwise we may face issues. + */ + + dev_dbg(dev, + "I2C write, addr: 0x%02x, reg: 0x%02x, value: 0x%02x, mask: 0x%02x\n", + i2c_addr, reg, value, mask); + + ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_addr, reg, value, mask); + if (ret == -EOPNOTSUPP) + dev_err(dev, + "ACPI didn't mapped the OpRegion needed to access I2C address 0x%02x.\n" + "Need to compile the kernel using CONFIG_*_PMIC_OPREGION settings\n", + i2c_addr); + + return ret; +} + +static int atomisp_get_acpi_power(struct device *dev) +{ + char name[5]; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + struct acpi_buffer b_name = { sizeof(name), name }; + union acpi_object *package, *element; + acpi_handle handle = ACPI_HANDLE(dev); + acpi_handle rhandle; + acpi_status status; + int clock_num = -1; + int i; + + status = acpi_evaluate_object(handle, "_PR0", NULL, &buffer); + if (!ACPI_SUCCESS(status)) + return -1; + + package = buffer.pointer; + + if (!buffer.length || !package + || package->type != ACPI_TYPE_PACKAGE + || !package->package.count) + goto fail; + + for (i = 0; i < package->package.count; i++) { + element = &package->package.elements[i]; + + if (element->type != ACPI_TYPE_LOCAL_REFERENCE) + continue; + + rhandle = element->reference.handle; + if (!rhandle) + goto fail; + + acpi_get_name(rhandle, ACPI_SINGLE_NAME, &b_name); + + dev_dbg(dev, "Found PM resource '%s'\n", name); + if (strlen(name) == 4 && !strncmp(name, "CLK", 3)) { + if (name[3] >= '0' && name[3] <= '4') + clock_num = name[3] - '0'; +#if 0 + /* + * We could abort here, but let's parse all resources, + * as this is helpful for debugging purposes + */ + if (clock_num >= 0) + break; +#endif + } + } + +fail: + ACPI_FREE(buffer.pointer); + + return clock_num; +} + +static u8 gmin_get_pmic_id_and_addr(struct device *dev) +{ + struct i2c_client *power = NULL; + static u8 pmic_i2c_addr; + + if (pmic_id) + return pmic_i2c_addr; + + if (gmin_i2c_dev_exists(dev, PMIC_ACPI_TI, &power)) + pmic_id = PMIC_TI; + else if (gmin_i2c_dev_exists(dev, PMIC_ACPI_AXP, &power)) + pmic_id = PMIC_AXP; + else if (gmin_i2c_dev_exists(dev, PMIC_ACPI_CRYSTALCOVE, &power)) + pmic_id = PMIC_CRYSTALCOVE; + else + pmic_id = PMIC_REGULATOR; + + pmic_i2c_addr = power ? power->addr : 0; + return pmic_i2c_addr; +} + +static int gmin_detect_pmic(struct v4l2_subdev *subdev) +{ + struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct device *dev = &client->dev; + u8 pmic_i2c_addr; + + pmic_i2c_addr = gmin_get_pmic_id_and_addr(dev); + dev_info(dev, "gmin: power management provided via %s (i2c addr 0x%02x)\n", + pmic_name[pmic_id], pmic_i2c_addr); + return pmic_i2c_addr; +} + +static int gmin_subdev_add(struct gmin_subdev *gs) +{ + struct i2c_client *client = v4l2_get_subdevdata(gs->subdev); + struct device *dev = &client->dev; + struct acpi_device *adev = ACPI_COMPANION(dev); + int ret, default_val, clock_num = -1; + + dev_info(dev, "%s: ACPI path is %pfw\n", __func__, dev_fwnode(dev)); + + /*WA:CHT requires XTAL clock as PLL is not stable.*/ + gs->clock_src = gmin_get_var_int(dev, false, "ClkSrc", + VLV2_CLK_PLL_19P2MHZ); + + /* + * Get ACPI _PR0 derived clock here already because it is used + * to determine the csi_port default. + */ + if (acpi_device_power_manageable(adev)) + clock_num = atomisp_get_acpi_power(dev); + + /* Compare clock to CsiPort 1 pmc-clock used in the CHT/BYT reference designs */ + if (IS_ISP2401) + default_val = clock_num == 4 ? 1 : 0; + else + default_val = clock_num == 0 ? 1 : 0; + + gs->csi_port = gmin_get_var_int(dev, false, "CsiPort", default_val); + gs->csi_lanes = gmin_get_var_int(dev, false, "CsiLanes", 1); + + gs->gpio0 = gpiod_get_index(dev, NULL, 0, GPIOD_OUT_LOW); + if (IS_ERR(gs->gpio0)) + gs->gpio0 = NULL; + else + dev_info(dev, "will handle gpio0 via ACPI\n"); + + gs->gpio1 = gpiod_get_index(dev, NULL, 1, GPIOD_OUT_LOW); + if (IS_ERR(gs->gpio1)) + gs->gpio1 = NULL; + else + dev_info(dev, "will handle gpio1 via ACPI\n"); + + /* + * Those are used only when there is an external regulator apart + * from the PMIC that would be providing power supply, like on the + * two cases below: + * + * The ECS E7 board drives camera 2.8v from an external regulator + * instead of the PMIC. There's a gmin_CamV2P8 config variable + * that specifies the GPIO to handle this particular case, + * but this needs a broader architecture for handling camera power. + * + * The CHT RVP board drives camera 1.8v from an* external regulator + * instead of the PMIC just like ECS E7 board. + */ + + gs->v1p8_gpio = gmin_get_var_int(dev, true, "V1P8GPIO", -1); + gs->v2p8_gpio = gmin_get_var_int(dev, true, "V2P8GPIO", -1); + + /* + * FIXME: + * + * The ACPI handling code checks for the _PR? tables in order to + * know what is required to switch the device from power state + * D0 (_PR0) up to D3COLD (_PR3). + * + * The adev->flags.power_manageable is set to true if the device + * has a _PR0 table, which can be checked by calling + * acpi_device_power_manageable(adev). + * + * However, this only says that the device can be set to power off + * mode. + * + * At least on the DSDT tables we've seen so far, there's no _PR3, + * nor _PS3 (which would have a somewhat similar effect). + * So, using ACPI for power management won't work, except if adding + * an ACPI override logic somewhere. + * + * So, at least for the existing devices we know, the check below + * will always be false. + */ + if (acpi_device_can_wakeup(adev) && + acpi_device_can_poweroff(adev)) { + dev_info(dev, + "gmin: power management provided via device PM\n"); + return 0; + } + + /* + * The code below is here due to backward compatibility with devices + * whose ACPI BIOS may not contain everything that would be needed + * in order to set clocks and do power management. + */ + + /* + * According with : + * https://github.com/projectceladon/hardware-intel-kernelflinger/blob/master/doc/fastboot.md + * + * The "CamClk" EFI var is set via fastboot on some Android devices, + * and seems to contain the number of the clock used to feed the + * sensor. + * + * On systems with a proper ACPI table, this is given via the _PR0 + * power resource table. The logic below should first check if there + * is a power resource already, falling back to the EFI vars detection + * otherwise. + */ + + /* If getting the clock from _PR0 above failed, fall-back to EFI and/or DMI match */ + if (clock_num < 0) + clock_num = gmin_get_var_int(dev, false, "CamClk", 0); + + if (clock_num < 0 || clock_num > MAX_CLK_COUNT) { + dev_err(dev, "Invalid clock number\n"); + return -EINVAL; + } + + snprintf(gmin_pmc_clk_name, sizeof(gmin_pmc_clk_name), + "%s_%d", "pmc_plt_clk", clock_num); + + gs->pmc_clk = devm_clk_get(dev, gmin_pmc_clk_name); + if (IS_ERR(gs->pmc_clk)) { + ret = PTR_ERR(gs->pmc_clk); + dev_err(dev, "Failed to get clk from %s: %d\n", gmin_pmc_clk_name, ret); + return ret; + } + dev_info(dev, "Will use CLK%d (%s)\n", clock_num, gmin_pmc_clk_name); + + /* + * The firmware might enable the clock at + * boot (this information may or may not + * be reflected in the enable clock register). + * To change the rate we must disable the clock + * first to cover these cases. Due to common + * clock framework restrictions that do not allow + * to disable a clock that has not been enabled, + * we need to enable the clock first. + */ + ret = clk_prepare_enable(gs->pmc_clk); + if (!ret) + clk_disable_unprepare(gs->pmc_clk); + + switch (pmic_id) { + case PMIC_REGULATOR: + gs->v1p8_reg = regulator_get(dev, "V1P8SX"); + gs->v2p8_reg = regulator_get(dev, "V2P8SX"); + + gs->v1p2_reg = regulator_get(dev, "V1P2A"); + gs->v2p8_vcm_reg = regulator_get(dev, "VPROG4B"); + + /* Note: ideally we would initialize v[12]p8_on to the + * output of regulator_is_enabled(), but sadly that + * API is broken with the current drivers, returning + * "1" for a regulator that will then emit a + * "unbalanced disable" WARNing if we try to disable + * it. + */ + break; + + case PMIC_AXP: + gs->eldo1_1p6v = gmin_get_var_int(dev, false, + "eldo1_1p8v", + ELDO1_1P6V); + gs->eldo1_sel_reg = gmin_get_var_int(dev, false, + "eldo1_sel_reg", + ELDO1_SEL_REG); + gs->eldo1_ctrl_shift = gmin_get_var_int(dev, false, + "eldo1_ctrl_shift", + ELDO1_CTRL_SHIFT); + gs->eldo2_1p8v = gmin_get_var_int(dev, false, + "eldo2_1p8v", + ELDO2_1P8V); + gs->eldo2_sel_reg = gmin_get_var_int(dev, false, + "eldo2_sel_reg", + ELDO2_SEL_REG); + gs->eldo2_ctrl_shift = gmin_get_var_int(dev, false, + "eldo2_ctrl_shift", + ELDO2_CTRL_SHIFT); + break; + + default: + break; + } + + return 0; +} + +static struct gmin_subdev *find_gmin_subdev(struct v4l2_subdev *subdev) +{ + int i; + + for (i = 0; i < MAX_SUBDEVS; i++) + if (gmin_subdevs[i].subdev == subdev) + return &gmin_subdevs[i]; + return NULL; +} + +static struct gmin_subdev *find_free_gmin_subdev_slot(void) +{ + unsigned int i; + + for (i = 0; i < MAX_SUBDEVS; i++) + if (gmin_subdevs[i].subdev == NULL) + return &gmin_subdevs[i]; + return NULL; +} + +static int axp_regulator_set(struct device *dev, struct gmin_subdev *gs, + int sel_reg, u8 setting, + int ctrl_reg, int shift, bool on) +{ + int ret; + int val; + + ret = gmin_i2c_write(dev, gs->pwm_i2c_addr, sel_reg, setting, 0xff); + if (ret) + return ret; + + val = on ? 1 << shift : 0; + + ret = gmin_i2c_write(dev, gs->pwm_i2c_addr, ctrl_reg, val, 1 << shift); + if (ret) + return ret; + + return 0; +} + +/* + * Some boards contain a hw-bug where turning eldo2 back on after having turned + * it off causes the CPLM3218 ambient-light-sensor on the image-sensor's I2C bus + * to crash, hanging the bus. Do not turn eldo2 off on these systems. + */ +static const struct dmi_system_id axp_leave_eldo2_on_ids[] = { + { + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "TrekStor"), + DMI_MATCH(DMI_PRODUCT_NAME, "SurfTab duo W1 10.1 (VT4)"), + }, + }, + { } +}; + +static int axp_v1p8_on(struct device *dev, struct gmin_subdev *gs) +{ + int ret; + + ret = axp_regulator_set(dev, gs, gs->eldo2_sel_reg, gs->eldo2_1p8v, + ELDO_CTRL_REG, gs->eldo2_ctrl_shift, true); + if (ret) + return ret; + + /* + * This sleep comes out of the gc2235 driver, which is the + * only one I currently see that wants to set both 1.8v rails. + */ + usleep_range(110, 150); + + ret = axp_regulator_set(dev, gs, gs->eldo1_sel_reg, gs->eldo1_1p6v, + ELDO_CTRL_REG, gs->eldo1_ctrl_shift, true); + return ret; +} + +static int axp_v1p8_off(struct device *dev, struct gmin_subdev *gs) +{ + int ret; + + ret = axp_regulator_set(dev, gs, gs->eldo1_sel_reg, gs->eldo1_1p6v, + ELDO_CTRL_REG, gs->eldo1_ctrl_shift, false); + if (ret) + return ret; + + if (dmi_check_system(axp_leave_eldo2_on_ids)) + return 0; + + ret = axp_regulator_set(dev, gs, gs->eldo2_sel_reg, gs->eldo2_1p8v, + ELDO_CTRL_REG, gs->eldo2_ctrl_shift, false); + return ret; +} + +static int gmin_gpio0_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + + if (gs) { + gpiod_set_value(gs->gpio0, on); + return 0; + } + return -EINVAL; +} + +static int gmin_gpio1_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + + if (gs) { + gpiod_set_value(gs->gpio1, on); + return 0; + } + return -EINVAL; +} + +static int gmin_v1p2_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + + if (!gs || gs->v1p2_on == on) + return 0; + gs->v1p2_on = on; + + /* use regulator for PMIC */ + if (gs->v1p2_reg) { + if (on) + return regulator_enable(gs->v1p2_reg); + else + return regulator_disable(gs->v1p2_reg); + } + + /* TODO:v1p2 may need to extend to other PMICs */ + + return -EINVAL; +} + +static int gmin_v1p8_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + int ret; + int value; + + if (!gs || gs->v1p8_on == on) + return 0; + + if (gs->v1p8_gpio >= 0) { + pr_info("atomisp_gmin_platform: 1.8v power on GPIO %d\n", + gs->v1p8_gpio); + ret = gpio_request(gs->v1p8_gpio, "camera_v1p8_en"); + if (!ret) + ret = gpio_direction_output(gs->v1p8_gpio, 0); + if (ret) + pr_err("V1P8 GPIO initialization failed\n"); + } + + gs->v1p8_on = on; + + ret = 0; + mutex_lock(&gmin_regulator_mutex); + if (on) { + gmin_v1p8_enable_count++; + if (gmin_v1p8_enable_count > 1) + goto out; /* Already on */ + } else { + gmin_v1p8_enable_count--; + if (gmin_v1p8_enable_count > 0) + goto out; /* Still needed */ + } + + if (gs->v1p8_gpio >= 0) + gpio_set_value(gs->v1p8_gpio, on); + + if (gs->v1p8_reg) { + regulator_set_voltage(gs->v1p8_reg, 1800000, 1800000); + if (on) + ret = regulator_enable(gs->v1p8_reg); + else + ret = regulator_disable(gs->v1p8_reg); + + goto out; + } + + switch (pmic_id) { + case PMIC_AXP: + if (on) + ret = axp_v1p8_on(subdev->dev, gs); + else + ret = axp_v1p8_off(subdev->dev, gs); + break; + case PMIC_TI: + value = on ? LDO_1P8V_ON : LDO_1P8V_OFF; + + ret = gmin_i2c_write(subdev->dev, gs->pwm_i2c_addr, + LDO10_REG, value, 0xff); + break; + case PMIC_CRYSTALCOVE: + value = on ? CRYSTAL_ON : CRYSTAL_OFF; + + ret = gmin_i2c_write(subdev->dev, gs->pwm_i2c_addr, + CRYSTAL_1P8V_REG, value, 0xff); + break; + default: + dev_err(subdev->dev, "Couldn't set power mode for v1p8\n"); + ret = -EINVAL; + } + +out: + mutex_unlock(&gmin_regulator_mutex); + return ret; +} + +static int gmin_v2p8_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + int ret; + int value; + + if (WARN_ON(!gs)) + return -ENODEV; + + if (gs->v2p8_gpio >= 0) { + pr_info("atomisp_gmin_platform: 2.8v power on GPIO %d\n", + gs->v2p8_gpio); + ret = gpio_request(gs->v2p8_gpio, "camera_v2p8"); + if (!ret) + ret = gpio_direction_output(gs->v2p8_gpio, 0); + if (ret) + pr_err("V2P8 GPIO initialization failed\n"); + } + + if (gs->v2p8_on == on) + return 0; + gs->v2p8_on = on; + + ret = 0; + mutex_lock(&gmin_regulator_mutex); + if (on) { + gmin_v2p8_enable_count++; + if (gmin_v2p8_enable_count > 1) + goto out; /* Already on */ + } else { + gmin_v2p8_enable_count--; + if (gmin_v2p8_enable_count > 0) + goto out; /* Still needed */ + } + + if (gs->v2p8_gpio >= 0) + gpio_set_value(gs->v2p8_gpio, on); + + if (gs->v2p8_reg) { + regulator_set_voltage(gs->v2p8_reg, 2900000, 2900000); + if (on) + ret = regulator_enable(gs->v2p8_reg); + else + ret = regulator_disable(gs->v2p8_reg); + + goto out; + } + + switch (pmic_id) { + case PMIC_AXP: + ret = axp_regulator_set(subdev->dev, gs, ALDO1_SEL_REG, + ALDO1_2P8V, ALDO1_CTRL3_REG, + ALDO1_CTRL3_SHIFT, on); + break; + case PMIC_TI: + value = on ? LDO_2P8V_ON : LDO_2P8V_OFF; + + ret = gmin_i2c_write(subdev->dev, gs->pwm_i2c_addr, + LDO9_REG, value, 0xff); + break; + case PMIC_CRYSTALCOVE: + value = on ? CRYSTAL_ON : CRYSTAL_OFF; + + ret = gmin_i2c_write(subdev->dev, gs->pwm_i2c_addr, + CRYSTAL_2P8V_REG, value, 0xff); + break; + default: + dev_err(subdev->dev, "Couldn't set power mode for v2p8\n"); + ret = -EINVAL; + } + +out: + mutex_unlock(&gmin_regulator_mutex); + return ret; +} + +static int gmin_acpi_pm_ctrl(struct v4l2_subdev *subdev, int on) +{ + int ret = 0; + struct gmin_subdev *gs = find_gmin_subdev(subdev); + struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct acpi_device *adev = ACPI_COMPANION(&client->dev); + + /* Use the ACPI power management to control it */ + on = !!on; + if (gs->clock_on == on) + return 0; + + dev_dbg(subdev->dev, "Setting power state to %s\n", + on ? "on" : "off"); + + if (on) + ret = acpi_device_set_power(adev, + ACPI_STATE_D0); + else + ret = acpi_device_set_power(adev, + ACPI_STATE_D3_COLD); + + if (!ret) + gs->clock_on = on; + else + dev_err(subdev->dev, "Couldn't set power state to %s\n", + on ? "on" : "off"); + + return ret; +} + +static int gmin_flisclk_ctrl(struct v4l2_subdev *subdev, int on) +{ + int ret = 0; + struct gmin_subdev *gs = find_gmin_subdev(subdev); + struct i2c_client *client = v4l2_get_subdevdata(subdev); + + if (gs->clock_on == !!on) + return 0; + + if (on) { + ret = clk_set_rate(gs->pmc_clk, + gs->clock_src ? CLK_RATE_19_2MHZ : CLK_RATE_25_0MHZ); + + if (ret) + dev_err(&client->dev, "unable to set PMC rate %d\n", + gs->clock_src); + + ret = clk_prepare_enable(gs->pmc_clk); + if (ret == 0) + gs->clock_on = true; + } else { + clk_disable_unprepare(gs->pmc_clk); + gs->clock_on = false; + } + + return ret; +} + +static int camera_sensor_csi_alloc(struct v4l2_subdev *sd, u32 port, u32 lanes, + u32 format, u32 bayer_order) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *csi; + + csi = kzalloc(sizeof(*csi), GFP_KERNEL); + if (!csi) + return -ENOMEM; + + csi->port = port; + csi->num_lanes = lanes; + csi->input_format = format; + csi->raw_bayer_order = bayer_order; + v4l2_set_subdev_hostdata(sd, csi); + csi->metadata_format = ATOMISP_INPUT_FORMAT_EMBEDDED; + csi->metadata_effective_width = NULL; + dev_info(&client->dev, + "camera pdata: port: %d lanes: %d order: %8.8x\n", + port, lanes, bayer_order); + + return 0; +} + +static void camera_sensor_csi_free(struct v4l2_subdev *sd) +{ + struct camera_mipi_info *csi; + + csi = v4l2_get_subdev_hostdata(sd); + kfree(csi); +} + +static int gmin_csi_cfg(struct v4l2_subdev *sd, int flag) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct gmin_subdev *gs = find_gmin_subdev(sd); + + if (!client || !gs) + return -ENODEV; + + if (flag) + return camera_sensor_csi_alloc(sd, gs->csi_port, gs->csi_lanes, + gs->csi_fmt, gs->csi_bayer); + camera_sensor_csi_free(sd); + return 0; +} + +static struct camera_vcm_control *gmin_get_vcm_ctrl(struct v4l2_subdev *subdev, + char *camera_module) +{ + struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct gmin_subdev *gs = find_gmin_subdev(subdev); + struct camera_vcm_control *vcm; + + if (!client || !gs) + return NULL; + + if (!camera_module) + return NULL; + + mutex_lock(&vcm_lock); + list_for_each_entry(vcm, &vcm_devices, list) { + if (!strcmp(camera_module, vcm->camera_module)) { + mutex_unlock(&vcm_lock); + return vcm; + } + } + + mutex_unlock(&vcm_lock); + return NULL; +} + +static struct camera_sensor_platform_data pmic_gmin_plat = { + .gpio0_ctrl = gmin_gpio0_ctrl, + .gpio1_ctrl = gmin_gpio1_ctrl, + .v1p8_ctrl = gmin_v1p8_ctrl, + .v2p8_ctrl = gmin_v2p8_ctrl, + .v1p2_ctrl = gmin_v1p2_ctrl, + .flisclk_ctrl = gmin_flisclk_ctrl, + .csi_cfg = gmin_csi_cfg, + .get_vcm_ctrl = gmin_get_vcm_ctrl, +}; + +static struct camera_sensor_platform_data acpi_gmin_plat = { + .gpio0_ctrl = gmin_gpio0_ctrl, + .gpio1_ctrl = gmin_gpio1_ctrl, + .v1p8_ctrl = gmin_acpi_pm_ctrl, + .v2p8_ctrl = gmin_acpi_pm_ctrl, + .v1p2_ctrl = gmin_acpi_pm_ctrl, + .flisclk_ctrl = gmin_acpi_pm_ctrl, + .csi_cfg = gmin_csi_cfg, + .get_vcm_ctrl = gmin_get_vcm_ctrl, +}; + +struct camera_sensor_platform_data * +gmin_camera_platform_data(struct v4l2_subdev *subdev, + enum atomisp_input_format csi_format, + enum atomisp_bayer_order csi_bayer) +{ + u8 pmic_i2c_addr = gmin_detect_pmic(subdev); + struct gmin_subdev *gs; + + gs = find_free_gmin_subdev_slot(); + gs->subdev = subdev; + gs->csi_fmt = csi_format; + gs->csi_bayer = csi_bayer; + gs->pwm_i2c_addr = pmic_i2c_addr; + + gmin_subdev_add(gs); + if (gs->pmc_clk) + return &pmic_gmin_plat; + else + return &acpi_gmin_plat; +} +EXPORT_SYMBOL_GPL(gmin_camera_platform_data); + +int atomisp_gmin_register_vcm_control(struct camera_vcm_control *vcmCtrl) +{ + if (!vcmCtrl) + return -EINVAL; + + mutex_lock(&vcm_lock); + list_add_tail(&vcmCtrl->list, &vcm_devices); + mutex_unlock(&vcm_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(atomisp_gmin_register_vcm_control); + +static int gmin_get_hardcoded_var(struct device *dev, + struct gmin_cfg_var *varlist, + const char *var8, char *out, size_t *out_len) +{ + struct gmin_cfg_var *gv; + + for (gv = varlist; gv->name; gv++) { + size_t vl; + + if (strcmp(var8, gv->name)) + continue; + + dev_info(dev, "Found DMI entry for '%s'\n", var8); + + vl = strlen(gv->val); + if (vl > *out_len - 1) + return -ENOSPC; + + strscpy(out, gv->val, *out_len); + *out_len = vl; + return 0; + } + + return -EINVAL; +} + + +static int gmin_get_config_dsm_var(struct device *dev, + const char *var, + char *out, size_t *out_len) +{ + acpi_handle handle = ACPI_HANDLE(dev); + union acpi_object *obj, *cur = NULL; + int i; + + /* + * The data reported by "CamClk" seems to be either 0 or 1 at the + * _DSM table. + * + * At the ACPI tables we looked so far, this is not related to the + * actual clock source for the sensor, which is given by the + * _PR0 ACPI table. So, ignore it, as otherwise this will be + * set to a wrong value. + */ + if (!strcmp(var, "CamClk")) + return -EINVAL; + + /* Return on unexpected object type */ + obj = acpi_evaluate_dsm_typed(handle, &atomisp_dsm_guid, 0, 0, NULL, + ACPI_TYPE_PACKAGE); + if (!obj) { + dev_info_once(dev, "Didn't find ACPI _DSM table.\n"); + return -EINVAL; + } + +#if 0 /* Just for debugging purposes */ + for (i = 0; i < obj->package.count; i++) { + union acpi_object *cur = &obj->package.elements[i]; + + if (cur->type == ACPI_TYPE_INTEGER) + dev_info(dev, "object #%d, type %d, value: %lld\n", + i, cur->type, cur->integer.value); + else if (cur->type == ACPI_TYPE_STRING) + dev_info(dev, "object #%d, type %d, string: %s\n", + i, cur->type, cur->string.pointer); + else + dev_info(dev, "object #%d, type %d\n", + i, cur->type); + } +#endif + + /* Seek for the desired var */ + for (i = 0; i < obj->package.count - 1; i += 2) { + if (obj->package.elements[i].type == ACPI_TYPE_STRING && + !strcmp(obj->package.elements[i].string.pointer, var)) { + /* Next element should be the required value */ + cur = &obj->package.elements[i + 1]; + break; + } + } + + if (!cur) { + dev_info(dev, "didn't found _DSM entry for '%s'\n", var); + ACPI_FREE(obj); + return -EINVAL; + } + + /* + * While it could be possible to have an ACPI_TYPE_INTEGER, + * and read the value from cur->integer.value, the table + * seen so far uses the string type. So, produce a warning + * if it founds something different than string, letting it + * to fall back to the old code. + */ + if (cur && cur->type != ACPI_TYPE_STRING) { + dev_info(dev, "found non-string _DSM entry for '%s'\n", var); + ACPI_FREE(obj); + return -EINVAL; + } + + dev_info(dev, "found _DSM entry for '%s': %s\n", var, + cur->string.pointer); + strscpy(out, cur->string.pointer, *out_len); + *out_len = strlen(cur->string.pointer); + + ACPI_FREE(obj); + return 0; +} + +/* Retrieves a device-specific configuration variable. The dev + * argument should be a device with an ACPI companion, as all + * configuration is based on firmware ID. + */ +static int gmin_get_config_var(struct device *maindev, + bool is_gmin, + const char *var, + char *out, size_t *out_len) +{ + efi_char16_t var16[CFG_VAR_NAME_MAX]; + const struct dmi_system_id *id; + struct device *dev = maindev; + char var8[CFG_VAR_NAME_MAX]; + efi_status_t status; + int i, ret; + + /* For sensors, try first to use the _DSM table */ + if (!is_gmin) { + ret = gmin_get_config_dsm_var(maindev, var, out, out_len); + if (!ret) + return 0; + } + + /* Fall-back to other approaches */ + + if (!is_gmin && ACPI_COMPANION(dev)) + dev = &ACPI_COMPANION(dev)->dev; + + if (!is_gmin) + ret = snprintf(var8, sizeof(var8), "%s_%s", dev_name(dev), var); + else + ret = snprintf(var8, sizeof(var8), "gmin_%s", var); + + if (ret < 0 || ret >= sizeof(var8) - 1) + return -EINVAL; + + /* First check a hard-coded list of board-specific variables. + * Some device firmwares lack the ability to set EFI variables at + * runtime. + */ + id = dmi_first_match(gmin_vars); + if (id) { + ret = gmin_get_hardcoded_var(maindev, id->driver_data, var8, + out, out_len); + if (!ret) + return 0; + } + + /* Our variable names are ASCII by construction, but EFI names + * are wide chars. Convert and zero-pad. + */ + memset(var16, 0, sizeof(var16)); + for (i = 0; i < sizeof(var8) && var8[i]; i++) + var16[i] = var8[i]; + + status = EFI_UNSUPPORTED; + if (efi_rt_services_supported(EFI_RT_SUPPORTED_GET_VARIABLE)) + status = efi.get_variable(var16, &GMIN_CFG_VAR_EFI_GUID, NULL, + (unsigned long *)out_len, out); + if (status == EFI_SUCCESS) { + dev_info(maindev, "found EFI entry for '%s'\n", var8); + } else if (is_gmin) { + dev_info(maindev, "Failed to find EFI gmin variable %s\n", var8); + } else { + dev_info(maindev, "Failed to find EFI variable %s\n", var8); + } + + return ret; +} + +int gmin_get_var_int(struct device *dev, bool is_gmin, const char *var, int def) +{ + char val[CFG_VAR_NAME_MAX]; + size_t len = sizeof(val); + long result; + int ret; + + ret = gmin_get_config_var(dev, is_gmin, var, val, &len); + if (!ret) { + val[len] = 0; + ret = kstrtol(val, 0, &result); + } else { + dev_info(dev, "%s: using default (%d)\n", var, def); + } + + return ret ? def : result; +} +EXPORT_SYMBOL_GPL(gmin_get_var_int); + +/* PCI quirk: The BYT ISP advertises PCI runtime PM but it doesn't + * work. Disable so the kernel framework doesn't hang the device + * trying. The driver itself does direct calls to the PUNIT to manage + * ISP power. + */ +static void isp_pm_cap_fixup(struct pci_dev *pdev) +{ + dev_info(&pdev->dev, "Disabling PCI power management on camera ISP\n"); + pdev->pm_cap = 0; +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0f38, isp_pm_cap_fixup); + +MODULE_DESCRIPTION("Ancillary routines for binding ACPI devices"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/pci/atomisp_internal.h b/drivers/staging/media/atomisp/pci/atomisp_internal.h new file mode 100644 index 000000000..653e6d74a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_internal.h @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef __ATOMISP_INTERNAL_H__ +#define __ATOMISP_INTERNAL_H__ + +#include "../../include/linux/atomisp_platform.h" +#include +#include +#include +#include + +#include +#include + +/* ISP2400*/ +#include "ia_css_types.h" +#include "sh_css_legacy.h" + +#include "atomisp_csi2.h" +#include "atomisp_subdev.h" +#include "atomisp_tpg.h" +#include "atomisp_compat.h" + +#include "gp_device.h" +#include "irq.h" +#include + +#define V4L2_EVENT_FRAME_END 5 + +#define IS_HWREVISION(isp, rev) \ + (((isp)->media_dev.hw_revision & ATOMISP_HW_REVISION_MASK) == \ + ((rev) << ATOMISP_HW_REVISION_SHIFT)) + +#define MAX_STREAM_NUM 2 + +#define ATOMISP_PCI_DEVICE_SOC_MASK 0xfff8 +/* MRFLD with 0x1178: ISP freq can burst to 457MHz */ +#define ATOMISP_PCI_DEVICE_SOC_MRFLD 0x1178 +/* MRFLD with 0x1179: max ISP freq limited to 400MHz */ +#define ATOMISP_PCI_DEVICE_SOC_MRFLD_1179 0x1179 +/* MRFLD with 0x117a: max ISP freq is 400MHz and max freq at Vmin is 200MHz */ +#define ATOMISP_PCI_DEVICE_SOC_MRFLD_117A 0x117a +#define ATOMISP_PCI_DEVICE_SOC_BYT 0x0f38 +#define ATOMISP_PCI_DEVICE_SOC_ANN 0x1478 +#define ATOMISP_PCI_DEVICE_SOC_CHT 0x22b8 + +#define ATOMISP_PCI_REV_MRFLD_A0_MAX 0 +#define ATOMISP_PCI_REV_BYT_A0_MAX 4 + +#define ATOM_ISP_STEP_WIDTH 2 +#define ATOM_ISP_STEP_HEIGHT 2 + +#define ATOM_ISP_MIN_WIDTH 4 +#define ATOM_ISP_MIN_HEIGHT 4 +#define ATOM_ISP_MAX_WIDTH UINT_MAX +#define ATOM_ISP_MAX_HEIGHT UINT_MAX + +/* sub-QCIF resolution */ +#define ATOM_RESOLUTION_SUBQCIF_WIDTH 128 +#define ATOM_RESOLUTION_SUBQCIF_HEIGHT 96 + +#define ATOM_ISP_MAX_WIDTH_TMP 1280 +#define ATOM_ISP_MAX_HEIGHT_TMP 720 + +#define ATOM_ISP_I2C_BUS_1 4 +#define ATOM_ISP_I2C_BUS_2 5 + +#define ATOM_ISP_POWER_DOWN 0 +#define ATOM_ISP_POWER_UP 1 + +#define ATOM_ISP_MAX_INPUTS 3 + +#define ATOMISP_SC_TYPE_SIZE 2 + +#define ATOMISP_ISP_TIMEOUT_DURATION (2 * HZ) +#define ATOMISP_EXT_ISP_TIMEOUT_DURATION (6 * HZ) +#define ATOMISP_WDT_KEEP_CURRENT_DELAY 0 +#define ATOMISP_ISP_MAX_TIMEOUT_COUNT 2 +#define ATOMISP_CSS_STOP_TIMEOUT_US 200000 + +#define ATOMISP_CSS_Q_DEPTH 3 +#define ATOMISP_CSS_EVENTS_MAX 16 +#define ATOMISP_CONT_RAW_FRAMES 15 +#define ATOMISP_METADATA_QUEUE_DEPTH_FOR_HAL 8 +#define ATOMISP_S3A_BUF_QUEUE_DEPTH_FOR_HAL 8 + +#define ATOMISP_DELAYED_INIT_NOT_QUEUED 0 +#define ATOMISP_DELAYED_INIT_QUEUED 1 +#define ATOMISP_DELAYED_INIT_DONE 2 + +/* + * Define how fast CPU should be able to serve ISP interrupts. + * The bigger the value, the higher risk that the ISP is not + * triggered sufficiently fast for it to process image during + * vertical blanking time, increasing risk of dropped frames. + * 1000 us is a reasonable value considering that the processing + * time is typically ~2000 us. + */ +#define ATOMISP_MAX_ISR_LATENCY 1000 + +/* Add new YUVPP pipe for SOC sensor. */ +#define ATOMISP_CSS_SUPPORT_YUVPP 1 + +#define ATOMISP_CSS_OUTPUT_SECOND_INDEX 1 +#define ATOMISP_CSS_OUTPUT_DEFAULT_INDEX 0 + +/* + * ATOMISP_SOC_CAMERA + * This is to differentiate between ext-isp and soc camera in + * Moorefield/Baytrail platform. + */ +#define ATOMISP_SOC_CAMERA(asd) \ + (asd->isp->inputs[asd->input_curr].type == SOC_CAMERA) + +#define ATOMISP_USE_YUVPP(asd) \ + (ATOMISP_SOC_CAMERA(asd) && ATOMISP_CSS_SUPPORT_YUVPP && \ + !asd->copy_mode) + +#define ATOMISP_DEPTH_SENSOR_STREAMON_COUNT 2 + +#define ATOMISP_DEPTH_DEFAULT_MASTER_SENSOR 0 +#define ATOMISP_DEPTH_DEFAULT_SLAVE_SENSOR 1 + +/* ISP2401 */ +#define ATOMISP_ION_DEVICE_FD_OFFSET 16 +#define ATOMISP_ION_SHARED_FD_MASK (0xFFFF) +#define ATOMISP_ION_DEVICE_FD_MASK (~ATOMISP_ION_SHARED_FD_MASK) +#define ION_FD_UNSET (-1) + +#define DIV_NEAREST_STEP(n, d, step) \ + round_down((2 * (n) + (d) * (step)) / (2 * (d)), (step)) + +struct atomisp_input_subdev { + unsigned int type; + enum atomisp_camera_port port; + struct v4l2_subdev *camera; + struct v4l2_subdev *motor; + struct v4l2_frmsizeenum frame_size; + + /* + * To show this resource is used by + * which stream, in ISP multiple stream mode + */ + struct atomisp_sub_device *asd; + + int sensor_index; +}; + +enum atomisp_dfs_mode { + ATOMISP_DFS_MODE_AUTO = 0, + ATOMISP_DFS_MODE_LOW, + ATOMISP_DFS_MODE_MAX, +}; + +struct atomisp_regs { + /* PCI config space info */ + u16 pcicmdsts; + u32 ispmmadr; + u32 msicap; + u32 msi_addr; + u16 msi_data; + u8 intr; + u32 interrupt_control; + u32 pmcs; + u32 cg_dis; + u32 i_control; + + /* I-Unit PHY related info */ + u32 csi_rcomp_config; + u32 csi_afe_dly; + u32 csi_control; + + /* New for MRFLD */ + u32 csi_afe_rcomp_config; + u32 csi_afe_hs_control; + u32 csi_deadline_control; + u32 csi_access_viol; +}; + +struct atomisp_sw_contex { + int running_freq; +}; + +#define ATOMISP_DEVICE_STREAMING_DISABLED 0 +#define ATOMISP_DEVICE_STREAMING_ENABLED 1 +#define ATOMISP_DEVICE_STREAMING_STOPPING 2 + +/* + * ci device struct + */ +struct atomisp_device { + struct device *dev; + struct v4l2_device v4l2_dev; + struct media_device media_dev; + struct atomisp_platform_data *pdata; + void *mmu_l1_base; + void __iomem *base; + const struct firmware *firmware; + + struct pm_qos_request pm_qos; + s32 max_isr_latency; + + /* + * ISP modules + * Multiple streams are represents by multiple + * atomisp_sub_device instances + */ + struct atomisp_sub_device *asd; + /* + * this will be assigned dyanamically. + * For Merr/BTY(ISP2400), 2 streams are supported. + */ + unsigned int num_of_streams; + + struct atomisp_mipi_csi2_device csi2_port[ATOMISP_CAMERA_NR_PORTS]; + struct atomisp_tpg_device tpg; + + /* Purpose of mutex is to protect and serialize use of isp data + * structures and css API calls. */ + struct mutex mutex; + + unsigned int input_cnt; + struct atomisp_input_subdev inputs[ATOM_ISP_MAX_INPUTS]; + struct v4l2_subdev *flash; + struct v4l2_subdev *motor; + + struct atomisp_regs saved_regs; + struct atomisp_sw_contex sw_contex; + struct atomisp_css_env css_env; + + /* isp timeout status flag */ + bool isp_timeout; + bool isp_fatal_error; + struct work_struct assert_recovery_work; + + spinlock_t lock; /* Protects asd[i].streaming */ + + bool need_gfx_throttle; + + unsigned int mipi_frame_size; + const struct atomisp_dfs_config *dfs; + unsigned int hpll_freq; + + bool css_initialized; +}; + +#define v4l2_dev_to_atomisp_device(dev) \ + container_of(dev, struct atomisp_device, v4l2_dev) + +extern struct device *atomisp_dev; + +#endif /* __ATOMISP_INTERNAL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_ioctl.c b/drivers/staging/media/atomisp/pci/atomisp_ioctl.c new file mode 100644 index 000000000..cb01ba65c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_ioctl.c @@ -0,0 +1,2403 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include + +#include +#include + +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_fops.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" +#include "atomisp-regs.h" +#include "atomisp_compat.h" + +#include "sh_css_hrt.h" + +#include "gp_device.h" +#include "device_access.h" +#include "irq.h" + +static const char *DRIVER = "atomisp"; /* max size 15 */ +static const char *CARD = "ATOM ISP"; /* max size 31 */ + +/* + * FIXME: ISP should not know beforehand all CIDs supported by sensor. + * Instead, it needs to propagate to sensor unkonwn CIDs. + */ +static struct v4l2_queryctrl ci_v4l2_controls[] = { + { + .id = V4L2_CID_AUTO_WHITE_BALANCE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Automatic White Balance", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_RED_BALANCE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Red Balance", + .minimum = 0x00, + .maximum = 0xff, + .step = 1, + .default_value = 0x00, + }, + { + .id = V4L2_CID_BLUE_BALANCE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Blue Balance", + .minimum = 0x00, + .maximum = 0xff, + .step = 1, + .default_value = 0x00, + }, + { + .id = V4L2_CID_GAMMA, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Gamma", + .minimum = 0x00, + .maximum = 0xff, + .step = 1, + .default_value = 0x00, + }, + { + .id = V4L2_CID_POWER_LINE_FREQUENCY, + .type = V4L2_CTRL_TYPE_MENU, + .name = "Light frequency filter", + .minimum = 1, + .maximum = 2, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_COLORFX, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Image Color Effect", + .minimum = 0, + .maximum = 9, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_COLORFX_CBCR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Image Color Effect CbCr", + .minimum = 0, + .maximum = 0xffff, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Bad Pixel Correction", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "GDC/CAC", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_VIDEO_STABLIZATION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Video Stablization", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_FIXED_PATTERN_NR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Fixed Pattern Noise Reduction", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "False Color Correction", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_REQUEST_FLASH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Request flash frames", + .minimum = 0, + .maximum = 10, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_ATOMISP_LOW_LIGHT, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Low light mode", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Horizontal binning factor", + .minimum = 0, + .maximum = 10, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Vertical binning factor", + .minimum = 0, + .maximum = 10, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_2A_STATUS, + .type = V4L2_CTRL_TYPE_BITMASK, + .name = "AE and AWB status", + .minimum = 0, + .maximum = V4L2_2A_STATUS_AE_READY | V4L2_2A_STATUS_AWB_READY, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_EXPOSURE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .minimum = -4, + .maximum = 4, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_EXPOSURE_ZONE_NUM, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "one-time exposure zone number", + .minimum = 0x0, + .maximum = 0xffff, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_EXPOSURE_AUTO_PRIORITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Exposure auto priority", + .minimum = V4L2_EXPOSURE_AUTO, + .maximum = V4L2_EXPOSURE_APERTURE_PRIORITY, + .step = 1, + .default_value = V4L2_EXPOSURE_AUTO, + }, + { + .id = V4L2_CID_SCENE_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "scene mode", + .minimum = 0, + .maximum = 13, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ISO_SENSITIVITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "iso", + .minimum = -4, + .maximum = 4, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ISO_SENSITIVITY_AUTO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "iso mode", + .minimum = V4L2_ISO_SENSITIVITY_MANUAL, + .maximum = V4L2_ISO_SENSITIVITY_AUTO, + .step = 1, + .default_value = V4L2_ISO_SENSITIVITY_AUTO, + }, + { + .id = V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "white balance", + .minimum = 0, + .maximum = 9, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_EXPOSURE_METERING, + .type = V4L2_CTRL_TYPE_MENU, + .name = "metering", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_3A_LOCK, + .type = V4L2_CTRL_TYPE_BITMASK, + .name = "3a lock", + .minimum = 0, + .maximum = V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE + | V4L2_LOCK_FOCUS, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern", + .minimum = 0, + .maximum = 0xffff, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN_COLOR_R, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Solid Color R", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN_COLOR_GR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Solid Color GR", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN_COLOR_GB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Solid Color GB", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN_COLOR_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Solid Color B", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, +}; + +static const u32 ctrls_num = ARRAY_SIZE(ci_v4l2_controls); + +/* + * supported V4L2 fmts and resolutions + */ +const struct atomisp_format_bridge atomisp_output_fmts[] = { + { + .pixelformat = V4L2_PIX_FMT_YUV420, + .depth = 12, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YUV420, + .sh_fmt = IA_CSS_FRAME_FORMAT_YUV420, + .description = "YUV420, planar", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_YVU420, + .depth = 12, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YVU420, + .sh_fmt = IA_CSS_FRAME_FORMAT_YV12, + .description = "YVU420, planar", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_YUV422P, + .depth = 16, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YUV422P, + .sh_fmt = IA_CSS_FRAME_FORMAT_YUV422, + .description = "YUV422, planar", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_YUV444, + .depth = 24, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YUV444, + .sh_fmt = IA_CSS_FRAME_FORMAT_YUV444, + .description = "YUV444" + }, { + .pixelformat = V4L2_PIX_FMT_NV12, + .depth = 12, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_NV12, + .sh_fmt = IA_CSS_FRAME_FORMAT_NV12, + .description = "NV12, Y-plane, CbCr interleaved", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_NV21, + .depth = 12, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_NV21, + .sh_fmt = IA_CSS_FRAME_FORMAT_NV21, + .description = "NV21, Y-plane, CbCr interleaved", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_NV16, + .depth = 16, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_NV16, + .sh_fmt = IA_CSS_FRAME_FORMAT_NV16, + .description = "NV16, Y-plane, CbCr interleaved", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_YUYV, + .depth = 16, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YUYV, + .sh_fmt = IA_CSS_FRAME_FORMAT_YUYV, + .description = "YUYV, interleaved" + }, { + .pixelformat = V4L2_PIX_FMT_UYVY, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, + .sh_fmt = IA_CSS_FRAME_FORMAT_UYVY, + .description = "UYVY, interleaved" + }, { /* This one is for parallel sensors! DO NOT USE! */ + .pixelformat = V4L2_PIX_FMT_UYVY, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, + .sh_fmt = IA_CSS_FRAME_FORMAT_UYVY, + .description = "UYVY, interleaved" + }, { + .pixelformat = V4L2_PIX_FMT_SBGGR16, + .depth = 16, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_SBGGR16, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 16" + }, { + .pixelformat = V4L2_PIX_FMT_SBGGR8, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 8" + }, { + .pixelformat = V4L2_PIX_FMT_SGBRG8, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 8" + }, { + .pixelformat = V4L2_PIX_FMT_SGRBG8, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 8" + }, { + .pixelformat = V4L2_PIX_FMT_SRGGB8, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 8" + }, { + .pixelformat = V4L2_PIX_FMT_SBGGR10, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 10" + }, { + .pixelformat = V4L2_PIX_FMT_SGBRG10, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 10" + }, { + .pixelformat = V4L2_PIX_FMT_SGRBG10, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 10" + }, { + .pixelformat = V4L2_PIX_FMT_SRGGB10, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 10" + }, { + .pixelformat = V4L2_PIX_FMT_SBGGR12, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 12" + }, { + .pixelformat = V4L2_PIX_FMT_SGBRG12, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 12" + }, { + .pixelformat = V4L2_PIX_FMT_SGRBG12, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 12" + }, { + .pixelformat = V4L2_PIX_FMT_SRGGB12, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .sh_fmt = IA_CSS_FRAME_FORMAT_RAW, + .description = "Bayer 12" + }, { + .pixelformat = V4L2_PIX_FMT_RGB32, + .depth = 32, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_RGB32, + .sh_fmt = IA_CSS_FRAME_FORMAT_RGBA888, + .description = "32 RGB 8-8-8-8" + }, { + .pixelformat = V4L2_PIX_FMT_RGB565, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_BGR565_2X8_LE, + .sh_fmt = IA_CSS_FRAME_FORMAT_RGB565, + .description = "16 RGB 5-6-5" +#if 0 + }, { + .pixelformat = V4L2_PIX_FMT_JPEG, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_JPEG_1X8, + .sh_fmt = IA_CSS_FRAME_FORMAT_BINARY_8, + .description = "JPEG" + }, { + /* This is a custom format being used by M10MO to send the RAW data */ + .pixelformat = V4L2_PIX_FMT_CUSTOM_M10MO_RAW, + .depth = 8, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_M10MO_RAW, + .sh_fmt = IA_CSS_FRAME_FORMAT_BINARY_8, + .description = "Custom RAW for M10MO" +#endif + }, +}; + +const struct atomisp_format_bridge * +atomisp_get_format_bridge(unsigned int pixelformat) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_output_fmts); i++) { + if (atomisp_output_fmts[i].pixelformat == pixelformat) + return &atomisp_output_fmts[i]; + } + + return NULL; +} + +const struct atomisp_format_bridge * +atomisp_get_format_bridge_from_mbus(u32 mbus_code) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_output_fmts); i++) { + if (mbus_code == atomisp_output_fmts[i].mbus_code) + return &atomisp_output_fmts[i]; + } + + return NULL; +} + +int atomisp_pipe_check(struct atomisp_video_pipe *pipe, bool settings_change) +{ + lockdep_assert_held(&pipe->isp->mutex); + + if (pipe->isp->isp_fatal_error) + return -EIO; + + if (settings_change && vb2_is_busy(&pipe->vb_queue)) { + dev_err(pipe->isp->dev, "Set fmt/input IOCTL while streaming\n"); + return -EBUSY; + } + + switch (pipe->asd->streaming) { + case ATOMISP_DEVICE_STREAMING_DISABLED: + break; + case ATOMISP_DEVICE_STREAMING_ENABLED: + if (settings_change) { + dev_err(pipe->isp->dev, "Set fmt/input IOCTL while streaming\n"); + return -EBUSY; + } + break; + case ATOMISP_DEVICE_STREAMING_STOPPING: + dev_err(pipe->isp->dev, "IOCTL issued while stopping\n"); + return -EBUSY; + default: + return -EINVAL; + } + + return 0; +} + +/* + * v4l2 ioctls + * return ISP capabilities + */ +static int atomisp_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + + strscpy(cap->driver, DRIVER, sizeof(cap->driver)); + strscpy(cap->card, CARD, sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", dev_name(isp->dev)); + + return 0; +} + +/* + * enum input are used to check primary/secondary camera + */ +static int atomisp_enum_input(struct file *file, void *fh, + struct v4l2_input *input) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + int index = input->index; + struct v4l2_subdev *motor; + + if (index >= isp->input_cnt) + return -EINVAL; + + if (!isp->inputs[index].camera) + return -EINVAL; + + memset(input, 0, sizeof(struct v4l2_input)); + strscpy(input->name, isp->inputs[index].camera->name, + sizeof(input->name)); + + /* + * HACK: append actuator's name to sensor's + * As currently userspace can't talk directly to subdev nodes, this + * ioctl is the only way to enum inputs + possible external actuators + * for 3A tuning purpose. + */ + if (!IS_ISP2401) + motor = isp->inputs[index].motor; + else + motor = isp->motor; + + if (motor && strlen(motor->name) > 0) { + const int cur_len = strlen(input->name); + const int max_size = sizeof(input->name) - cur_len - 1; + + if (max_size > 1) { + input->name[cur_len] = '+'; + strscpy(&input->name[cur_len + 1], + motor->name, max_size); + } + } + + input->type = V4L2_INPUT_TYPE_CAMERA; + input->index = index; + input->reserved[0] = isp->inputs[index].type; + input->reserved[1] = isp->inputs[index].port; + + return 0; +} + +static unsigned int +atomisp_subdev_streaming_count(struct atomisp_sub_device *asd) +{ + return asd->video_out_preview.vb_queue.start_streaming_called + + asd->video_out_capture.vb_queue.start_streaming_called + + asd->video_out_video_capture.vb_queue.start_streaming_called + + asd->video_out_vf.vb_queue.start_streaming_called; +} + +unsigned int atomisp_streaming_count(struct atomisp_device *isp) +{ + unsigned int i, sum; + + for (i = 0, sum = 0; i < isp->num_of_streams; i++) + sum += isp->asd[i].streaming == + ATOMISP_DEVICE_STREAMING_ENABLED; + + return sum; +} + +/* + * get input are used to get current primary/secondary camera + */ +static int atomisp_g_input(struct file *file, void *fh, unsigned int *input) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + + *input = asd->input_curr; + return 0; +} + +static int atomisp_s_fmt_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *vdev = video_devdata(file); + + return atomisp_set_fmt(vdev, f); +} + +/* + * set input are used to set current primary/secondary camera + */ +static int atomisp_s_input(struct file *file, void *fh, unsigned int input) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct v4l2_subdev *camera = NULL; + struct v4l2_subdev *motor; + int ret; + + ret = atomisp_pipe_check(pipe, true); + if (ret) + return ret; + + if (input >= ATOM_ISP_MAX_INPUTS || input >= isp->input_cnt) { + dev_dbg(isp->dev, "input_cnt: %d\n", isp->input_cnt); + return -EINVAL; + } + + /* + * check whether the request camera: + * 1: already in use + * 2: if in use, whether it is used by other streams + */ + if (isp->inputs[input].asd && isp->inputs[input].asd != asd) { + dev_err(isp->dev, + "%s, camera is already used by stream: %d\n", __func__, + isp->inputs[input].asd->index); + return -EBUSY; + } + + camera = isp->inputs[input].camera; + if (!camera) { + dev_err(isp->dev, "%s, no camera\n", __func__); + return -EINVAL; + } + + /* power off the current owned sensor, as it is not used this time */ + if (isp->inputs[asd->input_curr].asd == asd && + asd->input_curr != input) { + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, s_power, 0); + if (ret) + dev_warn(isp->dev, + "Failed to power-off sensor\n"); + /* clear the asd field to show this camera is not used */ + isp->inputs[asd->input_curr].asd = NULL; + } + + /* powe on the new sensor */ + ret = v4l2_subdev_call(isp->inputs[input].camera, core, s_power, 1); + if (ret) { + dev_err(isp->dev, "Failed to power-on sensor\n"); + return ret; + } + /* + * Some sensor driver resets the run mode during power-on, thus force + * update the run mode to sensor after power-on. + */ + atomisp_update_run_mode(asd); + + /* select operating sensor */ + ret = v4l2_subdev_call(isp->inputs[input].camera, video, s_routing, + 0, isp->inputs[input].sensor_index, 0); + if (ret && (ret != -ENOIOCTLCMD)) { + dev_err(isp->dev, "Failed to select sensor\n"); + return ret; + } + + if (!IS_ISP2401) { + motor = isp->inputs[input].motor; + } else { + motor = isp->motor; + if (motor) + ret = v4l2_subdev_call(motor, core, s_power, 1); + } + + if (motor) + ret = v4l2_subdev_call(motor, core, init, 1); + + asd->input_curr = input; + /* mark this camera is used by the current stream */ + isp->inputs[input].asd = asd; + + return 0; +} + +static int atomisp_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct v4l2_subdev_frame_size_enum fse = { + .index = fsize->index, + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + int ret; + + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + pad, enum_frame_size, NULL, &fse); + if (ret) + return ret; + + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; + fsize->discrete.width = fse.max_width - pad_w; + fsize->discrete.height = fse.max_height - pad_h; + + return 0; +} + +static int atomisp_enum_frameintervals(struct file *file, void *priv, + struct v4l2_frmivalenum *fival) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct v4l2_subdev_frame_interval_enum fie = { + .code = atomisp_in_fmt_conv[0].code, + .index = fival->index, + .width = fival->width, + .height = fival->height, + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + int ret; + + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + pad, enum_frame_interval, NULL, + &fie); + if (ret) + return ret; + + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; + fival->discrete = fie.interval; + + return ret; +} + +static int atomisp_enum_fmt_cap(struct file *file, void *fh, + struct v4l2_fmtdesc *f) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct v4l2_subdev_mbus_code_enum code = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + const struct atomisp_format_bridge *format; + struct v4l2_subdev *camera; + unsigned int i, fi = 0; + int rval; + + camera = isp->inputs[asd->input_curr].camera; + if(!camera) { + dev_err(isp->dev, "%s(): camera is NULL, device is %s\n", + __func__, vdev->name); + return -EINVAL; + } + + rval = v4l2_subdev_call(camera, pad, enum_mbus_code, NULL, &code); + if (rval == -ENOIOCTLCMD) { + dev_warn(isp->dev, + "enum_mbus_code pad op not supported by %s. Please fix your sensor driver!\n", + camera->name); + } + + if (rval) + return rval; + + for (i = 0; i < ARRAY_SIZE(atomisp_output_fmts); i++) { + format = &atomisp_output_fmts[i]; + + /* + * Is the atomisp-supported format is valid for the + * sensor (configuration)? If not, skip it. + * + * FIXME: fix the pipeline to allow sensor format too. + */ + if (format->sh_fmt == IA_CSS_FRAME_FORMAT_RAW) + continue; + + /* Found a match. Now let's pick f->index'th one. */ + if (fi < f->index) { + fi++; + continue; + } + + strscpy(f->description, format->description, + sizeof(f->description)); + f->pixelformat = format->pixelformat; + return 0; + } + + return -EINVAL; +} + +static int atomisp_adjust_fmt(struct v4l2_format *f) +{ + const struct atomisp_format_bridge *format_bridge; + u32 padded_width; + + format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat); + /* Currently, raw formats are broken!!! */ + if (!format_bridge || format_bridge->sh_fmt == IA_CSS_FRAME_FORMAT_RAW) { + f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420; + + format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat); + if (!format_bridge) + return -EINVAL; + } + + padded_width = f->fmt.pix.width + pad_w; + + if (format_bridge->planar) { + f->fmt.pix.bytesperline = padded_width; + f->fmt.pix.sizeimage = PAGE_ALIGN(f->fmt.pix.height * + DIV_ROUND_UP(format_bridge->depth * + padded_width, 8)); + } else { + f->fmt.pix.bytesperline = DIV_ROUND_UP(format_bridge->depth * + padded_width, 8); + f->fmt.pix.sizeimage = PAGE_ALIGN(f->fmt.pix.height * f->fmt.pix.bytesperline); + } + + if (f->fmt.pix.field == V4L2_FIELD_ANY) + f->fmt.pix.field = V4L2_FIELD_NONE; + + /* + * FIXME: do we need to setup this differently, depending on the + * sensor or the pipeline? + */ + f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709; + f->fmt.pix.ycbcr_enc = V4L2_YCBCR_ENC_709; + f->fmt.pix.xfer_func = V4L2_XFER_FUNC_709; + + f->fmt.pix.width -= pad_w; + f->fmt.pix.height -= pad_h; + + return 0; +} + +/* This function looks up the closest available resolution. */ +static int atomisp_try_fmt_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *vdev = video_devdata(file); + u32 pixfmt = f->fmt.pix.pixelformat; + int ret; + + /* + * atomisp_try_fmt() gived results with padding included, note + * (this gets removed again by the atomisp_adjust_fmt() call below. + */ + f->fmt.pix.width += pad_w; + f->fmt.pix.height += pad_h; + + ret = atomisp_try_fmt(vdev, &f->fmt.pix, NULL); + if (ret) + return ret; + + /* + * atomisp_try_fmt() replaces pixelformat with the sensors native + * format, restore the actual format requested by userspace. + */ + f->fmt.pix.pixelformat = pixfmt; + + return atomisp_adjust_fmt(f); +} + +static int atomisp_g_fmt_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe; + + pipe = atomisp_to_video_pipe(vdev); + + f->fmt.pix = pipe->pix; + + /* If s_fmt was issued, just return whatever is was previouly set */ + if (f->fmt.pix.sizeimage) + return 0; + + f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420; + f->fmt.pix.width = 10000; + f->fmt.pix.height = 10000; + + return atomisp_try_fmt_cap(file, fh, f); +} + +int atomisp_alloc_css_stat_bufs(struct atomisp_sub_device *asd, + uint16_t stream_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_s3a_buf *s3a_buf = NULL, *_s3a_buf; + struct atomisp_dis_buf *dis_buf = NULL, *_dis_buf; + struct atomisp_metadata_buf *md_buf = NULL, *_md_buf; + int count; + struct ia_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + unsigned int i; + + if (list_empty(&asd->s3a_stats) && + asd->params.curr_grid_info.s3a_grid.enable) { + count = ATOMISP_CSS_Q_DEPTH + + ATOMISP_S3A_BUF_QUEUE_DEPTH_FOR_HAL; + dev_dbg(isp->dev, "allocating %d 3a buffers\n", count); + while (count--) { + s3a_buf = kzalloc(sizeof(struct atomisp_s3a_buf), GFP_KERNEL); + if (!s3a_buf) + goto error; + + if (atomisp_css_allocate_stat_buffers( + asd, stream_id, s3a_buf, NULL, NULL)) { + kfree(s3a_buf); + goto error; + } + + list_add_tail(&s3a_buf->list, &asd->s3a_stats); + } + } + + if (list_empty(&asd->dis_stats) && dvs_grid_info && + dvs_grid_info->enable) { + count = ATOMISP_CSS_Q_DEPTH + 1; + dev_dbg(isp->dev, "allocating %d dis buffers\n", count); + while (count--) { + dis_buf = kzalloc(sizeof(struct atomisp_dis_buf), GFP_KERNEL); + if (!dis_buf) + goto error; + if (atomisp_css_allocate_stat_buffers( + asd, stream_id, NULL, dis_buf, NULL)) { + kfree(dis_buf); + goto error; + } + + list_add_tail(&dis_buf->list, &asd->dis_stats); + } + } + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + if (list_empty(&asd->metadata[i]) && + list_empty(&asd->metadata_ready[i]) && + list_empty(&asd->metadata_in_css[i])) { + count = ATOMISP_CSS_Q_DEPTH + + ATOMISP_METADATA_QUEUE_DEPTH_FOR_HAL; + dev_dbg(isp->dev, "allocating %d metadata buffers for type %d\n", + count, i); + while (count--) { + md_buf = kzalloc(sizeof(struct atomisp_metadata_buf), + GFP_KERNEL); + if (!md_buf) + goto error; + + if (atomisp_css_allocate_stat_buffers( + asd, stream_id, NULL, NULL, md_buf)) { + kfree(md_buf); + goto error; + } + list_add_tail(&md_buf->list, &asd->metadata[i]); + } + } + } + return 0; + +error: + dev_err(isp->dev, "failed to allocate statistics buffers\n"); + + list_for_each_entry_safe(dis_buf, _dis_buf, &asd->dis_stats, list) { + atomisp_css_free_dis_buffer(dis_buf); + list_del(&dis_buf->list); + kfree(dis_buf); + } + + list_for_each_entry_safe(s3a_buf, _s3a_buf, &asd->s3a_stats, list) { + atomisp_css_free_3a_buffer(s3a_buf); + list_del(&s3a_buf->list); + kfree(s3a_buf); + } + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + list_for_each_entry_safe(md_buf, _md_buf, &asd->metadata[i], + list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + } + return -ENOMEM; +} + +static int atomisp_qbuf_wrapper(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + + /* FIXME this abuse of buf->reserved2 comes from the original atomisp buffer handling */ + if (!atomisp_is_vf_pipe(pipe) && + (buf->reserved2 & ATOMISP_BUFFER_HAS_PER_FRAME_SETTING)) { + /* this buffer will have a per-frame parameter */ + pipe->frame_request_config_id[buf->index] = buf->reserved2 & + ~ATOMISP_BUFFER_HAS_PER_FRAME_SETTING; + dev_dbg(isp->dev, + "This buffer requires per_frame setting which has isp_config_id %d\n", + pipe->frame_request_config_id[buf->index]); + } else { + pipe->frame_request_config_id[buf->index] = 0; + } + + return vb2_ioctl_qbuf(file, fh, buf); +} + +static int atomisp_dqbuf_wrapper(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + struct ia_css_frame *frame; + struct vb2_buffer *vb; + int ret; + + ret = vb2_ioctl_dqbuf(file, fh, buf); + if (ret) + return ret; + + vb = pipe->vb_queue.bufs[buf->index]; + frame = vb_to_frame(vb); + + /* FIXME this abuse of buf->reserved* comes from the original atomisp buffer handling */ + buf->reserved = asd->frame_status[buf->index]; + + /* + * Hack: + * Currently frame_status in the enum type which takes no more lower + * 8 bit. + * use bit[31:16] for exp_id as it is only in the range of 1~255 + */ + buf->reserved &= 0x0000ffff; + if (!(buf->flags & V4L2_BUF_FLAG_ERROR)) + buf->reserved |= frame->exp_id; + buf->reserved2 = pipe->frame_config_id[buf->index]; + + dev_dbg(isp->dev, + "dqbuf buffer %d (%s) for asd%d with exp_id %d, isp_config_id %d\n", + buf->index, vdev->name, asd->index, buf->reserved >> 16, + buf->reserved2); + return 0; +} + +enum ia_css_pipe_id atomisp_get_css_pipe_id(struct atomisp_sub_device *asd) +{ + if (ATOMISP_USE_YUVPP(asd)) + return IA_CSS_PIPE_ID_YUVPP; + + if (asd->continuous_mode->val) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + return IA_CSS_PIPE_ID_VIDEO; + else + return IA_CSS_PIPE_ID_PREVIEW; + } + + /* + * Disable vf_pp and run CSS in video mode. This allows using ISP + * scaling but it has one frame delay due to CSS internal buffering. + */ + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) + return IA_CSS_PIPE_ID_VIDEO; + + /* + * Disable vf_pp and run CSS in still capture mode. In this mode + * CSS does not cause extra latency with buffering, but scaling + * is not available. + */ + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) + return IA_CSS_PIPE_ID_CAPTURE; + + switch (asd->run_mode->val) { + case ATOMISP_RUN_MODE_PREVIEW: + return IA_CSS_PIPE_ID_PREVIEW; + case ATOMISP_RUN_MODE_VIDEO: + return IA_CSS_PIPE_ID_VIDEO; + case ATOMISP_RUN_MODE_STILL_CAPTURE: + default: + return IA_CSS_PIPE_ID_CAPTURE; + } +} + +static unsigned int atomisp_sensor_start_stream(struct atomisp_sub_device *asd) +{ + if (asd->vfpp->val != ATOMISP_VFPP_ENABLE || + asd->copy_mode) + return 1; + + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO || + (asd->run_mode->val == ATOMISP_RUN_MODE_STILL_CAPTURE && + !atomisp_is_mbuscode_raw( + asd->fmt[ + asd->capture_pad].fmt.code) && + !asd->continuous_mode->val)) + return 2; + else + return 1; +} + +int atomisp_stream_on_master_slave_sensor(struct atomisp_device *isp, + bool isp_timeout) +{ + unsigned int master, slave, delay_slave = 0; + int ret; + + master = ATOMISP_DEPTH_DEFAULT_MASTER_SENSOR; + slave = ATOMISP_DEPTH_DEFAULT_SLAVE_SENSOR; + dev_warn(isp->dev, + "depth mode use default master=%s.slave=%s.\n", + isp->inputs[master].camera->name, + isp->inputs[slave].camera->name); + + ret = v4l2_subdev_call(isp->inputs[master].camera, core, + ioctl, ATOMISP_IOC_G_DEPTH_SYNC_COMP, + &delay_slave); + if (ret) + dev_warn(isp->dev, + "get depth sensor %s compensation delay failed.\n", + isp->inputs[master].camera->name); + + ret = v4l2_subdev_call(isp->inputs[master].camera, + video, s_stream, 1); + if (ret) { + dev_err(isp->dev, "depth mode master sensor %s stream-on failed.\n", + isp->inputs[master].camera->name); + return -EINVAL; + } + + if (delay_slave != 0) + udelay(delay_slave); + + ret = v4l2_subdev_call(isp->inputs[slave].camera, + video, s_stream, 1); + if (ret) { + dev_err(isp->dev, "depth mode slave sensor %s stream-on failed.\n", + isp->inputs[slave].camera->name); + v4l2_subdev_call(isp->inputs[master].camera, video, s_stream, 0); + + return -EINVAL; + } + + return 0; +} + +/* Input system HW workaround */ +/* Input system address translation corrupts burst during */ +/* invalidate. SW workaround for this is to set burst length */ +/* manually to 128 in case of 13MPx snapshot and to 1 otherwise. */ +static void atomisp_dma_burst_len_cfg(struct atomisp_sub_device *asd) +{ + struct v4l2_mbus_framefmt *sink; + + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + + if (sink->width * sink->height >= 4096 * 3072) + atomisp_css2_hw_store_32(DMA_BURST_SIZE_REG, 0x7F); + else + atomisp_css2_hw_store_32(DMA_BURST_SIZE_REG, 0x00); +} + +int atomisp_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct atomisp_video_pipe *pipe = vq_to_pipe(vq); + struct atomisp_sub_device *asd = pipe->asd; + struct video_device *vdev = &pipe->vdev; + struct atomisp_device *isp = asd->isp; + struct pci_dev *pdev = to_pci_dev(isp->dev); + enum ia_css_pipe_id css_pipe_id; + unsigned int sensor_start_stream; + unsigned long irqflags; + int ret; + + mutex_lock(&isp->mutex); + + dev_dbg(isp->dev, "Start stream on pad %d for asd%d\n", + atomisp_subdev_source_pad(vdev), asd->index); + + ret = atomisp_pipe_check(pipe, false); + if (ret) + goto out_unlock; + + /* Input system HW workaround */ + atomisp_dma_burst_len_cfg(asd); + + /* + * The number of streaming video nodes is based on which + * binary is going to be run. + */ + sensor_start_stream = atomisp_sensor_start_stream(asd); + + /* Reset pending capture request count. */ + asd->pending_capture_request = 0; + + if (atomisp_subdev_streaming_count(asd) > sensor_start_stream) { + /* trigger still capture */ + if (asd->continuous_mode->val && + atomisp_subdev_source_pad(vdev) + == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + dev_dbg(isp->dev, "SDV last video raw buffer id: %u\n", + asd->latest_preview_exp_id); + else + dev_dbg(isp->dev, "ZSL last preview raw buffer id: %u\n", + asd->latest_preview_exp_id); + + if (asd->delayed_init == ATOMISP_DELAYED_INIT_QUEUED) { + flush_work(&asd->delayed_init_work); + mutex_unlock(&isp->mutex); + ret = wait_for_completion_interruptible(&asd->init_done); + mutex_lock(&isp->mutex); + if (ret) { + ret = -ERESTARTSYS; + goto out_unlock; + } + } + + /* handle per_frame_setting parameter and buffers */ + atomisp_handle_parameter_and_buffer(pipe); + + /* + * only ZSL/SDV capture request will be here, raise + * the ISP freq to the highest possible to minimize + * the S2S latency. + */ + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_MAX, false); + /* + * When asd->enable_raw_buffer_lock->val is true, + * An extra IOCTL is needed to call + * atomisp_css_exp_id_capture and trigger real capture + */ + if (!asd->enable_raw_buffer_lock->val) { + ret = atomisp_css_offline_capture_configure(asd, + asd->params.offline_parm.num_captures, + asd->params.offline_parm.skip_frames, + asd->params.offline_parm.offset); + if (ret) { + ret = -EINVAL; + goto out_unlock; + } + } + } + atomisp_qbuffers_to_css(asd); + ret = 0; + goto out_unlock; + } + + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED) { + atomisp_qbuffers_to_css(asd); + goto start_sensor; + } + + css_pipe_id = atomisp_get_css_pipe_id(asd); + + /* Invalidate caches. FIXME: should flush only necessary buffers */ + wbinvd(); + + if (asd->params.css_update_params_needed) { + atomisp_apply_css_parameters(asd, &asd->params.css_param); + if (asd->params.css_param.update_flag.dz_config) + asd->params.config.dz_config = &asd->params.css_param.dz_config; + atomisp_css_update_isp_params(asd); + asd->params.css_update_params_needed = false; + memset(&asd->params.css_param.update_flag, 0, + sizeof(struct atomisp_parameters)); + } + asd->params.dvs_6axis = NULL; + + ret = atomisp_css_start(asd, css_pipe_id, false); + if (ret) { + atomisp_flush_video_pipe(pipe, true); + goto out_unlock; + } + + spin_lock_irqsave(&isp->lock, irqflags); + asd->streaming = ATOMISP_DEVICE_STREAMING_ENABLED; + spin_unlock_irqrestore(&isp->lock, irqflags); + atomic_set(&asd->sof_count, -1); + atomic_set(&asd->sequence, -1); + atomic_set(&asd->sequence_temp, -1); + + asd->params.dis_proj_data_valid = false; + asd->latest_preview_exp_id = 0; + asd->postview_exp_id = 1; + asd->preview_exp_id = 1; + + /* handle per_frame_setting parameter and buffers */ + atomisp_handle_parameter_and_buffer(pipe); + + atomisp_qbuffers_to_css(asd); + + /* Only start sensor when the last streaming instance started */ + if (atomisp_subdev_streaming_count(asd) < sensor_start_stream) { + ret = 0; + goto out_unlock; + } + +start_sensor: + if (isp->flash) { + asd->params.num_flash_frames = 0; + asd->params.flash_state = ATOMISP_FLASH_IDLE; + atomisp_setup_flash(asd); + } + + atomisp_css_irq_enable(isp, IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF, + atomisp_css_valid_sof(isp)); + atomisp_csi2_configure(asd); + /* + * set freq to max when streaming count > 1 which indicate + * dual camera would run + */ + if (atomisp_streaming_count(isp) > 1) { + if (atomisp_freq_scaling(isp, + ATOMISP_DFS_MODE_MAX, false) < 0) + dev_dbg(isp->dev, "DFS max mode failed!\n"); + } else { + if (atomisp_freq_scaling(isp, + ATOMISP_DFS_MODE_AUTO, false) < 0) + dev_dbg(isp->dev, "DFS auto mode failed!\n"); + } + + if (asd->depth_mode->val && atomisp_streaming_count(isp) == + ATOMISP_DEPTH_SENSOR_STREAMON_COUNT) { + ret = atomisp_stream_on_master_slave_sensor(isp, false); + if (ret) { + dev_err(isp->dev, "master slave sensor stream on failed!\n"); + goto out_unlock; + } + goto start_delay_wq; + } else if (asd->depth_mode->val && (atomisp_streaming_count(isp) < + ATOMISP_DEPTH_SENSOR_STREAMON_COUNT)) { + goto start_delay_wq; + } + + /* Enable the CSI interface on ANN B0/K0 */ + if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << + ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)) { + pci_write_config_word(pdev, MRFLD_PCI_CSI_CONTROL, + isp->saved_regs.csi_control | MRFLD_PCI_CSI_CONTROL_CSI_READY); + } + + /* stream on the sensor */ + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_stream, 1); + if (ret) { + spin_lock_irqsave(&isp->lock, irqflags); + asd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED; + spin_unlock_irqrestore(&isp->lock, irqflags); + ret = -EINVAL; + goto out_unlock; + } + +start_delay_wq: + if (asd->continuous_mode->val) { + atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + + reinit_completion(&asd->init_done); + asd->delayed_init = ATOMISP_DELAYED_INIT_QUEUED; + queue_work(asd->delayed_init_workq, &asd->delayed_init_work); + } else { + asd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED; + } + +out_unlock: + mutex_unlock(&isp->mutex); + return ret; +} + +void atomisp_stop_streaming(struct vb2_queue *vq) +{ + struct atomisp_video_pipe *pipe = vq_to_pipe(vq); + struct atomisp_sub_device *asd = pipe->asd; + struct video_device *vdev = &pipe->vdev; + struct atomisp_device *isp = asd->isp; + struct pci_dev *pdev = to_pci_dev(isp->dev); + bool recreate_streams[MAX_STREAM_NUM] = {0}; + enum ia_css_pipe_id css_pipe_id; + bool first_streamoff = false; + unsigned long flags; + int i, ret; + + mutex_lock(&isp->mutex); + + dev_dbg(isp->dev, "Stop stream on pad %d for asd%d\n", + atomisp_subdev_source_pad(vdev), asd->index); + + /* + * There is no guarantee that the buffers queued to / owned by the ISP + * will properly be returned to the queue when stopping. Set a flag to + * avoid new buffers getting queued and then wait for all the current + * buffers to finish. + */ + pipe->stopping = true; + mutex_unlock(&isp->mutex); + /* wait max 1 second */ + ret = wait_event_timeout(pipe->vb_queue.done_wq, + atomisp_buffers_in_css(pipe) == 0, HZ); + mutex_lock(&isp->mutex); + pipe->stopping = false; + if (ret == 0) + dev_warn(isp->dev, "Warning timeout waiting for CSS to return buffers\n"); + + /* + * do only videobuf_streamoff for capture & vf pipes in + * case of continuous capture + */ + if (asd->continuous_mode->val && + atomisp_subdev_source_pad(vdev) != ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW && + atomisp_subdev_source_pad(vdev) != ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) { + if (atomisp_subdev_source_pad(vdev) == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) { + /* stop continuous still capture if needed */ + if (asd->params.offline_parm.num_captures == -1) + atomisp_css_offline_capture_configure(asd, + 0, 0, 0); + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_AUTO, false); + } + + goto out_unlock; + } + + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED) + first_streamoff = true; + + spin_lock_irqsave(&isp->lock, flags); + if (atomisp_subdev_streaming_count(asd) == 1) + asd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED; + else + asd->streaming = ATOMISP_DEVICE_STREAMING_STOPPING; + spin_unlock_irqrestore(&isp->lock, flags); + + if (!first_streamoff) + goto stopsensor; + + atomisp_clear_css_buffer_counters(asd); + atomisp_css_irq_enable(isp, IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF, false); + + if (asd->delayed_init == ATOMISP_DELAYED_INIT_QUEUED) { + cancel_work_sync(&asd->delayed_init_work); + asd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED; + } + + css_pipe_id = atomisp_get_css_pipe_id(asd); + atomisp_css_stop(asd, css_pipe_id, false); + + atomisp_flush_video_pipe(pipe, true); + + atomisp_subdev_cleanup_pending_events(asd); +stopsensor: + if (atomisp_subdev_streaming_count(asd) != atomisp_sensor_start_stream(asd)) + goto out_unlock; + + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_stream, 0); + + if (isp->flash) { + asd->params.num_flash_frames = 0; + asd->params.flash_state = ATOMISP_FLASH_IDLE; + } + + /* if other streams are running, isp should not be powered off */ + if (atomisp_streaming_count(isp)) { + atomisp_css_flush(isp); + goto out_unlock; + } + + /* Disable the CSI interface on ANN B0/K0 */ + if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << + ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)) { + pci_write_config_word(pdev, MRFLD_PCI_CSI_CONTROL, + isp->saved_regs.csi_control & ~MRFLD_PCI_CSI_CONTROL_CSI_READY); + } + + if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, false)) + dev_warn(isp->dev, "DFS failed.\n"); + /* + * ISP work around, need to reset isp + * Is it correct time to reset ISP when first node does streamoff? + */ + if (isp->isp_timeout) + dev_err(isp->dev, "%s: Resetting with WA activated", + __func__); + /* + * It is possible that the other asd stream is in the stage + * that v4l2_setfmt is just get called on it, which will + * create css stream on that stream. But at this point, there + * is no way to destroy the css stream created on that stream. + * + * So force stream destroy here. + */ + for (i = 0; i < isp->num_of_streams; i++) { + if (isp->asd[i].stream_prepared) { + atomisp_destroy_pipes_stream_force(&isp->asd[i]); + recreate_streams[i] = true; + } + } + + /* disable PUNIT/ISP acknowlede/handshake - SRSE=3 */ + pci_write_config_dword(pdev, PCI_I_CONTROL, + isp->saved_regs.i_control | MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK); + dev_err(isp->dev, "atomisp_reset"); + atomisp_reset(isp); + for (i = 0; i < isp->num_of_streams; i++) { + if (recreate_streams[i]) { + int ret2; + + ret2 = atomisp_create_pipes_stream(&isp->asd[i]); + if (ret2) { + dev_err(isp->dev, "%s error re-creating streams: %d\n", + __func__, ret2); + if (!ret) + ret = ret2; + } + } + } + isp->isp_timeout = false; +out_unlock: + mutex_unlock(&isp->mutex); +} + +/* + * To get the current value of a control. + * applications initialize the id field of a struct v4l2_control and + * call this ioctl with a pointer to this structure + */ +static int atomisp_g_ctrl(struct file *file, void *fh, + struct v4l2_control *control) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + int i, ret = -EINVAL; + + for (i = 0; i < ctrls_num; i++) { + if (ci_v4l2_controls[i].id == control->id) { + ret = 0; + break; + } + } + + if (ret) + return ret; + + switch (control->id) { + case V4L2_CID_IRIS_ABSOLUTE: + case V4L2_CID_EXPOSURE_ABSOLUTE: + case V4L2_CID_FNUMBER_ABSOLUTE: + case V4L2_CID_2A_STATUS: + case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE: + case V4L2_CID_EXPOSURE: + case V4L2_CID_EXPOSURE_AUTO: + case V4L2_CID_SCENE_MODE: + case V4L2_CID_ISO_SENSITIVITY: + case V4L2_CID_ISO_SENSITIVITY_AUTO: + case V4L2_CID_CONTRAST: + case V4L2_CID_SATURATION: + case V4L2_CID_SHARPNESS: + case V4L2_CID_3A_LOCK: + case V4L2_CID_EXPOSURE_ZONE_NUM: + case V4L2_CID_TEST_PATTERN: + case V4L2_CID_TEST_PATTERN_COLOR_R: + case V4L2_CID_TEST_PATTERN_COLOR_GR: + case V4L2_CID_TEST_PATTERN_COLOR_GB: + case V4L2_CID_TEST_PATTERN_COLOR_B: + return v4l2_g_ctrl(isp->inputs[asd->input_curr].camera-> + ctrl_handler, control); + case V4L2_CID_COLORFX: + ret = atomisp_color_effect(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION: + ret = atomisp_bad_pixel(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC: + ret = atomisp_gdc_cac(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_VIDEO_STABLIZATION: + ret = atomisp_video_stable(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_FIXED_PATTERN_NR: + ret = atomisp_fixed_pattern(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION: + ret = atomisp_false_color(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_LOW_LIGHT: + ret = atomisp_low_light(asd, 0, &control->value); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +/* + * To change the value of a control. + * applications initialize the id and value fields of a struct v4l2_control + * and call this ioctl. + */ +static int atomisp_s_ctrl(struct file *file, void *fh, + struct v4l2_control *control) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + int i, ret = -EINVAL; + + for (i = 0; i < ctrls_num; i++) { + if (ci_v4l2_controls[i].id == control->id) { + ret = 0; + break; + } + } + + if (ret) + return ret; + + switch (control->id) { + case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE: + case V4L2_CID_EXPOSURE: + case V4L2_CID_EXPOSURE_AUTO: + case V4L2_CID_EXPOSURE_AUTO_PRIORITY: + case V4L2_CID_SCENE_MODE: + case V4L2_CID_ISO_SENSITIVITY: + case V4L2_CID_ISO_SENSITIVITY_AUTO: + case V4L2_CID_POWER_LINE_FREQUENCY: + case V4L2_CID_EXPOSURE_METERING: + case V4L2_CID_CONTRAST: + case V4L2_CID_SATURATION: + case V4L2_CID_SHARPNESS: + case V4L2_CID_3A_LOCK: + case V4L2_CID_COLORFX_CBCR: + case V4L2_CID_TEST_PATTERN: + case V4L2_CID_TEST_PATTERN_COLOR_R: + case V4L2_CID_TEST_PATTERN_COLOR_GR: + case V4L2_CID_TEST_PATTERN_COLOR_GB: + case V4L2_CID_TEST_PATTERN_COLOR_B: + return v4l2_s_ctrl(NULL, + isp->inputs[asd->input_curr].camera-> + ctrl_handler, control); + case V4L2_CID_COLORFX: + ret = atomisp_color_effect(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION: + ret = atomisp_bad_pixel(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC: + ret = atomisp_gdc_cac(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_VIDEO_STABLIZATION: + ret = atomisp_video_stable(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_FIXED_PATTERN_NR: + ret = atomisp_fixed_pattern(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION: + ret = atomisp_false_color(asd, 1, &control->value); + break; + case V4L2_CID_REQUEST_FLASH: + ret = atomisp_flash_enable(asd, control->value); + break; + case V4L2_CID_ATOMISP_LOW_LIGHT: + ret = atomisp_low_light(asd, 1, &control->value); + break; + default: + ret = -EINVAL; + break; + } + return ret; +} + +/* + * To query the attributes of a control. + * applications set the id field of a struct v4l2_queryctrl and call the + * this ioctl with a pointer to this structure. The driver fills + * the rest of the structure. + */ +static int atomisp_queryctl(struct file *file, void *fh, + struct v4l2_queryctrl *qc) +{ + int i, ret = -EINVAL; + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + + switch (qc->id) { + case V4L2_CID_FOCUS_ABSOLUTE: + case V4L2_CID_FOCUS_RELATIVE: + case V4L2_CID_FOCUS_STATUS: + if (!IS_ISP2401) { + return v4l2_queryctrl(isp->inputs[asd->input_curr].camera-> + ctrl_handler, qc); + } + /* ISP2401 */ + if (isp->motor) + return v4l2_queryctrl(isp->motor->ctrl_handler, qc); + else + return v4l2_queryctrl(isp->inputs[asd->input_curr]. + camera->ctrl_handler, qc); + } + + if (qc->id & V4L2_CTRL_FLAG_NEXT_CTRL) + return ret; + + for (i = 0; i < ctrls_num; i++) { + if (ci_v4l2_controls[i].id == qc->id) { + memcpy(qc, &ci_v4l2_controls[i], + sizeof(struct v4l2_queryctrl)); + qc->reserved[0] = 0; + ret = 0; + break; + } + } + if (ret != 0) + qc->flags = V4L2_CTRL_FLAG_DISABLED; + + return ret; +} + +static int atomisp_camera_g_ext_ctrls(struct file *file, void *fh, + struct v4l2_ext_controls *c) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + struct v4l2_subdev *motor; + struct v4l2_control ctrl; + int i; + int ret = 0; + + if (!IS_ISP2401) + motor = isp->inputs[asd->input_curr].motor; + else + motor = isp->motor; + + for (i = 0; i < c->count; i++) { + ctrl.id = c->controls[i].id; + ctrl.value = c->controls[i].value; + switch (ctrl.id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + case V4L2_CID_EXPOSURE_AUTO: + case V4L2_CID_IRIS_ABSOLUTE: + case V4L2_CID_FNUMBER_ABSOLUTE: + case V4L2_CID_BIN_FACTOR_HORZ: + case V4L2_CID_BIN_FACTOR_VERT: + case V4L2_CID_3A_LOCK: + case V4L2_CID_TEST_PATTERN: + case V4L2_CID_TEST_PATTERN_COLOR_R: + case V4L2_CID_TEST_PATTERN_COLOR_GR: + case V4L2_CID_TEST_PATTERN_COLOR_GB: + case V4L2_CID_TEST_PATTERN_COLOR_B: + /* + * Exposure related control will be handled by sensor + * driver + */ + ret = + v4l2_g_ctrl(isp->inputs[asd->input_curr].camera-> + ctrl_handler, &ctrl); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + case V4L2_CID_FOCUS_RELATIVE: + case V4L2_CID_FOCUS_STATUS: + case V4L2_CID_FOCUS_AUTO: + if (motor) + ret = v4l2_g_ctrl(motor->ctrl_handler, &ctrl); + break; + case V4L2_CID_FLASH_STATUS: + case V4L2_CID_FLASH_INTENSITY: + case V4L2_CID_FLASH_TORCH_INTENSITY: + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + case V4L2_CID_FLASH_TIMEOUT: + case V4L2_CID_FLASH_STROBE: + case V4L2_CID_FLASH_MODE: + case V4L2_CID_FLASH_STATUS_REGISTER: + if (isp->flash) + ret = + v4l2_g_ctrl(isp->flash->ctrl_handler, + &ctrl); + break; + case V4L2_CID_ZOOM_ABSOLUTE: + ret = atomisp_digital_zoom(asd, 0, &ctrl.value); + break; + case V4L2_CID_G_SKIP_FRAMES: + ret = v4l2_subdev_call( + isp->inputs[asd->input_curr].camera, + sensor, g_skip_frames, (u32 *)&ctrl.value); + break; + default: + ret = -EINVAL; + } + + if (ret) { + c->error_idx = i; + break; + } + c->controls[i].value = ctrl.value; + } + return ret; +} + +/* This ioctl allows the application to get multiple controls by class */ +static int atomisp_g_ext_ctrls(struct file *file, void *fh, + struct v4l2_ext_controls *c) +{ + struct v4l2_control ctrl; + int i, ret = 0; + + /* + * input_lock is not need for the Camera related IOCTLs + * The input_lock downgrade the FPS of 3A + */ + ret = atomisp_camera_g_ext_ctrls(file, fh, c); + if (ret != -EINVAL) + return ret; + + for (i = 0; i < c->count; i++) { + ctrl.id = c->controls[i].id; + ctrl.value = c->controls[i].value; + ret = atomisp_g_ctrl(file, fh, &ctrl); + c->controls[i].value = ctrl.value; + if (ret) { + c->error_idx = i; + break; + } + } + return ret; +} + +static int atomisp_camera_s_ext_ctrls(struct file *file, void *fh, + struct v4l2_ext_controls *c) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + struct v4l2_subdev *motor; + struct v4l2_control ctrl; + int i; + int ret = 0; + + if (!IS_ISP2401) + motor = isp->inputs[asd->input_curr].motor; + else + motor = isp->motor; + + for (i = 0; i < c->count; i++) { + struct v4l2_ctrl *ctr; + + ctrl.id = c->controls[i].id; + ctrl.value = c->controls[i].value; + switch (ctrl.id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + case V4L2_CID_EXPOSURE_AUTO: + case V4L2_CID_EXPOSURE_METERING: + case V4L2_CID_IRIS_ABSOLUTE: + case V4L2_CID_FNUMBER_ABSOLUTE: + case V4L2_CID_VCM_TIMING: + case V4L2_CID_VCM_SLEW: + case V4L2_CID_3A_LOCK: + case V4L2_CID_TEST_PATTERN: + case V4L2_CID_TEST_PATTERN_COLOR_R: + case V4L2_CID_TEST_PATTERN_COLOR_GR: + case V4L2_CID_TEST_PATTERN_COLOR_GB: + case V4L2_CID_TEST_PATTERN_COLOR_B: + ret = v4l2_s_ctrl(NULL, + isp->inputs[asd->input_curr].camera-> + ctrl_handler, &ctrl); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + case V4L2_CID_FOCUS_RELATIVE: + case V4L2_CID_FOCUS_STATUS: + case V4L2_CID_FOCUS_AUTO: + if (motor) + ret = v4l2_s_ctrl(NULL, motor->ctrl_handler, + &ctrl); + else + ret = v4l2_s_ctrl(NULL, + isp->inputs[asd->input_curr]. + camera->ctrl_handler, &ctrl); + break; + case V4L2_CID_FLASH_STATUS: + case V4L2_CID_FLASH_INTENSITY: + case V4L2_CID_FLASH_TORCH_INTENSITY: + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + case V4L2_CID_FLASH_TIMEOUT: + case V4L2_CID_FLASH_STROBE: + case V4L2_CID_FLASH_MODE: + case V4L2_CID_FLASH_STATUS_REGISTER: + if (isp->flash) { + ret = + v4l2_s_ctrl(NULL, isp->flash->ctrl_handler, + &ctrl); + /* + * When flash mode is changed we need to reset + * flash state + */ + if (ctrl.id == V4L2_CID_FLASH_MODE) { + asd->params.flash_state = + ATOMISP_FLASH_IDLE; + asd->params.num_flash_frames = 0; + } + } + break; + case V4L2_CID_ZOOM_ABSOLUTE: + ret = atomisp_digital_zoom(asd, 1, &ctrl.value); + break; + default: + ctr = v4l2_ctrl_find(&asd->ctrl_handler, ctrl.id); + if (ctr) + ret = v4l2_ctrl_s_ctrl(ctr, ctrl.value); + else + ret = -EINVAL; + } + + if (ret) { + c->error_idx = i; + break; + } + c->controls[i].value = ctrl.value; + } + return ret; +} + +/* This ioctl allows the application to set multiple controls by class */ +static int atomisp_s_ext_ctrls(struct file *file, void *fh, + struct v4l2_ext_controls *c) +{ + struct v4l2_control ctrl; + int i, ret = 0; + + /* + * input_lock is not need for the Camera related IOCTLs + * The input_lock downgrade the FPS of 3A + */ + ret = atomisp_camera_s_ext_ctrls(file, fh, c); + if (ret != -EINVAL) + return ret; + + for (i = 0; i < c->count; i++) { + ctrl.id = c->controls[i].id; + ctrl.value = c->controls[i].value; + ret = atomisp_s_ctrl(file, fh, &ctrl); + c->controls[i].value = ctrl.value; + if (ret) { + c->error_idx = i; + break; + } + } + return ret; +} + +/* + * vidioc_g/s_param are used to switch isp running mode + */ +static int atomisp_g_parm(struct file *file, void *fh, + struct v4l2_streamparm *parm) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(isp->dev, "unsupported v4l2 buf type\n"); + return -EINVAL; + } + + parm->parm.capture.capturemode = asd->run_mode->val; + + return 0; +} + +static int atomisp_s_parm(struct file *file, void *fh, + struct v4l2_streamparm *parm) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + int mode; + int rval; + int fps; + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(isp->dev, "unsupported v4l2 buf type\n"); + return -EINVAL; + } + + asd->high_speed_mode = false; + switch (parm->parm.capture.capturemode) { + case CI_MODE_NONE: { + struct v4l2_subdev_frame_interval fi = {0}; + + fi.interval = parm->parm.capture.timeperframe; + + rval = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_frame_interval, &fi); + if (!rval) + parm->parm.capture.timeperframe = fi.interval; + + if (fi.interval.numerator != 0) { + fps = fi.interval.denominator / fi.interval.numerator; + if (fps > 30) + asd->high_speed_mode = true; + } + + return rval == -ENOIOCTLCMD ? 0 : rval; + } + case CI_MODE_VIDEO: + mode = ATOMISP_RUN_MODE_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + mode = ATOMISP_RUN_MODE_STILL_CAPTURE; + break; + case CI_MODE_CONTINUOUS: + mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE; + break; + case CI_MODE_PREVIEW: + mode = ATOMISP_RUN_MODE_PREVIEW; + break; + default: + return -EINVAL; + } + + rval = v4l2_ctrl_s_ctrl(asd->run_mode, mode); + + return rval == -ENOIOCTLCMD ? 0 : rval; +} + +static long atomisp_vidioc_default(struct file *file, void *fh, + bool valid_prio, unsigned int cmd, void *arg) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct v4l2_subdev *motor; + int err; + + if (!IS_ISP2401) + motor = isp->inputs[asd->input_curr].motor; + else + motor = isp->motor; + + switch (cmd) { + case ATOMISP_IOC_S_SENSOR_RUNMODE: + if (IS_ISP2401) + err = atomisp_set_sensor_runmode(asd, arg); + else + err = -EINVAL; + break; + + case ATOMISP_IOC_G_XNR: + err = atomisp_xnr(asd, 0, arg); + break; + + case ATOMISP_IOC_S_XNR: + err = atomisp_xnr(asd, 1, arg); + break; + + case ATOMISP_IOC_G_NR: + err = atomisp_nr(asd, 0, arg); + break; + + case ATOMISP_IOC_S_NR: + err = atomisp_nr(asd, 1, arg); + break; + + case ATOMISP_IOC_G_TNR: + err = atomisp_tnr(asd, 0, arg); + break; + + case ATOMISP_IOC_S_TNR: + err = atomisp_tnr(asd, 1, arg); + break; + + case ATOMISP_IOC_G_BLACK_LEVEL_COMP: + err = atomisp_black_level(asd, 0, arg); + break; + + case ATOMISP_IOC_S_BLACK_LEVEL_COMP: + err = atomisp_black_level(asd, 1, arg); + break; + + case ATOMISP_IOC_G_EE: + err = atomisp_ee(asd, 0, arg); + break; + + case ATOMISP_IOC_S_EE: + err = atomisp_ee(asd, 1, arg); + break; + + case ATOMISP_IOC_G_DIS_STAT: + err = atomisp_get_dis_stat(asd, arg); + break; + + case ATOMISP_IOC_G_DVS2_BQ_RESOLUTIONS: + err = atomisp_get_dvs2_bq_resolutions(asd, arg); + break; + + case ATOMISP_IOC_S_DIS_COEFS: + err = atomisp_css_cp_dvs2_coefs(asd, arg, + &asd->params.css_param, true); + if (!err && arg) + asd->params.css_update_params_needed = true; + break; + + case ATOMISP_IOC_S_DIS_VECTOR: + err = atomisp_cp_dvs_6axis_config(asd, arg, + &asd->params.css_param, true); + if (!err && arg) + asd->params.css_update_params_needed = true; + break; + + case ATOMISP_IOC_G_ISP_PARM: + err = atomisp_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_PARM: + err = atomisp_param(asd, 1, arg); + break; + + case ATOMISP_IOC_G_3A_STAT: + err = atomisp_3a_stat(asd, 0, arg); + break; + + case ATOMISP_IOC_G_ISP_GAMMA: + err = atomisp_gamma(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_GAMMA: + err = atomisp_gamma(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_GDC_TAB: + err = atomisp_gdc_cac_table(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_GDC_TAB: + err = atomisp_gdc_cac_table(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_MACC: + err = atomisp_macc_table(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_MACC: + err = atomisp_macc_table(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_BAD_PIXEL_DETECTION: + err = atomisp_bad_pixel_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_BAD_PIXEL_DETECTION: + err = atomisp_bad_pixel_param(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_FALSE_COLOR_CORRECTION: + err = atomisp_false_color_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_FALSE_COLOR_CORRECTION: + err = atomisp_false_color_param(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_CTC: + err = atomisp_ctc(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_CTC: + err = atomisp_ctc(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_WHITE_BALANCE: + err = atomisp_white_balance_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_WHITE_BALANCE: + err = atomisp_white_balance_param(asd, 1, arg); + break; + + case ATOMISP_IOC_G_3A_CONFIG: + err = atomisp_3a_config_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_3A_CONFIG: + err = atomisp_3a_config_param(asd, 1, arg); + break; + + case ATOMISP_IOC_S_ISP_FPN_TABLE: + err = atomisp_fixed_pattern_table(asd, arg); + break; + + case ATOMISP_IOC_ISP_MAKERNOTE: + err = atomisp_exif_makernote(asd, arg); + break; + + case ATOMISP_IOC_G_SENSOR_MODE_DATA: + err = atomisp_get_sensor_mode_data(asd, arg); + break; + + case ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA: + if (motor) + err = v4l2_subdev_call(motor, core, ioctl, cmd, arg); + else + err = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, ioctl, cmd, arg); + break; + + case ATOMISP_IOC_S_EXPOSURE: + case ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP: + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_INFO: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT: + err = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, ioctl, cmd, arg); + break; + case ATOMISP_IOC_G_UPDATE_EXPOSURE: + if (IS_ISP2401) + err = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, ioctl, cmd, arg); + else + err = -EINVAL; + break; + + case ATOMISP_IOC_S_ISP_SHD_TAB: + err = atomisp_set_shading_table(asd, arg); + break; + + case ATOMISP_IOC_G_ISP_GAMMA_CORRECTION: + err = atomisp_gamma_correction(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_GAMMA_CORRECTION: + err = atomisp_gamma_correction(asd, 1, arg); + break; + + case ATOMISP_IOC_S_PARAMETERS: + err = atomisp_set_parameters(vdev, arg); + break; + + case ATOMISP_IOC_S_CONT_CAPTURE_CONFIG: + err = atomisp_offline_capture_configure(asd, arg); + break; + case ATOMISP_IOC_G_METADATA: + err = atomisp_get_metadata(asd, 0, arg); + break; + case ATOMISP_IOC_G_METADATA_BY_TYPE: + err = atomisp_get_metadata_by_type(asd, 0, arg); + break; + case ATOMISP_IOC_EXT_ISP_CTRL: + err = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, ioctl, cmd, arg); + break; + case ATOMISP_IOC_EXP_ID_UNLOCK: + err = atomisp_exp_id_unlock(asd, arg); + break; + case ATOMISP_IOC_EXP_ID_CAPTURE: + err = atomisp_exp_id_capture(asd, arg); + break; + case ATOMISP_IOC_S_ENABLE_DZ_CAPT_PIPE: + err = atomisp_enable_dz_capt_pipe(asd, arg); + break; + case ATOMISP_IOC_G_FORMATS_CONFIG: + err = atomisp_formats(asd, 0, arg); + break; + + case ATOMISP_IOC_S_FORMATS_CONFIG: + err = atomisp_formats(asd, 1, arg); + break; + case ATOMISP_IOC_S_EXPOSURE_WINDOW: + err = atomisp_s_ae_window(asd, arg); + break; + case ATOMISP_IOC_INJECT_A_FAKE_EVENT: + err = atomisp_inject_a_fake_event(asd, arg); + break; + case ATOMISP_IOC_G_INVALID_FRAME_NUM: + err = atomisp_get_invalid_frame_num(vdev, arg); + break; + case ATOMISP_IOC_S_ARRAY_RESOLUTION: + err = atomisp_set_array_res(asd, arg); + break; + default: + err = -EINVAL; + break; + } + + return err; +} + +const struct v4l2_ioctl_ops atomisp_ioctl_ops = { + .vidioc_querycap = atomisp_querycap, + .vidioc_enum_input = atomisp_enum_input, + .vidioc_g_input = atomisp_g_input, + .vidioc_s_input = atomisp_s_input, + .vidioc_queryctrl = atomisp_queryctl, + .vidioc_s_ctrl = atomisp_s_ctrl, + .vidioc_g_ctrl = atomisp_g_ctrl, + .vidioc_s_ext_ctrls = atomisp_s_ext_ctrls, + .vidioc_g_ext_ctrls = atomisp_g_ext_ctrls, + .vidioc_enum_framesizes = atomisp_enum_framesizes, + .vidioc_enum_frameintervals = atomisp_enum_frameintervals, + .vidioc_enum_fmt_vid_cap = atomisp_enum_fmt_cap, + .vidioc_try_fmt_vid_cap = atomisp_try_fmt_cap, + .vidioc_g_fmt_vid_cap = atomisp_g_fmt_cap, + .vidioc_s_fmt_vid_cap = atomisp_s_fmt_cap, + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = atomisp_qbuf_wrapper, + .vidioc_dqbuf = atomisp_dqbuf_wrapper, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + .vidioc_default = atomisp_vidioc_default, + .vidioc_s_parm = atomisp_s_parm, + .vidioc_g_parm = atomisp_g_parm, +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp_ioctl.h b/drivers/staging/media/atomisp/pci/atomisp_ioctl.h new file mode 100644 index 000000000..59e071f03 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_ioctl.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_IOCTL_H__ +#define __ATOMISP_IOCTL_H__ + +#include "ia_css.h" + +struct atomisp_device; +struct atomisp_video_pipe; + +extern const struct atomisp_format_bridge atomisp_output_fmts[]; + +const struct +atomisp_format_bridge *atomisp_get_format_bridge(unsigned int pixelformat); + +const struct +atomisp_format_bridge *atomisp_get_format_bridge_from_mbus(u32 mbus_code); + +int atomisp_pipe_check(struct atomisp_video_pipe *pipe, bool streaming_ok); + +int atomisp_alloc_css_stat_bufs(struct atomisp_sub_device *asd, + uint16_t stream_id); + +int atomisp_start_streaming(struct vb2_queue *vq, unsigned int count); +void atomisp_stop_streaming(struct vb2_queue *vq); + +enum ia_css_pipe_id atomisp_get_css_pipe_id(struct atomisp_sub_device + *asd); + +extern const struct v4l2_ioctl_ops atomisp_ioctl_ops; + +unsigned int atomisp_streaming_count(struct atomisp_device *isp); + +/* compat_ioctl for 32bit userland app and 64bit kernel */ +long atomisp_compat_ioctl32(struct file *file, + unsigned int cmd, unsigned long arg); + +int atomisp_stream_on_master_slave_sensor(struct atomisp_device *isp, + bool isp_timeout); + +int atomisp_start_streaming(struct vb2_queue *vq, unsigned int count); +void atomisp_stop_streaming(struct vb2_queue *vq); + +#endif /* __ATOMISP_IOCTL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_subdev.c b/drivers/staging/media/atomisp/pci/atomisp_subdev.c new file mode 100644 index 000000000..cadc468b4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_subdev.c @@ -0,0 +1,1371 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_compat.h" +#include "atomisp_internal.h" + +const struct atomisp_in_fmt_conv atomisp_in_fmt_conv[] = { + { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, ATOMISP_INPUT_FORMAT_RAW_8, IA_CSS_BAYER_ORDER_BGGR }, + { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, ATOMISP_INPUT_FORMAT_RAW_8, IA_CSS_BAYER_ORDER_GBRG }, + { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, ATOMISP_INPUT_FORMAT_RAW_8, IA_CSS_BAYER_ORDER_GRBG }, + { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, ATOMISP_INPUT_FORMAT_RAW_8, IA_CSS_BAYER_ORDER_RGGB }, + { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, ATOMISP_INPUT_FORMAT_RAW_10, IA_CSS_BAYER_ORDER_BGGR }, + { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, ATOMISP_INPUT_FORMAT_RAW_10, IA_CSS_BAYER_ORDER_GBRG }, + { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, ATOMISP_INPUT_FORMAT_RAW_10, IA_CSS_BAYER_ORDER_GRBG }, + { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, ATOMISP_INPUT_FORMAT_RAW_10, IA_CSS_BAYER_ORDER_RGGB }, + { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, ATOMISP_INPUT_FORMAT_RAW_12, IA_CSS_BAYER_ORDER_BGGR }, + { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, ATOMISP_INPUT_FORMAT_RAW_12, IA_CSS_BAYER_ORDER_GBRG }, + { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, ATOMISP_INPUT_FORMAT_RAW_12, IA_CSS_BAYER_ORDER_GRBG }, + { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, ATOMISP_INPUT_FORMAT_RAW_12, IA_CSS_BAYER_ORDER_RGGB }, + { MEDIA_BUS_FMT_UYVY8_1X16, 8, 8, ATOMISP_INPUT_FORMAT_YUV422_8, 0 }, + { MEDIA_BUS_FMT_YUYV8_1X16, 8, 8, ATOMISP_INPUT_FORMAT_YUV422_8, 0 }, +#if 0 // disabled due to clang warnings + { MEDIA_BUS_FMT_JPEG_1X8, 8, 8, IA_CSS_FRAME_FORMAT_BINARY_8, 0 }, + { V4L2_MBUS_FMT_CUSTOM_NV12, 12, 12, IA_CSS_FRAME_FORMAT_NV12, 0 }, + { V4L2_MBUS_FMT_CUSTOM_NV21, 12, 12, IA_CSS_FRAME_FORMAT_NV21, 0 }, +#endif + { V4L2_MBUS_FMT_CUSTOM_YUV420, 12, 12, ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY, 0 }, +#if 0 + { V4L2_MBUS_FMT_CUSTOM_M10MO_RAW, 8, 8, IA_CSS_FRAME_FORMAT_BINARY_8, 0 }, +#endif + /* no valid V4L2 MBUS code for metadata format, so leave it 0. */ + { 0, 0, 0, ATOMISP_INPUT_FORMAT_EMBEDDED, 0 }, + {} +}; + +static const struct { + u32 code; + u32 compressed; +} compressed_codes[] = { + { MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 }, + { MEDIA_BUS_FMT_SGBRG10_1X10, MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 }, + { MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 }, + { MEDIA_BUS_FMT_SRGGB10_1X10, MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 }, +}; + +u32 atomisp_subdev_uncompressed_code(u32 code) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(compressed_codes); i++) + if (code == compressed_codes[i].compressed) + return compressed_codes[i].code; + + return code; +} + +bool atomisp_subdev_is_compressed(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_in_fmt_conv) - 1; i++) + if (code == atomisp_in_fmt_conv[i].code) + return atomisp_in_fmt_conv[i].bpp != + atomisp_in_fmt_conv[i].depth; + + return false; +} + +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_in_fmt_conv) - 1; i++) + if (code == atomisp_in_fmt_conv[i].code) + return atomisp_in_fmt_conv + i; + + return NULL; +} + +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + enum atomisp_input_format atomisp_in_fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_in_fmt_conv) - 1; i++) + if (atomisp_in_fmt_conv[i].atomisp_in_fmt == atomisp_in_fmt) + return atomisp_in_fmt_conv + i; + + return NULL; +} + +bool atomisp_subdev_format_conversion(struct atomisp_sub_device *asd, + unsigned int source_pad) +{ + struct v4l2_mbus_framefmt *sink, *src; + + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + src = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, source_pad); + + return atomisp_is_mbuscode_raw(sink->code) + && !atomisp_is_mbuscode_raw(src->code); +} + +uint16_t atomisp_subdev_source_pad(struct video_device *vdev) +{ + struct media_link *link; + u16 ret = 0; + + list_for_each_entry(link, &vdev->entity.links, list) { + if (link->source) { + ret = link->source->index; + break; + } + } + return ret; +} + +/* + * V4L2 subdev operations + */ + +/* + * isp_subdev_ioctl - CCDC module private ioctl's + * @sd: ISP V4L2 subdevice + * @cmd: ioctl command + * @arg: ioctl argument + * + * Return 0 on success or a negative error code otherwise. + */ +static long isp_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + return 0; +} + +/* + * isp_subdev_set_power - Power on/off the CCDC module + * @sd: ISP V4L2 subdevice + * @on: power on/off + * + * Return 0 on success or a negative error code otherwise. + */ +static int isp_subdev_set_power(struct v4l2_subdev *sd, int on) +{ + return 0; +} + +static int isp_subdev_subscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = isp_sd->isp; + + if (sub->type != V4L2_EVENT_FRAME_SYNC && + sub->type != V4L2_EVENT_FRAME_END && + sub->type != V4L2_EVENT_ATOMISP_3A_STATS_READY && + sub->type != V4L2_EVENT_ATOMISP_METADATA_READY && + sub->type != V4L2_EVENT_ATOMISP_PAUSE_BUFFER && + sub->type != V4L2_EVENT_ATOMISP_CSS_RESET && + sub->type != V4L2_EVENT_ATOMISP_RAW_BUFFERS_ALLOC_DONE && + sub->type != V4L2_EVENT_ATOMISP_ACC_COMPLETE) + return -EINVAL; + + if (sub->type == V4L2_EVENT_FRAME_SYNC && + !atomisp_css_valid_sof(isp)) + return -EINVAL; + + return v4l2_event_subscribe(fh, sub, 16, NULL); +} + +static int isp_subdev_unsubscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +/* + * isp_subdev_enum_mbus_code - Handle pixel format enumeration + * @sd: pointer to v4l2 subdev structure + * @fh : V4L2 subdev file handle + * @code: pointer to v4l2_subdev_pad_mbus_code_enum structure + * return -EINVAL or zero on success + */ +static int isp_subdev_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= ARRAY_SIZE(atomisp_in_fmt_conv) - 1) + return -EINVAL; + + code->code = atomisp_in_fmt_conv[code->index].code; + + return 0; +} + +static int isp_subdev_validate_rect(struct v4l2_subdev *sd, uint32_t pad, + uint32_t target) +{ + switch (pad) { + case ATOMISP_SUBDEV_PAD_SINK: + switch (target) { + case V4L2_SEL_TGT_CROP: + return 0; + } + break; + default: + switch (target) { + case V4L2_SEL_TGT_COMPOSE: + return 0; + } + break; + } + + return -EINVAL; +} + +struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + u32 which, uint32_t pad, + uint32_t target) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + + if (which == V4L2_SUBDEV_FORMAT_TRY) { + switch (target) { + case V4L2_SEL_TGT_CROP: + return v4l2_subdev_get_try_crop(sd, sd_state, pad); + case V4L2_SEL_TGT_COMPOSE: + return v4l2_subdev_get_try_compose(sd, sd_state, pad); + } + } + + switch (target) { + case V4L2_SEL_TGT_CROP: + return &isp_sd->fmt[pad].crop; + case V4L2_SEL_TGT_COMPOSE: + return &isp_sd->fmt[pad].compose; + } + + return NULL; +} + +struct v4l2_mbus_framefmt +*atomisp_subdev_get_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, uint32_t which, + uint32_t pad) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + + if (which == V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_get_try_format(sd, sd_state, pad); + + return &isp_sd->fmt[pad].fmt; +} + +static void isp_get_fmt_rect(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + uint32_t which, + struct v4l2_mbus_framefmt **ffmt, + struct v4l2_rect *crop[ATOMISP_SUBDEV_PADS_NUM], + struct v4l2_rect *comp[ATOMISP_SUBDEV_PADS_NUM]) +{ + unsigned int i; + + for (i = 0; i < ATOMISP_SUBDEV_PADS_NUM; i++) { + ffmt[i] = atomisp_subdev_get_ffmt(sd, sd_state, which, i); + crop[i] = atomisp_subdev_get_rect(sd, sd_state, which, i, + V4L2_SEL_TGT_CROP); + comp[i] = atomisp_subdev_get_rect(sd, sd_state, which, i, + V4L2_SEL_TGT_COMPOSE); + } +} + +static void isp_subdev_propagate(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + u32 which, uint32_t pad, uint32_t target, + uint32_t flags) +{ + struct v4l2_mbus_framefmt *ffmt[ATOMISP_SUBDEV_PADS_NUM]; + struct v4l2_rect *crop[ATOMISP_SUBDEV_PADS_NUM], + *comp[ATOMISP_SUBDEV_PADS_NUM]; + + if (flags & V4L2_SEL_FLAG_KEEP_CONFIG) + return; + + isp_get_fmt_rect(sd, sd_state, which, ffmt, crop, comp); + + switch (pad) { + case ATOMISP_SUBDEV_PAD_SINK: { + struct v4l2_rect r = {0}; + + /* Only crop target supported on sink pad. */ + r.width = ffmt[pad]->width; + r.height = ffmt[pad]->height; + + atomisp_subdev_set_selection(sd, sd_state, which, pad, + target, flags, &r); + break; + } + } +} + +static int isp_subdev_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + struct v4l2_rect *rec; + int rval = isp_subdev_validate_rect(sd, sel->pad, sel->target); + + if (rval) + return rval; + + rec = atomisp_subdev_get_rect(sd, sd_state, sel->which, sel->pad, + sel->target); + if (!rec) + return -EINVAL; + + sel->r = *rec; + return 0; +} + +static const char *atomisp_pad_str(unsigned int pad) +{ + static const char *const pad_str[] = { + "ATOMISP_SUBDEV_PAD_SINK", + "ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE", + "ATOMISP_SUBDEV_PAD_SOURCE_VF", + "ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW", + "ATOMISP_SUBDEV_PAD_SOURCE_VIDEO", + }; + + if (pad >= ARRAY_SIZE(pad_str)) + return "ATOMISP_INVALID_PAD"; + return pad_str[pad]; +} + +int atomisp_subdev_set_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + u32 which, uint32_t pad, uint32_t target, + u32 flags, struct v4l2_rect *r) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = isp_sd->isp; + struct v4l2_mbus_framefmt *ffmt[ATOMISP_SUBDEV_PADS_NUM]; + struct v4l2_rect *crop[ATOMISP_SUBDEV_PADS_NUM], + *comp[ATOMISP_SUBDEV_PADS_NUM]; + unsigned int i; + unsigned int padding_w = pad_w; + unsigned int padding_h = pad_h; + + isp_get_fmt_rect(sd, sd_state, which, ffmt, crop, comp); + + dev_dbg(isp->dev, + "sel: pad %s tgt %s l %d t %d w %d h %d which %s f 0x%8.8x\n", + atomisp_pad_str(pad), target == V4L2_SEL_TGT_CROP + ? "V4L2_SEL_TGT_CROP" : "V4L2_SEL_TGT_COMPOSE", + r->left, r->top, r->width, r->height, + which == V4L2_SUBDEV_FORMAT_TRY ? "V4L2_SUBDEV_FORMAT_TRY" + : "V4L2_SUBDEV_FORMAT_ACTIVE", flags); + + r->width = rounddown(r->width, ATOM_ISP_STEP_WIDTH); + r->height = rounddown(r->height, ATOM_ISP_STEP_HEIGHT); + + switch (pad) { + case ATOMISP_SUBDEV_PAD_SINK: { + /* Only crop target supported on sink pad. */ + unsigned int dvs_w, dvs_h; + + crop[pad]->width = ffmt[pad]->width; + crop[pad]->height = ffmt[pad]->height; + + /* Workaround for BYT 1080p perfectshot since the maxinum resolution of + * front camera ov2722 is 1932x1092 and cannot use pad_w > 12*/ + if (!strncmp(isp->inputs[isp_sd->input_curr].camera->name, + "ov2722", 6) && crop[pad]->height == 1092) { + padding_w = 12; + padding_h = 12; + } + + if (isp->inputs[isp_sd->input_curr].type == SOC_CAMERA) { + padding_w = 0; + padding_h = 0; + } + + if (atomisp_subdev_format_conversion(isp_sd, + isp_sd->capture_pad) + && crop[pad]->width && crop[pad]->height) { + crop[pad]->width -= padding_w; + crop[pad]->height -= padding_h; + } + + /* if subdev type is SOC camera,we do not need to set DVS */ + if (isp->inputs[isp_sd->input_curr].type == SOC_CAMERA) + isp_sd->params.video_dis_en = 0; + + if (isp_sd->params.video_dis_en && + isp_sd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + !isp_sd->continuous_mode->val) { + /* This resolution contains 20 % of DVS slack + * (of the desired captured image before + * scaling, or 1 / 6 of what we get from the + * sensor) in both width and height. Remove + * it. */ + crop[pad]->width = roundup(crop[pad]->width * 5 / 6, + ATOM_ISP_STEP_WIDTH); + crop[pad]->height = roundup(crop[pad]->height * 5 / 6, + ATOM_ISP_STEP_HEIGHT); + } + + crop[pad]->width = min(crop[pad]->width, r->width); + crop[pad]->height = min(crop[pad]->height, r->height); + + if (!(flags & V4L2_SEL_FLAG_KEEP_CONFIG)) { + for (i = ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE; + i < ATOMISP_SUBDEV_PADS_NUM; i++) { + struct v4l2_rect tmp = *crop[pad]; + + atomisp_subdev_set_selection( + sd, sd_state, which, i, + V4L2_SEL_TGT_COMPOSE, + flags, &tmp); + } + } + + if (which == V4L2_SUBDEV_FORMAT_TRY) + break; + + if (isp_sd->params.video_dis_en && + isp_sd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + !isp_sd->continuous_mode->val) { + dvs_w = rounddown(crop[pad]->width / 5, + ATOM_ISP_STEP_WIDTH); + dvs_h = rounddown(crop[pad]->height / 5, + ATOM_ISP_STEP_HEIGHT); + } else if (!isp_sd->params.video_dis_en && + isp_sd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + /* + * For CSS2.0, digital zoom needs to set dvs envelope to 12 + * when dvs is disabled. + */ + dvs_w = dvs_h = 12; + } else { + dvs_w = dvs_h = 0; + } + atomisp_css_video_set_dis_envelope(isp_sd, dvs_w, dvs_h); + atomisp_css_input_set_effective_resolution(isp_sd, + ATOMISP_INPUT_STREAM_GENERAL, + crop[pad]->width, + crop[pad]->height); + break; + } + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: { + /* Only compose target is supported on source pads. */ + + if (isp_sd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + /* Scaling is disabled in this mode */ + r->width = crop[ATOMISP_SUBDEV_PAD_SINK]->width; + r->height = crop[ATOMISP_SUBDEV_PAD_SINK]->height; + } + + if (crop[ATOMISP_SUBDEV_PAD_SINK]->width == r->width + && crop[ATOMISP_SUBDEV_PAD_SINK]->height == r->height) + isp_sd->params.yuv_ds_en = false; + else + isp_sd->params.yuv_ds_en = true; + + comp[pad]->width = r->width; + comp[pad]->height = r->height; + + if (r->width == 0 || r->height == 0 || + crop[ATOMISP_SUBDEV_PAD_SINK]->width == 0 || + crop[ATOMISP_SUBDEV_PAD_SINK]->height == 0) + break; + /* + * do cropping on sensor input if ratio of required resolution + * is different with sensor output resolution ratio: + * + * ratio = width / height + * + * if ratio_output < ratio_sensor: + * effect_width = sensor_height * out_width / out_height; + * effect_height = sensor_height; + * else + * effect_width = sensor_width; + * effect_height = sensor_width * out_height / out_width; + * + */ + if (r->width * crop[ATOMISP_SUBDEV_PAD_SINK]->height < + crop[ATOMISP_SUBDEV_PAD_SINK]->width * r->height) + atomisp_css_input_set_effective_resolution(isp_sd, + ATOMISP_INPUT_STREAM_GENERAL, + rounddown(crop[ATOMISP_SUBDEV_PAD_SINK]-> + height * r->width / r->height, + ATOM_ISP_STEP_WIDTH), + crop[ATOMISP_SUBDEV_PAD_SINK]->height); + else + atomisp_css_input_set_effective_resolution(isp_sd, + ATOMISP_INPUT_STREAM_GENERAL, + crop[ATOMISP_SUBDEV_PAD_SINK]->width, + rounddown(crop[ATOMISP_SUBDEV_PAD_SINK]-> + width * r->height / r->width, + ATOM_ISP_STEP_WIDTH)); + + break; + } + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + comp[pad]->width = r->width; + comp[pad]->height = r->height; + break; + default: + return -EINVAL; + } + + /* Set format dimensions on non-sink pads as well. */ + if (pad != ATOMISP_SUBDEV_PAD_SINK) { + ffmt[pad]->width = comp[pad]->width; + ffmt[pad]->height = comp[pad]->height; + } + + if (!atomisp_subdev_get_rect(sd, sd_state, which, pad, target)) + return -EINVAL; + *r = *atomisp_subdev_get_rect(sd, sd_state, which, pad, target); + + dev_dbg(isp->dev, "sel actual: l %d t %d w %d h %d\n", + r->left, r->top, r->width, r->height); + + return 0; +} + +static int isp_subdev_set_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + int rval = isp_subdev_validate_rect(sd, sel->pad, sel->target); + + if (rval) + return rval; + + return atomisp_subdev_set_selection(sd, sd_state, sel->which, + sel->pad, + sel->target, sel->flags, &sel->r); +} + +static int atomisp_get_sensor_bin_factor(struct atomisp_sub_device *asd) +{ + struct v4l2_control ctrl = {0}; + struct atomisp_device *isp = asd->isp; + int hbin, vbin; + int ret; + + if (isp->inputs[asd->input_curr].type == FILE_INPUT || + isp->inputs[asd->input_curr].type == TEST_PATTERN) + return 0; + + ctrl.id = V4L2_CID_BIN_FACTOR_HORZ; + ret = + v4l2_g_ctrl(isp->inputs[asd->input_curr].camera->ctrl_handler, + &ctrl); + hbin = ctrl.value; + ctrl.id = V4L2_CID_BIN_FACTOR_VERT; + ret |= + v4l2_g_ctrl(isp->inputs[asd->input_curr].camera->ctrl_handler, + &ctrl); + vbin = ctrl.value; + + /* + * ISP needs to know binning factor from sensor. + * In case horizontal and vertical sensor's binning factors + * are different or sensor does not support binning factor CID, + * ISP will apply default 0 value. + */ + if (ret || hbin != vbin) + hbin = 0; + + return hbin; +} + +void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + uint32_t which, + u32 pad, struct v4l2_mbus_framefmt *ffmt) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = isp_sd->isp; + struct v4l2_mbus_framefmt *__ffmt = + atomisp_subdev_get_ffmt(sd, sd_state, which, pad); + + dev_dbg(isp->dev, "ffmt: pad %s w %d h %d code 0x%8.8x which %s\n", + atomisp_pad_str(pad), ffmt->width, ffmt->height, ffmt->code, + which == V4L2_SUBDEV_FORMAT_TRY ? "V4L2_SUBDEV_FORMAT_TRY" + : "V4L2_SUBDEV_FORMAT_ACTIVE"); + + switch (pad) { + case ATOMISP_SUBDEV_PAD_SINK: { + const struct atomisp_in_fmt_conv *fc = + atomisp_find_in_fmt_conv(ffmt->code); + + if (!fc) { + fc = atomisp_in_fmt_conv; + ffmt->code = fc->code; + dev_dbg(isp->dev, "using 0x%8.8x instead\n", + ffmt->code); + } + + *__ffmt = *ffmt; + + isp_subdev_propagate(sd, sd_state, which, pad, + V4L2_SEL_TGT_CROP, 0); + + if (which == V4L2_SUBDEV_FORMAT_ACTIVE) { + atomisp_css_input_set_resolution(isp_sd, + ATOMISP_INPUT_STREAM_GENERAL, ffmt); + atomisp_css_input_set_binning_factor(isp_sd, + ATOMISP_INPUT_STREAM_GENERAL, + atomisp_get_sensor_bin_factor(isp_sd)); + atomisp_css_input_set_bayer_order(isp_sd, ATOMISP_INPUT_STREAM_GENERAL, + fc->bayer_order); + atomisp_css_input_set_format(isp_sd, ATOMISP_INPUT_STREAM_GENERAL, + fc->atomisp_in_fmt); + atomisp_css_set_default_isys_config(isp_sd, ATOMISP_INPUT_STREAM_GENERAL, + ffmt); + } + + break; + } + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: + __ffmt->code = ffmt->code; + break; + } +} + +/* + * isp_subdev_get_format - Retrieve the video format on a pad + * @sd : ISP V4L2 subdevice + * @fh : V4L2 subdev file handle + * @pad: Pad number + * @fmt: Format + * + * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond + * to the format type. + */ +static int isp_subdev_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + fmt->format = *atomisp_subdev_get_ffmt(sd, sd_state, fmt->which, + fmt->pad); + + return 0; +} + +/* + * isp_subdev_set_format - Set the video format on a pad + * @sd : ISP subdev V4L2 subdevice + * @fh : V4L2 subdev file handle + * @pad: Pad number + * @fmt: Format + * + * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond + * to the format type. + */ +static int isp_subdev_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + atomisp_subdev_set_ffmt(sd, sd_state, fmt->which, fmt->pad, + &fmt->format); + + return 0; +} + +/* V4L2 subdev core operations */ +static const struct v4l2_subdev_core_ops isp_subdev_v4l2_core_ops = { + .ioctl = isp_subdev_ioctl, .s_power = isp_subdev_set_power, + .subscribe_event = isp_subdev_subscribe_event, + .unsubscribe_event = isp_subdev_unsubscribe_event, +}; + +/* V4L2 subdev pad operations */ +static const struct v4l2_subdev_pad_ops isp_subdev_v4l2_pad_ops = { + .enum_mbus_code = isp_subdev_enum_mbus_code, + .get_fmt = isp_subdev_get_format, + .set_fmt = isp_subdev_set_format, + .get_selection = isp_subdev_get_selection, + .set_selection = isp_subdev_set_selection, + .link_validate = v4l2_subdev_link_validate_default, +}; + +/* V4L2 subdev operations */ +static const struct v4l2_subdev_ops isp_subdev_v4l2_ops = { + .core = &isp_subdev_v4l2_core_ops, + .pad = &isp_subdev_v4l2_pad_ops, +}; + +static void isp_subdev_init_params(struct atomisp_sub_device *asd) +{ + unsigned int i; + + /* parameters initialization */ + INIT_LIST_HEAD(&asd->s3a_stats); + INIT_LIST_HEAD(&asd->s3a_stats_in_css); + INIT_LIST_HEAD(&asd->s3a_stats_ready); + INIT_LIST_HEAD(&asd->dis_stats); + INIT_LIST_HEAD(&asd->dis_stats_in_css); + spin_lock_init(&asd->dis_stats_lock); + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + INIT_LIST_HEAD(&asd->metadata[i]); + INIT_LIST_HEAD(&asd->metadata_in_css[i]); + INIT_LIST_HEAD(&asd->metadata_ready[i]); + } +} + +/* +* isp_subdev_link_setup - Setup isp subdev connections +* @entity: ispsubdev media entity +* @local: Pad at the local end of the link +* @remote: Pad at the remote end of the link +* @flags: Link flags +* +* return -EINVAL or zero on success +*/ +static int isp_subdev_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = isp_sd->isp; + unsigned int i; + + switch (local->index | is_media_entity_v4l2_subdev(remote->entity)) { + case ATOMISP_SUBDEV_PAD_SINK | MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN: + /* Read from the sensor CSI2-ports. */ + if (!(flags & MEDIA_LNK_FL_ENABLED)) { + isp_sd->input = ATOMISP_SUBDEV_INPUT_NONE; + break; + } + + if (isp_sd->input != ATOMISP_SUBDEV_INPUT_NONE) + return -EBUSY; + + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { + if (remote->entity != &isp->csi2_port[i].subdev.entity) + continue; + + isp_sd->input = ATOMISP_SUBDEV_INPUT_CSI2_PORT1 + i; + return 0; + } + + return -EINVAL; + + case ATOMISP_SUBDEV_PAD_SINK | MEDIA_ENT_F_OLD_BASE: + /* read from memory */ + if (flags & MEDIA_LNK_FL_ENABLED) { + if (isp_sd->input >= ATOMISP_SUBDEV_INPUT_CSI2_PORT1 && + isp_sd->input < (ATOMISP_SUBDEV_INPUT_CSI2_PORT1 + + ATOMISP_CAMERA_NR_PORTS)) + return -EBUSY; + isp_sd->input = ATOMISP_SUBDEV_INPUT_MEMORY; + } else { + if (isp_sd->input == ATOMISP_SUBDEV_INPUT_MEMORY) + isp_sd->input = ATOMISP_SUBDEV_INPUT_NONE; + } + break; + + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW | MEDIA_ENT_F_OLD_BASE: + /* always write to memory */ + break; + + case ATOMISP_SUBDEV_PAD_SOURCE_VF | MEDIA_ENT_F_OLD_BASE: + /* always write to memory */ + break; + + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE | MEDIA_ENT_F_OLD_BASE: + /* always write to memory */ + break; + + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO | MEDIA_ENT_F_OLD_BASE: + /* always write to memory */ + break; + + default: + return -EINVAL; + } + + return 0; +} + +/* media operations */ +static const struct media_entity_operations isp_subdev_media_ops = { + .link_setup = isp_subdev_link_setup, + .link_validate = v4l2_subdev_link_validate, + /* .set_power = v4l2_subdev_set_power, */ +}; + +static int __atomisp_update_run_mode(struct atomisp_sub_device *asd) +{ + struct atomisp_device *isp = asd->isp; + struct v4l2_ctrl *ctrl = asd->run_mode; + struct v4l2_ctrl *c; + s32 mode; + + if (ctrl->val != ATOMISP_RUN_MODE_VIDEO && + asd->continuous_mode->val) + mode = ATOMISP_RUN_MODE_PREVIEW; + else + mode = ctrl->val; + + c = v4l2_ctrl_find( + isp->inputs[asd->input_curr].camera->ctrl_handler, + V4L2_CID_RUN_MODE); + + if (c) + return v4l2_ctrl_s_ctrl(c, mode); + + return 0; +} + +int atomisp_update_run_mode(struct atomisp_sub_device *asd) +{ + int rval; + + mutex_lock(asd->ctrl_handler.lock); + rval = __atomisp_update_run_mode(asd); + mutex_unlock(asd->ctrl_handler.lock); + + return rval; +} + +static int s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct atomisp_sub_device *asd = container_of( + ctrl->handler, struct atomisp_sub_device, ctrl_handler); + unsigned int streaming; + unsigned long flags; + + switch (ctrl->id) { + case V4L2_CID_RUN_MODE: + return __atomisp_update_run_mode(asd); + case V4L2_CID_DEPTH_MODE: + /* Use spinlock instead of mutex to avoid possible locking issues */ + spin_lock_irqsave(&asd->isp->lock, flags); + streaming = asd->streaming; + spin_unlock_irqrestore(&asd->isp->lock, flags); + if (streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { + dev_err(asd->isp->dev, + "ISP is streaming, it is not supported to change the depth mode\n"); + return -EINVAL; + } + break; + } + + return 0; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = &s_ctrl, +}; + +static const struct v4l2_ctrl_config ctrl_fmt_auto = { + .ops = &ctrl_ops, + .id = V4L2_CID_FMT_AUTO, + .name = "Automatic format guessing", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .min = 0, + .max = 1, + .step = 1, + .def = 1, +}; + +static const char *const ctrl_run_mode_menu[] = { + NULL, + "Video", + "Still capture", + "Continuous capture", + "Preview", +}; + +static const struct v4l2_ctrl_config ctrl_run_mode = { + .ops = &ctrl_ops, + .id = V4L2_CID_RUN_MODE, + .name = "Atomisp run mode", + .type = V4L2_CTRL_TYPE_MENU, + .min = 1, + .def = 1, + .max = 4, + .qmenu = ctrl_run_mode_menu, +}; + +static const char *const ctrl_vfpp_mode_menu[] = { + "Enable", /* vfpp always enabled */ + "Disable to scaler mode", /* CSS into video mode and disable */ + "Disable to low latency mode", /* CSS into still mode and disable */ +}; + +static const struct v4l2_ctrl_config ctrl_vfpp = { + .id = V4L2_CID_VFPP, + .name = "Atomisp vf postprocess", + .type = V4L2_CTRL_TYPE_MENU, + .min = 0, + .def = 0, + .max = 2, + .qmenu = ctrl_vfpp_mode_menu, +}; + +/* + * Control for ISP continuous mode + * + * When enabled, capture processing is possible without + * stopping the preview pipeline. When disabled, ISP needs + * to be restarted between preview and capture. + */ +static const struct v4l2_ctrl_config ctrl_continuous_mode = { + .ops = &ctrl_ops, + .id = V4L2_CID_ATOMISP_CONTINUOUS_MODE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Continuous mode", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +/* + * Control for continuous mode raw buffer size + * + * The size of the RAW ringbuffer sets limit on how much + * back in time application can go when requesting capture + * frames to be rendered, and how many frames can be rendered + * in a burst at full sensor rate. + * + * Note: this setting has a big impact on memory consumption of + * the CSS subsystem. + */ +static const struct v4l2_ctrl_config ctrl_continuous_raw_buffer_size = { + .ops = &ctrl_ops, + .id = V4L2_CID_ATOMISP_CONTINUOUS_RAW_BUFFER_SIZE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Continuous raw ringbuffer size", + .min = 1, + .max = 100, /* depends on CSS version, runtime checked */ + .step = 1, + .def = 3, +}; + +/* + * Control for enabling continuous viewfinder + * + * When enabled, and ISP is in continuous mode (see ctrl_continuous_mode ), + * preview pipeline continues concurrently with capture + * processing. When disabled, and continuous mode is used, + * preview is paused while captures are processed, but + * full pipeline restart is not needed. + * + * By setting this to disabled, capture processing is + * essentially given priority over preview, and the effective + * capture output rate may be higher than with continuous + * viewfinder enabled. + */ +static const struct v4l2_ctrl_config ctrl_continuous_viewfinder = { + .id = V4L2_CID_ATOMISP_CONTINUOUS_VIEWFINDER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Continuous viewfinder", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +/* + * Control for enabling Lock&Unlock Raw Buffer mechanism + * + * When enabled, Raw Buffer can be locked and unlocked. + * Application can hold the exp_id of Raw Buffer + * and unlock it when no longer needed. + * Note: Make sure set this configuration before creating stream. + */ +static const struct v4l2_ctrl_config ctrl_enable_raw_buffer_lock = { + .id = V4L2_CID_ENABLE_RAW_BUFFER_LOCK, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Lock Unlock Raw Buffer", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +/* + * Control to disable digital zoom of the whole stream + * + * When it is true, pipe configuration enable_dz will be set to false. + * This can help get a better performance by disabling pp binary. + * + * Note: Make sure set this configuration before creating stream. + */ +static const struct v4l2_ctrl_config ctrl_disable_dz = { + .id = V4L2_CID_DISABLE_DZ, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Disable digital zoom", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +/* + * Control for ISP depth mode + * + * When enabled, that means ISP will deal with dual streams and sensors will be + * in slave/master mode. + * slave sensor will have no output until master sensor is streamed on. + */ +static const struct v4l2_ctrl_config ctrl_depth_mode = { + .ops = &ctrl_ops, + .id = V4L2_CID_DEPTH_MODE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Depth mode", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +static void atomisp_init_subdev_pipe(struct atomisp_sub_device *asd, + struct atomisp_video_pipe *pipe, enum v4l2_buf_type buf_type) +{ + pipe->type = buf_type; + pipe->asd = asd; + pipe->isp = asd->isp; + spin_lock_init(&pipe->irq_lock); + mutex_init(&pipe->vb_queue_mutex); + INIT_LIST_HEAD(&pipe->buffers_in_css); + INIT_LIST_HEAD(&pipe->activeq); + INIT_LIST_HEAD(&pipe->buffers_waiting_for_param); + INIT_LIST_HEAD(&pipe->per_frame_params); + memset(pipe->frame_request_config_id, + 0, VIDEO_MAX_FRAME * sizeof(unsigned int)); + memset(pipe->frame_params, + 0, VIDEO_MAX_FRAME * + sizeof(struct atomisp_css_params_with_list *)); +} + +/* + * isp_subdev_init_entities - Initialize V4L2 subdev and media entity + * @asd: ISP CCDC module + * + * Return 0 on success and a negative error code on failure. + */ +static int isp_subdev_init_entities(struct atomisp_sub_device *asd) +{ + struct v4l2_subdev *sd = &asd->subdev; + struct media_pad *pads = asd->pads; + struct media_entity *me = &sd->entity; + int ret; + + asd->input = ATOMISP_SUBDEV_INPUT_NONE; + + v4l2_subdev_init(sd, &isp_subdev_v4l2_ops); + sprintf(sd->name, "ATOMISP_SUBDEV_%d", asd->index); + v4l2_set_subdevdata(sd, asd); + sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE; + + pads[ATOMISP_SUBDEV_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + pads[ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW].flags = MEDIA_PAD_FL_SOURCE; + pads[ATOMISP_SUBDEV_PAD_SOURCE_VF].flags = MEDIA_PAD_FL_SOURCE; + pads[ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE].flags = MEDIA_PAD_FL_SOURCE; + pads[ATOMISP_SUBDEV_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE; + + asd->fmt[ATOMISP_SUBDEV_PAD_SINK].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + asd->fmt[ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + asd->fmt[ATOMISP_SUBDEV_PAD_SOURCE_VF].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + asd->fmt[ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + asd->fmt[ATOMISP_SUBDEV_PAD_SOURCE_VIDEO].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + + me->ops = &isp_subdev_media_ops; + me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; + ret = media_entity_pads_init(me, ATOMISP_SUBDEV_PADS_NUM, pads); + if (ret < 0) + return ret; + + atomisp_init_subdev_pipe(asd, &asd->video_out_preview, + V4L2_BUF_TYPE_VIDEO_CAPTURE); + + atomisp_init_subdev_pipe(asd, &asd->video_out_vf, + V4L2_BUF_TYPE_VIDEO_CAPTURE); + + atomisp_init_subdev_pipe(asd, &asd->video_out_capture, + V4L2_BUF_TYPE_VIDEO_CAPTURE); + + atomisp_init_subdev_pipe(asd, &asd->video_out_video_capture, + V4L2_BUF_TYPE_VIDEO_CAPTURE); + + ret = atomisp_video_init(&asd->video_out_capture, "CAPTURE", + ATOMISP_RUN_MODE_STILL_CAPTURE); + if (ret < 0) + return ret; + + ret = atomisp_video_init(&asd->video_out_vf, "VIEWFINDER", + ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE); + if (ret < 0) + return ret; + + ret = atomisp_video_init(&asd->video_out_preview, "PREVIEW", + ATOMISP_RUN_MODE_PREVIEW); + if (ret < 0) + return ret; + + ret = atomisp_video_init(&asd->video_out_video_capture, "VIDEO", + ATOMISP_RUN_MODE_VIDEO); + if (ret < 0) + return ret; + + ret = v4l2_ctrl_handler_init(&asd->ctrl_handler, 1); + if (ret) + return ret; + + asd->fmt_auto = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_fmt_auto, NULL); + asd->run_mode = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_run_mode, NULL); + asd->vfpp = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_vfpp, NULL); + asd->continuous_mode = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_continuous_mode, NULL); + asd->continuous_viewfinder = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_continuous_viewfinder, + NULL); + asd->continuous_raw_buffer_size = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_continuous_raw_buffer_size, + NULL); + + asd->enable_raw_buffer_lock = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_enable_raw_buffer_lock, + NULL); + asd->depth_mode = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_depth_mode, + NULL); + asd->disable_dz = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_disable_dz, + NULL); + + /* Make controls visible on subdev as well. */ + asd->subdev.ctrl_handler = &asd->ctrl_handler; + spin_lock_init(&asd->raw_buffer_bitmap_lock); + return asd->ctrl_handler.error; +} + +int atomisp_create_pads_links(struct atomisp_device *isp) +{ + struct atomisp_sub_device *asd; + int i, j, ret = 0; + + isp->num_of_streams = 2; + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { + for (j = 0; j < isp->num_of_streams; j++) { + ret = + media_create_pad_link(&isp->csi2_port[i].subdev. + entity, CSI2_PAD_SOURCE, + &isp->asd[j].subdev.entity, + ATOMISP_SUBDEV_PAD_SINK, 0); + if (ret < 0) + return ret; + } + } + for (i = 0; i < isp->input_cnt; i++) { + /* Don't create links for the test-pattern-generator */ + if (isp->inputs[i].type == TEST_PATTERN) + continue; + + ret = media_create_pad_link(&isp->inputs[i].camera->entity, 0, + &isp->csi2_port[isp->inputs[i]. + port].subdev.entity, + CSI2_PAD_SINK, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); + if (ret < 0) + return ret; + } + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + ret = media_create_pad_link(&asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW, + &asd->video_out_preview.vdev.entity, + 0, 0); + if (ret < 0) + return ret; + ret = media_create_pad_link(&asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SOURCE_VF, + &asd->video_out_vf.vdev.entity, 0, + 0); + if (ret < 0) + return ret; + ret = media_create_pad_link(&asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE, + &asd->video_out_capture.vdev.entity, + 0, 0); + if (ret < 0) + return ret; + ret = media_create_pad_link(&asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SOURCE_VIDEO, + &asd->video_out_video_capture.vdev. + entity, 0, 0); + if (ret < 0) + return ret; + } + return 0; +} + +static void atomisp_subdev_cleanup_entities(struct atomisp_sub_device *asd) +{ + v4l2_ctrl_handler_free(&asd->ctrl_handler); + + media_entity_cleanup(&asd->subdev.entity); +} + +void atomisp_subdev_cleanup_pending_events(struct atomisp_sub_device *asd) +{ + struct v4l2_fh *fh, *fh_tmp; + struct v4l2_event event; + unsigned int i, pending_event; + + list_for_each_entry_safe(fh, fh_tmp, + &asd->subdev.devnode->fh_list, list) { + pending_event = v4l2_event_pending(fh); + for (i = 0; i < pending_event; i++) + v4l2_event_dequeue(fh, &event, 1); + } +} + +void atomisp_subdev_unregister_entities(struct atomisp_sub_device *asd) +{ + atomisp_subdev_cleanup_entities(asd); + v4l2_device_unregister_subdev(&asd->subdev); + atomisp_video_unregister(&asd->video_out_preview); + atomisp_video_unregister(&asd->video_out_vf); + atomisp_video_unregister(&asd->video_out_capture); + atomisp_video_unregister(&asd->video_out_video_capture); +} + +int atomisp_subdev_register_subdev(struct atomisp_sub_device *asd, + struct v4l2_device *vdev) +{ + return v4l2_device_register_subdev(vdev, &asd->subdev); +} + +int atomisp_subdev_register_video_nodes(struct atomisp_sub_device *asd, + struct v4l2_device *vdev) +{ + int ret; + + /* + * FIXME: check if all device caps are properly initialized. + * Should any of those use V4L2_CAP_META_CAPTURE? Probably yes. + */ + + asd->video_out_preview.vdev.v4l2_dev = vdev; + asd->video_out_preview.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + ret = video_register_device(&asd->video_out_preview.vdev, + VFL_TYPE_VIDEO, -1); + if (ret < 0) + goto error; + + asd->video_out_capture.vdev.v4l2_dev = vdev; + asd->video_out_capture.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + ret = video_register_device(&asd->video_out_capture.vdev, + VFL_TYPE_VIDEO, -1); + if (ret < 0) + goto error; + + asd->video_out_vf.vdev.v4l2_dev = vdev; + asd->video_out_vf.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + ret = video_register_device(&asd->video_out_vf.vdev, + VFL_TYPE_VIDEO, -1); + if (ret < 0) + goto error; + + asd->video_out_video_capture.vdev.v4l2_dev = vdev; + asd->video_out_video_capture.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + ret = video_register_device(&asd->video_out_video_capture.vdev, + VFL_TYPE_VIDEO, -1); + if (ret < 0) + goto error; + + return 0; + +error: + atomisp_subdev_unregister_entities(asd); + return ret; +} + +/* + * atomisp_subdev_init - ISP Subdevice initialization. + * @dev: Device pointer specific to the ATOM ISP. + * + * TODO: Get the initialisation values from platform data. + * + * Return 0 on success or a negative error code otherwise. + */ +int atomisp_subdev_init(struct atomisp_device *isp) +{ + struct atomisp_sub_device *asd; + int i, ret = 0; + + /* + * CSS2.0 running ISP2400 support + * multiple streams + */ + isp->num_of_streams = 2; + isp->asd = devm_kzalloc(isp->dev, sizeof(struct atomisp_sub_device) * + isp->num_of_streams, GFP_KERNEL); + if (!isp->asd) + return -ENOMEM; + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + asd->isp = isp; + isp_subdev_init_params(asd); + asd->index = i; + ret = isp_subdev_init_entities(asd); + if (ret < 0) { + atomisp_subdev_cleanup_entities(asd); + break; + } + } + + return ret; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp_subdev.h b/drivers/staging/media/atomisp/pci/atomisp_subdev.h new file mode 100644 index 000000000..bd2872cbb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_subdev.h @@ -0,0 +1,426 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef __ATOMISP_SUBDEV_H__ +#define __ATOMISP_SUBDEV_H__ + +#include +#include +#include +#include +#include "atomisp_common.h" +#include "atomisp_compat.h" +#include "atomisp_v4l2.h" + +#include "ia_css.h" + +/* EXP_ID's ranger is 1 ~ 250 */ +#define ATOMISP_MAX_EXP_ID (250) +enum atomisp_subdev_input_entity { + ATOMISP_SUBDEV_INPUT_NONE, + ATOMISP_SUBDEV_INPUT_MEMORY, + ATOMISP_SUBDEV_INPUT_CSI2, + /* + * The following enum for CSI2 port must go together in one row. + * Otherwise it breaks the code logic. + */ + ATOMISP_SUBDEV_INPUT_CSI2_PORT1, + ATOMISP_SUBDEV_INPUT_CSI2_PORT2, + ATOMISP_SUBDEV_INPUT_CSI2_PORT3, +}; + +#define ATOMISP_SUBDEV_PAD_SINK 0 +/* capture output for still frames */ +#define ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE 1 +/* viewfinder output for downscaled capture output */ +#define ATOMISP_SUBDEV_PAD_SOURCE_VF 2 +/* preview output for display */ +#define ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW 3 +/* main output for video pipeline */ +#define ATOMISP_SUBDEV_PAD_SOURCE_VIDEO 4 +#define ATOMISP_SUBDEV_PADS_NUM 5 + +struct atomisp_in_fmt_conv { + u32 code; + u8 bpp; /* bits per pixel */ + u8 depth; /* uncompressed */ + enum atomisp_input_format atomisp_in_fmt; + enum ia_css_bayer_order bayer_order; +}; + +struct atomisp_sub_device; + +struct atomisp_video_pipe { + struct video_device vdev; + enum v4l2_buf_type type; + struct media_pad pad; + struct vb2_queue vb_queue; + /* Lock for vb_queue, when also taking isp->mutex this must be taken first! */ + struct mutex vb_queue_mutex; + /* List of video-buffers handed over to the CSS */ + struct list_head buffers_in_css; + /* List of video-buffers handed over to the driver, but not yet to the CSS */ + struct list_head activeq; + /* + * the buffers waiting for per-frame parameters, this is only valid + * in per-frame setting mode. + */ + struct list_head buffers_waiting_for_param; + /* the link list to store per_frame parameters */ + struct list_head per_frame_params; + + /* Filled through atomisp_get_css_frame_info() on queue setup */ + struct ia_css_frame_info frame_info; + + /* Store here the initial run mode */ + unsigned int default_run_mode; + /* Set from streamoff to disallow queuing further buffers in CSS */ + bool stopping; + + /* + * irq_lock is used to protect video buffer state change operations and + * also to make activeq and capq operations atomic. + */ + spinlock_t irq_lock; + unsigned int users; + + struct atomisp_device *isp; + struct v4l2_pix_format pix; + u32 sh_fmt; + + struct atomisp_sub_device *asd; + + /* + * This frame_config_id is got from CSS when dequueues buffers from CSS, + * it is used to indicate which parameter it has applied. + */ + unsigned int frame_config_id[VIDEO_MAX_FRAME]; + /* + * This config id is set when camera HAL enqueues buffer, it has a + * non-zero value to indicate which parameter it needs to applu + */ + unsigned int frame_request_config_id[VIDEO_MAX_FRAME]; + struct atomisp_css_params_with_list *frame_params[VIDEO_MAX_FRAME]; +}; + +#define vq_to_pipe(queue) \ + container_of(queue, struct atomisp_video_pipe, vb_queue) + +#define vb_to_pipe(vb) vq_to_pipe((vb)->vb2_queue) + +struct atomisp_pad_format { + struct v4l2_mbus_framefmt fmt; + struct v4l2_rect crop; + struct v4l2_rect compose; +}; + +/* Internal states for flash process */ +enum atomisp_flash_state { + ATOMISP_FLASH_IDLE, + ATOMISP_FLASH_REQUESTED, + ATOMISP_FLASH_ONGOING, + ATOMISP_FLASH_DONE +}; + +/* + * This structure is used to cache the CSS parameters, it aligns to + * struct ia_css_isp_config but without un-supported and deprecated parts. + */ +struct atomisp_css_params { + struct ia_css_wb_config wb_config; + struct ia_css_cc_config cc_config; + struct ia_css_tnr_config tnr_config; + struct ia_css_ecd_config ecd_config; + struct ia_css_ynr_config ynr_config; + struct ia_css_fc_config fc_config; + struct ia_css_formats_config formats_config; + struct ia_css_cnr_config cnr_config; + struct ia_css_macc_config macc_config; + struct ia_css_ctc_config ctc_config; + struct ia_css_aa_config aa_config; + struct ia_css_aa_config baa_config; + struct ia_css_ce_config ce_config; + struct ia_css_ob_config ob_config; + struct ia_css_dp_config dp_config; + struct ia_css_de_config de_config; + struct ia_css_gc_config gc_config; + struct ia_css_nr_config nr_config; + struct ia_css_ee_config ee_config; + struct ia_css_anr_config anr_config; + struct ia_css_3a_config s3a_config; + struct ia_css_xnr_config xnr_config; + struct ia_css_dz_config dz_config; + struct ia_css_cc_config yuv2rgb_cc_config; + struct ia_css_cc_config rgb2yuv_cc_config; + struct ia_css_macc_table macc_table; + struct ia_css_gamma_table gamma_table; + struct ia_css_ctc_table ctc_table; + + struct ia_css_xnr_table xnr_table; + struct ia_css_rgb_gamma_table r_gamma_table; + struct ia_css_rgb_gamma_table g_gamma_table; + struct ia_css_rgb_gamma_table b_gamma_table; + + struct ia_css_vector motion_vector; + struct ia_css_anr_thres anr_thres; + + struct ia_css_dvs_6axis_config *dvs_6axis; + struct ia_css_dvs2_coefficients *dvs2_coeff; + struct ia_css_shading_table *shading_table; + struct ia_css_morph_table *morph_table; + + /* + * Used to store the user pointer address of the frame. driver needs to + * translate to ia_css_frame * and then set to CSS. + */ + void *output_frame; + u32 isp_config_id; + + /* Indicates which parameters need to be updated. */ + struct atomisp_parameters update_flag; +}; + +struct atomisp_subdev_params { + /* FIXME: Determines whether raw capture buffer are being passed to + * user space. Unimplemented for now. */ + int online_process; + int yuv_ds_en; + unsigned int color_effect; + bool gdc_cac_en; + bool macc_en; + bool bad_pixel_en; + bool video_dis_en; + bool sc_en; + bool fpn_en; + bool xnr_en; + bool low_light; + int false_color; + unsigned int histogram_elenum; + + /* Current grid info */ + struct ia_css_grid_info curr_grid_info; + enum ia_css_pipe_id s3a_enabled_pipe; + + int s3a_output_bytes; + + bool dis_proj_data_valid; + + struct ia_css_dz_config dz_config; /** Digital Zoom */ + struct ia_css_capture_config capture_config; + + struct ia_css_isp_config config; + + /* current configurations */ + struct atomisp_css_params css_param; + + /* + * Intermediate buffers used to communicate data between + * CSS and user space. + */ + struct ia_css_3a_statistics *s3a_user_stat; + + void *metadata_user[ATOMISP_METADATA_TYPE_NUM]; + u32 metadata_width_size; + + struct ia_css_dvs2_statistics *dvs_stat; + struct ia_css_dvs_6axis_config *dvs_6axis; + u32 exp_id; + int dvs_hor_coef_bytes; + int dvs_ver_coef_bytes; + int dvs_ver_proj_bytes; + int dvs_hor_proj_bytes; + + /* Flash */ + int num_flash_frames; + enum atomisp_flash_state flash_state; + enum atomisp_frame_status last_frame_status; + + /* continuous capture */ + struct atomisp_cont_capture_conf offline_parm; + /* Flag to check if driver needs to update params to css */ + bool css_update_params_needed; +}; + +struct atomisp_css_params_with_list { + /* parameters for CSS */ + struct atomisp_css_params params; + struct list_head list; +}; + +struct atomisp_sub_device { + struct v4l2_subdev subdev; + struct media_pad pads[ATOMISP_SUBDEV_PADS_NUM]; + struct atomisp_pad_format fmt[ATOMISP_SUBDEV_PADS_NUM]; + u16 capture_pad; /* main capture pad; defines much of isp config */ + + enum atomisp_subdev_input_entity input; + unsigned int output; + struct atomisp_video_pipe video_out_capture; /* capture output */ + struct atomisp_video_pipe video_out_vf; /* viewfinder output */ + struct atomisp_video_pipe video_out_preview; /* preview output */ + /* video pipe main output */ + struct atomisp_video_pipe video_out_video_capture; + /* struct isp_subdev_params params; */ + struct atomisp_device *isp; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *fmt_auto; + struct v4l2_ctrl *run_mode; + struct v4l2_ctrl *depth_mode; + struct v4l2_ctrl *vfpp; + struct v4l2_ctrl *continuous_mode; + struct v4l2_ctrl *continuous_raw_buffer_size; + struct v4l2_ctrl *continuous_viewfinder; + struct v4l2_ctrl *enable_raw_buffer_lock; + + /* ISP2401 */ + struct v4l2_ctrl *ion_dev_fd; + + struct v4l2_ctrl *disable_dz; + + struct atomisp_subdev_params params; + + struct atomisp_stream_env stream_env[ATOMISP_INPUT_STREAM_NUM]; + + struct v4l2_pix_format dvs_envelop; + unsigned int s3a_bufs_in_css[IA_CSS_PIPE_ID_NUM]; + unsigned int dis_bufs_in_css; + + unsigned int metadata_bufs_in_css + [ATOMISP_INPUT_STREAM_NUM][IA_CSS_PIPE_ID_NUM]; + /* The list of free and available metadata buffers for CSS */ + struct list_head metadata[ATOMISP_METADATA_TYPE_NUM]; + /* The list of metadata buffers which have been en-queued to CSS */ + struct list_head metadata_in_css[ATOMISP_METADATA_TYPE_NUM]; + /* The list of metadata buffers which are ready for userspace to get */ + struct list_head metadata_ready[ATOMISP_METADATA_TYPE_NUM]; + + /* The list of free and available s3a stat buffers for CSS */ + struct list_head s3a_stats; + /* The list of s3a stat buffers which have been en-queued to CSS */ + struct list_head s3a_stats_in_css; + /* The list of s3a stat buffers which are ready for userspace to get */ + struct list_head s3a_stats_ready; + + struct list_head dis_stats; + struct list_head dis_stats_in_css; + spinlock_t dis_stats_lock; + + struct ia_css_frame *vf_frame; /* TODO: needed? */ + struct ia_css_frame *raw_output_frame; + enum atomisp_frame_status frame_status[VIDEO_MAX_FRAME]; + + /* This field specifies which camera (v4l2 input) is selected. */ + int input_curr; + + atomic_t sof_count; + atomic_t sequence; /* Sequence value that is assigned to buffer. */ + atomic_t sequence_temp; + + /* + * Writers of streaming must hold both isp->mutex and isp->lock. + * Readers of streaming need to hold only one of the two locks. + */ + unsigned int streaming; + bool stream_prepared; /* whether css stream is created */ + + /* subdev index: will be used to show which subdev is holding the + * resource, like which camera is used by which subdev + */ + unsigned int index; + + /* delayed memory allocation for css */ + struct completion init_done; + struct workqueue_struct *delayed_init_workq; + unsigned int delayed_init; + struct work_struct delayed_init_work; + + unsigned int latest_preview_exp_id; /* CSS ZSL/SDV raw buffer id */ + + unsigned int mipi_frame_size; + + bool copy_mode; /* CSI2+ use copy mode */ + bool yuvpp_mode; /* CSI2+ yuvpp pipe */ + + int raw_buffer_bitmap[ATOMISP_MAX_EXP_ID / 32 + + 1]; /* Record each Raw Buffer lock status */ + int raw_buffer_locked_count; + spinlock_t raw_buffer_bitmap_lock; + + /* ISP2401 */ + bool re_trigger_capture; + + struct atomisp_resolution sensor_array_res; + bool high_speed_mode; /* Indicate whether now is a high speed mode */ + int pending_capture_request; /* Indicates the number of pending capture requests. */ + + unsigned int preview_exp_id; + unsigned int postview_exp_id; +}; + +extern const struct atomisp_in_fmt_conv atomisp_in_fmt_conv[]; + +u32 atomisp_subdev_uncompressed_code(u32 code); +bool atomisp_subdev_is_compressed(u32 code); +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv(u32 code); + +/* ISP2400 */ +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + enum atomisp_input_format atomisp_in_fmt); + +/* ISP2401 */ +const struct atomisp_in_fmt_conv +*atomisp_find_in_fmt_conv_by_atomisp_in_fmt(enum atomisp_input_format + atomisp_in_fmt); + +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_compressed(u32 code); +bool atomisp_subdev_format_conversion(struct atomisp_sub_device *asd, + unsigned int source_pad); +uint16_t atomisp_subdev_source_pad(struct video_device *vdev); + +/* Get pointer to appropriate format */ +struct v4l2_mbus_framefmt +*atomisp_subdev_get_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, uint32_t which, + uint32_t pad); +struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + u32 which, uint32_t pad, + uint32_t target); +int atomisp_subdev_set_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + u32 which, uint32_t pad, uint32_t target, + u32 flags, struct v4l2_rect *r); +/* Actually set the format */ +void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + uint32_t which, + u32 pad, struct v4l2_mbus_framefmt *ffmt); + +int atomisp_update_run_mode(struct atomisp_sub_device *asd); + +void atomisp_subdev_cleanup_pending_events(struct atomisp_sub_device *asd); + +void atomisp_subdev_unregister_entities(struct atomisp_sub_device *asd); +int atomisp_subdev_register_subdev(struct atomisp_sub_device *asd, + struct v4l2_device *vdev); +int atomisp_subdev_register_video_nodes(struct atomisp_sub_device *asd, + struct v4l2_device *vdev); +int atomisp_subdev_init(struct atomisp_device *isp); +void atomisp_subdev_cleanup(struct atomisp_device *isp); +int atomisp_create_pads_links(struct atomisp_device *isp); + +#endif /* __ATOMISP_SUBDEV_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_tables.h b/drivers/staging/media/atomisp/pci/atomisp_tables.h new file mode 100644 index 000000000..e718a3f66 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_tables.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#ifndef __ATOMISP_TABLES_H__ +#define __ATOMISP_TABLES_H__ + +#include "sh_css_params.h" + +/*Sepia image effect table*/ +static struct ia_css_cc_config sepia_cc_config = { + .fraction_bits = 8, + .matrix = {141, 18, 68, -40, -5, -19, 35, 4, 16}, +}; + +/*Negative image effect table*/ +static struct ia_css_cc_config nega_cc_config = { + .fraction_bits = 8, + .matrix = {255, 29, 120, 0, 374, 342, 0, 672, -301}, +}; + +/*Mono image effect table*/ +static struct ia_css_cc_config mono_cc_config = { + .fraction_bits = 8, + .matrix = {255, 29, 120, 0, 0, 0, 0, 0, 0}, +}; + +/*Skin whiten image effect table*/ +static struct ia_css_macc_table skin_low_macc_table = { + .data = { + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 7168, 0, 2048, 8192, + 5120, -1024, 2048, 8192, + 8192, 2048, -1024, 5120, + 8192, 2048, 0, 7168, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192 + } +}; + +static struct ia_css_macc_table skin_medium_macc_table = { + .data = { + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 5120, 0, 6144, 8192, + 3072, -1024, 2048, 6144, + 6144, 2048, -1024, 3072, + 8192, 6144, 0, 5120, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192 + } +}; + +static struct ia_css_macc_table skin_high_macc_table = { + .data = { + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 4096, 0, 8192, 8192, + 0, -2048, 4096, 6144, + 6144, 4096, -2048, 0, + 8192, 8192, 0, 4096, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192 + } +}; + +/*Blue enhencement image effect table*/ +static struct ia_css_macc_table blue_macc_table = { + .data = { + 9728, -3072, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 9728, 0, -3072, 8192, + 12800, 1536, -3072, 8192, + 11264, 0, 0, 11264, + 9728, -3072, 0, 11264 + } +}; + +/*Green enhencement image effect table*/ +static struct ia_css_macc_table green_macc_table = { + .data = { + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 10240, 4096, 0, 8192, + 10240, 4096, 0, 12288, + 12288, 0, 0, 12288, + 14336, -2048, 4096, 8192, + 10240, 0, 4096, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192 + } +}; + +static struct ia_css_ctc_table vivid_ctc_table = { + .data.vamem_2 = { + 0, 384, 837, 957, 1011, 1062, 1083, 1080, + 1078, 1077, 1053, 1039, 1012, 992, 969, 951, + 929, 906, 886, 866, 845, 823, 809, 790, + 772, 758, 741, 726, 711, 701, 688, 675, + 666, 656, 648, 639, 633, 626, 618, 612, + 603, 594, 582, 572, 557, 545, 529, 516, + 504, 491, 480, 467, 459, 447, 438, 429, + 419, 412, 404, 397, 389, 382, 376, 368, + 363, 357, 351, 345, 340, 336, 330, 326, + 321, 318, 312, 308, 304, 300, 297, 294, + 291, 286, 284, 281, 278, 275, 271, 268, + 261, 257, 251, 245, 240, 235, 232, 225, + 223, 218, 213, 209, 206, 204, 199, 197, + 193, 189, 186, 185, 183, 179, 177, 175, + 172, 170, 169, 167, 164, 164, 162, 160, + 158, 157, 156, 154, 154, 152, 151, 150, + 149, 148, 146, 147, 146, 144, 143, 143, + 142, 141, 140, 141, 139, 138, 138, 138, + 137, 136, 136, 135, 134, 134, 134, 133, + 132, 132, 131, 130, 131, 130, 129, 128, + 129, 127, 127, 127, 127, 125, 125, 125, + 123, 123, 122, 120, 118, 115, 114, 111, + 110, 108, 106, 105, 103, 102, 100, 99, + 97, 97, 96, 95, 94, 93, 93, 91, + 91, 91, 90, 90, 89, 89, 88, 88, + 89, 88, 88, 87, 87, 87, 87, 86, + 87, 87, 86, 87, 86, 86, 84, 84, + 82, 80, 78, 76, 74, 72, 70, 68, + 67, 65, 62, 60, 58, 56, 55, 54, + 53, 51, 49, 49, 47, 45, 45, 45, + 41, 40, 39, 39, 34, 33, 34, 32, + 25, 23, 24, 20, 13, 9, 12, 0, + 0 + } +}; +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp_tpg.c b/drivers/staging/media/atomisp/pci/atomisp_tpg.c new file mode 100644 index 000000000..e29a96da5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_tpg.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include "atomisp_internal.h" +#include "atomisp_tpg.h" + +static int tpg_s_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static int tpg_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + /*to fake*/ + return 0; +} + +static int tpg_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + + if (format->pad) + return -EINVAL; + /* only raw8 grbg is supported by TPG */ + fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + sd_state->pads->try_fmt = *fmt; + return 0; + } + return 0; +} + +static int tpg_log_status(struct v4l2_subdev *sd) +{ + /*to fake*/ + return 0; +} + +static int tpg_s_power(struct v4l2_subdev *sd, int on) +{ + return 0; +} + +static int tpg_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + /*to fake*/ + return 0; +} + +static int tpg_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + /*to fake*/ + return 0; +} + +static int tpg_enum_frame_ival(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_interval_enum *fie) +{ + /*to fake*/ + return 0; +} + +static const struct v4l2_subdev_video_ops tpg_video_ops = { + .s_stream = tpg_s_stream, +}; + +static const struct v4l2_subdev_core_ops tpg_core_ops = { + .log_status = tpg_log_status, + .s_power = tpg_s_power, +}; + +static const struct v4l2_subdev_pad_ops tpg_pad_ops = { + .enum_mbus_code = tpg_enum_mbus_code, + .enum_frame_size = tpg_enum_frame_size, + .enum_frame_interval = tpg_enum_frame_ival, + .get_fmt = tpg_get_fmt, + .set_fmt = tpg_set_fmt, +}; + +static const struct v4l2_subdev_ops tpg_ops = { + .core = &tpg_core_ops, + .video = &tpg_video_ops, + .pad = &tpg_pad_ops, +}; + +void atomisp_tpg_unregister_entities(struct atomisp_tpg_device *tpg) +{ + media_entity_cleanup(&tpg->sd.entity); + v4l2_device_unregister_subdev(&tpg->sd); +} + +int atomisp_tpg_register_entities(struct atomisp_tpg_device *tpg, + struct v4l2_device *vdev) +{ + int ret; + /* Register the subdev and video nodes. */ + ret = v4l2_device_register_subdev(vdev, &tpg->sd); + if (ret < 0) + goto error; + + return 0; + +error: + atomisp_tpg_unregister_entities(tpg); + return ret; +} + +void atomisp_tpg_cleanup(struct atomisp_device *isp) +{ +} + +int atomisp_tpg_init(struct atomisp_device *isp) +{ + struct atomisp_tpg_device *tpg = &isp->tpg; + struct v4l2_subdev *sd = &tpg->sd; + struct media_pad *pads = tpg->pads; + struct media_entity *me = &sd->entity; + int ret; + + tpg->isp = isp; + v4l2_subdev_init(sd, &tpg_ops); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + strscpy(sd->name, "tpg_subdev", sizeof(sd->name)); + v4l2_set_subdevdata(sd, tpg); + + pads[0].flags = MEDIA_PAD_FL_SINK; + me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; + + ret = media_entity_pads_init(me, 1, pads); + if (ret < 0) + goto fail; + return 0; +fail: + atomisp_tpg_cleanup(isp); + return ret; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp_tpg.h b/drivers/staging/media/atomisp/pci/atomisp_tpg.h new file mode 100644 index 000000000..4176e076f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_tpg.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_TPG_H__ +#define __ATOMISP_TPG_H__ + +#include +#include + +struct atomisp_tpg_device { + struct v4l2_subdev sd; + struct atomisp_device *isp; + struct media_pad pads[1]; +}; + +void atomisp_tpg_cleanup(struct atomisp_device *isp); +int atomisp_tpg_init(struct atomisp_device *isp); +void atomisp_tpg_unregister_entities(struct atomisp_tpg_device *tpg); +int atomisp_tpg_register_entities(struct atomisp_tpg_device *tpg, + struct v4l2_device *vdev); + +#endif /* __ATOMISP_TPG_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp_trace_event.h b/drivers/staging/media/atomisp/pci/atomisp_trace_event.h new file mode 100644 index 000000000..538d45e00 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_trace_event.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support Camera Imaging tracer core. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM atomisp + +#if !defined(ATOMISP_TRACE_EVENT_H) || defined(TRACE_HEADER_MULTI_READ) +#define ATOMISP_TRACE_EVENT_H + +#include +#include +TRACE_EVENT(camera_meminfo, + + TP_PROTO(const char *name, int uptr_size, int counter, int sys_size, + int sys_res_size, int cam_sys_use, int cam_dyc_use, + int cam_res_use), + + TP_ARGS(name, uptr_size, counter, sys_size, sys_res_size, cam_sys_use, + cam_dyc_use, cam_res_use), + + TP_STRUCT__entry( + __array(char, name, 24) + __field(int, uptr_size) + __field(int, counter) + __field(int, sys_size) + __field(int, sys_res_size) + __field(int, cam_res_use) + __field(int, cam_dyc_use) + __field(int, cam_sys_use) + ), + + TP_fast_assign( + strscpy(__entry->name, name, 24); + __entry->uptr_size = uptr_size; + __entry->counter = counter; + __entry->sys_size = sys_size; + __entry->sys_res_size = sys_res_size; + __entry->cam_res_use = cam_res_use; + __entry->cam_dyc_use = cam_dyc_use; + __entry->cam_sys_use = cam_sys_use; + ), + + TP_printk( + "<%s> User ptr memory:%d pages,\tISP private memory used:%d pages:\tsysFP system size:%d,\treserved size:%d\tcamFP sysUse:%d,\tdycUse:%d,\tresUse:%d.\n", + __entry->name, __entry->uptr_size, __entry->counter, + __entry->sys_size, __entry->sys_res_size, __entry->cam_sys_use, + __entry->cam_dyc_use, __entry->cam_res_use) + ); + +TRACE_EVENT(camera_debug, + + TP_PROTO(const char *name, char *info, const int line), + + TP_ARGS(name, info, line), + + TP_STRUCT__entry( + __array(char, name, 24) + __array(char, info, 24) + __field(int, line) + ), + + TP_fast_assign( + strscpy(__entry->name, name, 24); + strscpy(__entry->info, info, 24); + __entry->line = line; + ), + + TP_printk("<%s>-<%d> %s\n", __entry->name, __entry->line, + __entry->info) + ); + +TRACE_EVENT(ipu_cstate, + + TP_PROTO(int cstate), + + TP_ARGS(cstate), + + TP_STRUCT__entry( + __field(int, cstate) + ), + + TP_fast_assign( + __entry->cstate = cstate; + ), + + TP_printk("cstate=%d", __entry->cstate) + ); + +TRACE_EVENT(ipu_pstate, + + TP_PROTO(int freq, int util), + + TP_ARGS(freq, util), + + TP_STRUCT__entry( + __field(int, freq) + __field(int, util) + ), + + TP_fast_assign( + __entry->freq = freq; + __entry->util = util; + ), + + TP_printk("freq=%d util=%d", __entry->freq, __entry->util) + ); +#endif + +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE atomisp_trace_event +/* This part must be outside protection */ +#include diff --git a/drivers/staging/media/atomisp/pci/atomisp_v4l2.c b/drivers/staging/media/atomisp/pci/atomisp_v4l2.c new file mode 100644 index 000000000..e786b8192 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_v4l2.c @@ -0,0 +1,1746 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../../include/linux/atomisp_gmin_platform.h" + +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_fops.h" +#include "atomisp_ioctl.h" +#include "atomisp_internal.h" +#include "atomisp-regs.h" +#include "atomisp_dfs_tables.h" +#include "atomisp_drvfs.h" +#include "hmm/hmm.h" +#include "atomisp_trace_event.h" + +#include "sh_css_firmware.h" + +#include "device_access.h" + +/* Timeouts to wait for all subdevs to be registered */ +#define SUBDEV_WAIT_TIMEOUT 50 /* ms */ +#define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */ + +/* G-Min addition: pull this in from intel_mid_pm.h */ +#define CSTATE_EXIT_LATENCY_C1 1 + +static uint skip_fwload; +module_param(skip_fwload, uint, 0644); +MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load"); + +/* memory optimization: deferred firmware loading */ +bool defer_fw_load; +module_param(defer_fw_load, bool, 0644); +MODULE_PARM_DESC(defer_fw_load, + "Defer FW loading until device is opened (default:disable)"); + +/* cross componnet debug message flag */ +int dbg_level; +module_param(dbg_level, int, 0644); +MODULE_PARM_DESC(dbg_level, "debug message level (default:0)"); + +/* log function switch */ +int dbg_func = 2; +module_param(dbg_func, int, 0644); +MODULE_PARM_DESC(dbg_func, + "log function switch non/trace_printk/printk (default:printk)"); + +int mipicsi_flag; +module_param(mipicsi_flag, int, 0644); +MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm"); + +static char firmware_name[256]; +module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0); +MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name."); + +/*set to 16x16 since this is the amount of lines and pixels the sensor +exports extra. If these are kept at the 10x8 that they were on, in yuv +downscaling modes incorrect resolutions where requested to the sensor +driver with strange outcomes as a result. The proper way tot do this +would be to have a list of tables the specify the sensor res, mipi rec, +output res, and isp output res. however since we do not have this yet, +the chosen solution is the next best thing. */ +int pad_w = 16; +module_param(pad_w, int, 0644); +MODULE_PARM_DESC(pad_w, "extra data for ISP processing"); + +int pad_h = 16; +module_param(pad_h, int, 0644); +MODULE_PARM_DESC(pad_h, "extra data for ISP processing"); + +/* + * FIXME: this is a hack to make easier to support ISP2401 variant. + * As a given system will either be ISP2401 or not, we can just use + * a boolean, in order to replace existing #ifdef ISP2401 everywhere. + * + * Once this driver gets into a better shape, however, the best would + * be to replace this to something stored inside atomisp allocated + * structures. + */ + +struct device *atomisp_dev; + +static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_457MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +/* Merrifield and Moorefield DFS rules */ +static const struct atomisp_dfs_config dfs_config_merr = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_400MHZ, + .highest_freq = ISP_FREQ_457MHZ, + .dfs_table = dfs_rules_merr, + .dfs_table_size = ARRAY_SIZE(dfs_rules_merr), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_dfs_config dfs_config_merr_1179 = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_400MHZ, + .highest_freq = ISP_FREQ_400MHZ, + .dfs_table = dfs_rules_merr_1179, + .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = { + { + .width = 1920, + .height = 1080, + .fps = 30, + .isp_freq = ISP_FREQ_266MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = 1080, + .height = 1920, + .fps = 30, + .isp_freq = ISP_FREQ_266MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = 1920, + .height = 1080, + .fps = 45, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = 1080, + .height = 1920, + .fps = 45, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = 60, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_200MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_200MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static struct atomisp_dfs_config dfs_config_merr_117a = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_200MHZ, + .highest_freq = ISP_FREQ_400MHZ, + .dfs_table = dfs_rules_merr_117a, + .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_dfs_config dfs_config_byt = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_400MHZ, + .highest_freq = ISP_FREQ_400MHZ, + .dfs_table = dfs_rules_byt, + .dfs_table_size = ARRAY_SIZE(dfs_rules_byt), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = 1280, + .height = 720, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_dfs_config dfs_config_cht = { + .lowest_freq = ISP_FREQ_100MHZ, + .max_freq_at_vmin = ISP_FREQ_356MHZ, + .highest_freq = ISP_FREQ_356MHZ, + .dfs_table = dfs_rules_cht, + .dfs_table_size = ARRAY_SIZE(dfs_rules_cht), +}; + +/* This one should be visible also by atomisp_cmd.c */ +const struct atomisp_dfs_config dfs_config_cht_soc = { + .lowest_freq = ISP_FREQ_100MHZ, + .max_freq_at_vmin = ISP_FREQ_356MHZ, + .highest_freq = ISP_FREQ_356MHZ, + .dfs_table = dfs_rules_cht_soc, + .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc), +}; + +int atomisp_video_init(struct atomisp_video_pipe *video, const char *name, + unsigned int run_mode) +{ + int ret; + const char *direction; + + switch (video->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + direction = "output"; + video->pad.flags = MEDIA_PAD_FL_SINK; + video->vdev.fops = &atomisp_fops; + video->vdev.ioctl_ops = &atomisp_ioctl_ops; + video->vdev.lock = &video->isp->mutex; + break; + default: + return -EINVAL; + } + + ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad); + if (ret < 0) + return ret; + + /* Initialize the video device. */ + snprintf(video->vdev.name, sizeof(video->vdev.name), + "ATOMISP ISP %s %s", name, direction); + video->vdev.release = video_device_release_empty; + video_set_drvdata(&video->vdev, video->isp); + video->default_run_mode = run_mode; + + return 0; +} + +void atomisp_video_unregister(struct atomisp_video_pipe *video) +{ + if (video_is_registered(&video->vdev)) { + media_entity_cleanup(&video->vdev.entity); + video_unregister_device(&video->vdev); + } +} + +static int atomisp_save_iunit_reg(struct atomisp_device *isp) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + + dev_dbg(isp->dev, "%s\n", __func__); + + pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts); + /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */ + pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap); + pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr); + pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data); + pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr); + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control); + + pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs); + /* Ensure read/write combining is enabled. */ + pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control); + isp->saved_regs.i_control |= + MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING | + MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING; + pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, + &isp->saved_regs.csi_access_viol); + pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, + &isp->saved_regs.csi_rcomp_config); + /* + * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE. + * ANN/CHV: RCOMP updates do not happen when using CSI2+ path + * and sensor sending "continuous clock". + * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence + * is missed, and IUNIT can hang. + * For both issues, setting this bit is a workaround. + */ + isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE; + pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, + &isp->saved_regs.csi_afe_dly); + pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, + &isp->saved_regs.csi_control); + if (isp->media_dev.hw_revision >= + (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT)) + isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN; + /* + * On CHT CSI_READY bit should be enabled before stream on + */ + if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << + ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0))) + isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY; + pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, + &isp->saved_regs.csi_afe_rcomp_config); + pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, + &isp->saved_regs.csi_afe_hs_control); + pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, + &isp->saved_regs.csi_deadline_control); + return 0; +} + +static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + + dev_dbg(isp->dev, "%s\n", __func__); + + pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts); + pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr); + pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap); + pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr); + pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data); + pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr); + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control); + pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control); + + pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs); + pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, + isp->saved_regs.csi_access_viol); + pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, + isp->saved_regs.csi_rcomp_config); + pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, + isp->saved_regs.csi_afe_dly); + pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, + isp->saved_regs.csi_control); + pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, + isp->saved_regs.csi_afe_rcomp_config); + pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, + isp->saved_regs.csi_afe_hs_control); + pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, + isp->saved_regs.csi_deadline_control); + + /* + * for MRFLD, Software/firmware needs to write a 1 to bit0 + * of the register at CSI_RECEIVER_SELECTION_REG to enable + * SH CSI backend write 0 will enable Arasan CSI backend, + * which has bugs(like sighting:4567697 and 4567699) and + * will be removed in B0 + */ + atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); + return 0; +} + +static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + u32 irq; + unsigned long flags; + + spin_lock_irqsave(&isp->lock, flags); + + /* + * MRFLD HAS requirement: cannot power off i-unit if + * ISP has IRQ not serviced. + * So, here we need to check if there is any pending + * IRQ, if so, waiting for it to be served + */ + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); + irq &= BIT(INTR_IIR); + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); + + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); + if (!(irq & BIT(INTR_IIR))) + goto done; + + atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF); + atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq); + if (irq != 0) { + dev_err(isp->dev, + "%s: fail to clear isp interrupt status reg=0x%x\n", + __func__, irq); + spin_unlock_irqrestore(&isp->lock, flags); + return -EAGAIN; + } else { + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); + irq &= BIT(INTR_IIR); + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); + + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); + if (!(irq & BIT(INTR_IIR))) { + atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0); + goto done; + } + dev_err(isp->dev, + "%s: error in iunit interrupt. status reg=0x%x\n", + __func__, irq); + spin_unlock_irqrestore(&isp->lock, flags); + return -EAGAIN; + } +done: + /* + * MRFLD WORKAROUND: + * before powering off IUNIT, clear the pending interrupts + * and disable the interrupt. driver should avoid writing 0 + * to IIR. It could block subsequent interrupt messages. + * HW sighting:4568410. + */ + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); + irq &= ~BIT(INTR_IER); + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); + + atomisp_msi_irq_uninit(isp); + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); + spin_unlock_irqrestore(&isp->lock, flags); + + return 0; +} + +/* +* WA for DDR DVFS enable/disable +* By default, ISP will force DDR DVFS 1600MHz before disable DVFS +*/ +static void punit_ddr_dvfs_enable(bool enable) +{ + int door_bell = 1 << 8; + int max_wait = 30; + int reg; + + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); + if (enable) { + reg &= ~(MRFLD_BIT0 | MRFLD_BIT1); + } else { + reg |= (MRFLD_BIT1 | door_bell); + reg &= ~(MRFLD_BIT0); + } + iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg); + + /* Check Req_ACK to see freq status, wait until door_bell is cleared */ + while ((reg & door_bell) && max_wait--) { + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); + usleep_range(100, 500); + } + + if (max_wait == -1) + pr_info("DDR DVFS, door bell is not cleared within 3ms\n"); +} + +static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable) +{ + unsigned long timeout; + u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON : + MRFLD_ISPSSPM0_IUNIT_POWER_OFF; + + dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off"); + + /* WA for P-Unit, if DVFS enabled, ISP timeout observed */ + if (IS_CHT && enable) + punit_ddr_dvfs_enable(false); + + /* + * FIXME:WA for ECS28A, with this sleep, CTS + * android.hardware.camera2.cts.CameraDeviceTest#testCameraDeviceAbort + * PASS, no impact on other platforms + */ + if (IS_BYT && enable) + msleep(10); + + /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */ + iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, + val, MRFLD_ISPSSPM0_ISPSSC_MASK); + + /* WA:Enable DVFS */ + if (IS_CHT && !enable) + punit_ddr_dvfs_enable(true); + + /* + * There should be no IUNIT access while power-down is + * in progress. HW sighting: 4567865. + * Wait up to 50 ms for the IUNIT to shut down. + * And we do the same for power on. + */ + timeout = jiffies + msecs_to_jiffies(50); + do { + u32 tmp; + + /* Wait until ISPSSPM0 bit[25:24] shows the right value */ + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp); + tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK; + if (tmp == val) { + trace_ipu_cstate(enable); + return 0; + } + + if (time_after(jiffies, timeout)) + break; + + /* FIXME: experienced value for delay */ + usleep_range(100, 150); + } while (1); + + if (enable) + msleep(10); + + dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off"); + return -EBUSY; +} + +int atomisp_power_off(struct device *dev) +{ + struct atomisp_device *isp = dev_get_drvdata(dev); + struct pci_dev *pdev = to_pci_dev(dev); + int ret; + u32 reg; + + atomisp_css_uninit(isp); + + ret = atomisp_mrfld_pre_power_down(isp); + if (ret) + return ret; + + /* + * MRFLD IUNIT DPHY is located in an always-power-on island + * MRFLD HW design need all CSI ports are disabled before + * powering down the IUNIT. + */ + pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®); + reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK; + pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg); + + cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); + return atomisp_mrfld_power(isp, false); +} + +int atomisp_power_on(struct device *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *) + dev_get_drvdata(dev); + int ret; + + ret = atomisp_mrfld_power(isp, true); + if (ret) + return ret; + + cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); + + /*restore register values for iUnit and iUnitPHY registers*/ + if (isp->saved_regs.pcicmdsts) + atomisp_restore_iunit_reg(isp); + + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); + + return atomisp_css_init(isp); +} + +static int __maybe_unused atomisp_suspend(struct device *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *) + dev_get_drvdata(dev); + /* FIXME: only has one isp_subdev at present */ + struct atomisp_sub_device *asd = &isp->asd[0]; + unsigned long flags; + + /* + * FIXME: Suspend is not supported by sensors. Abort if any video + * node was opened. + */ + if (atomisp_dev_users(isp)) + return -EBUSY; + + spin_lock_irqsave(&isp->lock, flags); + if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { + spin_unlock_irqrestore(&isp->lock, flags); + dev_err(isp->dev, "atomisp cannot suspend at this time.\n"); + return -EINVAL; + } + spin_unlock_irqrestore(&isp->lock, flags); + + return atomisp_power_off(dev); +} + +static int __maybe_unused atomisp_resume(struct device *dev) +{ + return atomisp_power_on(dev); +} + +int atomisp_csi_lane_config(struct atomisp_device *isp) +{ + struct pci_dev *pdev = to_pci_dev(isp->dev); + static const struct { + u8 code; + u8 lanes[MRFLD_PORT_NUM]; + } portconfigs[] = { + /* Tangier/Merrifield available lane configurations */ + { 0x00, { 4, 1, 0 } }, /* 00000 */ + { 0x01, { 3, 1, 0 } }, /* 00001 */ + { 0x02, { 2, 1, 0 } }, /* 00010 */ + { 0x03, { 1, 1, 0 } }, /* 00011 */ + { 0x04, { 2, 1, 2 } }, /* 00100 */ + { 0x08, { 3, 1, 1 } }, /* 01000 */ + { 0x09, { 2, 1, 1 } }, /* 01001 */ + { 0x0a, { 1, 1, 1 } }, /* 01010 */ + + /* Anniedale/Moorefield only configurations */ + { 0x10, { 4, 2, 0 } }, /* 10000 */ + { 0x11, { 3, 2, 0 } }, /* 10001 */ + { 0x12, { 2, 2, 0 } }, /* 10010 */ + { 0x13, { 1, 2, 0 } }, /* 10011 */ + { 0x14, { 2, 2, 2 } }, /* 10100 */ + { 0x18, { 3, 2, 1 } }, /* 11000 */ + { 0x19, { 2, 2, 1 } }, /* 11001 */ + { 0x1a, { 1, 2, 1 } }, /* 11010 */ + }; + + unsigned int i, j; + u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 }; + u32 csi_control; + int nportconfigs; + u32 port_config_mask; + int port3_lanes_shift; + + if (isp->media_dev.hw_revision < + ATOMISP_HW_REVISION_ISP2401_LEGACY << + ATOMISP_HW_REVISION_SHIFT) { + /* Merrifield */ + port_config_mask = MRFLD_PORT_CONFIG_MASK; + port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT; + } else { + /* Moorefield / Cherryview */ + port_config_mask = CHV_PORT_CONFIG_MASK; + port3_lanes_shift = CHV_PORT3_LANES_SHIFT; + } + + if (isp->media_dev.hw_revision < + ATOMISP_HW_REVISION_ISP2401 << + ATOMISP_HW_REVISION_SHIFT) { + /* Merrifield / Moorefield legacy input system */ + nportconfigs = MRFLD_PORT_CONFIG_NUM; + } else { + /* Moorefield / Cherryview new input system */ + nportconfigs = ARRAY_SIZE(portconfigs); + } + + for (i = 0; i < isp->input_cnt; i++) { + struct camera_mipi_info *mipi_info; + + if (isp->inputs[i].type != RAW_CAMERA && + isp->inputs[i].type != SOC_CAMERA) + continue; + + mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera); + if (!mipi_info) + continue; + + switch (mipi_info->port) { + case ATOMISP_CAMERA_PORT_PRIMARY: + sensor_lanes[0] = mipi_info->num_lanes; + break; + case ATOMISP_CAMERA_PORT_SECONDARY: + sensor_lanes[1] = mipi_info->num_lanes; + break; + case ATOMISP_CAMERA_PORT_TERTIARY: + sensor_lanes[2] = mipi_info->num_lanes; + break; + default: + dev_err(isp->dev, + "%s: invalid port: %d for the %dth sensor\n", + __func__, mipi_info->port, i); + return -EINVAL; + } + } + + for (i = 0; i < nportconfigs; i++) { + for (j = 0; j < MRFLD_PORT_NUM; j++) + if (sensor_lanes[j] && + sensor_lanes[j] != portconfigs[i].lanes[j]) + break; + + if (j == MRFLD_PORT_NUM) + break; /* Found matching setting */ + } + + if (i >= nportconfigs) { + dev_err(isp->dev, + "%s: could not find the CSI port setting for %d-%d-%d\n", + __func__, + sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]); + return -EINVAL; + } + + pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control); + csi_control &= ~port_config_mask; + csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT) + | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT)) + | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT)) + | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT)) + | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT) + | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT) + | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift); + + pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control); + + dev_dbg(isp->dev, + "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n", + __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1], + portconfigs[i].lanes[2], csi_control); + + return 0; +} + +static int atomisp_subdev_probe(struct atomisp_device *isp) +{ + const struct atomisp_platform_data *pdata; + struct intel_v4l2_subdev_table *subdevs; + int ret, raw_index = -1, count; + + pdata = atomisp_get_platform_data(); + if (!pdata) { + dev_err(isp->dev, "no platform data available\n"); + return 0; + } + + /* FIXME: should return -EPROBE_DEFER if not all subdevs were probed */ + for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) { + int camera_count = 0; + + for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { + if (subdevs->type == RAW_CAMERA || + subdevs->type == SOC_CAMERA) + camera_count++; + } + if (camera_count) + break; + msleep(SUBDEV_WAIT_TIMEOUT); + } + /* Wait more time to give more time for subdev init code to finish */ + msleep(5 * SUBDEV_WAIT_TIMEOUT); + + /* FIXME: should, instead, use I2C probe */ + + for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { + struct v4l2_subdev *subdev; + struct i2c_board_info *board_info = + &subdevs->v4l2_subdev.board_info; + struct i2c_adapter *adapter = + i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id); + + dev_info(isp->dev, "Probing Subdev %s\n", board_info->type); + + if (!adapter) { + dev_err(isp->dev, + "Failed to find i2c adapter for subdev %s\n", + board_info->type); + break; + } + + /* In G-Min, the sensor devices will already be probed + * (via ACPI) and registered, do not create new + * ones */ + subdev = atomisp_gmin_find_subdev(adapter, board_info); + if (!subdev) { + dev_warn(isp->dev, "Subdev %s not found\n", + board_info->type); + continue; + } + ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev); + if (ret) { + dev_warn(isp->dev, "Subdev %s detection fail\n", + board_info->type); + continue; + } + + if (!subdev) { + dev_warn(isp->dev, "Subdev %s detection fail\n", + board_info->type); + continue; + } + + dev_info(isp->dev, "Subdev %s successfully register\n", + board_info->type); + + switch (subdevs->type) { + case RAW_CAMERA: + dev_dbg(isp->dev, "raw_index: %d\n", raw_index); + raw_index = isp->input_cnt; + fallthrough; + case SOC_CAMERA: + dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt); + if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { + dev_warn(isp->dev, + "too many atomisp inputs, ignored\n"); + break; + } + + isp->inputs[isp->input_cnt].type = subdevs->type; + isp->inputs[isp->input_cnt].port = subdevs->port; + isp->inputs[isp->input_cnt].camera = subdev; + isp->inputs[isp->input_cnt].sensor_index = 0; + /* + * initialize the subdev frame size, then next we can + * judge whether frame_size store effective value via + * pixel_format. + */ + isp->inputs[isp->input_cnt].frame_size.pixel_format = 0; + isp->input_cnt++; + break; + case CAMERA_MOTOR: + if (isp->motor) { + dev_warn(isp->dev, + "too many atomisp motors, ignored %s\n", + board_info->type); + continue; + } + isp->motor = subdev; + break; + case LED_FLASH: + case XENON_FLASH: + if (isp->flash) { + dev_warn(isp->dev, + "too many atomisp flash devices, ignored %s\n", + board_info->type); + continue; + } + isp->flash = subdev; + break; + default: + dev_dbg(isp->dev, "unknown subdev probed\n"); + break; + } + } + + /* + * HACK: Currently VCM belongs to primary sensor only, but correct + * approach must be to acquire from platform code which sensor + * owns it. + */ + if (isp->motor && raw_index >= 0) + isp->inputs[raw_index].motor = isp->motor; + + /* Proceed even if no modules detected. For COS mode and no modules. */ + if (!isp->input_cnt) + dev_warn(isp->dev, "no camera attached or fail to detect\n"); + else + dev_info(isp->dev, "detected %d camera sensors\n", + isp->input_cnt); + + return atomisp_csi_lane_config(isp); +} + +static void atomisp_unregister_entities(struct atomisp_device *isp) +{ + unsigned int i; + struct v4l2_subdev *sd, *next; + + for (i = 0; i < isp->num_of_streams; i++) + atomisp_subdev_unregister_entities(&isp->asd[i]); + atomisp_tpg_unregister_entities(&isp->tpg); + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) + atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); + + list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list) + v4l2_device_unregister_subdev(sd); + + v4l2_device_unregister(&isp->v4l2_dev); + media_device_unregister(&isp->media_dev); + media_device_cleanup(&isp->media_dev); +} + +static int atomisp_register_entities(struct atomisp_device *isp) +{ + int ret = 0; + unsigned int i; + + isp->media_dev.dev = isp->dev; + + strscpy(isp->media_dev.model, "Intel Atom ISP", + sizeof(isp->media_dev.model)); + + media_device_init(&isp->media_dev); + isp->v4l2_dev.mdev = &isp->media_dev; + ret = v4l2_device_register(isp->dev, &isp->v4l2_dev); + if (ret < 0) { + dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n", + __func__, ret); + goto v4l2_device_failed; + } + + ret = atomisp_subdev_probe(isp); + if (ret < 0) + goto csi_and_subdev_probe_failed; + + /* Register internal entities */ + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { + ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i], + &isp->v4l2_dev); + if (ret == 0) + continue; + + /* error case */ + dev_err(isp->dev, "failed to register the CSI port: %d\n", i); + /* deregister all registered CSI ports */ + while (i--) + atomisp_mipi_csi2_unregister_entities( + &isp->csi2_port[i]); + + goto csi_and_subdev_probe_failed; + } + + ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev); + if (ret < 0) { + dev_err(isp->dev, "atomisp_tpg_register_entities\n"); + goto tpg_register_failed; + } + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + ret = atomisp_subdev_register_subdev(asd, &isp->v4l2_dev); + if (ret < 0) { + dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n"); + for (; i > 0; i--) + atomisp_subdev_unregister_entities( + &isp->asd[i - 1]); + goto subdev_register_failed; + } + } + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + init_completion(&asd->init_done); + + asd->delayed_init_workq = + alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE, + 1); + if (!asd->delayed_init_workq) { + dev_err(isp->dev, + "Failed to initialize delayed init workq\n"); + ret = -ENOMEM; + + for (; i > 0; i--) + destroy_workqueue(isp->asd[i - 1]. + delayed_init_workq); + goto wq_alloc_failed; + } + INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work); + } + + for (i = 0; i < isp->input_cnt; i++) { + if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) { + dev_err(isp->dev, "isp->inputs port %d not supported\n", + isp->inputs[i].port); + ret = -EINVAL; + goto link_failed; + } + } + + if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) { + dev_dbg(isp->dev, + "TPG detected, camera_cnt: %d\n", isp->input_cnt); + isp->inputs[isp->input_cnt].type = TEST_PATTERN; + isp->inputs[isp->input_cnt].port = -1; + isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd; + } else { + dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n"); + } + + return 0; + +link_failed: + for (i = 0; i < isp->num_of_streams; i++) + destroy_workqueue(isp->asd[i]. + delayed_init_workq); +wq_alloc_failed: + for (i = 0; i < isp->num_of_streams; i++) + atomisp_subdev_unregister_entities( + &isp->asd[i]); +subdev_register_failed: + atomisp_tpg_unregister_entities(&isp->tpg); +tpg_register_failed: + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) + atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); +csi_and_subdev_probe_failed: + v4l2_device_unregister(&isp->v4l2_dev); +v4l2_device_failed: + media_device_unregister(&isp->media_dev); + media_device_cleanup(&isp->media_dev); + return ret; +} + +static int atomisp_register_device_nodes(struct atomisp_device *isp) +{ + int i, err; + + for (i = 0; i < isp->num_of_streams; i++) { + err = atomisp_subdev_register_video_nodes(&isp->asd[i], &isp->v4l2_dev); + if (err) + return err; + } + + err = atomisp_create_pads_links(isp); + if (err) + return err; + + err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev); + if (err) + return err; + + return media_device_register(&isp->media_dev); +} + +static int atomisp_initialize_modules(struct atomisp_device *isp) +{ + int ret; + + ret = atomisp_mipi_csi2_init(isp); + if (ret < 0) { + dev_err(isp->dev, "mipi csi2 initialization failed\n"); + goto error_mipi_csi2; + } + + ret = atomisp_tpg_init(isp); + if (ret < 0) { + dev_err(isp->dev, "tpg initialization failed\n"); + goto error_tpg; + } + + ret = atomisp_subdev_init(isp); + if (ret < 0) { + dev_err(isp->dev, "ISP subdev initialization failed\n"); + goto error_isp_subdev; + } + + return 0; + +error_isp_subdev: +error_tpg: + atomisp_tpg_cleanup(isp); +error_mipi_csi2: + atomisp_mipi_csi2_cleanup(isp); + return ret; +} + +static void atomisp_uninitialize_modules(struct atomisp_device *isp) +{ + atomisp_tpg_cleanup(isp); + atomisp_mipi_csi2_cleanup(isp); +} + +const struct firmware * +atomisp_load_firmware(struct atomisp_device *isp) +{ + const struct firmware *fw; + int rc; + char *fw_path = NULL; + + if (skip_fwload) + return NULL; + + if (firmware_name[0] != '\0') { + fw_path = firmware_name; + } else { + if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) + == ATOMISP_HW_REVISION_ISP2401) + fw_path = "shisp_2401a0_v21.bin"; + + if (isp->media_dev.hw_revision == + ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) + | ATOMISP_HW_STEPPING_A0)) + fw_path = "shisp_2401a0_legacy_v21.bin"; + + if (isp->media_dev.hw_revision == + ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) + | ATOMISP_HW_STEPPING_B0)) + fw_path = "shisp_2400b0_v21.bin"; + } + + if (!fw_path) { + dev_err(isp->dev, "Unsupported hw_revision 0x%x\n", + isp->media_dev.hw_revision); + return NULL; + } + + rc = request_firmware(&fw, fw_path, isp->dev); + if (rc) { + dev_err(isp->dev, + "atomisp: Error %d while requesting firmware %s\n", + rc, fw_path); + return NULL; + } + + return fw; +} + +/* + * Check for flags the driver was compiled with against the PCI + * device. Always returns true on other than ISP 2400. + */ +static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id) +{ + const char *name; + const char *product; + + product = dmi_get_system_info(DMI_PRODUCT_NAME); + + switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { + case ATOMISP_PCI_DEVICE_SOC_MRFLD: + name = "Merrifield"; + break; + case ATOMISP_PCI_DEVICE_SOC_BYT: + name = "Baytrail"; + break; + case ATOMISP_PCI_DEVICE_SOC_ANN: + name = "Anniedale"; + break; + case ATOMISP_PCI_DEVICE_SOC_CHT: + name = "Cherrytrail"; + break; + default: + dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n", + product, id->vendor, id->device); + return false; + } + + if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) { + dev_err(&pdev->dev, "%s revision %d is not unsupported\n", + name, pdev->revision); + return false; + } + + /* + * FIXME: + * remove the if once the driver become generic + */ + +#ifndef ISP2401 + if (IS_ISP2401) { + dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n", + name); + return false; + } +#else + if (!IS_ISP2401) { + dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n", + name); + return false; + } +#endif + + dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n", + name, pdev->revision, IS_ISP2401 ? '1' : '0', product); + + return true; +} + +#define ATOM_ISP_PCI_BAR 0 + +static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + const struct atomisp_platform_data *pdata; + struct atomisp_device *isp; + unsigned int start; + int err, val; + u32 irq; + + if (!is_valid_device(pdev, id)) + return -ENODEV; + + /* Pointer to struct device. */ + atomisp_dev = &pdev->dev; + + pdata = atomisp_get_platform_data(); + if (!pdata) + dev_warn(&pdev->dev, "no platform data available\n"); + + err = pcim_enable_device(pdev); + if (err) { + dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err); + return err; + } + + start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR); + dev_dbg(&pdev->dev, "start: 0x%x\n", start); + + err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev)); + if (err) { + dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err); + goto ioremap_fail; + } + + isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL); + if (!isp) { + err = -ENOMEM; + goto atomisp_dev_alloc_fail; + } + + isp->dev = &pdev->dev; + isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR]; + isp->saved_regs.ispmmadr = start; + + dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base); + + mutex_init(&isp->mutex); + spin_lock_init(&isp->lock); + + /* This is not a true PCI device on SoC, so the delay is not needed. */ + pdev->d3hot_delay = 0; + + pci_set_drvdata(pdev, isp); + + switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { + case ATOMISP_PCI_DEVICE_SOC_MRFLD: + isp->media_dev.hw_revision = + (ATOMISP_HW_REVISION_ISP2400 + << ATOMISP_HW_REVISION_SHIFT) | + ATOMISP_HW_STEPPING_B0; + + switch (id->device) { + case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179: + isp->dfs = &dfs_config_merr_1179; + break; + case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A: + isp->dfs = &dfs_config_merr_117a; + + break; + default: + isp->dfs = &dfs_config_merr; + break; + } + isp->hpll_freq = HPLL_FREQ_1600MHZ; + break; + case ATOMISP_PCI_DEVICE_SOC_BYT: + isp->media_dev.hw_revision = + (ATOMISP_HW_REVISION_ISP2400 + << ATOMISP_HW_REVISION_SHIFT) | + ATOMISP_HW_STEPPING_B0; + + /* + * Note: some Intel-based tablets with Android use a different + * DFS table. Based on the comments at the Yocto Aero meta + * version of this driver (at the ssid.h header), they're + * identified via a "spid" var: + * + * androidboot.spid=vend:cust:manu:plat:prod:hard + * + * As we don't have this upstream, nor we know enough details + * to use a DMI or PCI match table, the old code was just + * removed, but let's keep a note here as a reminder that, + * for certain devices, we may need to limit the max DFS + * frequency to be below certain values, adjusting the + * resolution accordingly. + */ + isp->dfs = &dfs_config_byt; + + /* + * HPLL frequency is known to be device-specific, but we don't + * have specs yet for exactly how it varies. Default to + * BYT-CR but let provisioning set it via EFI variable + */ + isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ); + + /* + * for BYT/CHT we are put isp into D3cold to avoid pci registers access + * in power off. Set d3cold_delay to 0 since default 100ms is not + * necessary. + */ + pdev->d3cold_delay = 0; + break; + case ATOMISP_PCI_DEVICE_SOC_ANN: + isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 + << ATOMISP_HW_REVISION_SHIFT); + isp->media_dev.hw_revision |= pdev->revision < 2 ? + ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; + isp->dfs = &dfs_config_merr; + isp->hpll_freq = HPLL_FREQ_1600MHZ; + break; + case ATOMISP_PCI_DEVICE_SOC_CHT: + isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 + << ATOMISP_HW_REVISION_SHIFT); + isp->media_dev.hw_revision |= pdev->revision < 2 ? + ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; + + isp->dfs = &dfs_config_cht; + pdev->d3cold_delay = 0; + + iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val); + switch (val & CCK_FUSE_HPLL_FREQ_MASK) { + case 0x00: + isp->hpll_freq = HPLL_FREQ_800MHZ; + break; + case 0x01: + isp->hpll_freq = HPLL_FREQ_1600MHZ; + break; + case 0x02: + isp->hpll_freq = HPLL_FREQ_2000MHZ; + break; + default: + isp->hpll_freq = HPLL_FREQ_1600MHZ; + dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n"); + } + break; + default: + dev_err(&pdev->dev, "un-supported IUNIT device\n"); + err = -ENODEV; + goto atomisp_dev_alloc_fail; + } + + dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq); + + isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY; + + /* Load isp firmware from user space */ + if (!defer_fw_load) { + isp->firmware = atomisp_load_firmware(isp); + if (!isp->firmware) { + err = -ENOENT; + dev_dbg(&pdev->dev, "Firmware load failed\n"); + goto load_fw_fail; + } + + err = sh_css_check_firmware_version(isp->dev, isp->firmware->data); + if (err) { + dev_dbg(&pdev->dev, "Firmware version check failed\n"); + goto fw_validation_fail; + } + } else { + dev_info(&pdev->dev, "Firmware load will be deferred\n"); + } + + pci_set_master(pdev); + + err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); + if (err < 0) { + dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err); + goto enable_msi_fail; + } + + atomisp_msi_irq_init(isp); + + cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); + + /* + * for MRFLD, Software/firmware needs to write a 1 to bit 0 of + * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI + * backend write 0 will enable Arasan CSI backend, which has + * bugs(like sighting:4567697 and 4567699) and will be removed + * in B0 + */ + atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); + + if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) == + ATOMISP_PCI_DEVICE_SOC_MRFLD) { + u32 csi_afe_trim; + + /* + * Workaround for imbalance data eye issue which is observed + * on TNG B0. + */ + pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim); + csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << + MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | + (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << + MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | + (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << + MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT)); + csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << + MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | + (MRFLD_PCI_CSI2_HSRXCLKTRIM << + MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | + (MRFLD_PCI_CSI3_HSRXCLKTRIM << + MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT); + pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim); + } + + err = atomisp_initialize_modules(isp); + if (err < 0) { + dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err); + goto initialize_modules_fail; + } + + err = atomisp_register_entities(isp); + if (err < 0) { + dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err); + goto register_entities_fail; + } + + INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work); + + /* save the iunit context only once after all the values are init'ed. */ + atomisp_save_iunit_reg(isp); + + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_allow(&pdev->dev); + + /* Init ISP memory management */ + hmm_init(); + + err = devm_request_threaded_irq(&pdev->dev, pdev->irq, + atomisp_isr, atomisp_isr_thread, + IRQF_SHARED, "isp_irq", isp); + if (err) { + dev_err(&pdev->dev, "Failed to request irq (%d)\n", err); + goto request_irq_fail; + } + + /* Load firmware into ISP memory */ + if (!defer_fw_load) { + err = atomisp_css_load_firmware(isp); + if (err) { + dev_err(&pdev->dev, "Failed to init css.\n"); + goto css_init_fail; + } + } else { + dev_dbg(&pdev->dev, "Skip css init.\n"); + } + /* Clear FW image from memory */ + release_firmware(isp->firmware); + isp->firmware = NULL; + isp->css_env.isp_css_fw.data = NULL; + + err = atomisp_register_device_nodes(isp); + if (err) + goto css_init_fail; + + atomisp_drvfs_init(isp); + + return 0; + +css_init_fail: + devm_free_irq(&pdev->dev, pdev->irq, isp); +request_irq_fail: + hmm_cleanup(); + pm_runtime_get_noresume(&pdev->dev); + atomisp_unregister_entities(isp); +register_entities_fail: + atomisp_uninitialize_modules(isp); +initialize_modules_fail: + cpu_latency_qos_remove_request(&isp->pm_qos); + atomisp_msi_irq_uninit(isp); + pci_free_irq_vectors(pdev); +enable_msi_fail: +fw_validation_fail: + release_firmware(isp->firmware); +load_fw_fail: + /* + * Switch off ISP, as keeping it powered on would prevent + * reaching S0ix states. + * + * The following lines have been copied from atomisp suspend path + */ + + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); + irq &= BIT(INTR_IIR); + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); + + pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); + irq &= ~BIT(INTR_IER); + pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); + + atomisp_msi_irq_uninit(isp); + + /* Address later when we worry about the ...field chips */ + if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power(isp, false)) + dev_err(&pdev->dev, "Failed to switch off ISP\n"); + +atomisp_dev_alloc_fail: + pcim_iounmap_regions(pdev, BIT(ATOM_ISP_PCI_BAR)); + +ioremap_fail: + return err; +} + +static void atomisp_pci_remove(struct pci_dev *pdev) +{ + struct atomisp_device *isp = pci_get_drvdata(pdev); + + dev_info(&pdev->dev, "Removing atomisp driver\n"); + + atomisp_drvfs_exit(); + + ia_css_unload_firmware(); + hmm_cleanup(); + + pm_runtime_forbid(&pdev->dev); + pm_runtime_get_noresume(&pdev->dev); + cpu_latency_qos_remove_request(&isp->pm_qos); + + atomisp_msi_irq_uninit(isp); + atomisp_unregister_entities(isp); + + release_firmware(isp->firmware); +} + +static const struct pci_device_id atomisp_pci_tbl[] = { + /* Merrifield */ + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)}, + /* Baytrail */ + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)}, + /* Anniedale (Merrifield+ / Moorefield) */ + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)}, + /* Cherrytrail */ + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)}, + {0,} +}; + +MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl); + +static const struct dev_pm_ops atomisp_pm_ops = { + .runtime_suspend = atomisp_power_off, + .runtime_resume = atomisp_power_on, + .suspend = atomisp_suspend, + .resume = atomisp_resume, +}; + +static struct pci_driver atomisp_pci_driver = { + .driver = { + .pm = &atomisp_pm_ops, + }, + .name = "atomisp-isp2", + .id_table = atomisp_pci_tbl, + .probe = atomisp_pci_probe, + .remove = atomisp_pci_remove, +}; + +module_pci_driver(atomisp_pci_driver); + +MODULE_AUTHOR("Wen Wang "); +MODULE_AUTHOR("Xiaolin Zhang "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver"); diff --git a/drivers/staging/media/atomisp/pci/atomisp_v4l2.h b/drivers/staging/media/atomisp/pci/atomisp_v4l2.h new file mode 100644 index 000000000..ccf1c0ac1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp_v4l2.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __ATOMISP_V4L2_H__ +#define __ATOMISP_V4L2_H__ + +struct atomisp_video_pipe; +struct v4l2_device; +struct atomisp_device; +struct firmware; + +int atomisp_video_init(struct atomisp_video_pipe *video, const char *name, + unsigned int run_mode); +void atomisp_video_unregister(struct atomisp_video_pipe *video); +const struct firmware *atomisp_load_firmware(struct atomisp_device *isp); +int atomisp_csi_lane_config(struct atomisp_device *isp); + +#endif /* __ATOMISP_V4L2_H__ */ diff --git a/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf.h b/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf.h new file mode 100644 index 000000000..0579deac5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf.h @@ -0,0 +1,377 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_CIRCBUF_H +#define _IA_CSS_CIRCBUF_H + +#include +#include +#include +#include +#include +#include "ia_css_circbuf_comm.h" +#include "ia_css_circbuf_desc.h" + +/**************************************************************** + * + * Data structures. + * + ****************************************************************/ +/** + * @brief Data structure for the circular buffer. + */ +typedef struct ia_css_circbuf_s ia_css_circbuf_t; +struct ia_css_circbuf_s { + ia_css_circbuf_desc_t *desc; /* Pointer to the descriptor of the circbuf */ + ia_css_circbuf_elem_t *elems; /* an array of elements */ +}; + +/** + * @brief Create the circular buffer. + * + * @param cb The pointer to the circular buffer. + * @param elems An array of elements. + * @param desc The descriptor set to the size using ia_css_circbuf_desc_init(). + */ +void ia_css_circbuf_create( + ia_css_circbuf_t *cb, + ia_css_circbuf_elem_t *elems, + ia_css_circbuf_desc_t *desc); + +/** + * @brief Destroy the circular buffer. + * + * @param cb The pointer to the circular buffer. + */ +void ia_css_circbuf_destroy( + ia_css_circbuf_t *cb); + +/** + * @brief Pop a value out of the circular buffer. + * Get a value at the head of the circular buffer. + * The user should call "ia_css_circbuf_is_empty()" + * to avoid accessing to an empty buffer. + * + * @param cb The pointer to the circular buffer. + * + * @return the pop-out value. + */ +uint32_t ia_css_circbuf_pop( + ia_css_circbuf_t *cb); + +/** + * @brief Extract a value out of the circular buffer. + * Get a value at an arbitrary poistion in the circular + * buffer. The user should call "ia_css_circbuf_is_empty()" + * to avoid accessing to an empty buffer. + * + * @param cb The pointer to the circular buffer. + * @param offset The offset from "start" to the target position. + * + * @return the extracted value. + */ +uint32_t ia_css_circbuf_extract( + ia_css_circbuf_t *cb, + int offset); + +/**************************************************************** + * + * Inline functions. + * + ****************************************************************/ +/** + * @brief Set the "val" field in the element. + * + * @param elem The pointer to the element. + * @param val The value to be set. + */ +static inline void ia_css_circbuf_elem_set_val( + ia_css_circbuf_elem_t *elem, + uint32_t val) +{ + OP___assert(elem); + + elem->val = val; +} + +/** + * @brief Initialize the element. + * + * @param elem The pointer to the element. + */ +static inline void ia_css_circbuf_elem_init( + ia_css_circbuf_elem_t *elem) +{ + OP___assert(elem); + ia_css_circbuf_elem_set_val(elem, 0); +} + +/** + * @brief Copy an element. + * + * @param src The element as the copy source. + * @param dest The element as the copy destination. + */ +static inline void ia_css_circbuf_elem_cpy( + ia_css_circbuf_elem_t *src, + ia_css_circbuf_elem_t *dest) +{ + OP___assert(src); + OP___assert(dest); + + ia_css_circbuf_elem_set_val(dest, src->val); +} + +/** + * @brief Get position in the circular buffer. + * + * @param cb The pointer to the circular buffer. + * @param base The base position. + * @param offset The offset. + * + * @return the position at offset. + */ +static inline uint8_t ia_css_circbuf_get_pos_at_offset( + ia_css_circbuf_t *cb, + u32 base, + int offset) +{ + u8 dest; + + OP___assert(cb); + OP___assert(cb->desc); + OP___assert(cb->desc->size > 0); + + /* step 1: adjudst the offset */ + while (offset < 0) { + offset += cb->desc->size; + } + + /* step 2: shift and round by the upper limit */ + dest = OP_std_modadd(base, offset, cb->desc->size); + + return dest; +} + +/** + * @brief Get the offset between two positions in the circular buffer. + * Get the offset from the source position to the terminal position, + * along the direction in which the new elements come in. + * + * @param cb The pointer to the circular buffer. + * @param src_pos The source position. + * @param dest_pos The terminal position. + * + * @return the offset. + */ +static inline int ia_css_circbuf_get_offset( + ia_css_circbuf_t *cb, + u32 src_pos, + uint32_t dest_pos) +{ + int offset; + + OP___assert(cb); + OP___assert(cb->desc); + + offset = (int)(dest_pos - src_pos); + offset += (offset < 0) ? cb->desc->size : 0; + + return offset; +} + +/** + * @brief Get the maximum number of elements. + * + * @param cb The pointer to the circular buffer. + * + * @return the maximum number of elements. + * + * TODO: Test this API. + */ +static inline uint32_t ia_css_circbuf_get_size( + ia_css_circbuf_t *cb) +{ + OP___assert(cb); + OP___assert(cb->desc); + + return cb->desc->size; +} + +/** + * @brief Get the number of available elements. + * + * @param cb The pointer to the circular buffer. + * + * @return the number of available elements. + */ +static inline uint32_t ia_css_circbuf_get_num_elems( + ia_css_circbuf_t *cb) +{ + int num; + + OP___assert(cb); + OP___assert(cb->desc); + + num = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end); + + return (uint32_t)num; +} + +/** + * @brief Test if the circular buffer is empty. + * + * @param cb The pointer to the circular buffer. + * + * @return + * - true when it is empty. + * - false when it is not empty. + */ +static inline bool ia_css_circbuf_is_empty( + ia_css_circbuf_t *cb) +{ + OP___assert(cb); + OP___assert(cb->desc); + + return ia_css_circbuf_desc_is_empty(cb->desc); +} + +/** + * @brief Test if the circular buffer is full. + * + * @param cb The pointer to the circular buffer. + * + * @return + * - true when it is full. + * - false when it is not full. + */ +static inline bool ia_css_circbuf_is_full(ia_css_circbuf_t *cb) +{ + OP___assert(cb); + OP___assert(cb->desc); + + return ia_css_circbuf_desc_is_full(cb->desc); +} + +/** + * @brief Write a new element into the circular buffer. + * Write a new element WITHOUT checking whether the + * circular buffer is full or not. So it also overwrites + * the oldest element when the buffer is full. + * + * @param cb The pointer to the circular buffer. + * @param elem The new element. + */ +static inline void ia_css_circbuf_write( + ia_css_circbuf_t *cb, + ia_css_circbuf_elem_t elem) +{ + OP___assert(cb); + OP___assert(cb->desc); + + /* Cannot continue as the queue is full*/ + assert(!ia_css_circbuf_is_full(cb)); + + ia_css_circbuf_elem_cpy(&elem, &cb->elems[cb->desc->end]); + + cb->desc->end = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->end, 1); +} + +/** + * @brief Push a value in the circular buffer. + * Put a new value at the tail of the circular buffer. + * The user should call "ia_css_circbuf_is_full()" + * to avoid accessing to a full buffer. + * + * @param cb The pointer to the circular buffer. + * @param val The value to be pushed in. + */ +static inline void ia_css_circbuf_push( + ia_css_circbuf_t *cb, + uint32_t val) +{ + ia_css_circbuf_elem_t elem; + + OP___assert(cb); + + /* set up an element */ + ia_css_circbuf_elem_init(&elem); + ia_css_circbuf_elem_set_val(&elem, val); + + /* write the element into the buffer */ + ia_css_circbuf_write(cb, elem); +} + +/** + * @brief Get the number of free elements. + * + * @param cb The pointer to the circular buffer. + * + * @return: The number of free elements. + */ +static inline uint32_t ia_css_circbuf_get_free_elems( + ia_css_circbuf_t *cb) +{ + OP___assert(cb); + OP___assert(cb->desc); + + return ia_css_circbuf_desc_get_free_elems(cb->desc); +} + +/** + * @brief Peek an element in Circular Buffer. + * + * @param cb The pointer to the circular buffer. + * @param offset Offset to the element. + * + * @return the elements value. + */ +uint32_t ia_css_circbuf_peek( + ia_css_circbuf_t *cb, + int offset); + +/** + * @brief Get an element in Circular Buffer. + * + * @param cb The pointer to the circular buffer. + * @param offset Offset to the element. + * + * @return the elements value. + */ +uint32_t ia_css_circbuf_peek_from_start( + ia_css_circbuf_t *cb, + int offset); + +/** + * @brief Increase Size of a Circular Buffer. + * Use 'CAUTION' before using this function, This was added to + * support / fix issue with increasing size for tagger only + * + * @param cb The pointer to the circular buffer. + * @param sz_delta delta increase for new size + * @param elems (optional) pointers to new additional elements + * cb element array size will not be increased dynamically, + * but new elements should be added at the end to existing + * cb element array which if of max_size >= new size + * + * @return true on successfully increasing the size + * false on failure + */ +bool ia_css_circbuf_increase_size( + ia_css_circbuf_t *cb, + unsigned int sz_delta, + ia_css_circbuf_elem_t *elems); + +#endif /*_IA_CSS_CIRCBUF_H */ diff --git a/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_comm.h b/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_comm.h new file mode 100644 index 000000000..6fa6da859 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_comm.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_CIRCBUF_COMM_H +#define _IA_CSS_CIRCBUF_COMM_H + +#include /* uint8_t, uint32_t */ + +#define IA_CSS_CIRCBUF_PADDING 1 /* The circular buffer is implemented in lock-less manner, wherein + * the head and tail can advance independently without any locks. + * But to achieve this, an extra buffer element is required to detect + * queue full & empty conditions, wherein the tail trails the head for + * full and is equal to head for empty condition. This causes 1 buffer + * not being available for use. + */ + +/**************************************************************** + * + * Portable Data structures + * + ****************************************************************/ +/** + * @brief Data structure for the circular descriptor. + */ +typedef struct ia_css_circbuf_desc_s ia_css_circbuf_desc_t; +struct ia_css_circbuf_desc_s { + u8 size; /* the maximum number of elements*/ + u8 step; /* number of bytes per element */ + u8 start; /* index of the oldest element */ + u8 end; /* index at which to write the new element */ +}; + +#define SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT \ + (4 * sizeof(uint8_t)) + +/** + * @brief Data structure for the circular buffer element. + */ +typedef struct ia_css_circbuf_elem_s ia_css_circbuf_elem_t; +struct ia_css_circbuf_elem_s { + u32 val; /* the value stored in the element */ +}; + +#define SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT \ + (sizeof(uint32_t)) + +#endif /*_IA_CSS_CIRCBUF_COMM_H*/ diff --git a/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_desc.h b/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_desc.h new file mode 100644 index 000000000..1071813a2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_desc.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_CIRCBUF_DESC_H_ +#define _IA_CSS_CIRCBUF_DESC_H_ + +#include +#include +#include +#include +#include "ia_css_circbuf_comm.h" +/**************************************************************** + * + * Inline functions. + * + ****************************************************************/ +/** + * @brief Test if the circular buffer is empty. + * + * @param cb_desc The pointer to the circular buffer descriptor. + * + * @return + * - true when it is empty. + * - false when it is not empty. + */ +static inline bool ia_css_circbuf_desc_is_empty( + ia_css_circbuf_desc_t *cb_desc) +{ + OP___assert(cb_desc); + return (cb_desc->end == cb_desc->start); +} + +/** + * @brief Test if the circular buffer descriptor is full. + * + * @param cb_desc The pointer to the circular buffer + * descriptor. + * + * @return + * - true when it is full. + * - false when it is not full. + */ +static inline bool ia_css_circbuf_desc_is_full( + ia_css_circbuf_desc_t *cb_desc) +{ + OP___assert(cb_desc); + return (OP_std_modadd(cb_desc->end, 1, cb_desc->size) == cb_desc->start); +} + +/** + * @brief Initialize the circular buffer descriptor + * + * @param cb_desc The pointer circular buffer descriptor + * @param size The size of the circular buffer + */ +static inline void ia_css_circbuf_desc_init( + ia_css_circbuf_desc_t *cb_desc, + int8_t size) +{ + OP___assert(cb_desc); + cb_desc->size = size; +} + +/** + * @brief Get a position in the circular buffer descriptor. + * + * @param cb The pointer to the circular buffer descriptor. + * @param base The base position. + * @param offset The offset. + * + * @return the position in the circular buffer descriptor. + */ +static inline uint8_t ia_css_circbuf_desc_get_pos_at_offset( + ia_css_circbuf_desc_t *cb_desc, + u32 base, + int offset) +{ + u8 dest; + + OP___assert(cb_desc); + OP___assert(cb_desc->size > 0); + + /* step 1: adjust the offset */ + while (offset < 0) { + offset += cb_desc->size; + } + + /* step 2: shift and round by the upper limit */ + dest = OP_std_modadd(base, offset, cb_desc->size); + + return dest; +} + +/** + * @brief Get the offset between two positions in the circular buffer + * descriptor. + * Get the offset from the source position to the terminal position, + * along the direction in which the new elements come in. + * + * @param cb_desc The pointer to the circular buffer descriptor. + * @param src_pos The source position. + * @param dest_pos The terminal position. + * + * @return the offset. + */ +static inline int ia_css_circbuf_desc_get_offset( + ia_css_circbuf_desc_t *cb_desc, + u32 src_pos, + uint32_t dest_pos) +{ + int offset; + + OP___assert(cb_desc); + + offset = (int)(dest_pos - src_pos); + offset += (offset < 0) ? cb_desc->size : 0; + + return offset; +} + +/** + * @brief Get the number of available elements. + * + * @param cb_desc The pointer to the circular buffer. + * + * @return The number of available elements. + */ +static inline uint32_t ia_css_circbuf_desc_get_num_elems( + ia_css_circbuf_desc_t *cb_desc) +{ + int num; + + OP___assert(cb_desc); + + num = ia_css_circbuf_desc_get_offset(cb_desc, + cb_desc->start, + cb_desc->end); + + return (uint32_t)num; +} + +/** + * @brief Get the number of free elements. + * + * @param cb_desc The pointer to the circular buffer descriptor. + * + * @return: The number of free elements. + */ +static inline uint32_t ia_css_circbuf_desc_get_free_elems( + ia_css_circbuf_desc_t *cb_desc) +{ + u32 num; + + OP___assert(cb_desc); + + num = ia_css_circbuf_desc_get_offset(cb_desc, + cb_desc->start, + cb_desc->end); + + return (cb_desc->size - num); +} +#endif /*_IA_CSS_CIRCBUF_DESC_H_ */ diff --git a/drivers/staging/media/atomisp/pci/base/circbuf/src/circbuf.c b/drivers/staging/media/atomisp/pci/base/circbuf/src/circbuf.c new file mode 100644 index 000000000..d9f7c1437 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/base/circbuf/src/circbuf.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_circbuf.h" + +#include + +/********************************************************************** + * + * Forward declarations. + * + **********************************************************************/ +/* + * @brief Read the oldest element from the circular buffer. + * Read the oldest element WITHOUT checking whehter the + * circular buffer is empty or not. The oldest element is + * also removed out from the circular buffer. + * + * @param cb The pointer to the circular buffer. + * + * @return the oldest element. + */ +static inline ia_css_circbuf_elem_t +ia_css_circbuf_read(ia_css_circbuf_t *cb); + +/* + * @brief Shift a chunk of elements in the circular buffer. + * A chunk of elements (i.e. the ones from the "start" position + * to the "chunk_src" position) are shifted in the circular buffer, + * along the direction of new elements coming. + * + * @param cb The pointer to the circular buffer. + * @param chunk_src The position at which the first element in the chunk is. + * @param chunk_dest The position to which the first element in the chunk would be shift. + */ +static inline void ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb, + u32 chunk_src, + uint32_t chunk_dest); + +/* + * @brief Get the "val" field in the element. + * + * @param elem The pointer to the element. + * + * @return the "val" field. + */ +static inline uint32_t +ia_css_circbuf_elem_get_val(ia_css_circbuf_elem_t *elem); + +/********************************************************************** + * + * Non-inline functions. + * + **********************************************************************/ +/* + * @brief Create the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +void +ia_css_circbuf_create(ia_css_circbuf_t *cb, + ia_css_circbuf_elem_t *elems, + ia_css_circbuf_desc_t *desc) +{ + u32 i; + + OP___assert(desc); + + cb->desc = desc; + /* Initialize to defaults */ + cb->desc->start = 0; + cb->desc->end = 0; + cb->desc->step = 0; + + for (i = 0; i < cb->desc->size; i++) + ia_css_circbuf_elem_init(&elems[i]); + + cb->elems = elems; +} + +/* + * @brief Destroy the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +void ia_css_circbuf_destroy(ia_css_circbuf_t *cb) +{ + cb->desc = NULL; + + cb->elems = NULL; +} + +/* + * @brief Pop a value out of the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +uint32_t ia_css_circbuf_pop(ia_css_circbuf_t *cb) +{ + u32 ret; + ia_css_circbuf_elem_t elem; + + assert(!ia_css_circbuf_is_empty(cb)); + + /* read an element from the buffer */ + elem = ia_css_circbuf_read(cb); + ret = ia_css_circbuf_elem_get_val(&elem); + return ret; +} + +/* + * @brief Extract a value out of the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +uint32_t ia_css_circbuf_extract(ia_css_circbuf_t *cb, int offset) +{ + int max_offset; + u32 val; + u32 pos; + u32 src_pos; + u32 dest_pos; + + /* get the maximum offest */ + max_offset = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end); + max_offset--; + + /* + * Step 1: When the target element is at the "start" position. + */ + if (offset == 0) { + val = ia_css_circbuf_pop(cb); + return val; + } + + /* + * Step 2: When the target element is out of the range. + */ + if (offset > max_offset) { + val = 0; + return val; + } + + /* + * Step 3: When the target element is between the "start" and + * "end" position. + */ + /* get the position of the target element */ + pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, offset); + + /* get the value from the target element */ + val = ia_css_circbuf_elem_get_val(&cb->elems[pos]); + + /* shift the elements */ + src_pos = ia_css_circbuf_get_pos_at_offset(cb, pos, -1); + dest_pos = pos; + ia_css_circbuf_shift_chunk(cb, src_pos, dest_pos); + + return val; +} + +/* + * @brief Peek an element from the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +uint32_t ia_css_circbuf_peek(ia_css_circbuf_t *cb, int offset) +{ + int pos; + + pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->end, offset); + + /* get the value at the position */ + return cb->elems[pos].val; +} + +/* + * @brief Get the value of an element from the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +uint32_t ia_css_circbuf_peek_from_start(ia_css_circbuf_t *cb, int offset) +{ + int pos; + + pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, offset); + + /* get the value at the position */ + return cb->elems[pos].val; +} + +/* @brief increase size of a circular buffer. + * Use 'CAUTION' before using this function. This was added to + * support / fix issue with increasing size for tagger only + * Please refer to "ia_css_circbuf.h" for details. + */ +bool ia_css_circbuf_increase_size( + ia_css_circbuf_t *cb, + unsigned int sz_delta, + ia_css_circbuf_elem_t *elems) +{ + u8 curr_size; + u8 curr_end; + unsigned int i = 0; + + if (!cb || sz_delta == 0) + return false; + + curr_size = cb->desc->size; + curr_end = cb->desc->end; + /* We assume cb was pre defined as global to allow + * increase in size */ + /* FM: are we sure this cannot cause size to become too big? */ + if (((uint8_t)(cb->desc->size + (uint8_t)sz_delta) > cb->desc->size) && + ((uint8_t)sz_delta == sz_delta)) + cb->desc->size += (uint8_t)sz_delta; + else + return false; /* overflow in size */ + + /* If elems are passed update them else we assume its been taken + * care before calling this function */ + if (elems) { + /* cb element array size will not be increased dynamically, + * but pointers to new elements can be added at the end + * of existing pre defined cb element array of + * size >= new size if not already added */ + for (i = curr_size; i < cb->desc->size; i++) + cb->elems[i] = elems[i - curr_size]; + } + /* Fix Start / End */ + if (curr_end < cb->desc->start) { + if (curr_end == 0) { + /* Easily fix End */ + cb->desc->end = curr_size; + } else { + /* Move elements and fix Start*/ + ia_css_circbuf_shift_chunk(cb, + curr_size - 1, + curr_size + sz_delta - 1); + } + } + + return true; +} + +/**************************************************************** + * + * Inline functions. + * + ****************************************************************/ +/* + * @brief Get the "val" field in the element. + * Refer to "Forward declarations" for details. + */ +static inline uint32_t +ia_css_circbuf_elem_get_val(ia_css_circbuf_elem_t *elem) +{ + return elem->val; +} + +/* + * @brief Read the oldest element from the circular buffer. + * Refer to "Forward declarations" for details. + */ +static inline ia_css_circbuf_elem_t +ia_css_circbuf_read(ia_css_circbuf_t *cb) +{ + ia_css_circbuf_elem_t elem; + + /* get the element from the target position */ + elem = cb->elems[cb->desc->start]; + + /* clear the target position */ + ia_css_circbuf_elem_init(&cb->elems[cb->desc->start]); + + /* adjust the "start" position */ + cb->desc->start = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, 1); + return elem; +} + +/* + * @brief Shift a chunk of elements in the circular buffer. + * Refer to "Forward declarations" for details. + */ +static inline void +ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb, + u32 chunk_src, uint32_t chunk_dest) +{ + int chunk_offset; + int chunk_sz; + int i; + + /* get the chunk offset and size */ + chunk_offset = ia_css_circbuf_get_offset(cb, + chunk_src, chunk_dest); + chunk_sz = ia_css_circbuf_get_offset(cb, cb->desc->start, chunk_src) + 1; + + /* shift each element to its terminal position */ + for (i = 0; i < chunk_sz; i++) { + /* copy the element from the source to the destination */ + ia_css_circbuf_elem_cpy(&cb->elems[chunk_src], + &cb->elems[chunk_dest]); + + /* clear the source position */ + ia_css_circbuf_elem_init(&cb->elems[chunk_src]); + + /* adjust the source/terminal positions */ + chunk_src = ia_css_circbuf_get_pos_at_offset(cb, chunk_src, -1); + chunk_dest = ia_css_circbuf_get_pos_at_offset(cb, chunk_dest, -1); + } + + /* adjust the index "start" */ + cb->desc->start = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, + chunk_offset); +} diff --git a/drivers/staging/media/atomisp/pci/base/refcount/interface/ia_css_refcount.h b/drivers/staging/media/atomisp/pci/base/refcount/interface/ia_css_refcount.h new file mode 100644 index 000000000..78cf0cbfb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/base/refcount/interface/ia_css_refcount.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_REFCOUNT_H_ +#define _IA_CSS_REFCOUNT_H_ + +#include +#include +#include +#include + +typedef void (*clear_func)(ia_css_ptr ptr); + +/*! \brief Function for initializing refcount list + * + * \param[in] size Size of the refcount list. + * \return ia_css_err + */ +int ia_css_refcount_init(uint32_t size); + +/*! \brief Function for de-initializing refcount list + * + * \return None + */ +void ia_css_refcount_uninit(void); + +/*! \brief Function for increasing reference by 1. + * + * \param[in] id ID of the object. + * \param[in] ptr Data of the object (ptr). + * \return ia_css_ptr (saved address) + */ +ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr); + +/*! \brief Function for decrease reference by 1. + * + * \param[in] id ID of the object. + * \param[in] ptr Data of the object (ptr). + * + * - true, if it is successful. + * - false, otherwise. + */ +bool ia_css_refcount_decrement(s32 id, ia_css_ptr ptr); + +/*! \brief Function to check if reference count is 1. + * + * \param[in] ptr Data of the object (ptr). + * + * - true, if it is successful. + * - false, otherwise. + */ +bool ia_css_refcount_is_single(ia_css_ptr ptr); + +/*! \brief Function to clear reference list objects. + * + * \param[in] id ID of the object. + * \param[in] clear_func function to be run to free reference objects. + * + * return None + */ +void ia_css_refcount_clear(s32 id, + clear_func clear_func_ptr); + +/*! \brief Function to verify if object is valid + * + * \param[in] ptr Data of the object (ptr) + * + * - true, if valid + * - false, if invalid + */ +bool ia_css_refcount_is_valid(ia_css_ptr ptr); + +#endif /* _IA_CSS_REFCOUNT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/base/refcount/src/refcount.c b/drivers/staging/media/atomisp/pci/base/refcount/src/refcount.c new file mode 100644 index 000000000..a9c881631 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/base/refcount/src/refcount.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include "ia_css_refcount.h" +#include "sh_css_defs.h" + +#include "platform_support.h" + +#include "assert_support.h" + +#include "ia_css_debug.h" + +/* TODO: enable for other memory aswell + now only for ia_css_ptr */ +struct ia_css_refcount_entry { + u32 count; + ia_css_ptr data; + s32 id; +}; + +struct ia_css_refcount_list { + u32 size; + struct ia_css_refcount_entry *items; +}; + +static struct ia_css_refcount_list myrefcount; + +static struct ia_css_refcount_entry *refcount_find_entry(ia_css_ptr ptr, + bool firstfree) +{ + u32 i; + + if (ptr == 0) + return NULL; + if (!myrefcount.items) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "%s(): Ref count not initialized!\n", __func__); + return NULL; + } + + for (i = 0; i < myrefcount.size; i++) { + if ((&myrefcount.items[i])->data == 0) { + if (firstfree) { + /* for new entry */ + return &myrefcount.items[i]; + } + } + if ((&myrefcount.items[i])->data == ptr) { + /* found entry */ + return &myrefcount.items[i]; + } + } + return NULL; +} + +int ia_css_refcount_init(uint32_t size) +{ + int err = 0; + + if (size == 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s(): Size of 0 for Ref count init!\n", __func__); + return -EINVAL; + } + if (myrefcount.items) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s(): Ref count is already initialized\n", __func__); + return -EINVAL; + } + myrefcount.items = + kvmalloc(sizeof(struct ia_css_refcount_entry) * size, GFP_KERNEL); + if (!myrefcount.items) + err = -ENOMEM; + if (!err) { + memset(myrefcount.items, 0, + sizeof(struct ia_css_refcount_entry) * size); + myrefcount.size = size; + } + return err; +} + +void ia_css_refcount_uninit(void) +{ + struct ia_css_refcount_entry *entry; + u32 i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s() entry\n", __func__); + for (i = 0; i < myrefcount.size; i++) { + /* driver verifier tool has issues with &arr[i] + and prefers arr + i; as these are actually equivalent + the line below uses + i + */ + entry = myrefcount.items + i; + if (entry->data != mmgr_NULL) { + /* ia_css_debug_dtrace(IA_CSS_DBG_TRACE, + "ia_css_refcount_uninit: freeing (%x)\n", + entry->data);*/ + hmm_free(entry->data); + entry->data = mmgr_NULL; + entry->count = 0; + entry->id = 0; + } + } + kvfree(myrefcount.items); + myrefcount.items = NULL; + myrefcount.size = 0; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s() leave\n", __func__); +} + +ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr) +{ + struct ia_css_refcount_entry *entry; + + if (ptr == mmgr_NULL) + return ptr; + + entry = refcount_find_entry(ptr, false); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s(%x) 0x%x\n", __func__, id, ptr); + + if (!entry) { + entry = refcount_find_entry(ptr, true); + assert(entry); + if (!entry) + return mmgr_NULL; + entry->id = id; + } + + if (entry->id != id) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "%s(): Ref count IDS do not match!\n", __func__); + return mmgr_NULL; + } + + if (entry->data == ptr) + entry->count += 1; + else if (entry->data == mmgr_NULL) { + entry->data = ptr; + entry->count = 1; + } else + return mmgr_NULL; + + return ptr; +} + +bool ia_css_refcount_decrement(s32 id, ia_css_ptr ptr) +{ + struct ia_css_refcount_entry *entry; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s(%x) 0x%x\n", __func__, id, ptr); + + if (ptr == mmgr_NULL) + return false; + + entry = refcount_find_entry(ptr, false); + + if (entry) { + if (entry->id != id) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "%s(): Ref count IDS do not match!\n", __func__); + return false; + } + if (entry->count > 0) { + entry->count -= 1; + if (entry->count == 0) { + /* ia_css_debug_dtrace(IA_CSS_DBEUG_TRACE, + "ia_css_refcount_decrement: freeing\n");*/ + hmm_free(ptr); + entry->data = mmgr_NULL; + entry->id = 0; + } + return true; + } + } + + /* SHOULD NOT HAPPEN: ptr not managed by refcount, or not + valid anymore */ + if (entry) + IA_CSS_ERROR("id %x, ptr 0x%x entry %p entry->id %x entry->count %d\n", + id, ptr, entry, entry->id, entry->count); + else + IA_CSS_ERROR("entry NULL\n"); + assert(false); + + return false; +} + +bool ia_css_refcount_is_single(ia_css_ptr ptr) +{ + struct ia_css_refcount_entry *entry; + + if (ptr == mmgr_NULL) + return false; + + entry = refcount_find_entry(ptr, false); + + if (entry) + return (entry->count == 1); + + return true; +} + +void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr) +{ + struct ia_css_refcount_entry *entry; + u32 i; + u32 count = 0; + + assert(clear_func_ptr); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s(%x)\n", + __func__, id); + + for (i = 0; i < myrefcount.size; i++) { + /* driver verifier tool has issues with &arr[i] + and prefers arr + i; as these are actually equivalent + the line below uses + i + */ + entry = myrefcount.items + i; + if ((entry->data != mmgr_NULL) && (entry->id == id)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s: %x: 0x%x\n", __func__, + id, entry->data); + if (clear_func_ptr) { + /* clear using provided function */ + clear_func_ptr(entry->data); + } else { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s: using hmm_free: no clear_func\n", __func__); + hmm_free(entry->data); + } + + if (entry->count != 0) { + IA_CSS_WARNING("Ref count for entry %x is not zero!", entry->id); + } + + assert(entry->count == 0); + + entry->data = mmgr_NULL; + entry->count = 0; + entry->id = 0; + count++; + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "%s(%x): cleared %d\n", __func__, id, + count); +} + +bool ia_css_refcount_is_valid(ia_css_ptr ptr) +{ + struct ia_css_refcount_entry *entry; + + if (ptr == mmgr_NULL) + return false; + + entry = refcount_find_entry(ptr, false); + + return entry; +} diff --git a/drivers/staging/media/atomisp/pci/bits.h b/drivers/staging/media/atomisp/pci/bits.h new file mode 100644 index 000000000..9fab02ebd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/bits.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_BITS_H +#define _HRT_BITS_H + +#include "defs.h" + +#define _hrt_ones(n) HRTCAT(_hrt_ones_, n) +#define _hrt_ones_0x0 0x00000000U +#define _hrt_ones_0x1 0x00000001U +#define _hrt_ones_0x2 0x00000003U +#define _hrt_ones_0x3 0x00000007U +#define _hrt_ones_0x4 0x0000000FU +#define _hrt_ones_0x5 0x0000001FU +#define _hrt_ones_0x6 0x0000003FU +#define _hrt_ones_0x7 0x0000007FU +#define _hrt_ones_0x8 0x000000FFU +#define _hrt_ones_0x9 0x000001FFU +#define _hrt_ones_0xA 0x000003FFU +#define _hrt_ones_0xB 0x000007FFU +#define _hrt_ones_0xC 0x00000FFFU +#define _hrt_ones_0xD 0x00001FFFU +#define _hrt_ones_0xE 0x00003FFFU +#define _hrt_ones_0xF 0x00007FFFU +#define _hrt_ones_0x10 0x0000FFFFU +#define _hrt_ones_0x11 0x0001FFFFU +#define _hrt_ones_0x12 0x0003FFFFU +#define _hrt_ones_0x13 0x0007FFFFU +#define _hrt_ones_0x14 0x000FFFFFU +#define _hrt_ones_0x15 0x001FFFFFU +#define _hrt_ones_0x16 0x003FFFFFU +#define _hrt_ones_0x17 0x007FFFFFU +#define _hrt_ones_0x18 0x00FFFFFFU +#define _hrt_ones_0x19 0x01FFFFFFU +#define _hrt_ones_0x1A 0x03FFFFFFU +#define _hrt_ones_0x1B 0x07FFFFFFU +#define _hrt_ones_0x1C 0x0FFFFFFFU +#define _hrt_ones_0x1D 0x1FFFFFFFU +#define _hrt_ones_0x1E 0x3FFFFFFFU +#define _hrt_ones_0x1F 0x7FFFFFFFU +#define _hrt_ones_0x20 0xFFFFFFFFU + +#define _hrt_ones_0 _hrt_ones_0x0 +#define _hrt_ones_1 _hrt_ones_0x1 +#define _hrt_ones_2 _hrt_ones_0x2 +#define _hrt_ones_3 _hrt_ones_0x3 +#define _hrt_ones_4 _hrt_ones_0x4 +#define _hrt_ones_5 _hrt_ones_0x5 +#define _hrt_ones_6 _hrt_ones_0x6 +#define _hrt_ones_7 _hrt_ones_0x7 +#define _hrt_ones_8 _hrt_ones_0x8 +#define _hrt_ones_9 _hrt_ones_0x9 +#define _hrt_ones_10 _hrt_ones_0xA +#define _hrt_ones_11 _hrt_ones_0xB +#define _hrt_ones_12 _hrt_ones_0xC +#define _hrt_ones_13 _hrt_ones_0xD +#define _hrt_ones_14 _hrt_ones_0xE +#define _hrt_ones_15 _hrt_ones_0xF +#define _hrt_ones_16 _hrt_ones_0x10 +#define _hrt_ones_17 _hrt_ones_0x11 +#define _hrt_ones_18 _hrt_ones_0x12 +#define _hrt_ones_19 _hrt_ones_0x13 +#define _hrt_ones_20 _hrt_ones_0x14 +#define _hrt_ones_21 _hrt_ones_0x15 +#define _hrt_ones_22 _hrt_ones_0x16 +#define _hrt_ones_23 _hrt_ones_0x17 +#define _hrt_ones_24 _hrt_ones_0x18 +#define _hrt_ones_25 _hrt_ones_0x19 +#define _hrt_ones_26 _hrt_ones_0x1A +#define _hrt_ones_27 _hrt_ones_0x1B +#define _hrt_ones_28 _hrt_ones_0x1C +#define _hrt_ones_29 _hrt_ones_0x1D +#define _hrt_ones_30 _hrt_ones_0x1E +#define _hrt_ones_31 _hrt_ones_0x1F +#define _hrt_ones_32 _hrt_ones_0x20 + +#define _hrt_mask(b, n) \ + (_hrt_ones(n) << (b)) +#define _hrt_get_bits(w, b, n) \ + (((w) >> (b)) & _hrt_ones(n)) +#define _hrt_set_bits(w, b, n, v) \ + (((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b))) +#define _hrt_get_bit(w, b) \ + (((w) >> (b)) & 1) +#define _hrt_set_bit(w, b, v) \ + (((w) & (~(1 << (b)))) | (((v) & 1) << (b))) +#define _hrt_set_lower_half(w, v) \ + _hrt_set_bits(w, 0, 16, v) +#define _hrt_set_upper_half(w, v) \ + _hrt_set_bits(w, 16, 16, v) + +#endif /* _HRT_BITS_H */ diff --git a/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_binarydesc.h b/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_binarydesc.h new file mode 100644 index 000000000..e42eeaeb3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_binarydesc.h @@ -0,0 +1,295 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_BINARYDESC_H__ +#define __IA_CSS_PIPE_BINARYDESC_H__ + +#include + +#include /* ia_css_pipe */ +#include /* ia_css_frame_info */ +#include /* ia_css_binary_descr */ + +/* @brief Get a binary descriptor for copy. + * + * @param[in] pipe + * @param[out] copy_desc + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return None + * + */ +void ia_css_pipe_get_copy_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *copy_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/* @brief Get a binary descriptor for vfpp. + * + * @param[in] pipe + * @param[out] vfpp_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +void ia_css_pipe_get_vfpp_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *vf_pp_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/* @brief Get numerator and denominator of bayer downscaling factor. + * + * @param[in] bds_factor: The bayer downscaling factor. + * (= The bds_factor member in the sh_css_bds_factor structure.) + * @param[out] bds: The rational fraction of the bayer downscaling factor. + * (= The respective member in the sh_css_bds_factor structure.) + * @return 0 or error code upon error. + * + */ +int sh_css_bds_factor_get_fract(unsigned int bds_factor, struct u32_fract *bds); + +/* @brief Get a binary descriptor for preview stage. + * + * @param[in] pipe + * @param[out] preview_descr + * @param[in/out] in_info + * @param[in/out] bds_out_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return 0 or error code upon error. + * + */ +int ia_css_pipe_get_preview_binarydesc( + struct ia_css_pipe *const pipe, + struct ia_css_binary_descr *preview_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *bds_out_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/* @brief Get a binary descriptor for video stage. + * + * @param[in/out] pipe + * @param[out] video_descr + * @param[in/out] in_info + * @param[in/out] bds_out_info + * @param[in/out] vf_info + * @return 0 or error code upon error. + * + */ +int ia_css_pipe_get_video_binarydesc( + struct ia_css_pipe *const pipe, + struct ia_css_binary_descr *video_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *bds_out_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + int stream_config_left_padding); + +/* @brief Get a binary descriptor for yuv scaler stage. + * + * @param[in/out] pipe + * @param[out] yuv_scaler_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] internal_out_info + * @param[in/out] vf_info + * @return None + * + */ +void ia_css_pipe_get_yuvscaler_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *yuv_scaler_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *internal_out_info, + struct ia_css_frame_info *vf_info); + +/* @brief Get a binary descriptor for capture pp stage. + * + * @param[in/out] pipe + * @param[out] capture_pp_descr + * @param[in/out] in_info + * @param[in/out] vf_info + * @return None + * + */ +void ia_css_pipe_get_capturepp_binarydesc( + struct ia_css_pipe *const pipe, + struct ia_css_binary_descr *capture_pp_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/* @brief Get a binary descriptor for primary capture. + * + * @param[in] pipe + * @param[out] prim_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return None + * + */ +void ia_css_pipe_get_primary_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *prim_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + unsigned int stage_idx); + +/* @brief Get a binary descriptor for pre gdc stage. + * + * @param[in] pipe + * @param[out] pre_gdc_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +void ia_css_pipe_get_pre_gdc_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/* @brief Get a binary descriptor for gdc stage. + * + * @param[in] pipe + * @param[out] gdc_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +void ia_css_pipe_get_gdc_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/* @brief Get a binary descriptor for post gdc. + * + * @param[in] pipe + * @param[out] post_gdc_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return None + * + */ +void ia_css_pipe_get_post_gdc_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *post_gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/* @brief Get a binary descriptor for de. + * + * @param[in] pipe + * @param[out] pre_de_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +void ia_css_pipe_get_pre_de_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *pre_de_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/* @brief Get a binary descriptor for pre anr stage. + * + * @param[in] pipe + * @param[out] pre_anr_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +void ia_css_pipe_get_pre_anr_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *pre_anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/* @brief Get a binary descriptor for ANR stage. + * + * @param[in] pipe + * @param[out] anr_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +void ia_css_pipe_get_anr_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/* @brief Get a binary descriptor for post anr stage. + * + * @param[in] pipe + * @param[out] post_anr_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return None + * + */ +void ia_css_pipe_get_post_anr_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *post_anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/* @brief Get a binary descriptor for ldc stage. + * + * @param[in/out] pipe + * @param[out] capture_pp_descr + * @param[in/out] in_info + * @param[in/out] vf_info + * @return None + * + */ +void ia_css_pipe_get_ldc_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *ldc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/* @brief Calculates the required BDS factor + * + * @param[in] input_res + * @param[in] output_res + * @param[in/out] bds_factor + * @return 0 or error code upon error. + */ +int binarydesc_calculate_bds_factor( + struct ia_css_resolution input_res, + struct ia_css_resolution output_res, + unsigned int *bds_factor); + +#endif /* __IA_CSS_PIPE_BINARYDESC_H__ */ diff --git a/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_stagedesc.h b/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_stagedesc.h new file mode 100644 index 000000000..7a0c988d8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_stagedesc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_STAGEDESC_H__ +#define __IA_CSS_PIPE_STAGEDESC_H__ + +#include /* ia_css_fw_info */ +#include +#include +#include "ia_css_pipeline.h" +#include "ia_css_pipeline_common.h" + +void ia_css_pipe_get_generic_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_frame *out_frame[], + struct ia_css_frame *in_frame, + struct ia_css_frame *vf_frame); + +void ia_css_pipe_get_firmwares_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_frame *out_frame[], + struct ia_css_frame *in_frame, + struct ia_css_frame *vf_frame, + const struct ia_css_fw_info *fw, + unsigned int mode); + +void ia_css_pipe_get_sp_func_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_frame *out_frame, + enum ia_css_pipeline_stage_sp_func sp_func, + unsigned int max_input_width); + +#endif /*__IA_CSS_PIPE_STAGEDESC__H__ */ diff --git a/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_util.h b/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_util.h new file mode 100644 index 000000000..c23d1bd91 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/camera/pipe/interface/ia_css_pipe_util.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_UTIL_H__ +#define __IA_CSS_PIPE_UTIL_H__ + +#include +#include + +/* @brief Get Input format bits per pixel based on stream configuration of this + * pipe. + * + * @param[in] pipe + * @return bits per pixel for the underlying stream + * + */ +unsigned int ia_css_pipe_util_pipe_input_format_bpp( + const struct ia_css_pipe *const pipe); + +void ia_css_pipe_util_create_output_frames( + struct ia_css_frame *frames[]); + +void ia_css_pipe_util_set_output_frames( + struct ia_css_frame *frames[], + unsigned int idx, + struct ia_css_frame *frame); + +#endif /* __IA_CSS_PIPE_UTIL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_binarydesc.c b/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_binarydesc.c new file mode 100644 index 000000000..06664ce75 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_binarydesc.c @@ -0,0 +1,844 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include "ia_css_pipe_binarydesc.h" +#include "ia_css_frame_format.h" +#include "ia_css_pipe.h" +#include "ia_css_pipe_util.h" +#include "ia_css_util.h" +#include "ia_css_debug.h" +#include "sh_css_params.h" +#include +/* HRT_GDC_N */ +#include "gdc_device.h" + +/* This module provides a binary descriptions to used to find a binary. Since, + * every stage is associated with a binary, it implicity helps stage + * description. Apart from providing a binary description, this module also + * populates the frame info's when required.*/ + +/* Generic descriptor for offline binaries. Internal function. */ +static void pipe_binarydesc_get_offline( + struct ia_css_pipe const *const pipe, + const int mode, + struct ia_css_binary_descr *descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info[], + struct ia_css_frame_info *vf_info) +{ + unsigned int i; + /* in_info, out_info, vf_info can be NULL */ + assert(pipe); + assert(descr); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "pipe_binarydesc_get_offline() enter:\n"); + + descr->mode = mode; + descr->online = false; + descr->continuous = pipe->stream->config.continuous; + descr->striped = false; + descr->two_ppc = false; + descr->enable_yuv_ds = false; + descr->enable_high_speed = false; + descr->enable_dvs_6axis = false; + descr->enable_reduced_pipe = false; + descr->enable_dz = true; + descr->enable_xnr = false; + descr->enable_dpc = false; + descr->enable_tnr = false; + descr->enable_capture_pp_bli = false; + descr->enable_fractional_ds = false; + descr->dvs_env.width = 0; + descr->dvs_env.height = 0; + descr->stream_format = pipe->stream->config.input_config.format; + descr->in_info = in_info; + descr->bds_out_info = NULL; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + descr->out_info[i] = out_info[i]; + descr->vf_info = vf_info; + descr->isp_pipe_version = pipe->config.isp_pipe_version; + descr->required_bds_factor = SH_CSS_BDS_FACTOR_1_00; + descr->stream_config_left_padding = -1; +} + +void ia_css_pipe_get_copy_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *copy_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + unsigned int i; + /* out_info can be NULL */ + assert(pipe); + assert(in_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_COPY, + copy_descr, in_info, out_infos, vf_info); + copy_descr->online = true; + copy_descr->continuous = false; + copy_descr->two_ppc = (pipe->stream->config.pixels_per_clock == 2); + copy_descr->enable_dz = false; + copy_descr->isp_pipe_version = IA_CSS_PIPE_VERSION_1; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_vfpp_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *vf_pp_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + unsigned int i; + /* out_info can be NULL ??? */ + assert(pipe); + assert(in_info); + IA_CSS_ENTER_PRIVATE(""); + + in_info->raw_bit_depth = 0; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_VF_PP, + vf_pp_descr, in_info, out_infos, NULL); + vf_pp_descr->enable_fractional_ds = true; + IA_CSS_LEAVE_PRIVATE(""); +} + +static struct u32_fract bds_factors_list[] = { + [SH_CSS_BDS_FACTOR_1_00] = {1, 1}, + [SH_CSS_BDS_FACTOR_1_25] = {5, 4}, + [SH_CSS_BDS_FACTOR_1_50] = {3, 2}, + [SH_CSS_BDS_FACTOR_2_00] = {2, 1}, + [SH_CSS_BDS_FACTOR_2_25] = {9, 4}, + [SH_CSS_BDS_FACTOR_2_50] = {5, 2}, + [SH_CSS_BDS_FACTOR_3_00] = {3, 1}, + [SH_CSS_BDS_FACTOR_4_00] = {4, 1}, + [SH_CSS_BDS_FACTOR_4_50] = {9, 2}, + [SH_CSS_BDS_FACTOR_5_00] = {5, 1}, + [SH_CSS_BDS_FACTOR_6_00] = {6, 1}, + [SH_CSS_BDS_FACTOR_8_00] = {8, 1}, +}; + +int sh_css_bds_factor_get_fract(unsigned int bds_factor, struct u32_fract *bds) +{ + /* Throw an error since bds_factor cannot be found in bds_factors_list */ + if (bds_factor >= ARRAY_SIZE(bds_factors_list)) + return -EINVAL; + + *bds = bds_factors_list[bds_factor]; + return 0; +} + +int binarydesc_calculate_bds_factor( + struct ia_css_resolution input_res, + struct ia_css_resolution output_res, + unsigned int *bds_factor) +{ + unsigned int i; + unsigned int in_w = input_res.width, + in_h = input_res.height, + out_w = output_res.width, out_h = output_res.height; + + unsigned int max_bds_factor = 8; + unsigned int max_rounding_margin = 2; + /* delta in pixels to account for rounding margin in the calculation */ + unsigned int delta = max_bds_factor * max_rounding_margin; + + /* Assert if the resolutions are not set */ + assert(in_w != 0 && in_h != 0); + assert(out_w != 0 && out_h != 0); + + /* Loop over all bds factors until a match is found */ + for (i = 0; i < ARRAY_SIZE(bds_factors_list); i++) { + unsigned int num = bds_factors_list[i].numerator; + unsigned int den = bds_factors_list[i].denominator; + + /* See width-wise and height-wise if this bds_factor + * satisfies the condition */ + bool cond = (out_w * num / den + delta > in_w) && + (out_w * num / den <= in_w) && + (out_h * num / den + delta > in_h) && + (out_h * num / den <= in_h); + + if (cond) { + *bds_factor = i; + return 0; + } + } + + /* Throw an error since a suitable bds_factor cannot be found */ + return -EINVAL; +} + +int ia_css_pipe_get_preview_binarydesc( + struct ia_css_pipe *const pipe, + struct ia_css_binary_descr *preview_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *bds_out_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + int err; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + int mode = IA_CSS_BINARY_MODE_PREVIEW; + unsigned int i; + + assert(pipe); + assert(in_info); + assert(out_info); + assert(vf_info); + IA_CSS_ENTER_PRIVATE(""); + + /* + * Set up the info of the input frame with + * the ISP required resolution + */ + in_info->res = pipe->config.input_effective_res; + in_info->padded_width = in_info->res.width; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + + if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format)) + mode = IA_CSS_BINARY_MODE_COPY; + else + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, mode, + preview_descr, in_info, out_infos, vf_info); + if (pipe->stream->config.online) { + preview_descr->online = pipe->stream->config.online; + preview_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + } + preview_descr->stream_format = pipe->stream->config.input_config.format; + + /* TODO: Remove this when bds_out_info is available! */ + *bds_out_info = *in_info; + + if (pipe->extra_config.enable_raw_binning) { + if (pipe->config.bayer_ds_out_res.width != 0 && + pipe->config.bayer_ds_out_res.height != 0) { + bds_out_info->res.width = + pipe->config.bayer_ds_out_res.width; + bds_out_info->res.height = + pipe->config.bayer_ds_out_res.height; + bds_out_info->padded_width = + pipe->config.bayer_ds_out_res.width; + err = + binarydesc_calculate_bds_factor(in_info->res, + bds_out_info->res, + &preview_descr->required_bds_factor); + if (err) + return err; + } else { + bds_out_info->res.width = in_info->res.width / 2; + bds_out_info->res.height = in_info->res.height / 2; + bds_out_info->padded_width = in_info->padded_width / 2; + preview_descr->required_bds_factor = + SH_CSS_BDS_FACTOR_2_00; + } + } else { + /* TODO: Remove this when bds_out_info->is available! */ + bds_out_info->res.width = in_info->res.width; + bds_out_info->res.height = in_info->res.height; + bds_out_info->padded_width = in_info->padded_width; + preview_descr->required_bds_factor = SH_CSS_BDS_FACTOR_1_00; + } + pipe->required_bds_factor = preview_descr->required_bds_factor; + + /* bayer ds and fractional ds cannot be enabled at the same time, + so we disable bds_out_info when fractional ds is used */ + if (!pipe->extra_config.enable_fractional_ds) + preview_descr->bds_out_info = bds_out_info; + else + preview_descr->bds_out_info = NULL; + /* + ----Preview binary----- + --in-->|--out->|vf_veceven|--|--->vf + ----------------------- + * Preview binary normally doesn't have a vf_port but + * instead it has an output port. However, the output is + * generated by vf_veceven module in which we might have + * a downscaling (by 1x, 2x, or 4x). Because the resolution + * might change, we need two different info, namely out_info + * & vf_info. In fill_binary_info we use out&vf info to + * calculate vf decimation factor. + */ + *out_info = *vf_info; + + /* In case of preview_ds binary, we can do any fractional amount + * of downscale, so there is no DS needed in vf_veceven. Therefore, + * out and vf infos will be the same. Otherwise, we set out resolution + * equal to in resolution. */ + if (!pipe->extra_config.enable_fractional_ds) { + /* TODO: Change this when bds_out_info is available! */ + out_info->res.width = bds_out_info->res.width; + out_info->res.height = bds_out_info->res.height; + out_info->padded_width = bds_out_info->padded_width; + } + preview_descr->enable_fractional_ds = + pipe->extra_config.enable_fractional_ds; + + preview_descr->enable_dpc = pipe->config.enable_dpc; + + preview_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +int ia_css_pipe_get_video_binarydesc( + struct ia_css_pipe *const pipe, + struct ia_css_binary_descr *video_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *bds_out_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + int stream_config_left_padding) +{ + int mode = IA_CSS_BINARY_MODE_VIDEO; + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + int err = 0; + bool stream_dz_config = false; + + /* vf_info can be NULL */ + assert(pipe); + assert(in_info); + /* assert(vf_info != NULL); */ + IA_CSS_ENTER_PRIVATE(""); + + /* The solution below is not optimal; we should move to using ia_css_pipe_get_copy_binarydesc() + * But for now this fixes things; this code used to be there but was removed + * with gerrit 8908 as this was wrong for Skycam; however 240x still needs this + */ + if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format)) + mode = IA_CSS_BINARY_MODE_COPY; + + in_info->res = pipe->config.input_effective_res; + in_info->padded_width = in_info->res.width; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, mode, + video_descr, in_info, out_infos, vf_info); + + if (pipe->stream->config.online) { + video_descr->online = pipe->stream->config.online; + video_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + } + + if (mode == IA_CSS_BINARY_MODE_VIDEO) { + stream_dz_config = + ((pipe->stream->isp_params_configs->dz_config.dx != + HRT_GDC_N) + || (pipe->stream->isp_params_configs->dz_config.dy != + HRT_GDC_N)); + + video_descr->enable_dz = pipe->config.enable_dz + || stream_dz_config; + video_descr->dvs_env = pipe->config.dvs_envelope; + video_descr->enable_yuv_ds = pipe->extra_config.enable_yuv_ds; + video_descr->enable_high_speed = + pipe->extra_config.enable_high_speed; + video_descr->enable_dvs_6axis = + pipe->extra_config.enable_dvs_6axis; + video_descr->enable_reduced_pipe = + pipe->extra_config.enable_reduced_pipe; + video_descr->isp_pipe_version = pipe->config.isp_pipe_version; + video_descr->enable_fractional_ds = + pipe->extra_config.enable_fractional_ds; + video_descr->enable_dpc = + pipe->config.enable_dpc; + video_descr->enable_tnr = + pipe->config.enable_tnr; + + if (pipe->extra_config.enable_raw_binning) { + if (pipe->config.bayer_ds_out_res.width != 0 && + pipe->config.bayer_ds_out_res.height != 0) { + bds_out_info->res.width = + pipe->config.bayer_ds_out_res.width; + bds_out_info->res.height = + pipe->config.bayer_ds_out_res.height; + bds_out_info->padded_width = + pipe->config.bayer_ds_out_res.width; + err = + binarydesc_calculate_bds_factor( + in_info->res, bds_out_info->res, + &video_descr->required_bds_factor); + if (err) + return err; + } else { + bds_out_info->res.width = + in_info->res.width / 2; + bds_out_info->res.height = + in_info->res.height / 2; + bds_out_info->padded_width = + in_info->padded_width / 2; + video_descr->required_bds_factor = + SH_CSS_BDS_FACTOR_2_00; + } + } else { + bds_out_info->res.width = in_info->res.width; + bds_out_info->res.height = in_info->res.height; + bds_out_info->padded_width = in_info->padded_width; + video_descr->required_bds_factor = + SH_CSS_BDS_FACTOR_1_00; + } + + pipe->required_bds_factor = video_descr->required_bds_factor; + + /* bayer ds and fractional ds cannot be enabled + at the same time, so we disable bds_out_info when + fractional ds is used */ + if (!pipe->extra_config.enable_fractional_ds) + video_descr->bds_out_info = bds_out_info; + else + video_descr->bds_out_info = NULL; + + video_descr->enable_fractional_ds = + pipe->extra_config.enable_fractional_ds; + video_descr->stream_config_left_padding = stream_config_left_padding; + } + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +void ia_css_pipe_get_yuvscaler_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *yuv_scaler_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *internal_out_info, + struct ia_css_frame_info *vf_info) +{ + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame_info *this_vf_info = NULL; + + assert(pipe); + assert(in_info); + /* Note: if the following assert fails, the number of ports has been + * changed; in that case an additional initializer must be added + * a few lines below after which this assert can be updated. + */ + assert(IA_CSS_BINARY_MAX_OUTPUT_PORTS == 2); + IA_CSS_ENTER_PRIVATE(""); + + in_info->padded_width = in_info->res.width; + in_info->raw_bit_depth = 0; + ia_css_frame_info_set_width(in_info, in_info->res.width, 0); + out_infos[0] = out_info; + out_infos[1] = internal_out_info; + /* add initializers here if + * assert(IA_CSS_BINARY_MAX_OUTPUT_PORTS == ...); + * fails + */ + + if (vf_info) { + this_vf_info = (vf_info->res.width == 0 && + vf_info->res.height == 0) ? NULL : vf_info; + } + + pipe_binarydesc_get_offline(pipe, + IA_CSS_BINARY_MODE_CAPTURE_PP, + yuv_scaler_descr, + in_info, out_infos, this_vf_info); + + yuv_scaler_descr->enable_fractional_ds = true; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_capturepp_binarydesc( + struct ia_css_pipe *const pipe, + struct ia_css_binary_descr *capture_pp_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(vf_info); + IA_CSS_ENTER_PRIVATE(""); + + /* the in_info is only used for resolution to enable + bayer down scaling. */ + if (pipe->out_yuv_ds_input_info.res.width) + *in_info = pipe->out_yuv_ds_input_info; + else + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_YUV420; + in_info->raw_bit_depth = 0; + ia_css_frame_info_set_width(in_info, in_info->res.width, 0); + + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, + IA_CSS_BINARY_MODE_CAPTURE_PP, + capture_pp_descr, + in_info, out_infos, vf_info); + + capture_pp_descr->enable_capture_pp_bli = + pipe->config.default_capture_config.enable_capture_pp_bli; + capture_pp_descr->enable_fractional_ds = true; + capture_pp_descr->enable_xnr = + pipe->config.default_capture_config.enable_xnr != 0; + IA_CSS_LEAVE_PRIVATE(""); +} + +/* lookup table for high quality primary binaries */ +static unsigned int primary_hq_binary_modes[NUM_PRIMARY_HQ_STAGES] = { + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE0, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE1, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE2, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE3, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE4, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE5 +}; + +void ia_css_pipe_get_primary_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *prim_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + unsigned int stage_idx) +{ + enum ia_css_pipe_version pipe_version = pipe->config.isp_pipe_version; + int mode; + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + assert(stage_idx < NUM_PRIMARY_HQ_STAGES); + /* vf_info can be NULL - example video_binarydescr */ + /*assert(vf_info != NULL);*/ + IA_CSS_ENTER_PRIVATE(""); + + if (pipe_version == IA_CSS_PIPE_VERSION_2_6_1) + mode = primary_hq_binary_modes[stage_idx]; + else + mode = IA_CSS_BINARY_MODE_PRIMARY; + + if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format)) + mode = IA_CSS_BINARY_MODE_COPY; + + in_info->res = pipe->config.input_effective_res; + in_info->padded_width = in_info->res.width; + + if (pipe->stream->config.pack_raw_pixels) + in_info->format = IA_CSS_FRAME_FORMAT_RAW_PACKED; + else + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, mode, + prim_descr, in_info, out_infos, vf_info); + + if (pipe->stream->config.online && + pipe->stream->config.mode != IA_CSS_INPUT_MODE_MEMORY) { + prim_descr->online = true; + prim_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + prim_descr->stream_format = pipe->stream->config.input_config.format; + } + if (mode == IA_CSS_BINARY_MODE_PRIMARY) { + prim_descr->isp_pipe_version = pipe->config.isp_pipe_version; + prim_descr->enable_fractional_ds = + pipe->extra_config.enable_fractional_ds; + /* We have both striped and non-striped primary binaries, + * if continuous viewfinder is required, then we must select + * a striped one. Otherwise we prefer to use a non-striped + * since it has better performance. */ + if (pipe_version == IA_CSS_PIPE_VERSION_2_6_1) + prim_descr->striped = false; + else + prim_descr->striped = prim_descr->continuous && + (!pipe->stream->stop_copy_preview || !pipe->stream->disable_cont_vf); + } + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_pre_gdc_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *pre_gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP, + pre_gdc_descr, in_info, out_infos, NULL); + pre_gdc_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_gdc_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_QPLANE6; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_GDC, + gdc_descr, in_info, out_infos, NULL); + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_post_gdc_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *post_gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + assert(vf_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_YUV420_16; + in_info->raw_bit_depth = 16; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_POST_ISP, + post_gdc_descr, in_info, out_infos, vf_info); + + post_gdc_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_pre_de_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *pre_de_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_1) + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP, + pre_de_descr, in_info, out_infos, NULL); + else if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_2_2) { + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_DE, + pre_de_descr, in_info, out_infos, NULL); + } + + if (pipe->stream->config.online) { + pre_de_descr->online = true; + pre_de_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + pre_de_descr->stream_format = pipe->stream->config.input_config.format; + } + pre_de_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_pre_anr_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *pre_anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP, + pre_anr_descr, in_info, out_infos, NULL); + + if (pipe->stream->config.online) { + pre_anr_descr->online = true; + pre_anr_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + pre_anr_descr->stream_format = pipe->stream->config.input_config.format; + } + pre_anr_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_anr_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ANR_ELEMENT_BITS; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_ANR, + anr_descr, in_info, out_infos, NULL); + + anr_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_post_anr_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *post_anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + assert(vf_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ANR_ELEMENT_BITS; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_POST_ISP, + post_anr_descr, in_info, out_infos, vf_info); + + post_anr_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_ldc_binarydesc( + struct ia_css_pipe const *const pipe, + struct ia_css_binary_descr *ldc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe); + assert(in_info); + assert(out_info); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + + in_info->format = IA_CSS_FRAME_FORMAT_YUV420; + in_info->raw_bit_depth = 0; + ia_css_frame_info_set_width(in_info, in_info->res.width, 0); + + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_CAPTURE_PP, + ldc_descr, in_info, out_infos, NULL); + ldc_descr->enable_dvs_6axis = + pipe->extra_config.enable_dvs_6axis; + IA_CSS_LEAVE_PRIVATE(""); +} diff --git a/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_stagedesc.c b/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_stagedesc.c new file mode 100644 index 000000000..6c93fa1c6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_stagedesc.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_pipe_stagedesc.h" +#include "assert_support.h" +#include "ia_css_debug.h" + +void ia_css_pipe_get_generic_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_frame *out_frame[], + struct ia_css_frame *in_frame, + struct ia_css_frame *vf_frame) +{ + unsigned int i; + + IA_CSS_ENTER_PRIVATE("stage_desc = %p, binary = %p, out_frame = %p, in_frame = %p, vf_frame = %p", + stage_desc, binary, out_frame, in_frame, vf_frame); + + assert(stage_desc && binary && binary->info); + if (!stage_desc || !binary || !binary->info) { + IA_CSS_ERROR("invalid arguments"); + goto ERR; + } + + stage_desc->binary = binary; + stage_desc->firmware = NULL; + stage_desc->sp_func = IA_CSS_PIPELINE_NO_FUNC; + stage_desc->max_input_width = 0; + stage_desc->mode = binary->info->sp.pipeline.mode; + stage_desc->in_frame = in_frame; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + stage_desc->out_frame[i] = out_frame[i]; + } + stage_desc->vf_frame = vf_frame; +ERR: + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_firmwares_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_frame *out_frame[], + struct ia_css_frame *in_frame, + struct ia_css_frame *vf_frame, + const struct ia_css_fw_info *fw, + unsigned int mode) +{ + unsigned int i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipe_get_firmwares_stage_desc() enter:\n"); + stage_desc->binary = binary; + stage_desc->firmware = fw; + stage_desc->sp_func = IA_CSS_PIPELINE_NO_FUNC; + stage_desc->max_input_width = 0; + stage_desc->mode = mode; + stage_desc->in_frame = in_frame; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + stage_desc->out_frame[i] = out_frame[i]; + } + stage_desc->vf_frame = vf_frame; +} + +void ia_css_pipe_get_sp_func_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_frame *out_frame, + enum ia_css_pipeline_stage_sp_func sp_func, + unsigned int max_input_width) +{ + unsigned int i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipe_get_sp_func_stage_desc() enter:\n"); + stage_desc->binary = NULL; + stage_desc->firmware = NULL; + stage_desc->sp_func = sp_func; + stage_desc->max_input_width = max_input_width; + stage_desc->mode = (unsigned int)-1; + stage_desc->in_frame = NULL; + stage_desc->out_frame[0] = out_frame; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + stage_desc->out_frame[i] = NULL; + } + stage_desc->vf_frame = NULL; +} diff --git a/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_util.c b/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_util.c new file mode 100644 index 000000000..03d9d168f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_util.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_pipe_util.h" +#include "ia_css_frame_public.h" +#include "ia_css_pipe.h" +#include "ia_css_util.h" +#include "assert_support.h" + +unsigned int ia_css_pipe_util_pipe_input_format_bpp( + const struct ia_css_pipe *const pipe) +{ + assert(pipe); + assert(pipe->stream); + + return ia_css_util_input_format_bpp(pipe->stream->config.input_config.format, + pipe->stream->config.pixels_per_clock == 2); +} + +void ia_css_pipe_util_create_output_frames( + struct ia_css_frame *frames[]) +{ + unsigned int i; + + assert(frames); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + frames[i] = NULL; + } +} + +void ia_css_pipe_util_set_output_frames( + struct ia_css_frame *frames[], + unsigned int idx, + struct ia_css_frame *frame) +{ + assert(idx < IA_CSS_BINARY_MAX_OUTPUT_PORTS); + + frames[idx] = frame; +} diff --git a/drivers/staging/media/atomisp/pci/camera/util/interface/ia_css_util.h b/drivers/staging/media/atomisp/pci/camera/util/interface/ia_css_util.h new file mode 100644 index 000000000..59df44d69 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/camera/util/interface/ia_css_util.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_UTIL_H__ +#define __IA_CSS_UTIL_H__ + +#include + +#include +#include +#include +#include +#include + +/* @brief convert "errno" error code to "ia_css_err" error code + * + * @param[in] "errno" error code + * @return "ia_css_err" error code + * + */ +int ia_css_convert_errno( + int in_err); + +/* @brief check vf frame info. + * + * @param[in] info + * @return 0 or error code upon error. + * + */ +int ia_css_util_check_vf_info( + const struct ia_css_frame_info *const info); + +/* @brief check input configuration. + * + * @param[in] stream_config + * @param[in] must_be_raw + * @return 0 or error code upon error. + * + */ +int ia_css_util_check_input( + const struct ia_css_stream_config *const stream_config, + bool must_be_raw, + bool must_be_yuv); + +/* @brief check vf and out frame info. + * + * @param[in] out_info + * @param[in] vf_info + * @return 0 or error code upon error. + * + */ +int ia_css_util_check_vf_out_info( + const struct ia_css_frame_info *const out_info, + const struct ia_css_frame_info *const vf_info); + +/* @brief check width and height + * + * @param[in] width + * @param[in] height + * @return 0 or error code upon error. + * + */ +int ia_css_util_check_res( + unsigned int width, + unsigned int height); + +/* ISP2401 */ +/* @brief compare resolutions (less or equal) + * + * @param[in] a resolution + * @param[in] b resolution + * @return true if both dimensions of a are less or + * equal than those of b, false otherwise + * + */ +bool ia_css_util_res_leq( + struct ia_css_resolution a, + struct ia_css_resolution b); + +/* ISP2401 */ +/** + * @brief Check if resolution is zero + * + * @param[in] resolution The resolution to check + * + * @returns true if resolution is zero + */ +bool ia_css_util_resolution_is_zero( + const struct ia_css_resolution resolution); + +/* ISP2401 */ +/** + * @brief Check if resolution is even + * + * @param[in] resolution The resolution to check + * + * @returns true if resolution is even + */ +bool ia_css_util_resolution_is_even( + const struct ia_css_resolution resolution); + +/* @brief check width and height + * + * @param[in] stream_format + * @param[in] two_ppc + * @return bits per pixel based on given parameters. + * + */ +unsigned int ia_css_util_input_format_bpp( + enum atomisp_input_format stream_format, + bool two_ppc); + +/* @brief check if input format it raw + * + * @param[in] stream_format + * @return true if the input format is raw or false otherwise + * + */ +bool ia_css_util_is_input_format_raw( + enum atomisp_input_format stream_format); + +/* @brief check if input format it yuv + * + * @param[in] stream_format + * @return true if the input format is yuv or false otherwise + * + */ +bool ia_css_util_is_input_format_yuv( + enum atomisp_input_format stream_format); + +#endif /* __IA_CSS_UTIL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/camera/util/src/util.c b/drivers/staging/media/atomisp/pci/camera/util/src/util.c new file mode 100644 index 000000000..40a71e37c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/camera/util/src/util.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_util.h" +#include +#include +#include + +/* for ia_css_binary_max_vf_width() */ +#include "ia_css_binary.h" + +/* MW: Table look-up ??? */ +unsigned int ia_css_util_input_format_bpp( + enum atomisp_input_format format, + bool two_ppc) +{ + unsigned int rval = 0; + + switch (format) { + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: + case ATOMISP_INPUT_FORMAT_YUV420_8: + case ATOMISP_INPUT_FORMAT_YUV422_8: + case ATOMISP_INPUT_FORMAT_RGB_888: + case ATOMISP_INPUT_FORMAT_RAW_8: + case ATOMISP_INPUT_FORMAT_BINARY_8: + case ATOMISP_INPUT_FORMAT_EMBEDDED: + rval = 8; + break; + case ATOMISP_INPUT_FORMAT_YUV420_10: + case ATOMISP_INPUT_FORMAT_YUV422_10: + case ATOMISP_INPUT_FORMAT_RAW_10: + rval = 10; + break; + case ATOMISP_INPUT_FORMAT_YUV420_16: + case ATOMISP_INPUT_FORMAT_YUV422_16: + rval = 16; + break; + case ATOMISP_INPUT_FORMAT_RGB_444: + rval = 4; + break; + case ATOMISP_INPUT_FORMAT_RGB_555: + rval = 5; + break; + case ATOMISP_INPUT_FORMAT_RGB_565: + rval = 65; + break; + case ATOMISP_INPUT_FORMAT_RGB_666: + case ATOMISP_INPUT_FORMAT_RAW_6: + rval = 6; + break; + case ATOMISP_INPUT_FORMAT_RAW_7: + rval = 7; + break; + case ATOMISP_INPUT_FORMAT_RAW_12: + rval = 12; + break; + case ATOMISP_INPUT_FORMAT_RAW_14: + if (two_ppc) + rval = 14; + else + rval = 12; + break; + case ATOMISP_INPUT_FORMAT_RAW_16: + if (two_ppc) + rval = 16; + else + rval = 12; + break; + default: + rval = 0; + break; + } + return rval; +} + +int ia_css_util_check_vf_info( + const struct ia_css_frame_info *const info) +{ + int err; + unsigned int max_vf_width; + + assert(info); + err = ia_css_frame_check_info(info); + if (err) + return err; + max_vf_width = ia_css_binary_max_vf_width(); + if (max_vf_width != 0 && info->res.width > max_vf_width * 2) + return -EINVAL; + return 0; +} + +int ia_css_util_check_vf_out_info( + const struct ia_css_frame_info *const out_info, + const struct ia_css_frame_info *const vf_info) +{ + int err; + + assert(out_info); + assert(vf_info); + + err = ia_css_frame_check_info(out_info); + if (err) + return err; + err = ia_css_util_check_vf_info(vf_info); + if (err) + return err; + return 0; +} + +int ia_css_util_check_res(unsigned int width, unsigned int height) +{ + /* height can be odd number for jpeg/embedded data from ISYS2401 */ + if (((width == 0) || + (height == 0) || + IS_ODD(width))) { + return -EINVAL; + } + return 0; +} + +/* ISP2401 */ +bool ia_css_util_res_leq(struct ia_css_resolution a, struct ia_css_resolution b) +{ + return a.width <= b.width && a.height <= b.height; +} + +/* ISP2401 */ +bool ia_css_util_resolution_is_zero(const struct ia_css_resolution resolution) +{ + return (resolution.width == 0) || (resolution.height == 0); +} + +/* ISP2401 */ +bool ia_css_util_resolution_is_even(const struct ia_css_resolution resolution) +{ + return IS_EVEN(resolution.height) && IS_EVEN(resolution.width); +} + +bool ia_css_util_is_input_format_raw(enum atomisp_input_format format) +{ + return ((format == ATOMISP_INPUT_FORMAT_RAW_6) || + (format == ATOMISP_INPUT_FORMAT_RAW_7) || + (format == ATOMISP_INPUT_FORMAT_RAW_8) || + (format == ATOMISP_INPUT_FORMAT_RAW_10) || + (format == ATOMISP_INPUT_FORMAT_RAW_12)); + /* raw_14 and raw_16 are not supported as input formats to the ISP. + * They can only be copied to a frame in memory using the + * copy binary. + */ +} + +bool ia_css_util_is_input_format_yuv(enum atomisp_input_format format) +{ + return format == ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY || + format == ATOMISP_INPUT_FORMAT_YUV420_8 || + format == ATOMISP_INPUT_FORMAT_YUV420_10 || + format == ATOMISP_INPUT_FORMAT_YUV420_16 || + format == ATOMISP_INPUT_FORMAT_YUV422_8 || + format == ATOMISP_INPUT_FORMAT_YUV422_10 || + format == ATOMISP_INPUT_FORMAT_YUV422_16; +} + +int ia_css_util_check_input( + const struct ia_css_stream_config *const stream_config, + bool must_be_raw, + bool must_be_yuv) +{ + assert(stream_config); + + if (!stream_config) + return -EINVAL; + + if (stream_config->input_config.effective_res.width == 0 || + stream_config->input_config.effective_res.height == 0) + return -EINVAL; + if (must_be_raw && + !ia_css_util_is_input_format_raw(stream_config->input_config.format)) + return -EINVAL; + + if (must_be_yuv && + !ia_css_util_is_input_format_yuv(stream_config->input_config.format)) + return -EINVAL; + + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/cell_params.h b/drivers/staging/media/atomisp/pci/cell_params.h new file mode 100644 index 000000000..3c21a1899 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/cell_params.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _cell_params_h +#define _cell_params_h + +#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/ +#define SP_ICACHE_TAG_BITS 4 /*size of tag*/ +#define SP_ICACHE_SET_BITS 8 /* 256 sets*/ +#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/ +#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/ + +#define SP_ICACHE_ADDRESS_BITS \ + (SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS) + +#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS) + +#define SP_FIFO_0_DEPTH 0 +#define SP_FIFO_1_DEPTH 0 +#define SP_FIFO_2_DEPTH 0 +#define SP_FIFO_3_DEPTH 0 +#define SP_FIFO_4_DEPTH 0 +#define SP_FIFO_5_DEPTH 0 +#define SP_FIFO_6_DEPTH 0 +#define SP_FIFO_7_DEPTH 0 + +#define SP_SLV_BUS_MAXBURSTSIZE 1 + +#endif /* _cell_params_h */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/csi_rx_global.h b/drivers/staging/media/atomisp/pci/css_2401_system/csi_rx_global.h new file mode 100644 index 000000000..3aabd0248 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/csi_rx_global.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_GLOBAL_H_INCLUDED__ +#define __CSI_RX_GLOBAL_H_INCLUDED__ + +#include + +typedef enum { + CSI_MIPI_PACKET_TYPE_UNDEFINED = 0, + CSI_MIPI_PACKET_TYPE_LONG, + CSI_MIPI_PACKET_TYPE_SHORT, + CSI_MIPI_PACKET_TYPE_RESERVED, + N_CSI_MIPI_PACKET_TYPE +} csi_mipi_packet_type_t; + +typedef struct csi_rx_backend_lut_entry_s csi_rx_backend_lut_entry_t; +struct csi_rx_backend_lut_entry_s { + u32 long_packet_entry; + u32 short_packet_entry; +}; + +typedef struct csi_rx_backend_cfg_s csi_rx_backend_cfg_t; +struct csi_rx_backend_cfg_s { + /* LUT entry for the packet */ + csi_rx_backend_lut_entry_t lut_entry; + + /* can be derived from the Data Type */ + csi_mipi_packet_type_t csi_mipi_packet_type; + + struct { + bool comp_enable; + u32 virtual_channel; + u32 data_type; + u32 comp_scheme; + u32 comp_predictor; + u32 comp_bit_idx; + } csi_mipi_cfg; +}; + +typedef struct csi_rx_frontend_cfg_s csi_rx_frontend_cfg_t; +struct csi_rx_frontend_cfg_s { + u32 active_lanes; +}; + +extern const u32 N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID]; +extern const u32 N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID]; +extern const u32 N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID]; +/* sid_width for CSI_RX_BACKEND_ID */ +extern const u32 N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID]; + +#endif /* __CSI_RX_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx.c b/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx.c new file mode 100644 index 000000000..9a8d8f546 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" +#include "csi_rx_global.h" + +const u32 N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = { + 4, /* 4 entries at CSI_RX_BACKEND0_ID*/ + 4, /* 4 entries at CSI_RX_BACKEND1_ID*/ + 4 /* 4 entries at CSI_RX_BACKEND2_ID*/ +}; + +const u32 N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = { + 8, /* 8 entries at CSI_RX_BACKEND0_ID*/ + 4, /* 4 entries at CSI_RX_BACKEND1_ID*/ + 4 /* 4 entries at CSI_RX_BACKEND2_ID*/ +}; + +const u32 N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID] = { + N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND0_ID */ + N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND1_ID */ + N_CSI_RX_DLANE_ID /* 4 dlanes for CSI_RX_FR0NTEND2_ID */ +}; + +/* sid_width for CSI_RX_BACKEND_ID */ +const u32 N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID] = { + 3, + 2, + 2 +}; diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx_local.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx_local.h new file mode 100644 index 000000000..6489ee644 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx_local.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_LOCAL_H_INCLUDED__ +#define __CSI_RX_LOCAL_H_INCLUDED__ + +#include "csi_rx_global.h" +#define N_CSI_RX_BE_MIPI_COMP_FMT_REG 4 +#define N_CSI_RX_BE_MIPI_CUSTOM_PEC 12 +#define N_CSI_RX_BE_SHORT_PKT_LUT 4 +#define N_CSI_RX_BE_LONG_PKT_LUT 8 +typedef struct csi_rx_fe_ctrl_state_s csi_rx_fe_ctrl_state_t; +typedef struct csi_rx_fe_ctrl_lane_s csi_rx_fe_ctrl_lane_t; +typedef struct csi_rx_be_ctrl_state_s csi_rx_be_ctrl_state_t; +/*mipi_backend_custom_mode_pixel_extraction_config*/ +typedef struct csi_rx_be_ctrl_pec_s csi_rx_be_ctrl_pec_t; + +struct csi_rx_fe_ctrl_lane_s { + hrt_data termen; + hrt_data settle; +}; + +struct csi_rx_fe_ctrl_state_s { + hrt_data enable; + hrt_data nof_enable_lanes; + hrt_data error_handling; + hrt_data status; + hrt_data status_dlane_hs; + hrt_data status_dlane_lp; + csi_rx_fe_ctrl_lane_t clane; + csi_rx_fe_ctrl_lane_t dlane[N_CSI_RX_DLANE_ID]; +}; + +struct csi_rx_be_ctrl_state_s { + hrt_data enable; + hrt_data status; + hrt_data comp_format_reg[N_CSI_RX_BE_MIPI_COMP_FMT_REG]; + hrt_data raw16; + hrt_data raw18; + hrt_data force_raw8; + hrt_data irq_status; + hrt_data custom_mode_enable; + hrt_data custom_mode_data_state; + hrt_data pec[N_CSI_RX_BE_MIPI_CUSTOM_PEC]; + hrt_data custom_mode_valid_eop_config; + hrt_data global_lut_disregard_reg; + hrt_data packet_status_stall; + hrt_data short_packet_lut_entry[N_CSI_RX_BE_SHORT_PKT_LUT]; + hrt_data long_packet_lut_entry[N_CSI_RX_BE_LONG_PKT_LUT]; +}; +#endif /* __CSI_RX_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx_private.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx_private.h new file mode 100644 index 000000000..ece45d80e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/csi_rx_private.h @@ -0,0 +1,306 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_PRIVATE_H_INCLUDED__ +#define __CSI_RX_PRIVATE_H_INCLUDED__ + +#include "rx_csi_defs.h" +#include "mipi_backend_defs.h" +#include "csi_rx.h" + +#include "device_access.h" /* ia_css_device_load_uint32 */ + +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "csi_rx_public.h" for details. + */ +static inline hrt_data csi_rx_fe_ctrl_reg_load( + const csi_rx_frontend_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_CSI_RX_FRONTEND_ID); + assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof( + hrt_data)); +} + +/** + * @brief Store a value to the register. + * Refer to "ibuf_ctrl_public.h" for details. + */ +static inline void csi_rx_fe_ctrl_reg_store( + const csi_rx_frontend_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_CSI_RX_FRONTEND_ID); + assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data), + value); +} + +/** + * @brief Load the register value. + * Refer to "csi_rx_public.h" for details. + */ +static inline hrt_data csi_rx_be_ctrl_reg_load( + const csi_rx_backend_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_CSI_RX_BACKEND_ID); + assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof( + hrt_data)); +} + +/** + * @brief Store a value to the register. + * Refer to "ibuf_ctrl_public.h" for details. + */ +static inline void csi_rx_be_ctrl_reg_store( + const csi_rx_backend_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_CSI_RX_BACKEND_ID); + assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data), + value); +} + +/* end of DLI */ + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the state of the csi rx fe dlane process. + * Refer to "csi_rx_public.h" for details. + */ +static inline void csi_rx_fe_ctrl_get_dlane_state( + const csi_rx_frontend_ID_t ID, + const u32 lane, + csi_rx_fe_ctrl_lane_t *dlane_state) +{ + dlane_state->termen = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane)); + dlane_state->settle = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane)); +} + +/** + * @brief Get the csi rx fe state. + * Refer to "csi_rx_public.h" for details. + */ +static inline void csi_rx_fe_ctrl_get_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state) +{ + u32 i; + + state->enable = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX); + state->nof_enable_lanes = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX); + state->error_handling = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX); + state->status = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX); + state->status_dlane_hs = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX); + state->status_dlane_lp = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX); + state->clane.termen = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX); + state->clane.settle = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX); + + /* + * Get the values of the register-set per + * dlane. + */ + for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) { + csi_rx_fe_ctrl_get_dlane_state( + ID, + i, + &state->dlane[i]); + } +} + +/** + * @brief dump the csi rx fe state. + * Refer to "csi_rx_public.h" for details. + */ +static inline void csi_rx_fe_ctrl_dump_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state) +{ + u32 i; + + ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x\n", ID, + state->enable); + ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x\n", ID, + state->nof_enable_lanes); + ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x\n", ID, + state->error_handling); + ia_css_print("CSI RX FE STATE Controller %d Status 0x%x\n", ID, state->status); + ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x\n", ID, + state->status_dlane_hs); + ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x\n", ID, + state->status_dlane_lp); + ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x\n", ID, + state->clane.termen); + ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x\n", ID, + state->clane.settle); + + /* + * Get the values of the register-set per + * dlane. + */ + for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) { + ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x\n", ID, i, + state->dlane[i].termen); + ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x\n", ID, i, + state->dlane[i].settle); + } +} + +/** + * @brief Get the csi rx be state. + * Refer to "csi_rx_public.h" for details. + */ +static inline void csi_rx_be_ctrl_get_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state) +{ + u32 i; + + state->enable = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX); + + state->status = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX); + + for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) { + state->comp_format_reg[i] = + csi_rx_be_ctrl_reg_load(ID, + _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX + i); + } + + state->raw16 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX); + + state->raw18 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX); + state->force_raw8 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX); + state->irq_status = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX); +#if 0 /* device access error for these registers */ + /* ToDo: rootcause this failure */ + state->custom_mode_enable = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX); + + state->custom_mode_data_state = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX); + for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) { + state->pec[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i); + } + state->custom_mode_valid_eop_config = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX); +#endif + state->global_lut_disregard_reg = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX); + state->packet_status_stall = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX); + /* + * Get the values of the register-set per + * lut. + */ + for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) { + state->short_packet_lut_entry[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i); + } + for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) { + state->long_packet_lut_entry[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i); + } +} + +/** + * @brief Dump the csi rx be state. + * Refer to "csi_rx_public.h" for details. + */ +static inline void csi_rx_be_ctrl_dump_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state) +{ + u32 i; + + ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x\n", ID, state->enable); + ia_css_print("CSI RX BE STATE Controller %d Status 0x%x\n", ID, state->status); + + for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) { + ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x\n", + ID, i, state->status); + } + ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x\n", ID, state->raw16); + ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x\n", ID, state->raw18); + ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x\n", ID, + state->force_raw8); + ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x\n", ID, + state->irq_status); +#if 0 /* ToDo:Getting device access error for this register */ + for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) { + ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x\n", ID, i, + state->pec[i]); + } +#endif + ia_css_print("CSI RX BE STATE Controller %d Global LUT disregard reg 0x%x\n", + ID, state->global_lut_disregard_reg); + ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x\n", ID, + state->packet_status_stall); + /* + * Get the values of the register-set per + * lut. + */ + for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) { + ia_css_print("CSI RX BE STATE Controller ID %d Short packet entry %d short packet lut id 0x%x\n", + ID, i, + state->short_packet_lut_entry[i]); + } + for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) { + ia_css_print("CSI RX BE STATE Controller ID %d Long packet entry %d long packet lut id 0x%x\n", + ID, i, + state->long_packet_lut_entry[i]); + } +} + +/* end of NCI */ + +#endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/ibuf_ctrl.c b/drivers/staging/media/atomisp/pci/css_2401_system/host/ibuf_ctrl.c new file mode 100644 index 000000000..8d19c9875 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/ibuf_ctrl.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "system_global.h" +#include "ibuf_ctrl_global.h" + +const u32 N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID] = { + 8, /* IBUF_CTRL0_ID supports at most 8 processes */ + 4, /* IBUF_CTRL1_ID supports at most 4 processes */ + 4 /* IBUF_CTRL2_ID supports at most 4 processes */ +}; diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/ibuf_ctrl_local.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/ibuf_ctrl_local.h new file mode 100644 index 000000000..f71841195 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/ibuf_ctrl_local.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_LOCAL_H_INCLUDED__ +#define __IBUF_CTRL_LOCAL_H_INCLUDED__ + +#include "ibuf_ctrl_global.h" +#include "ibuf_ctrl_local.h" + +typedef struct ibuf_ctrl_proc_state_s ibuf_ctrl_proc_state_t; +typedef struct ibuf_ctrl_state_s ibuf_ctrl_state_t; + +struct ibuf_ctrl_proc_state_s { + hrt_data num_items; + hrt_data num_stores; + hrt_data dma_channel; + hrt_data dma_command; + hrt_data ibuf_st_addr; + hrt_data ibuf_stride; + hrt_data ibuf_end_addr; + hrt_data dest_st_addr; + hrt_data dest_stride; + hrt_data dest_end_addr; + hrt_data sync_frame; + hrt_data sync_command; + hrt_data store_command; + hrt_data shift_returned_items; + hrt_data elems_ibuf; + hrt_data elems_dest; + hrt_data cur_stores; + hrt_data cur_acks; + hrt_data cur_s2m_ibuf_addr; + hrt_data cur_dma_ibuf_addr; + hrt_data cur_dma_dest_addr; + hrt_data cur_isp_dest_addr; + hrt_data dma_cmds_send; + hrt_data main_cntrl_state; + hrt_data dma_sync_state; + hrt_data isp_sync_state; +}; + +struct ibuf_ctrl_state_s { + hrt_data recalc_words; + hrt_data arbiters; + ibuf_ctrl_proc_state_t proc_state[N_STREAM2MMIO_SID_ID]; +}; + +#endif /* __IBUF_CTRL_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_dma.c b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_dma.c new file mode 100644 index 000000000..2a5159945 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_dma.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_local.h" +#include "isys_dma_global.h" +#include "assert_support.h" +#include "isys_dma_private.h" + +const isys2401_dma_channel N_ISYS2401_DMA_CHANNEL_PROCS[N_ISYS2401_DMA_ID] = { + N_ISYS2401_DMA_CHANNEL +}; + +void isys2401_dma_set_max_burst_size( + const isys2401_dma_ID_t dma_id, + uint32_t max_burst_size) +{ + assert(dma_id < N_ISYS2401_DMA_ID); + assert((max_burst_size > 0x00) && (max_burst_size <= 0xFF)); + + isys2401_dma_reg_store(dma_id, + DMA_DEV_INFO_REG_IDX(_DMA_V2_DEV_INTERF_MAX_BURST_IDX, HIVE_DMA_BUS_DDR_CONN), + (max_burst_size - 1)); +} diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_dma_private.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_dma_private.h new file mode 100644 index 000000000..a313e1dc7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_dma_private.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_PRIVATE_H_INCLUDED__ +#define __ISYS_DMA_PRIVATE_H_INCLUDED__ + +#include "isys_dma_public.h" +#include "device_access.h" +#include "assert_support.h" +#include "dma.h" +#include "dma_v2_defs.h" +#include "print_support.h" + +void isys2401_dma_reg_store(const isys2401_dma_ID_t dma_id, + const unsigned int reg, + const hrt_data value) +{ + unsigned int reg_loc; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address) - 1); + + reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data)); + + ia_css_print("isys dma store at addr(0x%x) val(%u)\n", reg_loc, + (unsigned int)value); + ia_css_device_store_uint32(reg_loc, value); +} + +hrt_data isys2401_dma_reg_load(const isys2401_dma_ID_t dma_id, + const unsigned int reg) +{ + unsigned int reg_loc; + hrt_data value; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address) - 1); + + reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data)); + + value = ia_css_device_load_uint32(reg_loc); + ia_css_print("isys dma load from addr(0x%x) val(%u)\n", reg_loc, + (unsigned int)value); + + return value; +} + +#endif /* __ISYS_DMA_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq.c b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq.c new file mode 100644 index 000000000..b6135c4b6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "device_access.h" +#include "assert_support.h" +#include "ia_css_debug.h" +#include "isys_irq.h" + +#ifndef __INLINE_ISYS2401_IRQ__ +/* + * Include definitions for isys irq private functions. isys_irq.h includes + * declarations of these functions by including isys_irq_public.h. + */ +#include "isys_irq_private.h" +#endif + +/* Public interface */ +void isys_irqc_status_enable(const isys_irq_ID_t isys_irqc_id) +{ + assert(isys_irqc_id < N_ISYS_IRQ_ID); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Setting irq mask for port %u\n", + isys_irqc_id); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX, + ISYS_IRQ_MASK_REG_VALUE); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX, + ISYS_IRQ_CLEAR_REG_VALUE); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX, + ISYS_IRQ_ENABLE_REG_VALUE); +} diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq_local.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq_local.h new file mode 100644 index 000000000..a76987190 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq_local.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_LOCAL_H__ +#define __ISYS_IRQ_LOCAL_H__ + +#include + +#if defined(ISP2401) + +typedef struct isys_irqc_state_s isys_irqc_state_t; + +struct isys_irqc_state_s { + hrt_data edge; + hrt_data mask; + hrt_data status; + hrt_data enable; + hrt_data level_no; + /*hrt_data clear; */ /* write-only register */ +}; + +#endif /* defined(ISP2401) */ + +#endif /* __ISYS_IRQ_LOCAL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq_private.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq_private.h new file mode 100644 index 000000000..fb168c25b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_irq_private.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_PRIVATE_H__ +#define __ISYS_IRQ_PRIVATE_H__ + +#include "isys_irq_global.h" +#include "isys_irq_local.h" + +#if defined(ISP2401) + +/* -------------------------------------------------------+ + | Native command interface (NCI) | + + -------------------------------------------------------*/ + +/** +* @brief Get the isys irq status. +* Refer to "isys_irq.h" for details. +*/ +void isys_irqc_state_get( + const isys_irq_ID_t isys_irqc_id, + isys_irqc_state_t *state) +{ + state->edge = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_EDGE_REG_IDX); + state->mask = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX); + state->status = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_STATUS_REG_IDX); + state->enable = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX); + state->level_no = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_LEVEL_NO_REG_IDX); + /* + ** Invalid to read/load from write-only register 'clear' + ** state->clear = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX); + */ +} + +/** +* @brief Dump the isys irq status. +* Refer to "isys_irq.h" for details. +*/ +void isys_irqc_state_dump( + const isys_irq_ID_t isys_irqc_id, + const isys_irqc_state_t *state) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq controller id %d\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n", + isys_irqc_id, + state->status, state->edge, state->mask, state->enable, state->level_no); +} + +/* end of NCI */ + +/* -------------------------------------------------------+ + | Device level interface (DLI) | + + -------------------------------------------------------*/ + +/* Support functions */ +void isys_irqc_reg_store( + const isys_irq_ID_t isys_irqc_id, + const unsigned int reg_idx, + const hrt_data value) +{ + unsigned int reg_addr; + + assert(isys_irqc_id < N_ISYS_IRQ_ID); + assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); + + reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); + + ia_css_device_store_uint32(reg_addr, value); +} + +hrt_data isys_irqc_reg_load( + const isys_irq_ID_t isys_irqc_id, + const unsigned int reg_idx) +{ + unsigned int reg_addr; + hrt_data value; + + assert(isys_irqc_id < N_ISYS_IRQ_ID); + assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); + + reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); + value = ia_css_device_load_uint32(reg_addr); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); + + return value; +} + +/* end of DLI */ + +#endif /* defined(ISP2401) */ + +#endif /* __ISYS_IRQ_PRIVATE_H__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio.c b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio.c new file mode 100644 index 000000000..b7d893aea --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "isys_stream2mmio.h" + +const stream2mmio_sid_ID_t N_STREAM2MMIO_SID_PROCS[N_STREAM2MMIO_ID] = { + N_STREAM2MMIO_SID_ID, + STREAM2MMIO_SID4_ID, + STREAM2MMIO_SID4_ID +}; diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio_local.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio_local.h new file mode 100644 index 000000000..4fbbcc233 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio_local.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ + +#include "isys_stream2mmio_global.h" + +typedef struct stream2mmio_state_s stream2mmio_state_t; +typedef struct stream2mmio_sid_state_s stream2mmio_sid_state_t; + +struct stream2mmio_sid_state_s { + hrt_data rcv_ack; + hrt_data pix_width_id; + hrt_data start_addr; + hrt_data end_addr; + hrt_data strides; + hrt_data num_items; + hrt_data block_when_no_cmd; +}; + +struct stream2mmio_state_s { + stream2mmio_sid_state_t sid_state[N_STREAM2MMIO_SID_ID]; +}; +#endif /* __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio_private.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio_private.h new file mode 100644 index 000000000..4a5646a22 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio_private.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ + +#include "isys_stream2mmio_public.h" +#include "device_access.h" /* ia_css_device_load_uint32 */ +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + +#define STREAM2MMIO_COMMAND_REG_ID 0 +#define STREAM2MMIO_ACKNOWLEDGE_REG_ID 1 +#define STREAM2MMIO_PIX_WIDTH_ID_REG_ID 2 +#define STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */ +#define STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */ +#define STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/ +#define STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */ +#define STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */ +#define STREAM2MMIO_REGS_PER_SID 8 + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the stream2mmio-controller state. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_state( + const stream2mmio_ID_t ID, + stream2mmio_state_t *state) +{ + stream2mmio_sid_ID_t i; + + /* + * Get the values of the register-set per + * stream2mmio-controller sids. + */ + for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { + stream2mmio_get_sid_state(ID, i, &state->sid_state[i]); + } +} + +/** + * @brief Get the state of the stream2mmio-controller sidess. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_sid_state( + const stream2mmio_ID_t ID, + const stream2mmio_sid_ID_t sid_id, + stream2mmio_sid_state_t *state) +{ + state->rcv_ack = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID); + + state->pix_width_id = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID); + + state->start_addr = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID); + + state->end_addr = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID); + + state->strides = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID); + + state->num_items = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_NUM_ITEMS_REG_ID); + + state->block_when_no_cmd = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID); +} + +/** + * @brief Dump the state of the stream2mmio-controller sidess. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_print_sid_state( + stream2mmio_sid_state_t *state) +{ + ia_css_print("\t \t Receive acks 0x%x\n", state->rcv_ack); + ia_css_print("\t \t Pixel width 0x%x\n", state->pix_width_id); + ia_css_print("\t \t Startaddr 0x%x\n", state->start_addr); + ia_css_print("\t \t Endaddr 0x%x\n", state->end_addr); + ia_css_print("\t \t Strides 0x%x\n", state->strides); + ia_css_print("\t \t Num Items 0x%x\n", state->num_items); + ia_css_print("\t \t block when no cmd 0x%x\n", state->block_when_no_cmd); +} + +/** + * @brief Dump the ibuf-controller state. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_dump_state( + const stream2mmio_ID_t ID, + stream2mmio_state_t *state) +{ + stream2mmio_sid_ID_t i; + + /* + * Get the values of the register-set per + * stream2mmio-controller sids. + */ + for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { + ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i); + stream2mmio_print_sid_state(&state->sid_state[i]); + } +} + +/* end of NCI */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C hrt_data stream2mmio_reg_load( + const stream2mmio_ID_t ID, + const stream2mmio_sid_ID_t sid_id, + const uint32_t reg_idx) +{ + u32 reg_bank_offset; + + assert(ID < N_STREAM2MMIO_ID); + + reg_bank_offset = STREAM2MMIO_REGS_PER_SID * sid_id; + return ia_css_device_load_uint32(STREAM2MMIO_CTRL_BASE[ID] + + (reg_bank_offset + reg_idx) * sizeof(hrt_data)); +} + +/** + * @brief Store a value to the register. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_reg_store( + const stream2mmio_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_STREAM2MMIO_ID); + assert(STREAM2MMIO_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] + + reg * sizeof(hrt_data), value); +} + +/* end of DLI */ + +#endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/pixelgen_local.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/pixelgen_local.h new file mode 100644 index 000000000..efaa4da8d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/pixelgen_local.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_LOCAL_H_INCLUDED__ +#define __PIXELGEN_LOCAL_H_INCLUDED__ + +#include "pixelgen_global.h" + +typedef struct pixelgen_ctrl_state_s pixelgen_ctrl_state_t; +struct pixelgen_ctrl_state_s { + hrt_data com_enable; + hrt_data prbs_rstval0; + hrt_data prbs_rstval1; + hrt_data syng_sid; + hrt_data syng_free_run; + hrt_data syng_pause; + hrt_data syng_nof_frames; + hrt_data syng_nof_pixels; + hrt_data syng_nof_line; + hrt_data syng_hblank_cyc; + hrt_data syng_vblank_cyc; + hrt_data syng_stat_hcnt; + hrt_data syng_stat_vcnt; + hrt_data syng_stat_fcnt; + hrt_data syng_stat_done; + hrt_data tpg_mode; + hrt_data tpg_hcnt_mask; + hrt_data tpg_vcnt_mask; + hrt_data tpg_xycnt_mask; + hrt_data tpg_hcnt_delta; + hrt_data tpg_vcnt_delta; + hrt_data tpg_r1; + hrt_data tpg_g1; + hrt_data tpg_b1; + hrt_data tpg_r2; + hrt_data tpg_g2; + hrt_data tpg_b2; +}; +#endif /* __PIXELGEN_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/host/pixelgen_private.h b/drivers/staging/media/atomisp/pci/css_2401_system/host/pixelgen_private.h new file mode 100644 index 000000000..8f79424be --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/host/pixelgen_private.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_PRIVATE_H_INCLUDED__ +#define __PIXELGEN_PRIVATE_H_INCLUDED__ +#include "pixelgen_public.h" +#include "PixelGen_SysBlock_defs.h" +#include "device_access.h" /* ia_css_device_load_uint32 */ +#include "assert_support.h" /* assert */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C hrt_data pixelgen_ctrl_reg_load( + const pixelgen_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_PIXELGEN_ID); + assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1); + return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof( + hrt_data)); +} + +/** + * @brief Store a value to the register. + * Refer to "pixelgen_ctrl_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_reg_store( + const pixelgen_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_PIXELGEN_ID); + assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data), + value); +} + +/* end of DLI */ + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the pixelgen state. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_get_state( + const pixelgen_ID_t ID, + pixelgen_ctrl_state_t *state) +{ + state->com_enable = + pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX); + state->prbs_rstval0 = + pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG0_IDX); + state->prbs_rstval1 = + pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG1_IDX); + state->syng_sid = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_SID_REG_IDX); + state->syng_free_run = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_FREE_RUN_REG_IDX); + state->syng_pause = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_PAUSE_REG_IDX); + state->syng_nof_frames = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_FRAME_REG_IDX); + state->syng_nof_pixels = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_PIXEL_REG_IDX); + state->syng_nof_line = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_LINE_REG_IDX); + state->syng_hblank_cyc = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_HBLANK_CYC_REG_IDX); + state->syng_vblank_cyc = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_VBLANK_CYC_REG_IDX); + state->syng_stat_hcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_HCNT_REG_IDX); + state->syng_stat_vcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_VCNT_REG_IDX); + state->syng_stat_fcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_FCNT_REG_IDX); + state->syng_stat_done = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_DONE_REG_IDX); + state->tpg_mode = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_MODE_REG_IDX); + state->tpg_hcnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_MASK_REG_IDX); + state->tpg_vcnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_MASK_REG_IDX); + state->tpg_xycnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_XYCNT_MASK_REG_IDX); + state->tpg_hcnt_delta = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_DELTA_REG_IDX); + state->tpg_vcnt_delta = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_DELTA_REG_IDX); + state->tpg_r1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_R1_REG_IDX); + state->tpg_g1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_G1_REG_IDX); + state->tpg_b1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_B1_REG_IDX); + state->tpg_r2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_R2_REG_IDX); + state->tpg_g2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_G2_REG_IDX); + state->tpg_b2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX); +} + +/** + * @brief Dump the pixelgen state. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_dump_state( + const pixelgen_ID_t ID, + pixelgen_ctrl_state_t *state) +{ + ia_css_print("Pixel Generator ID %d Enable 0x%x\n", ID, state->com_enable); + ia_css_print("Pixel Generator ID %d PRBS reset value 0 0x%x\n", ID, + state->prbs_rstval0); + ia_css_print("Pixel Generator ID %d PRBS reset value 1 0x%x\n", ID, + state->prbs_rstval1); + ia_css_print("Pixel Generator ID %d SYNC SID 0x%x\n", ID, state->syng_sid); + ia_css_print("Pixel Generator ID %d syng free run 0x%x\n", ID, + state->syng_free_run); + ia_css_print("Pixel Generator ID %d syng pause 0x%x\n", ID, state->syng_pause); + ia_css_print("Pixel Generator ID %d syng no of frames 0x%x\n", ID, + state->syng_nof_frames); + ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x\n", ID, + state->syng_nof_pixels); + ia_css_print("Pixel Generator ID %d syng no of line 0x%x\n", ID, + state->syng_nof_line); + ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x\n", ID, + state->syng_hblank_cyc); + ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x\n", ID, + state->syng_vblank_cyc); + ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x\n", ID, + state->syng_stat_hcnt); + ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x\n", ID, + state->syng_stat_vcnt); + ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x\n", ID, + state->syng_stat_fcnt); + ia_css_print("Pixel Generator ID %d syng stat done 0x%x\n", ID, + state->syng_stat_done); + ia_css_print("Pixel Generator ID %d tpg mode 0x%x\n", ID, state->tpg_mode); + ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID, + state->tpg_hcnt_mask); + ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID, + state->tpg_hcnt_mask); + ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x\n", ID, + state->tpg_xycnt_mask); + ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x\n", ID, + state->tpg_hcnt_delta); + ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x\n", ID, + state->tpg_vcnt_delta); + ia_css_print("Pixel Generator ID %d tpg r1 0x%x\n", ID, state->tpg_r1); + ia_css_print("Pixel Generator ID %d tpg g1 0x%x\n", ID, state->tpg_g1); + ia_css_print("Pixel Generator ID %d tpg b1 0x%x\n", ID, state->tpg_b1); + ia_css_print("Pixel Generator ID %d tpg r2 0x%x\n", ID, state->tpg_r2); + ia_css_print("Pixel Generator ID %d tpg g2 0x%x\n", ID, state->tpg_g2); + ia_css_print("Pixel Generator ID %d tpg b2 0x%x\n", ID, state->tpg_b2); +} + +/* end of NCI */ +#endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/hrt/PixelGen_SysBlock_defs.h b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/PixelGen_SysBlock_defs.h new file mode 100644 index 000000000..ae471dd51 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/PixelGen_SysBlock_defs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _PixelGen_SysBlock_defs_h +#define _PixelGen_SysBlock_defs_h + +/* Parematers and User_Parameters for HSS */ +#define _PXG_PPC Ppc +#define _PXG_PIXEL_BITS PixelWidth +#define _PXG_MAX_NOF_SID MaxNofSids +#define _PXG_DATA_BITS DataWidth +#define _PXG_CNT_BITS CntWidth +#define _PXG_FIFODEPTH FifoDepth +#define _PXG_DBG Dbg_device_not_included + +/* ID's and Address */ +#define _PXG_ADRRESS_ALIGN_REG 4 + +#define _PXG_COM_ENABLE_REG_IDX 0 +#define _PXG_PRBS_RSTVAL_REG0_IDX 1 +#define _PXG_PRBS_RSTVAL_REG1_IDX 2 +#define _PXG_SYNG_SID_REG_IDX 3 +#define _PXG_SYNG_FREE_RUN_REG_IDX 4 +#define _PXG_SYNG_PAUSE_REG_IDX 5 +#define _PXG_SYNG_NOF_FRAME_REG_IDX 6 +#define _PXG_SYNG_NOF_PIXEL_REG_IDX 7 +#define _PXG_SYNG_NOF_LINE_REG_IDX 8 +#define _PXG_SYNG_HBLANK_CYC_REG_IDX 9 +#define _PXG_SYNG_VBLANK_CYC_REG_IDX 10 +#define _PXG_SYNG_STAT_HCNT_REG_IDX 11 +#define _PXG_SYNG_STAT_VCNT_REG_IDX 12 +#define _PXG_SYNG_STAT_FCNT_REG_IDX 13 +#define _PXG_SYNG_STAT_DONE_REG_IDX 14 +#define _PXG_TPG_MODE_REG_IDX 15 +#define _PXG_TPG_HCNT_MASK_REG_IDX 16 +#define _PXG_TPG_VCNT_MASK_REG_IDX 17 +#define _PXG_TPG_XYCNT_MASK_REG_IDX 18 +#define _PXG_TPG_HCNT_DELTA_REG_IDX 19 +#define _PXG_TPG_VCNT_DELTA_REG_IDX 20 +#define _PXG_TPG_R1_REG_IDX 21 +#define _PXG_TPG_G1_REG_IDX 22 +#define _PXG_TPG_B1_REG_IDX 23 +#define _PXG_TPG_R2_REG_IDX 24 +#define _PXG_TPG_G2_REG_IDX 25 +#define _PXG_TPG_B2_REG_IDX 26 +/* */ +#define _PXG_SYNG_PAUSE_CYCLES 0 +/* Subblock ID's */ +#define _PXG_DISABLE_IDX 0 +#define _PXG_PRBS_IDX 0 +#define _PXG_TPG_IDX 1 +#define _PXG_SYNG_IDX 2 +#define _PXG_SMUX_IDX 3 +/* Register Widths */ +#define _PXG_COM_ENABLE_REG_WIDTH 2 +#define _PXG_COM_SRST_REG_WIDTH 4 +#define _PXG_PRBS_RSTVAL_REG0_WIDTH 31 +#define _PXG_PRBS_RSTVAL_REG1_WIDTH 31 + +#define _PXG_SYNG_SID_REG_WIDTH 3 + +#define _PXG_SYNG_FREE_RUN_REG_WIDTH 1 +#define _PXG_SYNG_PAUSE_REG_WIDTH 1 +/* +#define _PXG_SYNG_NOF_FRAME_REG_WIDTH +#define _PXG_SYNG_NOF_PIXEL_REG_WIDTH +#define _PXG_SYNG_NOF_LINE_REG_WIDTH +#define _PXG_SYNG_HBLANK_CYC_REG_WIDTH +#define _PXG_SYNG_VBLANK_CYC_REG_WIDTH +#define _PXG_SYNG_STAT_HCNT_REG_WIDTH +#define _PXG_SYNG_STAT_VCNT_REG_WIDTH +#define _PXG_SYNG_STAT_FCNT_REG_WIDTH +*/ +#define _PXG_SYNG_STAT_DONE_REG_WIDTH 1 +#define _PXG_TPG_MODE_REG_WIDTH 2 +/* +#define _PXG_TPG_HCNT_MASK_REG_WIDTH +#define _PXG_TPG_VCNT_MASK_REG_WIDTH +#define _PXG_TPG_XYCNT_MASK_REG_WIDTH +*/ +#define _PXG_TPG_HCNT_DELTA_REG_WIDTH 4 +#define _PXG_TPG_VCNT_DELTA_REG_WIDTH 4 +/* +#define _PXG_TPG_R1_REG_WIDTH +#define _PXG_TPG_G1_REG_WIDTH +#define _PXG_TPG_B1_REG_WIDTH +#define _PXG_TPG_R2_REG_WIDTH +#define _PXG_TPG_G2_REG_WIDTH +#define _PXG_TPG_B2_REG_WIDTH +*/ +#define _PXG_FIFO_DEPTH 2 +/* MISC */ +#define _PXG_ENABLE_REG_VAL 1 +#define _PXG_PRBS_ENABLE_REG_VAL 1 +#define _PXG_TPG_ENABLE_REG_VAL 2 +#define _PXG_SYNG_ENABLE_REG_VAL 4 +#define _PXG_FIFO_ENABLE_REG_VAL 8 +#define _PXG_PXL_BITS 14 +#define _PXG_INVALID_FLAG 0xDEADBEEF +#define _PXG_CAFE_FLAG 0xCAFEBABE + +#endif /* _PixelGen_SysBlock_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/hrt/ibuf_cntrl_defs.h b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/ibuf_cntrl_defs.h new file mode 100644 index 000000000..374466e6b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/ibuf_cntrl_defs.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ibuf_cntrl_defs_h_ +#define _ibuf_cntrl_defs_h_ + +#include +#include + +#define _IBUF_CNTRL_REG_ALIGN 4 +/* alignment of register banks, first bank are shared configuration and status registers: */ +#define _IBUF_CNTRL_PROC_REG_ALIGN 32 + +/* the actual amount of configuration registers per proc: */ +#define _IBUF_CNTRL_CONFIG_REGS_PER_PROC 18 +/* the actual amount of shared configuration registers: */ +#define _IBUF_CNTRL_CONFIG_REGS_NO_PROC 0 + +/* the actual amount of status registers per proc */ +#define _IBUF_CNTRL_STATUS_REGS_PER_PROC (_IBUF_CNTRL_CONFIG_REGS_PER_PROC + 10) +/* the actual amount shared status registers */ +#define _IBUF_CNTRL_STATUS_REGS_NO_PROC (_IBUF_CNTRL_CONFIG_REGS_NO_PROC + 2) + +/* time out bits, maximum time out value is 2^_IBUF_CNTRL_TIME_OUT_BITS - 1 */ +#define _IBUF_CNTRL_TIME_OUT_BITS 5 + +/* command token definition */ +#define _IBUF_CNTRL_CMD_TOKEN_LSB 0 +#define _IBUF_CNTRL_CMD_TOKEN_MSB 1 + +/* Str2MMIO defines */ +#define _IBUF_CNTRL_STREAM2MMIO_CMD_TOKEN_MSB _STREAM2MMIO_CMD_TOKEN_CMD_MSB +#define _IBUF_CNTRL_STREAM2MMIO_CMD_TOKEN_LSB _STREAM2MMIO_CMD_TOKEN_CMD_LSB +#define _IBUF_CNTRL_STREAM2MMIO_NUM_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _IBUF_CNTRL_STREAM2MMIO_ACK_EOF_BIT _STREAM2MMIO_PACK_ACK_EOF_BIT +#define _IBUF_CNTRL_STREAM2MMIO_ACK_TOKEN_VALID_BIT _STREAM2MMIO_ACK_TOKEN_VALID_BIT + +/* acknowledge token definition */ +#define _IBUF_CNTRL_ACK_TOKEN_STORES_IDX 0 +#define _IBUF_CNTRL_ACK_TOKEN_STORES_BITS 15 +#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX (_IBUF_CNTRL_ACK_TOKEN_STORES_BITS + _IBUF_CNTRL_ACK_TOKEN_STORES_IDX) +#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _IBUF_CNTRL_ACK_TOKEN_LSB _IBUF_CNTRL_ACK_TOKEN_STORES_IDX +#define _IBUF_CNTRL_ACK_TOKEN_MSB (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX - 1) +/* bit 31 indicates a valid ack: */ +#define _IBUF_CNTRL_ACK_TOKEN_VALID_BIT (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX) + +/*shared registers:*/ +#define _IBUF_CNTRL_RECALC_WORDS_STATUS 0 +#define _IBUF_CNTRL_ARBITERS_STATUS 1 + +#define _IBUF_CNTRL_SET_CRUN 2 /* NO PHYSICAL REGISTER!! Only used in HSS model */ + +/*register addresses for each proc: */ +#define _IBUF_CNTRL_CMD 0 +#define _IBUF_CNTRL_ACK 1 + +/* number of items (packets or words) per frame: */ +#define _IBUF_CNTRL_NUM_ITEMS_PER_STORE 2 + +/* number of stores (packets or words) per store/buffer: */ +#define _IBUF_CNTRL_NUM_STORES_PER_FRAME 3 + +/* the channel and command in the DMA */ +#define _IBUF_CNTRL_DMA_CHANNEL 4 +#define _IBUF_CNTRL_DMA_CMD 5 + +/* the start address and stride of the buffers */ +#define _IBUF_CNTRL_BUFFER_START_ADDRESS 6 +#define _IBUF_CNTRL_BUFFER_STRIDE 7 +#define _IBUF_CNTRL_BUFFER_END_ADDRESS 8 + +/* destination start address, stride and end address; should be the same as in the DMA */ +#define _IBUF_CNTRL_DEST_START_ADDRESS 9 +#define _IBUF_CNTRL_DEST_STRIDE 10 +#define _IBUF_CNTRL_DEST_END_ADDRESS 11 + +/* send a frame sync or not, default 1 */ +#define _IBUF_CNTRL_SYNC_FRAME 12 + +/* str2mmio cmds */ +#define _IBUF_CNTRL_STR2MMIO_SYNC_CMD 13 +#define _IBUF_CNTRL_STR2MMIO_STORE_CMD 14 + +/* num elems p word*/ +#define _IBUF_CNTRL_SHIFT_ITEMS 15 +#define _IBUF_CNTRL_ELEMS_P_WORD_IBUF 16 +#define _IBUF_CNTRL_ELEMS_P_WORD_DEST 17 + +/* STATUS */ +/* current frame and stores in buffer */ +#define _IBUF_CNTRL_CUR_STORES 18 +#define _IBUF_CNTRL_CUR_ACKS 19 + +/* current buffer and destination address for DMA cmd's */ +#define _IBUF_CNTRL_CUR_S2M_IBUF_ADDR 20 +#define _IBUF_CNTRL_CUR_DMA_IBUF_ADDR 21 +#define _IBUF_CNTRL_CUR_DMA_DEST_ADDR 22 +#define _IBUF_CNTRL_CUR_ISP_DEST_ADDR 23 + +#define _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND 24 + +#define _IBUF_CNTRL_MAIN_CNTRL_STATE 25 +#define _IBUF_CNTRL_DMA_SYNC_STATE 26 +#define _IBUF_CNTRL_ISP_SYNC_STATE 27 + +/*Commands: */ +#define _IBUF_CNTRL_CMD_STORE_FRAME_IDX 0 +#define _IBUF_CNTRL_CMD_ONLINE_IDX 1 + +/* initialize, copy st_addr to cur_addr etc */ +#define _IBUF_CNTRL_CMD_INITIALIZE 0 + +/* store an online frame (sync with ISP, use end cfg start, stride and end address: */ +#define _IBUF_CNTRL_CMD_STORE_ONLINE_FRAME ((1 << _IBUF_CNTRL_CMD_STORE_FRAME_IDX) | (1 << _IBUF_CNTRL_CMD_ONLINE_IDX)) + +/* store an offline frame (don't sync with ISP, requires start address as 2nd token, no end address: */ +#define _IBUF_CNTRL_CMD_STORE_OFFLINE_FRAME BIT(_IBUF_CNTRL_CMD_STORE_FRAME_IDX) + +/* false command token, should be different then commands. Use online bit, not store frame: */ +#define _IBUF_CNTRL_FALSE_ACK 2 + +#endif diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_common_defs.h b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_common_defs.h new file mode 100644 index 000000000..ac8be2d49 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_common_defs.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_common_defs_h_ +#define _css_receiver_2400_common_defs_h_ +#ifndef _mipi_backend_common_defs_h_ +#define _mipi_backend_common_defs_h_ + +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH 16 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */ + +/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit legacy */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB888 36 /* 10 0100 RGB888 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW6 40 /* 10 1000 RAW6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW7 41 /* 10 1001 RAW7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW8 42 /* 10 1010 RAW8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW10 43 /* 10 1011 RAW10 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW12 44 /* 10 1100 RAW12 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW14 45 /* 10 1101 RAW14 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_5 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_6 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_7 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_8 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_Emb 18 /* 01 0010 embedded eight bit non image data */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH1 8 /* 00 1000 Generic Short Packet Code 1 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH2 9 /* 00 1001 Generic Short Packet Code 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH3 10 /* 00 1010 Generic Short Packet Code 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH4 11 /* 00 1011 Generic Short Packet Code 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH5 12 /* 00 1100 Generic Short Packet Code 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH6 13 /* 00 1101 Generic Short Packet Code 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH7 14 /* 00 1110 Generic Short Packet Code 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +/* used reserved mipi positions for these */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38 + +//_HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 63 +#define _HRT_MIPI_BACKEND_FMT_TYPE_CUSTOM 63 + +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6 + +/* Definition of format_types at the interface CSS --> input_selector*/ +/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */ +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding + +/* definition for state machine of data FIFO for decode different type of data */ +#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9 +#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7 +#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7 + +#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */ + +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8 + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6 + +/* packet bit definition */ +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32 +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32 + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +/* +#define BE_CUST_EN_IDX 0 // 2bits +#define BE_CUST_EN_DATAID_IDX 2 // 6bits MIPI DATA ID +#define BE_CUST_EN_WIDTH 8 +#define BE_CUST_MODE_ALL 1 // Enable Custom Decoding for all DATA IDs +#define BE_CUST_MODE_ONE 3 // Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID + +// Data State config = {get_bits(6bits), valid(1bit)} // +#define BE_CUST_DATA_STATE_S0_IDX 0 // 7bits +#define BE_CUST_DATA_STATE_S1_IDX 8 //7 // 7bits +#define BE_CUST_DATA_STATE_S2_IDX 16//14 // 7bits / +#define BE_CUST_DATA_STATE_WIDTH 24//21 +#define BE_CUST_DATA_STATE_VALID_IDX 0 // 1bits +#define BE_CUST_DATA_STATE_GETBITS_IDX 1 // 6bits + +// Pixel Extractor config +#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 // 6bits +#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 6//5 // 5bits +#define BE_CUST_PIX_EXT_PIX_MASK_IDX 11//10 // 18bits +#define BE_CUST_PIX_EXT_PIX_EN_IDX 29 //28 // 1bits + +#define BE_CUST_PIX_EXT_WIDTH 30//29 + +// Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} +#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 // 4bits +#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 // 4bits +#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 // 4bits +#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 // 4bits +#define BE_CUST_PIX_VALID_EOP_WIDTH 16 +#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 // Normal (NO less get_bits case) Valid - 1bits +#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 // Normal (NO less get_bits case) EoP - 1bits +#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 // Especial (less get_bits case) Valid - 1bits +#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 // Especial (less get_bits case) EoP - 1bits + +*/ + +#endif /* _mipi_backend_common_defs_h_ */ +#endif /* _css_receiver_2400_common_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_defs.h b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_defs.h new file mode 100644 index 000000000..6fae1c262 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_defs.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _mipi_backend_defs_h +#define _mipi_backend_defs_h + +#include "mipi_backend_common_defs.h" + +#define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width + +#define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut + +// SH Backend Register IDs +#define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0 +#define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1 +//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX 2 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX 3 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX 4 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX 5 +#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX 6 +#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX 7 +#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX 8 +#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX 9 +#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX 10 +//// +#define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11 +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX 12 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX 13 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX 14 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX 15 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX 16 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX 17 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX 18 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX 19 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX 20 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX 21 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX 22 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX 23 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX 24 +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX 25 +//// +#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX 26 +#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX 27 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31 + +#define _HRT_MIPI_BACKEND_NOF_REGISTERS 32 // excluding the LP LUT entries + +#define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX 32 + +///////////////////////////////////////////////////////////////////////////////////////////////////// +#define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1 +//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH 32 +#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7 +#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH 9 +#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH 8 +#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH _HRT_MIPI_BACKEND_NOF_IRQS +#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0 +#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1 + 2 + 6 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7 + +///////////////////////////////////////////////////////////////////////////////////////////////////// + +#define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES 4 + +//#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration + +#define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH 2 +#define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 6 +#define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH + +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB 0 +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB + (pix_width) - 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) + (pix_width) - 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width) (_HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) + 1) + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +#define _HRT_MIPI_BACKEND_CUST_EN_IDX 0 /* 2bits */ +#define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ +#define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX 8 // 1 bit +#define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9 +#define _HRT_MIPI_BACKEND_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ +#define _HRT_MIPI_BACKEND_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ + +#define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1 + +/* Data State config = {get_bits(6bits), valid(1bit)} */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX 16 /* was 14 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH 24 /* was 21*/ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ + +/* Pixel Extractor config */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 6bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_ALIGN_IDX 6 /* 5bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_MASK_IDX 11 /* was 10 18bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_EN_IDX 29 /* was 28 1bits */ + +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_WIDTH 30 /* was 29 */ + +/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16 +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ + +/*************************************************************************************************/ +/* MIPI backend output streaming interface definition */ +/* These parameters define the fields within the streaming bus. These should also be used by the */ +/* subsequent block, ie stream2mmio. */ +/*************************************************************************************************/ +/* The pipe backend - stream2mmio should be design time configurable in */ +/* PixWidth - Number of bits per pixel */ +/* PPC - Pixel per Clocks */ +/* NumSids - Max number of source Ids (ifc's) and derived from that: */ +/* SidWidth - Number of bits required for the sid parameter */ +/* In order to keep this configurability, below Macro's have these as a parameter */ +/*************************************************************************************************/ + +#define HRT_MIPI_BACKEND_STREAM_EOP_BIT 0 +#define HRT_MIPI_BACKEND_STREAM_SOP_BIT 1 +#define HRT_MIPI_BACKEND_STREAM_EOF_BIT 2 +#define HRT_MIPI_BACKEND_STREAM_SOF_BIT 3 +#define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT 4 +#define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT + (sid_width) - 1) +#define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) + 1 + p) + +#define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, ppc) + ((pix_width) * p)) +#define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) + (pix_width) - 1) + +#if 0 +//#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14 +//#define HRT_MIPI_BACKEND_STREAM_CHID_BITS 4 +//#define HRT_MIPI_BACKEND_STREAM_PPC 4 +#endif + +#define HRT_MIPI_BACKEND_STREAM_BITS(sid_width, ppc, pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, (ppc - 1)) + 1) + +/* SP and LP LUT BIT POSITIONS */ +#define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0 +#define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1 +#define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT + (sid_width) - 1) // 1 + (4) - 1 = 4 +#define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 // 5 +#define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH - 1 // 6 +#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 +#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12 + +/* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */ + +#define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 +#define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) + 1 // 13 + +// temp solution +//#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11 +//#define HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT + 1 // 12 +//#define HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 25 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT + 1 // 26 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 39 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT + 1 // 40 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67 + +// vc hidden in pixb data (passed as raw12 the pipe) +#define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, 1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36 +#define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) + 1 // 37 + +#endif /* _mipi_backend_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/hrt/rx_csi_defs.h b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/rx_csi_defs.h new file mode 100644 index 000000000..d0e5b54d1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/rx_csi_defs.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _csi_rx_defs_h +#define _csi_rx_defs_h + +//#include "rx_csi_common_defs.h" + +#define MIPI_PKT_DATA_WIDTH 32 +//#define CLK_CROSSING_FIFO_DEPTH 16 +#define _CSI_RX_REG_ALIGN 4 + +//define number of IRQ (see below for definition of each IRQ bits) +#define CSI_RX_NOF_IRQS_BYTE_DOMAIN 11 +#define CSI_RX_NOF_IRQS_ISP_DOMAIN 15 // CSI_RX_NOF_IRQS_BYTE_DOMAIN + remaining from Dphy_rx already on ISP clock domain + +// REGISTER DESCRIPTION +//#define _HRT_CSI_RX_SOFTRESET_REG_IDX 0 +#define _HRT_CSI_RX_ENABLE_REG_IDX 0 +#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX 1 +#define _HRT_CSI_RX_ERROR_HANDLING_REG_IDX 2 +#define _HRT_CSI_RX_STATUS_REG_IDX 3 +#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 4 +#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 5 +//#define _HRT_CSI_RX_IRQ_CONFIG_REG_IDX 6 +#define _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX 6 +#define _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX 7 +#define _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx)) +#define _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx) + 1) + +#define _HRT_CSI_RX_NOF_REGISTERS(nof_dlanes) (8 + 2 * (nof_dlanes)) + +//#define _HRT_CSI_RX_SOFTRESET_REG_WIDTH 1 +#define _HRT_CSI_RX_ENABLE_REG_WIDTH 1 +#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_WIDTH 3 +#define _HRT_CSI_RX_ERROR_HANDLING_REG_WIDTH 4 +#define _HRT_CSI_RX_STATUS_REG_WIDTH 1 +#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_WIDTH 8 +#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_WIDTH 24 +#define _HRT_CSI_RX_IRQ_CONFIG_REG_WIDTH (CSI_RX_NOF_IRQS_ISP_DOMAIN) +#define _HRT_CSI_RX_DLY_CNT_REG_WIDTH 24 +//#define _HRT_CSI_RX_IRQ_STATUS_REG_WIDTH NOF_IRQS +//#define _HRT_CSI_RX_IRQ_CLEAR_REG_WIDTH 0 + +#define ONE_LANE_ENABLED 0 +#define TWO_LANES_ENABLED 1 +#define THREE_LANES_ENABLED 2 +#define FOUR_LANES_ENABLED 3 + +// Error handling reg bit positions +#define ERR_DECISION_BIT 0 +#define DISC_RESERVED_SP_BIT 1 +#define DISC_RESERVED_LP_BIT 2 +#define DIS_INCOMP_PKT_CHK_BIT 3 + +#define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_POSEDGE 0 +#define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_ORIGINAL 1 + +// Interrupt bits +#define _HRT_RX_CSI_IRQ_SINGLE_PH_ERROR_CORRECTED 0 +#define _HRT_RX_CSI_IRQ_MULTIPLE_PH_ERROR_DETECTED 1 +#define _HRT_RX_CSI_IRQ_PAYLOAD_CHECKSUM_ERROR 2 +#define _HRT_RX_CSI_IRQ_FIFO_FULL_ERROR 3 +#define _HRT_RX_CSI_IRQ_RESERVED_SP_DETECTED 4 +#define _HRT_RX_CSI_IRQ_RESERVED_LP_DETECTED 5 +//#define _HRT_RX_CSI_IRQ_PREMATURE_SOP 6 +#define _HRT_RX_CSI_IRQ_INCOMPLETE_PACKET 6 +#define _HRT_RX_CSI_IRQ_FRAME_SYNC_ERROR 7 +#define _HRT_RX_CSI_IRQ_LINE_SYNC_ERROR 8 +#define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_ERROR 9 +#define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_SYNC_ERROR 10 + +#define _HRT_RX_CSI_IRQ_DLANE_ESC_ERROR 11 +#define _HRT_RX_CSI_IRQ_DLANE_TRIGGERESC 12 +#define _HRT_RX_CSI_IRQ_DLANE_ULPSESC 13 +#define _HRT_RX_CSI_IRQ_CLANE_ULPSCLKNOT 14 + +/* OLD ARASAN FRONTEND IRQs +#define _HRT_RX_CSI_IRQ_OVERRUN_BIT 0 +#define _HRT_RX_CSI_IRQ_RESERVED_BIT 1 +#define _HRT_RX_CSI_IRQ_SLEEP_MODE_ENTRY_BIT 2 +#define _HRT_RX_CSI_IRQ_SLEEP_MODE_EXIT_BIT 3 +#define _HRT_RX_CSI_IRQ_ERR_SOT_HS_BIT 4 +#define _HRT_RX_CSI_IRQ_ERR_SOT_SYNC_HS_BIT 5 +#define _HRT_RX_CSI_IRQ_ERR_CONTROL_BIT 6 +#define _HRT_RX_CSI_IRQ_ERR_ECC_DOUBLE_BIT 7 +#define _HRT_RX_CSI_IRQ_ERR_ECC_CORRECTED_BIT 8 +#define _HRT_RX_CSI_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 +#define _HRT_RX_CSI_IRQ_ERR_CRC_BIT 10 +#define _HRT_RX_CSI_IRQ_ERR_ID_BIT 11 +#define _HRT_RX_CSI_IRQ_ERR_FRAME_SYNC_BIT 12 +#define _HRT_RX_CSI_IRQ_ERR_FRAME_DATA_BIT 13 +#define _HRT_RX_CSI_IRQ_DATA_TIMEOUT_BIT 14 +#define _HRT_RX_CSI_IRQ_ERR_ESCAPE_BIT 15 +#define _HRT_RX_CSI_IRQ_ERR_LINE_SYNC_BIT 16 +*/ + +////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE0 0 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE1 1 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE2 2 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE3 3 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE0 4 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE1 5 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE2 6 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE3 7 + +////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE0 0 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE1 1 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE2 2 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE3 3 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE0 4 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE0 5 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE0 6 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE0 7 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE1 8 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE1 9 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE1 10 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE1 11 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE2 12 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE2 13 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE2 14 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE2 15 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE3 16 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE3 17 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE3 18 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE3 19 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE0 20 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE1 21 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE2 22 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE3 23 + +/*********************************************************/ +/*** Relevant declarations from rx_csi_common_defs.h *****/ +/*********************************************************/ +/* packet bit definition */ +#define _HRT_RX_CSI_PKT_SOP_BITPOS 32 +#define _HRT_RX_CSI_PKT_EOP_BITPOS 33 +#define _HRT_RX_CSI_PKT_PAYLOAD_BITPOS 0 +#define _HRT_RX_CSI_PH_CH_ID_BITPOS 22 +#define _HRT_RX_CSI_PH_FMT_ID_BITPOS 16 +#define _HRT_RX_CSI_PH_DATA_FIELD_BITPOS 0 + +#define _HRT_RX_CSI_PKT_SOP_BITS 1 +#define _HRT_RX_CSI_PKT_EOP_BITS 1 +#define _HRT_RX_CSI_PKT_PAYLOAD_BITS 32 +#define _HRT_RX_CSI_PH_CH_ID_BITS 2 +#define _HRT_RX_CSI_PH_FMT_ID_BITS 6 +#define _HRT_RX_CSI_PH_DATA_FIELD_BITS 16 + +/* Definition of data format ID at the interface CSS_receiver units */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ + +#endif /* _csi_rx_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/hrt/stream2mmio_defs.h b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/stream2mmio_defs.h new file mode 100644 index 000000000..e17783f96 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/hrt/stream2mmio_defs.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _STREAM2MMMIO_DEFS_H +#define _STREAM2MMMIO_DEFS_H + +#include + +#define _STREAM2MMIO_REG_ALIGN 4 + +#define _STREAM2MMIO_COMMAND_REG_ID 0 +#define _STREAM2MMIO_ACKNOWLEDGE_REG_ID 1 +#define _STREAM2MMIO_PIX_WIDTH_ID_REG_ID 2 +#define _STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */ +#define _STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */ +#define _STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/ +#define _STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */ +#define _STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */ +#define _STREAM2MMIO_REGS_PER_SID 8 + +#define _STREAM2MMIO_SID_REG_OFFSET 8 +#define _STREAM2MMIO_MAX_NOF_SIDS 64 /* value used in hss model */ + +/* command token definition */ +#define _STREAM2MMIO_CMD_TOKEN_CMD_LSB 0 /* bits 1-0 is for the command field */ +#define _STREAM2MMIO_CMD_TOKEN_CMD_MSB 1 + +#define _STREAM2MMIO_CMD_TOKEN_WIDTH (_STREAM2MMIO_CMD_TOKEN_CMD_MSB + 1 - _STREAM2MMIO_CMD_TOKEN_CMD_LSB) + +#define _STREAM2MMIO_CMD_TOKEN_STORE_WORDS 0 /* command for storing a number of output words indicated by reg _STREAM2MMIO_NUM_ITEMS */ +#define _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS 1 /* command for storing a number of packets indicated by reg _STREAM2MMIO_NUM_ITEMS */ +#define _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME 2 /* command for waiting for a frame start */ + +/* acknowledges from packer module */ +/* fields: eof - indicates whether last (short) packet received was an eof packet */ +/* eop - indicates whether command has ended due to packet end or due to no of words requested has been received */ +/* count - indicates number of words stored */ +#define _STREAM2MMIO_PACK_NUM_ITEMS_BITS 16 +#define _STREAM2MMIO_PACK_ACK_EOP_BIT _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _STREAM2MMIO_PACK_ACK_EOF_BIT (_STREAM2MMIO_PACK_ACK_EOP_BIT + 1) + +/* acknowledge token definition */ +#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_LSB 0 /* bits 3-0 is for the command field */ +#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_MSB (_STREAM2MMIO_PACK_NUM_ITEMS_BITS - 1) +#define _STREAM2MMIO_ACK_TOKEN_EOP_BIT _STREAM2MMIO_PACK_ACK_EOP_BIT +#define _STREAM2MMIO_ACK_TOKEN_EOF_BIT _STREAM2MMIO_PACK_ACK_EOF_BIT +#define _STREAM2MMIO_ACK_TOKEN_VALID_BIT (_STREAM2MMIO_ACK_TOKEN_EOF_BIT + 1) /* this bit indicates a valid ack */ +/* if there is no valid ack, a read */ +/* on the ack register returns 0 */ +#define _STREAM2MMIO_ACK_TOKEN_WIDTH (_STREAM2MMIO_ACK_TOKEN_VALID_BIT + 1) + +/* commands for packer module */ +#define _STREAM2MMIO_PACK_CMD_STORE_WORDS 0 +#define _STREAM2MMIO_PACK_CMD_STORE_LONG_PACKET 1 +#define _STREAM2MMIO_PACK_CMD_STORE_SHORT_PACKET 2 + +#endif /* _STREAM2MMIO_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/ibuf_ctrl_global.h b/drivers/staging/media/atomisp/pci/css_2401_system/ibuf_ctrl_global.h new file mode 100644 index 000000000..56c5ed89b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/ibuf_ctrl_global.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_GLOBAL_H_INCLUDED__ +#define __IBUF_CTRL_GLOBAL_H_INCLUDED__ + +#include + +#include /* _IBUF_CNTRL_RECALC_WORDS_STATUS, + * _IBUF_CNTRL_ARBITERS_STATUS, + * _IBUF_CNTRL_PROC_REG_ALIGN, + * etc. + */ + +/* Definition of contents of main controller state register is lacking + * in ibuf_cntrl_defs.h, so define these here: + */ +#define _IBUF_CNTRL_MAIN_CNTRL_FSM_MASK 0xf +#define _IBUF_CNTRL_MAIN_CNTRL_FSM_NEXT_COMMAND_CHECK 0x9 +#define _IBUF_CNTRL_MAIN_CNTRL_MEM_INP_BUF_ALLOC BIT(8) +#define _IBUF_CNTRL_DMA_SYNC_WAIT_FOR_SYNC 1 +#define _IBUF_CNTRL_DMA_SYNC_FSM_WAIT_FOR_ACK (0x3 << 1) + +struct isp2401_ib_buffer_s { + u32 start_addr; /* start address of the buffer in the + * "input-buffer hardware block" + */ + + u32 stride; /* stride per buffer line (in bytes) */ + u32 lines; /* lines in the buffer */ +}; +typedef struct isp2401_ib_buffer_s isp2401_ib_buffer_t; + +typedef struct ibuf_ctrl_cfg_s ibuf_ctrl_cfg_t; +struct ibuf_ctrl_cfg_s { + bool online; + + struct { + /* DMA configuration */ + u32 channel; + u32 cmd; /* must be _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND */ + + /* DMA reconfiguration */ + u32 shift_returned_items; + u32 elems_per_word_in_ibuf; + u32 elems_per_word_in_dest; + } dma_cfg; + + isp2401_ib_buffer_t ib_buffer; + + struct { + u32 stride; + u32 start_addr; + u32 lines; + } dest_buf_cfg; + + u32 items_per_store; + u32 stores_per_frame; + + struct { + u32 sync_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME */ + u32 store_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS */ + } stream2mmio_cfg; +}; + +extern const u32 N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID]; + +#endif /* __IBUF_CTRL_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/isys_dma_global.h b/drivers/staging/media/atomisp/pci/css_2401_system/isys_dma_global.h new file mode 100644 index 000000000..f423f3413 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/isys_dma_global.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_GLOBAL_H_INCLUDED__ +#define __ISYS_DMA_GLOBAL_H_INCLUDED__ + +#include + +#define HIVE_ISYS2401_DMA_IBUF_DDR_CONN 0 +#define HIVE_ISYS2401_DMA_IBUF_VMEM_CONN 1 +#define _DMA_V2_ZERO_EXTEND 0 +#define _DMA_V2_SIGN_EXTEND 1 + +#define _DMA_ZERO_EXTEND _DMA_V2_ZERO_EXTEND +#define _DMA_SIGN_EXTEND _DMA_V2_SIGN_EXTEND + +/******************************************************** + * + * DMA Port. + * + * The DMA port definition for the input system + * 2401 DMA is the duplication of the DMA port + * definition for the CSS system DMA. It is duplicated + * here just as the temporal step before the device library + * is available. The device library is suppose to provide + * the capability of reusing the control interface of the + * same device prototypes. The refactor team will work on + * this, right? + * + ********************************************************/ +typedef struct isys2401_dma_port_cfg_s isys2401_dma_port_cfg_t; +struct isys2401_dma_port_cfg_s { + u32 stride; + u32 elements; + u32 cropping; + u32 width; +}; + +/* end of DMA Port */ + +/************************************************ + * + * DMA Device. + * + * The DMA device definition for the input system + * 2401 DMA is the duplicattion of the DMA device + * definition for the CSS system DMA. It is duplicated + * here just as the temporal step before the device library + * is available. The device library is suppose to provide + * the capability of reusing the control interface of the + * same device prototypes. The refactor team will work on + * this, right? + * + ************************************************/ +typedef enum { + isys2401_dma_ibuf_to_ddr_connection = HIVE_ISYS2401_DMA_IBUF_DDR_CONN, + isys2401_dma_ibuf_to_vmem_connection = HIVE_ISYS2401_DMA_IBUF_VMEM_CONN +} isys2401_dma_connection; + +typedef enum { + isys2401_dma_zero_extension = _DMA_ZERO_EXTEND, + isys2401_dma_sign_extension = _DMA_SIGN_EXTEND +} isys2401_dma_extension; + +typedef struct isys2401_dma_cfg_s isys2401_dma_cfg_t; +struct isys2401_dma_cfg_s { + isys2401_dma_channel channel; + isys2401_dma_connection connection; + isys2401_dma_extension extension; + u32 height; +}; + +/* end of DMA Device */ + +/* isys2401_dma_channel limits per DMA ID */ +extern const isys2401_dma_channel +N_ISYS2401_DMA_CHANNEL_PROCS[N_ISYS2401_DMA_ID]; + +#endif /* __ISYS_DMA_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/isys_irq_global.h b/drivers/staging/media/atomisp/pci/css_2401_system/isys_irq_global.h new file mode 100644 index 000000000..a81e4d13a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/isys_irq_global.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_GLOBAL_H__ +#define __ISYS_IRQ_GLOBAL_H__ + +#if defined(ISP2401) + +/* Register offset/index from base location */ +#define ISYS_IRQ_EDGE_REG_IDX (0) +#define ISYS_IRQ_MASK_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 1) +#define ISYS_IRQ_STATUS_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 2) +#define ISYS_IRQ_CLEAR_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 3) +#define ISYS_IRQ_ENABLE_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 4) +#define ISYS_IRQ_LEVEL_NO_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 5) + +/* Register values */ +#define ISYS_IRQ_MASK_REG_VALUE (0xFFFF) +#define ISYS_IRQ_CLEAR_REG_VALUE (0xFFFF) +#define ISYS_IRQ_ENABLE_REG_VALUE (0xFFFF) + +#endif /* defined(ISP2401) */ + +#endif /* __ISYS_IRQ_GLOBAL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/isys_stream2mmio_global.h b/drivers/staging/media/atomisp/pci/css_2401_system/isys_stream2mmio_global.h new file mode 100644 index 000000000..0611047ea --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/isys_stream2mmio_global.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ + +#include + +typedef struct stream2mmio_cfg_s stream2mmio_cfg_t; +struct stream2mmio_cfg_s { + u32 bits_per_pixel; + u32 enable_blocking; +}; + +/* Stream2MMIO limits per ID*/ +/* + * Stream2MMIO 0 has 8 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID]. + * + * Stream2MMIO 1 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID]. + * + * Stream2MMIO 2 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID]. + */ +extern const stream2mmio_sid_ID_t N_STREAM2MMIO_SID_PROCS[N_STREAM2MMIO_ID]; + +#endif /* __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_2401_system/pixelgen_global.h b/drivers/staging/media/atomisp/pci/css_2401_system/pixelgen_global.h new file mode 100644 index 000000000..f131f03cb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_2401_system/pixelgen_global.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_GLOBAL_H_INCLUDED__ +#define __PIXELGEN_GLOBAL_H_INCLUDED__ + +#include + +/** + * Pixel-generator. ("pixelgen_global.h") + */ +/* + * Duplicates "sync_generator_cfg_t" in "input_system_global.h". + */ +typedef struct isp2401_sync_generator_cfg_s isp2401_sync_generator_cfg_t; +struct isp2401_sync_generator_cfg_s { + u32 hblank_cycles; + u32 vblank_cycles; + u32 pixels_per_clock; + u32 nr_of_frames; + u32 pixels_per_line; + u32 lines_per_frame; +}; + +typedef enum { + PIXELGEN_TPG_MODE_RAMP = 0, + PIXELGEN_TPG_MODE_CHBO, + PIXELGEN_TPG_MODE_MONO, + N_PIXELGEN_TPG_MODE +} pixelgen_tpg_mode_t; + +/* + * "pixelgen_tpg_cfg_t" duplicates parts of + * "tpg_cfg_t" in "input_system_global.h". + */ +typedef struct pixelgen_tpg_cfg_s pixelgen_tpg_cfg_t; +struct pixelgen_tpg_cfg_s { + pixelgen_tpg_mode_t mode; /* CHBO, MONO */ + + struct { + /* be used by CHBO and MON */ + u32 R1; + u32 G1; + u32 B1; + + /* be used by CHBO only */ + u32 R2; + u32 G2; + u32 B2; + } color_cfg; + + struct { + u32 h_mask; /* horizontal mask */ + u32 v_mask; /* vertical mask */ + u32 hv_mask; /* horizontal+vertical mask? */ + } mask_cfg; + + struct { + s32 h_delta; /* horizontal delta? */ + s32 v_delta; /* vertical delta? */ + } delta_cfg; + + isp2401_sync_generator_cfg_t sync_gen_cfg; +}; + +/* + * "pixelgen_prbs_cfg_t" duplicates parts of + * prbs_cfg_t" in "input_system_global.h". + */ +typedef struct pixelgen_prbs_cfg_s pixelgen_prbs_cfg_t; +struct pixelgen_prbs_cfg_s { + s32 seed0; + s32 seed1; + + isp2401_sync_generator_cfg_t sync_gen_cfg; +}; + +/* end of Pixel-generator: TPG. ("pixelgen_global.h") */ +#endif /* __PIXELGEN_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/css_receiver_2400_common_defs.h b/drivers/staging/media/atomisp/pci/css_receiver_2400_common_defs.h new file mode 100644 index 000000000..d2c39f960 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_receiver_2400_common_defs.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_common_defs_h_ +#define _css_receiver_2400_common_defs_h_ +#ifndef _mipi_backend_common_defs_h_ +#define _mipi_backend_common_defs_h_ + +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH 16 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */ + +/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit legacy */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB888 36 /* 10 0100 RGB888 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW6 40 /* 10 1000 RAW6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW7 41 /* 10 1001 RAW7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW8 42 /* 10 1010 RAW8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW10 43 /* 10 1011 RAW10 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW12 44 /* 10 1100 RAW12 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW14 45 /* 10 1101 RAW14 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_5 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_6 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_7 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_8 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_Emb 18 /* 01 0010 embedded eight bit non image data */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH1 8 /* 00 1000 Generic Short Packet Code 1 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH2 9 /* 00 1001 Generic Short Packet Code 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH3 10 /* 00 1010 Generic Short Packet Code 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH4 11 /* 00 1011 Generic Short Packet Code 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH5 12 /* 00 1100 Generic Short Packet Code 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH6 13 /* 00 1101 Generic Short Packet Code 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH7 14 /* 00 1110 Generic Short Packet Code 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +/* used reserved mipi positions for these */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38 + +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6 + +/* Definition of format_types at the interface CSS --> input_selector*/ +/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */ +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding + +/* definition for state machine of data FIFO for decode different type of data */ +#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9 +#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7 +#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7 + +#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */ + +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8 + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6 + +/* packet bit definition */ +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32 +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32 + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +#define BE_CUST_EN_IDX 0 /* 2bits */ +#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ +#define BE_CUST_EN_WIDTH 8 +#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ +#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ + +/* Data State config = {get_bits(6bits), valid(1bit)} */ +#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ +#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */ +#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */ +#define BE_CUST_DATA_STATE_WIDTH 21 +#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ +#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ + +/* Pixel Extractor config */ +#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */ +#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */ +#define BE_CUST_PIX_EXT_WIDTH 29 + +/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ +#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_WIDTH 16 +#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ + +#endif /* _mipi_backend_common_defs_h_ */ +#endif /* _css_receiver_2400_common_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/css_receiver_2400_defs.h b/drivers/staging/media/atomisp/pci/css_receiver_2400_defs.h new file mode 100644 index 000000000..180ff7cd9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_receiver_2400_defs.h @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_defs_h_ +#define _css_receiver_2400_defs_h_ + +#include "css_receiver_2400_common_defs.h" + +#define CSS_RECEIVER_DATA_WIDTH 8 +#define CSS_RECEIVER_RX_TRIG 4 +#define CSS_RECEIVER_RF_WORD 32 +#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10 +#define CSS_RECEIVER_CSI_RF_ADDR 4 +#define CSS_RECEIVER_DATA_OUT 12 +#define CSS_RECEIVER_CHN_NO 2 +#define CSS_RECEIVER_DWORD_CNT 11 +#define CSS_RECEIVER_FORMAT_TYP 5 +#define CSS_RECEIVER_HRESPONSE 2 +#define CSS_RECEIVER_STATE_WIDTH 3 +#define CSS_RECEIVER_FIFO_DAT 32 +#define CSS_RECEIVER_CNT_VAL 2 +#define CSS_RECEIVER_PRED10_VAL 10 +#define CSS_RECEIVER_PRED12_VAL 12 +#define CSS_RECEIVER_CNT_WIDTH 8 +#define CSS_RECEIVER_WORD_CNT 16 +#define CSS_RECEIVER_PIXEL_LEN 6 +#define CSS_RECEIVER_PIXEL_CNT 5 +#define CSS_RECEIVER_COMP_8_BIT 8 +#define CSS_RECEIVER_COMP_7_BIT 7 +#define CSS_RECEIVER_COMP_6_BIT 6 + +#define CSI_CONFIG_WIDTH 4 + +/* division of gen_short data, ch_id and fmt_type over streaming data interface */ +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1) + +#define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4 +#define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4 + +#define hrt_css_receiver_2400_4_lane_port_offset 0x100 +#define hrt_css_receiver_2400_1_lane_port_offset 0x200 +#define hrt_css_receiver_2400_2_lane_port_offset 0x300 +#define hrt_css_receiver_2400_backend_port_offset 0x100 + +#define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3 +#define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4 +#define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16 +#define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25 +#define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26 +#define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27 +#define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28 + +/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */ +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13 +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16 + +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun" +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data" +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync" + +/* Bits for CSI2_DEVICE_READY register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7 + +/* Bits for CSI2_FUNC_PROG register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19 + +/* Bits for INIT_COUNT register */ +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0 +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16 + +/* Bits for COUNT registers */ +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8 + +/* Bits for RAW116_18_DATAID register */ +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6 + +/* Bits for COMP_FORMAT register, this selects the compression data format */ +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8 +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS) +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8 + +/* Bits for COMP_PREDICT register, this selects the predictor algorithm */ +#define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_PREDICT_1 1 +#define _HRT_CSS_RECEIVER_2400_PREDICT_2 2 + +/* Number of bits used for the delay registers */ +#define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8 + +/* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */ +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2 + +/* BITS for backend RAW16 and RAW 18 registers */ + +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1 + +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1 + +/* These hsync and vsync values are for HSS simulation only */ +#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16) +#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17) + +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1) + +// SH Backend Register IDs +#define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */ + +#define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28 + +#define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8 + +#endif /* _css_receiver_2400_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/css_trace.h b/drivers/staging/media/atomisp/pci/css_trace.h new file mode 100644 index 000000000..d2ce50fcf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/css_trace.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSS_TRACE_H_ +#define __CSS_TRACE_H_ + +#include +#include "sh_css_internal.h" /* for SH_CSS_MAX_SP_THREADS */ + +/* + structs and constants for tracing +*/ + +/* one tracer item: major, minor and counter. The counter value can be used for GP data */ +struct trace_item_t { + u8 major; + u8 minor; + u16 counter; +}; + +#define MAX_SCRATCH_DATA 4 +#define MAX_CMD_DATA 2 + +/* trace header: holds the version and the topology of the tracer. */ +struct trace_header_t { + /* 1st dword: descriptor */ + u8 version; + u8 max_threads; + u16 max_tracer_points; + /* 2nd field: command + data */ + /* 2nd dword */ + u32 command; + /* 3rd & 4th dword */ + u32 data[MAX_CMD_DATA]; + /* 3rd field: debug pointer */ + /* 5th & 6th dword: debug pointer mechanism */ + u32 debug_ptr_signature; + u32 debug_ptr_value; + /* Rest of the header: status & scratch data */ + u8 thr_status_byte[SH_CSS_MAX_SP_THREADS]; + u16 thr_status_word[SH_CSS_MAX_SP_THREADS]; + u32 thr_status_dword[SH_CSS_MAX_SP_THREADS]; + u32 scratch_debug[MAX_SCRATCH_DATA]; +}; + +/* offsets for master_port read/write */ +#define HDR_HDR_OFFSET 0 /* offset of the header */ +#define HDR_COMMAND_OFFSET offsetof(struct trace_header_t, command) +#define HDR_DATA_OFFSET offsetof(struct trace_header_t, data) +#define HDR_DEBUG_SIGNATURE_OFFSET offsetof(struct trace_header_t, debug_ptr_signature) +#define HDR_DEBUG_POINTER_OFFSET offsetof(struct trace_header_t, debug_ptr_value) +#define HDR_STATUS_OFFSET offsetof(struct trace_header_t, thr_status_byte) +#define HDR_STATUS_OFFSET_BYTE offsetof(struct trace_header_t, thr_status_byte) +#define HDR_STATUS_OFFSET_WORD offsetof(struct trace_header_t, thr_status_word) +#define HDR_STATUS_OFFSET_DWORD offsetof(struct trace_header_t, thr_status_dword) +#define HDR_STATUS_OFFSET_SCRATCH offsetof(struct trace_header_t, scratch_debug) + +/* +Trace version history: + 1: initial version, hdr = descr, command & ptr. + 2: added ISP + 24-bit fields. + 3: added thread ID. + 4: added status in header. +*/ +#define TRACER_VER 4 + +#define TRACE_BUFF_ADDR 0xA000 +#define TRACE_BUFF_SIZE 0x1000 /* 4K allocated */ + +#define TRACE_ENABLE_SP0 0 +#define TRACE_ENABLE_SP1 0 +#define TRACE_ENABLE_ISP 0 + +enum TRACE_CORE_ID { + TRACE_SP0_ID, + TRACE_SP1_ID, + TRACE_ISP_ID +}; + +/* TODO: add timing format? */ +enum TRACE_DUMP_FORMAT { + TRACE_DUMP_FORMAT_POINT_NO_TID, + TRACE_DUMP_FORMAT_VALUE24, + TRACE_DUMP_FORMAT_VALUE24_TIMING, + TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA, + TRACE_DUMP_FORMAT_POINT +}; + +/* currently divided as follows:*/ +#if (TRACE_ENABLE_SP0 + TRACE_ENABLE_SP1 + TRACE_ENABLE_ISP == 3) +/* can be divided as needed */ +#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE / 4) +#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE / 4) +#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE / 2) +#elif (TRACE_ENABLE_SP0 + TRACE_ENABLE_SP1 + TRACE_ENABLE_ISP == 2) +#if TRACE_ENABLE_SP0 +#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE / 2) +#else +#define TRACE_SP0_SIZE (0) +#endif +#if TRACE_ENABLE_SP1 +#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE / 2) +#else +#define TRACE_SP1_SIZE (0) +#endif +#if TRACE_ENABLE_ISP +#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE / 2) +#else +#define TRACE_ISP_SIZE (0) +#endif +#elif (TRACE_ENABLE_SP0 + TRACE_ENABLE_SP1 + TRACE_ENABLE_ISP == 1) +#if TRACE_ENABLE_SP0 +#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE) +#else +#define TRACE_SP0_SIZE (0) +#endif +#if TRACE_ENABLE_SP1 +#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE) +#else +#define TRACE_SP1_SIZE (0) +#endif +#if TRACE_ENABLE_ISP +#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE) +#else +#define TRACE_ISP_SIZE (0) +#endif +#else +#define TRACE_SP0_SIZE (0) +#define TRACE_SP1_SIZE (0) +#define TRACE_ISP_SIZE (0) +#endif + +#define TRACE_SP0_ADDR (TRACE_BUFF_ADDR) +#define TRACE_SP1_ADDR (TRACE_SP0_ADDR + TRACE_SP0_SIZE) +#define TRACE_ISP_ADDR (TRACE_SP1_ADDR + TRACE_SP1_SIZE) + +/* check if it's a legal division */ +#if (TRACE_BUFF_SIZE < TRACE_SP0_SIZE + TRACE_SP1_SIZE + TRACE_ISP_SIZE) +#error trace sizes are not divided correctly and are above limit +#endif + +#define TRACE_SP0_HEADER_ADDR (TRACE_SP0_ADDR) +#define TRACE_SP0_HEADER_SIZE (sizeof(struct trace_header_t)) +#define TRACE_SP0_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_SP0_DATA_ADDR (TRACE_SP0_HEADER_ADDR + TRACE_SP0_HEADER_SIZE) +#define TRACE_SP0_DATA_SIZE (TRACE_SP0_SIZE - TRACE_SP0_HEADER_SIZE) +#define TRACE_SP0_MAX_POINTS (TRACE_SP0_DATA_SIZE / TRACE_SP0_ITEM_SIZE) + +#define TRACE_SP1_HEADER_ADDR (TRACE_SP1_ADDR) +#define TRACE_SP1_HEADER_SIZE (sizeof(struct trace_header_t)) +#define TRACE_SP1_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_SP1_DATA_ADDR (TRACE_SP1_HEADER_ADDR + TRACE_SP1_HEADER_SIZE) +#define TRACE_SP1_DATA_SIZE (TRACE_SP1_SIZE - TRACE_SP1_HEADER_SIZE) +#define TRACE_SP1_MAX_POINTS (TRACE_SP1_DATA_SIZE / TRACE_SP1_ITEM_SIZE) + +#define TRACE_ISP_HEADER_ADDR (TRACE_ISP_ADDR) +#define TRACE_ISP_HEADER_SIZE (sizeof(struct trace_header_t)) +#define TRACE_ISP_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_ISP_DATA_ADDR (TRACE_ISP_HEADER_ADDR + TRACE_ISP_HEADER_SIZE) +#define TRACE_ISP_DATA_SIZE (TRACE_ISP_SIZE - TRACE_ISP_HEADER_SIZE) +#define TRACE_ISP_MAX_POINTS (TRACE_ISP_DATA_SIZE / TRACE_ISP_ITEM_SIZE) + +/* common majors */ +/* SP0 */ +#define MAJOR_MAIN 1 +#define MAJOR_ISP_STAGE_ENTRY 2 +#define MAJOR_DMA_PRXY 3 +#define MAJOR_START_ISP 4 +/* SP1 */ +#define MAJOR_OBSERVER_ISP0_EVENT 21 +#define MAJOR_OBSERVER_OUTPUT_FORM_EVENT 22 +#define MAJOR_OBSERVER_OUTPUT_SCAL_EVENT 23 +#define MAJOR_OBSERVER_IF_ACK 24 +#define MAJOR_OBSERVER_SP0_EVENT 25 +#define MAJOR_OBSERVER_SP_TERMINATE_EVENT 26 +#define MAJOR_OBSERVER_DMA_ACK 27 +#define MAJOR_OBSERVER_ACC_ACK 28 + +#define DEBUG_PTR_SIGNATURE 0xABCD /* signature for the debug parameter pointer */ + +/* command codes (1st byte) */ +typedef enum { + CMD_SET_ONE_MAJOR = 1, /* mask in one major. 2nd byte in the command is the major code */ + CMD_UNSET_ONE_MAJOR = 2, /* mask out one major. 2nd byte in the command is the major code */ + CMD_SET_ALL_MAJORS = 3, /* set the major print mask. the full mask is in the data DWORD */ + CMD_SET_VERBOSITY = 4 /* set verbosity level */ +} DBG_commands; + +/* command signature */ +#define CMD_SIGNATURE 0xAABBCC00 + +/* shared macros in traces infrastructure */ +/* increment the pointer cyclicly */ +#define DBG_NEXT_ITEM(x, max_items) (((x + 1) >= max_items) ? 0 : x + 1) +#define DBG_PREV_ITEM(x, max_items) ((x) ? x - 1 : max_items - 1) + +#define FIELD_MASK(width) (((1 << (width)) - 1)) +#define FIELD_PACK(value, mask, offset) (((value) & (mask)) << (offset)) +#define FIELD_UNPACK(value, mask, offset) (((value) >> (offset)) & (mask)) + +#define FIELD_VALUE_OFFSET (0) +#define FIELD_VALUE_WIDTH (16) +#define FIELD_VALUE_MASK FIELD_MASK(FIELD_VALUE_WIDTH) +#define FIELD_VALUE_PACK(f) FIELD_PACK(f, FIELD_VALUE_MASK, FIELD_VALUE_OFFSET) +#define FIELD_VALUE_UNPACK(f) FIELD_UNPACK(f, FIELD_VALUE_MASK, FIELD_VALUE_OFFSET) + +#define FIELD_MINOR_OFFSET (FIELD_VALUE_OFFSET + FIELD_VALUE_WIDTH) +#define FIELD_MINOR_WIDTH (8) +#define FIELD_MINOR_MASK FIELD_MASK(FIELD_MINOR_WIDTH) +#define FIELD_MINOR_PACK(f) FIELD_PACK(f, FIELD_MINOR_MASK, FIELD_MINOR_OFFSET) +#define FIELD_MINOR_UNPACK(f) FIELD_UNPACK(f, FIELD_MINOR_MASK, FIELD_MINOR_OFFSET) + +#define FIELD_MAJOR_OFFSET (FIELD_MINOR_OFFSET + FIELD_MINOR_WIDTH) +#define FIELD_MAJOR_WIDTH (5) +#define FIELD_MAJOR_MASK FIELD_MASK(FIELD_MAJOR_WIDTH) +#define FIELD_MAJOR_PACK(f) FIELD_PACK(f, FIELD_MAJOR_MASK, FIELD_MAJOR_OFFSET) +#define FIELD_MAJOR_UNPACK(f) FIELD_UNPACK(f, FIELD_MAJOR_MASK, FIELD_MAJOR_OFFSET) + +/* for quick traces - only insertion, compatible with the regular point */ +#define FIELD_FULL_MAJOR_WIDTH (8) +#define FIELD_FULL_MAJOR_MASK FIELD_MASK(FIELD_FULL_MAJOR_WIDTH) +#define FIELD_FULL_MAJOR_PACK(f) FIELD_PACK(f, FIELD_FULL_MAJOR_MASK, FIELD_MAJOR_OFFSET) + +/* The following 2 fields are used only when FIELD_TID value is 111b. + * it means we don't want to use thread id, but format. In this case, + * the last 2 MSB bits of the major field will indicates the format + */ +#define FIELD_MAJOR_W_FMT_OFFSET FIELD_MAJOR_OFFSET +#define FIELD_MAJOR_W_FMT_WIDTH (3) +#define FIELD_MAJOR_W_FMT_MASK FIELD_MASK(FIELD_MAJOR_W_FMT_WIDTH) +#define FIELD_MAJOR_W_FMT_PACK(f) FIELD_PACK(f, FIELD_MAJOR_W_FMT_MASK, FIELD_MAJOR_W_FMT_OFFSET) +#define FIELD_MAJOR_W_FMT_UNPACK(f) FIELD_UNPACK(f, FIELD_MAJOR_W_FMT_MASK, FIELD_MAJOR_W_FMT_OFFSET) + +#define FIELD_FORMAT_OFFSET (FIELD_MAJOR_OFFSET + FIELD_MAJOR_W_FMT_WIDTH) +#define FIELD_FORMAT_WIDTH (2) +#define FIELD_FORMAT_MASK FIELD_MASK(FIELD_MAJOR_W_FMT_WIDTH) +#define FIELD_FORMAT_PACK(f) FIELD_PACK(f, FIELD_FORMAT_MASK, FIELD_FORMAT_OFFSET) +#define FIELD_FORMAT_UNPACK(f) FIELD_UNPACK(f, FIELD_FORMAT_MASK, FIELD_FORMAT_OFFSET) + +#define FIELD_TID_SEL_FORMAT_PAT (7) + +#define FIELD_TID_OFFSET (FIELD_MAJOR_OFFSET + FIELD_MAJOR_WIDTH) +#define FIELD_TID_WIDTH (3) +#define FIELD_TID_MASK FIELD_MASK(FIELD_TID_WIDTH) +#define FIELD_TID_PACK(f) FIELD_PACK(f, FIELD_TID_MASK, FIELD_TID_OFFSET) +#define FIELD_TID_UNPACK(f) FIELD_UNPACK(f, FIELD_TID_MASK, FIELD_TID_OFFSET) + +#define FIELD_VALUE_24_OFFSET (0) +#define FIELD_VALUE_24_WIDTH (24) +#define FIELD_VALUE_24_MASK FIELD_MASK(FIELD_VALUE_24_WIDTH) +#define FIELD_VALUE_24_PACK(f) FIELD_PACK(f, FIELD_VALUE_24_MASK, FIELD_VALUE_24_OFFSET) +#define FIELD_VALUE_24_UNPACK(f) FIELD_UNPACK(f, FIELD_VALUE_24_MASK, FIELD_VALUE_24_OFFSET) + +#define PACK_TRACEPOINT(tid, major, minor, value) \ + (FIELD_TID_PACK(tid) | FIELD_MAJOR_PACK(major) | FIELD_MINOR_PACK(minor) | FIELD_VALUE_PACK(value)) + +#define PACK_QUICK_TRACEPOINT(major, minor) \ + (FIELD_FULL_MAJOR_PACK(major) | FIELD_MINOR_PACK(minor)) + +#define PACK_FORMATTED_TRACEPOINT(format, major, minor, value) \ + (FIELD_TID_PACK(FIELD_TID_SEL_FORMAT_PAT) | FIELD_FORMAT_PACK(format) | FIELD_MAJOR_PACK(major) | FIELD_MINOR_PACK(minor) | FIELD_VALUE_PACK(value)) + +#define PACK_TRACE_VALUE24(major, value) \ + (FIELD_TID_PACK(FIELD_TID_SEL_FORMAT_PAT) | FIELD_MAJOR_PACK(major) | FIELD_VALUE_24_PACK(value)) + +#endif /* __CSS_TRACE_H_ */ diff --git a/drivers/staging/media/atomisp/pci/defs.h b/drivers/staging/media/atomisp/pci/defs.h new file mode 100644 index 000000000..785e7a670 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/defs.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_DEFS_H_ +#define _HRT_DEFS_H_ + +#ifndef HRTCAT +#define _HRTCAT(m, n) m##n +#define HRTCAT(m, n) _HRTCAT(m, n) +#endif + +#ifndef HRTSTR +#define _HRTSTR(x) #x +#define HRTSTR(x) _HRTSTR(x) +#endif + +#ifndef HRTMIN +#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#endif /* _HRT_DEFS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/dma_v2_defs.h b/drivers/staging/media/atomisp/pci/dma_v2_defs.h new file mode 100644 index 000000000..27299e3a1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/dma_v2_defs.h @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _dma_v2_defs_h +#define _dma_v2_defs_h + +#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels +#define _DMA_V2_CONNECTIONS_ID Connections +#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths +#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth +#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat +#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass +#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst +#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept +#define _DMA_V2_DEV_SRMD_ID DevSRMD +#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters +#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth +#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth +#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat +#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass +#define _DMA_V2_NO_PACK_ID has_no_pack + +#define _DMA_V2_REG_ALIGN 4 +#define _DMA_V2_REG_ADDR_BITS 2 + +/* Command word */ +#define _DMA_V2_CMD_IDX 0 +#define _DMA_V2_CMD_BITS 6 +#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS) +#define _DMA_V2_CHANNEL_BITS 5 + +/* The command to set a parameter contains the PARAM field next */ +#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_PARAM_BITS 4 + +/* Commands to read, write or init specific blocks contain these + three values */ +#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_SPEC_DEV_A_XB_BITS 8 +#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS) +#define _DMA_V2_SPEC_DEV_B_XB_BITS 8 +#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS) +#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS) + +/* */ +#define _DMA_V2_CMD_CTRL_IDX 4 +#define _DMA_V2_CMD_CTRL_BITS 4 + +/* Packing setup word */ +#define _DMA_V2_CONNECTION_IDX 0 +#define _DMA_V2_CONNECTION_BITS 4 +#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS) +#define _DMA_V2_EXTENSION_BITS 1 + +/* Elements packing word */ +#define _DMA_V2_ELEMENTS_IDX 0 +#define _DMA_V2_ELEMENTS_BITS 8 +#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS) +#define _DMA_V2_LEFT_CROPPING_BITS 8 + +#define _DMA_V2_WIDTH_IDX 0 +#define _DMA_V2_WIDTH_BITS 16 + +#define _DMA_V2_HEIGHT_IDX 0 +#define _DMA_V2_HEIGHT_BITS 16 + +#define _DMA_V2_STRIDE_IDX 0 +#define _DMA_V2_STRIDE_BITS 32 + +/* Command IDs */ +#define _DMA_V2_MOVE_B2A_COMMAND 0 +#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1 +#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2 +#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3 +#define _DMA_V2_MOVE_A2B_COMMAND 4 +#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5 +#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6 +#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7 +#define _DMA_V2_INIT_A_COMMAND 8 +#define _DMA_V2_INIT_A_BLOCK_COMMAND 9 +#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10 +#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11 +#define _DMA_V2_INIT_B_COMMAND 12 +#define _DMA_V2_INIT_B_BLOCK_COMMAND 13 +#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14 +#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15 +#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32 +#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33 +#define _DMA_V2_SET_CRUN_COMMAND 62 + +/* Channel Parameter IDs */ +#define _DMA_V2_PACKING_SETUP_PARAM 0 +#define _DMA_V2_STRIDE_A_PARAM 1 +#define _DMA_V2_ELEM_CROPPING_A_PARAM 2 +#define _DMA_V2_WIDTH_A_PARAM 3 +#define _DMA_V2_STRIDE_B_PARAM 4 +#define _DMA_V2_ELEM_CROPPING_B_PARAM 5 +#define _DMA_V2_WIDTH_B_PARAM 6 +#define _DMA_V2_HEIGHT_PARAM 7 +#define _DMA_V2_QUEUED_CMDS 8 + +/* Parameter Constants */ +#define _DMA_V2_ZERO_EXTEND 0 +#define _DMA_V2_SIGN_EXTEND 1 + +/* SLAVE address map */ +#define _DMA_V2_SEL_FSM_CMD 0 +#define _DMA_V2_SEL_CH_REG 1 +#define _DMA_V2_SEL_CONN_GROUP 2 +#define _DMA_V2_SEL_DEV_INTERF 3 + +#define _DMA_V2_ADDR_SEL_COMP_IDX 12 +#define _DMA_V2_ADDR_SEL_COMP_BITS 4 +#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2 +#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6 +#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX) +#define _DMA_V2_ADDR_SEL_PARAM_BITS 4 + +#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4 + +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS) +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4 + +#define _DMA_V2_FSM_GROUP_CMD_IDX 0 +#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1 +#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2 +#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7 + +#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15 + +#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3 + +#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4 + +#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4 + +#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0 +#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1 +#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2 +#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3 +#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4 +#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5 + +#endif /* _dma_v2_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/gdc_v2_defs.h b/drivers/staging/media/atomisp/pci/gdc_v2_defs.h new file mode 100644 index 000000000..804df8179 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/gdc_v2_defs.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_GDC_v2_defs_h_ +#define HRT_GDC_v2_defs_h_ + +#define HRT_GDC_IS_V2 + +#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */ +#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */ + +#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */ +#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS) + +#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */ +#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */ +/* The supported range is [-256, .., +256] */ +/* in 14-bit signed notation, */ +/* We need all ten bits (MSB must be zero). */ +/* -s is inserted to solve this issue, and */ +/* therefore "1" is equal to +256. */ +#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1) + +#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */ +/* 2 bytes per coefficient */ + +#define _HRT_GDC_REG_ALIGN 4 + +// 31 30 29 25 24 0 +// |-----|---|--------|------------------------| +// | CMD | C | Reg_ID | Value | + +// There are just two commands possible for the GDC block: +// 1 - Configure reg +// 0 - Data token + +// C - Reserved bit +// Used in protocol to indicate whether it is C-run or other type of runs +// In case of C-run, this bit has a value of 1, for all the other runs, it is 0. + +// Reg_ID - Address of the register to be configured + +// Value - Value to store to the addressed register, maximum of 24 bits + +// Configure reg command is not followed by any other token. +// The address of the register and the data to be filled in is contained in the same token + +// When the first data token is received, it must be: +// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or, +// 2. P0'X (device configured in one of the tetragon modes) +// After the first data token is received, pre-defined number of tokens with the following meaning follow: +// 1. two tokens: SRC address ; DST address +// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address + +#define HRT_GDC_CONFIG_CMD 1 +#define HRT_GDC_DATA_CMD 0 + +#define HRT_GDC_CMD_POS 31 +#define HRT_GDC_CMD_BITS 1 +#define HRT_GDC_CRUN_POS 30 +#define HRT_GDC_REG_ID_POS 25 +#define HRT_GDC_REG_ID_BITS 5 +#define HRT_GDC_DATA_POS 0 +#define HRT_GDC_DATA_BITS 25 + +#define HRT_GDC_FRYIPXFRX_BITS 26 +#define HRT_GDC_P0X_BITS 23 + +#define HRT_GDC_MAX_OXDIM (8192 - 64) +#define HRT_GDC_MAX_OYDIM 4095 +#define HRT_GDC_MAX_IXDIM (8192 - 64) +#define HRT_GDC_MAX_IYDIM 4095 +#define HRT_GDC_MAX_DS_FAC 16 +#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1) +#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX + +/* GDC lookup tables entries are 10 bits values, but they're + stored 2 by 2 as 32 bit values, yielding 16 bits per entry. + A GDC lookup table contains 64 * 4 elements */ + +#define HRT_GDC_PERF_1_1_pix 0 +#define HRT_GDC_PERF_2_1_pix 1 +#define HRT_GDC_PERF_1_2_pix 2 +#define HRT_GDC_PERF_2_2_pix 3 + +#define HRT_GDC_NND_MODE 0 +#define HRT_GDC_BLI_MODE 1 +#define HRT_GDC_BCI_MODE 2 +#define HRT_GDC_LUT_MODE 3 + +#define HRT_GDC_SCAN_STB 0 +#define HRT_GDC_SCAN_STR 1 + +#define HRT_GDC_MODE_SCALING 0 +#define HRT_GDC_MODE_TETRAGON 1 + +#define HRT_GDC_LUT_COEFF_OFFSET 16 +#define HRT_GDC_FRY_BIT_OFFSET 16 +// FRYIPXFRX is the only register where we store two values in one field, +// to save one token in the scaling protocol. +// Like this, we have three tokens in the scaling protocol, +// Otherwise, we would have had four. +// The register bit-map is: +// 31 26 25 16 15 10 9 0 +// |------|----------|------|----------| +// | XXXX | FRY | IPX | FRX | + +#define HRT_GDC_CE_FSM0_POS 0 +#define HRT_GDC_CE_FSM0_LEN 2 +#define HRT_GDC_CE_OPY_POS 2 +#define HRT_GDC_CE_OPY_LEN 14 +#define HRT_GDC_CE_OPX_POS 16 +#define HRT_GDC_CE_OPX_LEN 16 +// CHK_ENGINE register bit-map: +// 31 16 15 2 1 0 +// |----------------|-----------|----| +// | OPX | OPY |FSM0| +// However, for the time being at least, +// this implementation is meaningless in hss model, +// So, we just return 0 + +#define HRT_GDC_CHK_ENGINE_IDX 0 +#define HRT_GDC_WOIX_IDX 1 +#define HRT_GDC_WOIY_IDX 2 +#define HRT_GDC_BPP_IDX 3 +#define HRT_GDC_FRYIPXFRX_IDX 4 +#define HRT_GDC_OXDIM_IDX 5 +#define HRT_GDC_OYDIM_IDX 6 +#define HRT_GDC_SRC_ADDR_IDX 7 +#define HRT_GDC_SRC_END_ADDR_IDX 8 +#define HRT_GDC_SRC_WRAP_ADDR_IDX 9 +#define HRT_GDC_SRC_STRIDE_IDX 10 +#define HRT_GDC_DST_ADDR_IDX 11 +#define HRT_GDC_DST_STRIDE_IDX 12 +#define HRT_GDC_DX_IDX 13 +#define HRT_GDC_DY_IDX 14 +#define HRT_GDC_P0X_IDX 15 +#define HRT_GDC_P0Y_IDX 16 +#define HRT_GDC_P1X_IDX 17 +#define HRT_GDC_P1Y_IDX 18 +#define HRT_GDC_P2X_IDX 19 +#define HRT_GDC_P2Y_IDX 20 +#define HRT_GDC_P3X_IDX 21 +#define HRT_GDC_P3Y_IDX 22 +#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc +#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT +#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right) +#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon + +#define HRT_GDC_LUT_IDX 32 + +#endif /* HRT_GDC_v2_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/gp_timer_defs.h b/drivers/staging/media/atomisp/pci/gp_timer_defs.h new file mode 100644 index 000000000..9bc04e5b4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/gp_timer_defs.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_timer_defs_h +#define _gp_timer_defs_h + +#define _HRT_GP_TIMER_REG_ALIGN 4 + +#define HIVE_GP_TIMER_RESET_REG_IDX 0 +#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1 +#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer) +#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer) +#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq) +#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq) +#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq) + +#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0 +#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1 +#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2 +#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3 +#define HIVE_GP_TIMER_COUNT_TYPES 4 + +#endif /* _gp_timer_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/gpio_block_defs.h b/drivers/staging/media/atomisp/pci/gpio_block_defs.h new file mode 100644 index 000000000..e1bd638d3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/gpio_block_defs.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gpio_block_defs_h_ +#define _gpio_block_defs_h_ + +#define _HRT_GPIO_BLOCK_REG_ALIGN 4 + +/* R/W registers */ +#define _gpio_block_reg_do_e 0 +#define _gpio_block_reg_do_select 1 +#define _gpio_block_reg_do_0 2 +#define _gpio_block_reg_do_1 3 +#define _gpio_block_reg_do_pwm_cnt_0 4 +#define _gpio_block_reg_do_pwm_cnt_1 5 +#define _gpio_block_reg_do_pwm_cnt_2 6 +#define _gpio_block_reg_do_pwm_cnt_3 7 +#define _gpio_block_reg_do_pwm_main_cnt 8 +#define _gpio_block_reg_do_pwm_enable 9 +#define _gpio_block_reg_di_debounce_sel 10 +#define _gpio_block_reg_di_debounce_cnt_0 11 +#define _gpio_block_reg_di_debounce_cnt_1 12 +#define _gpio_block_reg_di_debounce_cnt_2 13 +#define _gpio_block_reg_di_debounce_cnt_3 14 +#define _gpio_block_reg_di_active_level 15 + +/* read-only registers */ +#define _gpio_block_reg_di 16 + +#endif /* _gpio_block_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/debug_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/debug_global.h new file mode 100644 index 000000000..b6538beca --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/debug_global.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DEBUG_GLOBAL_H_INCLUDED__ +#define __DEBUG_GLOBAL_H_INCLUDED__ + +#include + +#define DEBUG_BUF_SIZE 1024 +#define DEBUG_BUF_MASK (DEBUG_BUF_SIZE - 1) + +#define DEBUG_DATA_ENABLE_ADDR 0x00 +#define DEBUG_DATA_BUF_MODE_ADDR 0x04 +#define DEBUG_DATA_HEAD_ADDR 0x08 +#define DEBUG_DATA_TAIL_ADDR 0x0C +#define DEBUG_DATA_BUF_ADDR 0x10 + +#define DEBUG_DATA_ENABLE_DDR_ADDR 0x00 +#define DEBUG_DATA_BUF_MODE_DDR_ADDR HIVE_ISP_DDR_WORD_BYTES +#define DEBUG_DATA_HEAD_DDR_ADDR (2 * HIVE_ISP_DDR_WORD_BYTES) +#define DEBUG_DATA_TAIL_DDR_ADDR (3 * HIVE_ISP_DDR_WORD_BYTES) +#define DEBUG_DATA_BUF_DDR_ADDR (4 * HIVE_ISP_DDR_WORD_BYTES) + +#define DEBUG_BUFFER_ISP_DMEM_ADDR 0x0 + +/* + * Enable HAS_WATCHDOG_SP_THREAD_DEBUG for additional SP thread and + * pipe information on watchdog output + * #undef HAS_WATCHDOG_SP_THREAD_DEBUG + * #define HAS_WATCHDOG_SP_THREAD_DEBUG + */ + +/* + * The linear buffer mode will accept data until the first + * overflow and then stop accepting new data + * The circular buffer mode will accept if there is place + * and discard the data if the buffer is full + */ +typedef enum { + DEBUG_BUFFER_MODE_LINEAR = 0, + DEBUG_BUFFER_MODE_CIRCULAR, + N_DEBUG_BUFFER_MODE +} debug_buf_mode_t; + +struct debug_data_s { + u32 enable; + u32 bufmode; + u32 head; + u32 tail; + u32 buf[DEBUG_BUF_SIZE]; +}; + +/* thread.sp.c doesn't have a notion of HIVE_ISP_DDR_WORD_BYTES + still one point of control is needed for debug purposes */ + +#ifdef HIVE_ISP_DDR_WORD_BYTES +struct debug_data_ddr_s { + u32 enable; + s8 padding1[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)]; + u32 bufmode; + s8 padding2[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)]; + u32 head; + s8 padding3[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)]; + u32 tail; + s8 padding4[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)]; + u32 buf[DEBUG_BUF_SIZE]; +}; +#endif + +#endif /* __DEBUG_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/dma_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/dma_global.h new file mode 100644 index 000000000..135034c72 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/dma_global.h @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_GLOBAL_H_INCLUDED__ +#define __DMA_GLOBAL_H_INCLUDED__ + +#include + +#define IS_DMA_VERSION_2 + +#define HIVE_ISP_NUM_DMA_CONNS 3 +#define HIVE_ISP_NUM_DMA_CHANNELS 32 + +#define N_DMA_CHANNEL_ID HIVE_ISP_NUM_DMA_CHANNELS + +#include "dma_v2_defs.h" + +/* + * Command token bit mappings + * + * transfer / config + * param id[4] channel id[5] cmd id[6] + * | b14 .. b11 | b10 ... b6 | b5 ... b0 | + * + * + * fast transfer: + * height[5] width[8] width[8] channel id[5] cmd id[6] + * | b31 .. b26 | b25 .. b18 | b17 .. b11 | b10 ... b6 | b5 ... b0 | + * + */ + +#define _DMA_PACKING_SETUP_PARAM _DMA_V2_PACKING_SETUP_PARAM +#define _DMA_HEIGHT_PARAM _DMA_V2_HEIGHT_PARAM +#define _DMA_STRIDE_A_PARAM _DMA_V2_STRIDE_A_PARAM +#define _DMA_ELEM_CROPPING_A_PARAM _DMA_V2_ELEM_CROPPING_A_PARAM +#define _DMA_WIDTH_A_PARAM _DMA_V2_WIDTH_A_PARAM +#define _DMA_STRIDE_B_PARAM _DMA_V2_STRIDE_B_PARAM +#define _DMA_ELEM_CROPPING_B_PARAM _DMA_V2_ELEM_CROPPING_B_PARAM +#define _DMA_WIDTH_B_PARAM _DMA_V2_WIDTH_B_PARAM + +#define _DMA_ZERO_EXTEND _DMA_V2_ZERO_EXTEND +#define _DMA_SIGN_EXTEND _DMA_V2_SIGN_EXTEND + +typedef unsigned int dma_channel; + +typedef enum { + dma_isp_to_bus_connection = HIVE_DMA_ISP_BUS_CONN, + dma_isp_to_ddr_connection = HIVE_DMA_ISP_DDR_CONN, + dma_bus_to_ddr_connection = HIVE_DMA_BUS_DDR_CONN, +} dma_connection; + +typedef enum { + dma_zero_extension = _DMA_ZERO_EXTEND, + dma_sign_extension = _DMA_SIGN_EXTEND +} dma_extension; + +#define DMA_PROP_SHIFT(val, param) ((val) << _DMA_V2_ ## param ## _IDX) +#define DMA_PROP_MASK(param) ((1U << _DMA_V2_ ## param ## _BITS) - 1) +#define DMA_PACK(val, param) DMA_PROP_SHIFT((val) & DMA_PROP_MASK(param), param) + +#define DMA_PACK_COMMAND(cmd) DMA_PACK(cmd, CMD) +#define DMA_PACK_CHANNEL(ch) DMA_PACK(ch, CHANNEL) +#define DMA_PACK_PARAM(par) DMA_PACK(par, PARAM) +#define DMA_PACK_EXTENSION(ext) DMA_PACK(ext, EXTENSION) +#define DMA_PACK_LEFT_CROPPING(lc) DMA_PACK(lc, LEFT_CROPPING) +#define DMA_PACK_WIDTH_A(w) DMA_PACK(w, SPEC_DEV_A_XB) +#define DMA_PACK_WIDTH_B(w) DMA_PACK(w, SPEC_DEV_B_XB) +#define DMA_PACK_HEIGHT(h) DMA_PACK(h, SPEC_YB) + +#define DMA_PACK_CMD_CHANNEL(cmd, ch) (DMA_PACK_COMMAND(cmd) | DMA_PACK_CHANNEL(ch)) +#define DMA_PACK_SETUP(conn, ext) ((conn) | DMA_PACK_EXTENSION(ext)) +#define DMA_PACK_CROP_ELEMS(elems, crop) ((elems) | DMA_PACK_LEFT_CROPPING(crop)) + +#define hive_dma_snd(dma_id, token) OP_std_snd(dma_id, (unsigned int)(token)) + +#define DMA_PACK_BLOCK_CMD(cmd, ch, width_a, width_b, height) \ + (DMA_PACK_COMMAND(cmd) | \ + DMA_PACK_CHANNEL(ch) | \ + DMA_PACK_WIDTH_A(width_a) | \ + DMA_PACK_WIDTH_B(width_b) | \ + DMA_PACK_HEIGHT(height)) + +#define hive_dma_move_data(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read ? _DMA_V2_MOVE_B2A_COMMAND : _DMA_V2_MOVE_A2B_COMMAND, channel)); \ + hive_dma_snd(dma_id, read ? (unsigned int)(addr_b) : (unsigned int)(addr_a)); \ + hive_dma_snd(dma_id, read ? (unsigned int)(addr_a) : (unsigned int)(addr_b)); \ + hive_dma_snd(dma_id, to_is_var); \ + hive_dma_snd(dma_id, from_is_var); \ +} + +#define hive_dma_move_data_no_ack(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read ? _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND : _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND, channel)); \ + hive_dma_snd(dma_id, read ? (unsigned int)(addr_b) : (unsigned int)(addr_a)); \ + hive_dma_snd(dma_id, read ? (unsigned int)(addr_a) : (unsigned int)(addr_b)); \ + hive_dma_snd(dma_id, to_is_var); \ + hive_dma_snd(dma_id, from_is_var); \ +} + +#define hive_dma_move_b2a_data(dma_id, channel, to_addr, from_addr, to_is_var, from_is_var) \ +{ \ + hive_dma_move_data(dma_id, true, channel, to_addr, from_addr, to_is_var, from_is_var) \ +} + +#define hive_dma_move_a2b_data(dma_id, channel, from_addr, to_addr, from_is_var, to_is_var) \ +{ \ + hive_dma_move_data(dma_id, false, channel, from_addr, to_addr, from_is_var, to_is_var) \ +} + +#define hive_dma_set_data(dma_id, channel, address, value, is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_INIT_A_COMMAND, channel)); \ + hive_dma_snd(dma_id, value); \ + hive_dma_snd(dma_id, address); \ + hive_dma_snd(dma_id, is_var); \ +} + +#define hive_dma_clear_data(dma_id, channel, address, is_var) hive_dma_set_data(dma_id, channel, address, 0, is_var) + +#define hive_dma_configure(dma_id, channel, connection, extension, height, \ + stride_A, elems_A, cropping_A, width_A, \ + stride_B, elems_B, cropping_B, width_B) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_CONFIG_CHANNEL_COMMAND, channel)); \ + hive_dma_snd(dma_id, DMA_PACK_SETUP(connection, extension)); \ + hive_dma_snd(dma_id, stride_A); \ + hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_A, cropping_A)); \ + hive_dma_snd(dma_id, width_A); \ + hive_dma_snd(dma_id, stride_B); \ + hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_B, cropping_B)); \ + hive_dma_snd(dma_id, width_B); \ + hive_dma_snd(dma_id, height); \ +} + +#define hive_dma_execute(dma_id, channel, cmd, to_addr, from_addr_value, to_is_var, from_is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(cmd, channel)); \ + hive_dma_snd(dma_id, to_addr); \ + hive_dma_snd(dma_id, from_addr_value); \ + hive_dma_snd(dma_id, to_is_var); \ + if ((cmd & DMA_CLEAR_CMDBIT) == 0) { \ + hive_dma_snd(dma_id, from_is_var); \ + } \ +} + +#define hive_dma_configure_fast(dma_id, channel, connection, extension, elems_A, elems_B) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_CONFIG_CHANNEL_COMMAND, channel)); \ + hive_dma_snd(dma_id, DMA_PACK_SETUP(connection, extension)); \ + hive_dma_snd(dma_id, 0); \ + hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_A, 0)); \ + hive_dma_snd(dma_id, 0); \ + hive_dma_snd(dma_id, 0); \ + hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_B, 0)); \ + hive_dma_snd(dma_id, 0); \ + hive_dma_snd(dma_id, 1); \ +} + +#define hive_dma_set_parameter(dma_id, channel, param, value) \ +{ \ + hive_dma_snd(dma_id, _DMA_V2_SET_CHANNEL_PARAM_COMMAND | DMA_PACK_CHANNEL(channel) | DMA_PACK_PARAM(param)); \ + hive_dma_snd(dma_id, value); \ +} + +#define DMA_SPECIFIC_CMDBIT 0x01 +#define DMA_CHECK_CMDBIT 0x02 +#define DMA_RW_CMDBIT 0x04 +#define DMA_CLEAR_CMDBIT 0x08 +#define DMA_ACK_CMDBIT 0x10 +#define DMA_CFG_CMDBIT 0x20 +#define DMA_PARAM_CMDBIT 0x01 + +/* Write complete check not necessary if there's no ack */ +#define DMA_NOACK_CMD (DMA_ACK_CMDBIT | DMA_CHECK_CMDBIT) +#define DMA_CFG_CMD (DMA_CFG_CMDBIT) +#define DMA_CFGPARAM_CMD (DMA_CFG_CMDBIT | DMA_PARAM_CMDBIT) + +#define DMA_CMD_NEEDS_ACK(cmd) ((cmd & DMA_NOACK_CMD) == 0) +#define DMA_CMD_IS_TRANSFER(cmd) ((cmd & DMA_CFG_CMDBIT) == 0) +#define DMA_CMD_IS_WR(cmd) ((cmd & DMA_RW_CMDBIT) != 0) +#define DMA_CMD_IS_RD(cmd) ((cmd & DMA_RW_CMDBIT) == 0) +#define DMA_CMD_IS_CLR(cmd) ((cmd & DMA_CLEAR_CMDBIT) != 0) +#define DMA_CMD_IS_CFG(cmd) ((cmd & DMA_CFG_CMDBIT) != 0) +#define DMA_CMD_IS_PARAMCFG(cmd) ((cmd & DMA_CFGPARAM_CMD) == DMA_CFGPARAM_CMD) + +/* As a matter of convention */ +#define DMA_TRANSFER_READ DMA_TRANSFER_B2A +#define DMA_TRANSFER_WRITE DMA_TRANSFER_A2B +/* store/load from the PoV of the system(memory) */ +#define DMA_TRANSFER_STORE DMA_TRANSFER_B2A +#define DMA_TRANSFER_LOAD DMA_TRANSFER_A2B +#define DMA_TRANSFER_CLEAR DMA_TRANSFER_CLEAR_A + +typedef enum { + DMA_TRANSFER_CLEAR_A = DMA_CLEAR_CMDBIT, /* 8 */ + DMA_TRANSFER_CLEAR_B = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT, /* 12 */ + DMA_TRANSFER_A2B = DMA_RW_CMDBIT, /* 4 */ + DMA_TRANSFER_B2A = 0, /* 0 */ + DMA_TRANSFER_CLEAR_A_NOACK = DMA_CLEAR_CMDBIT | DMA_NOACK_CMD, /* 26 */ + DMA_TRANSFER_CLEAR_B_NOACK = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_NOACK_CMD, /* 30 */ + DMA_TRANSFER_A2B_NOACK = DMA_RW_CMDBIT | DMA_NOACK_CMD, /* 22 */ + DMA_TRANSFER_B2A_NOACK = DMA_NOACK_CMD, /* 18 */ + DMA_FASTTRANSFER_CLEAR_A = DMA_CLEAR_CMDBIT | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_CLEAR_B = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_A2B = DMA_RW_CMDBIT | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_B2A = DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_CLEAR_A_NOACK = DMA_CLEAR_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_CLEAR_B_NOACK = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_A2B_NOACK = DMA_RW_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_B2A_NOACK = DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT, +} dma_transfer_type_t; + +typedef enum { + DMA_CONFIG_SETUP = _DMA_V2_PACKING_SETUP_PARAM, + DMA_CONFIG_HEIGHT = _DMA_V2_HEIGHT_PARAM, + DMA_CONFIG_STRIDE_A_ = _DMA_V2_STRIDE_A_PARAM, + DMA_CONFIG_CROP_ELEM_A = _DMA_V2_ELEM_CROPPING_A_PARAM, + DMA_CONFIG_WIDTH_A = _DMA_V2_WIDTH_A_PARAM, + DMA_CONFIG_STRIDE_B_ = _DMA_V2_STRIDE_B_PARAM, + DMA_CONFIG_CROP_ELEM_B = _DMA_V2_ELEM_CROPPING_B_PARAM, + DMA_CONFIG_WIDTH_B = _DMA_V2_WIDTH_B_PARAM, +} dma_config_type_t; + +struct dma_port_config { + u8 crop, elems; + u16 width; + u32 stride; +}; + +/* Descriptor for dma configuration */ +struct dma_channel_config { + u8 connection; + u8 extension; + u8 height; + struct dma_port_config a, b; +}; + +#endif /* __DMA_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/event_fifo_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/event_fifo_global.h new file mode 100644 index 000000000..a50635b71 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/event_fifo_global.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __EVENT_FIFO_GLOBAL_H +#define __EVENT_FIFO_GLOBAL_H + +/*#error "event_global.h: No global event information permitted"*/ + +#endif /* __EVENT_FIFO_GLOBAL_H */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/fifo_monitor_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/fifo_monitor_global.h new file mode 100644 index 000000000..d941c82d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/fifo_monitor_global.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_GLOBAL_H_INCLUDED__ +#define __FIFO_MONITOR_GLOBAL_H_INCLUDED__ + +#define IS_FIFO_MONITOR_VERSION_2 + +/* +#define HIVE_ISP_CSS_STREAM_SWITCH_NONE 0 +#define HIVE_ISP_CSS_STREAM_SWITCH_SP 1 +#define HIVE_ISP_CSS_STREAM_SWITCH_ISP 2 + * + * Actually, "HIVE_ISP_CSS_STREAM_SWITCH_SP = 1", "HIVE_ISP_CSS_STREAM_SWITCH_ISP = 0" + * "hive_isp_css_stream_switch_hrt.h" + */ +#define HIVE_ISP_CSS_STREAM_SWITCH_ISP 0 +#define HIVE_ISP_CSS_STREAM_SWITCH_SP 1 +#define HIVE_ISP_CSS_STREAM_SWITCH_NONE 2 + +#endif /* __FIFO_MONITOR_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/gdc_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/gdc_global.h new file mode 100644 index 000000000..599d993b8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/gdc_global.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_GLOBAL_H_INCLUDED__ +#define __GDC_GLOBAL_H_INCLUDED__ + +#define IS_GDC_VERSION_2 + +#include +#include "gdc_v2_defs.h" + +/* + * Storage addresses for packed data transfer + */ +#define GDC_PARAM_ICX_LEFT_ROUNDED_IDX 0 +#define GDC_PARAM_OXDIM_FLOORED_IDX 1 +#define GDC_PARAM_OXDIM_LAST_IDX 2 +#define GDC_PARAM_WOIX_LAST_IDX 3 +#define GDC_PARAM_IY_TOPLEFT_IDX 4 +#define GDC_PARAM_CHUNK_CNT_IDX 5 +/*#define GDC_PARAM_ELEMENTS_PER_XMEM_ADDR_IDX 6 */ /* Derived from bpp */ +#define GDC_PARAM_BPP_IDX 6 +#define GDC_PARAM_BLOCK_HEIGHT_IDX 7 +/*#define GDC_PARAM_DMA_CHANNEL_STRIDE_A_IDX 8*/ /* The DMA stride == the GDC buffer stride */ +#define GDC_PARAM_WOIX_IDX 8 +#define GDC_PARAM_DMA_CHANNEL_STRIDE_B_IDX 9 +#define GDC_PARAM_DMA_CHANNEL_WIDTH_A_IDX 10 +#define GDC_PARAM_DMA_CHANNEL_WIDTH_B_IDX 11 +#define GDC_PARAM_VECTORS_PER_LINE_IN_IDX 12 +#define GDC_PARAM_VECTORS_PER_LINE_OUT_IDX 13 +#define GDC_PARAM_VMEM_IN_DIMY_IDX 14 +#define GDC_PARAM_COMMAND_IDX 15 +#define N_GDC_PARAM 16 + +/* Because of the packed parameter transfer max(params) == max(fragments) */ +#define N_GDC_FRAGMENTS N_GDC_PARAM + +/* The GDC is capable of higher internal precision than the parameter data structures */ +#define HRT_GDC_COORD_SCALE_BITS 6 +#define HRT_GDC_COORD_SCALE BIT(HRT_GDC_COORD_SCALE_BITS) + +typedef enum { + GDC_CH0_ID = 0, + N_GDC_CHANNEL_ID +} gdc_channel_ID_t; + +typedef enum { + gdc_8_bpp = 8, + gdc_10_bpp = 10, + gdc_12_bpp = 12, + gdc_14_bpp = 14 +} gdc_bits_per_pixel_t; + +typedef struct gdc_scale_param_mem_s { + u16 params[N_GDC_PARAM]; + u16 ipx_start_array[N_GDC_PARAM]; + u16 ibuf_offset[N_GDC_PARAM]; + u16 obuf_offset[N_GDC_PARAM]; +} gdc_scale_param_mem_t; + +typedef struct gdc_warp_param_mem_s { + u32 origin_x; + u32 origin_y; + u32 in_addr_offset; + u32 in_block_width; + u32 in_block_height; + u32 p0_x; + u32 p0_y; + u32 p1_x; + u32 p1_y; + u32 p2_x; + u32 p2_y; + u32 p3_x; + u32 p3_y; + u32 padding[3]; +} gdc_warp_param_mem_t; + +#endif /* __GDC_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/gp_device_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/gp_device_global.h new file mode 100644 index 000000000..c8f416515 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/gp_device_global.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_GLOBAL_H_INCLUDED__ +#define __GP_DEVICE_GLOBAL_H_INCLUDED__ + +#define IS_GP_DEVICE_VERSION_2 + +#define _REG_GP_IRQ_REQ0_ADDR 0x08 +#define _REG_GP_IRQ_REQ1_ADDR 0x0C +/* The SP sends SW interrupt info to this register */ +#define _REG_GP_IRQ_REQUEST0_ADDR _REG_GP_IRQ_REQ0_ADDR +#define _REG_GP_IRQ_REQUEST1_ADDR _REG_GP_IRQ_REQ1_ADDR + +/* The SP configures FIFO switches in these registers */ +#define _REG_GP_SWITCH_IF_ADDR 0x40 +#define _REG_GP_SWITCH_GDC1_ADDR 0x44 +#define _REG_GP_SWITCH_GDC2_ADDR 0x48 +/* @ INPUT_FORMATTER_BASE -> GP_DEVICE_BASE */ +#define _REG_GP_IFMT_input_switch_lut_reg0 0x00030800 +#define _REG_GP_IFMT_input_switch_lut_reg1 0x00030804 +#define _REG_GP_IFMT_input_switch_lut_reg2 0x00030808 +#define _REG_GP_IFMT_input_switch_lut_reg3 0x0003080C +#define _REG_GP_IFMT_input_switch_lut_reg4 0x00030810 +#define _REG_GP_IFMT_input_switch_lut_reg5 0x00030814 +#define _REG_GP_IFMT_input_switch_lut_reg6 0x00030818 +#define _REG_GP_IFMT_input_switch_lut_reg7 0x0003081C +#define _REG_GP_IFMT_input_switch_fsync_lut 0x00030820 +#define _REG_GP_IFMT_srst 0x00030824 +#define _REG_GP_IFMT_slv_reg_srst 0x00030828 +#define _REG_GP_IFMT_input_switch_ch_id_fmt_type 0x0003082C + +/* @ GP_DEVICE_BASE */ +#define _REG_GP_SYNCGEN_ENABLE_ADDR 0x00090000 +#define _REG_GP_SYNCGEN_FREE_RUNNING_ADDR 0x00090004 +#define _REG_GP_SYNCGEN_PAUSE_ADDR 0x00090008 +#define _REG_GP_NR_FRAMES_ADDR 0x0009000C +#define _REG_GP_SYNGEN_NR_PIX_ADDR 0x00090010 +#define _REG_GP_SYNGEN_NR_LINES_ADDR 0x00090014 +#define _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR 0x00090018 +#define _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR 0x0009001C +#define _REG_GP_ISEL_SOF_ADDR 0x00090020 +#define _REG_GP_ISEL_EOF_ADDR 0x00090024 +#define _REG_GP_ISEL_SOL_ADDR 0x00090028 +#define _REG_GP_ISEL_EOL_ADDR 0x0009002C +#define _REG_GP_ISEL_LFSR_ENABLE_ADDR 0x00090030 +#define _REG_GP_ISEL_LFSR_ENABLE_B_ADDR 0x00090034 +#define _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR 0x00090038 +#define _REG_GP_ISEL_TPG_ENABLE_ADDR 0x0009003C +#define _REG_GP_ISEL_TPG_ENABLE_B_ADDR 0x00090040 +#define _REG_GP_ISEL_HOR_CNT_MASK_ADDR 0x00090044 +#define _REG_GP_ISEL_VER_CNT_MASK_ADDR 0x00090048 +#define _REG_GP_ISEL_XY_CNT_MASK_ADDR 0x0009004C +#define _REG_GP_ISEL_HOR_CNT_DELTA_ADDR 0x00090050 +#define _REG_GP_ISEL_VER_CNT_DELTA_ADDR 0x00090054 +#define _REG_GP_ISEL_TPG_MODE_ADDR 0x00090058 +#define _REG_GP_ISEL_TPG_RED1_ADDR 0x0009005C +#define _REG_GP_ISEL_TPG_GREEN1_ADDR 0x00090060 +#define _REG_GP_ISEL_TPG_BLUE1_ADDR 0x00090064 +#define _REG_GP_ISEL_TPG_RED2_ADDR 0x00090068 +#define _REG_GP_ISEL_TPG_GREEN2_ADDR 0x0009006C +#define _REG_GP_ISEL_TPG_BLUE2_ADDR 0x00090070 +#define _REG_GP_ISEL_CH_ID_ADDR 0x00090074 +#define _REG_GP_ISEL_FMT_TYPE_ADDR 0x00090078 +#define _REG_GP_ISEL_DATA_SEL_ADDR 0x0009007C +#define _REG_GP_ISEL_SBAND_SEL_ADDR 0x00090080 +#define _REG_GP_ISEL_SYNC_SEL_ADDR 0x00090084 +#define _REG_GP_SYNCGEN_HOR_CNT_ADDR 0x00090088 +#define _REG_GP_SYNCGEN_VER_CNT_ADDR 0x0009008C +#define _REG_GP_SYNCGEN_FRAME_CNT_ADDR 0x00090090 +#define _REG_GP_SOFT_RESET_ADDR 0x00090094 + +#endif /* __GP_DEVICE_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/gp_timer_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/gp_timer_global.h new file mode 100644 index 000000000..163003f2c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/gp_timer_global.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_GLOBAL_H_INCLUDED__ +#define __GP_TIMER_GLOBAL_H_INCLUDED__ + +#include "hive_isp_css_defs.h" /*HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ */ + +/* from gp_timer_defs.h*/ +#define GP_TIMER_COUNT_TYPE_HIGH 0 +#define GP_TIMER_COUNT_TYPE_LOW 1 +#define GP_TIMER_COUNT_TYPE_POSEDGE 2 +#define GP_TIMER_COUNT_TYPE_NEGEDGE 3 +#define GP_TIMER_COUNT_TYPE_TYPES 4 + +/* timer - 3 is selected */ +#define GP_TIMER_SEL 3 + +/*HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ is selected*/ +#define GP_TIMER_SIGNAL_SELECT HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ + +#endif /* __GP_TIMER_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/gpio_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/gpio_global.h new file mode 100644 index 000000000..b5f017482 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/gpio_global.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_GLOBAL_H_INCLUDED__ +#define __GPIO_GLOBAL_H_INCLUDED__ + +#define IS_GPIO_VERSION_1 + +#include + +/* pqiao: following part only defines in hive_isp_css_defs.h in fpga system. + port it here +*/ + +/* GPIO pin defines */ +/*#define HIVE_GPIO_CAMERA_BOARD_RESET_PIN_NR 0 +#define HIVE_GPIO_LCD_CLOCK_SELECT_PIN_NR 7 +#define HIVE_GPIO_HDMI_CLOCK_SELECT_PIN_NR 8 +#define HIVE_GPIO_LCD_VERT_FLIP_PIN_NR 8 +#define HIVE_GPIO_LCD_HOR_FLIP_PIN_NR 9 +#define HIVE_GPIO_AS3683_GPIO_P0_PIN_NR 1 +#define HIVE_GPIO_AS3683_DATA_P1_PIN_NR 2 +#define HIVE_GPIO_AS3683_CLK_P2_PIN_NR 3 +#define HIVE_GPIO_AS3683_T1_F0_PIN_NR 4 +#define HIVE_GPIO_AS3683_SFL_F1_PIN_NR 5 +#define HIVE_GPIO_AS3683_STROBE_F2_PIN_NR 6 +#define HIVE_GPIO_MAX1577_EN1_PIN_NR 1 +#define HIVE_GPIO_MAX1577_EN2_PIN_NR 2 +#define HIVE_GPIO_MAX8685A_EN_PIN_NR 3 +#define HIVE_GPIO_MAX8685A_TRIG_PIN_NR 4*/ + +#define HIVE_GPIO_STROBE_TRIGGER_PIN 2 + +#endif /* __GPIO_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/hmem_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/hmem_global.h new file mode 100644 index 000000000..746b07097 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/hmem_global.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_GLOBAL_H_INCLUDED__ +#define __HMEM_GLOBAL_H_INCLUDED__ + +#include + +#define IS_HMEM_VERSION_1 + +#include "isp.h" + +/* +#define ISP_HIST_ADDRESS_BITS 12 +#define ISP_HIST_ALIGNMENT 4 +#define ISP_HIST_COMP_IN_PREC 12 +#define ISP_HIST_DEPTH 1024 +#define ISP_HIST_WIDTH 24 +#define ISP_HIST_COMPONENTS 4 +*/ +#define ISP_HIST_ALIGNMENT_LOG2 2 + +#define HMEM_SIZE_LOG2 (ISP_HIST_ADDRESS_BITS - ISP_HIST_ALIGNMENT_LOG2) +#define HMEM_SIZE ISP_HIST_DEPTH + +#define HMEM_UNIT_SIZE (HMEM_SIZE / ISP_HIST_COMPONENTS) +#define HMEM_UNIT_COUNT ISP_HIST_COMPONENTS + +#define HMEM_RANGE_LOG2 ISP_HIST_WIDTH +#define HMEM_RANGE BIT(HMEM_RANGE_LOG2) + +typedef u32 hmem_data_t; + +#endif /* __HMEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug.c new file mode 100644 index 000000000..a502ba9f8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2016, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "debug.h" + +#include "hmm.h" + +#ifndef __INLINE_DEBUG__ +#include "debug_private.h" +#endif /* __INLINE_DEBUG__ */ + +#define __INLINE_SP__ +#include "sp.h" + +#include "assert_support.h" + +/* The address of the remote copy */ +hrt_address debug_buffer_address = (hrt_address) - 1; +ia_css_ptr debug_buffer_ddr_address = (ia_css_ptr)-1; +/* The local copy */ +static debug_data_t debug_data; +debug_data_t *debug_data_ptr = &debug_data; + +void debug_buffer_init(const hrt_address addr) +{ + debug_buffer_address = addr; + + debug_data.head = 0; + debug_data.tail = 0; +} + +void debug_buffer_ddr_init(const ia_css_ptr addr) +{ + debug_buf_mode_t mode = DEBUG_BUFFER_MODE_LINEAR; + u32 enable = 1; + u32 head = 0; + u32 tail = 0; + /* set the ddr queue */ + debug_buffer_ddr_address = addr; + hmm_store(addr + DEBUG_DATA_BUF_MODE_DDR_ADDR, + &mode, sizeof(debug_buf_mode_t)); + hmm_store(addr + DEBUG_DATA_HEAD_DDR_ADDR, + &head, sizeof(uint32_t)); + hmm_store(addr + DEBUG_DATA_TAIL_DDR_ADDR, + &tail, sizeof(uint32_t)); + hmm_store(addr + DEBUG_DATA_ENABLE_DDR_ADDR, + &enable, sizeof(uint32_t)); + + /* set the local copy */ + debug_data.head = 0; + debug_data.tail = 0; +} + +void debug_buffer_setmode(const debug_buf_mode_t mode) +{ + assert(debug_buffer_address != ((hrt_address)-1)); + + sp_dmem_store_uint32(SP0_ID, + debug_buffer_address + DEBUG_DATA_BUF_MODE_ADDR, mode); +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug_local.h new file mode 100644 index 000000000..536a4dcf0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug_local.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DEBUG_LOCAL_H_INCLUDED__ +#define __DEBUG_LOCAL_H_INCLUDED__ + +#include "debug_global.h" + +#endif /* __DEBUG_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug_private.h new file mode 100644 index 000000000..3fea43a21 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/debug_private.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DEBUG_PRIVATE_H_INCLUDED__ +#define __DEBUG_PRIVATE_H_INCLUDED__ + +#include "debug_public.h" + +#include "sp.h" + +#define __INLINE_ISP__ +#include "isp.h" + +#include "assert_support.h" + +STORAGE_CLASS_DEBUG_C bool is_debug_buffer_empty(void) +{ + return (debug_data_ptr->head == debug_data_ptr->tail); +} + +STORAGE_CLASS_DEBUG_C hrt_data debug_dequeue(void) +{ + hrt_data value = 0; + + assert(debug_buffer_address != ((hrt_address) - 1)); + + debug_synch_queue(); + + if (!is_debug_buffer_empty()) { + value = debug_data_ptr->buf[debug_data_ptr->head]; + debug_data_ptr->head = (debug_data_ptr->head + 1) & DEBUG_BUF_MASK; + sp_dmem_store_uint32(SP0_ID, debug_buffer_address + DEBUG_DATA_HEAD_ADDR, + debug_data_ptr->head); + } + + return value; +} + +STORAGE_CLASS_DEBUG_C void debug_synch_queue(void) +{ + u32 remote_tail = sp_dmem_load_uint32(SP0_ID, + debug_buffer_address + DEBUG_DATA_TAIL_ADDR); + /* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */ + if (remote_tail > debug_data_ptr->tail) { + size_t delta = remote_tail - debug_data_ptr->tail; + + sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR + + debug_data_ptr->tail * sizeof(uint32_t), + (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t)); + } else if (remote_tail < debug_data_ptr->tail) { + size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail; + + sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR + + debug_data_ptr->tail * sizeof(uint32_t), + (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t)); + sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR, + (void *)&debug_data_ptr->buf[0], + remote_tail * sizeof(uint32_t)); + } /* else we are up to date */ + debug_data_ptr->tail = remote_tail; +} + +STORAGE_CLASS_DEBUG_C void debug_synch_queue_isp(void) +{ + u32 remote_tail = isp_dmem_load_uint32(ISP0_ID, + DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_TAIL_ADDR); + /* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */ + if (remote_tail > debug_data_ptr->tail) { + size_t delta = remote_tail - debug_data_ptr->tail; + + isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR + + debug_data_ptr->tail * sizeof(uint32_t), + (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t)); + } else if (remote_tail < debug_data_ptr->tail) { + size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail; + + isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR + + debug_data_ptr->tail * sizeof(uint32_t), + (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t)); + isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR, + (void *)&debug_data_ptr->buf[0], + remote_tail * sizeof(uint32_t)); + } /* else we are up to date */ + debug_data_ptr->tail = remote_tail; +} + +STORAGE_CLASS_DEBUG_C void debug_synch_queue_ddr(void) +{ + u32 remote_tail; + + hmm_load(debug_buffer_ddr_address + DEBUG_DATA_TAIL_DDR_ADDR, &remote_tail, + sizeof(uint32_t)); + /* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */ + if (remote_tail > debug_data_ptr->tail) { + size_t delta = remote_tail - debug_data_ptr->tail; + + hmm_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR + + debug_data_ptr->tail * sizeof(uint32_t), + (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t)); + } else if (remote_tail < debug_data_ptr->tail) { + size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail; + + hmm_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR + + debug_data_ptr->tail * sizeof(uint32_t), + (void *)&debug_data_ptr->buf[debug_data_ptr->tail], delta * sizeof(uint32_t)); + hmm_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR, + (void *)&debug_data_ptr->buf[0], + remote_tail * sizeof(uint32_t)); + } /* else we are up to date */ + debug_data_ptr->tail = remote_tail; +} + +#endif /* __DEBUG_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma.c new file mode 100644 index 000000000..f85950c47 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2016, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "dma.h" + +#include "assert_support.h" + +#ifndef __INLINE_DMA__ +#include "dma_private.h" +#endif /* __INLINE_DMA__ */ + +void dma_get_state(const dma_ID_t ID, dma_state_t *state) +{ + int i; + hrt_data tmp; + + assert(ID < N_DMA_ID); + assert(state); + + tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX); + //reg [3:0] : flags error [3], stall, run, idle [0] + //reg [9:4] : command + //reg[14:10] : channel + //reg [23:15] : param + state->fsm_command_idle = tmp & 0x1; + state->fsm_command_run = tmp & 0x2; + state->fsm_command_stalling = tmp & 0x4; + state->fsm_command_error = tmp & 0x8; + state->last_command_channel = (tmp >> 10 & 0x1F); + state->last_command_param = (tmp >> 15 & 0x0F); + tmp = (tmp >> 4) & 0x3F; + /* state->last_command = (dma_commands_t)tmp; */ + /* if the enumerator is made non-linear */ + /* AM: the list below does not cover all the cases*/ + /* and these are not correct */ + /* therefore for just dumpinmg this command*/ + state->last_command = tmp; + + /* + if (tmp == 0) + state->last_command = DMA_COMMAND_READ; + if (tmp == 1) + state->last_command = DMA_COMMAND_WRITE; + if (tmp == 2) + state->last_command = DMA_COMMAND_SET_CHANNEL; + if (tmp == 3) + state->last_command = DMA_COMMAND_SET_PARAM; + if (tmp == 4) + state->last_command = DMA_COMMAND_READ_SPECIFIC; + if (tmp == 5) + state->last_command = DMA_COMMAND_WRITE_SPECIFIC; + if (tmp == 8) + state->last_command = DMA_COMMAND_INIT; + if (tmp == 12) + state->last_command = DMA_COMMAND_INIT_SPECIFIC; + if (tmp == 15) + state->last_command = DMA_COMMAND_RST; + */ + + /* No sub-fields, idx = 0 */ + state->current_command = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_CMD_IDX)); + state->current_addr_a = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_A_IDX)); + state->current_addr_b = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_B_IDX)); + + tmp = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_idle = tmp & 0x1; + state->fsm_ctrl_run = tmp & 0x2; + state->fsm_ctrl_stalling = tmp & 0x4; + state->fsm_ctrl_error = tmp & 0x8; + tmp = tmp >> 4; + /* state->fsm_ctrl_state = (dma_ctrl_states_t)tmp; */ + if (tmp == 0) + state->fsm_ctrl_state = DMA_CTRL_STATE_IDLE; + if (tmp == 1) + state->fsm_ctrl_state = DMA_CTRL_STATE_REQ_RCV; + if (tmp == 2) + state->fsm_ctrl_state = DMA_CTRL_STATE_RCV; + if (tmp == 3) + state->fsm_ctrl_state = DMA_CTRL_STATE_RCV_REQ; + if (tmp == 4) + state->fsm_ctrl_state = DMA_CTRL_STATE_INIT; + state->fsm_ctrl_source_dev = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_source_addr = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_source_stride = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_source_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_source_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_source_dev = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_dest_dev = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_dest_addr = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_dest_stride = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_source_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_dest_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_dest_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_source_elems = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_dest_elems = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_extension = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + + tmp = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_PACK_STATE_IDX, + _DMA_FSM_GROUP_FSM_PACK_IDX)); + state->pack_idle = tmp & 0x1; + state->pack_run = tmp & 0x2; + state->pack_stalling = tmp & 0x4; + state->pack_error = tmp & 0x8; + state->pack_cnt_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX, + _DMA_FSM_GROUP_FSM_PACK_IDX)); + state->pack_src_cnt_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX, + _DMA_FSM_GROUP_FSM_PACK_IDX)); + state->pack_dest_cnt_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX, + _DMA_FSM_GROUP_FSM_PACK_IDX)); + + tmp = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_REQ_STATE_IDX, + _DMA_FSM_GROUP_FSM_REQ_IDX)); + /* state->read_state = (dma_rw_states_t)tmp; */ + if (tmp == 0) + state->read_state = DMA_RW_STATE_IDLE; + if (tmp == 1) + state->read_state = DMA_RW_STATE_REQ; + if (tmp == 2) + state->read_state = DMA_RW_STATE_NEXT_LINE; + if (tmp == 3) + state->read_state = DMA_RW_STATE_UNLOCK_CHANNEL; + state->read_cnt_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX, + _DMA_FSM_GROUP_FSM_REQ_IDX)); + state->read_cnt_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX, + _DMA_FSM_GROUP_FSM_REQ_IDX)); + + tmp = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_WR_STATE_IDX, + _DMA_FSM_GROUP_FSM_WR_IDX)); + /* state->write_state = (dma_rw_states_t)tmp; */ + if (tmp == 0) + state->write_state = DMA_RW_STATE_IDLE; + if (tmp == 1) + state->write_state = DMA_RW_STATE_REQ; + if (tmp == 2) + state->write_state = DMA_RW_STATE_NEXT_LINE; + if (tmp == 3) + state->write_state = DMA_RW_STATE_UNLOCK_CHANNEL; + state->write_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX, + _DMA_FSM_GROUP_FSM_WR_IDX)); + state->write_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX, + _DMA_FSM_GROUP_FSM_WR_IDX)); + + for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) { + dma_port_state_t *port = &state->port_states[i]; + + tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(0, i)); + port->req_cs = ((tmp & 0x1) != 0); + port->req_we_n = ((tmp & 0x2) != 0); + port->req_run = ((tmp & 0x4) != 0); + port->req_ack = ((tmp & 0x8) != 0); + + tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(1, i)); + port->send_cs = ((tmp & 0x1) != 0); + port->send_we_n = ((tmp & 0x2) != 0); + port->send_run = ((tmp & 0x4) != 0); + port->send_ack = ((tmp & 0x8) != 0); + + tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(2, i)); + if (tmp & 0x1) + port->fifo_state = DMA_FIFO_STATE_WILL_BE_FULL; + if (tmp & 0x2) + port->fifo_state = DMA_FIFO_STATE_FULL; + if (tmp & 0x4) + port->fifo_state = DMA_FIFO_STATE_EMPTY; + port->fifo_counter = tmp >> 3; + } + + for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) { + dma_channel_state_t *ch = &state->channel_states[i]; + + ch->connection = DMA_GET_CONNECTION(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_PACKING_SETUP_PARAM))); + ch->sign_extend = DMA_GET_EXTENSION(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_PACKING_SETUP_PARAM))); + ch->height = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_HEIGHT_PARAM)); + ch->stride_a = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_STRIDE_A_PARAM)); + ch->elems_a = DMA_GET_ELEMENTS(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_ELEM_CROPPING_A_PARAM))); + ch->cropping_a = DMA_GET_CROPPING(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_ELEM_CROPPING_A_PARAM))); + ch->width_a = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_WIDTH_A_PARAM)); + ch->stride_b = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_STRIDE_B_PARAM)); + ch->elems_b = DMA_GET_ELEMENTS(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_ELEM_CROPPING_B_PARAM))); + ch->cropping_b = DMA_GET_CROPPING(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_ELEM_CROPPING_B_PARAM))); + ch->width_b = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_WIDTH_B_PARAM)); + } +} + +void +dma_set_max_burst_size(const dma_ID_t ID, dma_connection conn, + uint32_t max_burst_size) +{ + assert(ID < N_DMA_ID); + assert(max_burst_size > 0); + dma_reg_store(ID, DMA_DEV_INFO_REG_IDX(_DMA_DEV_INTERF_MAX_BURST_IDX, conn), + max_burst_size - 1); +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma_local.h new file mode 100644 index 000000000..7e4cc7573 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma_local.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_LOCAL_H_INCLUDED__ +#define __DMA_LOCAL_H_INCLUDED__ + +#include +#include "dma_global.h" + +#include /* HRTCAT() */ +#include /* _hrt_get_bits() */ +#include /* HIVE_DMA_NUM_CHANNELS */ +#include + +#define _DMA_FSM_GROUP_CMD_IDX _DMA_V2_FSM_GROUP_CMD_IDX +#define _DMA_FSM_GROUP_ADDR_A_IDX _DMA_V2_FSM_GROUP_ADDR_SRC_IDX +#define _DMA_FSM_GROUP_ADDR_B_IDX _DMA_V2_FSM_GROUP_ADDR_DEST_IDX + +#define _DMA_FSM_GROUP_CMD_CTRL_IDX _DMA_V2_FSM_GROUP_CMD_CTRL_IDX + +#define _DMA_FSM_GROUP_FSM_CTRL_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX + +#define _DMA_FSM_GROUP_FSM_PACK_IDX _DMA_V2_FSM_GROUP_FSM_PACK_IDX +#define _DMA_FSM_GROUP_FSM_PACK_STATE_IDX _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX +#define _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX +#define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX +#define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX + +#define _DMA_FSM_GROUP_FSM_REQ_IDX _DMA_V2_FSM_GROUP_FSM_REQ_IDX +#define _DMA_FSM_GROUP_FSM_REQ_STATE_IDX _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX +#define _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX +#define _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX + +#define _DMA_FSM_GROUP_FSM_WR_IDX _DMA_V2_FSM_GROUP_FSM_WR_IDX +#define _DMA_FSM_GROUP_FSM_WR_STATE_IDX _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX +#define _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX +#define _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX + +#define _DMA_DEV_INTERF_MAX_BURST_IDX _DMA_V2_DEV_INTERF_MAX_BURST_IDX + +/* + * Macro's to compute the DMA parameter register indices + */ +#define DMA_SEL_COMP(comp) (((comp) & _hrt_ones(_DMA_V2_ADDR_SEL_COMP_BITS)) << _DMA_V2_ADDR_SEL_COMP_IDX) +#define DMA_SEL_CH(ch) (((ch) & _hrt_ones(_DMA_V2_ADDR_SEL_CH_REG_BITS)) << _DMA_V2_ADDR_SEL_CH_REG_IDX) +#define DMA_SEL_PARAM(param) (((param) & _hrt_ones(_DMA_V2_ADDR_SEL_PARAM_BITS)) << _DMA_V2_ADDR_SEL_PARAM_IDX) +/* CG = Connection Group */ +#define DMA_SEL_CG_INFO(info) (((info) & _hrt_ones(_DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS)) << _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX) +#define DMA_SEL_CG_COMP(comp) (((comp) & _hrt_ones(_DMA_V2_ADDR_SEL_GROUP_COMP_BITS)) << _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) +#define DMA_SEL_DEV_INFO(info) (((info) & _hrt_ones(_DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS)) << _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX) +#define DMA_SEL_DEV_ID(dev) (((dev) & _hrt_ones(_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)) << _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX) + +#define DMA_COMMAND_FSM_REG_IDX (DMA_SEL_COMP(_DMA_V2_SEL_FSM_CMD) >> 2) +#define DMA_CHANNEL_PARAM_REG_IDX(ch, param) ((DMA_SEL_COMP(_DMA_V2_SEL_CH_REG) | DMA_SEL_CH(ch) | DMA_SEL_PARAM(param)) >> 2) +#define DMA_CG_INFO_REG_IDX(info_id, comp_id) ((DMA_SEL_COMP(_DMA_V2_SEL_CONN_GROUP) | DMA_SEL_CG_INFO(info_id) | DMA_SEL_CG_COMP(comp_id)) >> 2) +#define DMA_DEV_INFO_REG_IDX(info_id, dev_id) ((DMA_SEL_COMP(_DMA_V2_SEL_DEV_INTERF) | DMA_SEL_DEV_INFO(info_id) | DMA_SEL_DEV_ID(dev_id)) >> 2) +#define DMA_RST_REG_IDX (DMA_SEL_COMP(_DMA_V2_SEL_RESET) >> 2) + +#define DMA_GET_CONNECTION(val) _hrt_get_bits(val, _DMA_V2_CONNECTION_IDX, _DMA_V2_CONNECTION_BITS) +#define DMA_GET_EXTENSION(val) _hrt_get_bits(val, _DMA_V2_EXTENSION_IDX, _DMA_V2_EXTENSION_BITS) +#define DMA_GET_ELEMENTS(val) _hrt_get_bits(val, _DMA_V2_ELEMENTS_IDX, _DMA_V2_ELEMENTS_BITS) +#define DMA_GET_CROPPING(val) _hrt_get_bits(val, _DMA_V2_LEFT_CROPPING_IDX, _DMA_V2_LEFT_CROPPING_BITS) + +typedef enum { + DMA_CTRL_STATE_IDLE, + DMA_CTRL_STATE_REQ_RCV, + DMA_CTRL_STATE_RCV, + DMA_CTRL_STATE_RCV_REQ, + DMA_CTRL_STATE_INIT, + N_DMA_CTRL_STATES +} dma_ctrl_states_t; + +typedef enum { + DMA_COMMAND_READ, + DMA_COMMAND_WRITE, + DMA_COMMAND_SET_CHANNEL, + DMA_COMMAND_SET_PARAM, + DMA_COMMAND_READ_SPECIFIC, + DMA_COMMAND_WRITE_SPECIFIC, + DMA_COMMAND_INIT, + DMA_COMMAND_INIT_SPECIFIC, + DMA_COMMAND_RST, + N_DMA_COMMANDS +} dma_commands_t; + +typedef enum { + DMA_RW_STATE_IDLE, + DMA_RW_STATE_REQ, + DMA_RW_STATE_NEXT_LINE, + DMA_RW_STATE_UNLOCK_CHANNEL, + N_DMA_RW_STATES +} dma_rw_states_t; + +typedef enum { + DMA_FIFO_STATE_WILL_BE_FULL, + DMA_FIFO_STATE_FULL, + DMA_FIFO_STATE_EMPTY, + N_DMA_FIFO_STATES +} dma_fifo_states_t; + +/* typedef struct dma_state_s dma_state_t; */ +typedef struct dma_channel_state_s dma_channel_state_t; +typedef struct dma_port_state_s dma_port_state_t; + +struct dma_port_state_s { + bool req_cs; + bool req_we_n; + bool req_run; + bool req_ack; + bool send_cs; + bool send_we_n; + bool send_run; + bool send_ack; + dma_fifo_states_t fifo_state; + int fifo_counter; +}; + +struct dma_channel_state_s { + int connection; + bool sign_extend; + int height; + int stride_a; + int elems_a; + int cropping_a; + int width_a; + int stride_b; + int elems_b; + int cropping_b; + int width_b; +}; + +struct dma_state_s { + bool fsm_command_idle; + bool fsm_command_run; + bool fsm_command_stalling; + bool fsm_command_error; + dma_commands_t last_command; + int last_command_channel; + int last_command_param; + dma_commands_t current_command; + int current_addr_a; + int current_addr_b; + bool fsm_ctrl_idle; + bool fsm_ctrl_run; + bool fsm_ctrl_stalling; + bool fsm_ctrl_error; + dma_ctrl_states_t fsm_ctrl_state; + int fsm_ctrl_source_dev; + int fsm_ctrl_source_addr; + int fsm_ctrl_source_stride; + int fsm_ctrl_source_width; + int fsm_ctrl_source_height; + int fsm_ctrl_pack_source_dev; + int fsm_ctrl_pack_dest_dev; + int fsm_ctrl_dest_addr; + int fsm_ctrl_dest_stride; + int fsm_ctrl_pack_source_width; + int fsm_ctrl_pack_dest_height; + int fsm_ctrl_pack_dest_width; + int fsm_ctrl_pack_source_elems; + int fsm_ctrl_pack_dest_elems; + int fsm_ctrl_pack_extension; + int pack_idle; + int pack_run; + int pack_stalling; + int pack_error; + int pack_cnt_height; + int pack_src_cnt_width; + int pack_dest_cnt_width; + dma_rw_states_t read_state; + int read_cnt_height; + int read_cnt_width; + dma_rw_states_t write_state; + int write_height; + int write_width; + dma_port_state_t port_states[HIVE_ISP_NUM_DMA_CONNS]; + dma_channel_state_t channel_states[HIVE_DMA_NUM_CHANNELS]; +}; + +#endif /* __DMA_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma_private.h new file mode 100644 index 000000000..1f62bc2f1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma_private.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_PRIVATE_H_INCLUDED__ +#define __DMA_PRIVATE_H_INCLUDED__ + +#include "dma_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_DMA_C void dma_reg_store(const dma_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + assert(ID < N_DMA_ID); + assert(DMA_BASE[ID] != (hrt_address) - 1); + ia_css_device_store_uint32(DMA_BASE[ID] + reg * sizeof(hrt_data), value); +} + +STORAGE_CLASS_DMA_C hrt_data dma_reg_load(const dma_ID_t ID, + const unsigned int reg) +{ + assert(ID < N_DMA_ID); + assert(DMA_BASE[ID] != (hrt_address) - 1); + return ia_css_device_load_uint32(DMA_BASE[ID] + reg * sizeof(hrt_data)); +} + +#endif /* __DMA_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo.c new file mode 100644 index 000000000..62d4809e3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "event_fifo.h" + +#ifndef __INLINE_EVENT__ +#include "event_fifo_private.h" +#endif /* __INLINE_EVENT__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo_local.h new file mode 100644 index 000000000..25d382302 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo_local.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _EVENT_FIFO_LOCAL_H +#define _EVENT_FIFO_LOCAL_H + +/* + * All events come from connections mapped on the system + * bus but do not use a global IRQ + */ +#include "event_fifo_global.h" + +typedef enum { + SP0_EVENT_ID, + ISP0_EVENT_ID, + STR2MIPI_EVENT_ID, + N_EVENT_ID +} event_ID_t; + +#define EVENT_QUERY_BIT 0 + +/* Events are read from FIFO */ +static const hrt_address event_source_addr[N_EVENT_ID] = { + 0x0000000000380000ULL, + 0x0000000000380004ULL, + 0xffffffffffffffffULL +}; + +/* Read from FIFO are blocking, query data availability */ +static const hrt_address event_source_query_addr[N_EVENT_ID] = { + 0x0000000000380010ULL, + 0x0000000000380014ULL, + 0xffffffffffffffffULL +}; + +/* Events are written to FIFO */ +static const hrt_address event_sink_addr[N_EVENT_ID] = { + 0x0000000000380008ULL, + 0x000000000038000CULL, + 0x0000000000090104ULL +}; + +/* Writes to FIFO are blocking, query data space */ +static const hrt_address event_sink_query_addr[N_EVENT_ID] = { + 0x0000000000380018ULL, + 0x000000000038001CULL, + 0x000000000009010CULL +}; + +#endif /* _EVENT_FIFO_LOCAL_H */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo_private.h new file mode 100644 index 000000000..f59d45cc7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo_private.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __EVENT_FIFO_PRIVATE_H +#define __EVENT_FIFO_PRIVATE_H + +#include "event_fifo_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +#include /* _hrt_get_bits() */ + +STORAGE_CLASS_EVENT_C void event_wait_for(const event_ID_t ID) +{ + assert(ID < N_EVENT_ID); + assert(event_source_addr[ID] != ((hrt_address) - 1)); + (void)ia_css_device_load_uint32(event_source_addr[ID]); + return; +} + +STORAGE_CLASS_EVENT_C void cnd_event_wait_for(const event_ID_t ID, + const bool cnd) +{ + if (cnd) { + event_wait_for(ID); + } +} + +STORAGE_CLASS_EVENT_C hrt_data event_receive_token(const event_ID_t ID) +{ + assert(ID < N_EVENT_ID); + assert(event_source_addr[ID] != ((hrt_address) - 1)); + return ia_css_device_load_uint32(event_source_addr[ID]); +} + +STORAGE_CLASS_EVENT_C void event_send_token(const event_ID_t ID, + const hrt_data token) +{ + assert(ID < N_EVENT_ID); + assert(event_sink_addr[ID] != ((hrt_address) - 1)); + ia_css_device_store_uint32(event_sink_addr[ID], token); +} + +STORAGE_CLASS_EVENT_C bool is_event_pending(const event_ID_t ID) +{ + hrt_data value; + + assert(ID < N_EVENT_ID); + assert(event_source_query_addr[ID] != ((hrt_address) - 1)); + value = ia_css_device_load_uint32(event_source_query_addr[ID]); + return !_hrt_get_bit(value, EVENT_QUERY_BIT); +} + +STORAGE_CLASS_EVENT_C bool can_event_send_token(const event_ID_t ID) +{ + hrt_data value; + + assert(ID < N_EVENT_ID); + assert(event_sink_query_addr[ID] != ((hrt_address) - 1)); + value = ia_css_device_load_uint32(event_sink_query_addr[ID]); + return !_hrt_get_bit(value, EVENT_QUERY_BIT); +} + +#endif /* __EVENT_FIFO_PRIVATE_H */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor.c new file mode 100644 index 000000000..01698064b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor.c @@ -0,0 +1,570 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "fifo_monitor.h" + +#include +#include "device_access.h" + +#include + +#include "gp_device.h" + +#include "assert_support.h" + +#ifndef __INLINE_FIFO_MONITOR__ +#define STORAGE_CLASS_FIFO_MONITOR_DATA static const +#else +#define STORAGE_CLASS_FIFO_MONITOR_DATA const +#endif /* __INLINE_FIFO_MONITOR__ */ + +STORAGE_CLASS_FIFO_MONITOR_DATA unsigned int FIFO_SWITCH_ADDR[N_FIFO_SWITCH] = { + _REG_GP_SWITCH_IF_ADDR, + _REG_GP_SWITCH_GDC1_ADDR, + _REG_GP_SWITCH_GDC2_ADDR +}; + +#ifndef __INLINE_FIFO_MONITOR__ +#include "fifo_monitor_private.h" +#endif /* __INLINE_FIFO_MONITOR__ */ + +static inline bool fifo_monitor_status_valid( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const unsigned int port_id); + +static inline bool fifo_monitor_status_accept( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const unsigned int port_id); + +void fifo_channel_get_state( + const fifo_monitor_ID_t ID, + const fifo_channel_t channel_id, + fifo_channel_state_t *state) +{ + assert(channel_id < N_FIFO_CHANNEL); + assert(state); + + switch (channel_id) { + case FIFO_CHANNEL_ISP0_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_SP); /* ISP_STR_MON_PORT_ISP2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_SP); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_ISP); /* ISP_STR_MON_PORT_SP2ISP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_ISP); + break; + case FIFO_CHANNEL_SP0_TO_ISP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_ISP); /* ISP_STR_MON_PORT_SP2ISP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_ISP); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_SP); /* ISP_STR_MON_PORT_ISP2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_SP); + break; + case FIFO_CHANNEL_ISP0_TO_IF0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_PIF_A); /* ISP_STR_MON_PORT_ISP2PIFA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_PIF_A); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_A); /* MOD_STR_MON_PORT_CELLS2PIFA */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_A); + break; + case FIFO_CHANNEL_IF0_TO_ISP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_A); /* MOD_STR_MON_PORT_PIFA2CELLS */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_A); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_A); /* ISP_STR_MON_PORT_PIFA2ISP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_A); + break; + case FIFO_CHANNEL_ISP0_TO_IF1: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_PIF_B); /* ISP_STR_MON_PORT_ISP2PIFA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_PIF_B); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_B); /* MOD_STR_MON_PORT_CELLS2PIFB */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_B); + break; + case FIFO_CHANNEL_IF1_TO_ISP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_B); /* MOD_STR_MON_PORT_PIFB2CELLS */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_B); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_B); /* ISP_STR_MON_PORT_PIFB2ISP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_B); + break; + case FIFO_CHANNEL_ISP0_TO_DMA0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_DMA); /* ISP_STR_MON_PORT_ISP2DMA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_DMA); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_DMA_FR_ISP); /* MOD_STR_MON_PORT_ISP2DMA */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_DMA_FR_ISP); + break; + case FIFO_CHANNEL_DMA0_TO_ISP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_DMA2ISP); /* MOD_STR_MON_PORT_DMA2ISP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_DMA2ISP); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_DMA); /* ISP_STR_MON_PORT_DMA2ISP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_DMA); + break; + case FIFO_CHANNEL_ISP0_TO_GDC0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_GDC); /* ISP_STR_MON_PORT_ISP2GDC1 */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_GDC); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_GDC); /* MOD_STR_MON_PORT_CELLS2GDC1 */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_GDC); + break; + case FIFO_CHANNEL_GDC0_TO_ISP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_GDC); /* MOD_STR_MON_PORT_GDC12CELLS */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_GDC); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_GDC); /* ISP_STR_MON_PORT_GDC12ISP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_GDC); + break; + case FIFO_CHANNEL_ISP0_TO_GDC1: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_ISP2GDC2); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_ISP2GDC2); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC2); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC2); + break; + case FIFO_CHANNEL_GDC1_TO_ISP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC22CELLS); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC22CELLS); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_GDC22ISP); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_GDC22ISP); + break; + case FIFO_CHANNEL_ISP0_TO_HOST0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_GPD); /* ISP_STR_MON_PORT_ISP2GPD */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_GPD); + { + hrt_data value = ia_css_device_load_uint32(0x0000000000380014ULL); + + state->fifo_valid = !_hrt_get_bit(value, 0); + state->sink_accept = false; /* no monitor connected */ + } + break; + case FIFO_CHANNEL_HOST0_TO_ISP0: { + hrt_data value = ia_css_device_load_uint32(0x000000000038001CULL); + + state->fifo_valid = false; /* no monitor connected */ + state->sink_accept = !_hrt_get_bit(value, 0); + } + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_GPD); /* ISP_STR_MON_PORT_FA2ISP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_GPD); + break; + case FIFO_CHANNEL_SP0_TO_IF0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_PIF_A); /* SP_STR_MON_PORT_SP2PIFA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_PIF_A); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_A); /* MOD_STR_MON_PORT_CELLS2PIFA */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_A); + break; + case FIFO_CHANNEL_IF0_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_A); /* MOD_STR_MON_PORT_PIFA2CELLS */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_A); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_PIF_A); /* SP_STR_MON_PORT_PIFA2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_PIF_A); + break; + case FIFO_CHANNEL_SP0_TO_IF1: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_PIF_B); /* SP_STR_MON_PORT_SP2PIFB */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_PIF_B); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_B); /* MOD_STR_MON_PORT_CELLS2PIFB */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_B); + break; + case FIFO_CHANNEL_IF1_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_B); /* MOD_STR_MON_PORT_PIFB2CELLS */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_B); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_B); /* SP_STR_MON_PORT_PIFB2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_B); + break; + case FIFO_CHANNEL_SP0_TO_IF2: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_SIF); /* SP_STR_MON_PORT_SP2SIF */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_SIF); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_SIF); /* MOD_STR_MON_PORT_SP2SIF */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_SIF); + break; + case FIFO_CHANNEL_IF2_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_SIF); /* MOD_STR_MON_PORT_SIF2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_SIF); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_SIF); /* SP_STR_MON_PORT_SIF2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_SIF); + break; + case FIFO_CHANNEL_SP0_TO_DMA0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_DMA); /* SP_STR_MON_PORT_SP2DMA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_DMA); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_DMA_FR_SP); /* MOD_STR_MON_PORT_SP2DMA */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_DMA_FR_SP); + break; + case FIFO_CHANNEL_DMA0_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_DMA2SP); /* MOD_STR_MON_PORT_DMA2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_DMA2SP); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_DMA); /* SP_STR_MON_PORT_DMA2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_DMA); + break; + case FIFO_CHANNEL_SP0_TO_GDC0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_SP2GDC1); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_SP2GDC1); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC1); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC1); + break; + case FIFO_CHANNEL_GDC0_TO_SP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC12CELLS); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC12CELLS); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_GDC12SP); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_GDC12SP); + break; + case FIFO_CHANNEL_SP0_TO_GDC1: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_SP2GDC2); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_SP2GDC2); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC2); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC2); + break; + case FIFO_CHANNEL_GDC1_TO_SP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC22CELLS); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC22CELLS); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_GDC22SP); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_GDC22SP); + break; + case FIFO_CHANNEL_SP0_TO_HOST0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_GPD); /* SP_STR_MON_PORT_SP2GPD */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_GPD); + { + hrt_data value = ia_css_device_load_uint32(0x0000000000380010ULL); + + state->fifo_valid = !_hrt_get_bit(value, 0); + state->sink_accept = false; /* no monitor connected */ + } + break; + case FIFO_CHANNEL_HOST0_TO_SP0: { + hrt_data value = ia_css_device_load_uint32(0x0000000000380018ULL); + + state->fifo_valid = false; /* no monitor connected */ + state->sink_accept = !_hrt_get_bit(value, 0); + } + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_GPD); /* SP_STR_MON_PORT_FA2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_GPD); + break; + case FIFO_CHANNEL_SP0_TO_STREAM2MEM0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_MC); /* SP_STR_MON_PORT_SP2MC */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_MC); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_MC); /* MOD_STR_MON_PORT_SP2MC */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_MC); + break; + case FIFO_CHANNEL_STREAM2MEM0_TO_SP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_MC); /* SP_STR_MON_PORT_MC2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_MC); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_MC); /* MOD_STR_MON_PORT_MC2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_MC); + break; + case FIFO_CHANNEL_SP0_TO_INPUT_SYSTEM0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SP2ISYS); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SP2ISYS); + state->fifo_valid = false; + state->sink_accept = false; + break; + case FIFO_CHANNEL_INPUT_SYSTEM0_TO_SP0: + state->fifo_valid = false; + state->sink_accept = false; + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_ISYS2SP); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_ISYS2SP); + break; + default: + assert(0); + break; + } + + return; +} + +void fifo_switch_get_state( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id, + fifo_switch_state_t *state) +{ + hrt_data data = (hrt_data)-1; + + assert(ID == FIFO_MONITOR0_ID); + assert(switch_id < N_FIFO_SWITCH); + assert(state); + + (void)ID; + + data = gp_device_reg_load(GP_DEVICE0_ID, FIFO_SWITCH_ADDR[switch_id]); + + state->is_none = (data == HIVE_ISP_CSS_STREAM_SWITCH_NONE); + state->is_sp = (data == HIVE_ISP_CSS_STREAM_SWITCH_SP); + state->is_isp = (data == HIVE_ISP_CSS_STREAM_SWITCH_ISP); + + return; +} + +void fifo_monitor_get_state( + const fifo_monitor_ID_t ID, + fifo_monitor_state_t *state) +{ + fifo_channel_t ch_id; + fifo_switch_t sw_id; + + assert(ID < N_FIFO_MONITOR_ID); + assert(state); + + for (ch_id = 0; ch_id < N_FIFO_CHANNEL; ch_id++) { + fifo_channel_get_state(ID, ch_id, + &state->fifo_channels[ch_id]); + } + + for (sw_id = 0; sw_id < N_FIFO_SWITCH; sw_id++) { + fifo_switch_get_state(ID, sw_id, + &state->fifo_switches[sw_id]); + } + return; +} + +static inline bool fifo_monitor_status_valid( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const unsigned int port_id) +{ + hrt_data data = fifo_monitor_reg_load(ID, reg); + + return (data >> (((port_id * 2) + _hive_str_mon_valid_offset))) & 0x1; +} + +static inline bool fifo_monitor_status_accept( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const unsigned int port_id) +{ + hrt_data data = fifo_monitor_reg_load(ID, reg); + + return (data >> (((port_id * 2) + _hive_str_mon_accept_offset))) & 0x1; +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor_local.h new file mode 100644 index 000000000..dfdca944a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor_local.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_LOCAL_H_INCLUDED__ +#define __FIFO_MONITOR_LOCAL_H_INCLUDED__ + +#include +#include "fifo_monitor_global.h" + +#include "hive_isp_css_defs.h" /* ISP_STR_MON_PORT_SND_SP, ... */ + +#define _hive_str_mon_valid_offset 0 +#define _hive_str_mon_accept_offset 1 + +#define FIFO_CHANNEL_SP_VALID_MASK 0x55555555 +#define FIFO_CHANNEL_SP_VALID_B_MASK 0x00000055 +#define FIFO_CHANNEL_ISP_VALID_MASK 0x15555555 +#define FIFO_CHANNEL_MOD_VALID_MASK 0x55555555 + +typedef enum fifo_switch { + FIFO_SWITCH_IF, + FIFO_SWITCH_GDC0, + FIFO_SWITCH_GDC1, + N_FIFO_SWITCH +} fifo_switch_t; + +typedef enum fifo_channel { + FIFO_CHANNEL_ISP0_TO_SP0, + FIFO_CHANNEL_SP0_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_IF0, + FIFO_CHANNEL_IF0_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_IF1, + FIFO_CHANNEL_IF1_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_DMA0, + FIFO_CHANNEL_DMA0_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_GDC0, + FIFO_CHANNEL_GDC0_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_GDC1, + FIFO_CHANNEL_GDC1_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_HOST0, + FIFO_CHANNEL_HOST0_TO_ISP0, + FIFO_CHANNEL_SP0_TO_IF0, + FIFO_CHANNEL_IF0_TO_SP0, + FIFO_CHANNEL_SP0_TO_IF1, + FIFO_CHANNEL_IF1_TO_SP0, + FIFO_CHANNEL_SP0_TO_IF2, + FIFO_CHANNEL_IF2_TO_SP0, + FIFO_CHANNEL_SP0_TO_DMA0, + FIFO_CHANNEL_DMA0_TO_SP0, + FIFO_CHANNEL_SP0_TO_GDC0, + FIFO_CHANNEL_GDC0_TO_SP0, + FIFO_CHANNEL_SP0_TO_GDC1, + FIFO_CHANNEL_GDC1_TO_SP0, + FIFO_CHANNEL_SP0_TO_HOST0, + FIFO_CHANNEL_HOST0_TO_SP0, + FIFO_CHANNEL_SP0_TO_STREAM2MEM0, + FIFO_CHANNEL_STREAM2MEM0_TO_SP0, + FIFO_CHANNEL_SP0_TO_INPUT_SYSTEM0, + FIFO_CHANNEL_INPUT_SYSTEM0_TO_SP0, + /* + * No clue what this is + * + FIFO_CHANNEL_SP0_TO_IRQ0, + FIFO_CHANNEL_IRQ0_TO_SP0, + */ + N_FIFO_CHANNEL +} fifo_channel_t; + +struct fifo_channel_state_s { + bool src_valid; + bool fifo_accept; + bool fifo_valid; + bool sink_accept; +}; + +/* The switch is tri-state */ +struct fifo_switch_state_s { + bool is_none; + bool is_isp; + bool is_sp; +}; + +struct fifo_monitor_state_s { + struct fifo_channel_state_s fifo_channels[N_FIFO_CHANNEL]; + struct fifo_switch_state_s fifo_switches[N_FIFO_SWITCH]; +}; + +#endif /* __FIFO_MONITOR_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor_private.h new file mode 100644 index 000000000..10d9c076c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/fifo_monitor_private.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_PRIVATE_H_INCLUDED__ +#define __FIFO_MONITOR_PRIVATE_H_INCLUDED__ + +#include "fifo_monitor_public.h" + +#define __INLINE_GP_DEVICE__ +#include "gp_device.h" + +#include "device_access.h" + +#include "assert_support.h" + +#ifdef __INLINE_FIFO_MONITOR__ +extern const unsigned int FIFO_SWITCH_ADDR[N_FIFO_SWITCH]; +#endif + +STORAGE_CLASS_FIFO_MONITOR_C void fifo_switch_set( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id, + const hrt_data sel) +{ + assert(ID == FIFO_MONITOR0_ID); + assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); + assert(switch_id < N_FIFO_SWITCH); + (void)ID; + + gp_device_reg_store(GP_DEVICE0_ID, FIFO_SWITCH_ADDR[switch_id], sel); + + return; +} + +STORAGE_CLASS_FIFO_MONITOR_C hrt_data fifo_switch_get( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id) +{ + assert(ID == FIFO_MONITOR0_ID); + assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); + assert(switch_id < N_FIFO_SWITCH); + (void)ID; + + return gp_device_reg_load(GP_DEVICE0_ID, FIFO_SWITCH_ADDR[switch_id]); +} + +STORAGE_CLASS_FIFO_MONITOR_C void fifo_monitor_reg_store( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + assert(ID < N_FIFO_MONITOR_ID); + assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); + ia_css_device_store_uint32(FIFO_MONITOR_BASE[ID] + reg * sizeof(hrt_data), + value); + return; +} + +STORAGE_CLASS_FIFO_MONITOR_C hrt_data fifo_monitor_reg_load( + const fifo_monitor_ID_t ID, + const unsigned int reg) +{ + assert(ID < N_FIFO_MONITOR_ID); + assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); + return ia_css_device_load_uint32(FIFO_MONITOR_BASE[ID] + reg * sizeof( + hrt_data)); +} + +#endif /* __FIFO_MONITOR_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc.c new file mode 100644 index 000000000..25e082d6a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* The name "gdc.h is already taken" */ +#include "gdc_device.h" + +#include "device_access.h" + +#include "assert_support.h" + +/* + * Local function declarations + */ +static inline void gdc_reg_store( + const gdc_ID_t ID, + const unsigned int reg, + const hrt_data value); + +#ifndef __INLINE_GDC__ +#include "gdc_private.h" +#endif /* __INLINE_GDC__ */ + +/* + * Exported function implementations + */ +void gdc_lut_store( + const gdc_ID_t ID, + const int data[4][HRT_GDC_N]) +{ + unsigned int i, lut_offset = HRT_GDC_LUT_IDX; + + assert(ID < N_GDC_ID); + assert(HRT_GDC_LUT_COEFF_OFFSET <= (4 * sizeof(hrt_data))); + + for (i = 0; i < HRT_GDC_N; i++) { + hrt_data entry_0 = data[0][i] & HRT_GDC_BCI_COEF_MASK; + hrt_data entry_1 = data[1][i] & HRT_GDC_BCI_COEF_MASK; + hrt_data entry_2 = data[2][i] & HRT_GDC_BCI_COEF_MASK; + hrt_data entry_3 = data[3][i] & HRT_GDC_BCI_COEF_MASK; + + hrt_data word_0 = entry_0 | + (entry_1 << HRT_GDC_LUT_COEFF_OFFSET); + hrt_data word_1 = entry_2 | + (entry_3 << HRT_GDC_LUT_COEFF_OFFSET); + + gdc_reg_store(ID, lut_offset++, word_0); + gdc_reg_store(ID, lut_offset++, word_1); + } + return; +} + +/* + * Input LUT format: + * c0[0-1023], c1[0-1023], c2[0-1023] c3[0-1023] + * + * Output LUT format (interleaved): + * c0[0], c1[0], c2[0], c3[0], c0[1], c1[1], c2[1], c3[1], .... + * c0[1023], c1[1023], c2[1023], c3[1023] + * + * The first format needs c0[0], c1[0] (which are 1024 words apart) + * to program gdc LUT registers. This makes it difficult to do piecemeal + * reads in SP side gdc_lut_store + * + * Interleaved format allows use of contiguous bytes to store into + * gdc LUT registers. + * + * See gdc_lut_store() definition in host/gdc.c vs sp/gdc_private.h + * + */ +void gdc_lut_convert_to_isp_format(const int in_lut[4][HRT_GDC_N], + int out_lut[4][HRT_GDC_N]) +{ + unsigned int i; + int *out = (int *)out_lut; + + for (i = 0; i < HRT_GDC_N; i++) { + out[0] = in_lut[0][i]; + out[1] = in_lut[1][i]; + out[2] = in_lut[2][i]; + out[3] = in_lut[3][i]; + out += 4; + } +} + +int gdc_get_unity( + const gdc_ID_t ID) +{ + assert(ID < N_GDC_ID); + (void)ID; + return (int)(1UL << HRT_GDC_FRAC_BITS); +} + +/* + * Local function implementations + */ +static inline void gdc_reg_store( + const gdc_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + ia_css_device_store_uint32(GDC_BASE[ID] + reg * sizeof(hrt_data), value); + return; +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc_local.h new file mode 100644 index 000000000..4b2b3282c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc_local.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_LOCAL_H_INCLUDED__ +#define __GDC_LOCAL_H_INCLUDED__ + +#include "gdc_global.h" + +#endif /* __GDC_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc_private.h new file mode 100644 index 000000000..73051112f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gdc_private.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_PRIVATE_H_INCLUDED__ +#define __GDC_PRIVATE_H_INCLUDED__ + +#include "gdc_public.h" + +#endif /* __GDC_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device.c new file mode 100644 index 000000000..a80e547d4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "assert_support.h" +#include "gp_device.h" + +#ifndef __INLINE_GP_DEVICE__ +#include "gp_device_private.h" +#endif /* __INLINE_GP_DEVICE__ */ + +void gp_device_get_state( + const gp_device_ID_t ID, + gp_device_state_t *state) +{ + assert(ID < N_GP_DEVICE_ID); + assert(state); + + state->syncgen_enable = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_ENABLE_ADDR); + state->syncgen_free_running = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_FREE_RUNNING_ADDR); + state->syncgen_pause = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_PAUSE_ADDR); + state->nr_frames = gp_device_reg_load(ID, + _REG_GP_NR_FRAMES_ADDR); + state->syngen_nr_pix = gp_device_reg_load(ID, + _REG_GP_SYNGEN_NR_PIX_ADDR); + state->syngen_nr_pix = gp_device_reg_load(ID, + _REG_GP_SYNGEN_NR_PIX_ADDR); + state->syngen_nr_lines = gp_device_reg_load(ID, + _REG_GP_SYNGEN_NR_LINES_ADDR); + state->syngen_hblank_cycles = gp_device_reg_load(ID, + _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR); + state->syngen_vblank_cycles = gp_device_reg_load(ID, + _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR); + state->isel_sof = gp_device_reg_load(ID, + _REG_GP_ISEL_SOF_ADDR); + state->isel_eof = gp_device_reg_load(ID, + _REG_GP_ISEL_EOF_ADDR); + state->isel_sol = gp_device_reg_load(ID, + _REG_GP_ISEL_SOL_ADDR); + state->isel_eol = gp_device_reg_load(ID, + _REG_GP_ISEL_EOL_ADDR); + state->isel_lfsr_enable = gp_device_reg_load(ID, + _REG_GP_ISEL_LFSR_ENABLE_ADDR); + state->isel_lfsr_enable_b = gp_device_reg_load(ID, + _REG_GP_ISEL_LFSR_ENABLE_B_ADDR); + state->isel_lfsr_reset_value = gp_device_reg_load(ID, + _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR); + state->isel_tpg_enable = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_ENABLE_ADDR); + state->isel_tpg_enable_b = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_ENABLE_B_ADDR); + state->isel_hor_cnt_mask = gp_device_reg_load(ID, + _REG_GP_ISEL_HOR_CNT_MASK_ADDR); + state->isel_ver_cnt_mask = gp_device_reg_load(ID, + _REG_GP_ISEL_VER_CNT_MASK_ADDR); + state->isel_xy_cnt_mask = gp_device_reg_load(ID, + _REG_GP_ISEL_XY_CNT_MASK_ADDR); + state->isel_hor_cnt_delta = gp_device_reg_load(ID, + _REG_GP_ISEL_HOR_CNT_DELTA_ADDR); + state->isel_ver_cnt_delta = gp_device_reg_load(ID, + _REG_GP_ISEL_VER_CNT_DELTA_ADDR); + state->isel_tpg_mode = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_MODE_ADDR); + state->isel_tpg_red1 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_RED1_ADDR); + state->isel_tpg_green1 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_GREEN1_ADDR); + state->isel_tpg_blue1 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_BLUE1_ADDR); + state->isel_tpg_red2 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_RED2_ADDR); + state->isel_tpg_green2 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_GREEN2_ADDR); + state->isel_tpg_blue2 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_BLUE2_ADDR); + state->isel_ch_id = gp_device_reg_load(ID, + _REG_GP_ISEL_CH_ID_ADDR); + state->isel_fmt_type = gp_device_reg_load(ID, + _REG_GP_ISEL_FMT_TYPE_ADDR); + state->isel_data_sel = gp_device_reg_load(ID, + _REG_GP_ISEL_DATA_SEL_ADDR); + state->isel_sband_sel = gp_device_reg_load(ID, + _REG_GP_ISEL_SBAND_SEL_ADDR); + state->isel_sync_sel = gp_device_reg_load(ID, + _REG_GP_ISEL_SYNC_SEL_ADDR); + state->syncgen_hor_cnt = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_HOR_CNT_ADDR); + state->syncgen_ver_cnt = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_VER_CNT_ADDR); + state->syncgen_frame_cnt = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_FRAME_CNT_ADDR); + state->soft_reset = gp_device_reg_load(ID, + _REG_GP_SOFT_RESET_ADDR); + return; +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device_local.h new file mode 100644 index 000000000..320ed3526 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device_local.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_LOCAL_H_INCLUDED__ +#define __GP_DEVICE_LOCAL_H_INCLUDED__ + +#include "gp_device_global.h" + +/* @ GP_REGS_BASE -> GP_DEVICE_BASE */ +#define _REG_GP_SDRAM_WAKEUP_ADDR 0x00 +#define _REG_GP_IDLE_ADDR 0x04 +/* #define _REG_GP_IRQ_REQ0_ADDR 0x08 */ +/* #define _REG_GP_IRQ_REQ1_ADDR 0x0C */ +#define _REG_GP_SP_STREAM_STAT_ADDR 0x10 +#define _REG_GP_SP_STREAM_STAT_B_ADDR 0x14 +#define _REG_GP_ISP_STREAM_STAT_ADDR 0x18 +#define _REG_GP_MOD_STREAM_STAT_ADDR 0x1C +#define _REG_GP_SP_STREAM_STAT_IRQ_COND_ADDR 0x20 +#define _REG_GP_SP_STREAM_STAT_B_IRQ_COND_ADDR 0x24 +#define _REG_GP_ISP_STREAM_STAT_IRQ_COND_ADDR 0x28 +#define _REG_GP_MOD_STREAM_STAT_IRQ_COND_ADDR 0x2C +#define _REG_GP_SP_STREAM_STAT_IRQ_ENABLE_ADDR 0x30 +#define _REG_GP_SP_STREAM_STAT_B_IRQ_ENABLE_ADDR 0x34 +#define _REG_GP_ISP_STREAM_STAT_IRQ_ENABLE_ADDR 0x38 +#define _REG_GP_MOD_STREAM_STAT_IRQ_ENABLE_ADDR 0x3C +/* +#define _REG_GP_SWITCH_IF_ADDR 0x40 +#define _REG_GP_SWITCH_GDC1_ADDR 0x44 +#define _REG_GP_SWITCH_GDC2_ADDR 0x48 +*/ +#define _REG_GP_SLV_REG_RST_ADDR 0x50 +#define _REG_GP_SWITCH_ISYS2401_ADDR 0x54 + +/* @ INPUT_FORMATTER_BASE -> GP_DEVICE_BASE */ +/* +#define _REG_GP_IFMT_input_switch_lut_reg0 0x00030800 +#define _REG_GP_IFMT_input_switch_lut_reg1 0x00030804 +#define _REG_GP_IFMT_input_switch_lut_reg2 0x00030808 +#define _REG_GP_IFMT_input_switch_lut_reg3 0x0003080C +#define _REG_GP_IFMT_input_switch_lut_reg4 0x00030810 +#define _REG_GP_IFMT_input_switch_lut_reg5 0x00030814 +#define _REG_GP_IFMT_input_switch_lut_reg6 0x00030818 +#define _REG_GP_IFMT_input_switch_lut_reg7 0x0003081C +#define _REG_GP_IFMT_input_switch_fsync_lut 0x00030820 +#define _REG_GP_IFMT_srst 0x00030824 +#define _REG_GP_IFMT_slv_reg_srst 0x00030828 +#define _REG_GP_IFMT_input_switch_ch_id_fmt_type 0x0003082C +*/ +/* @ GP_DEVICE_BASE */ +/* +#define _REG_GP_SYNCGEN_ENABLE_ADDR 0x00090000 +#define _REG_GP_SYNCGEN_FREE_RUNNING_ADDR 0x00090004 +#define _REG_GP_SYNCGEN_PAUSE_ADDR 0x00090008 +#define _REG_GP_NR_FRAMES_ADDR 0x0009000C +#define _REG_GP_SYNGEN_NR_PIX_ADDR 0x00090010 +#define _REG_GP_SYNGEN_NR_LINES_ADDR 0x00090014 +#define _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR 0x00090018 +#define _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR 0x0009001C +#define _REG_GP_ISEL_SOF_ADDR 0x00090020 +#define _REG_GP_ISEL_EOF_ADDR 0x00090024 +#define _REG_GP_ISEL_SOL_ADDR 0x00090028 +#define _REG_GP_ISEL_EOL_ADDR 0x0009002C +#define _REG_GP_ISEL_LFSR_ENABLE_ADDR 0x00090030 +#define _REG_GP_ISEL_LFSR_ENABLE_B_ADDR 0x00090034 +#define _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR 0x00090038 +#define _REG_GP_ISEL_TPG_ENABLE_ADDR 0x0009003C +#define _REG_GP_ISEL_TPG_ENABLE_B_ADDR 0x00090040 +#define _REG_GP_ISEL_HOR_CNT_MASK_ADDR 0x00090044 +#define _REG_GP_ISEL_VER_CNT_MASK_ADDR 0x00090048 +#define _REG_GP_ISEL_XY_CNT_MASK_ADDR 0x0009004C +#define _REG_GP_ISEL_HOR_CNT_DELTA_ADDR 0x00090050 +#define _REG_GP_ISEL_VER_CNT_DELTA_ADDR 0x00090054 +#define _REG_GP_ISEL_TPG_MODE_ADDR 0x00090058 +#define _REG_GP_ISEL_TPG_RED1_ADDR 0x0009005C +#define _REG_GP_ISEL_TPG_GREEN1_ADDR 0x00090060 +#define _REG_GP_ISEL_TPG_BLUE1_ADDR 0x00090064 +#define _REG_GP_ISEL_TPG_RED2_ADDR 0x00090068 +#define _REG_GP_ISEL_TPG_GREEN2_ADDR 0x0009006C +#define _REG_GP_ISEL_TPG_BLUE2_ADDR 0x00090070 +#define _REG_GP_ISEL_CH_ID_ADDR 0x00090074 +#define _REG_GP_ISEL_FMT_TYPE_ADDR 0x00090078 +#define _REG_GP_ISEL_DATA_SEL_ADDR 0x0009007C +#define _REG_GP_ISEL_SBAND_SEL_ADDR 0x00090080 +#define _REG_GP_ISEL_SYNC_SEL_ADDR 0x00090084 +#define _REG_GP_SYNCGEN_HOR_CNT_ADDR 0x00090088 +#define _REG_GP_SYNCGEN_VER_CNT_ADDR 0x0009008C +#define _REG_GP_SYNCGEN_FRAME_CNT_ADDR 0x00090090 +#define _REG_GP_SOFT_RESET_ADDR 0x00090094 +*/ + +struct gp_device_state_s { + int syncgen_enable; + int syncgen_free_running; + int syncgen_pause; + int nr_frames; + int syngen_nr_pix; + int syngen_nr_lines; + int syngen_hblank_cycles; + int syngen_vblank_cycles; + int isel_sof; + int isel_eof; + int isel_sol; + int isel_eol; + int isel_lfsr_enable; + int isel_lfsr_enable_b; + int isel_lfsr_reset_value; + int isel_tpg_enable; + int isel_tpg_enable_b; + int isel_hor_cnt_mask; + int isel_ver_cnt_mask; + int isel_xy_cnt_mask; + int isel_hor_cnt_delta; + int isel_ver_cnt_delta; + int isel_tpg_mode; + int isel_tpg_red1; + int isel_tpg_green1; + int isel_tpg_blue1; + int isel_tpg_red2; + int isel_tpg_green2; + int isel_tpg_blue2; + int isel_ch_id; + int isel_fmt_type; + int isel_data_sel; + int isel_sband_sel; + int isel_sync_sel; + int syncgen_hor_cnt; + int syncgen_ver_cnt; + int syncgen_frame_cnt; + int soft_reset; +}; + +#endif /* __GP_DEVICE_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device_private.h new file mode 100644 index 000000000..f11a19f21 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_device_private.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_PRIVATE_H_INCLUDED__ +#define __GP_DEVICE_PRIVATE_H_INCLUDED__ + +#include "gp_device_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_GP_DEVICE_C void gp_device_reg_store( + const gp_device_ID_t ID, + const unsigned int reg_addr, + const hrt_data value) +{ + assert(ID < N_GP_DEVICE_ID); + assert(GP_DEVICE_BASE[ID] != (hrt_address) - 1); + assert((reg_addr % sizeof(hrt_data)) == 0); + ia_css_device_store_uint32(GP_DEVICE_BASE[ID] + reg_addr, value); + return; +} + +STORAGE_CLASS_GP_DEVICE_C hrt_data gp_device_reg_load( + const gp_device_ID_t ID, + const hrt_address reg_addr) +{ + assert(ID < N_GP_DEVICE_ID); + assert(GP_DEVICE_BASE[ID] != (hrt_address)-1); + assert((reg_addr % sizeof(hrt_data)) == 0); + return ia_css_device_load_uint32(GP_DEVICE_BASE[ID] + reg_addr); +} + +#endif /* __GP_DEVICE_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer.c new file mode 100644 index 000000000..2a58dba3c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /*uint32_t */ +#include "gp_timer.h" /*system_local.h, + gp_timer_public.h*/ + +#ifndef __INLINE_GP_TIMER__ +#include "gp_timer_private.h" /*device_access.h*/ +#endif /* __INLINE_GP_TIMER__ */ +#include "system_local.h" + +/* FIXME: not sure if reg_load(), reg_store() should be API. + */ +static uint32_t +gp_timer_reg_load(uint32_t reg); + +static void +gp_timer_reg_store(u32 reg, uint32_t value); + +static uint32_t +gp_timer_reg_load(uint32_t reg) +{ + return ia_css_device_load_uint32( + GP_TIMER_BASE + + (reg * sizeof(uint32_t))); +} + +static void +gp_timer_reg_store(u32 reg, uint32_t value) +{ + ia_css_device_store_uint32((GP_TIMER_BASE + + (reg * sizeof(uint32_t))), + value); +} + +void gp_timer_init(gp_timer_ID_t ID) +{ + /* set_overall_enable*/ + gp_timer_reg_store(_REG_GP_TIMER_OVERALL_ENABLE, 1); + + /*set enable*/ + gp_timer_reg_store(_REG_GP_TIMER_ENABLE_ID(ID), 1); + + /* set signal select */ + gp_timer_reg_store(_REG_GP_TIMER_SIGNAL_SELECT_ID(ID), GP_TIMER_SIGNAL_SELECT); + + /*set count type */ + gp_timer_reg_store(_REG_GP_TIMER_COUNT_TYPE_ID(ID), GP_TIMER_COUNT_TYPE_LOW); + + /*reset gp timer */ + gp_timer_reg_store(_REG_GP_TIMER_RESET_REG, 0xFF); +} + +uint32_t +gp_timer_read(gp_timer_ID_t ID) +{ + return gp_timer_reg_load(_REG_GP_TIMER_VALUE_ID(ID)); +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer_local.h new file mode 100644 index 000000000..efede2558 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer_local.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_LOCAL_H_INCLUDED__ +#define __GP_TIMER_LOCAL_H_INCLUDED__ + +#include "gp_timer_global.h" /*GP_TIMER_SEL + GP_TIMER_SIGNAL_SELECT*/ + +#include "gp_timer_defs.h" /*HIVE_GP_TIMER_xxx registers*/ +#include "hive_isp_css_defs.h" /*HIVE_GP_TIMER_NUM_COUNTERS + HIVE_GP_TIMER_NUM_IRQS*/ + +#define _REG_GP_TIMER_RESET_REG HIVE_GP_TIMER_RESET_REG_IDX +#define _REG_GP_TIMER_OVERALL_ENABLE HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + +/*Register offsets for timers [1,7] can be obtained + * by adding (GP_TIMERx_ID * sizeof(uint32_t))*/ +#define _REG_GP_TIMER_ENABLE_ID(timer_id) HIVE_GP_TIMER_ENABLE_REG_IDX(timer_id) +#define _REG_GP_TIMER_VALUE_ID(timer_id) HIVE_GP_TIMER_VALUE_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS) +#define _REG_GP_TIMER_COUNT_TYPE_ID(timer_id) HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS) +#define _REG_GP_TIMER_SIGNAL_SELECT_ID(timer_id) HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS) + +#define _REG_GP_TIMER_IRQ_TRIGGER_VALUE_ID(irq_id) HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq_id, HIVE_GP_TIMER_NUM_COUNTERS) + +#define _REG_GP_TIMER_IRQ_TIMER_SELECT_ID(irq_id) \ + HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq_id, HIVE_GP_TIMER_NUM_COUNTERS, HIVE_GP_TIMER_NUM_IRQS) + +#define _REG_GP_TIMER_IRQ_ENABLE_ID(irq_id) \ + HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq_id, HIVE_GP_TIMER_NUM_COUNTERS, HIVE_GP_TIMER_NUM_IRQS) + +#endif /*__GP_TIMER_LOCAL_H_INCLUDED__*/ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer_private.h new file mode 100644 index 000000000..3e1b36105 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gp_timer_private.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_PRIVATE_H_INCLUDED__ +#define __GP_TIMER_PRIVATE_H_INCLUDED__ + +#include "gp_timer_public.h" +#include "device_access.h" +#include "assert_support.h" + +#endif /* __GP_TIMER_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_local.h new file mode 100644 index 000000000..14013733f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_local.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_LOCAL_H_INCLUDED__ +#define __GPIO_LOCAL_H_INCLUDED__ + +#include "gpio_global.h" + +#endif /* __GPIO_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_private.h new file mode 100644 index 000000000..cc60bed71 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_private.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_PRIVATE_H_INCLUDED__ +#define __GPIO_PRIVATE_H_INCLUDED__ + +#include "gpio_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_GPIO_C void gpio_reg_store( + const gpio_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + OP___assert(ID < N_GPIO_ID); + OP___assert(GPIO_BASE[ID] != (hrt_address) - 1); + ia_css_device_store_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data), value); + return; +} + +STORAGE_CLASS_GPIO_C hrt_data gpio_reg_load( + const gpio_ID_t ID, + const unsigned int reg) +{ + OP___assert(ID < N_GPIO_ID); + OP___assert(GPIO_BASE[ID] != (hrt_address) - 1); + return ia_css_device_load_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data)); +} + +#endif /* __GPIO_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem.c new file mode 100644 index 000000000..be102d5ce --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmem.h" + +#ifndef __INLINE_HMEM__ +#include "hmem_private.h" +#endif /* __INLINE_HMEM__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem_local.h new file mode 100644 index 000000000..a3ee274bd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem_local.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_LOCAL_H_INCLUDED__ +#define __HMEM_LOCAL_H_INCLUDED__ + +#include "hmem_global.h" + +#endif /* __HMEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem_private.h new file mode 100644 index 000000000..80d81983b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/hmem_private.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_PRIVATE_H_INCLUDED__ +#define __HMEM_PRIVATE_H_INCLUDED__ + +#include "hmem_public.h" + +#include "assert_support.h" + +STORAGE_CLASS_HMEM_C size_t sizeof_hmem( + const hmem_ID_t ID) +{ + assert(ID < N_HMEM_ID); + (void)ID; + return HMEM_SIZE * sizeof(hmem_data_t); +} + +#endif /* __HMEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter.c new file mode 100644 index 000000000..5cd6136f2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" + +#ifndef ISP2401 + +#include "input_formatter.h" +#include +#include "gp_device.h" + +#include "assert_support.h" + +#ifndef __INLINE_INPUT_FORMATTER__ +#include "input_formatter_private.h" +#endif /* __INLINE_INPUT_FORMATTER__ */ + +static const unsigned int input_formatter_alignment[N_INPUT_FORMATTER_ID] = { + ISP_VEC_ALIGN, ISP_VEC_ALIGN, HIVE_ISP_CTRL_DATA_BYTES +}; + +const hrt_address HIVE_IF_SRST_ADDRESS[N_INPUT_FORMATTER_ID] = { + INPUT_FORMATTER0_SRST_OFFSET, + INPUT_FORMATTER1_SRST_OFFSET, + INPUT_FORMATTER2_SRST_OFFSET, + INPUT_FORMATTER3_SRST_OFFSET +}; + +const hrt_data HIVE_IF_SRST_MASK[N_INPUT_FORMATTER_ID] = { + INPUT_FORMATTER0_SRST_MASK, + INPUT_FORMATTER1_SRST_MASK, + INPUT_FORMATTER2_SRST_MASK, + INPUT_FORMATTER3_SRST_MASK +}; + +const u8 HIVE_IF_SWITCH_CODE[N_INPUT_FORMATTER_ID] = { + HIVE_INPUT_SWITCH_SELECT_IF_PRIM, + HIVE_INPUT_SWITCH_SELECT_IF_PRIM, + HIVE_INPUT_SWITCH_SELECT_IF_SEC, + HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM +}; + +/* MW Should be part of system_global.h, where we have the main enumeration */ +static const bool HIVE_IF_BIN_COPY[N_INPUT_FORMATTER_ID] = { + false, false, false, true +}; + +void input_formatter_rst( + const input_formatter_ID_t ID) +{ + hrt_address addr; + hrt_data rst; + + assert(ID < N_INPUT_FORMATTER_ID); + + addr = HIVE_IF_SRST_ADDRESS[ID]; + rst = HIVE_IF_SRST_MASK[ID]; + + /* TEMPORARY HACK: THIS RESET BREAKS THE METADATA FEATURE + * WICH USES THE STREAM2MEMRY BLOCK. + * MUST BE FIXED PROPERLY + */ + if (!HIVE_IF_BIN_COPY[ID]) { + input_formatter_reg_store(ID, addr, rst); + } + + return; +} + +unsigned int input_formatter_get_alignment( + const input_formatter_ID_t ID) +{ + assert(ID < N_INPUT_FORMATTER_ID); + + return input_formatter_alignment[ID]; +} + +void input_formatter_set_fifo_blocking_mode( + const input_formatter_ID_t ID, + const bool enable) +{ + assert(ID < N_INPUT_FORMATTER_ID); + + /* cnd_input_formatter_reg_store() */ + if (!HIVE_IF_BIN_COPY[ID]) { + input_formatter_reg_store(ID, + HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS, enable); + } + return; +} + +void input_formatter_get_switch_state( + const input_formatter_ID_t ID, + input_formatter_switch_state_t *state) +{ + assert(ID < N_INPUT_FORMATTER_ID); + assert(state); + + /* We'll change this into an intelligent function to get switch info per IF */ + (void)ID; + + state->if_input_switch_lut_reg[0] = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg0); + state->if_input_switch_lut_reg[1] = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg1); + state->if_input_switch_lut_reg[2] = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg2); + state->if_input_switch_lut_reg[3] = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg3); + state->if_input_switch_lut_reg[4] = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg4); + state->if_input_switch_lut_reg[5] = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg5); + state->if_input_switch_lut_reg[6] = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg6); + state->if_input_switch_lut_reg[7] = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg7); + state->if_input_switch_fsync_lut = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_fsync_lut); + state->if_input_switch_ch_id_fmt_type = gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_ch_id_fmt_type); + + return; +} + +void input_formatter_get_state( + const input_formatter_ID_t ID, + input_formatter_state_t *state) +{ + assert(ID < N_INPUT_FORMATTER_ID); + assert(state); + /* + state->reset = input_formatter_reg_load(ID, + HIVE_IF_RESET_ADDRESS); + */ + state->start_line = input_formatter_reg_load(ID, + HIVE_IF_START_LINE_ADDRESS); + state->start_column = input_formatter_reg_load(ID, + HIVE_IF_START_COLUMN_ADDRESS); + state->cropped_height = input_formatter_reg_load(ID, + HIVE_IF_CROPPED_HEIGHT_ADDRESS); + state->cropped_width = input_formatter_reg_load(ID, + HIVE_IF_CROPPED_WIDTH_ADDRESS); + state->ver_decimation = input_formatter_reg_load(ID, + HIVE_IF_VERTICAL_DECIMATION_ADDRESS); + state->hor_decimation = input_formatter_reg_load(ID, + HIVE_IF_HORIZONTAL_DECIMATION_ADDRESS); + state->hor_deinterleaving = input_formatter_reg_load(ID, + HIVE_IF_H_DEINTERLEAVING_ADDRESS); + state->left_padding = input_formatter_reg_load(ID, + HIVE_IF_LEFTPADDING_WIDTH_ADDRESS); + state->eol_offset = input_formatter_reg_load(ID, + HIVE_IF_END_OF_LINE_OFFSET_ADDRESS); + state->vmem_start_address = input_formatter_reg_load(ID, + HIVE_IF_VMEM_START_ADDRESS_ADDRESS); + state->vmem_end_address = input_formatter_reg_load(ID, + HIVE_IF_VMEM_END_ADDRESS_ADDRESS); + state->vmem_increment = input_formatter_reg_load(ID, + HIVE_IF_VMEM_INCREMENT_ADDRESS); + state->is_yuv420 = input_formatter_reg_load(ID, + HIVE_IF_YUV_420_FORMAT_ADDRESS); + state->vsync_active_low = input_formatter_reg_load(ID, + HIVE_IF_VSYNCK_ACTIVE_LOW_ADDRESS); + state->hsync_active_low = input_formatter_reg_load(ID, + HIVE_IF_HSYNCK_ACTIVE_LOW_ADDRESS); + state->allow_fifo_overflow = input_formatter_reg_load(ID, + HIVE_IF_ALLOW_FIFO_OVERFLOW_ADDRESS); + state->block_fifo_when_no_req = input_formatter_reg_load(ID, + HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS); + state->ver_deinterleaving = input_formatter_reg_load(ID, + HIVE_IF_V_DEINTERLEAVING_ADDRESS); + /* FSM */ + state->fsm_sync_status = input_formatter_reg_load(ID, + HIVE_IF_FSM_SYNC_STATUS); + state->fsm_sync_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_SYNC_COUNTER); + state->fsm_crop_status = input_formatter_reg_load(ID, + HIVE_IF_FSM_CROP_STATUS); + state->fsm_crop_line_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_CROP_LINE_COUNTER); + state->fsm_crop_pixel_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_CROP_PIXEL_COUNTER); + state->fsm_deinterleaving_index = input_formatter_reg_load(ID, + HIVE_IF_FSM_DEINTERLEAVING_IDX); + state->fsm_dec_h_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_DECIMATION_H_COUNTER); + state->fsm_dec_v_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_DECIMATION_V_COUNTER); + state->fsm_dec_block_v_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_DECIMATION_BLOCK_V_COUNTER); + state->fsm_padding_status = input_formatter_reg_load(ID, + HIVE_IF_FSM_PADDING_STATUS); + state->fsm_padding_elem_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_PADDING_ELEMENT_COUNTER); + state->fsm_vector_support_error = input_formatter_reg_load(ID, + HIVE_IF_FSM_VECTOR_SUPPORT_ERROR); + state->fsm_vector_buffer_full = input_formatter_reg_load(ID, + HIVE_IF_FSM_VECTOR_SUPPORT_BUFF_FULL); + state->vector_support = input_formatter_reg_load(ID, + HIVE_IF_FSM_VECTOR_SUPPORT); + state->sensor_data_lost = input_formatter_reg_load(ID, + HIVE_IF_FIFO_SENSOR_STATUS); + + return; +} + +void input_formatter_bin_get_state( + const input_formatter_ID_t ID, + input_formatter_bin_state_t *state) +{ + assert(ID < N_INPUT_FORMATTER_ID); + assert(state); + + state->reset = input_formatter_reg_load(ID, + HIVE_STR2MEM_SOFT_RESET_REG_ADDRESS); + state->input_endianness = input_formatter_reg_load(ID, + HIVE_STR2MEM_INPUT_ENDIANNESS_REG_ADDRESS); + state->output_endianness = input_formatter_reg_load(ID, + HIVE_STR2MEM_OUTPUT_ENDIANNESS_REG_ADDRESS); + state->bitswap = input_formatter_reg_load(ID, + HIVE_STR2MEM_BIT_SWAPPING_REG_ADDRESS); + state->block_synch = input_formatter_reg_load(ID, + HIVE_STR2MEM_BLOCK_SYNC_LEVEL_REG_ADDRESS); + state->packet_synch = input_formatter_reg_load(ID, + HIVE_STR2MEM_PACKET_SYNC_LEVEL_REG_ADDRESS); + state->readpostwrite_synch = input_formatter_reg_load(ID, + HIVE_STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ADDRESS); + state->is_2ppc = input_formatter_reg_load(ID, + HIVE_STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ADDRESS); + state->en_status_update = input_formatter_reg_load(ID, + HIVE_STR2MEM_EN_STAT_UPDATE_ADDRESS); + return; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter_local.h new file mode 100644 index 000000000..dfb593c10 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter_local.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_FORMATTER_LOCAL_H_INCLUDED__ +#define __INPUT_FORMATTER_LOCAL_H_INCLUDED__ + +#include "input_formatter_global.h" + +#include "isp.h" /* ISP_VEC_ALIGN */ + +typedef struct input_formatter_switch_state_s input_formatter_switch_state_t; +typedef struct input_formatter_state_s input_formatter_state_t; +typedef struct input_formatter_bin_state_s input_formatter_bin_state_t; + +#define HIVE_IF_FSM_SYNC_STATUS 0x100 +#define HIVE_IF_FSM_SYNC_COUNTER 0x104 +#define HIVE_IF_FSM_DEINTERLEAVING_IDX 0x114 +#define HIVE_IF_FSM_DECIMATION_H_COUNTER 0x118 +#define HIVE_IF_FSM_DECIMATION_V_COUNTER 0x11C +#define HIVE_IF_FSM_DECIMATION_BLOCK_V_COUNTER 0x120 +#define HIVE_IF_FSM_PADDING_STATUS 0x124 +#define HIVE_IF_FSM_PADDING_ELEMENT_COUNTER 0x128 +#define HIVE_IF_FSM_VECTOR_SUPPORT_ERROR 0x12C +#define HIVE_IF_FSM_VECTOR_SUPPORT_BUFF_FULL 0x130 +#define HIVE_IF_FSM_VECTOR_SUPPORT 0x134 +#define HIVE_IF_FIFO_SENSOR_STATUS 0x138 + +/* + * The switch LUT's coding defines a sink for each + * single channel ID + channel format type. Conversely + * the sink (i.e. an input formatter) can be reached + * from multiple channel & format type combinations + * + * LUT[0,1] channel=0, format type {0,1,...31} + * LUT[2,3] channel=1, format type {0,1,...31} + * LUT[4,5] channel=2, format type {0,1,...31} + * LUT[6,7] channel=3, format type {0,1,...31} + * + * Each register hold 16 2-bit fields encoding the sink + * {0,1,2,3}, "0" means unconnected. + * + * The single FSYNCH register uses four 3-bit fields of 1-hot + * encoded sink information, "0" means unconnected. + * + * The encoding is redundant. The FSYNCH setting will connect + * a channel to a sink. At that point the LUT's belonging to + * that channel can be directed to another sink. Thus the data + * goes to another place than the synch + */ +struct input_formatter_switch_state_s { + int if_input_switch_lut_reg[8]; + int if_input_switch_fsync_lut; + int if_input_switch_ch_id_fmt_type; + bool if_input_switch_map[HIVE_SWITCH_N_CHANNELS][HIVE_SWITCH_N_FORMATTYPES]; +}; + +struct input_formatter_state_s { + /* int reset; */ + int start_line; + int start_column; + int cropped_height; + int cropped_width; + int ver_decimation; + int hor_decimation; + int ver_deinterleaving; + int hor_deinterleaving; + int left_padding; + int eol_offset; + int vmem_start_address; + int vmem_end_address; + int vmem_increment; + int is_yuv420; + int vsync_active_low; + int hsync_active_low; + int allow_fifo_overflow; + int block_fifo_when_no_req; + int fsm_sync_status; + int fsm_sync_counter; + int fsm_crop_status; + int fsm_crop_line_counter; + int fsm_crop_pixel_counter; + int fsm_deinterleaving_index; + int fsm_dec_h_counter; + int fsm_dec_v_counter; + int fsm_dec_block_v_counter; + int fsm_padding_status; + int fsm_padding_elem_counter; + int fsm_vector_support_error; + int fsm_vector_buffer_full; + int vector_support; + int sensor_data_lost; +}; + +struct input_formatter_bin_state_s { + u32 reset; + u32 input_endianness; + u32 output_endianness; + u32 bitswap; + u32 block_synch; + u32 packet_synch; + u32 readpostwrite_synch; + u32 is_2ppc; + u32 en_status_update; +}; + +#endif /* __INPUT_FORMATTER_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter_private.h new file mode 100644 index 000000000..e2bc952e6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter_private.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_FORMATTER_PRIVATE_H_INCLUDED__ +#define __INPUT_FORMATTER_PRIVATE_H_INCLUDED__ + +#include "input_formatter_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_INPUT_FORMATTER_C void input_formatter_reg_store( + const input_formatter_ID_t ID, + const hrt_address reg_addr, + const hrt_data value) +{ + assert(ID < N_INPUT_FORMATTER_ID); + assert(INPUT_FORMATTER_BASE[ID] != (hrt_address)-1); + assert((reg_addr % sizeof(hrt_data)) == 0); + ia_css_device_store_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr, value); + return; +} + +STORAGE_CLASS_INPUT_FORMATTER_C hrt_data input_formatter_reg_load( + const input_formatter_ID_t ID, + const unsigned int reg_addr) +{ + assert(ID < N_INPUT_FORMATTER_ID); + assert(INPUT_FORMATTER_BASE[ID] != (hrt_address)-1); + assert((reg_addr % sizeof(hrt_data)) == 0); + return ia_css_device_load_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr); +} + +#endif /* __INPUT_FORMATTER_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_system.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_system.c new file mode 100644 index 000000000..712e01c37 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_system.c @@ -0,0 +1,1790 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" + +#ifndef ISP2401 + +#include "input_system.h" +#include +#include "gp_device.h" + +#include "assert_support.h" + +#ifndef __INLINE_INPUT_SYSTEM__ +#include "input_system_private.h" +#endif /* __INLINE_INPUT_SYSTEM__ */ + +#define ZERO (0x0) +#define ONE (1U) + +static const isp2400_ib_buffer_t IB_BUFFER_NULL = {0, 0, 0 }; + +static input_system_err_t input_system_configure_channel( + const channel_cfg_t channel); + +static input_system_err_t input_system_configure_channel_sensor( + const channel_cfg_t channel); + +static input_system_err_t input_buffer_configuration(void); + +static input_system_err_t configuration_to_registers(void); + +static void receiver_rst(const rx_ID_t ID); +static void input_system_network_rst(const input_system_ID_t ID); + +static void capture_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const isp2400_ib_buffer_t *const cfg); + +static void acquisition_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const isp2400_ib_buffer_t *const cfg); + +static void ctrl_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const ctrl_unit_cfg_t *const cfg); + +static void input_system_network_configure( + const input_system_ID_t ID, + const input_system_network_cfg_t *const cfg); + +// MW: CSI is previously named as "rx" short for "receiver" +static input_system_err_t set_csi_cfg( + csi_cfg_t *const lhs, + const csi_cfg_t *const rhs, + input_system_config_flags_t *const flags); + +static input_system_err_t set_source_type( + input_system_source_t *const lhs, + const input_system_source_t rhs, + input_system_config_flags_t *const flags); + +static input_system_err_t input_system_multiplexer_cfg( + input_system_multiplex_t *const lhs, + const input_system_multiplex_t rhs, + input_system_config_flags_t *const flags); + +static inline void capture_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + capture_unit_state_t *state); + +static inline void acquisition_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + acquisition_unit_state_t *state); + +static inline void ctrl_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + ctrl_unit_state_t *state); + +static inline void mipi_port_get_state( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + mipi_port_state_t *state); + +static inline void rx_channel_get_state( + const rx_ID_t ID, + const unsigned int ch_id, + rx_channel_state_t *state); + +static void gp_device_rst(const gp_device_ID_t ID); + +static void input_selector_cfg_for_sensor(const gp_device_ID_t ID); + +static void input_switch_rst(const gp_device_ID_t ID); + +static void input_switch_cfg( + const gp_device_ID_t ID, + const input_switch_cfg_t *const cfg +); + +void input_system_get_state( + const input_system_ID_t ID, + input_system_state_t *state) +{ + sub_system_ID_t sub_id; + + assert(ID < N_INPUT_SYSTEM_ID); + assert(state); + + state->str_multicastA_sel = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX); + state->str_multicastB_sel = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_B_IDX); + state->str_multicastC_sel = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_C_IDX); + state->str_mux_sel = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX); + state->str_mon_status = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_STRMON_STAT_IDX); + state->str_mon_irq_cond = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_STRMON_COND_IDX); + state->str_mon_irq_en = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX); + state->isys_srst = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_SRST_IDX); + state->isys_slv_reg_srst = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_SLV_REG_SRST_IDX); + state->str_deint_portA_cnt = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_REG_PORT_A_IDX); + state->str_deint_portB_cnt = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_REG_PORT_B_IDX); + + for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; + sub_id++) { + capture_unit_get_state(ID, sub_id, + &state->capture_unit[sub_id - CAPTURE_UNIT0_ID]); + } + for (sub_id = ACQUISITION_UNIT0_ID; + sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) { + acquisition_unit_get_state(ID, sub_id, + &state->acquisition_unit[sub_id - ACQUISITION_UNIT0_ID]); + } + for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; + sub_id++) { + ctrl_unit_get_state(ID, sub_id, + &state->ctrl_unit_state[sub_id - CTRL_UNIT0_ID]); + } +} + +void receiver_get_state( + const rx_ID_t ID, + receiver_state_t *state) +{ + enum mipi_port_id port_id; + unsigned int ch_id; + + assert(ID < N_RX_ID); + assert(state); + + state->fs_to_ls_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX); + state->ls_to_data_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX); + state->data_to_le_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX); + state->le_to_fe_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX); + state->fe_to_fs_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX); + state->le_to_fs_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX); + state->is_two_ppc = (bool)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX); + state->backend_rst = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX); + state->raw18 = (uint16_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_RAW18_REG_IDX); + state->force_raw8 = (bool)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX); + state->raw16 = (uint16_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_RAW16_REG_IDX); + + for (port_id = (enum mipi_port_id)0; port_id < N_MIPI_PORT_ID; port_id++) { + mipi_port_get_state(ID, port_id, + &state->mipi_port_state[port_id]); + } + for (ch_id = 0U; ch_id < N_RX_CHANNEL_ID; ch_id++) { + rx_channel_get_state(ID, ch_id, + &state->rx_channel_state[ch_id]); + } + + state->be_gsp_acc_ovl = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX); + state->be_srst = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_SRST_REG_IDX); + state->be_is_two_ppc = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX); + state->be_comp_format0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX); + state->be_comp_format1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX); + state->be_comp_format2 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX); + state->be_comp_format3 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX); + state->be_sel = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_SEL_REG_IDX); + state->be_raw16_config = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX); + state->be_raw18_config = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX); + state->be_force_raw8 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX); + state->be_irq_status = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX); + state->be_irq_clear = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX); +} + +bool is_mipi_format_yuv420( + const mipi_format_t mipi_format) +{ + bool is_yuv420 = ( + (mipi_format == MIPI_FORMAT_YUV420_8) || + (mipi_format == MIPI_FORMAT_YUV420_10) || + (mipi_format == MIPI_FORMAT_YUV420_8_SHIFT) || + (mipi_format == MIPI_FORMAT_YUV420_10_SHIFT)); + /* MIPI_FORMAT_YUV420_8_LEGACY is not YUV420 */ + + return is_yuv420; +} + +void receiver_set_compression( + const rx_ID_t ID, + const unsigned int cfg_ID, + const mipi_compressor_t comp, + const mipi_predictor_t pred) +{ + const unsigned int field_id = cfg_ID % N_MIPI_FORMAT_CUSTOM; + const unsigned int ch_id = cfg_ID / N_MIPI_FORMAT_CUSTOM; + hrt_data val; + hrt_address addr = 0; + hrt_data reg; + + assert(ID < N_RX_ID); + assert(cfg_ID < N_MIPI_COMPRESSOR_CONTEXT); + assert(field_id < N_MIPI_FORMAT_CUSTOM); + assert(ch_id < N_RX_CHANNEL_ID); + assert(comp < N_MIPI_COMPRESSOR_METHODS); + assert(pred < N_MIPI_PREDICTOR_TYPES); + + val = (((uint8_t)pred) << 3) | comp; + + switch (ch_id) { + case 0: + addr = ((field_id < 6) ? _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX : + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX); + break; + case 1: + addr = ((field_id < 6) ? _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX : + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX); + break; + case 2: + addr = ((field_id < 6) ? _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX : + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX); + break; + case 3: + addr = ((field_id < 6) ? _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX : + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX); + break; + default: + /* should not happen */ + assert(false); + return; + } + + reg = ((field_id < 6) ? (val << (field_id * 5)) : (val << (( + field_id - 6) * 5))); + receiver_reg_store(ID, addr, reg); +} + +void receiver_port_enable( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const bool cnd) +{ + hrt_data reg = receiver_port_reg_load(ID, port_ID, + _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX); + + if (cnd) { + reg |= 0x01; + } else { + reg &= ~0x01; + } + + receiver_port_reg_store(ID, port_ID, + _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, reg); +} + +bool is_receiver_port_enabled( + const rx_ID_t ID, + const enum mipi_port_id port_ID) +{ + hrt_data reg = receiver_port_reg_load(ID, port_ID, + _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX); + return ((reg & 0x01) != 0); +} + +void receiver_irq_enable( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const rx_irq_info_t irq_info) +{ + receiver_port_reg_store(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, irq_info); +} + +rx_irq_info_t receiver_get_irq_info( + const rx_ID_t ID, + const enum mipi_port_id port_ID) +{ + return receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX); +} + +void receiver_irq_clear( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const rx_irq_info_t irq_info) +{ + receiver_port_reg_store(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX, irq_info); +} + +static inline void capture_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + capture_unit_state_t *state) +{ + assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID)); + assert(state); + + state->StartMode = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_START_MODE_REG_ID); + state->Start_Addr = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_START_ADDR_REG_ID); + state->Mem_Region_Size = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_MEM_REGION_SIZE_REG_ID); + state->Num_Mem_Regions = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_NUM_MEM_REGIONS_REG_ID); +// AM: Illegal read from following registers. + /* state->Init = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_INIT_REG_ID); + state->Start = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_START_REG_ID); + state->Stop = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_STOP_REG_ID); + */ + state->Packet_Length = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_PACKET_LENGTH_REG_ID); + state->Received_Length = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_RECEIVED_LENGTH_REG_ID); + state->Received_Short_Packets = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_RECEIVED_SHORT_PACKETS_REG_ID); + state->Received_Long_Packets = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_RECEIVED_LONG_PACKETS_REG_ID); + state->Last_Command = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_LAST_COMMAND_REG_ID); + state->Next_Command = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_NEXT_COMMAND_REG_ID); + state->Last_Acknowledge = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_LAST_ACKNOWLEDGE_REG_ID); + state->Next_Acknowledge = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_NEXT_ACKNOWLEDGE_REG_ID); + state->FSM_State_Info = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_FSM_STATE_INFO_REG_ID); +} + +static inline void acquisition_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + acquisition_unit_state_t *state) +{ + assert(sub_id == ACQUISITION_UNIT0_ID); + assert(state); + + state->Start_Addr = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_START_ADDR_REG_ID); + state->Mem_Region_Size = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_MEM_REGION_SIZE_REG_ID); + state->Num_Mem_Regions = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_NUM_MEM_REGIONS_REG_ID); +// AM: Illegal read from following registers. + /* state->Init = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_INIT_REG_ID); + */ + state->Received_Short_Packets = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_RECEIVED_SHORT_PACKETS_REG_ID); + state->Received_Long_Packets = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_RECEIVED_LONG_PACKETS_REG_ID); + state->Last_Command = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_LAST_COMMAND_REG_ID); + state->Next_Command = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_NEXT_COMMAND_REG_ID); + state->Last_Acknowledge = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_LAST_ACKNOWLEDGE_REG_ID); + state->Next_Acknowledge = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_NEXT_ACKNOWLEDGE_REG_ID); + state->FSM_State_Info = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_FSM_STATE_INFO_REG_ID); + state->Int_Cntr_Info = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_INT_CNTR_INFO_REG_ID); +} + +static inline void ctrl_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + ctrl_unit_state_t *state) +{ + assert(sub_id == CTRL_UNIT0_ID); + assert(state); + + state->captA_start_addr = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_A_REG_ID); + state->captB_start_addr = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_B_REG_ID); + state->captC_start_addr = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_C_REG_ID); + state->captA_mem_region_size = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID); + state->captB_mem_region_size = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID); + state->captC_mem_region_size = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID); + state->captA_num_mem_regions = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID); + state->captB_num_mem_regions = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID); + state->captC_num_mem_regions = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID); + state->acq_start_addr = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_ACQ_START_ADDR_REG_ID); + state->acq_mem_region_size = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID); + state->acq_num_mem_regions = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID); +// AM: Illegal read from following registers. + /* state->ctrl_init = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_INIT_REG_ID); + */ + state->last_cmd = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_LAST_COMMAND_REG_ID); + state->next_cmd = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_NEXT_COMMAND_REG_ID); + state->last_ack = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID); + state->next_ack = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID); + state->top_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_FSM_STATE_INFO_REG_ID); + state->captA_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID); + state->captB_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID); + state->captC_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID); + state->acq_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID); + state->capt_reserve_one_mem_region = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID); +} + +static inline void mipi_port_get_state( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + mipi_port_state_t *state) +{ + int i; + + assert(ID < N_RX_ID); + assert(port_ID < N_MIPI_PORT_ID); + assert(state); + + state->device_ready = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX); + state->irq_status = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX); + state->irq_enable = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX); + state->timeout_count = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX); + state->init_count = (uint16_t)receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX); + state->raw16_18 = (uint16_t)receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX); + state->sync_count = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX); + state->rx_count = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX); + + for (i = 0; i < MIPI_4LANE_CFG ; i++) { + state->lane_sync_count[i] = (uint8_t)((state->sync_count) >> (i * 8)); + state->lane_rx_count[i] = (uint8_t)((state->rx_count) >> (i * 8)); + } +} + +static inline void rx_channel_get_state( + const rx_ID_t ID, + const unsigned int ch_id, + rx_channel_state_t *state) +{ + int i; + + assert(ID < N_RX_ID); + assert(ch_id < N_RX_CHANNEL_ID); + assert(state); + + switch (ch_id) { + case 0: + state->comp_scheme0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX); + state->comp_scheme1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX); + break; + case 1: + state->comp_scheme0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX); + state->comp_scheme1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX); + break; + case 2: + state->comp_scheme0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX); + state->comp_scheme1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX); + break; + case 3: + state->comp_scheme0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX); + state->comp_scheme1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX); + break; + } + + /* See Table 7.1.17,..., 7.1.24 */ + for (i = 0; i < 6; i++) { + u8 val = (uint8_t)((state->comp_scheme0) >> (i * 5)) & 0x1f; + + state->comp[i] = (mipi_compressor_t)(val & 0x07); + state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3); + } + for (i = 6; i < N_MIPI_FORMAT_CUSTOM; i++) { + u8 val = (uint8_t)((state->comp_scheme0) >> ((i - 6) * 5)) & 0x1f; + + state->comp[i] = (mipi_compressor_t)(val & 0x07); + state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3); + } +} + +// MW: "2400" in the name is not good, but this is to avoid a naming conflict +static input_system_cfg2400_t config; + +static void receiver_rst( + const rx_ID_t ID) +{ + enum mipi_port_id port_id; + + assert(ID < N_RX_ID); + +// Disable all ports. + for (port_id = MIPI_PORT0_ID; port_id < N_MIPI_PORT_ID; port_id++) { + receiver_port_enable(ID, port_id, false); + } + + // AM: Additional actions for stopping receiver? +} + +//Single function to reset all the devices mapped via GP_DEVICE. +static void gp_device_rst(const gp_device_ID_t ID) +{ + assert(ID < N_GP_DEVICE_ID); + + gp_device_reg_store(ID, _REG_GP_SYNCGEN_ENABLE_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_FREE_RUNNING_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_PAUSE_ADDR, ONE); + // gp_device_reg_store(ID, _REG_GP_NR_FRAMES_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_PIX_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_PIX_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_LINES_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR, ZERO); +// AM: Following calls cause strange warnings. Probably they should not be initialized. +// gp_device_reg_store(ID, _REG_GP_ISEL_SOF_ADDR, ZERO); +// gp_device_reg_store(ID, _REG_GP_ISEL_EOF_ADDR, ZERO); +// gp_device_reg_store(ID, _REG_GP_ISEL_SOL_ADDR, ZERO); +// gp_device_reg_store(ID, _REG_GP_ISEL_EOL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_ENABLE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_ENABLE_B_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_ENABLE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_ENABLE_B_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_HOR_CNT_MASK_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_VER_CNT_MASK_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_XY_CNT_MASK_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_HOR_CNT_DELTA_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_VER_CNT_DELTA_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_MODE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_RED1_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_GREEN1_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_BLUE1_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_RED2_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_GREEN2_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_BLUE2_ADDR, ZERO); + //gp_device_reg_store(ID, _REG_GP_ISEL_CH_ID_ADDR, ZERO); + //gp_device_reg_store(ID, _REG_GP_ISEL_FMT_TYPE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_DATA_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_SBAND_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_SYNC_SEL_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_HOR_CNT_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_VER_CNT_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_FRAME_CNT_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_SOFT_RESET_ADDR, + ZERO); // AM: Maybe this soft reset is not safe. +} + +static void input_selector_cfg_for_sensor(const gp_device_ID_t ID) +{ + assert(ID < N_GP_DEVICE_ID); + + gp_device_reg_store(ID, _REG_GP_ISEL_SOF_ADDR, ONE); + gp_device_reg_store(ID, _REG_GP_ISEL_EOF_ADDR, ONE); + gp_device_reg_store(ID, _REG_GP_ISEL_SOL_ADDR, ONE); + gp_device_reg_store(ID, _REG_GP_ISEL_EOL_ADDR, ONE); + gp_device_reg_store(ID, _REG_GP_ISEL_CH_ID_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_FMT_TYPE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_DATA_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_SBAND_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_SYNC_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_SOFT_RESET_ADDR, ZERO); +} + +static void input_switch_rst(const gp_device_ID_t ID) +{ + int addr; + + assert(ID < N_GP_DEVICE_ID); + + // Initialize the data&hsync LUT. + for (addr = _REG_GP_IFMT_input_switch_lut_reg0; + addr <= _REG_GP_IFMT_input_switch_lut_reg7; addr += SIZEOF_HRT_REG) { + gp_device_reg_store(ID, addr, ZERO); + } + + // Initialize the vsync LUT. + gp_device_reg_store(ID, + _REG_GP_IFMT_input_switch_fsync_lut, + ZERO); +} + +static void input_switch_cfg( + const gp_device_ID_t ID, + const input_switch_cfg_t *const cfg) +{ + int addr_offset; + + assert(ID < N_GP_DEVICE_ID); + assert(cfg); + + // Initialize the data&hsync LUT. + for (addr_offset = 0; addr_offset < N_RX_CHANNEL_ID * 2; addr_offset++) { + assert(addr_offset * SIZEOF_HRT_REG + _REG_GP_IFMT_input_switch_lut_reg0 <= + _REG_GP_IFMT_input_switch_lut_reg7); + gp_device_reg_store(ID, + _REG_GP_IFMT_input_switch_lut_reg0 + addr_offset * SIZEOF_HRT_REG, + cfg->hsync_data_reg[addr_offset]); + } + + // Initialize the vsync LUT. + gp_device_reg_store(ID, + _REG_GP_IFMT_input_switch_fsync_lut, + cfg->vsync_data_reg); +} + +static void input_system_network_rst(const input_system_ID_t ID) +{ + unsigned int sub_id; + + // Reset all 3 multicasts. + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX, + INPUT_SYSTEM_DISCARD_ALL); + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_B_IDX, + INPUT_SYSTEM_DISCARD_ALL); + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_C_IDX, + INPUT_SYSTEM_DISCARD_ALL); + + // Reset stream mux. + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX, + N_INPUT_SYSTEM_MULTIPLEX); + + // Reset 3 capture units. + for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; + sub_id++) { + input_system_sub_system_reg_store(ID, + sub_id, + CAPT_INIT_REG_ID, + 1U << CAPT_INIT_RST_REG_BIT); + } + + // Reset acquisition unit. + for (sub_id = ACQUISITION_UNIT0_ID; + sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) { + input_system_sub_system_reg_store(ID, + sub_id, + ACQ_INIT_REG_ID, + 1U << ACQ_INIT_RST_REG_BIT); + } + + // DMA unit reset is not needed. + + // Reset controller units. + // NB: In future we need to keep part of ctrl_state for split capture and + for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; + sub_id++) { + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_INIT_REG_ID, + 1U); //AM: Is there any named constant? + } +} + +// Function that resets current configuration. +input_system_err_t input_system_configuration_reset(void) +{ + unsigned int i; + + receiver_rst(RX0_ID); + + input_system_network_rst(INPUT_SYSTEM0_ID); + + gp_device_rst(GP_DEVICE0_ID); + + input_switch_rst(GP_DEVICE0_ID); + + //target_rst(); + + // Reset IRQ_CTRLs. + + // Reset configuration data structures. + for (i = 0; i < N_CHANNELS; i++) { + config.ch_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + config.target_isp_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + config.target_sp_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + config.target_strm2mem_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + } + + for (i = 0; i < N_CSI_PORTS; i++) { + config.csi_buffer_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL; + } + + config.source_type_flags = INPUT_SYSTEM_CFG_FLAG_RESET; + config.acquisition_buffer_unique_flags = INPUT_SYSTEM_CFG_FLAG_RESET; + config.unallocated_ib_mem_words = IB_CAPACITY_IN_WORDS; + //config.acq_allocated_ib_mem_words = 0; + + // Set the start of the session cofiguration. + config.session_flags = INPUT_SYSTEM_CFG_FLAG_REQUIRED; + + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// MW: Comments are good, but doxygen is required, place it at the declaration +// Function that appends the channel to current configuration. +static input_system_err_t input_system_configure_channel( + const channel_cfg_t channel) +{ + input_system_err_t error = INPUT_SYSTEM_ERR_NO_ERROR; + // Check if channel is not already configured. + if (config.ch_flags[channel.ch_id] & INPUT_SYSTEM_CFG_FLAG_SET) { + return INPUT_SYSTEM_ERR_CHANNEL_ALREADY_SET; + } else { + switch (channel.source_type) { + case INPUT_SYSTEM_SOURCE_SENSOR: + error = input_system_configure_channel_sensor(channel); + break; + case INPUT_SYSTEM_SOURCE_TPG: + case INPUT_SYSTEM_SOURCE_PRBS: + case INPUT_SYSTEM_SOURCE_FIFO: + default: + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + } + + if (error != INPUT_SYSTEM_ERR_NO_ERROR) return error; + // Input switch channel configurations must be combined in united config. + config.input_switch_cfg.hsync_data_reg[channel.source_cfg.csi_cfg.csi_port * 2] + = + channel.target_cfg.input_switch_channel_cfg.hsync_data_reg[0]; + config.input_switch_cfg.hsync_data_reg[channel.source_cfg.csi_cfg.csi_port * 2 + + 1] = + channel.target_cfg.input_switch_channel_cfg.hsync_data_reg[1]; + config.input_switch_cfg.vsync_data_reg |= + (channel.target_cfg.input_switch_channel_cfg.vsync_data_reg & 0x7) << + (channel.source_cfg.csi_cfg.csi_port * 3); + + // Other targets are just copied and marked as set. + config.target_isp[channel.source_cfg.csi_cfg.csi_port] = + channel.target_cfg.target_isp_cfg; + config.target_sp[channel.source_cfg.csi_cfg.csi_port] = + channel.target_cfg.target_sp_cfg; + config.target_strm2mem[channel.source_cfg.csi_cfg.csi_port] = + channel.target_cfg.target_strm2mem_cfg; + config.target_isp_flags[channel.source_cfg.csi_cfg.csi_port] |= + INPUT_SYSTEM_CFG_FLAG_SET; + config.target_sp_flags[channel.source_cfg.csi_cfg.csi_port] |= + INPUT_SYSTEM_CFG_FLAG_SET; + config.target_strm2mem_flags[channel.source_cfg.csi_cfg.csi_port] |= + INPUT_SYSTEM_CFG_FLAG_SET; + + config.ch_flags[channel.ch_id] = INPUT_SYSTEM_CFG_FLAG_SET; + } + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// Function that partitions input buffer space with determining addresses. +static input_system_err_t input_buffer_configuration(void) +{ + u32 current_address = 0; + u32 unallocated_memory = IB_CAPACITY_IN_WORDS; + + isp2400_ib_buffer_t candidate_buffer_acq = IB_BUFFER_NULL; + u32 size_requested; + input_system_config_flags_t acq_already_specified = INPUT_SYSTEM_CFG_FLAG_RESET; + input_system_csi_port_t port; + + for (port = INPUT_SYSTEM_PORT_A; port < N_INPUT_SYSTEM_PORTS; port++) { + csi_cfg_t source = config.csi_value[port];//.csi_cfg; + + if (config.csi_flags[port] & INPUT_SYSTEM_CFG_FLAG_SET) { + // Check and set csi buffer in input buffer. + switch (source.buffering_mode) { + case INPUT_SYSTEM_FIFO_CAPTURE: + case INPUT_SYSTEM_XMEM_ACQUIRE: + config.csi_buffer_flags[port] = + INPUT_SYSTEM_CFG_FLAG_BLOCKED; // Well, not used. + break; + + case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING: + case INPUT_SYSTEM_SRAM_BUFFERING: + case INPUT_SYSTEM_XMEM_BUFFERING: + case INPUT_SYSTEM_XMEM_CAPTURE: + size_requested = source.csi_buffer.mem_reg_size * + source.csi_buffer.nof_mem_regs; + if (source.csi_buffer.mem_reg_size > 0 + && source.csi_buffer.nof_mem_regs > 0 + && size_requested <= unallocated_memory + ) { + config.csi_buffer[port].mem_reg_addr = current_address; + config.csi_buffer[port].mem_reg_size = source.csi_buffer.mem_reg_size; + config.csi_buffer[port].nof_mem_regs = source.csi_buffer.nof_mem_regs; + current_address += size_requested; + unallocated_memory -= size_requested; + config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_SET; + } else { + config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + break; + + default: + config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + } + + // Check acquisition buffer specified but set it later since it has to be unique. + switch (source.buffering_mode) { + case INPUT_SYSTEM_FIFO_CAPTURE: + case INPUT_SYSTEM_SRAM_BUFFERING: + case INPUT_SYSTEM_XMEM_CAPTURE: + // Nothing to do. + break; + + case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING: + case INPUT_SYSTEM_XMEM_BUFFERING: + case INPUT_SYSTEM_XMEM_ACQUIRE: + if (acq_already_specified == INPUT_SYSTEM_CFG_FLAG_RESET) { + size_requested = source.acquisition_buffer.mem_reg_size + * source.acquisition_buffer.nof_mem_regs; + if (source.acquisition_buffer.mem_reg_size > 0 + && source.acquisition_buffer.nof_mem_regs > 0 + && size_requested <= unallocated_memory + ) { + candidate_buffer_acq = source.acquisition_buffer; + acq_already_specified = INPUT_SYSTEM_CFG_FLAG_SET; + } + } else { + // Check if specified acquisition buffer is the same as specified before. + if (source.acquisition_buffer.mem_reg_size != candidate_buffer_acq.mem_reg_size + || source.acquisition_buffer.nof_mem_regs != candidate_buffer_acq.nof_mem_regs + ) { + config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + } + break; + + default: + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + } + } else { + config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_BLOCKED; + } + } // end of for ( port ) + + // Set the acquisition buffer at the end. + size_requested = candidate_buffer_acq.mem_reg_size * + candidate_buffer_acq.nof_mem_regs; + if (acq_already_specified == INPUT_SYSTEM_CFG_FLAG_SET + && size_requested <= unallocated_memory) { + config.acquisition_buffer_unique.mem_reg_addr = current_address; + config.acquisition_buffer_unique.mem_reg_size = + candidate_buffer_acq.mem_reg_size; + config.acquisition_buffer_unique.nof_mem_regs = + candidate_buffer_acq.nof_mem_regs; + current_address += size_requested; + unallocated_memory -= size_requested; + config.acquisition_buffer_unique_flags = INPUT_SYSTEM_CFG_FLAG_SET; + + assert(current_address <= IB_CAPACITY_IN_WORDS); + } + + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +static void capture_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const isp2400_ib_buffer_t *const cfg) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= + CAPTURE_UNIT2_ID)); // Commented part is always true. + assert(cfg); + + input_system_sub_system_reg_store(ID, + sub_id, + CAPT_START_ADDR_REG_ID, + cfg->mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + CAPT_MEM_REGION_SIZE_REG_ID, + cfg->mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + CAPT_NUM_MEM_REGIONS_REG_ID, + cfg->nof_mem_regs); +} + +static void acquisition_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const isp2400_ib_buffer_t *const cfg) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(sub_id == ACQUISITION_UNIT0_ID); + assert(cfg); + + input_system_sub_system_reg_store(ID, + sub_id, + ACQ_START_ADDR_REG_ID, + cfg->mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ACQ_NUM_MEM_REGIONS_REG_ID, + cfg->nof_mem_regs); + input_system_sub_system_reg_store(ID, + sub_id, + ACQ_MEM_REGION_SIZE_REG_ID, + cfg->mem_reg_size); +} + +static void ctrl_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const ctrl_unit_cfg_t *const cfg) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(sub_id == CTRL_UNIT0_ID); + assert(cfg); + + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_A_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT0_ID].mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT0_ID].mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT0_ID].nof_mem_regs); + + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_B_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT1_ID].mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT1_ID].mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT1_ID].nof_mem_regs); + + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_C_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT2_ID].mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT2_ID].mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT2_ID].nof_mem_regs); + + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_ACQ_START_ADDR_REG_ID, + cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID, + cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID, + cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].nof_mem_regs); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID, + 0); +} + +static void input_system_network_configure( + const input_system_ID_t ID, + const input_system_network_cfg_t *const cfg) +{ + u32 sub_id; + + assert(ID < N_INPUT_SYSTEM_ID); + assert(cfg); + + // Set all 3 multicasts. + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX, + cfg->multicast_cfg[CAPTURE_UNIT0_ID]); + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_B_IDX, + cfg->multicast_cfg[CAPTURE_UNIT1_ID]); + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_C_IDX, + cfg->multicast_cfg[CAPTURE_UNIT2_ID]); + + // Set stream mux. + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX, + cfg->mux_cfg); + + // Set capture units. + for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; + sub_id++) { + capture_unit_configure(ID, + sub_id, + &cfg->ctrl_unit_cfg[ID].buffer_mipi[sub_id - CAPTURE_UNIT0_ID]); + } + + // Set acquisition units. + for (sub_id = ACQUISITION_UNIT0_ID; + sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) { + acquisition_unit_configure(ID, + sub_id, + &cfg->ctrl_unit_cfg[sub_id - ACQUISITION_UNIT0_ID].buffer_acquire[sub_id - + ACQUISITION_UNIT0_ID]); + } + + // No DMA configuration needed. Ctrl_unit will fully control it. + + // Set controller units. + for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; + sub_id++) { + ctrl_unit_configure(ID, + sub_id, + &cfg->ctrl_unit_cfg[sub_id - CTRL_UNIT0_ID]); + } +} + +static input_system_err_t configuration_to_registers(void) +{ + input_system_network_cfg_t input_system_network_cfg; + int i; + + assert(config.source_type_flags & INPUT_SYSTEM_CFG_FLAG_SET); + + switch (config.source_type) { + case INPUT_SYSTEM_SOURCE_SENSOR: + + // Determine stream multicasts setting based on the mode of csi_cfg_t. + // AM: This should be moved towards earlier function call, e.g. in + // the commit function. + for (i = MIPI_PORT0_ID; i < N_MIPI_PORT_ID; i++) { + if (config.csi_flags[i] & INPUT_SYSTEM_CFG_FLAG_SET) { + switch (config.csi_value[i].buffering_mode) { + case INPUT_SYSTEM_FIFO_CAPTURE: + config.multicast[i] = INPUT_SYSTEM_CSI_BACKEND; + break; + + case INPUT_SYSTEM_XMEM_CAPTURE: + case INPUT_SYSTEM_SRAM_BUFFERING: + case INPUT_SYSTEM_XMEM_BUFFERING: + config.multicast[i] = INPUT_SYSTEM_INPUT_BUFFER; + break; + + case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING: + config.multicast[i] = INPUT_SYSTEM_MULTICAST; + break; + + case INPUT_SYSTEM_XMEM_ACQUIRE: + config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL; + break; + + default: + config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL; + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + //break; + } + } else { + config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL; + } + + input_system_network_cfg.multicast_cfg[i] = config.multicast[i]; + + } // for + + input_system_network_cfg.mux_cfg = config.multiplexer; + + input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - + CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT0_ID] = + config.csi_buffer[MIPI_PORT0_ID]; + input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - + CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT1_ID] = + config.csi_buffer[MIPI_PORT1_ID]; + input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - + CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT2_ID] = + config.csi_buffer[MIPI_PORT2_ID]; + input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - + CTRL_UNIT0_ID].buffer_acquire[ACQUISITION_UNIT0_ID - + ACQUISITION_UNIT0_ID] = + config.acquisition_buffer_unique; + + // First set input network around CSI receiver. + input_system_network_configure(INPUT_SYSTEM0_ID, &input_system_network_cfg); + + // Set the CSI receiver. + //... + break; + + case INPUT_SYSTEM_SOURCE_TPG: + case INPUT_SYSTEM_SOURCE_PRBS: + case INPUT_SYSTEM_SOURCE_FIFO: + break; + + default: + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + + } // end of switch (source_type) + + // Set input selector. + input_selector_cfg_for_sensor(GP_DEVICE0_ID); + + // Set input switch. + input_switch_cfg(GP_DEVICE0_ID, &config.input_switch_cfg); + + // Set input formatters. + // AM: IF are set dynamically. + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// Function that applies the whole configuration. +input_system_err_t input_system_configuration_commit(void) +{ + // The last configuration step is to configure the input buffer. + input_system_err_t error = input_buffer_configuration(); + + if (error != INPUT_SYSTEM_ERR_NO_ERROR) { + return error; + } + + // Translate the whole configuration into registers. + error = configuration_to_registers(); + if (error != INPUT_SYSTEM_ERR_NO_ERROR) { + return error; + } + + // Translate the whole configuration into ctrl commands etc. + + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// FIFO + +input_system_err_t input_system_csi_fifo_channel_cfg( + u32 ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_FIFO_CAPTURE; + channel.source_cfg.csi_cfg.csi_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.nof_xmem_buffers = 0; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +input_system_err_t input_system_csi_fifo_channel_with_counting_cfg( + u32 ch_id, + u32 nof_frames, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + u32 csi_mem_reg_size, + u32 csi_nof_mem_regs, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = + INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size; + channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +// SRAM + +input_system_err_t input_system_csi_sram_channel_cfg( + u32 ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + u32 csi_mem_reg_size, + u32 csi_nof_mem_regs, + // uint32_t acq_mem_reg_size, + // uint32_t acq_nof_mem_regs, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_SRAM_BUFFERING; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size; + channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.nof_xmem_buffers = 0; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +//XMEM + +// Collects all parameters and puts them in channel_cfg_t. +input_system_err_t input_system_csi_xmem_channel_cfg( + u32 ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + u32 csi_mem_reg_size, + u32 csi_nof_mem_regs, + u32 acq_mem_reg_size, + u32 acq_nof_mem_regs, + target_cfg2400_t target, + uint32_t nof_xmem_buffers +) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_BUFFERING; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size; + channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size; + channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_xmem_buffers; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +input_system_err_t input_system_csi_xmem_acquire_only_channel_cfg( + u32 ch_id, + u32 nof_frames, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + u32 acq_mem_reg_size, + u32 acq_nof_mem_regs, + target_cfg2400_t target) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_ACQUIRE; + channel.source_cfg.csi_cfg.csi_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size; + channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +input_system_err_t input_system_csi_xmem_capture_only_channel_cfg( + u32 ch_id, + u32 nof_frames, + input_system_csi_port_t port, + u32 csi_mem_reg_size, + u32 csi_nof_mem_regs, + u32 acq_mem_reg_size, + u32 acq_nof_mem_regs, + target_cfg2400_t target) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + //channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + //channel.source_cfg.csi_cfg.backend_ch = backend_ch; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_CAPTURE; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size; + channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size; + channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +// Non - CSI + +input_system_err_t input_system_prbs_channel_cfg( + u32 ch_id, + u32 nof_frames,//not used yet + u32 seed, + u32 sync_gen_width, + u32 sync_gen_height, + u32 sync_gen_hblank_cycles, + u32 sync_gen_vblank_cycles, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + (void)nof_frames; + + channel.ch_id = ch_id; + channel.source_type = INPUT_SYSTEM_SOURCE_PRBS; + + channel.source_cfg.prbs_cfg.seed = seed; + channel.source_cfg.prbs_cfg.sync_gen_cfg.width = sync_gen_width; + channel.source_cfg.prbs_cfg.sync_gen_cfg.height = sync_gen_height; + channel.source_cfg.prbs_cfg.sync_gen_cfg.hblank_cycles = sync_gen_hblank_cycles; + channel.source_cfg.prbs_cfg.sync_gen_cfg.vblank_cycles = sync_gen_vblank_cycles; + + channel.target_cfg = target; + + return input_system_configure_channel(channel); +} + +input_system_err_t input_system_tpg_channel_cfg( + u32 ch_id, + u32 nof_frames,//not used yet + u32 x_mask, + u32 y_mask, + u32 x_delta, + u32 y_delta, + u32 xy_mask, + u32 sync_gen_width, + u32 sync_gen_height, + u32 sync_gen_hblank_cycles, + u32 sync_gen_vblank_cycles, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + (void)nof_frames; + + channel.ch_id = ch_id; + channel.source_type = INPUT_SYSTEM_SOURCE_TPG; + + channel.source_cfg.tpg_cfg.x_mask = x_mask; + channel.source_cfg.tpg_cfg.y_mask = y_mask; + channel.source_cfg.tpg_cfg.x_delta = x_delta; + channel.source_cfg.tpg_cfg.y_delta = y_delta; + channel.source_cfg.tpg_cfg.xy_mask = xy_mask; + channel.source_cfg.tpg_cfg.sync_gen_cfg.width = sync_gen_width; + channel.source_cfg.tpg_cfg.sync_gen_cfg.height = sync_gen_height; + channel.source_cfg.tpg_cfg.sync_gen_cfg.hblank_cycles = sync_gen_hblank_cycles; + channel.source_cfg.tpg_cfg.sync_gen_cfg.vblank_cycles = sync_gen_vblank_cycles; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +// MW: Don't use system specific names, (even in system specific files) "cfg2400" -> cfg +input_system_err_t input_system_gpfifo_channel_cfg( + u32 ch_id, + u32 nof_frames, //not used yet + + target_cfg2400_t target) +{ + channel_cfg_t channel; + + (void)nof_frames; + + channel.ch_id = ch_id; + channel.source_type = INPUT_SYSTEM_SOURCE_FIFO; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +/////////////////////////////////////////////////////////////////////////// +// +// Private specialized functions for channel setting. +// +/////////////////////////////////////////////////////////////////////////// + +// Fills the parameters to config.csi_value[port] +static input_system_err_t input_system_configure_channel_sensor( + const channel_cfg_t channel) +{ + const u32 port = channel.source_cfg.csi_cfg.csi_port; + input_system_err_t status = INPUT_SYSTEM_ERR_NO_ERROR; + + input_system_multiplex_t mux; + + if (port >= N_INPUT_SYSTEM_PORTS) + return INPUT_SYSTEM_ERR_GENERIC; + + //check if port > N_INPUT_SYSTEM_MULTIPLEX + + status = set_source_type(&config.source_type, channel.source_type, + &config.source_type_flags); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + + // Check for conflicts on source (implicitly on multicast, capture unit and input buffer). + + status = set_csi_cfg(&config.csi_value[port], &channel.source_cfg.csi_cfg, + &config.csi_flags[port]); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + + switch (channel.source_cfg.csi_cfg.buffering_mode) { + case INPUT_SYSTEM_FIFO_CAPTURE: + + // Check for conflicts on mux. + mux = INPUT_SYSTEM_MIPI_PORT0 + port; + status = input_system_multiplexer_cfg(&config.multiplexer, mux, + &config.multiplexer_flags); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + config.multicast[port] = INPUT_SYSTEM_CSI_BACKEND; + + // Shared resource, so it should be blocked. + //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + + break; + case INPUT_SYSTEM_SRAM_BUFFERING: + + // Check for conflicts on mux. + mux = INPUT_SYSTEM_ACQUISITION_UNIT; + status = input_system_multiplexer_cfg(&config.multiplexer, mux, + &config.multiplexer_flags); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + config.multicast[port] = INPUT_SYSTEM_INPUT_BUFFER; + + // Shared resource, so it should be blocked. + //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + + break; + case INPUT_SYSTEM_XMEM_BUFFERING: + + // Check for conflicts on mux. + mux = INPUT_SYSTEM_ACQUISITION_UNIT; + status = input_system_multiplexer_cfg(&config.multiplexer, mux, + &config.multiplexer_flags); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + config.multicast[port] = INPUT_SYSTEM_INPUT_BUFFER; + + // Shared resource, so it should be blocked. + //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + + break; + case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING: + case INPUT_SYSTEM_XMEM_CAPTURE: + case INPUT_SYSTEM_XMEM_ACQUIRE: + default: + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + } + + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// Test flags and set structure. +static input_system_err_t set_source_type( + input_system_source_t *const lhs, + const input_system_source_t rhs, + input_system_config_flags_t *const flags) +{ + // MW: Not enough asserts + assert(lhs); + assert(flags); + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_SET) { + // Check for consistency with already set value. + if ((*lhs) == (rhs)) { + return INPUT_SYSTEM_ERR_NO_ERROR; + } else { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + } + // Check the value (individually). + if (rhs >= N_INPUT_SYSTEM_SOURCE) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + // Set the value. + *lhs = rhs; + + *flags |= INPUT_SYSTEM_CFG_FLAG_SET; + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// Test flags and set structure. +static input_system_err_t set_csi_cfg( + csi_cfg_t *const lhs, + const csi_cfg_t *const rhs, + input_system_config_flags_t *const flags) +{ + u32 memory_required; + u32 acq_memory_required; + + assert(lhs); + assert(flags); + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + + if (*flags & INPUT_SYSTEM_CFG_FLAG_SET) { + // check for consistency with already set value. + if (/*lhs->backend_ch == rhs.backend_ch + &&*/ lhs->buffering_mode == rhs->buffering_mode + && lhs->csi_buffer.mem_reg_size == rhs->csi_buffer.mem_reg_size + && lhs->csi_buffer.nof_mem_regs == rhs->csi_buffer.nof_mem_regs + && lhs->acquisition_buffer.mem_reg_size == rhs->acquisition_buffer.mem_reg_size + && lhs->acquisition_buffer.nof_mem_regs == rhs->acquisition_buffer.nof_mem_regs + && lhs->nof_xmem_buffers == rhs->nof_xmem_buffers + ) { + return INPUT_SYSTEM_ERR_NO_ERROR; + } else { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + } + // Check the value (individually). + // no check for backend_ch + // no check for nof_xmem_buffers + memory_required = rhs->csi_buffer.mem_reg_size * rhs->csi_buffer.nof_mem_regs; + acq_memory_required = rhs->acquisition_buffer.mem_reg_size * + rhs->acquisition_buffer.nof_mem_regs; + if (rhs->buffering_mode >= N_INPUT_SYSTEM_BUFFERING_MODE + || + // Check if required memory is available in input buffer (SRAM). + (memory_required + acq_memory_required) > config.unallocated_ib_mem_words + + ) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + // Set the value. + //lhs[port]->backend_ch = rhs.backend_ch; + lhs->buffering_mode = rhs->buffering_mode; + lhs->nof_xmem_buffers = rhs->nof_xmem_buffers; + + lhs->csi_buffer.mem_reg_size = rhs->csi_buffer.mem_reg_size; + lhs->csi_buffer.nof_mem_regs = rhs->csi_buffer.nof_mem_regs; + lhs->acquisition_buffer.mem_reg_size = rhs->acquisition_buffer.mem_reg_size; + lhs->acquisition_buffer.nof_mem_regs = rhs->acquisition_buffer.nof_mem_regs; + // ALX: NB: Here we just set buffer parameters, but still not allocate it + // (no addresses determined). That will be done during commit. + + // FIXIT: acq_memory_required is not deducted, since it can be allocated multiple times. + config.unallocated_ib_mem_words -= memory_required; +//assert(config.unallocated_ib_mem_words >=0); + *flags |= INPUT_SYSTEM_CFG_FLAG_SET; + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// Test flags and set structure. +static input_system_err_t input_system_multiplexer_cfg( + input_system_multiplex_t *const lhs, + const input_system_multiplex_t rhs, + input_system_config_flags_t *const flags) +{ + assert(lhs); + assert(flags); + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_SET) { + // Check for consistency with already set value. + if ((*lhs) == (rhs)) { + return INPUT_SYSTEM_ERR_NO_ERROR; + } else { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + } + // Check the value (individually). + if (rhs >= N_INPUT_SYSTEM_MULTIPLEX) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + } + // Set the value. + *lhs = rhs; + + *flags |= INPUT_SYSTEM_CFG_FLAG_SET; + return INPUT_SYSTEM_ERR_NO_ERROR; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq.c new file mode 100644 index 000000000..80b5fd0dc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq.c @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "assert_support.h" +#include "irq.h" + +#ifndef __INLINE_GP_DEVICE__ +#define __INLINE_GP_DEVICE__ +#endif +#include "gp_device.h" /* _REG_GP_IRQ_REQUEST_ADDR */ + +static inline void irq_wait_for_write_complete( + const irq_ID_t ID); + +static inline bool any_irq_channel_enabled( + const irq_ID_t ID); + +static inline irq_ID_t virq_get_irq_id(const enum virq_id irq_ID, + unsigned int *channel_ID); + +#ifndef __INLINE_IRQ__ +#include "irq_private.h" +#endif /* __INLINE_IRQ__ */ + +static unsigned short IRQ_N_CHANNEL[N_IRQ_ID] = { + IRQ0_ID_N_CHANNEL, + IRQ1_ID_N_CHANNEL, + IRQ2_ID_N_CHANNEL, + IRQ3_ID_N_CHANNEL +}; + +static unsigned short IRQ_N_ID_OFFSET[N_IRQ_ID + 1] = { + IRQ0_ID_OFFSET, + IRQ1_ID_OFFSET, + IRQ2_ID_OFFSET, + IRQ3_ID_OFFSET, + IRQ_END_OFFSET +}; + +static enum virq_id IRQ_NESTING_ID[N_IRQ_ID] = { + N_virq_id, + virq_ifmt, + virq_isys, + virq_isel +}; + +void irq_clear_all( + const irq_ID_t ID) +{ + hrt_data mask = 0xFFFFFFFF; + + assert(ID < N_IRQ_ID); + assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH); + + if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) { + mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]); + } + + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, mask); + return; +} + +/* + * Do we want the user to be able to set the signalling method ? + */ +void irq_enable_channel( + const irq_ID_t ID, + const unsigned int irq_id) +{ + unsigned int mask = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX); + unsigned int enable = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX); + unsigned int edge_in = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_EDGE_REG_IDX); + unsigned int me = 1U << irq_id; + + assert(ID < N_IRQ_ID); + assert(irq_id < IRQ_N_CHANNEL[ID]); + + mask |= me; + enable |= me; + edge_in |= me; /* rising edge */ + + /* to avoid mishaps configuration must follow the following order */ + + /* mask this interrupt */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask & ~me); + /* rising edge at input */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_EDGE_REG_IDX, edge_in); + /* enable interrupt to output */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX, enable); + /* clear current irq only */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, me); + /* unmask interrupt from input */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask); + + irq_wait_for_write_complete(ID); + + return; +} + +void irq_enable_pulse( + const irq_ID_t ID, + bool pulse) +{ + unsigned int edge_out = 0x0; + + if (pulse) { + edge_out = 0xffffffff; + } + /* output is given as edge, not pulse */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX, edge_out); + return; +} + +void irq_disable_channel( + const irq_ID_t ID, + const unsigned int irq_id) +{ + unsigned int mask = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX); + unsigned int enable = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX); + unsigned int me = 1U << irq_id; + + assert(ID < N_IRQ_ID); + assert(irq_id < IRQ_N_CHANNEL[ID]); + + mask &= ~me; + enable &= ~me; + + /* enable interrupt to output */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX, enable); + /* unmask interrupt from input */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask); + /* clear current irq only */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, me); + + irq_wait_for_write_complete(ID); + + return; +} + +enum hrt_isp_css_irq_status irq_get_channel_id( + const irq_ID_t ID, + unsigned int *irq_id) +{ + unsigned int irq_status = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + unsigned int idx; + enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_success; + + assert(ID < N_IRQ_ID); + assert(irq_id); + + /* find the first irq bit */ + for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) { + if (irq_status & (1U << idx)) + break; + } + if (idx == IRQ_N_CHANNEL[ID]) + return hrt_isp_css_irq_status_error; + + /* now check whether there are more bits set */ + if (irq_status != (1U << idx)) + status = hrt_isp_css_irq_status_more_irqs; + + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << idx); + + irq_wait_for_write_complete(ID); + + if (irq_id) + *irq_id = (unsigned int)idx; + + return status; +} + +static const hrt_address IRQ_REQUEST_ADDR[N_IRQ_SW_CHANNEL_ID] = { + _REG_GP_IRQ_REQUEST0_ADDR, + _REG_GP_IRQ_REQUEST1_ADDR +}; + +void irq_raise( + const irq_ID_t ID, + const irq_sw_channel_id_t irq_id) +{ + hrt_address addr; + + OP___assert(ID == IRQ0_ID); + OP___assert(IRQ_BASE[ID] != (hrt_address)-1); + OP___assert(irq_id < N_IRQ_SW_CHANNEL_ID); + + (void)ID; + + addr = IRQ_REQUEST_ADDR[irq_id]; + /* The SW IRQ pins are remapped to offset zero */ + gp_device_reg_store(GP_DEVICE0_ID, + (unsigned int)addr, 1); + gp_device_reg_store(GP_DEVICE0_ID, + (unsigned int)addr, 0); + return; +} + +void irq_controller_get_state(const irq_ID_t ID, + struct irq_controller_state *state) +{ + assert(ID < N_IRQ_ID); + assert(state); + + state->irq_edge = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_EDGE_REG_IDX); + state->irq_mask = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX); + state->irq_status = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + state->irq_enable = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX); + state->irq_level_not_pulse = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX); + return; +} + +bool any_virq_signal(void) +{ + unsigned int irq_status = irq_reg_load(IRQ0_ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + + return (irq_status != 0); +} + +void cnd_virq_enable_channel( + const enum virq_id irq_ID, + const bool en) +{ + irq_ID_t i; + unsigned int channel_ID; + irq_ID_t ID = virq_get_irq_id(irq_ID, &channel_ID); + + assert(ID < N_IRQ_ID); + + for (i = IRQ1_ID; i < N_IRQ_ID; i++) { + /* It is not allowed to enable the pin of a nested IRQ directly */ + assert(irq_ID != IRQ_NESTING_ID[i]); + } + + if (en) { + irq_enable_channel(ID, channel_ID); + if (IRQ_NESTING_ID[ID] != N_virq_id) { + /* Single level nesting, otherwise we'd need to recurse */ + irq_enable_channel(IRQ0_ID, IRQ_NESTING_ID[ID]); + } + } else { + irq_disable_channel(ID, channel_ID); + if ((IRQ_NESTING_ID[ID] != N_virq_id) && !any_irq_channel_enabled(ID)) { + /* Only disable the top if the nested ones are empty */ + irq_disable_channel(IRQ0_ID, IRQ_NESTING_ID[ID]); + } + } + return; +} + +void virq_clear_all(void) +{ + irq_ID_t irq_id; + + for (irq_id = (irq_ID_t)0; irq_id < N_IRQ_ID; irq_id++) { + irq_clear_all(irq_id); + } + return; +} + +enum hrt_isp_css_irq_status +virq_get_channel_signals(struct virq_info *irq_info) +{ + enum hrt_isp_css_irq_status irq_status = hrt_isp_css_irq_status_error; + irq_ID_t ID; + + assert(irq_info); + + for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) { + if (any_irq_channel_enabled(ID)) { + hrt_data irq_data = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + + if (irq_data != 0) { + /* The error condition is an IRQ pulse received with no IRQ status written */ + irq_status = hrt_isp_css_irq_status_success; + } + + irq_info->irq_status_reg[ID] |= irq_data; + + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, irq_data); + + irq_wait_for_write_complete(ID); + } + } + + return irq_status; +} + +void virq_clear_info(struct virq_info *irq_info) +{ + irq_ID_t ID; + + assert(irq_info); + + for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) { + irq_info->irq_status_reg[ID] = 0; + } + return; +} + +enum hrt_isp_css_irq_status virq_get_channel_id( + enum virq_id *irq_id) +{ + unsigned int irq_status = irq_reg_load(IRQ0_ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + unsigned int idx; + enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_success; + irq_ID_t ID; + + assert(irq_id); + + /* find the first irq bit on device 0 */ + for (idx = 0; idx < IRQ_N_CHANNEL[IRQ0_ID]; idx++) { + if (irq_status & (1U << idx)) + break; + } + + if (idx == IRQ_N_CHANNEL[IRQ0_ID]) { + return hrt_isp_css_irq_status_error; + } + + /* Check whether there are more bits set on device 0 */ + if (irq_status != (1U << idx)) { + status = hrt_isp_css_irq_status_more_irqs; + } + + /* Check whether we have an IRQ on one of the nested devices */ + for (ID = N_IRQ_ID - 1 ; ID > (irq_ID_t)0; ID--) { + if (IRQ_NESTING_ID[ID] == (enum virq_id)idx) { + break; + } + } + + /* If we have a nested IRQ, load that state, discard the device 0 state */ + if (ID != IRQ0_ID) { + irq_status = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + /* find the first irq bit on device "id" */ + for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) { + if (irq_status & (1U << idx)) + break; + } + + if (idx == IRQ_N_CHANNEL[ID]) { + return hrt_isp_css_irq_status_error; + } + + /* Alternatively check whether there are more bits set on this device */ + if (irq_status != (1U << idx)) { + status = hrt_isp_css_irq_status_more_irqs; + } else { + /* If this device is empty, clear the state on device 0 */ + irq_reg_store(IRQ0_ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << IRQ_NESTING_ID[ID]); + } + } /* if (ID != IRQ0_ID) */ + + /* Here we proceed to clear the IRQ on detected device, if no nested IRQ, this is device 0 */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << idx); + + irq_wait_for_write_complete(ID); + + idx += IRQ_N_ID_OFFSET[ID]; + if (irq_id) + *irq_id = (enum virq_id)idx; + + return status; +} + +static inline void irq_wait_for_write_complete( + const irq_ID_t ID) +{ + assert(ID < N_IRQ_ID); + assert(IRQ_BASE[ID] != (hrt_address)-1); + (void)ia_css_device_load_uint32(IRQ_BASE[ID] + + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX * sizeof(hrt_data)); +} + +static inline bool any_irq_channel_enabled( + const irq_ID_t ID) +{ + hrt_data en_reg; + + assert(ID < N_IRQ_ID); + + en_reg = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX); + + return (en_reg != 0); +} + +static inline irq_ID_t virq_get_irq_id( + const enum virq_id irq_ID, + unsigned int *channel_ID) +{ + irq_ID_t ID; + + assert(channel_ID); + + for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) { + if (irq_ID < IRQ_N_ID_OFFSET[ID + 1]) { + break; + } + } + + *channel_ID = (unsigned int)irq_ID - IRQ_N_ID_OFFSET[ID]; + + return ID; +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq_local.h new file mode 100644 index 000000000..6a25345ae --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq_local.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IRQ_LOCAL_H_INCLUDED__ +#define __IRQ_LOCAL_H_INCLUDED__ + +#include "irq_global.h" + +#include + +/* IRQ0_ID */ +#include "hive_isp_css_defs.h" +#define HIVE_GP_DEV_IRQ_NUM_IRQS 32 +/* IRQ1_ID */ +#include "input_formatter_subsystem_defs.h" +#define HIVE_IFMT_IRQ_NUM_IRQS 5 +/* IRQ2_ID */ +#include "input_system_defs.h" +/* IRQ3_ID */ +#include "input_selector_defs.h" + +#define IRQ_ID_OFFSET 32 +#define IRQ0_ID_OFFSET 0 +#define IRQ1_ID_OFFSET IRQ_ID_OFFSET +#define IRQ2_ID_OFFSET (2 * IRQ_ID_OFFSET) +#define IRQ3_ID_OFFSET (3 * IRQ_ID_OFFSET) +#define IRQ_END_OFFSET (4 * IRQ_ID_OFFSET) + +#define IRQ0_ID_N_CHANNEL HIVE_GP_DEV_IRQ_NUM_IRQS +#define IRQ1_ID_N_CHANNEL HIVE_IFMT_IRQ_NUM_IRQS +#define IRQ2_ID_N_CHANNEL HIVE_ISYS_IRQ_NUM_BITS +#define IRQ3_ID_N_CHANNEL HIVE_ISEL_IRQ_NUM_IRQS + +enum virq_id { + virq_gpio_pin_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID, + virq_gpio_pin_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID, + virq_gpio_pin_2 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID, + virq_gpio_pin_3 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID, + virq_gpio_pin_4 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID, + virq_gpio_pin_5 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID, + virq_gpio_pin_6 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID, + virq_gpio_pin_7 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID, + virq_gpio_pin_8 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID, + virq_gpio_pin_9 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID, + virq_gpio_pin_10 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID, + virq_gpio_pin_11 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID, + virq_sp = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_BIT_ID, + virq_isp = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_BIT_ID, + virq_isys = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISYS_BIT_ID, + virq_isel = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISEL_BIT_ID, + virq_ifmt = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_IFMT_BIT_ID, + virq_sp_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID, + virq_isp_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID, + virq_mod_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID, + virq_isp_pmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID, + virq_isp_bamem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID, + virq_isp_dmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID, + virq_sp_icache_mem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID, + virq_sp_dmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID, + virq_mmu_cache_mem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID, + virq_gp_timer_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID, + virq_gp_timer_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID, + virq_sw_pin_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID, + virq_sw_pin_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID, + virq_dma = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_DMA_BIT_ID, + virq_sp_stream_mon_b = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID, + + virq_ifmt0_id = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID, + virq_ifmt1_id = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID, + virq_ifmt2_id = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_IFT_SEC_BIT_ID, + virq_ifmt3_id = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_MEM_CPY_BIT_ID, + virq_ifmt_sideband_changed = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID, + + virq_isys_sof = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_SOF_BIT_ID, + virq_isys_eof = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_EOF_BIT_ID, + virq_isys_sol = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_SOL_BIT_ID, + virq_isys_eol = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_EOL_BIT_ID, + virq_isys_csi = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID, + virq_isys_csi_be = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID, + virq_isys_capt0_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP, + virq_isys_capt0_id_late_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP, + virq_isys_capt1_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP, + virq_isys_capt1_id_late_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP, + virq_isys_capt2_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP, + virq_isys_capt2_id_late_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP, + virq_isys_acq_sop_mismatch = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH, + virq_isys_ctrl_capt0 = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_INP_CTRL_CAPA, + virq_isys_ctrl_capt1 = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_INP_CTRL_CAPB, + virq_isys_ctrl_capt2 = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_INP_CTRL_CAPC, + virq_isys_cio_to_ahb = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CIO2AHB, + virq_isys_dma = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_DMA_BIT_ID, + virq_isys_fifo_monitor = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_STREAM_MON_BIT_ID, + + virq_isel_sof = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID, + virq_isel_eof = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID, + virq_isel_sol = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID, + virq_isel_eol = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID, + + N_virq_id = IRQ_END_OFFSET +}; + +struct virq_info { + hrt_data irq_status_reg[N_IRQ_ID]; +}; + +struct irq_controller_state { + unsigned int irq_edge; + unsigned int irq_mask; + unsigned int irq_status; + unsigned int irq_enable; + unsigned int irq_level_not_pulse; +}; + +#endif /* __IRQ_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq_private.h new file mode 100644 index 000000000..e98663ef0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq_private.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IRQ_PRIVATE_H_INCLUDED__ +#define __IRQ_PRIVATE_H_INCLUDED__ + +#include "irq_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_IRQ_C void irq_reg_store( + const irq_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + assert(ID < N_IRQ_ID); + assert(IRQ_BASE[ID] != (hrt_address) - 1); + ia_css_device_store_uint32(IRQ_BASE[ID] + reg * sizeof(hrt_data), value); + return; +} + +STORAGE_CLASS_IRQ_C hrt_data irq_reg_load( + const irq_ID_t ID, + const unsigned int reg) +{ + assert(ID < N_IRQ_ID); + assert(IRQ_BASE[ID] != (hrt_address) - 1); + return ia_css_device_load_uint32(IRQ_BASE[ID] + reg * sizeof(hrt_data)); +} + +#endif /* __IRQ_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp.c new file mode 100644 index 000000000..4ad5e2db8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include +#include "isp.h" + +#ifndef __INLINE_ISP__ +#include "isp_private.h" +#endif /* __INLINE_ISP__ */ + +#include "assert_support.h" + +void cnd_isp_irq_enable( + const isp_ID_t ID, + const bool cnd) +{ + if (cnd) { + isp_ctrl_setbit(ID, ISP_IRQ_READY_REG, ISP_IRQ_READY_BIT); + /* Enabling the IRQ immediately triggers an interrupt, clear it */ + isp_ctrl_setbit(ID, ISP_IRQ_CLEAR_REG, ISP_IRQ_CLEAR_BIT); + } else { + isp_ctrl_clearbit(ID, ISP_IRQ_READY_REG, + ISP_IRQ_READY_BIT); + } + return; +} + +void isp_get_state( + const isp_ID_t ID, + isp_state_t *state, + isp_stall_t *stall) +{ + hrt_data sc = isp_ctrl_load(ID, ISP_SC_REG); + + assert(state); + assert(stall); + +#if defined(_hrt_sysmem_ident_address) + /* Patch to avoid compiler unused symbol warning in C_RUN build */ + (void)__hrt_sysmem_ident_address; + (void)_hrt_sysmem_map_var; +#endif + + state->pc = isp_ctrl_load(ID, ISP_PC_REG); + state->status_register = sc; + state->is_broken = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_BROKEN_BIT); + state->is_idle = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT); + state->is_sleeping = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_SLEEPING_BIT); + state->is_stalling = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_STALLING_BIT); + stall->stat_ctrl = + !isp_ctrl_getbit(ID, ISP_CTRL_SINK_REG, ISP_CTRL_SINK_BIT); + stall->pmem = + !isp_ctrl_getbit(ID, ISP_PMEM_SINK_REG, ISP_PMEM_SINK_BIT); + stall->dmem = + !isp_ctrl_getbit(ID, ISP_DMEM_SINK_REG, ISP_DMEM_SINK_BIT); + stall->vmem = + !isp_ctrl_getbit(ID, ISP_VMEM_SINK_REG, ISP_VMEM_SINK_BIT); + stall->fifo0 = + !isp_ctrl_getbit(ID, ISP_FIFO0_SINK_REG, ISP_FIFO0_SINK_BIT); + stall->fifo1 = + !isp_ctrl_getbit(ID, ISP_FIFO1_SINK_REG, ISP_FIFO1_SINK_BIT); + stall->fifo2 = + !isp_ctrl_getbit(ID, ISP_FIFO2_SINK_REG, ISP_FIFO2_SINK_BIT); + stall->fifo3 = + !isp_ctrl_getbit(ID, ISP_FIFO3_SINK_REG, ISP_FIFO3_SINK_BIT); + stall->fifo4 = + !isp_ctrl_getbit(ID, ISP_FIFO4_SINK_REG, ISP_FIFO4_SINK_BIT); + stall->fifo5 = + !isp_ctrl_getbit(ID, ISP_FIFO5_SINK_REG, ISP_FIFO5_SINK_BIT); + stall->fifo6 = + !isp_ctrl_getbit(ID, ISP_FIFO6_SINK_REG, ISP_FIFO6_SINK_BIT); + stall->vamem1 = + !isp_ctrl_getbit(ID, ISP_VAMEM1_SINK_REG, ISP_VAMEM1_SINK_BIT); + stall->vamem2 = + !isp_ctrl_getbit(ID, ISP_VAMEM2_SINK_REG, ISP_VAMEM2_SINK_BIT); + stall->vamem3 = + !isp_ctrl_getbit(ID, ISP_VAMEM3_SINK_REG, ISP_VAMEM3_SINK_BIT); + stall->hmem = + !isp_ctrl_getbit(ID, ISP_HMEM_SINK_REG, ISP_HMEM_SINK_BIT); + /* + stall->icache_master = + !isp_ctrl_getbit(ID, ISP_ICACHE_MT_SINK_REG, + ISP_ICACHE_MT_SINK_BIT); + */ + return; +} + +/* ISP functions to control the ISP state from the host, even in crun. */ + +/* Inspect readiness of an ISP indexed by ID */ +unsigned int isp_is_ready(isp_ID_t ID) +{ + assert(ID < N_ISP_ID); + return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT); +} + +/* Inspect sleeping of an ISP indexed by ID */ +unsigned int isp_is_sleeping(isp_ID_t ID) +{ + assert(ID < N_ISP_ID); + return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_SLEEPING_BIT); +} + +/* To be called by the host immediately before starting ISP ID. */ +void isp_start(isp_ID_t ID) +{ + assert(ID < N_ISP_ID); +} + +/* Wake up ISP ID. */ +void isp_wake(isp_ID_t ID) +{ + assert(ID < N_ISP_ID); + isp_ctrl_setbit(ID, ISP_SC_REG, ISP_START_BIT); + udelay(1); +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp_local.h new file mode 100644 index 000000000..4dbec4063 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp_local.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_LOCAL_H_INCLUDED__ +#define __ISP_LOCAL_H_INCLUDED__ + +#include "isp_global.h" + +#include + +#define HIVE_ISP_VMEM_MASK ((1U << ISP_VMEM_ELEMBITS) - 1) + +typedef struct isp_state_s isp_state_t; +typedef struct isp_stall_s isp_stall_t; + +struct isp_state_s { + int pc; + int status_register; + bool is_broken; + bool is_idle; + bool is_sleeping; + bool is_stalling; +}; + +struct isp_stall_s { + bool fifo0; + bool fifo1; + bool fifo2; + bool fifo3; + bool fifo4; + bool fifo5; + bool fifo6; + bool stat_ctrl; + bool dmem; + bool vmem; + bool vamem1; + bool vamem2; + bool vamem3; + bool hmem; + bool pmem; + bool icache_master; +}; + +#endif /* __ISP_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp_private.h new file mode 100644 index 000000000..2f9aeb3bd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp_private.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_PRIVATE_H_INCLUDED__ +#define __ISP_PRIVATE_H_INCLUDED__ + +#ifdef HRT_MEMORY_ACCESS +#include +#endif + +#include "isp_public.h" + +#include "device_access.h" + +#include "assert_support.h" +#include "type_support.h" + +STORAGE_CLASS_ISP_C void isp_ctrl_store( + const isp_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + assert(ID < N_ISP_ID); + assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_store_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); +#else + hrt_master_port_store_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); +#endif + return; +} + +STORAGE_CLASS_ISP_C hrt_data isp_ctrl_load( + const isp_ID_t ID, + const unsigned int reg) +{ + assert(ID < N_ISP_ID); + assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); +#if !defined(HRT_MEMORY_ACCESS) + return ia_css_device_load_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); +#else + return hrt_master_port_uload_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); +#endif +} + +STORAGE_CLASS_ISP_C bool isp_ctrl_getbit( + const isp_ID_t ID, + const unsigned int reg, + const unsigned int bit) +{ + hrt_data val = isp_ctrl_load(ID, reg); + + return (val & (1UL << bit)) != 0; +} + +STORAGE_CLASS_ISP_C void isp_ctrl_setbit( + const isp_ID_t ID, + const unsigned int reg, + const unsigned int bit) +{ + hrt_data data = isp_ctrl_load(ID, reg); + + isp_ctrl_store(ID, reg, (data | (1UL << bit))); + return; +} + +STORAGE_CLASS_ISP_C void isp_ctrl_clearbit( + const isp_ID_t ID, + const unsigned int reg, + const unsigned int bit) +{ + hrt_data data = isp_ctrl_load(ID, reg); + + isp_ctrl_store(ID, reg, (data & ~(1UL << bit))); + return; +} + +STORAGE_CLASS_ISP_C void isp_dmem_store( + const isp_ID_t ID, + unsigned int addr, + const void *data, + const size_t size) +{ + assert(ID < N_ISP_ID); + assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1); +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_store(ISP_DMEM_BASE[ID] + addr, data, size); +#else + hrt_master_port_store(ISP_DMEM_BASE[ID] + addr, data, size); +#endif + return; +} + +STORAGE_CLASS_ISP_C void isp_dmem_load( + const isp_ID_t ID, + const unsigned int addr, + void *data, + const size_t size) +{ + assert(ID < N_ISP_ID); + assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1); +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_load(ISP_DMEM_BASE[ID] + addr, data, size); +#else + hrt_master_port_load(ISP_DMEM_BASE[ID] + addr, data, size); +#endif + return; +} + +STORAGE_CLASS_ISP_C void isp_dmem_store_uint32( + const isp_ID_t ID, + unsigned int addr, + const uint32_t data) +{ + assert(ID < N_ISP_ID); + assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1); + (void)ID; +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_store_uint32(ISP_DMEM_BASE[ID] + addr, data); +#else + hrt_master_port_store_32(ISP_DMEM_BASE[ID] + addr, data); +#endif + return; +} + +STORAGE_CLASS_ISP_C uint32_t isp_dmem_load_uint32( + const isp_ID_t ID, + const unsigned int addr) +{ + assert(ID < N_ISP_ID); + assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1); + (void)ID; +#if !defined(HRT_MEMORY_ACCESS) + return ia_css_device_load_uint32(ISP_DMEM_BASE[ID] + addr); +#else + return hrt_master_port_uload_32(ISP_DMEM_BASE[ID] + addr); +#endif +} + +STORAGE_CLASS_ISP_C uint32_t isp_2w_cat_1w( + const u16 x0, + const uint16_t x1) +{ + u32 out = ((uint32_t)(x1 & HIVE_ISP_VMEM_MASK) << ISP_VMEM_ELEMBITS) + | (x0 & HIVE_ISP_VMEM_MASK); + return out; +} + +#endif /* __ISP_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/mmu.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/mmu.c new file mode 100644 index 000000000..eb02835aa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/mmu.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* The name "mmu.h is already taken" */ +#include "mmu_device.h" + +void mmu_set_page_table_base_index( + const mmu_ID_t ID, + const hrt_data base_index) +{ + mmu_reg_store(ID, _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX, base_index); + return; +} + +hrt_data mmu_get_page_table_base_index( + const mmu_ID_t ID) +{ + return mmu_reg_load(ID, _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX); +} + +void mmu_invalidate_cache( + const mmu_ID_t ID) +{ + mmu_reg_store(ID, _HRT_MMU_INVALIDATE_TLB_REG_IDX, 1); + return; +} + +void mmu_invalidate_cache_all(void) +{ + mmu_ID_t mmu_id; + + for (mmu_id = (mmu_ID_t)0; mmu_id < N_MMU_ID; mmu_id++) { + mmu_invalidate_cache(mmu_id); + } +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/mmu_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/mmu_local.h new file mode 100644 index 000000000..913150504 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/mmu_local.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MMU_LOCAL_H_INCLUDED__ +#define __MMU_LOCAL_H_INCLUDED__ + +#include "mmu_global.h" + +#endif /* __MMU_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp.c new file mode 100644 index 000000000..aae18465b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "sp.h" + +#ifndef __INLINE_SP__ +#include "sp_private.h" +#endif /* __INLINE_SP__ */ + +#include "assert_support.h" + +void cnd_sp_irq_enable( + const sp_ID_t ID, + const bool cnd) +{ + if (cnd) { + sp_ctrl_setbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT); + /* Enabling the IRQ immediately triggers an interrupt, clear it */ + sp_ctrl_setbit(ID, SP_IRQ_CLEAR_REG, SP_IRQ_CLEAR_BIT); + } else { + sp_ctrl_clearbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT); + } +} + +void sp_get_state( + const sp_ID_t ID, + sp_state_t *state, + sp_stall_t *stall) +{ + hrt_data sc = sp_ctrl_load(ID, SP_SC_REG); + + assert(state); + assert(stall); + + state->pc = sp_ctrl_load(ID, SP_PC_REG); + state->status_register = sc; + state->is_broken = (sc & (1U << SP_BROKEN_BIT)) != 0; + state->is_idle = (sc & (1U << SP_IDLE_BIT)) != 0; + state->is_sleeping = (sc & (1U << SP_SLEEPING_BIT)) != 0; + state->is_stalling = (sc & (1U << SP_STALLING_BIT)) != 0; + stall->fifo0 = + !sp_ctrl_getbit(ID, SP_FIFO0_SINK_REG, SP_FIFO0_SINK_BIT); + stall->fifo1 = + !sp_ctrl_getbit(ID, SP_FIFO1_SINK_REG, SP_FIFO1_SINK_BIT); + stall->fifo2 = + !sp_ctrl_getbit(ID, SP_FIFO2_SINK_REG, SP_FIFO2_SINK_BIT); + stall->fifo3 = + !sp_ctrl_getbit(ID, SP_FIFO3_SINK_REG, SP_FIFO3_SINK_BIT); + stall->fifo4 = + !sp_ctrl_getbit(ID, SP_FIFO4_SINK_REG, SP_FIFO4_SINK_BIT); + stall->fifo5 = + !sp_ctrl_getbit(ID, SP_FIFO5_SINK_REG, SP_FIFO5_SINK_BIT); + stall->fifo6 = + !sp_ctrl_getbit(ID, SP_FIFO6_SINK_REG, SP_FIFO6_SINK_BIT); + stall->fifo7 = + !sp_ctrl_getbit(ID, SP_FIFO7_SINK_REG, SP_FIFO7_SINK_BIT); + stall->fifo8 = + !sp_ctrl_getbit(ID, SP_FIFO8_SINK_REG, SP_FIFO8_SINK_BIT); + stall->fifo9 = + !sp_ctrl_getbit(ID, SP_FIFO9_SINK_REG, SP_FIFO9_SINK_BIT); + stall->fifoa = + !sp_ctrl_getbit(ID, SP_FIFOA_SINK_REG, SP_FIFOA_SINK_BIT); + stall->dmem = + !sp_ctrl_getbit(ID, SP_DMEM_SINK_REG, SP_DMEM_SINK_BIT); + stall->control_master = + !sp_ctrl_getbit(ID, SP_CTRL_MT_SINK_REG, SP_CTRL_MT_SINK_BIT); + stall->icache_master = + !sp_ctrl_getbit(ID, SP_ICACHE_MT_SINK_REG, + SP_ICACHE_MT_SINK_BIT); +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_local.h new file mode 100644 index 000000000..2956c7023 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_local.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_LOCAL_H_INCLUDED__ +#define __SP_LOCAL_H_INCLUDED__ + +#include +#include "sp_global.h" + +struct sp_state_s { + int pc; + int status_register; + bool is_broken; + bool is_idle; + bool is_sleeping; + bool is_stalling; +}; + +struct sp_stall_s { + bool fifo0; + bool fifo1; + bool fifo2; + bool fifo3; + bool fifo4; + bool fifo5; + bool fifo6; + bool fifo7; + bool fifo8; + bool fifo9; + bool fifoa; + bool dmem; + bool control_master; + bool icache_master; +}; + +#define sp_address_of(var) (HIVE_ADDR_ ## var) + +/* + * deprecated + */ +#define store_sp_int(var, value) \ + sp_dmem_store_uint32(SP0_ID, (unsigned int)sp_address_of(var), \ + (uint32_t)(value)) + +#define store_sp_ptr(var, value) \ + sp_dmem_store_uint32(SP0_ID, (unsigned int)sp_address_of(var), \ + (uint32_t)(value)) + +#define load_sp_uint(var) \ + sp_dmem_load_uint32(SP0_ID, (unsigned int)sp_address_of(var)) + +#define load_sp_array_uint8(array_name, index) \ + sp_dmem_load_uint8(SP0_ID, (unsigned int)sp_address_of(array_name) + \ + (index) * sizeof(uint8_t)) + +#define load_sp_array_uint16(array_name, index) \ + sp_dmem_load_uint16(SP0_ID, (unsigned int)sp_address_of(array_name) + \ + (index) * sizeof(uint16_t)) + +#define load_sp_array_uint(array_name, index) \ + sp_dmem_load_uint32(SP0_ID, (unsigned int)sp_address_of(array_name) + \ + (index) * sizeof(uint32_t)) + +#define store_sp_var(var, data, bytes) \ + sp_dmem_store(SP0_ID, (unsigned int)sp_address_of(var), data, bytes) + +#define store_sp_array_uint8(array_name, index, value) \ + sp_dmem_store_uint8(SP0_ID, (unsigned int)sp_address_of(array_name) + \ + (index) * sizeof(uint8_t), value) + +#define store_sp_array_uint16(array_name, index, value) \ + sp_dmem_store_uint16(SP0_ID, (unsigned int)sp_address_of(array_name) + \ + (index) * sizeof(uint16_t), value) + +#define store_sp_array_uint(array_name, index, value) \ + sp_dmem_store_uint32(SP0_ID, (unsigned int)sp_address_of(array_name) + \ + (index) * sizeof(uint32_t), value) + +#define store_sp_var_with_offset(var, offset, data, bytes) \ + sp_dmem_store(SP0_ID, (unsigned int)sp_address_of(var) + \ + offset, data, bytes) + +#define load_sp_var(var, data, bytes) \ + sp_dmem_load(SP0_ID, (unsigned int)sp_address_of(var), data, bytes) + +#define load_sp_var_with_offset(var, offset, data, bytes) \ + sp_dmem_load(SP0_ID, (unsigned int)sp_address_of(var) + offset, \ + data, bytes) + +#endif /* __SP_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_private.h new file mode 100644 index 000000000..05e6b438d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_private.h @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_PRIVATE_H_INCLUDED__ +#define __SP_PRIVATE_H_INCLUDED__ + +#include "sp_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_SP_C void sp_ctrl_store( + const sp_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_SP_ID); + assert(SP_CTRL_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); + return; +} + +STORAGE_CLASS_SP_C hrt_data sp_ctrl_load( + const sp_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_SP_ID); + assert(SP_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); +} + +STORAGE_CLASS_SP_C bool sp_ctrl_getbit( + const sp_ID_t ID, + const hrt_address reg, + const unsigned int bit) +{ + hrt_data val = sp_ctrl_load(ID, reg); + + return (val & (1UL << bit)) != 0; +} + +STORAGE_CLASS_SP_C void sp_ctrl_setbit( + const sp_ID_t ID, + const hrt_address reg, + const unsigned int bit) +{ + hrt_data data = sp_ctrl_load(ID, reg); + + sp_ctrl_store(ID, reg, (data | (1UL << bit))); + return; +} + +STORAGE_CLASS_SP_C void sp_ctrl_clearbit( + const sp_ID_t ID, + const hrt_address reg, + const unsigned int bit) +{ + hrt_data data = sp_ctrl_load(ID, reg); + + sp_ctrl_store(ID, reg, (data & ~(1UL << bit))); + return; +} + +STORAGE_CLASS_SP_C void sp_dmem_store( + const sp_ID_t ID, + hrt_address addr, + const void *data, + const size_t size) +{ + assert(ID < N_SP_ID); + assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + ia_css_device_store(SP_DMEM_BASE[ID] + addr, data, size); + return; +} + +STORAGE_CLASS_SP_C void sp_dmem_load( + const sp_ID_t ID, + const hrt_address addr, + void *data, + const size_t size) +{ + assert(ID < N_SP_ID); + assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + ia_css_device_load(SP_DMEM_BASE[ID] + addr, data, size); + return; +} + +STORAGE_CLASS_SP_C void sp_dmem_store_uint8( + const sp_ID_t ID, + hrt_address addr, + const uint8_t data) +{ + assert(ID < N_SP_ID); + assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; + ia_css_device_store_uint8(SP_DMEM_BASE[SP0_ID] + addr, data); + return; +} + +STORAGE_CLASS_SP_C void sp_dmem_store_uint16( + const sp_ID_t ID, + hrt_address addr, + const uint16_t data) +{ + assert(ID < N_SP_ID); + assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; + ia_css_device_store_uint16(SP_DMEM_BASE[SP0_ID] + addr, data); + return; +} + +STORAGE_CLASS_SP_C void sp_dmem_store_uint32( + const sp_ID_t ID, + hrt_address addr, + const uint32_t data) +{ + assert(ID < N_SP_ID); + assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; + ia_css_device_store_uint32(SP_DMEM_BASE[SP0_ID] + addr, data); + return; +} + +STORAGE_CLASS_SP_C uint8_t sp_dmem_load_uint8( + const sp_ID_t ID, + const hrt_address addr) +{ + assert(ID < N_SP_ID); + assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; + return ia_css_device_load_uint8(SP_DMEM_BASE[SP0_ID] + addr); +} + +STORAGE_CLASS_SP_C uint16_t sp_dmem_load_uint16( + const sp_ID_t ID, + const hrt_address addr) +{ + assert(ID < N_SP_ID); + assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; + return ia_css_device_load_uint16(SP_DMEM_BASE[SP0_ID] + addr); +} + +STORAGE_CLASS_SP_C uint32_t sp_dmem_load_uint32( + const sp_ID_t ID, + const hrt_address addr) +{ + assert(ID < N_SP_ID); + assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; + return ia_css_device_load_uint32(SP_DMEM_BASE[SP0_ID] + addr); +} + +#endif /* __SP_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl.c new file mode 100644 index 000000000..bc9e7f10f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "timed_ctrl.h" + +#ifndef __INLINE_TIMED_CTRL__ +#include "timed_ctrl_private.h" +#endif /* __INLINE_TIMED_CTRL__ */ + +#include "assert_support.h" + +void timed_ctrl_snd_commnd( + const timed_ctrl_ID_t ID, + hrt_data mask, + hrt_data condition, + hrt_data counter, + hrt_address addr, + hrt_data value) +{ + OP___assert(ID == TIMED_CTRL0_ID); + OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address)-1); + + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, mask); + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, condition); + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, counter); + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, (hrt_data)addr); + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, value); +} + +/* pqiao TODO: make sure the following commands get + correct BASE address both for csim and android */ + +void timed_ctrl_snd_sp_commnd( + const timed_ctrl_ID_t ID, + hrt_data mask, + hrt_data condition, + hrt_data counter, + const sp_ID_t SP_ID, + hrt_address offset, + hrt_data value) +{ + OP___assert(SP_ID < N_SP_ID); + OP___assert(SP_DMEM_BASE[SP_ID] != (hrt_address)-1); + + timed_ctrl_snd_commnd(ID, mask, condition, counter, + SP_DMEM_BASE[SP_ID] + offset, value); +} + +void timed_ctrl_snd_gpio_commnd( + const timed_ctrl_ID_t ID, + hrt_data mask, + hrt_data condition, + hrt_data counter, + const gpio_ID_t GPIO_ID, + hrt_address offset, + hrt_data value) +{ + OP___assert(GPIO_ID < N_GPIO_ID); + OP___assert(GPIO_BASE[GPIO_ID] != (hrt_address)-1); + + timed_ctrl_snd_commnd(ID, mask, condition, counter, + GPIO_BASE[GPIO_ID] + offset, value); +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl_local.h new file mode 100644 index 000000000..f58ee6afc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl_local.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TIMED_CTRL_LOCAL_H_INCLUDED__ +#define __TIMED_CTRL_LOCAL_H_INCLUDED__ + +#include "timed_ctrl_global.h" + +#endif /* __TIMED_CTRL_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl_private.h new file mode 100644 index 000000000..c19eeafed --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl_private.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TIMED_CTRL_PRIVATE_H_INCLUDED__ +#define __TIMED_CTRL_PRIVATE_H_INCLUDED__ + +#include "timed_ctrl_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_TIMED_CTRL_C void timed_ctrl_reg_store( + const timed_ctrl_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + OP___assert(ID < N_TIMED_CTRL_ID); + OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address) - 1); + ia_css_device_store_uint32(TIMED_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); +} + +#endif /* __GP_DEVICE_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vamem_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vamem_local.h new file mode 100644 index 000000000..c68ed984c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vamem_local.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VAMEM_LOCAL_H_INCLUDED__ +#define __VAMEM_LOCAL_H_INCLUDED__ + +#include "vamem_global.h" + +#endif /* __VAMEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c new file mode 100644 index 000000000..6620f0914 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2016, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "isp.h" +#include "vmem.h" +#include "vmem_local.h" + +#if !defined(HRT_MEMORY_ACCESS) +#include "ia_css_device_access.h" +#endif +#include "assert_support.h" + +typedef unsigned long long hive_uedge; +typedef hive_uedge *hive_wide; + +/* Copied from SDK: sim_semantics.c */ + +/* subword bits move like this: MSB[____xxxx____]LSB -> MSB[00000000xxxx]LSB */ +#define SUBWORD(w, start, end) (((w) & (((1ULL << ((end) - 1)) - 1) << 1 | 1)) >> (start)) + +/* inverse subword bits move like this: MSB[xxxx____xxxx]LSB -> MSB[xxxx0000xxxx]LSB */ +#define INV_SUBWORD(w, start, end) ((w) & (~(((1ULL << ((end) - 1)) - 1) << 1 | 1) | ((1ULL << (start)) - 1))) + +#define uedge_bits (8 * sizeof(hive_uedge)) +#define move_lower_bits(target, target_bit, src, src_bit) move_subword(target, target_bit, src, 0, src_bit) +#define move_upper_bits(target, target_bit, src, src_bit) move_subword(target, target_bit, src, src_bit, uedge_bits) +#define move_word(target, target_bit, src) move_subword(target, target_bit, src, 0, uedge_bits) + +static void +move_subword( + hive_uedge *target, + unsigned int target_bit, + hive_uedge src, + unsigned int src_start, + unsigned int src_end) +{ + unsigned int start_elem = target_bit / uedge_bits; + unsigned int start_bit = target_bit % uedge_bits; + unsigned int subword_width = src_end - src_start; + + hive_uedge src_subword = SUBWORD(src, src_start, src_end); + + if (subword_width + start_bit > uedge_bits) { /* overlap */ + hive_uedge old_val1; + hive_uedge old_val0 = INV_SUBWORD(target[start_elem], start_bit, uedge_bits); + + target[start_elem] = old_val0 | (src_subword << start_bit); + old_val1 = INV_SUBWORD(target[start_elem + 1], 0, + subword_width + start_bit - uedge_bits); + target[start_elem + 1] = old_val1 | (src_subword >> (uedge_bits - start_bit)); + } else { + hive_uedge old_val = INV_SUBWORD(target[start_elem], start_bit, + start_bit + subword_width); + + target[start_elem] = old_val | (src_subword << start_bit); + } +} + +static void +hive_sim_wide_unpack( + hive_wide vector, + hive_wide elem, + hive_uint elem_bits, + hive_uint index) +{ + /* pointers into wide_type: */ + unsigned int start_elem = (elem_bits * index) / uedge_bits; + unsigned int start_bit = (elem_bits * index) % uedge_bits; + unsigned int end_elem = (elem_bits * (index + 1) - 1) / uedge_bits; + unsigned int end_bit = ((elem_bits * (index + 1) - 1) % uedge_bits) + 1; + + if (elem_bits == uedge_bits) { + /* easy case for speedup: */ + elem[0] = vector[index]; + } else if (start_elem == end_elem) { + /* only one (<=64 bits) element needs to be (partly) copied: */ + move_subword(elem, 0, vector[start_elem], start_bit, end_bit); + } else { + /* general case: handles edge spanning cases (includes >64bit elements) */ + unsigned int bits_written = 0; + unsigned int i; + + move_upper_bits(elem, bits_written, vector[start_elem], start_bit); + bits_written += (64 - start_bit); + for (i = start_elem + 1; i < end_elem; i++) { + move_word(elem, bits_written, vector[i]); + bits_written += uedge_bits; + } + move_lower_bits(elem, bits_written, vector[end_elem], end_bit); + } +} + +static void +hive_sim_wide_pack( + hive_wide vector, + hive_wide elem, + hive_uint elem_bits, + hive_uint index) +{ + /* pointers into wide_type: */ + unsigned int start_elem = (elem_bits * index) / uedge_bits; + + /* easy case for speedup: */ + if (elem_bits == uedge_bits) { + vector[start_elem] = elem[0]; + } else if (elem_bits > uedge_bits) { + unsigned int bits_to_write = elem_bits; + unsigned int start_bit = elem_bits * index; + unsigned int i = 0; + + for (; bits_to_write > uedge_bits; + bits_to_write -= uedge_bits, i++, start_bit += uedge_bits) { + move_word(vector, start_bit, elem[i]); + } + move_lower_bits(vector, start_bit, elem[i], bits_to_write); + } else { + /* only one element needs to be (partly) copied: */ + move_lower_bits(vector, elem_bits * index, elem[0], elem_bits); + } +} + +static void load_vector( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from) +{ + unsigned int i; + hive_uedge *data; + unsigned int size = sizeof(short) * ISP_NWAY; + + VMEM_ARRAY(v, 2 * ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */ + assert(ISP_BAMEM_BASE[ID] != (hrt_address) - 1); +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_load(ISP_BAMEM_BASE[ID] + (unsigned long)from, &v[0][0], size); +#else + hrt_master_port_load(ISP_BAMEM_BASE[ID] + (unsigned long)from, &v[0][0], size); +#endif + data = (hive_uedge *)v; + for (i = 0; i < ISP_NWAY; i++) { + hive_uedge elem = 0; + + hive_sim_wide_unpack(data, &elem, ISP_VEC_ELEMBITS, i); + to[i] = elem; + } + udelay(1); /* Spend at least 1 cycles per vector */ +} + +static void store_vector( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from) +{ + unsigned int i; + unsigned int size = sizeof(short) * ISP_NWAY; + + VMEM_ARRAY(v, 2 * ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */ + //load_vector (&v[1][0], &to[ISP_NWAY]); /* Fetch the next vector, since it will be overwritten. */ + hive_uedge *data = (hive_uedge *)v; + + for (i = 0; i < ISP_NWAY; i++) { + hive_sim_wide_pack(data, (hive_wide)&from[i], ISP_VEC_ELEMBITS, i); + } + assert(ISP_BAMEM_BASE[ID] != (hrt_address) - 1); +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_store(ISP_BAMEM_BASE[ID] + (unsigned long)to, &v, size); +#else + //hrt_mem_store (ISP, VMEM, (unsigned)to, &v, siz); /* This will overwrite the next vector as well */ + hrt_master_port_store(ISP_BAMEM_BASE[ID] + (unsigned long)to, &v, size); +#endif + udelay(1); /* Spend at least 1 cycles per vector */ +} + +void isp_vmem_load( + const isp_ID_t ID, + const t_vmem_elem *from, + t_vmem_elem *to, + unsigned int elems) /* In t_vmem_elem */ +{ + unsigned int c; + const t_vmem_elem *vp = from; + + assert(ID < N_ISP_ID); + assert((unsigned long)from % ISP_VEC_ALIGN == 0); + assert(elems % ISP_NWAY == 0); + for (c = 0; c < elems; c += ISP_NWAY) { + load_vector(ID, &to[c], vp); + vp = (t_vmem_elem *)((char *)vp + ISP_VEC_ALIGN); + } +} + +void isp_vmem_store( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from, + unsigned int elems) /* In t_vmem_elem */ +{ + unsigned int c; + t_vmem_elem *vp = to; + + assert(ID < N_ISP_ID); + assert((unsigned long)to % ISP_VEC_ALIGN == 0); + assert(elems % ISP_NWAY == 0); + for (c = 0; c < elems; c += ISP_NWAY) { + store_vector(ID, vp, &from[c]); + vp = (t_vmem_elem *)((char *)vp + ISP_VEC_ALIGN); + } +} + +void isp_vmem_2d_load( + const isp_ID_t ID, + const t_vmem_elem *from, + t_vmem_elem *to, + unsigned int height, + unsigned int width, + unsigned int stride_to, /* In t_vmem_elem */ + + unsigned stride_from /* In t_vmem_elem */) +{ + unsigned int h; + + assert(ID < N_ISP_ID); + assert((unsigned long)from % ISP_VEC_ALIGN == 0); + assert(width % ISP_NWAY == 0); + assert(stride_from % ISP_NWAY == 0); + for (h = 0; h < height; h++) { + unsigned int c; + const t_vmem_elem *vp = from; + + for (c = 0; c < width; c += ISP_NWAY) { + load_vector(ID, &to[stride_to * h + c], vp); + vp = (t_vmem_elem *)((char *)vp + ISP_VEC_ALIGN); + } + from = (const t_vmem_elem *)((const char *)from + stride_from / ISP_NWAY * + ISP_VEC_ALIGN); + } +} + +void isp_vmem_2d_store( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from, + unsigned int height, + unsigned int width, + unsigned int stride_to, /* In t_vmem_elem */ + + unsigned stride_from /* In t_vmem_elem */) +{ + unsigned int h; + + assert(ID < N_ISP_ID); + assert((unsigned long)to % ISP_VEC_ALIGN == 0); + assert(width % ISP_NWAY == 0); + assert(stride_to % ISP_NWAY == 0); + for (h = 0; h < height; h++) { + unsigned int c; + t_vmem_elem *vp = to; + + for (c = 0; c < width; c += ISP_NWAY) { + store_vector(ID, vp, &from[stride_from * h + c]); + vp = (t_vmem_elem *)((char *)vp + ISP_VEC_ALIGN); + } + to = (t_vmem_elem *)((char *)to + stride_to / ISP_NWAY * ISP_VEC_ALIGN); + } +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem_local.h new file mode 100644 index 000000000..d0ba59ced --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem_local.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VMEM_LOCAL_H_INCLUDED__ +#define __VMEM_LOCAL_H_INCLUDED__ + +#include "type_support.h" +#include "vmem_global.h" + +typedef u16 t_vmem_elem; + +#define VMEM_ARRAY(x, s) t_vmem_elem x[s / ISP_NWAY][ISP_NWAY] + +void isp_vmem_load( + const isp_ID_t ID, + const t_vmem_elem *from, + t_vmem_elem *to, + unsigned int elems); /* In t_vmem_elem */ + +void isp_vmem_store( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from, + unsigned int elems); /* In t_vmem_elem */ + +void isp_vmem_2d_load( + const isp_ID_t ID, + const t_vmem_elem *from, + t_vmem_elem *to, + unsigned int height, + unsigned int width, + unsigned int stride_to, /* In t_vmem_elem */ + + unsigned stride_from /* In t_vmem_elem */); + +void isp_vmem_2d_store( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from, + unsigned int height, + unsigned int width, + unsigned int stride_to, /* In t_vmem_elem */ + + unsigned stride_from /* In t_vmem_elem */); + +#endif /* __VMEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem_private.h new file mode 100644 index 000000000..39cf1316b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem_private.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VMEM_PRIVATE_H_INCLUDED__ +#define __VMEM_PRIVATE_H_INCLUDED__ + +#include "vmem_public.h" + +#endif /* __VMEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/input_formatter_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/input_formatter_global.h new file mode 100644 index 000000000..605cf02e5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/input_formatter_global.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_FORMATTER_GLOBAL_H_INCLUDED__ +#define __INPUT_FORMATTER_GLOBAL_H_INCLUDED__ + +#define IS_INPUT_FORMATTER_VERSION2 +#define IS_INPUT_SWITCH_VERSION2 + +#include +#include +#include "if_defs.h" +#include "str2mem_defs.h" +#include "input_switch_2400_defs.h" + +#define _HIVE_INPUT_SWITCH_GET_FSYNC_REG_LSB(ch_id) ((ch_id) * 3) + +#define HIVE_SWITCH_N_CHANNELS 4 +#define HIVE_SWITCH_N_FORMATTYPES 32 +#define HIVE_SWITCH_N_SWITCH_CODE 4 +#define HIVE_SWITCH_M_CHANNELS 0x00000003 +#define HIVE_SWITCH_M_FORMATTYPES 0x0000001f +#define HIVE_SWITCH_M_SWITCH_CODE 0x00000003 +#define HIVE_SWITCH_M_FSYNC 0x00000007 + +#define HIVE_SWITCH_ENCODE_FSYNC(x) \ + (1U << (((x) - 1) & HIVE_SWITCH_M_CHANNELS)) + +#define _HIVE_INPUT_SWITCH_GET_LUT_FIELD(reg, bit_index) \ + (((reg) >> (bit_index)) & HIVE_SWITCH_M_SWITCH_CODE) +#define _HIVE_INPUT_SWITCH_SET_LUT_FIELD(reg, bit_index, val) \ + (((reg) & ~(HIVE_SWITCH_M_SWITCH_CODE << (bit_index))) | (((hrt_data)(val) & HIVE_SWITCH_M_SWITCH_CODE) << (bit_index))) +#define _HIVE_INPUT_SWITCH_GET_FSYNC_FIELD(reg, bit_index) \ + (((reg) >> (bit_index)) & HIVE_SWITCH_M_FSYNC) +#define _HIVE_INPUT_SWITCH_SET_FSYNC_FIELD(reg, bit_index, val) \ + (((reg) & ~(HIVE_SWITCH_M_FSYNC << (bit_index))) | (((hrt_data)(val) & HIVE_SWITCH_M_FSYNC) << (bit_index))) + +typedef struct input_formatter_cfg_s input_formatter_cfg_t; + +/* Hardware registers */ +/*#define HIVE_IF_RESET_ADDRESS 0x000*/ /* deprecated */ +#define HIVE_IF_START_LINE_ADDRESS 0x004 +#define HIVE_IF_START_COLUMN_ADDRESS 0x008 +#define HIVE_IF_CROPPED_HEIGHT_ADDRESS 0x00C +#define HIVE_IF_CROPPED_WIDTH_ADDRESS 0x010 +#define HIVE_IF_VERTICAL_DECIMATION_ADDRESS 0x014 +#define HIVE_IF_HORIZONTAL_DECIMATION_ADDRESS 0x018 +#define HIVE_IF_H_DEINTERLEAVING_ADDRESS 0x01C +#define HIVE_IF_LEFTPADDING_WIDTH_ADDRESS 0x020 +#define HIVE_IF_END_OF_LINE_OFFSET_ADDRESS 0x024 +#define HIVE_IF_VMEM_START_ADDRESS_ADDRESS 0x028 +#define HIVE_IF_VMEM_END_ADDRESS_ADDRESS 0x02C +#define HIVE_IF_VMEM_INCREMENT_ADDRESS 0x030 +#define HIVE_IF_YUV_420_FORMAT_ADDRESS 0x034 +#define HIVE_IF_VSYNCK_ACTIVE_LOW_ADDRESS 0x038 +#define HIVE_IF_HSYNCK_ACTIVE_LOW_ADDRESS 0x03C +#define HIVE_IF_ALLOW_FIFO_OVERFLOW_ADDRESS 0x040 +#define HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS 0x044 +#define HIVE_IF_V_DEINTERLEAVING_ADDRESS 0x048 +#define HIVE_IF_FSM_CROP_PIXEL_COUNTER 0x110 +#define HIVE_IF_FSM_CROP_LINE_COUNTER 0x10C +#define HIVE_IF_FSM_CROP_STATUS 0x108 + +/* Registers only for simulation */ +#define HIVE_IF_CRUN_MODE_ADDRESS 0x04C +#define HIVE_IF_DUMP_OUTPUT_ADDRESS 0x050 + +/* Follow the DMA syntax, "cmd" last */ +#define IF_PACK(val, cmd) ((val & 0x0fff) | (cmd /*& 0xf000*/)) + +#define HIVE_STR2MEM_SOFT_RESET_REG_ADDRESS (_STR2MEM_SOFT_RESET_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_INPUT_ENDIANNESS_REG_ADDRESS (_STR2MEM_INPUT_ENDIANNESS_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_OUTPUT_ENDIANNESS_REG_ADDRESS (_STR2MEM_OUTPUT_ENDIANNESS_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_BIT_SWAPPING_REG_ADDRESS (_STR2MEM_BIT_SWAPPING_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_BLOCK_SYNC_LEVEL_REG_ADDRESS (_STR2MEM_BLOCK_SYNC_LEVEL_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_PACKET_SYNC_LEVEL_REG_ADDRESS (_STR2MEM_PACKET_SYNC_LEVEL_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ADDRESS (_STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ADDRESS (_STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_EN_STAT_UPDATE_ADDRESS (_STR2MEM_EN_STAT_UPDATE_ID * _STR2MEM_REG_ALIGN) + +/* + * This data structure is shared between host and SP + */ +struct input_formatter_cfg_s { + u32 start_line; + u32 start_column; + u32 left_padding; + u32 cropped_height; + u32 cropped_width; + u32 deinterleaving; + u32 buf_vecs; + u32 buf_start_index; + u32 buf_increment; + u32 buf_eol_offset; + u32 is_yuv420_format; + u32 block_no_reqs; +}; + +extern const hrt_address HIVE_IF_SRST_ADDRESS[N_INPUT_FORMATTER_ID]; +extern const hrt_data HIVE_IF_SRST_MASK[N_INPUT_FORMATTER_ID]; +extern const u8 HIVE_IF_SWITCH_CODE[N_INPUT_FORMATTER_ID]; + +#endif /* __INPUT_FORMATTER_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/irq_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/irq_global.h new file mode 100644 index 000000000..4a1dea6df --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/irq_global.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IRQ_GLOBAL_H_INCLUDED__ +#define __IRQ_GLOBAL_H_INCLUDED__ + +#include + +#define IS_IRQ_VERSION_2 +#define IS_IRQ_MAP_VERSION_2 + +/* We cannot include the (hrt host ID) file defining the "CSS_RECEIVER" property without side effects */ +#ifndef HAS_NO_RX +#include "irq_types_hrt.h" +#endif + +/* The IRQ is not mapped uniformly on its related interfaces */ +#define IRQ_SW_CHANNEL_OFFSET hrt_isp_css_irq_sw_pin_0 + +typedef enum { + IRQ_SW_CHANNEL0_ID = hrt_isp_css_irq_sw_pin_0 - IRQ_SW_CHANNEL_OFFSET, + IRQ_SW_CHANNEL1_ID = hrt_isp_css_irq_sw_pin_1 - IRQ_SW_CHANNEL_OFFSET, + N_IRQ_SW_CHANNEL_ID +} irq_sw_channel_id_t; + +#endif /* __IRQ_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/isp_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/isp_global.h new file mode 100644 index 000000000..5c6891c9b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/isp_global.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_GLOBAL_H_INCLUDED__ +#define __ISP_GLOBAL_H_INCLUDED__ + +#include + +#include "mamoiada_params.h" + +#define ISP_PMEM_WIDTH_LOG2 ISP_LOG2_PMEM_WIDTH +#define ISP_PMEM_SIZE ISP_PMEM_DEPTH + +#define ISP_NWAY_LOG2 6 +#define ISP_VEC_NELEMS_LOG2 ISP_NWAY_LOG2 + +#ifdef PIPE_GENERATION +#define PIPEMEM(x) MEM(x) +#define ISP_NWAY BIT(ISP_NWAY_LOG2) +#else +#define PIPEMEM(x) +#endif + +/* The number of data bytes in a vector disregarding the reduced precision */ +#define ISP_VEC_BYTES (ISP_VEC_NELEMS * sizeof(uint16_t)) + +/* ISP SC Registers */ +#define ISP_SC_REG 0x00 +#define ISP_PC_REG 0x07 +#define ISP_IRQ_READY_REG 0x00 +#define ISP_IRQ_CLEAR_REG 0x00 + +/* ISP SC Register bits */ +#define ISP_RST_BIT 0x00 +#define ISP_START_BIT 0x01 +#define ISP_BREAK_BIT 0x02 +#define ISP_RUN_BIT 0x03 +#define ISP_BROKEN_BIT 0x04 +#define ISP_IDLE_BIT 0x05 /* READY */ +#define ISP_SLEEPING_BIT 0x06 +#define ISP_STALLING_BIT 0x07 +#define ISP_IRQ_CLEAR_BIT 0x08 +#define ISP_IRQ_READY_BIT 0x0A +#define ISP_IRQ_SLEEPING_BIT 0x0B + +/* ISP Register bits */ +#define ISP_CTRL_SINK_BIT 0x00 +#define ISP_PMEM_SINK_BIT 0x01 +#define ISP_DMEM_SINK_BIT 0x02 +#define ISP_FIFO0_SINK_BIT 0x03 +#define ISP_FIFO1_SINK_BIT 0x04 +#define ISP_FIFO2_SINK_BIT 0x05 +#define ISP_FIFO3_SINK_BIT 0x06 +#define ISP_FIFO4_SINK_BIT 0x07 +#define ISP_FIFO5_SINK_BIT 0x08 +#define ISP_FIFO6_SINK_BIT 0x09 +#define ISP_VMEM_SINK_BIT 0x0A +#define ISP_VAMEM1_SINK_BIT 0x0B +#define ISP_VAMEM2_SINK_BIT 0x0C +#define ISP_VAMEM3_SINK_BIT 0x0D +#define ISP_HMEM_SINK_BIT 0x0E + +#define ISP_CTRL_SINK_REG 0x08 +#define ISP_PMEM_SINK_REG 0x08 +#define ISP_DMEM_SINK_REG 0x08 +#define ISP_FIFO0_SINK_REG 0x08 +#define ISP_FIFO1_SINK_REG 0x08 +#define ISP_FIFO2_SINK_REG 0x08 +#define ISP_FIFO3_SINK_REG 0x08 +#define ISP_FIFO4_SINK_REG 0x08 +#define ISP_FIFO5_SINK_REG 0x08 +#define ISP_FIFO6_SINK_REG 0x08 +#define ISP_VMEM_SINK_REG 0x08 +#define ISP_VAMEM1_SINK_REG 0x08 +#define ISP_VAMEM2_SINK_REG 0x08 +#define ISP_VAMEM3_SINK_REG 0x08 +#define ISP_HMEM_SINK_REG 0x08 + +/* ISP2401 */ +#define BAMEM VMEM +#define XNR3_DOWN_BAMEM_BASE_ADDRESS (0x16880) +#define XNR3_UP_BAMEM_BASE_ADDRESS (0x12880) +#define bmem_ldrow(fu, pid, offset, data) bmem_ldrow_s(fu, pid, offset, data) +#define bmem_strow(fu, pid, offset, data) bmem_strow_s(fu, pid, offset, data) +#define bmem_ldblk(fu, pid, offset, data) bmem_ldblk_s(fu, pid, offset, data) +#define bmem_stblk(fu, pid, offset, data) bmem_stblk_s(fu, pid, offset, data) + +#endif /* __ISP_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/mmu_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/mmu_global.h new file mode 100644 index 000000000..8738fed6a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/mmu_global.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MMU_GLOBAL_H_INCLUDED__ +#define __MMU_GLOBAL_H_INCLUDED__ + +#define IS_MMU_VERSION_2 + +#include + +#endif /* __MMU_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/sp_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/sp_global.h new file mode 100644 index 000000000..b8338f9b5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/sp_global.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_GLOBAL_H_INCLUDED__ +#define __SP_GLOBAL_H_INCLUDED__ + +#include + +#include + +#define SP_PMEM_WIDTH_LOG2 SP_PMEM_LOG_WIDTH_BITS +#define SP_PMEM_SIZE SP_PMEM_DEPTH + +#define SP_DMEM_SIZE 0x4000 + +/* SP Registers */ +#define SP_PC_REG 0x09 +#define SP_SC_REG 0x00 +#define SP_START_ADDR_REG 0x01 +#define SP_ICACHE_ADDR_REG 0x05 +#define SP_IRQ_READY_REG 0x00 +#define SP_IRQ_CLEAR_REG 0x00 +#define SP_ICACHE_INV_REG 0x00 +#define SP_CTRL_SINK_REG 0x0A + +/* SP Register bits */ +#define SP_RST_BIT 0x00 +#define SP_START_BIT 0x01 +#define SP_BREAK_BIT 0x02 +#define SP_RUN_BIT 0x03 +#define SP_BROKEN_BIT 0x04 +#define SP_IDLE_BIT 0x05 /* READY */ +#define SP_SLEEPING_BIT 0x06 +#define SP_STALLING_BIT 0x07 +#define SP_IRQ_CLEAR_BIT 0x08 +#define SP_IRQ_READY_BIT 0x0A +#define SP_IRQ_SLEEPING_BIT 0x0B + +#define SP_ICACHE_INV_BIT 0x0C +#define SP_IPREFETCH_EN_BIT 0x0D + +#define SP_FIFO0_SINK_BIT 0x00 +#define SP_FIFO1_SINK_BIT 0x01 +#define SP_FIFO2_SINK_BIT 0x02 +#define SP_FIFO3_SINK_BIT 0x03 +#define SP_FIFO4_SINK_BIT 0x04 +#define SP_FIFO5_SINK_BIT 0x05 +#define SP_FIFO6_SINK_BIT 0x06 +#define SP_FIFO7_SINK_BIT 0x07 +#define SP_FIFO8_SINK_BIT 0x08 +#define SP_FIFO9_SINK_BIT 0x09 +#define SP_FIFOA_SINK_BIT 0x0A +#define SP_DMEM_SINK_BIT 0x0B +#define SP_CTRL_MT_SINK_BIT 0x0C +#define SP_ICACHE_MT_SINK_BIT 0x0D + +#define SP_FIFO0_SINK_REG 0x0A +#define SP_FIFO1_SINK_REG 0x0A +#define SP_FIFO2_SINK_REG 0x0A +#define SP_FIFO3_SINK_REG 0x0A +#define SP_FIFO4_SINK_REG 0x0A +#define SP_FIFO5_SINK_REG 0x0A +#define SP_FIFO6_SINK_REG 0x0A +#define SP_FIFO7_SINK_REG 0x0A +#define SP_FIFO8_SINK_REG 0x0A +#define SP_FIFO9_SINK_REG 0x0A +#define SP_FIFOA_SINK_REG 0x0A +#define SP_DMEM_SINK_REG 0x0A +#define SP_CTRL_MT_SINK_REG 0x0A +#define SP_ICACHE_MT_SINK_REG 0x0A + +#endif /* __SP_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/timed_ctrl_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/timed_ctrl_global.h new file mode 100644 index 000000000..3f2915a78 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/timed_ctrl_global.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TIMED_CTRL_GLOBAL_H_INCLUDED__ +#define __TIMED_CTRL_GLOBAL_H_INCLUDED__ + +#define IS_TIMED_CTRL_VERSION_1 + +#include "timed_controller_defs.h" + +/** + * Order of the input bits for the timed controller taken from + * ISP_CSS_2401 System Architecture Description valid for + * 2400, 2401. + * + * Check for other systems. + */ +#define HIVE_TIMED_CTRL_GPIO_PIN_0_BIT_ID 0 +#define HIVE_TIMED_CTRL_GPIO_PIN_1_BIT_ID 1 +#define HIVE_TIMED_CTRL_GPIO_PIN_2_BIT_ID 2 +#define HIVE_TIMED_CTRL_GPIO_PIN_3_BIT_ID 3 +#define HIVE_TIMED_CTRL_GPIO_PIN_4_BIT_ID 4 +#define HIVE_TIMED_CTRL_GPIO_PIN_5_BIT_ID 5 +#define HIVE_TIMED_CTRL_GPIO_PIN_6_BIT_ID 6 +#define HIVE_TIMED_CTRL_GPIO_PIN_7_BIT_ID 7 +#define HIVE_TIMED_CTRL_GPIO_PIN_8_BIT_ID 8 +#define HIVE_TIMED_CTRL_GPIO_PIN_9_BIT_ID 9 +#define HIVE_TIMED_CTRL_GPIO_PIN_10_BIT_ID 10 +#define HIVE_TIMED_CTRL_GPIO_PIN_11_BIT_ID 11 +#define HIVE_TIMED_CTRL_IRQ_SP_BIT_ID 12 +#define HIVE_TIMED_CTRL_IRQ_ISP_BIT_ID 13 +#define HIVE_TIMED_CTRL_IRQ_INPUT_SYSTEM_BIT_ID 14 +#define HIVE_TIMED_CTRL_IRQ_INPUT_SELECTOR_BIT_ID 15 +#define HIVE_TIMED_CTRL_IRQ_IF_BLOCK_BIT_ID 16 +#define HIVE_TIMED_CTRL_IRQ_GP_TIMER_0_BIT_ID 17 +#define HIVE_TIMED_CTRL_IRQ_GP_TIMER_1_BIT_ID 18 +#define HIVE_TIMED_CTRL_CSI_SOL_BIT_ID 19 +#define HIVE_TIMED_CTRL_CSI_EOL_BIT_ID 20 +#define HIVE_TIMED_CTRL_CSI_SOF_BIT_ID 21 +#define HIVE_TIMED_CTRL_CSI_EOF_BIT_ID 22 +#define HIVE_TIMED_CTRL_IRQ_IS_STREAMING_MONITOR_BIT_ID 23 + +#endif /* __TIMED_CTRL_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/vamem_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/vamem_global.h new file mode 100644 index 000000000..0d290e815 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/vamem_global.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VAMEM_GLOBAL_H_INCLUDED__ +#define __VAMEM_GLOBAL_H_INCLUDED__ + +#include + +#define IS_VAMEM_VERSION_2 + +/* (log) stepsize of linear interpolation */ +#define VAMEM_INTERP_STEP_LOG2 4 +#define VAMEM_INTERP_STEP BIT(VAMEM_INTERP_STEP_LOG2) +/* (physical) size of the tables */ +#define VAMEM_TABLE_UNIT_SIZE ((1 << (ISP_VAMEM_ADDRESS_BITS - VAMEM_INTERP_STEP_LOG2)) + 1) +/* (logical) size of the tables */ +#define VAMEM_TABLE_UNIT_STEP ((VAMEM_TABLE_UNIT_SIZE - 1) << 1) +/* Number of tables */ +#define VAMEM_TABLE_UNIT_COUNT (ISP_VAMEM_DEPTH / VAMEM_TABLE_UNIT_STEP) + +typedef u16 vamem_data_t; + +#endif /* __VAMEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/vmem_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_common/vmem_global.h new file mode 100644 index 000000000..537b07421 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/vmem_global.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VMEM_GLOBAL_H_INCLUDED__ +#define __VMEM_GLOBAL_H_INCLUDED__ + +#include "isp.h" + +#define VMEM_SIZE ISP_VMEM_DEPTH +#define VMEM_ELEMBITS ISP_VMEM_ELEMBITS +#define VMEM_ALIGN ISP_VMEM_ALIGN + +#ifndef PIPE_GENERATION +typedef tvector *pvector; +#endif + +#endif /* __VMEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_defs.h b/drivers/staging/media/atomisp/pci/hive_isp_css_defs.h new file mode 100644 index 000000000..e9cf27438 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_defs.h @@ -0,0 +1,412 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_defs_h__ +#define _hive_isp_css_defs_h__ + +#define HIVE_ISP_CTRL_DATA_WIDTH 32 +#define HIVE_ISP_CTRL_ADDRESS_WIDTH 32 +#define HIVE_ISP_CTRL_MAX_BURST_SIZE 1 +#define HIVE_ISP_DDR_ADDRESS_WIDTH 36 + +#define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */ +#define HIVE_ISP_NUM_GPIO_PINS 12 + +/* This list of vector num_elems/elem_bits pairs is valid both in C as initializer + and in the DMA parameter list */ +#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}} +#define HIVE_ISP_DDR_WORD_BITS 256 +#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS / 8) +#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) /* hss only */ +#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) /* RTL only */ +#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8) +#define HIVE_ISP_PAGE_SHIFT 12 +#define HIVE_ISP_PAGE_SIZE BIT(HIVE_ISP_PAGE_SHIFT) + +#define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS +#define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES + +/* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where */ +/* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */ +#define HIVE_ISP_DDR_BASE_OFFSET 0x120000000 /* 0x200000 */ + +#define HIVE_DMA_ISP_BUS_CONN 0 +#define HIVE_DMA_ISP_DDR_CONN 1 +#define HIVE_DMA_BUS_DDR_CONN 2 +#define HIVE_DMA_ISP_MASTER master_port0 +#define HIVE_DMA_BUS_MASTER master_port1 +#define HIVE_DMA_DDR_MASTER master_port2 + +#define HIVE_DMA_NUM_CHANNELS 32 /* old value was 8 */ +#define HIVE_DMA_CMD_FIFO_DEPTH 24 /* old value was 12 */ + +#define HIVE_IF_PIXEL_WIDTH 12 + +#define HIVE_MMU_TLB_SETS 8 +#define HIVE_MMU_TLB_SET_BLOCKS 8 +#define HIVE_MMU_TLB_BLOCK_ELEMENTS 8 +#define HIVE_MMU_PAGE_TABLE_LEVELS 2 +#define HIVE_MMU_PAGE_BYTES HIVE_ISP_PAGE_SIZE + +#define HIVE_ISP_CH_ID_BITS 2 +#define HIVE_ISP_FMT_TYPE_BITS 5 +#define HIVE_ISP_ISEL_SEL_BITS 2 + +#define HIVE_GP_REGS_SDRAM_WAKEUP_IDX 0 +#define HIVE_GP_REGS_IDLE_IDX 1 +#define HIVE_GP_REGS_IRQ_0_IDX 2 +#define HIVE_GP_REGS_IRQ_1_IDX 3 +#define HIVE_GP_REGS_SP_STREAM_STAT_IDX 4 +#define HIVE_GP_REGS_SP_STREAM_STAT_B_IDX 5 +#define HIVE_GP_REGS_ISP_STREAM_STAT_IDX 6 +#define HIVE_GP_REGS_MOD_STREAM_STAT_IDX 7 +#define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_COND_IDX 8 +#define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_COND_IDX 9 +#define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_COND_IDX 10 +#define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_COND_IDX 11 +#define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_ENABLE_IDX 12 +#define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_ENABLE_IDX 13 +#define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_ENABLE_IDX 14 +#define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_ENABLE_IDX 15 +#define HIVE_GP_REGS_SWITCH_PRIM_IF_IDX 16 +#define HIVE_GP_REGS_SWITCH_GDC1_IDX 17 +#define HIVE_GP_REGS_SWITCH_GDC2_IDX 18 +#define HIVE_GP_REGS_SRST_IDX 19 +#define HIVE_GP_REGS_SLV_REG_SRST_IDX 20 + +/* Bit numbers of the soft reset register */ +#define HIVE_GP_REGS_SRST_ISYS_CBUS 0 +#define HIVE_GP_REGS_SRST_ISEL_CBUS 1 +#define HIVE_GP_REGS_SRST_IFMT_CBUS 2 +#define HIVE_GP_REGS_SRST_GPDEV_CBUS 3 +#define HIVE_GP_REGS_SRST_GPIO 4 +#define HIVE_GP_REGS_SRST_TC 5 +#define HIVE_GP_REGS_SRST_GPTIMER 6 +#define HIVE_GP_REGS_SRST_FACELLFIFOS 7 +#define HIVE_GP_REGS_SRST_D_OSYS 8 +#define HIVE_GP_REGS_SRST_IFT_SEC_PIPE 9 +#define HIVE_GP_REGS_SRST_GDC1 10 +#define HIVE_GP_REGS_SRST_GDC2 11 +#define HIVE_GP_REGS_SRST_VEC_BUS 12 +#define HIVE_GP_REGS_SRST_ISP 13 +#define HIVE_GP_REGS_SRST_SLV_GRP_BUS 14 +#define HIVE_GP_REGS_SRST_DMA 15 +#define HIVE_GP_REGS_SRST_SF_ISP_SP 16 +#define HIVE_GP_REGS_SRST_SF_PIF_CELLS 17 +#define HIVE_GP_REGS_SRST_SF_SIF_SP 18 +#define HIVE_GP_REGS_SRST_SF_MC_SP 19 +#define HIVE_GP_REGS_SRST_SF_ISYS_SP 20 +#define HIVE_GP_REGS_SRST_SF_DMA_CELLS 21 +#define HIVE_GP_REGS_SRST_SF_GDC1_CELLS 22 +#define HIVE_GP_REGS_SRST_SF_GDC2_CELLS 23 +#define HIVE_GP_REGS_SRST_SP 24 +#define HIVE_GP_REGS_SRST_OCP2CIO 25 +#define HIVE_GP_REGS_SRST_NBUS 26 +#define HIVE_GP_REGS_SRST_HOST12BUS 27 +#define HIVE_GP_REGS_SRST_WBUS 28 +#define HIVE_GP_REGS_SRST_IC_OSYS 29 +#define HIVE_GP_REGS_SRST_WBUS_IC 30 + +/* Bit numbers of the slave register soft reset register */ +#define HIVE_GP_REGS_SLV_REG_SRST_DMA 0 +#define HIVE_GP_REGS_SLV_REG_SRST_GDC1 1 +#define HIVE_GP_REGS_SLV_REG_SRST_GDC2 2 + +/* order of the input bits for the irq controller */ +#define HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID 0 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID 1 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID 2 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID 3 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID 4 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID 5 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID 6 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID 7 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID 8 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID 9 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID 10 +#define HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID 11 +#define HIVE_GP_DEV_IRQ_SP_BIT_ID 12 +#define HIVE_GP_DEV_IRQ_ISP_BIT_ID 13 +#define HIVE_GP_DEV_IRQ_ISYS_BIT_ID 14 +#define HIVE_GP_DEV_IRQ_ISEL_BIT_ID 15 +#define HIVE_GP_DEV_IRQ_IFMT_BIT_ID 16 +#define HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID 17 +#define HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID 18 +#define HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID 19 +#define HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID 20 +#define HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID 21 +#define HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID 22 +#define HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID 23 +#define HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID 24 +#define HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID 25 +#define HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID 26 +#define HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID 27 +#define HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID 28 +#define HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID 29 +#define HIVE_GP_DEV_IRQ_DMA_BIT_ID 30 +#define HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID 31 + +#define HIVE_GP_REGS_NUM_SW_IRQ_REGS 2 + +/* order of the input bits for the timed controller */ +#define HIVE_GP_DEV_TC_GPIO_PIN_0_BIT_ID 0 +#define HIVE_GP_DEV_TC_GPIO_PIN_1_BIT_ID 1 +#define HIVE_GP_DEV_TC_GPIO_PIN_2_BIT_ID 2 +#define HIVE_GP_DEV_TC_GPIO_PIN_3_BIT_ID 3 +#define HIVE_GP_DEV_TC_GPIO_PIN_4_BIT_ID 4 +#define HIVE_GP_DEV_TC_GPIO_PIN_5_BIT_ID 5 +#define HIVE_GP_DEV_TC_GPIO_PIN_6_BIT_ID 6 +#define HIVE_GP_DEV_TC_GPIO_PIN_7_BIT_ID 7 +#define HIVE_GP_DEV_TC_GPIO_PIN_8_BIT_ID 8 +#define HIVE_GP_DEV_TC_GPIO_PIN_9_BIT_ID 9 +#define HIVE_GP_DEV_TC_GPIO_PIN_10_BIT_ID 10 +#define HIVE_GP_DEV_TC_GPIO_PIN_11_BIT_ID 11 +#define HIVE_GP_DEV_TC_SP_BIT_ID 12 +#define HIVE_GP_DEV_TC_ISP_BIT_ID 13 +#define HIVE_GP_DEV_TC_ISYS_BIT_ID 14 +#define HIVE_GP_DEV_TC_ISEL_BIT_ID 15 +#define HIVE_GP_DEV_TC_IFMT_BIT_ID 16 +#define HIVE_GP_DEV_TC_GP_TIMER_0_BIT_ID 17 +#define HIVE_GP_DEV_TC_GP_TIMER_1_BIT_ID 18 +#define HIVE_GP_DEV_TC_MIPI_SOL_BIT_ID 19 +#define HIVE_GP_DEV_TC_MIPI_EOL_BIT_ID 20 +#define HIVE_GP_DEV_TC_MIPI_SOF_BIT_ID 21 +#define HIVE_GP_DEV_TC_MIPI_EOF_BIT_ID 22 +#define HIVE_GP_DEV_TC_INPSYS_SM 23 + +/* definitions for the gp_timer block */ +#define HIVE_GP_TIMER_0 0 +#define HIVE_GP_TIMER_1 1 +#define HIVE_GP_TIMER_2 2 +#define HIVE_GP_TIMER_3 3 +#define HIVE_GP_TIMER_4 4 +#define HIVE_GP_TIMER_5 5 +#define HIVE_GP_TIMER_6 6 +#define HIVE_GP_TIMER_7 7 +#define HIVE_GP_TIMER_NUM_COUNTERS 8 + +#define HIVE_GP_TIMER_IRQ_0 0 +#define HIVE_GP_TIMER_IRQ_1 1 +#define HIVE_GP_TIMER_NUM_IRQS 2 + +#define HIVE_GP_TIMER_GPIO_0_BIT_ID 0 +#define HIVE_GP_TIMER_GPIO_1_BIT_ID 1 +#define HIVE_GP_TIMER_GPIO_2_BIT_ID 2 +#define HIVE_GP_TIMER_GPIO_3_BIT_ID 3 +#define HIVE_GP_TIMER_GPIO_4_BIT_ID 4 +#define HIVE_GP_TIMER_GPIO_5_BIT_ID 5 +#define HIVE_GP_TIMER_GPIO_6_BIT_ID 6 +#define HIVE_GP_TIMER_GPIO_7_BIT_ID 7 +#define HIVE_GP_TIMER_GPIO_8_BIT_ID 8 +#define HIVE_GP_TIMER_GPIO_9_BIT_ID 9 +#define HIVE_GP_TIMER_GPIO_10_BIT_ID 10 +#define HIVE_GP_TIMER_GPIO_11_BIT_ID 11 +#define HIVE_GP_TIMER_INP_SYS_IRQ 12 +#define HIVE_GP_TIMER_ISEL_IRQ 13 +#define HIVE_GP_TIMER_IFMT_IRQ 14 +#define HIVE_GP_TIMER_SP_STRMON_IRQ 15 +#define HIVE_GP_TIMER_SP_B_STRMON_IRQ 16 +#define HIVE_GP_TIMER_ISP_STRMON_IRQ 17 +#define HIVE_GP_TIMER_MOD_STRMON_IRQ 18 +#define HIVE_GP_TIMER_ISP_BAMEM_ERROR_IRQ 20 +#define HIVE_GP_TIMER_ISP_DMEM_ERROR_IRQ 21 +#define HIVE_GP_TIMER_SP_ICACHE_MEM_ERROR_IRQ 22 +#define HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ 23 +#define HIVE_GP_TIMER_SP_OUT_RUN_DP 24 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 25 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 26 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I2 27 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I3 28 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I4 29 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I5 30 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I6 31 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I7 32 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I8 33 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I9 34 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I10 35 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 36 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 37 +#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 38 +#define HIVE_GP_TIMER_ISP_OUT_RUN_DP 39 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 40 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 41 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 42 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 43 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I1 44 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I2 45 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I3 46 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I4 47 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I5 48 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I6 49 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 50 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53 +#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54 +#define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55 +#define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56 +#define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57 +#define HIVE_GP_TIMER_MIPI_EOF_BIT_ID 58 +#define HIVE_GP_TIMER_INPSYS_SM 59 + +/* port definitions for the streaming monitors */ +/* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */ +#define SP_STR_MON_PORT_SP2SIF 0 +#define SP_STR_MON_PORT_SIF2SP 1 +#define SP_STR_MON_PORT_SP2MC 2 +#define SP_STR_MON_PORT_MC2SP 3 +#define SP_STR_MON_PORT_SP2DMA 4 +#define SP_STR_MON_PORT_DMA2SP 5 +#define SP_STR_MON_PORT_SP2ISP 6 +#define SP_STR_MON_PORT_ISP2SP 7 +#define SP_STR_MON_PORT_SP2GPD 8 +#define SP_STR_MON_PORT_FA2SP 9 +#define SP_STR_MON_PORT_SP2ISYS 10 +#define SP_STR_MON_PORT_ISYS2SP 11 +#define SP_STR_MON_PORT_SP2PIFA 12 +#define SP_STR_MON_PORT_PIFA2SP 13 +#define SP_STR_MON_PORT_SP2PIFB 14 +#define SP_STR_MON_PORT_PIFB2SP 15 + +#define SP_STR_MON_PORT_B_SP2GDC1 0 +#define SP_STR_MON_PORT_B_GDC12SP 1 +#define SP_STR_MON_PORT_B_SP2GDC2 2 +#define SP_STR_MON_PORT_B_GDC22SP 3 + +/* previously used SP streaming monitor port identifiers, kept for backward compatibility */ +#define SP_STR_MON_PORT_SND_SIF SP_STR_MON_PORT_SP2SIF +#define SP_STR_MON_PORT_RCV_SIF SP_STR_MON_PORT_SIF2SP +#define SP_STR_MON_PORT_SND_MC SP_STR_MON_PORT_SP2MC +#define SP_STR_MON_PORT_RCV_MC SP_STR_MON_PORT_MC2SP +#define SP_STR_MON_PORT_SND_DMA SP_STR_MON_PORT_SP2DMA +#define SP_STR_MON_PORT_RCV_DMA SP_STR_MON_PORT_DMA2SP +#define SP_STR_MON_PORT_SND_ISP SP_STR_MON_PORT_SP2ISP +#define SP_STR_MON_PORT_RCV_ISP SP_STR_MON_PORT_ISP2SP +#define SP_STR_MON_PORT_SND_GPD SP_STR_MON_PORT_SP2GPD +#define SP_STR_MON_PORT_RCV_GPD SP_STR_MON_PORT_FA2SP +/* Deprecated */ +#define SP_STR_MON_PORT_SND_PIF SP_STR_MON_PORT_SP2PIFA +#define SP_STR_MON_PORT_RCV_PIF SP_STR_MON_PORT_PIFA2SP +#define SP_STR_MON_PORT_SND_PIFB SP_STR_MON_PORT_SP2PIFB +#define SP_STR_MON_PORT_RCV_PIFB SP_STR_MON_PORT_PIFB2SP + +#define SP_STR_MON_PORT_SND_PIF_A SP_STR_MON_PORT_SP2PIFA +#define SP_STR_MON_PORT_RCV_PIF_A SP_STR_MON_PORT_PIFA2SP +#define SP_STR_MON_PORT_SND_PIF_B SP_STR_MON_PORT_SP2PIFB +#define SP_STR_MON_PORT_RCV_PIF_B SP_STR_MON_PORT_PIFB2SP + +/* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */ +#define ISP_STR_MON_PORT_ISP2PIFA 0 +#define ISP_STR_MON_PORT_PIFA2ISP 1 +#define ISP_STR_MON_PORT_ISP2PIFB 2 +#define ISP_STR_MON_PORT_PIFB2ISP 3 +#define ISP_STR_MON_PORT_ISP2DMA 4 +#define ISP_STR_MON_PORT_DMA2ISP 5 +#define ISP_STR_MON_PORT_ISP2GDC1 6 +#define ISP_STR_MON_PORT_GDC12ISP 7 +#define ISP_STR_MON_PORT_ISP2GDC2 8 +#define ISP_STR_MON_PORT_GDC22ISP 9 +#define ISP_STR_MON_PORT_ISP2GPD 10 +#define ISP_STR_MON_PORT_FA2ISP 11 +#define ISP_STR_MON_PORT_ISP2SP 12 +#define ISP_STR_MON_PORT_SP2ISP 13 + +/* previously used ISP streaming monitor port identifiers, kept for backward compatibility */ +#define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA +#define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP +#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB +#define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP +#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA +#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP +#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1 +#define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP +#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD +#define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP +#define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP +#define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP + +/* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */ + +#define MOD_STR_MON_PORT_PIFA2CELLS 0 +#define MOD_STR_MON_PORT_CELLS2PIFA 1 +#define MOD_STR_MON_PORT_PIFB2CELLS 2 +#define MOD_STR_MON_PORT_CELLS2PIFB 3 +#define MOD_STR_MON_PORT_SIF2SP 4 +#define MOD_STR_MON_PORT_SP2SIF 5 +#define MOD_STR_MON_PORT_MC2SP 6 +#define MOD_STR_MON_PORT_SP2MC 7 +#define MOD_STR_MON_PORT_DMA2ISP 8 +#define MOD_STR_MON_PORT_ISP2DMA 9 +#define MOD_STR_MON_PORT_DMA2SP 10 +#define MOD_STR_MON_PORT_SP2DMA 11 +#define MOD_STR_MON_PORT_GDC12CELLS 12 +#define MOD_STR_MON_PORT_CELLS2GDC1 13 +#define MOD_STR_MON_PORT_GDC22CELLS 14 +#define MOD_STR_MON_PORT_CELLS2GDC2 15 + +#define MOD_STR_MON_PORT_SND_PIF_A 0 +#define MOD_STR_MON_PORT_RCV_PIF_A 1 +#define MOD_STR_MON_PORT_SND_PIF_B 2 +#define MOD_STR_MON_PORT_RCV_PIF_B 3 +#define MOD_STR_MON_PORT_SND_SIF 4 +#define MOD_STR_MON_PORT_RCV_SIF 5 +#define MOD_STR_MON_PORT_SND_MC 6 +#define MOD_STR_MON_PORT_RCV_MC 7 +#define MOD_STR_MON_PORT_SND_DMA2ISP 8 +#define MOD_STR_MON_PORT_RCV_DMA_FR_ISP 9 +#define MOD_STR_MON_PORT_SND_DMA2SP 10 +#define MOD_STR_MON_PORT_RCV_DMA_FR_SP 11 +#define MOD_STR_MON_PORT_SND_GDC 12 +#define MOD_STR_MON_PORT_RCV_GDC 13 + +/* testbench signals: */ + +/* testbench GP adapter register ids */ +#define HIVE_TESTBENCH_GPIO_DATA_OUT_REG_IDX 0 +#define HIVE_TESTBENCH_GPIO_DIR_OUT_REG_IDX 1 +#define HIVE_TESTBENCH_IRQ_REG_IDX 2 +#define HIVE_TESTBENCH_SDRAM_WAKEUP_REG_IDX 3 +#define HIVE_TESTBENCH_IDLE_REG_IDX 4 +#define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5 +#define HIVE_TESTBENCH_MIPI_BFM_EN_REG_IDX 6 +#define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7 +#define HIVE_TESTBENCH_DDR_STALL_EN_REG_IDX 8 + +#define HIVE_TESTBENCH_ISP_PMEM_ERROR_IRQ_REG_IDX 9 +#define HIVE_TESTBENCH_ISP_BAMEM_ERROR_IRQ_REG_IDX 10 +#define HIVE_TESTBENCH_ISP_DMEM_ERROR_IRQ_REG_IDX 11 +#define HIVE_TESTBENCH_SP_ICACHE_MEM_ERROR_IRQ_REG_IDX 12 +#define HIVE_TESTBENCH_SP_DMEM_ERROR_IRQ_REG_IDX 13 + +/* Signal monitor input bit ids */ +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_O_BIT_ID 0 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_1_BIT_ID 1 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_2_BIT_ID 2 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_3_BIT_ID 3 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_4_BIT_ID 4 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_5_BIT_ID 5 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_6_BIT_ID 6 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_7_BIT_ID 7 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_8_BIT_ID 8 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_9_BIT_ID 9 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_10_BIT_ID 10 +#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_11_BIT_ID 11 +#define HIVE_TESTBENCH_SIG_MON_IRQ_PIN_BIT_ID 12 +#define HIVE_TESTBENCH_SIG_MON_SDRAM_WAKEUP_PIN_BIT_ID 13 +#define HIVE_TESTBENCH_SIG_MON_IDLE_PIN_BIT_ID 14 + +#define ISP2400_DEBUG_NETWORK 1 + +#endif /* _hive_isp_css_defs_h__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/assert_support.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/assert_support.h new file mode 100644 index 000000000..7382c0bbf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/assert_support.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ASSERT_SUPPORT_H_INCLUDED__ +#define __ASSERT_SUPPORT_H_INCLUDED__ + +/** + * The following macro can help to test the size of a struct at compile + * time rather than at run-time. It does not work for all compilers; see + * below. + * + * Depending on the value of 'condition', the following macro is expanded to: + * - condition==true: + * an expression containing an array declaration with negative size, + * usually resulting in a compilation error + * - condition==false: + * (void) 1; // C statement with no effect + * + * example: + * COMPILATION_ERROR_IF( sizeof(struct host_sp_queues) != SIZE_OF_HOST_SP_QUEUES_STRUCT); + * + * verify that the macro indeed triggers a compilation error with your compiler: + * COMPILATION_ERROR_IF( sizeof(struct host_sp_queues) != (sizeof(struct host_sp_queues)+1) ); + * + * Not all compilers will trigger an error with this macro; use a search engine to search for + * BUILD_BUG_ON to find other methods. + */ +#define COMPILATION_ERROR_IF(condition) ((void)sizeof(char[1 - 2 * !!(condition)])) + +/* Compile time assertion */ +#ifndef CT_ASSERT +#define CT_ASSERT(cnd) ((void)sizeof(char[(cnd) ? 1 : -1])) +#endif /* CT_ASSERT */ + +#include + +/* TODO: it would be cleaner to use this: + * #define assert(cnd) BUG_ON(cnd) + * but that causes many compiler warnings (==errors) under Android + * because it seems that the BUG_ON() macro is not seen as a check by + * gcc like the BUG() macro is. */ +#define assert(cnd) \ + do { \ + if (!(cnd)) \ + BUG(); \ + } while (0) + +#ifndef PIPE_GENERATION +/* Deprecated OP___assert, this is still used in ~1000 places + * in the code. This will be removed over time. + * The implementation for the pipe generation tool is in see support.isp.h */ +#define OP___assert(cnd) assert(cnd) + +static inline void compile_time_assert(unsigned int cond) +{ + /* Call undefined function if cond is false */ + void _compile_time_assert(void); + if (!cond) _compile_time_assert(); +} +#endif /* PIPE_GENERATION */ + +#endif /* __ASSERT_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/bitop_support.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/bitop_support.h new file mode 100644 index 000000000..29f14e900 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/bitop_support.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __BITOP_SUPPORT_H_INCLUDED__ +#define __BITOP_SUPPORT_H_INCLUDED__ + +#define bitop_setbit(a, b) ((a) |= (1UL << (b))) + +#define bitop_getbit(a, b) (((a) & (1UL << (b))) != 0) + +#define bitop_clearbit(a, b) ((a) &= ~(1UL << (b))) + +#endif /* __BITOP_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/csi_rx.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/csi_rx.h new file mode 100644 index 000000000..4602885d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/csi_rx.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_H_INCLUDED__ +#define __CSI_RX_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & + * inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "csi_rx_local.h" + +#ifndef __INLINE_CSI_RX__ +#include "csi_rx_public.h" +#else /* __INLINE_CSI_RX__ */ +#include "csi_rx_private.h" +#endif /* __INLINE_CSI_RX__ */ + +#endif /* __CSI_RX_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/debug.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/debug.h new file mode 100644 index 000000000..0f8195ba8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/debug.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DEBUG_H_INCLUDED__ +#define __DEBUG_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the DMA device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "system_local.h" +#include "debug_local.h" + +#ifndef __INLINE_DEBUG__ +#define STORAGE_CLASS_DEBUG_H extern +#define STORAGE_CLASS_DEBUG_C +#include "debug_public.h" +#else /* __INLINE_DEBUG__ */ +#define STORAGE_CLASS_DEBUG_H static inline +#define STORAGE_CLASS_DEBUG_C static inline +#include "debug_private.h" +#endif /* __INLINE_DEBUG__ */ + +#endif /* __DEBUG_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/device_access/device_access.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/device_access/device_access.h new file mode 100644 index 000000000..492f9e26c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/device_access/device_access.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __DEVICE_ACCESS_H_INCLUDED__ +#define __DEVICE_ACCESS_H_INCLUDED__ + +/*! + * \brief + * Define the public interface for physical system + * access functions to SRAM and registers. Access + * types are limited to those defined in + * All accesses are aligned + * + * The address representation is private to the system + * and represented as/stored in "hrt_address". + * + * The system global address can differ by an offset; + * The device base address. This offset must be added + * by the implementation of the access function + * + * "store" is a transfer to the device + * "load" is a transfer from the device + */ + +#include + +/* + * User provided file that defines the system address types: + * - hrt_address a type that can hold the (sub)system address range + */ +#include "system_local.h" +/* + * We cannot assume that the global system address size is the size of + * a pointer because a (say) 64-bit host can be simulated in a 32-bit + * environment. Only if the host environment is modelled as on the target + * we could use a pointer. Even then, prototyping may need to be done + * before the target environment is available. AS we cannot wait for that + * we are stuck with integer addresses + */ + +/*typedef char *sys_address;*/ +typedef hrt_address sys_address; + +/*! Set the (sub)system base address + + \param base_addr[in] The offset on which the (sub)system is located + in the global address map + + \return none, + */ +void device_set_base_address( + const sys_address base_addr); + +/*! Get the (sub)system base address + + \return base_address, + */ +sys_address device_get_base_address(void); + +/*! Read an 8-bit value from a device register or memory in the device + + \param addr[in] Local address + + \return device[addr] + */ +uint8_t ia_css_device_load_uint8( + const hrt_address addr); + +/*! Read a 16-bit value from a device register or memory in the device + + \param addr[in] Local address + + \return device[addr] + */ +uint16_t ia_css_device_load_uint16( + const hrt_address addr); + +/*! Read a 32-bit value from a device register or memory in the device + + \param addr[in] Local address + + \return device[addr] + */ +uint32_t ia_css_device_load_uint32( + const hrt_address addr); + +/*! Read a 64-bit value from a device register or memory in the device + + \param addr[in] Local address + + \return device[addr] + */ +uint64_t ia_css_device_load_uint64( + const hrt_address addr); + +/*! Write an 8-bit value to a device register or memory in the device + + \param addr[in] Local address + \param data[in] value + + \return none, device[addr] = value + */ +void ia_css_device_store_uint8( + const hrt_address addr, + const uint8_t data); + +/*! Write a 16-bit value to a device register or memory in the device + + \param addr[in] Local address + \param data[in] value + + \return none, device[addr] = value + */ +void ia_css_device_store_uint16( + const hrt_address addr, + const uint16_t data); + +/*! Write a 32-bit value to a device register or memory in the device + + \param addr[in] Local address + \param data[in] value + + \return none, device[addr] = value + */ +void ia_css_device_store_uint32( + const hrt_address addr, + const uint32_t data); + +/*! Write a 64-bit value to a device register or memory in the device + + \param addr[in] Local address + \param data[in] value + + \return none, device[addr] = value + */ +void ia_css_device_store_uint64( + const hrt_address addr, + const uint64_t data); + +/*! Read an array of bytes from device registers or memory in the device + + \param addr[in] Local address + \param data[out] pointer to the destination array + \param size[in] number of bytes to read + + \return none + */ +void ia_css_device_load( + const hrt_address addr, + void *data, + const size_t size); + +/*! Write an array of bytes to device registers or memory in the device + + \param addr[in] Local address + \param data[in] pointer to the source array + \param size[in] number of bytes to write + + \return none + */ +void ia_css_device_store( + const hrt_address addr, + const void *data, + const size_t size); + +#endif /* __DEVICE_ACCESS_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/dma.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/dma.h new file mode 100644 index 000000000..2f5ebfcd7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/dma.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_H_INCLUDED__ +#define __DMA_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the DMA device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "system_local.h" +#include "dma_local.h" + +#ifndef __INLINE_DMA__ +#define STORAGE_CLASS_DMA_H extern +#define STORAGE_CLASS_DMA_C +#include "dma_public.h" +#else /* __INLINE_DMA__ */ +#define STORAGE_CLASS_DMA_H static inline +#define STORAGE_CLASS_DMA_C static inline +#include "dma_private.h" +#endif /* __INLINE_DMA__ */ + +#endif /* __DMA_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/event_fifo.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/event_fifo.h new file mode 100644 index 000000000..0a085abd3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/event_fifo.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __EVENT_FIFO_H +#define __EVENT_FIFO_H + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the IRQ device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "event_fifo_local.h" + +#ifndef __INLINE_EVENT__ +#define STORAGE_CLASS_EVENT_H extern +#define STORAGE_CLASS_EVENT_C +#include "event_fifo_public.h" +#else /* __INLINE_EVENT__ */ +#define STORAGE_CLASS_EVENT_H static inline +#define STORAGE_CLASS_EVENT_C static inline +#include "event_fifo_private.h" +#endif /* __INLINE_EVENT__ */ + +#endif /* __EVENT_FIFO_H */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/fifo_monitor.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/fifo_monitor.h new file mode 100644 index 000000000..19a1bdd91 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/fifo_monitor.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_H_INCLUDED__ +#define __FIFO_MONITOR_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "fifo_monitor_local.h" + +#ifndef __INLINE_FIFO_MONITOR__ +#define STORAGE_CLASS_FIFO_MONITOR_H extern +#define STORAGE_CLASS_FIFO_MONITOR_C +#include "fifo_monitor_public.h" +#else /* __INLINE_FIFO_MONITOR__ */ +#define STORAGE_CLASS_FIFO_MONITOR_H static inline +#define STORAGE_CLASS_FIFO_MONITOR_C static inline +#include "fifo_monitor_private.h" +#endif /* __INLINE_FIFO_MONITOR__ */ + +#endif /* __FIFO_MONITOR_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/gdc_device.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/gdc_device.h new file mode 100644 index 000000000..4ed57fb45 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/gdc_device.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_DEVICE_H_INCLUDED__ +#define __GDC_DEVICE_H_INCLUDED__ + +/* The file gdc.h already exists */ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the GDC device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "gdc_local.h" + +#ifndef __INLINE_GDC__ +#define STORAGE_CLASS_GDC_H extern +#define STORAGE_CLASS_GDC_C +#include "gdc_public.h" +#else /* __INLINE_GDC__ */ +#define STORAGE_CLASS_GDC_H static inline +#define STORAGE_CLASS_GDC_C static inline +#include "gdc_private.h" +#endif /* __INLINE_GDC__ */ + +#endif /* __GDC_DEVICE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/gp_device.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/gp_device.h new file mode 100644 index 000000000..d122bdeae --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/gp_device.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_H_INCLUDED__ +#define __GP_DEVICE_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "gp_device_local.h" + +#ifndef __INLINE_GP_DEVICE__ +#define STORAGE_CLASS_GP_DEVICE_H extern +#define STORAGE_CLASS_GP_DEVICE_C +#include "gp_device_public.h" +#else /* __INLINE_GP_DEVICE__ */ +#define STORAGE_CLASS_GP_DEVICE_H static inline +#define STORAGE_CLASS_GP_DEVICE_C static inline +#include "gp_device_private.h" +#endif /* __INLINE_GP_DEVICE__ */ + +#endif /* __GP_DEVICE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/gp_timer.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/gp_timer.h new file mode 100644 index 000000000..0b7e92b96 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/gp_timer.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_H_INCLUDED__ +#define __GP_TIMER_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" /*GP_TIMER_BASE address */ +#include "gp_timer_local.h" /*GP_TIMER register offsets */ + +#ifndef __INLINE_GP_TIMER__ +#define STORAGE_CLASS_GP_TIMER_H extern +#define STORAGE_CLASS_GP_TIMER_C +#include "gp_timer_public.h" /* functions*/ +#else /* __INLINE_GP_TIMER__ */ +#define STORAGE_CLASS_GP_TIMER_H static inline +#define STORAGE_CLASS_GP_TIMER_C static inline +#include "gp_timer_private.h" /* inline functions*/ +#endif /* __INLINE_GP_TIMER__ */ + +#endif /* __GP_TIMER_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/gpio.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/gpio.h new file mode 100644 index 000000000..6f16ca77c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/gpio.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_H_INCLUDED__ +#define __GPIO_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "gpio_local.h" + +#ifndef __INLINE_GPIO__ +#define STORAGE_CLASS_GPIO_H extern +#define STORAGE_CLASS_GPIO_C +#include "gpio_public.h" +#else /* __INLINE_GPIO__ */ +#define STORAGE_CLASS_GPIO_H static inline +#define STORAGE_CLASS_GPIO_C static inline +#include "gpio_private.h" +#endif /* __INLINE_GPIO__ */ + +#endif /* __GPIO_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/hmem.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/hmem.h new file mode 100644 index 000000000..898facd7b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/hmem.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_H_INCLUDED__ +#define __HMEM_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the HMEM device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "hmem_local.h" + +#ifndef __INLINE_HMEM__ +#define STORAGE_CLASS_HMEM_H extern +#define STORAGE_CLASS_HMEM_C +#include "hmem_public.h" +#else /* __INLINE_HMEM__ */ +#define STORAGE_CLASS_HMEM_H static inline +#define STORAGE_CLASS_HMEM_C static inline +#include "hmem_private.h" +#endif /* __INLINE_HMEM__ */ + +#endif /* __HMEM_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/csi_rx_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/csi_rx_public.h new file mode 100644 index 000000000..3d6621f2f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/csi_rx_public.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_PUBLIC_H_INCLUDED__ +#define __CSI_RX_PUBLIC_H_INCLUDED__ + +#ifdef ISP2401 +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the csi rx frontend state. + * Get the state of the csi rx frontend regiester-set. + * + * @param[in] id The global unique ID of the csi rx fe controller. + * @param[out] state Point to the register-state. + */ +void csi_rx_fe_ctrl_get_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state); +/** + * @brief Dump the csi rx frontend state. + * Dump the state of the csi rx frontend regiester-set. + * + * @param[in] id The global unique ID of the csi rx fe controller. + * @param[in] state Point to the register-state. + */ +void csi_rx_fe_ctrl_dump_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state); +/** + * @brief Get the state of the csi rx fe dlane. + * Get the state of the register set per dlane process. + * + * @param[in] id The global unique ID of the input-buffer controller. + * @param[in] lane The lane ID. + * @param[out] state Point to the dlane state. + */ +void csi_rx_fe_ctrl_get_dlane_state( + const csi_rx_frontend_ID_t ID, + const u32 lane, + csi_rx_fe_ctrl_lane_t *dlane_state); +/** + * @brief Get the csi rx backend state. + * Get the state of the csi rx backend regiester-set. + * + * @param[in] id The global unique ID of the csi rx be controller. + * @param[out] state Point to the register-state. + */ +void csi_rx_be_ctrl_get_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state); +/** + * @brief Dump the csi rx backend state. + * Dump the state of the csi rx backend regiester-set. + * + * @param[in] id The global unique ID of the csi rx be controller. + * @param[in] state Point to the register-state. + */ +void csi_rx_be_ctrl_dump_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state); +/* end of NCI */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Load the value of the register of the csi rx fe. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offset address of the register. + * + * @return the value of the register. + */ +hrt_data csi_rx_fe_ctrl_reg_load( + const csi_rx_frontend_ID_t ID, + const hrt_address reg); +/** + * @brief Store a value to the register. + * Store a value to the registe of the csi rx fe. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offset address of the register. + * @param[in] value The value to be stored. + * + */ +void csi_rx_fe_ctrl_reg_store( + const csi_rx_frontend_ID_t ID, + const hrt_address reg, + const hrt_data value); +/** + * @brief Load the register value. + * Load the value of the register of the csirx be. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offset address of the register. + * + * @return the value of the register. + */ +hrt_data csi_rx_be_ctrl_reg_load( + const csi_rx_backend_ID_t ID, + const hrt_address reg); +/** + * @brief Store a value to the register. + * Store a value to the registe of the csi rx be. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offset address of the register. + * @param[in] value The value to be stored. + * + */ +void csi_rx_be_ctrl_reg_store( + const csi_rx_backend_ID_t ID, + const hrt_address reg, + const hrt_data value); +/* end of DLI */ +#endif /* ISP2401 */ +#endif /* __CSI_RX_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/debug_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/debug_public.h new file mode 100644 index 000000000..5660bd422 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/debug_public.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DEBUG_PUBLIC_H_INCLUDED__ +#define __DEBUG_PUBLIC_H_INCLUDED__ + +#include +#include +#include "system_local.h" + +/*! brief + * + * Simple queuing trace buffer for debug data + * instantiatable in SP DMEM + * + * The buffer has a remote and a local store + * which contain duplicate data (when in sync). + * The buffers are automatically synched when the + * user dequeues, or manualy using the synch function + * + * An alternative (storage efficient) implementation + * could manage the buffers to contain unique data + * + * The buffer empty status is computed from local + * state which does not reflect the presence of data + * in the remote buffer (unless the alternative + * implementation is followed) + */ + +typedef struct debug_data_s debug_data_t; +typedef struct debug_data_ddr_s debug_data_ddr_t; + +extern debug_data_t *debug_data_ptr; +extern hrt_address debug_buffer_address; +extern ia_css_ptr debug_buffer_ddr_address; + +/*! Check the empty state of the local debug data buffer + + \return isEmpty(buffer) + */ +STORAGE_CLASS_DEBUG_H bool is_debug_buffer_empty(void); + +/*! Dequeue a token from the debug data buffer + + \return isEmpty(buffer)?0:buffer[head] + */ +STORAGE_CLASS_DEBUG_H hrt_data debug_dequeue(void); + +/*! Synchronise the remote buffer to the local buffer + + \return none + */ +STORAGE_CLASS_DEBUG_H void debug_synch_queue(void); + +/*! Synchronise the remote buffer to the local buffer + + \return none + */ +STORAGE_CLASS_DEBUG_H void debug_synch_queue_isp(void); + +/*! Synchronise the remote buffer to the local buffer + + \return none + */ +STORAGE_CLASS_DEBUG_H void debug_synch_queue_ddr(void); + +/*! Set the offset/address of the (remote) debug buffer + + \return none + */ +void debug_buffer_init( + const hrt_address addr); + +/*! Set the offset/address of the (remote) debug buffer + + \return none + */ +void debug_buffer_ddr_init( + const ia_css_ptr addr); + +/*! Set the (remote) operating mode of the debug buffer + + \return none + */ +void debug_buffer_setmode( + const debug_buf_mode_t mode); + +#endif /* __DEBUG_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/dma_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/dma_public.h new file mode 100644 index 000000000..a23cbc9a2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/dma_public.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_PUBLIC_H_INCLUDED__ +#define __DMA_PUBLIC_H_INCLUDED__ + +#include "system_local.h" + +typedef struct dma_state_s dma_state_t; + +/*! Read the control registers of DMA[ID] + + \param ID[in] DMA identifier + \param state[out] input formatter state structure + + \return none, state = DMA[ID].state + */ +void dma_get_state( + const dma_ID_t ID, + dma_state_t *state); + +/*! Write to a control register of DMA[ID] + + \param ID[in] DMA identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, DMA[ID].ctrl[reg] = value + */ +STORAGE_CLASS_DMA_H void dma_reg_store( + const dma_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from a control register of DMA[ID] + + \param ID[in] DMA identifier + \param reg[in] register index + \param value[in] The data to be written + + \return DMA[ID].ctrl[reg] + */ +STORAGE_CLASS_DMA_H hrt_data dma_reg_load( + const dma_ID_t ID, + const unsigned int reg); + +/*! Set maximum burst size of DMA[ID] + + \param ID[in] DMA identifier + \param conn[in] Connection to set max burst size for + \param max_burst_size[in] Maximum burst size in words + + \return none +*/ +void +dma_set_max_burst_size( + dma_ID_t ID, + dma_connection conn, + uint32_t max_burst_size); + +#endif /* __DMA_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/event_fifo_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/event_fifo_public.h new file mode 100644 index 000000000..22f1875f0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/event_fifo_public.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __EVENT_FIFO_PUBLIC_H +#define __EVENT_FIFO_PUBLIC_H + +#include +#include "system_local.h" + +/*! Blocking read from an event source EVENT[ID] + + \param ID[in] EVENT identifier + + \return none, dequeue(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H void event_wait_for( + const event_ID_t ID); + +/*! Conditional blocking wait for an event source EVENT[ID] + + \param ID[in] EVENT identifier + \param cnd[in] predicate + + \return none, if(cnd) dequeue(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H void cnd_event_wait_for( + const event_ID_t ID, + const bool cnd); + +/*! Blocking read from an event source EVENT[ID] + + \param ID[in] EVENT identifier + + \return dequeue(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H hrt_data event_receive_token( + const event_ID_t ID); + +/*! Blocking write to an event sink EVENT[ID] + + \param ID[in] EVENT identifier + \param token[in] token to be written on the event + + \return none, enqueue(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H void event_send_token( + const event_ID_t ID, + const hrt_data token); + +/*! Query an event source EVENT[ID] + + \param ID[in] EVENT identifier + + \return !isempty(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H bool is_event_pending( + const event_ID_t ID); + +/*! Query an event sink EVENT[ID] + + \param ID[in] EVENT identifier + + \return !isfull(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H bool can_event_send_token( + const event_ID_t ID); + +#endif /* __EVENT_FIFO_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/fifo_monitor_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/fifo_monitor_public.h new file mode 100644 index 000000000..7c1c3d2f2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/fifo_monitor_public.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_PUBLIC_H_INCLUDED__ +#define __FIFO_MONITOR_PUBLIC_H_INCLUDED__ + +#include "system_local.h" + +typedef struct fifo_channel_state_s fifo_channel_state_t; +typedef struct fifo_switch_state_s fifo_switch_state_t; +typedef struct fifo_monitor_state_s fifo_monitor_state_t; + +/*! Set a fifo switch multiplex + + \param ID[in] FIFO_MONITOR identifier + \param switch_id[in] fifo switch identifier + \param sel[in] fifo switch selector + + \return none, fifo_switch[switch_id].sel = sel + */ +STORAGE_CLASS_FIFO_MONITOR_H void fifo_switch_set( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id, + const hrt_data sel); + +/*! Get a fifo switch multiplex + + \param ID[in] FIFO_MONITOR identifier + \param switch_id[in] fifo switch identifier + + \return fifo_switch[switch_id].sel + */ +STORAGE_CLASS_FIFO_MONITOR_H hrt_data fifo_switch_get( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id); + +/*! Read the state of FIFO_MONITOR[ID] + + \param ID[in] FIFO_MONITOR identifier + \param state[out] fifo monitor state structure + + \return none, state = FIFO_MONITOR[ID].state + */ +void fifo_monitor_get_state( + const fifo_monitor_ID_t ID, + fifo_monitor_state_t *state); + +/*! Read the state of a fifo channel + + \param ID[in] FIFO_MONITOR identifier + \param channel_id[in] fifo channel identifier + \param state[out] fifo channel state structure + + \return none, state = fifo_channel[channel_id].state + */ +void fifo_channel_get_state( + const fifo_monitor_ID_t ID, + const fifo_channel_t channel_id, + fifo_channel_state_t *state); + +/*! Read the state of a fifo switch + + \param ID[in] FIFO_MONITOR identifier + \param switch_id[in] fifo switch identifier + \param state[out] fifo switch state structure + + \return none, state = fifo_switch[switch_id].state + */ +void fifo_switch_get_state( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id, + fifo_switch_state_t *state); + +/*! Write to a control register of FIFO_MONITOR[ID] + + \param ID[in] FIFO_MONITOR identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, FIFO_MONITOR[ID].ctrl[reg] = value + */ +STORAGE_CLASS_FIFO_MONITOR_H void fifo_monitor_reg_store( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from a control register of FIFO_MONITOR[ID] + + \param ID[in] FIFO_MONITOR identifier + \param reg[in] register index + \param value[in] The data to be written + + \return FIFO_MONITOR[ID].ctrl[reg] + */ +STORAGE_CLASS_FIFO_MONITOR_H hrt_data fifo_monitor_reg_load( + const fifo_monitor_ID_t ID, + const unsigned int reg); + +#endif /* __FIFO_MONITOR_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gdc_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gdc_public.h new file mode 100644 index 000000000..385b79254 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gdc_public.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_PUBLIC_H_INCLUDED__ +#define __GDC_PUBLIC_H_INCLUDED__ + +/*! Write the bicubic interpolation table of GDC[ID] + + \param ID[in] GDC identifier + \param data[in] The data matrix to be written + + \pre + - data must point to a matrix[4][HRT_GDC_N] + + \implementation dependent + - The value of "HRT_GDC_N" is device specific + - The LUT should not be partially written + - The LUT format is a quadri-phase interpolation + table. The layout is device specific + - The range of the values data[n][m] is device + specific + + \return none, GDC[ID].lut[0...3][0...HRT_GDC_N-1] = data + */ +void gdc_lut_store( + const gdc_ID_t ID, + const int data[4][HRT_GDC_N]); + +/*! Convert the bicubic interpolation table of GDC[ID] to the ISP-specific format + + \param ID[in] GDC identifier + \param in_lut[in] The data matrix to be converted + \param out_lut[out] The data matrix as the output of conversion + */ +void gdc_lut_convert_to_isp_format( + const int in_lut[4][HRT_GDC_N], + int out_lut[4][HRT_GDC_N]); + +/*! Return the integer representation of 1.0 of GDC[ID] + + \param ID[in] GDC identifier + + \return unity + */ +int gdc_get_unity( + const gdc_ID_t ID); + +#endif /* __GDC_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gp_device_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gp_device_public.h new file mode 100644 index 000000000..f017742d9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gp_device_public.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_PUBLIC_H_INCLUDED__ +#define __GP_DEVICE_PUBLIC_H_INCLUDED__ + +#include "system_local.h" + +typedef struct gp_device_state_s gp_device_state_t; + +/*! Read the state of GP_DEVICE[ID] + + \param ID[in] GP_DEVICE identifier + \param state[out] gp device state structure + + \return none, state = GP_DEVICE[ID].state + */ +void gp_device_get_state( + const gp_device_ID_t ID, + gp_device_state_t *state); + +/*! Write to a control register of GP_DEVICE[ID] + + \param ID[in] GP_DEVICE identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return none, GP_DEVICE[ID].ctrl[reg] = value + */ +STORAGE_CLASS_GP_DEVICE_H void gp_device_reg_store( + const gp_device_ID_t ID, + const unsigned int reg_addr, + const hrt_data value); + +/*! Read from a control register of GP_DEVICE[ID] + + \param ID[in] GP_DEVICE identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return GP_DEVICE[ID].ctrl[reg] + */ +STORAGE_CLASS_GP_DEVICE_H hrt_data gp_device_reg_load( + const gp_device_ID_t ID, + const hrt_address reg_addr); + +#endif /* __GP_DEVICE_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gp_timer_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gp_timer_public.h new file mode 100644 index 000000000..13baf7236 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gp_timer_public.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_PUBLIC_H_INCLUDED__ +#define __GP_TIMER_PUBLIC_H_INCLUDED__ + +#include "system_local.h" + +/*! initialize mentioned timer +param ID timer_id +*/ +extern void +gp_timer_init(gp_timer_ID_t ID); + +/*! read timer value for (platform selected)selected timer. +param ID timer_id + \return uint32_t 32 bit timer value +*/ +extern uint32_t +gp_timer_read(gp_timer_ID_t ID); + +#endif /* __GP_TIMER_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gpio_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gpio_public.h new file mode 100644 index 000000000..13df9b57a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/gpio_public.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_PUBLIC_H_INCLUDED__ +#define __GPIO_PUBLIC_H_INCLUDED__ + +#include "system_local.h" + +/*! Write to a control register of GPIO[ID] + + \param ID[in] GPIO identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return none, GPIO[ID].ctrl[reg] = value + */ +STORAGE_CLASS_GPIO_H void gpio_reg_store( + const gpio_ID_t ID, + const unsigned int reg_addr, + const hrt_data value); + +/*! Read from a control register of GPIO[ID] + + \param ID[in] GPIO identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return GPIO[ID].ctrl[reg] + */ +STORAGE_CLASS_GPIO_H hrt_data gpio_reg_load( + const gpio_ID_t ID, + const unsigned int reg_addr); + +#endif /* __GPIO_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/hmem_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/hmem_public.h new file mode 100644 index 000000000..8d271fb84 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/hmem_public.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_PUBLIC_H_INCLUDED__ +#define __HMEM_PUBLIC_H_INCLUDED__ + +#include /* size_t */ + +/*! Return the size of HMEM[ID] + + \param ID[in] HMEM identifier + + \Note: The size is the byte size of the area it occupies + in the address map. I.e. disregarding internal structure + + \return sizeof(HMEM[ID]) + */ +STORAGE_CLASS_HMEM_H size_t sizeof_hmem( + const hmem_ID_t ID); + +#endif /* __HMEM_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/input_formatter_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/input_formatter_public.h new file mode 100644 index 000000000..81dc58640 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/input_formatter_public.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_FORMATTER_PUBLIC_H_INCLUDED__ +#define __INPUT_FORMATTER_PUBLIC_H_INCLUDED__ + +#include +#include "system_local.h" + +/*! Reset INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + + \return none, reset(INPUT_FORMATTER[ID]) + */ +void input_formatter_rst( + const input_formatter_ID_t ID); + +/*! Set the blocking mode of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param enable[in] blocking enable flag + + \use + - In HW, the capture unit will deliver an infinite stream of frames, + the input formatter will synchronise on the first SOF. In simulation + there are only a fixed number of frames, presented only once. By + enabling blocking the inputformatter will wait on the first presented + frame, thus avoiding race in the simulation setup. + + \return none, INPUT_FORMATTER[ID].blocking_mode = enable + */ +void input_formatter_set_fifo_blocking_mode( + const input_formatter_ID_t ID, + const bool enable); + +/*! Return the data alignment of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + + \return alignment(INPUT_FORMATTER[ID].data) + */ +unsigned int input_formatter_get_alignment( + const input_formatter_ID_t ID); + +/*! Read the source switch state into INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param state[out] input formatter switch state structure + + \return none, state = INPUT_FORMATTER[ID].switch_state + */ +void input_formatter_get_switch_state( + const input_formatter_ID_t ID, + input_formatter_switch_state_t *state); + +/*! Read the control registers of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param state[out] input formatter state structure + + \return none, state = INPUT_FORMATTER[ID].state + */ +void input_formatter_get_state( + const input_formatter_ID_t ID, + input_formatter_state_t *state); + +/*! Read the control registers of bin copy INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param state[out] input formatter state structure + + \return none, state = INPUT_FORMATTER[ID].state + */ +void input_formatter_bin_get_state( + const input_formatter_ID_t ID, + input_formatter_bin_state_t *state); + +/*! Write to a control register of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return none, INPUT_FORMATTER[ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_FORMATTER_H void input_formatter_reg_store( + const input_formatter_ID_t ID, + const hrt_address reg_addr, + const hrt_data value); + +/*! Read from a control register of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return INPUT_FORMATTER[ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_FORMATTER_H hrt_data input_formatter_reg_load( + const input_formatter_ID_t ID, + const unsigned int reg_addr); + +#endif /* __INPUT_FORMATTER_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/irq_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/irq_public.h new file mode 100644 index 000000000..d335e7b0a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/irq_public.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IRQ_PUBLIC_H_INCLUDED__ +#define __IRQ_PUBLIC_H_INCLUDED__ + +#include +#include "system_local.h" + +/*! Read the control registers of IRQ[ID] + + \param ID[in] IRQ identifier + \param state[out] irq controller state structure + + \return none, state = IRQ[ID].state + */ +void irq_controller_get_state(const irq_ID_t ID, + struct irq_controller_state *state); + +/*! Write to a control register of IRQ[ID] + + \param ID[in] IRQ identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, IRQ[ID].ctrl[reg] = value + */ +STORAGE_CLASS_IRQ_H void irq_reg_store( + const irq_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from a control register of IRQ[ID] + + \param ID[in] IRQ identifier + \param reg[in] register index + \param value[in] The data to be written + + \return IRQ[ID].ctrl[reg] + */ +STORAGE_CLASS_IRQ_H hrt_data irq_reg_load( + const irq_ID_t ID, + const unsigned int reg); + +/*! Enable an IRQ channel of IRQ[ID] with a mode + + \param ID[in] IRQ (device) identifier + \param irq[in] IRQ (channel) identifier + + \return none, enable(IRQ[ID].channel[irq_ID]) + */ +void irq_enable_channel( + const irq_ID_t ID, + const unsigned int irq_ID); + +/*! Enable pulse interrupts for IRQ[ID] with a mode + + \param ID[in] IRQ (device) identifier + \param enable enable/disable pulse interrupts + + \return none + */ +void irq_enable_pulse( + const irq_ID_t ID, + bool pulse); + +/*! Disable an IRQ channel of IRQ[ID] + + \param ID[in] IRQ (device) identifier + \param irq[in] IRQ (channel) identifier + + \return none, disable(IRQ[ID].channel[irq_ID]) + */ +void irq_disable_channel( + const irq_ID_t ID, + const unsigned int irq); + +/*! Clear the state of all IRQ channels of IRQ[ID] + + \param ID[in] IRQ (device) identifier + + \return none, clear(IRQ[ID].channel[]) + */ +void irq_clear_all( + const irq_ID_t ID); + +/*! Return the ID of a signalling IRQ channel of IRQ[ID] + + \param ID[in] IRQ (device) identifier + \param irq_id[out] active IRQ (channel) identifier + + \Note: This function operates as strtok(), based on the return + state the user is informed if there are additional signalling + channels + + \return state(IRQ[ID]) + */ +enum hrt_isp_css_irq_status irq_get_channel_id( + const irq_ID_t ID, + unsigned int *irq_id); + +/*! Raise an interrupt on channel irq_id of device IRQ[ID] + + \param ID[in] IRQ (device) identifier + \param irq_id[in] IRQ (channel) identifier + + \return none, signal(IRQ[ID].channel[irq_id]) + */ +void irq_raise( + const irq_ID_t ID, + const irq_sw_channel_id_t irq_id); + +/*! Test if any IRQ channel of the virtual super IRQ has raised a signal + + \return any(VIRQ.channel[irq_ID] != 0) + */ +bool any_virq_signal(void); + +/*! Enable an IRQ channel of the virtual super IRQ + + \param irq[in] IRQ (channel) identifier + \param en[in] predicate channel enable + + \return none, VIRQ.channel[irq_ID].enable = en + */ +void cnd_virq_enable_channel( + const enum virq_id irq_ID, + const bool en); + +/*! Clear the state of all IRQ channels of the virtual super IRQ + + \return none, clear(VIRQ.channel[]) + */ +void virq_clear_all(void); + +/*! Clear the IRQ info state of the virtual super IRQ + + \param irq_info[in/out] The IRQ (channel) state + + \return none + */ +void virq_clear_info(struct virq_info *irq_info); + +/*! Return the ID of a signalling IRQ channel of the virtual super IRQ + + \param irq_id[out] active IRQ (channel) identifier + + \Note: This function operates as strtok(), based on the return + state the user is informed if there are additional signalling + channels + + \return state(IRQ[...]) + */ +enum hrt_isp_css_irq_status virq_get_channel_id( + enum virq_id *irq_id); + +/*! Return the IDs of all signaling IRQ channels of the virtual super IRQ + + \param irq_info[out] all active IRQ (channel) identifiers + + \Note: Unlike "irq_get_channel_id()" this function returns all + channel signaling info. The new info is OR'd with the current + info state. N.B. this is the same as repeatedly calling the function + "irq_get_channel_id()" in a (non-blocked) handler routine + + \return (error(state(IRQ[...])) + */ +enum hrt_isp_css_irq_status +virq_get_channel_signals(struct virq_info *irq_info); + +#endif /* __IRQ_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/isp_public.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/isp_public.h new file mode 100644 index 000000000..a8ff75c63 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/isp_public.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_PUBLIC_H_INCLUDED__ +#define __ISP_PUBLIC_H_INCLUDED__ + +#include +#include "system_local.h" + +/*! Enable or disable the program complete irq signal of ISP[ID] + + \param ID[in] SP identifier + \param cnd[in] predicate + + \return none, if(cnd) enable(ISP[ID].irq) else disable(ISP[ID].irq) + */ +void cnd_isp_irq_enable( + const isp_ID_t ID, + const bool cnd); + +/*! Read the state of cell ISP[ID] + + \param ID[in] ISP identifier + \param state[out] isp state structure + \param stall[out] isp stall conditions + + \return none, state = ISP[ID].state, stall = ISP[ID].stall + */ +void isp_get_state( + const isp_ID_t ID, + isp_state_t *state, + isp_stall_t *stall); + +/*! Write to the status and control register of ISP[ID] + + \param ID[in] ISP identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, ISP[ID].sc[reg] = value + */ +STORAGE_CLASS_ISP_H void isp_ctrl_store( + const isp_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from the status and control register of ISP[ID] + + \param ID[in] ISP identifier + \param reg[in] register index + \param value[in] The data to be written + + \return ISP[ID].sc[reg] + */ +STORAGE_CLASS_ISP_H hrt_data isp_ctrl_load( + const isp_ID_t ID, + const unsigned int reg); + +/*! Get the status of a bitfield in the control register of ISP[ID] + + \param ID[in] ISP identifier + \param reg[in] register index + \param bit[in] The bit index to be checked + + \return (ISP[ID].sc[reg] & (1< +#include "system_local.h" + +typedef struct sp_state_s sp_state_t; +typedef struct sp_stall_s sp_stall_t; + +/*! Enable or disable the program complete irq signal of SP[ID] + + \param ID[in] SP identifier + \param cnd[in] predicate + + \return none, if(cnd) enable(SP[ID].irq) else disable(SP[ID].irq) + */ +void cnd_sp_irq_enable( + const sp_ID_t ID, + const bool cnd); + +/*! Read the state of cell SP[ID] + + \param ID[in] SP identifier + \param state[out] sp state structure + \param stall[out] isp stall conditions + + \return none, state = SP[ID].state, stall = SP[ID].stall + */ +void sp_get_state( + const sp_ID_t ID, + sp_state_t *state, + sp_stall_t *stall); + +/*! Write to the status and control register of SP[ID] + + \param ID[in] SP identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, SP[ID].sc[reg] = value + */ +STORAGE_CLASS_SP_H void sp_ctrl_store( + const sp_ID_t ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from the status and control register of SP[ID] + + \param ID[in] SP identifier + \param reg[in] register index + \param value[in] The data to be written + + \return SP[ID].sc[reg] + */ +STORAGE_CLASS_SP_H hrt_data sp_ctrl_load( + const sp_ID_t ID, + const hrt_address reg); + +/*! Get the status of a bitfield in the control register of SP[ID] + + \param ID[in] SP identifier + \param reg[in] register index + \param bit[in] The bit index to be checked + + \return (SP[ID].sc[reg] & (1< +#include + +#if defined(ISP2401) + +#include "isys_irq_public.h" + +#endif /* defined(ISP2401) */ + +#endif /* __IA_CSS_ISYS_IRQ_H__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/isys_stream2mmio.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/isys_stream2mmio.h new file mode 100644 index 000000000..b0f09ffb4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/isys_stream2mmio.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & + * inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "isys_stream2mmio_local.h" + +#ifndef __INLINE_STREAM2MMIO__ +#define STORAGE_CLASS_STREAM2MMIO_H extern +#define STORAGE_CLASS_STREAM2MMIO_C +#include "isys_stream2mmio_public.h" +#else /* __INLINE_STREAM2MMIO__ */ +#define STORAGE_CLASS_STREAM2MMIO_H static inline +#define STORAGE_CLASS_STREAM2MMIO_C static inline +#include "isys_stream2mmio_private.h" +#endif /* __INLINE_STREAM2MMIO__ */ + +#endif /* __ISYS_STREAM2MMIO_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/math_support.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/math_support.h new file mode 100644 index 000000000..a444ec14f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/math_support.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MATH_SUPPORT_H +#define __MATH_SUPPORT_H + +#include /* Override the definition of max/min from linux kernel*/ + +#define IS_ODD(a) ((a) & 0x1) +#define IS_EVEN(a) (!IS_ODD(a)) + +/* force a value to a lower even value */ +#define EVEN_FLOOR(x) ((x) & ~1) + +/* ISP2401 */ +/* If the number is odd, find the next even number */ +#define EVEN_CEIL(x) ((IS_ODD(x)) ? ((x) + 1) : (x)) + +/* A => B */ +#define IMPLIES(a, b) (!(a) || (b)) + +/* for preprocessor and array sizing use MIN and MAX + otherwise use min and max */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define ROUND_DIV(a, b) (((b) != 0) ? ((a) + ((b) >> 1)) / (b) : 0) +#define CEIL_DIV(a, b) (((b) != 0) ? ((a) + (b) - 1) / (b) : 0) +#define CEIL_MUL(a, b) (CEIL_DIV(a, b) * (b)) +#define CEIL_MUL2(a, b) (((a) + (b) - 1) & ~((b) - 1)) +#define CEIL_SHIFT(a, b) (((a) + (1 << (b)) - 1) >> (b)) +#define CEIL_SHIFT_MUL(a, b) (CEIL_SHIFT(a, b) << (b)) +#define ROUND_HALF_DOWN_DIV(a, b) (((b) != 0) ? ((a) + (b / 2) - 1) / (b) : 0) +#define ROUND_HALF_DOWN_MUL(a, b) (ROUND_HALF_DOWN_DIV(a, b) * (b)) + +/*To Find next power of 2 number from x */ +#define bit2(x) ((x) | ((x) >> 1)) +#define bit4(x) (bit2(x) | (bit2(x) >> 2)) +#define bit8(x) (bit4(x) | (bit4(x) >> 4)) +#define bit16(x) (bit8(x) | (bit8(x) >> 8)) +#define bit32(x) (bit16(x) | (bit16(x) >> 16)) +#define NEXT_POWER_OF_2(x) (bit32(x - 1) + 1) + +/* min and max should not be macros as they will evaluate their arguments twice. + if you really need a macro (e.g. for CPP or for initializing an array) + use MIN() and MAX(), otherwise use min() and max(). + +*/ + +#if !defined(PIPE_GENERATION) + +/* +This macro versions are added back as we are mixing types in usage of inline. +This causes corner cases of calculations to be incorrect due to conversions +between signed and unsigned variables or overflows. +Before the addition of the inline functions, max, min and ceil_div were macros +and therefore adding them back. + +Leaving out the other math utility functions as they are newly added +*/ + +#define ceil_div(a, b) (CEIL_DIV(a, b)) + +static inline unsigned int ceil_mul(unsigned int a, unsigned int b) +{ + return CEIL_MUL(a, b); +} + +static inline unsigned int ceil_mul2(unsigned int a, unsigned int b) +{ + return CEIL_MUL2(a, b); +} + +static inline unsigned int ceil_shift(unsigned int a, unsigned int b) +{ + return CEIL_SHIFT(a, b); +} + +static inline unsigned int ceil_shift_mul(unsigned int a, unsigned int b) +{ + return CEIL_SHIFT_MUL(a, b); +} + +/* ISP2401 */ +static inline unsigned int round_half_down_div(unsigned int a, unsigned int b) +{ + return ROUND_HALF_DOWN_DIV(a, b); +} + +/* ISP2401 */ +static inline unsigned int round_half_down_mul(unsigned int a, unsigned int b) +{ + return ROUND_HALF_DOWN_MUL(a, b); +} + +/* @brief Next Power of Two + * + * @param[in] unsigned number + * + * @return next power of two + * + * This function rounds input to the nearest power of 2 (2^x) + * towards infinity + * + * Input Range: 0 .. 2^(8*sizeof(int)-1) + * + * IF input is a power of 2 + * out = in + * OTHERWISE + * out = 2^(ceil(log2(in)) + * + */ + +static inline unsigned int ceil_pow2(unsigned int a) +{ + if (a == 0) { + return 1; + } + /* IF input is already a power of two*/ + else if ((!((a) & ((a) - 1)))) { + return a; + } else { + unsigned int v = a; + + v |= v >> 1; + v |= v >> 2; + v |= v >> 4; + v |= v >> 8; + v |= v >> 16; + return (v + 1); + } +} + +#endif /* !defined(PIPE_GENERATION) */ + +/* + * For SP and ISP, SDK provides the definition of OP_std_modadd. + * We need it only for host + */ +#define OP_std_modadd(base, offset, size) ((base + offset) % (size)) + +#endif /* __MATH_SUPPORT_H */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/misc_support.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/misc_support.h new file mode 100644 index 000000000..393452d7a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/misc_support.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MISC_SUPPORT_H_INCLUDED__ +#define __MISC_SUPPORT_H_INCLUDED__ + +/* suppress compiler warnings on unused variables */ +#ifndef NOT_USED +#define NOT_USED(a) ((void)(a)) +#endif + +/* Calculate the total bytes for pow(2) byte alignment */ +#define tot_bytes_for_pow2_align(pow2, cur_bytes) ((cur_bytes + (pow2 - 1)) & ~(pow2 - 1)) + +#endif /* __MISC_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/mmu_device.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/mmu_device.h new file mode 100644 index 000000000..b6f6eda4c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/mmu_device.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MMU_DEVICE_H_INCLUDED__ +#define __MMU_DEVICE_H_INCLUDED__ + +/* The file mmu.h already exists */ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the MMU device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "mmu_local.h" + +#include "mmu_public.h" + +#endif /* __MMU_DEVICE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/pixelgen.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/pixelgen.h new file mode 100644 index 000000000..e34cd3c58 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/pixelgen.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_H_INCLUDED__ +#define __PIXELGEN_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & + * inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "pixelgen_local.h" + +#ifndef __INLINE_PIXELGEN__ +#define STORAGE_CLASS_PIXELGEN_H extern +#define STORAGE_CLASS_PIXELGEN_C +#include "pixelgen_public.h" +#else /* __INLINE_PIXELGEN__ */ +#define STORAGE_CLASS_PIXELGEN_H static inline +#define STORAGE_CLASS_PIXELGEN_C static inline +#include "pixelgen_private.h" +#endif /* __INLINE_PIXELGEN__ */ + +#endif /* __PIXELGEN_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/platform_support.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/platform_support.h new file mode 100644 index 000000000..0cdef4a5e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/platform_support.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PLATFORM_SUPPORT_H_INCLUDED__ +#define __PLATFORM_SUPPORT_H_INCLUDED__ + +/** +* @file +* Platform specific includes and functionality. +*/ + +#include +#include +#include + +#define UINT16_MAX USHRT_MAX +#define UINT32_MAX UINT_MAX +#define UCHAR_MAX (255) + +#define CSS_ALIGN(d, a) d __attribute__((aligned(a))) + +#endif /* __PLATFORM_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/print_support.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/print_support.h new file mode 100644 index 000000000..a3c7f3de6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/print_support.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PRINT_SUPPORT_H_INCLUDED__ +#define __PRINT_SUPPORT_H_INCLUDED__ + +#include + +extern int (*sh_css_printf)(const char *fmt, va_list args); +/* depends on host supplied print function in ia_css_init() */ +static inline __printf(1, 2) void ia_css_print(const char *fmt, ...) +{ + va_list ap; + + if (sh_css_printf) { + va_start(ap, fmt); + sh_css_printf(fmt, ap); + va_end(ap); + } +} + +/* Start adding support for bxt tracing functions for poc. From + * bxt_sandbox/support/print_support.h. */ +/* TODO: support these macros in userspace. */ +#define PWARN(format, ...) ia_css_print("warning: ", ##__VA_ARGS__) +#define PRINT(format, ...) ia_css_print(format, ##__VA_ARGS__) +#define PERROR(format, ...) ia_css_print("error: " format, ##__VA_ARGS__) +#define PDEBUG(format, ...) ia_css_print("debug: " format, ##__VA_ARGS__) + +#endif /* __PRINT_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/queue.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/queue.h new file mode 100644 index 000000000..e6978750a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/queue.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_H_INCLUDED__ +#define __QUEUE_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and is system agnostic + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - system and cell agnostic interfaces, constants and identifiers + * - public: cell specific interfaces + * - private: cell specific inline implementations + * - global: inter cell constants and identifiers + * - local: cell specific constants and identifiers + * + */ + +#include "queue_local.h" + +#ifndef __INLINE_QUEUE__ +#define STORAGE_CLASS_QUEUE_H extern +#define STORAGE_CLASS_QUEUE_C +/* #include "queue_public.h" */ +#include "ia_css_queue.h" +#else /* __INLINE_QUEUE__ */ +#define STORAGE_CLASS_QUEUE_H static inline +#define STORAGE_CLASS_QUEUE_C static inline +#include "queue_private.h" +#endif /* __INLINE_QUEUE__ */ + +#endif /* __QUEUE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/resource.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/resource.h new file mode 100644 index 000000000..9be45b679 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/resource.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __RESOURCE_H_INCLUDED__ +#define __RESOURCE_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses a RESOURCE manager. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "system_local.h" +#include "resource_local.h" + +#ifndef __INLINE_RESOURCE__ +#define STORAGE_CLASS_RESOURCE_H extern +#define STORAGE_CLASS_RESOURCE_C +#include "resource_public.h" +#else /* __INLINE_RESOURCE__ */ +#define STORAGE_CLASS_RESOURCE_H static inline +#define STORAGE_CLASS_RESOURCE_C static inline +#include "resource_private.h" +#endif /* __INLINE_RESOURCE__ */ + +#endif /* __RESOURCE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/sp.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/sp.h new file mode 100644 index 000000000..a7d00c7bb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/sp.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_H_INCLUDED__ +#define __SP_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the SP cell. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "sp_local.h" + +#ifndef __INLINE_SP__ +#define STORAGE_CLASS_SP_H extern +#define STORAGE_CLASS_SP_C +#include "sp_public.h" +#else /* __INLINE_SP__ */ +#define STORAGE_CLASS_SP_H static inline +#define STORAGE_CLASS_SP_C static inline +#include "sp_private.h" +#endif /* __INLINE_SP__ */ + +#endif /* __SP_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/tag.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/tag.h new file mode 100644 index 000000000..98d7e922a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/tag.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TAG_H_INCLUDED__ +#define __TAG_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and is system agnostic + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: cell specific interfaces + * - private: cell specific inline implementations + * - global: inter cell constants and identifiers + * - local: cell specific constants and identifiers + * + */ + +#include "tag_local.h" + +#ifndef __INLINE_TAG__ +#define STORAGE_CLASS_TAG_H extern +#define STORAGE_CLASS_TAG_C +#include "tag_public.h" +#else /* __INLINE_TAG__ */ +#define STORAGE_CLASS_TAG_H static inline +#define STORAGE_CLASS_TAG_C static inline +#include "tag_private.h" +#endif /* __INLINE_TAG__ */ + +#endif /* __TAG_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/timed_ctrl.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/timed_ctrl.h new file mode 100644 index 000000000..65b2871fb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/timed_ctrl.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TIMED_CTRL_H_INCLUDED__ +#define __TIMED_CTRL_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "timed_ctrl_local.h" + +#ifndef __INLINE_TIMED_CTRL__ +#define STORAGE_CLASS_TIMED_CTRL_H extern +#define STORAGE_CLASS_TIMED_CTRL_C +#include "timed_ctrl_public.h" +#else /* __INLINE_TIMED_CTRL__ */ +#define STORAGE_CLASS_TIMED_CTRL_H static inline +#define STORAGE_CLASS_TIMED_CTRL_C static inline +#include "timed_ctrl_private.h" +#endif /* __INLINE_TIMED_CTRL__ */ + +#endif /* __TIMED_CTRL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/type_support.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/type_support.h new file mode 100644 index 000000000..b996ee54d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/type_support.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TYPE_SUPPORT_H_INCLUDED__ +#define __TYPE_SUPPORT_H_INCLUDED__ + +/** +* @file +* Platform specific types. +* +* Per the DLI spec, types are in "type_support.h" and +* "platform_support.h" is for unclassified/to be refactored +* platform specific definitions. +*/ + +#define IA_CSS_UINT8_T_BITS 8 +#define IA_CSS_UINT16_T_BITS 16 +#define IA_CSS_UINT32_T_BITS 32 +#define IA_CSS_INT32_T_BITS 32 +#define IA_CSS_UINT64_T_BITS 64 + +#define CHAR_BIT (8) + +#include +#include +#include +#define HOST_ADDRESS(x) (unsigned long)(x) + +#endif /* __TYPE_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/vamem.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/vamem.h new file mode 100644 index 000000000..3ea6758aa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/vamem.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VAMEM_H_INCLUDED__ +#define __VAMEM_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the VAMEM device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "vamem_local.h" +#include "vamem_public.h" + +#endif /* __VAMEM_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/vmem.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/vmem.h new file mode 100644 index 000000000..da479b370 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_include/vmem.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VMEM_H_INCLUDED__ +#define __VMEM_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the VMEM device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "system_local.h" +#include "vmem_local.h" + +#ifndef __INLINE_VMEM__ +#define STORAGE_CLASS_VMEM_H extern +#define STORAGE_CLASS_VMEM_C +#include "vmem_public.h" +#else /* __INLINE_VMEM__ */ +#define STORAGE_CLASS_VMEM_H static inline +#define STORAGE_CLASS_VMEM_C static inline +#include "vmem_private.h" +#endif /* __INLINE_VMEM__ */ + +#endif /* __VMEM_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/queue_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/queue_local.h new file mode 100644 index 000000000..31121a22d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/queue_local.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_LOCAL_H_INCLUDED__ +#define __QUEUE_LOCAL_H_INCLUDED__ + +#include "queue_global.h" + +#endif /* __QUEUE_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/queue_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/queue_private.h new file mode 100644 index 000000000..be6162dfb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/queue_private.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_PRIVATE_H_INCLUDED__ +#define __QUEUE_PRIVATE_H_INCLUDED__ + +#endif /* __QUEUE_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag.c b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag.c new file mode 100644 index 000000000..8931539a4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "tag.h" +#include /* NULL */ +#include +#include "tag_local.h" + +/* + * @brief Creates the tag description from the given parameters. + * @param[in] num_captures + * @param[in] skip + * @param[in] offset + * @param[out] tag_descr + */ +void +sh_css_create_tag_descr(int num_captures, + unsigned int skip, + int offset, + unsigned int exp_id, + struct sh_css_tag_descr *tag_descr) +{ + assert(tag_descr); + + tag_descr->num_captures = num_captures; + tag_descr->skip = skip; + tag_descr->offset = offset; + tag_descr->exp_id = exp_id; +} + +/* + * @brief Encodes the members of tag description into a 32-bit value. + * @param[in] tag Pointer to the tag description + * @return (unsigned int) Encoded 32-bit tag-info + */ +unsigned int +sh_css_encode_tag_descr(struct sh_css_tag_descr *tag) +{ + int num_captures; + unsigned int num_captures_sign; + unsigned int skip; + int offset; + unsigned int offset_sign; + unsigned int exp_id; + unsigned int encoded_tag; + + assert(tag); + + if (tag->num_captures < 0) { + num_captures = -tag->num_captures; + num_captures_sign = 1; + } else { + num_captures = tag->num_captures; + num_captures_sign = 0; + } + skip = tag->skip; + if (tag->offset < 0) { + offset = -tag->offset; + offset_sign = 1; + } else { + offset = tag->offset; + offset_sign = 0; + } + exp_id = tag->exp_id; + + if (exp_id != 0) { + /* we encode either an exp_id or capture data */ + assert((num_captures == 0) && (skip == 0) && (offset == 0)); + + encoded_tag = TAG_EXP | (exp_id & 0xFF) << TAG_EXP_ID_SHIFT; + } else { + encoded_tag = TAG_CAP + | ((num_captures_sign & 0x00000001) << TAG_NUM_CAPTURES_SIGN_SHIFT) + | ((offset_sign & 0x00000001) << TAG_OFFSET_SIGN_SHIFT) + | ((num_captures & 0x000000FF) << TAG_NUM_CAPTURES_SHIFT) + | ((skip & 0x000000FF) << TAG_OFFSET_SHIFT) + | ((offset & 0x000000FF) << TAG_SKIP_SHIFT); + } + return encoded_tag; +} diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag_local.h b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag_local.h new file mode 100644 index 000000000..921e50a45 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag_local.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TAG_LOCAL_H_INCLUDED__ +#define __TAG_LOCAL_H_INCLUDED__ + +#include "tag_global.h" + +#define SH_CSS_MINIMUM_TAG_ID (-1) + +#endif /* __TAG_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag_private.h b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag_private.h new file mode 100644 index 000000000..b14f09ade --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/host/tag_private.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TAG_PRIVATE_H_INCLUDED__ +#define __TAG_PRIVATE_H_INCLUDED__ + +#endif /* __TAG_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_shared/queue_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/queue_global.h new file mode 100644 index 000000000..6ae453782 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/queue_global.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_GLOBAL_H_INCLUDED__ +#define __QUEUE_GLOBAL_H_INCLUDED__ + +#endif /* __QUEUE_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_shared/sw_event_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/sw_event_global.h new file mode 100644 index 000000000..b256ea19c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/sw_event_global.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SW_EVENT_GLOBAL_H_INCLUDED__ +#define __SW_EVENT_GLOBAL_H_INCLUDED__ + +#define MAX_NR_OF_PAYLOADS_PER_SW_EVENT 4 + +enum ia_css_psys_sw_event { + IA_CSS_PSYS_SW_EVENT_BUFFER_ENQUEUED, /* from host to SP */ + IA_CSS_PSYS_SW_EVENT_BUFFER_DEQUEUED, /* from SP to host */ + IA_CSS_PSYS_SW_EVENT_EVENT_DEQUEUED, /* from SP to host, one way only */ + IA_CSS_PSYS_SW_EVENT_START_STREAM, + IA_CSS_PSYS_SW_EVENT_STOP_STREAM, + IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY, + IA_CSS_PSYS_SW_EVENT_UNLOCK_RAW_BUFFER, + IA_CSS_PSYS_SW_EVENT_STAGE_ENABLE_DISABLE /* for extension state change enable/disable */ +}; + +enum ia_css_isys_sw_event { + IA_CSS_ISYS_SW_EVENT_EVENT_DEQUEUED +}; + +#endif /* __SW_EVENT_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_shared/tag_global.h b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/tag_global.h new file mode 100644 index 000000000..af5a47ace --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_shared/tag_global.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TAG_GLOBAL_H_INCLUDED__ +#define __TAG_GLOBAL_H_INCLUDED__ + +/* offsets for encoding/decoding the tag into an uint32_t */ + +#define TAG_CAP 1 +#define TAG_EXP 2 + +#define TAG_NUM_CAPTURES_SIGN_SHIFT 6 +#define TAG_OFFSET_SIGN_SHIFT 7 +#define TAG_NUM_CAPTURES_SHIFT 8 +#define TAG_OFFSET_SHIFT 16 +#define TAG_SKIP_SHIFT 24 + +#define TAG_EXP_ID_SHIFT 8 + +/* Data structure containing the tagging information which is used in + * continuous mode to specify which frames should be captured. + * num_captures The number of RAW frames to be processed to + * YUV. Setting this to -1 will make continuous + * capture run until it is stopped. + * skip Skip N frames in between captures. This can be + * used to select a slower capture frame rate than + * the sensor output frame rate. + * offset Start the RAW-to-YUV processing at RAW buffer + * with this offset. This allows the user to + * process RAW frames that were captured in the + * past or future. + * exp_id Exposure id of the RAW frame to tag. + * + * NOTE: Either exp_id = 0 or all other fields are 0 + * (so yeah, this could be a union) + */ + +struct sh_css_tag_descr { + int num_captures; + unsigned int skip; + int offset; + unsigned int exp_id; +}; + +#endif /* __TAG_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_streaming_to_mipi_types_hrt.h b/drivers/staging/media/atomisp/pci/hive_isp_css_streaming_to_mipi_types_hrt.h new file mode 100644 index 000000000..301dd9239 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_streaming_to_mipi_types_hrt.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_ +#define _hive_isp_css_streaming_to_mipi_types_hrt_h_ + +#include + +#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1) +#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1) + +#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS) +#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH) + +#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */ diff --git a/drivers/staging/media/atomisp/pci/hive_types.h b/drivers/staging/media/atomisp/pci/hive_types.h new file mode 100644 index 000000000..55d36931f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hive_types.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_HIVE_TYPES_H +#define _HRT_HIVE_TYPES_H + +#include "version.h" +#include "defs.h" + +#ifndef HRTCAT3 +#define _HRTCAT3(m, n, o) m##n##o +#define HRTCAT3(m, n, o) _HRTCAT3(m, n, o) +#endif + +#ifndef HRTCAT4 +#define _HRTCAT4(m, n, o, p) m##n##o##p +#define HRTCAT4(m, n, o, p) _HRTCAT4(m, n, o, p) +#endif + +#ifndef HRTMIN +#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +/* boolean data type */ +typedef unsigned int hive_bool; +#define hive_false 0 +#define hive_true 1 + +typedef signed char hive_int8; +typedef short hive_int16; +typedef int hive_int32; +typedef long long hive_int64; + +typedef unsigned char hive_uint8; +typedef unsigned short hive_uint16; +typedef unsigned int hive_uint32; +typedef unsigned long long hive_uint64; + +#define HRT_DATA_WIDTH 32 +#define HRT_ADDRESS_WIDTH 64 +#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8) +#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8) +#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3) + +typedef hive_uint32 hrt_data; +typedef hive_uint64 hrt_address; + +/* use 64 bit addresses in simulation, where possible */ +typedef hive_uint64 hive_sim_address; + +/* below is for csim, not for hrt, rename and move this elsewhere */ + +typedef unsigned int hive_uint; +typedef hive_uint32 hive_address; +typedef hive_address hive_slave_address; +typedef hive_address hive_mem_address; + +/* MMIO devices */ +typedef hive_uint hive_mmio_id; +typedef hive_mmio_id hive_slave_id; +typedef hive_mmio_id hive_port_id; +typedef hive_mmio_id hive_master_id; +typedef hive_mmio_id hive_mem_id; +typedef hive_mmio_id hive_dev_id; +typedef hive_mmio_id hive_fifo_id; + +typedef hive_uint hive_hier_id; +typedef hive_hier_id hive_device_id; +typedef hive_device_id hive_proc_id; +typedef hive_device_id hive_cell_id; +typedef hive_device_id hive_host_id; +typedef hive_device_id hive_bus_id; +typedef hive_device_id hive_bridge_id; +typedef hive_device_id hive_fifo_adapter_id; +typedef hive_device_id hive_custom_device_id; + +typedef hive_uint hive_slot_id; +typedef hive_uint hive_fu_id; +typedef hive_uint hive_reg_file_id; +typedef hive_uint hive_reg_id; + +/* Streaming devices */ +typedef hive_uint hive_outport_id; +typedef hive_uint hive_inport_id; + +typedef hive_uint hive_msink_id; + +/* HRT specific */ +typedef char *hive_program; +typedef char *hive_function; + +#endif /* _HRT_HIVE_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/hmm/hmm.c b/drivers/staging/media/atomisp/pci/hmm/hmm.c new file mode 100644 index 000000000..bb12644fd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hmm/hmm.c @@ -0,0 +1,606 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +/* + * This file contains entry functions for memory management of ISP driver + */ +#include +#include +#include +#include /* for kmap */ +#include /* for page_to_phys */ +#include + +#include "hmm/hmm.h" +#include "hmm/hmm_bo.h" + +#include "atomisp_internal.h" +#include "asm/cacheflush.h" +#include "mmu/isp_mmu.h" +#include "mmu/sh_mmu_mrfld.h" + +struct hmm_bo_device bo_device; +static ia_css_ptr dummy_ptr = mmgr_EXCEPTION; +static bool hmm_initialized; + +/* + * p: private + * v: vmalloc + */ +static const char hmm_bo_type_string[] = "pv"; + +static ssize_t bo_show(struct device *dev, struct device_attribute *attr, + char *buf, struct list_head *bo_list, bool active) +{ + ssize_t ret = 0; + struct hmm_buffer_object *bo; + unsigned long flags; + int i; + long total[HMM_BO_LAST] = { 0 }; + long count[HMM_BO_LAST] = { 0 }; + int index1 = 0; + int index2 = 0; + + ret = scnprintf(buf, PAGE_SIZE, "type pgnr\n"); + if (ret <= 0) + return 0; + + index1 += ret; + + spin_lock_irqsave(&bo_device.list_lock, flags); + list_for_each_entry(bo, bo_list, list) { + if ((active && (bo->status & HMM_BO_ALLOCED)) || + (!active && !(bo->status & HMM_BO_ALLOCED))) { + ret = scnprintf(buf + index1, PAGE_SIZE - index1, + "%c %d\n", + hmm_bo_type_string[bo->type], bo->pgnr); + + total[bo->type] += bo->pgnr; + count[bo->type]++; + if (ret > 0) + index1 += ret; + } + } + spin_unlock_irqrestore(&bo_device.list_lock, flags); + + for (i = 0; i < HMM_BO_LAST; i++) { + if (count[i]) { + ret = scnprintf(buf + index1 + index2, + PAGE_SIZE - index1 - index2, + "%ld %c buffer objects: %ld KB\n", + count[i], hmm_bo_type_string[i], + total[i] * 4); + if (ret > 0) + index2 += ret; + } + } + + /* Add trailing zero, not included by scnprintf */ + return index1 + index2 + 1; +} + +static ssize_t active_bo_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return bo_show(dev, attr, buf, &bo_device.entire_bo_list, true); +} + +static ssize_t free_bo_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return bo_show(dev, attr, buf, &bo_device.entire_bo_list, false); +} + + +static DEVICE_ATTR_RO(active_bo); +static DEVICE_ATTR_RO(free_bo); + +static struct attribute *sysfs_attrs_ctrl[] = { + &dev_attr_active_bo.attr, + &dev_attr_free_bo.attr, + NULL +}; + +static struct attribute_group atomisp_attribute_group[] = { + {.attrs = sysfs_attrs_ctrl }, +}; + +int hmm_init(void) +{ + int ret; + + ret = hmm_bo_device_init(&bo_device, &sh_mmu_mrfld, + ISP_VM_START, ISP_VM_SIZE); + if (ret) + dev_err(atomisp_dev, "hmm_bo_device_init failed.\n"); + + hmm_initialized = true; + + /* + * As hmm use NULL to indicate invalid ISP virtual address, + * and ISP_VM_START is defined to 0 too, so we allocate + * one piece of dummy memory, which should return value 0, + * at the beginning, to avoid hmm_alloc return 0 in the + * further allocation. + */ + dummy_ptr = hmm_alloc(1); + + if (!ret) { + ret = sysfs_create_group(&atomisp_dev->kobj, + atomisp_attribute_group); + if (ret) + dev_err(atomisp_dev, + "%s Failed to create sysfs\n", __func__); + } + + return ret; +} + +void hmm_cleanup(void) +{ + if (dummy_ptr == mmgr_EXCEPTION) + return; + sysfs_remove_group(&atomisp_dev->kobj, atomisp_attribute_group); + + /* free dummy memory first */ + hmm_free(dummy_ptr); + dummy_ptr = 0; + + hmm_bo_device_exit(&bo_device); + hmm_initialized = false; +} + +static ia_css_ptr __hmm_alloc(size_t bytes, enum hmm_bo_type type, + void *vmalloc_addr) +{ + unsigned int pgnr; + struct hmm_buffer_object *bo; + int ret; + + /* + * Check if we are initialized. In the ideal world we wouldn't need + * this but we can tackle it once the driver is a lot cleaner + */ + + if (!hmm_initialized) + hmm_init(); + /* Get page number from size */ + pgnr = size_to_pgnr_ceil(bytes); + + /* Buffer object structure init */ + bo = hmm_bo_alloc(&bo_device, pgnr); + if (!bo) { + dev_err(atomisp_dev, "hmm_bo_create failed.\n"); + goto create_bo_err; + } + + /* Allocate pages for memory */ + ret = hmm_bo_alloc_pages(bo, type, vmalloc_addr); + if (ret) { + dev_err(atomisp_dev, "hmm_bo_alloc_pages failed.\n"); + goto alloc_page_err; + } + + /* Combine the virtual address and pages together */ + ret = hmm_bo_bind(bo); + if (ret) { + dev_err(atomisp_dev, "hmm_bo_bind failed.\n"); + goto bind_err; + } + + dev_dbg(atomisp_dev, "pages: 0x%08x (%zu bytes), type: %d, vmalloc %p\n", + bo->start, bytes, type, vmalloc); + + return bo->start; + +bind_err: + hmm_bo_free_pages(bo); +alloc_page_err: + hmm_bo_unref(bo); +create_bo_err: + return 0; +} + +ia_css_ptr hmm_alloc(size_t bytes) +{ + return __hmm_alloc(bytes, HMM_BO_PRIVATE, NULL); +} + +ia_css_ptr hmm_create_from_vmalloc_buf(size_t bytes, void *vmalloc_addr) +{ + return __hmm_alloc(bytes, HMM_BO_VMALLOC, vmalloc_addr); +} + +void hmm_free(ia_css_ptr virt) +{ + struct hmm_buffer_object *bo; + + dev_dbg(atomisp_dev, "%s: free 0x%08x\n", __func__, virt); + + if (WARN_ON(virt == mmgr_EXCEPTION)) + return; + + bo = hmm_bo_device_search_start(&bo_device, (unsigned int)virt); + + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object start with address 0x%x\n", + (unsigned int)virt); + return; + } + + hmm_bo_unbind(bo); + hmm_bo_free_pages(bo); + hmm_bo_unref(bo); +} + +static inline int hmm_check_bo(struct hmm_buffer_object *bo, unsigned int ptr) +{ + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + ptr); + return -EINVAL; + } + + if (!hmm_bo_page_allocated(bo)) { + dev_err(atomisp_dev, + "buffer object has no page allocated.\n"); + return -EINVAL; + } + + if (!hmm_bo_allocated(bo)) { + dev_err(atomisp_dev, + "buffer object has no virtual address space allocated.\n"); + return -EINVAL; + } + + return 0; +} + +/* Read function in ISP memory management */ +static int load_and_flush_by_kmap(ia_css_ptr virt, void *data, + unsigned int bytes) +{ + struct hmm_buffer_object *bo; + unsigned int idx, offset, len; + char *src, *des; + int ret; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + ret = hmm_check_bo(bo, virt); + if (ret) + return ret; + + des = (char *)data; + while (bytes) { + idx = (virt - bo->start) >> PAGE_SHIFT; + offset = (virt - bo->start) - (idx << PAGE_SHIFT); + + src = (char *)kmap_local_page(bo->pages[idx]) + offset; + + if ((bytes + offset) >= PAGE_SIZE) { + len = PAGE_SIZE - offset; + bytes -= len; + } else { + len = bytes; + bytes = 0; + } + + virt += len; /* update virt for next loop */ + + if (des) { + memcpy(des, src, len); + des += len; + } + + clflush_cache_range(src, len); + + kunmap_local(src); + } + + return 0; +} + +/* Read function in ISP memory management */ +static int load_and_flush(ia_css_ptr virt, void *data, unsigned int bytes) +{ + struct hmm_buffer_object *bo; + int ret; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + ret = hmm_check_bo(bo, virt); + if (ret) + return ret; + + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + void *src = bo->vmap_addr; + + src += (virt - bo->start); + memcpy(data, src, bytes); + if (bo->status & HMM_BO_VMAPED_CACHED) + clflush_cache_range(src, bytes); + } else { + void *vptr; + + vptr = hmm_bo_vmap(bo, true); + if (!vptr) + return load_and_flush_by_kmap(virt, data, bytes); + else + vptr = vptr + (virt - bo->start); + + memcpy(data, vptr, bytes); + clflush_cache_range(vptr, bytes); + hmm_bo_vunmap(bo); + } + + return 0; +} + +/* Read function in ISP memory management */ +int hmm_load(ia_css_ptr virt, void *data, unsigned int bytes) +{ + if (!virt) { + dev_warn(atomisp_dev, + "hmm_store: address is NULL\n"); + return -EINVAL; + } + if (!data) { + dev_err(atomisp_dev, + "hmm_store: data is a NULL argument\n"); + return -EINVAL; + } + return load_and_flush(virt, data, bytes); +} + +/* Flush hmm data from the data cache */ +int hmm_flush(ia_css_ptr virt, unsigned int bytes) +{ + return load_and_flush(virt, NULL, bytes); +} + +/* Write function in ISP memory management */ +int hmm_store(ia_css_ptr virt, const void *data, unsigned int bytes) +{ + struct hmm_buffer_object *bo; + unsigned int idx, offset, len; + char *src, *des; + int ret; + + if (!virt) { + dev_warn(atomisp_dev, + "hmm_store: address is NULL\n"); + return -EINVAL; + } + if (!data) { + dev_err(atomisp_dev, + "hmm_store: data is a NULL argument\n"); + return -EINVAL; + } + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + ret = hmm_check_bo(bo, virt); + if (ret) + return ret; + + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + void *dst = bo->vmap_addr; + + dst += (virt - bo->start); + memcpy(dst, data, bytes); + if (bo->status & HMM_BO_VMAPED_CACHED) + clflush_cache_range(dst, bytes); + } else { + void *vptr; + + vptr = hmm_bo_vmap(bo, true); + if (vptr) { + vptr = vptr + (virt - bo->start); + + memcpy(vptr, data, bytes); + clflush_cache_range(vptr, bytes); + hmm_bo_vunmap(bo); + return 0; + } + } + + src = (char *)data; + while (bytes) { + idx = (virt - bo->start) >> PAGE_SHIFT; + offset = (virt - bo->start) - (idx << PAGE_SHIFT); + + des = (char *)kmap_local_page(bo->pages[idx]); + + if (!des) { + dev_err(atomisp_dev, + "kmap buffer object page failed: pg_idx = %d\n", + idx); + return -EINVAL; + } + + des += offset; + + if ((bytes + offset) >= PAGE_SIZE) { + len = PAGE_SIZE - offset; + bytes -= len; + } else { + len = bytes; + bytes = 0; + } + + virt += len; + + memcpy(des, src, len); + + src += len; + + clflush_cache_range(des, len); + + kunmap_local(des); + } + + return 0; +} + +/* memset function in ISP memory management */ +int hmm_set(ia_css_ptr virt, int c, unsigned int bytes) +{ + struct hmm_buffer_object *bo; + unsigned int idx, offset, len; + char *des; + int ret; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + ret = hmm_check_bo(bo, virt); + if (ret) + return ret; + + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + void *dst = bo->vmap_addr; + + dst += (virt - bo->start); + memset(dst, c, bytes); + + if (bo->status & HMM_BO_VMAPED_CACHED) + clflush_cache_range(dst, bytes); + } else { + void *vptr; + + vptr = hmm_bo_vmap(bo, true); + if (vptr) { + vptr = vptr + (virt - bo->start); + memset(vptr, c, bytes); + clflush_cache_range(vptr, bytes); + hmm_bo_vunmap(bo); + return 0; + } + } + + while (bytes) { + idx = (virt - bo->start) >> PAGE_SHIFT; + offset = (virt - bo->start) - (idx << PAGE_SHIFT); + + des = (char *)kmap_local_page(bo->pages[idx]) + offset; + + if ((bytes + offset) >= PAGE_SIZE) { + len = PAGE_SIZE - offset; + bytes -= len; + } else { + len = bytes; + bytes = 0; + } + + virt += len; + + memset(des, c, len); + + clflush_cache_range(des, len); + + kunmap_local(des); + } + + return 0; +} + +/* Virtual address to physical address convert */ +phys_addr_t hmm_virt_to_phys(ia_css_ptr virt) +{ + unsigned int idx, offset; + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + virt); + return -1; + } + + idx = (virt - bo->start) >> PAGE_SHIFT; + offset = (virt - bo->start) - (idx << PAGE_SHIFT); + + return page_to_phys(bo->pages[idx]) + offset; +} + +int hmm_mmap(struct vm_area_struct *vma, ia_css_ptr virt) +{ + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_start(&bo_device, virt); + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object start with address 0x%x\n", + virt); + return -EINVAL; + } + + return hmm_bo_mmap(vma, bo); +} + +/* Map ISP virtual address into IA virtual address */ +void *hmm_vmap(ia_css_ptr virt, bool cached) +{ + struct hmm_buffer_object *bo; + void *ptr; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + virt); + return NULL; + } + + ptr = hmm_bo_vmap(bo, cached); + if (ptr) + return ptr + (virt - bo->start); + else + return NULL; +} + +/* Flush the memory which is mapped as cached memory through hmm_vmap */ +void hmm_flush_vmap(ia_css_ptr virt) +{ + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + if (!bo) { + dev_warn(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + virt); + return; + } + + hmm_bo_flush_vmap(bo); +} + +void hmm_vunmap(ia_css_ptr virt) +{ + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + if (!bo) { + dev_warn(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + virt); + return; + } + + hmm_bo_vunmap(bo); +} diff --git a/drivers/staging/media/atomisp/pci/hmm/hmm_bo.c b/drivers/staging/media/atomisp/pci/hmm/hmm_bo.c new file mode 100644 index 000000000..5e53eed8a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/hmm/hmm_bo.c @@ -0,0 +1,1087 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +/* + * This file contains functions for buffer object structure management + */ +#include +#include +#include /* for GFP_ATOMIC */ +#include +#include +#include +#include +#include /* for kmalloc */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "atomisp_internal.h" +#include "hmm/hmm_common.h" +#include "hmm/hmm_bo.h" + +static int __bo_init(struct hmm_bo_device *bdev, struct hmm_buffer_object *bo, + unsigned int pgnr) +{ + check_bodev_null_return(bdev, -EINVAL); + var_equal_return(hmm_bo_device_inited(bdev), 0, -EINVAL, + "hmm_bo_device not inited yet.\n"); + /* prevent zero size buffer object */ + if (pgnr == 0) { + dev_err(atomisp_dev, "0 size buffer is not allowed.\n"); + return -EINVAL; + } + + memset(bo, 0, sizeof(*bo)); + mutex_init(&bo->mutex); + + /* init the bo->list HEAD as an element of entire_bo_list */ + INIT_LIST_HEAD(&bo->list); + + bo->bdev = bdev; + bo->vmap_addr = NULL; + bo->status = HMM_BO_FREE; + bo->start = bdev->start; + bo->pgnr = pgnr; + bo->end = bo->start + pgnr_to_size(pgnr); + bo->prev = NULL; + bo->next = NULL; + + return 0; +} + +static struct hmm_buffer_object *__bo_search_and_remove_from_free_rbtree( + struct rb_node *node, unsigned int pgnr) +{ + struct hmm_buffer_object *this, *ret_bo, *temp_bo; + + this = rb_entry(node, struct hmm_buffer_object, node); + if (this->pgnr == pgnr || + (this->pgnr > pgnr && !this->node.rb_left)) { + goto remove_bo_and_return; + } else { + if (this->pgnr < pgnr) { + if (!this->node.rb_right) + return NULL; + ret_bo = __bo_search_and_remove_from_free_rbtree( + this->node.rb_right, pgnr); + } else { + ret_bo = __bo_search_and_remove_from_free_rbtree( + this->node.rb_left, pgnr); + } + if (!ret_bo) { + if (this->pgnr > pgnr) + goto remove_bo_and_return; + else + return NULL; + } + return ret_bo; + } + +remove_bo_and_return: + /* NOTE: All nodes on free rbtree have a 'prev' that points to NULL. + * 1. check if 'this->next' is NULL: + * yes: erase 'this' node and rebalance rbtree, return 'this'. + */ + if (!this->next) { + rb_erase(&this->node, &this->bdev->free_rbtree); + return this; + } + /* NOTE: if 'this->next' is not NULL, always return 'this->next' bo. + * 2. check if 'this->next->next' is NULL: + * yes: change the related 'next/prev' pointer, + * return 'this->next' but the rbtree stays unchanged. + */ + temp_bo = this->next; + this->next = temp_bo->next; + if (temp_bo->next) + temp_bo->next->prev = this; + temp_bo->next = NULL; + temp_bo->prev = NULL; + return temp_bo; +} + +static struct hmm_buffer_object *__bo_search_by_addr(struct rb_root *root, + ia_css_ptr start) +{ + struct rb_node *n = root->rb_node; + struct hmm_buffer_object *bo; + + do { + bo = rb_entry(n, struct hmm_buffer_object, node); + + if (bo->start > start) { + if (!n->rb_left) + return NULL; + n = n->rb_left; + } else if (bo->start < start) { + if (!n->rb_right) + return NULL; + n = n->rb_right; + } else { + return bo; + } + } while (n); + + return NULL; +} + +static struct hmm_buffer_object *__bo_search_by_addr_in_range( + struct rb_root *root, unsigned int start) +{ + struct rb_node *n = root->rb_node; + struct hmm_buffer_object *bo; + + do { + bo = rb_entry(n, struct hmm_buffer_object, node); + + if (bo->start > start) { + if (!n->rb_left) + return NULL; + n = n->rb_left; + } else { + if (bo->end > start) + return bo; + if (!n->rb_right) + return NULL; + n = n->rb_right; + } + } while (n); + + return NULL; +} + +static void __bo_insert_to_free_rbtree(struct rb_root *root, + struct hmm_buffer_object *bo) +{ + struct rb_node **new = &root->rb_node; + struct rb_node *parent = NULL; + struct hmm_buffer_object *this; + unsigned int pgnr = bo->pgnr; + + while (*new) { + parent = *new; + this = container_of(*new, struct hmm_buffer_object, node); + + if (pgnr < this->pgnr) { + new = &((*new)->rb_left); + } else if (pgnr > this->pgnr) { + new = &((*new)->rb_right); + } else { + bo->prev = this; + bo->next = this->next; + if (this->next) + this->next->prev = bo; + this->next = bo; + bo->status = (bo->status & ~HMM_BO_MASK) | HMM_BO_FREE; + return; + } + } + + bo->status = (bo->status & ~HMM_BO_MASK) | HMM_BO_FREE; + + rb_link_node(&bo->node, parent, new); + rb_insert_color(&bo->node, root); +} + +static void __bo_insert_to_alloc_rbtree(struct rb_root *root, + struct hmm_buffer_object *bo) +{ + struct rb_node **new = &root->rb_node; + struct rb_node *parent = NULL; + struct hmm_buffer_object *this; + unsigned int start = bo->start; + + while (*new) { + parent = *new; + this = container_of(*new, struct hmm_buffer_object, node); + + if (start < this->start) + new = &((*new)->rb_left); + else + new = &((*new)->rb_right); + } + + kref_init(&bo->kref); + bo->status = (bo->status & ~HMM_BO_MASK) | HMM_BO_ALLOCED; + + rb_link_node(&bo->node, parent, new); + rb_insert_color(&bo->node, root); +} + +static struct hmm_buffer_object *__bo_break_up(struct hmm_bo_device *bdev, + struct hmm_buffer_object *bo, + unsigned int pgnr) +{ + struct hmm_buffer_object *new_bo; + unsigned long flags; + int ret; + + new_bo = kmem_cache_alloc(bdev->bo_cache, GFP_KERNEL); + if (!new_bo) { + dev_err(atomisp_dev, "%s: __bo_alloc failed!\n", __func__); + return NULL; + } + ret = __bo_init(bdev, new_bo, pgnr); + if (ret) { + dev_err(atomisp_dev, "%s: __bo_init failed!\n", __func__); + kmem_cache_free(bdev->bo_cache, new_bo); + return NULL; + } + + new_bo->start = bo->start; + new_bo->end = new_bo->start + pgnr_to_size(pgnr); + bo->start = new_bo->end; + bo->pgnr = bo->pgnr - pgnr; + + spin_lock_irqsave(&bdev->list_lock, flags); + list_add_tail(&new_bo->list, &bo->list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + return new_bo; +} + +static void __bo_take_off_handling(struct hmm_buffer_object *bo) +{ + struct hmm_bo_device *bdev = bo->bdev; + /* There are 4 situations when we take off a known bo from free rbtree: + * 1. if bo->next && bo->prev == NULL, bo is a rbtree node + * and does not have a linked list after bo, to take off this bo, + * we just need erase bo directly and rebalance the free rbtree + */ + if (!bo->prev && !bo->next) { + rb_erase(&bo->node, &bdev->free_rbtree); + /* 2. when bo->next != NULL && bo->prev == NULL, bo is a rbtree node, + * and has a linked list,to take off this bo we need erase bo + * first, then, insert bo->next into free rbtree and rebalance + * the free rbtree + */ + } else if (!bo->prev && bo->next) { + bo->next->prev = NULL; + rb_erase(&bo->node, &bdev->free_rbtree); + __bo_insert_to_free_rbtree(&bdev->free_rbtree, bo->next); + bo->next = NULL; + /* 3. when bo->prev != NULL && bo->next == NULL, bo is not a rbtree + * node, bo is the last element of the linked list after rbtree + * node, to take off this bo, we just need set the "prev/next" + * pointers to NULL, the free rbtree stays unchaged + */ + } else if (bo->prev && !bo->next) { + bo->prev->next = NULL; + bo->prev = NULL; + /* 4. when bo->prev != NULL && bo->next != NULL ,bo is not a rbtree + * node, bo is in the middle of the linked list after rbtree node, + * to take off this bo, we just set take the "prev/next" pointers + * to NULL, the free rbtree stays unchaged + */ + } else if (bo->prev && bo->next) { + bo->next->prev = bo->prev; + bo->prev->next = bo->next; + bo->next = NULL; + bo->prev = NULL; + } +} + +static struct hmm_buffer_object *__bo_merge(struct hmm_buffer_object *bo, + struct hmm_buffer_object *next_bo) +{ + struct hmm_bo_device *bdev; + unsigned long flags; + + bdev = bo->bdev; + next_bo->start = bo->start; + next_bo->pgnr = next_bo->pgnr + bo->pgnr; + + spin_lock_irqsave(&bdev->list_lock, flags); + list_del(&bo->list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + kmem_cache_free(bo->bdev->bo_cache, bo); + + return next_bo; +} + +/* + * hmm_bo_device functions. + */ +int hmm_bo_device_init(struct hmm_bo_device *bdev, + struct isp_mmu_client *mmu_driver, + unsigned int vaddr_start, + unsigned int size) +{ + struct hmm_buffer_object *bo; + unsigned long flags; + int ret; + + check_bodev_null_return(bdev, -EINVAL); + + ret = isp_mmu_init(&bdev->mmu, mmu_driver); + if (ret) { + dev_err(atomisp_dev, "isp_mmu_init failed.\n"); + return ret; + } + + bdev->start = vaddr_start; + bdev->pgnr = size_to_pgnr_ceil(size); + bdev->size = pgnr_to_size(bdev->pgnr); + + spin_lock_init(&bdev->list_lock); + mutex_init(&bdev->rbtree_mutex); + + bdev->flag = HMM_BO_DEVICE_INITED; + + INIT_LIST_HEAD(&bdev->entire_bo_list); + bdev->allocated_rbtree = RB_ROOT; + bdev->free_rbtree = RB_ROOT; + + bdev->bo_cache = kmem_cache_create("bo_cache", + sizeof(struct hmm_buffer_object), 0, 0, NULL); + if (!bdev->bo_cache) { + dev_err(atomisp_dev, "%s: create cache failed!\n", __func__); + isp_mmu_exit(&bdev->mmu); + return -ENOMEM; + } + + bo = kmem_cache_alloc(bdev->bo_cache, GFP_KERNEL); + if (!bo) { + dev_err(atomisp_dev, "%s: __bo_alloc failed!\n", __func__); + isp_mmu_exit(&bdev->mmu); + return -ENOMEM; + } + + ret = __bo_init(bdev, bo, bdev->pgnr); + if (ret) { + dev_err(atomisp_dev, "%s: __bo_init failed!\n", __func__); + kmem_cache_free(bdev->bo_cache, bo); + isp_mmu_exit(&bdev->mmu); + return -EINVAL; + } + + spin_lock_irqsave(&bdev->list_lock, flags); + list_add_tail(&bo->list, &bdev->entire_bo_list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + __bo_insert_to_free_rbtree(&bdev->free_rbtree, bo); + + return 0; +} + +struct hmm_buffer_object *hmm_bo_alloc(struct hmm_bo_device *bdev, + unsigned int pgnr) +{ + struct hmm_buffer_object *bo, *new_bo; + struct rb_root *root = &bdev->free_rbtree; + + check_bodev_null_return(bdev, NULL); + var_equal_return(hmm_bo_device_inited(bdev), 0, NULL, + "hmm_bo_device not inited yet.\n"); + + if (pgnr == 0) { + dev_err(atomisp_dev, "0 size buffer is not allowed.\n"); + return NULL; + } + + mutex_lock(&bdev->rbtree_mutex); + bo = __bo_search_and_remove_from_free_rbtree(root->rb_node, pgnr); + if (!bo) { + mutex_unlock(&bdev->rbtree_mutex); + dev_err(atomisp_dev, "%s: Out of Memory! hmm_bo_alloc failed", + __func__); + return NULL; + } + + if (bo->pgnr > pgnr) { + new_bo = __bo_break_up(bdev, bo, pgnr); + if (!new_bo) { + mutex_unlock(&bdev->rbtree_mutex); + dev_err(atomisp_dev, "%s: __bo_break_up failed!\n", + __func__); + return NULL; + } + + __bo_insert_to_alloc_rbtree(&bdev->allocated_rbtree, new_bo); + __bo_insert_to_free_rbtree(&bdev->free_rbtree, bo); + + mutex_unlock(&bdev->rbtree_mutex); + return new_bo; + } + + __bo_insert_to_alloc_rbtree(&bdev->allocated_rbtree, bo); + + mutex_unlock(&bdev->rbtree_mutex); + return bo; +} + +void hmm_bo_release(struct hmm_buffer_object *bo) +{ + struct hmm_bo_device *bdev = bo->bdev; + struct hmm_buffer_object *next_bo, *prev_bo; + + mutex_lock(&bdev->rbtree_mutex); + + /* + * FIX ME: + * + * how to destroy the bo when it is stilled MMAPED? + * + * ideally, this will not happened as hmm_bo_release + * will only be called when kref reaches 0, and in mmap + * operation the hmm_bo_ref will eventually be called. + * so, if this happened, something goes wrong. + */ + if (bo->status & HMM_BO_MMAPED) { + mutex_unlock(&bdev->rbtree_mutex); + dev_dbg(atomisp_dev, "destroy bo which is MMAPED, do nothing\n"); + return; + } + + if (bo->status & HMM_BO_BINDED) { + dev_warn(atomisp_dev, "the bo is still binded, unbind it first...\n"); + hmm_bo_unbind(bo); + } + + if (bo->status & HMM_BO_PAGE_ALLOCED) { + dev_warn(atomisp_dev, "the pages is not freed, free pages first\n"); + hmm_bo_free_pages(bo); + } + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + dev_warn(atomisp_dev, "the vunmap is not done, do it...\n"); + hmm_bo_vunmap(bo); + } + + rb_erase(&bo->node, &bdev->allocated_rbtree); + + prev_bo = list_entry(bo->list.prev, struct hmm_buffer_object, list); + next_bo = list_entry(bo->list.next, struct hmm_buffer_object, list); + + if (bo->list.prev != &bdev->entire_bo_list && + prev_bo->end == bo->start && + (prev_bo->status & HMM_BO_MASK) == HMM_BO_FREE) { + __bo_take_off_handling(prev_bo); + bo = __bo_merge(prev_bo, bo); + } + + if (bo->list.next != &bdev->entire_bo_list && + next_bo->start == bo->end && + (next_bo->status & HMM_BO_MASK) == HMM_BO_FREE) { + __bo_take_off_handling(next_bo); + bo = __bo_merge(bo, next_bo); + } + + __bo_insert_to_free_rbtree(&bdev->free_rbtree, bo); + + mutex_unlock(&bdev->rbtree_mutex); + return; +} + +void hmm_bo_device_exit(struct hmm_bo_device *bdev) +{ + struct hmm_buffer_object *bo; + unsigned long flags; + + dev_dbg(atomisp_dev, "%s: entering!\n", __func__); + + check_bodev_null_return_void(bdev); + + /* + * release all allocated bos even they a in use + * and all bos will be merged into a big bo + */ + while (!RB_EMPTY_ROOT(&bdev->allocated_rbtree)) + hmm_bo_release( + rbtree_node_to_hmm_bo(bdev->allocated_rbtree.rb_node)); + + dev_dbg(atomisp_dev, "%s: finished releasing all allocated bos!\n", + __func__); + + /* free all bos to release all ISP virtual memory */ + while (!list_empty(&bdev->entire_bo_list)) { + bo = list_to_hmm_bo(bdev->entire_bo_list.next); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_del(&bo->list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + kmem_cache_free(bdev->bo_cache, bo); + } + + dev_dbg(atomisp_dev, "%s: finished to free all bos!\n", __func__); + + kmem_cache_destroy(bdev->bo_cache); + + isp_mmu_exit(&bdev->mmu); +} + +int hmm_bo_device_inited(struct hmm_bo_device *bdev) +{ + check_bodev_null_return(bdev, -EINVAL); + + return bdev->flag == HMM_BO_DEVICE_INITED; +} + +int hmm_bo_allocated(struct hmm_buffer_object *bo) +{ + check_bo_null_return(bo, 0); + + return bo->status & HMM_BO_ALLOCED; +} + +struct hmm_buffer_object *hmm_bo_device_search_start( + struct hmm_bo_device *bdev, ia_css_ptr vaddr) +{ + struct hmm_buffer_object *bo; + + check_bodev_null_return(bdev, NULL); + + mutex_lock(&bdev->rbtree_mutex); + bo = __bo_search_by_addr(&bdev->allocated_rbtree, vaddr); + if (!bo) { + mutex_unlock(&bdev->rbtree_mutex); + dev_err(atomisp_dev, "%s can not find bo with addr: 0x%x\n", + __func__, vaddr); + return NULL; + } + mutex_unlock(&bdev->rbtree_mutex); + + return bo; +} + +struct hmm_buffer_object *hmm_bo_device_search_in_range( + struct hmm_bo_device *bdev, unsigned int vaddr) +{ + struct hmm_buffer_object *bo; + + check_bodev_null_return(bdev, NULL); + + mutex_lock(&bdev->rbtree_mutex); + bo = __bo_search_by_addr_in_range(&bdev->allocated_rbtree, vaddr); + if (!bo) { + mutex_unlock(&bdev->rbtree_mutex); + dev_err(atomisp_dev, "%s can not find bo contain addr: 0x%x\n", + __func__, vaddr); + return NULL; + } + mutex_unlock(&bdev->rbtree_mutex); + + return bo; +} + +struct hmm_buffer_object *hmm_bo_device_search_vmap_start( + struct hmm_bo_device *bdev, const void *vaddr) +{ + struct list_head *pos; + struct hmm_buffer_object *bo; + unsigned long flags; + + check_bodev_null_return(bdev, NULL); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_for_each(pos, &bdev->entire_bo_list) { + bo = list_to_hmm_bo(pos); + /* pass bo which has no vm_node allocated */ + if ((bo->status & HMM_BO_MASK) == HMM_BO_FREE) + continue; + if (bo->vmap_addr == vaddr) + goto found; + } + spin_unlock_irqrestore(&bdev->list_lock, flags); + return NULL; +found: + spin_unlock_irqrestore(&bdev->list_lock, flags); + return bo; +} + +static void free_pages_bulk_array(unsigned long nr_pages, struct page **page_array) +{ + unsigned long i; + + for (i = 0; i < nr_pages; i++) + __free_pages(page_array[i], 0); +} + +static void free_private_bo_pages(struct hmm_buffer_object *bo) +{ + set_pages_array_wb(bo->pages, bo->pgnr); + free_pages_bulk_array(bo->pgnr, bo->pages); +} + +/*Allocate pages which will be used only by ISP*/ +static int alloc_private_pages(struct hmm_buffer_object *bo) +{ + const gfp_t gfp = __GFP_NOWARN | __GFP_RECLAIM | __GFP_FS; + int ret; + + ret = alloc_pages_bulk_array(gfp, bo->pgnr, bo->pages); + if (ret != bo->pgnr) { + free_pages_bulk_array(ret, bo->pages); + dev_err(atomisp_dev, "alloc_pages_bulk_array() failed\n"); + return -ENOMEM; + } + + ret = set_pages_array_uc(bo->pages, bo->pgnr); + if (ret) { + dev_err(atomisp_dev, "set pages uncacheable failed.\n"); + free_pages_bulk_array(bo->pgnr, bo->pages); + return ret; + } + + return 0; +} + +static int alloc_vmalloc_pages(struct hmm_buffer_object *bo, void *vmalloc_addr) +{ + void *vaddr = vmalloc_addr; + int i; + + for (i = 0; i < bo->pgnr; i++) { + bo->pages[i] = vmalloc_to_page(vaddr); + if (!bo->pages[i]) { + dev_err(atomisp_dev, "Error could not get page %d of vmalloc buf\n", i); + return -ENOMEM; + } + vaddr += PAGE_SIZE; + } + + return 0; +} + +/* + * allocate/free physical pages for the bo. + * + * type indicate where are the pages from. currently we have 3 types + * of memory: HMM_BO_PRIVATE, HMM_BO_VMALLOC. + * + * vmalloc_addr is only valid when type is HMM_BO_VMALLOC. + */ +int hmm_bo_alloc_pages(struct hmm_buffer_object *bo, + enum hmm_bo_type type, + void *vmalloc_addr) +{ + int ret = -EINVAL; + + check_bo_null_return(bo, -EINVAL); + + mutex_lock(&bo->mutex); + check_bo_status_no_goto(bo, HMM_BO_PAGE_ALLOCED, status_err); + + bo->pages = kcalloc(bo->pgnr, sizeof(struct page *), GFP_KERNEL); + if (unlikely(!bo->pages)) { + ret = -ENOMEM; + goto alloc_err; + } + + if (type == HMM_BO_PRIVATE) { + ret = alloc_private_pages(bo); + } else if (type == HMM_BO_VMALLOC) { + ret = alloc_vmalloc_pages(bo, vmalloc_addr); + } else { + dev_err(atomisp_dev, "invalid buffer type.\n"); + ret = -EINVAL; + } + if (ret) + goto alloc_err; + + bo->type = type; + + bo->status |= HMM_BO_PAGE_ALLOCED; + + mutex_unlock(&bo->mutex); + + return 0; + +alloc_err: + kfree(bo->pages); + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, "alloc pages err...\n"); + return ret; +status_err: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "buffer object has already page allocated.\n"); + return -EINVAL; +} + +/* + * free physical pages of the bo. + */ +void hmm_bo_free_pages(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + mutex_lock(&bo->mutex); + + check_bo_status_yes_goto(bo, HMM_BO_PAGE_ALLOCED, status_err2); + + /* clear the flag anyway. */ + bo->status &= (~HMM_BO_PAGE_ALLOCED); + + if (bo->type == HMM_BO_PRIVATE) + free_private_bo_pages(bo); + else if (bo->type == HMM_BO_VMALLOC) + ; /* No-op, nothing to do */ + else + dev_err(atomisp_dev, "invalid buffer type.\n"); + + kfree(bo->pages); + mutex_unlock(&bo->mutex); + + return; + +status_err2: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "buffer object not page allocated yet.\n"); +} + +int hmm_bo_page_allocated(struct hmm_buffer_object *bo) +{ + check_bo_null_return(bo, 0); + + return bo->status & HMM_BO_PAGE_ALLOCED; +} + +/* + * bind the physical pages to a virtual address space. + */ +int hmm_bo_bind(struct hmm_buffer_object *bo) +{ + int ret; + unsigned int virt; + struct hmm_bo_device *bdev; + unsigned int i; + + check_bo_null_return(bo, -EINVAL); + + mutex_lock(&bo->mutex); + + check_bo_status_yes_goto(bo, + HMM_BO_PAGE_ALLOCED | HMM_BO_ALLOCED, + status_err1); + + check_bo_status_no_goto(bo, HMM_BO_BINDED, status_err2); + + bdev = bo->bdev; + + virt = bo->start; + + for (i = 0; i < bo->pgnr; i++) { + ret = + isp_mmu_map(&bdev->mmu, virt, + page_to_phys(bo->pages[i]), 1); + if (ret) + goto map_err; + virt += (1 << PAGE_SHIFT); + } + + /* + * flush TBL here. + * + * theoretically, we donot need to flush TLB as we didnot change + * any existed address mappings, but for Silicon Hive's MMU, its + * really a bug here. I guess when fetching PTEs (page table entity) + * to TLB, its MMU will fetch additional INVALID PTEs automatically + * for performance issue. EX, we only set up 1 page address mapping, + * meaning updating 1 PTE, but the MMU fetches 4 PTE at one time, + * so the additional 3 PTEs are invalid. + */ + if (bo->start != 0x0) + isp_mmu_flush_tlb_range(&bdev->mmu, bo->start, + (bo->pgnr << PAGE_SHIFT)); + + bo->status |= HMM_BO_BINDED; + + mutex_unlock(&bo->mutex); + + return 0; + +map_err: + /* unbind the physical pages with related virtual address space */ + virt = bo->start; + for ( ; i > 0; i--) { + isp_mmu_unmap(&bdev->mmu, virt, 1); + virt += pgnr_to_size(1); + } + + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "setup MMU address mapping failed.\n"); + return ret; + +status_err2: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, "buffer object already binded.\n"); + return -EINVAL; +status_err1: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "buffer object vm_node or page not allocated.\n"); + return -EINVAL; +} + +/* + * unbind the physical pages with related virtual address space. + */ +void hmm_bo_unbind(struct hmm_buffer_object *bo) +{ + unsigned int virt; + struct hmm_bo_device *bdev; + unsigned int i; + + check_bo_null_return_void(bo); + + mutex_lock(&bo->mutex); + + check_bo_status_yes_goto(bo, + HMM_BO_PAGE_ALLOCED | + HMM_BO_ALLOCED | + HMM_BO_BINDED, status_err); + + bdev = bo->bdev; + + virt = bo->start; + + for (i = 0; i < bo->pgnr; i++) { + isp_mmu_unmap(&bdev->mmu, virt, 1); + virt += pgnr_to_size(1); + } + + /* + * flush TLB as the address mapping has been removed and + * related TLBs should be invalidated. + */ + isp_mmu_flush_tlb_range(&bdev->mmu, bo->start, + (bo->pgnr << PAGE_SHIFT)); + + bo->status &= (~HMM_BO_BINDED); + + mutex_unlock(&bo->mutex); + + return; + +status_err: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "buffer vm or page not allocated or not binded yet.\n"); +} + +int hmm_bo_binded(struct hmm_buffer_object *bo) +{ + int ret; + + check_bo_null_return(bo, 0); + + mutex_lock(&bo->mutex); + + ret = bo->status & HMM_BO_BINDED; + + mutex_unlock(&bo->mutex); + + return ret; +} + +void *hmm_bo_vmap(struct hmm_buffer_object *bo, bool cached) +{ + check_bo_null_return(bo, NULL); + + mutex_lock(&bo->mutex); + if (((bo->status & HMM_BO_VMAPED) && !cached) || + ((bo->status & HMM_BO_VMAPED_CACHED) && cached)) { + mutex_unlock(&bo->mutex); + return bo->vmap_addr; + } + + /* cached status need to be changed, so vunmap first */ + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + vunmap(bo->vmap_addr); + bo->vmap_addr = NULL; + bo->status &= ~(HMM_BO_VMAPED | HMM_BO_VMAPED_CACHED); + } + + bo->vmap_addr = vmap(bo->pages, bo->pgnr, VM_MAP, + cached ? PAGE_KERNEL : PAGE_KERNEL_NOCACHE); + if (unlikely(!bo->vmap_addr)) { + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, "vmap failed...\n"); + return NULL; + } + bo->status |= (cached ? HMM_BO_VMAPED_CACHED : HMM_BO_VMAPED); + + mutex_unlock(&bo->mutex); + return bo->vmap_addr; +} + +void hmm_bo_flush_vmap(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + mutex_lock(&bo->mutex); + if (!(bo->status & HMM_BO_VMAPED_CACHED) || !bo->vmap_addr) { + mutex_unlock(&bo->mutex); + return; + } + + clflush_cache_range(bo->vmap_addr, bo->pgnr * PAGE_SIZE); + mutex_unlock(&bo->mutex); +} + +void hmm_bo_vunmap(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + mutex_lock(&bo->mutex); + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + vunmap(bo->vmap_addr); + bo->vmap_addr = NULL; + bo->status &= ~(HMM_BO_VMAPED | HMM_BO_VMAPED_CACHED); + } + + mutex_unlock(&bo->mutex); + return; +} + +void hmm_bo_ref(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + kref_get(&bo->kref); +} + +static void kref_hmm_bo_release(struct kref *kref) +{ + if (!kref) + return; + + hmm_bo_release(kref_to_hmm_bo(kref)); +} + +void hmm_bo_unref(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + kref_put(&bo->kref, kref_hmm_bo_release); +} + +static void hmm_bo_vm_open(struct vm_area_struct *vma) +{ + struct hmm_buffer_object *bo = + (struct hmm_buffer_object *)vma->vm_private_data; + + check_bo_null_return_void(bo); + + hmm_bo_ref(bo); + + mutex_lock(&bo->mutex); + + bo->status |= HMM_BO_MMAPED; + + bo->mmap_count++; + + mutex_unlock(&bo->mutex); +} + +static void hmm_bo_vm_close(struct vm_area_struct *vma) +{ + struct hmm_buffer_object *bo = + (struct hmm_buffer_object *)vma->vm_private_data; + + check_bo_null_return_void(bo); + + hmm_bo_unref(bo); + + mutex_lock(&bo->mutex); + + bo->mmap_count--; + + if (!bo->mmap_count) { + bo->status &= (~HMM_BO_MMAPED); + vma->vm_private_data = NULL; + } + + mutex_unlock(&bo->mutex); +} + +static const struct vm_operations_struct hmm_bo_vm_ops = { + .open = hmm_bo_vm_open, + .close = hmm_bo_vm_close, +}; + +/* + * mmap the bo to user space. + */ +int hmm_bo_mmap(struct vm_area_struct *vma, struct hmm_buffer_object *bo) +{ + unsigned int start, end; + unsigned int virt; + unsigned int pgnr, i; + unsigned int pfn; + + check_bo_null_return(bo, -EINVAL); + + check_bo_status_yes_goto(bo, HMM_BO_PAGE_ALLOCED, status_err); + + pgnr = bo->pgnr; + start = vma->vm_start; + end = vma->vm_end; + + /* + * check vma's virtual address space size and buffer object's size. + * must be the same. + */ + if ((start + pgnr_to_size(pgnr)) != end) { + dev_warn(atomisp_dev, + "vma's address space size not equal to buffer object's size"); + return -EINVAL; + } + + virt = vma->vm_start; + for (i = 0; i < pgnr; i++) { + pfn = page_to_pfn(bo->pages[i]); + if (remap_pfn_range(vma, virt, pfn, PAGE_SIZE, PAGE_SHARED)) { + dev_warn(atomisp_dev, + "remap_pfn_range failed: virt = 0x%x, pfn = 0x%x, mapped_pgnr = %d\n", + virt, pfn, 1); + return -EINVAL; + } + virt += PAGE_SIZE; + } + + vma->vm_private_data = bo; + + vma->vm_ops = &hmm_bo_vm_ops; + vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; + + /* + * call hmm_bo_vm_open explicitly. + */ + hmm_bo_vm_open(vma); + + return 0; + +status_err: + dev_err(atomisp_dev, "buffer page not allocated yet.\n"); + return -EINVAL; +} diff --git a/drivers/staging/media/atomisp/pci/ia_css.h b/drivers/staging/media/atomisp/pci/ia_css.h new file mode 100644 index 000000000..d83e1ae5b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_H_ +#define _IA_CSS_H_ + +/* @file + * This file is the starting point of the CSS-API. It includes all CSS-API + * header files. + */ + +#include "ia_css_3a.h" +#include "ia_css_acc_types.h" +#include "ia_css_buffer.h" +#include "ia_css_control.h" +#include "ia_css_device_access.h" +#include "ia_css_dvs.h" +#include "ia_css_env.h" +#include "ia_css_err.h" +#include "ia_css_event_public.h" +#include "ia_css_firmware.h" +#include "ia_css_frame_public.h" +#include "ia_css_input_port.h" +#include "ia_css_irq.h" +#include "ia_css_metadata.h" +#include "ia_css_mipi.h" +#include "ia_css_pipe_public.h" +#include "ia_css_prbs.h" +#include "ia_css_properties.h" +#include "ia_css_stream_format.h" +#include "ia_css_stream_public.h" +#include "ia_css_tpg.h" +#include "ia_css_version.h" +#include "ia_css_mmu.h" +#include "ia_css_morph.h" +#include "ia_css_shading.h" +#include "ia_css_timer.h" + +/* + Please do not add code to this file. Public functionality is to be + exposed in a function/data type specific header file. + Please add to the appropriate header file or create a new one. + */ + +#endif /* _IA_CSS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_3a.h b/drivers/staging/media/atomisp/pci/ia_css_3a.h new file mode 100644 index 000000000..70cfc915c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_3a.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_3A_H +#define __IA_CSS_3A_H + +/* @file + * This file contains types used for 3A statistics + */ + +#include +#include "ia_css_types.h" +#include "ia_css_err.h" +#include "system_global.h" + +enum ia_css_3a_tables { + IA_CSS_S3A_TBL_HI, + IA_CSS_S3A_TBL_LO, + IA_CSS_RGBY_TBL, + IA_CSS_NUM_3A_TABLES +}; + +/* Structure that holds 3A statistics in the ISP internal + * format. Use ia_css_get_3a_statistics() to translate + * this to the format used on the host (3A library). + * */ +struct ia_css_isp_3a_statistics { + union { + struct { + ia_css_ptr s3a_tbl; + } dmem; + struct { + ia_css_ptr s3a_tbl_hi; + ia_css_ptr s3a_tbl_lo; + } vmem; + } data; + struct { + ia_css_ptr rgby_tbl; + } data_hmem; + u32 exp_id; /** exposure id, to match statistics to a frame, + see ia_css_event_public.h for more detail. */ + u32 isp_config_id;/** Unique ID to track which config was actually applied to a particular frame */ + ia_css_ptr data_ptr; /** pointer to base of all data */ + u32 size; /** total size of all data */ + u32 dmem_size; + u32 vmem_size; /** both lo and hi have this size */ + u32 hmem_size; +}; + +#define SIZE_OF_DMEM_STRUCT \ + (SIZE_OF_IA_CSS_PTR) + +#define SIZE_OF_VMEM_STRUCT \ + (2 * SIZE_OF_IA_CSS_PTR) + +#define SIZE_OF_DATA_UNION \ + (MAX(SIZE_OF_DMEM_STRUCT, SIZE_OF_VMEM_STRUCT)) + +#define SIZE_OF_DATA_HMEM_STRUCT \ + (SIZE_OF_IA_CSS_PTR) + +#define SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT \ + (SIZE_OF_DATA_UNION + \ + SIZE_OF_DATA_HMEM_STRUCT + \ + sizeof(uint32_t) + \ + sizeof(uint32_t) + \ + SIZE_OF_IA_CSS_PTR + \ + 4 * sizeof(uint32_t)) + +/* Map with host-side pointers to ISP-format statistics. + * These pointers can either be copies of ISP data or memory mapped + * ISP pointers. + * All of the data behind these pointers is allocated contiguously, the + * allocated pointer is stored in the data_ptr field. The other fields + * point into this one block of data. + */ +struct ia_css_isp_3a_statistics_map { + void *data_ptr; /** Pointer to start of memory */ + struct ia_css_3a_output *dmem_stats; + u16 *vmem_stats_hi; + u16 *vmem_stats_lo; + struct ia_css_bh_table *hmem_stats; + u32 size; /** total size in bytes of data_ptr */ + u32 data_allocated; /** indicate whether data_ptr + was allocated or not. */ +}; + +/* @brief Copy and translate 3A statistics from an ISP buffer to a host buffer + * @param[out] host_stats Host buffer. + * @param[in] isp_stats ISP buffer. + * @return error value if temporary memory cannot be allocated + * + * This copies 3a statistics from an ISP pointer to a host pointer and then + * translates some of the statistics, details depend on which ISP binary is + * used. + * Always use this function, never copy the buffer directly. + */ +int +ia_css_get_3a_statistics(struct ia_css_3a_statistics *host_stats, + const struct ia_css_isp_3a_statistics *isp_stats); + +/* @brief Translate 3A statistics from ISP format to host format. + * @param[out] host_stats host-format statistics + * @param[in] isp_stats ISP-format statistics + * @return None + * + * This function translates statistics from the internal ISP-format to + * the host-format. This function does not include an additional copy + * step. + * */ +void +ia_css_translate_3a_statistics( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_isp_3a_statistics_map *isp_stats); + +/* Convenience functions for alloc/free of certain datatypes */ + +/* @brief Allocate memory for the 3a statistics on the ISP + * @param[in] grid The grid. + * @return Pointer to the allocated 3a statistics buffer on the ISP +*/ +struct ia_css_isp_3a_statistics * +ia_css_isp_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid); + +/* @brief Free the 3a statistics memory on the isp + * @param[in] me Pointer to the 3a statistics buffer on the ISP. + * @return None +*/ +void +ia_css_isp_3a_statistics_free(struct ia_css_isp_3a_statistics *me); + +/* @brief Allocate memory for the 3a statistics on the host + * @param[in] grid The grid. + * @return Pointer to the allocated 3a statistics buffer on the host +*/ +struct ia_css_3a_statistics * +ia_css_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid); + +/* @brief Free the 3a statistics memory on the host + * @param[in] me Pointer to the 3a statistics buffer on the host. + * @return None + */ +void +ia_css_3a_statistics_free(struct ia_css_3a_statistics *me); + +/* @brief Allocate a 3a statistics map structure + * @param[in] isp_stats pointer to ISP 3a statistis struct + * @param[in] data_ptr host-side pointer to ISP 3a statistics. + * @return Pointer to the allocated 3a statistics map + * + * This function allocates the ISP 3a statistics map structure + * and uses the data_ptr as base pointer to set the appropriate + * pointers to all relevant subsets of the 3a statistics (dmem, + * vmem, hmem). + * If the data_ptr is NULL, this function will allocate the host-side + * memory. This information is stored in the struct and used in the + * ia_css_isp_3a_statistics_map_free() function to determine whether + * the memory should be freed or not. + * Note that this function does not allocate or map any ISP + * memory. +*/ +struct ia_css_isp_3a_statistics_map * +ia_css_isp_3a_statistics_map_allocate( + const struct ia_css_isp_3a_statistics *isp_stats, + void *data_ptr); + +/* @brief Free the 3a statistics map + * @param[in] me Pointer to the 3a statistics map + * @return None + * + * This function frees the map struct. If the data_ptr inside it + * was allocated inside ia_css_isp_3a_statistics_map_allocate(), it + * will be freed in this function. Otherwise it will not be freed. + */ +void +ia_css_isp_3a_statistics_map_free(struct ia_css_isp_3a_statistics_map *me); + +#endif /* __IA_CSS_3A_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_acc_types.h b/drivers/staging/media/atomisp/pci/ia_css_acc_types.h new file mode 100644 index 000000000..a20879aed --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_acc_types.h @@ -0,0 +1,473 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_ACC_TYPES_H +#define _IA_CSS_ACC_TYPES_H + +/* @file + * This file contains types used for acceleration + */ + +#include /* HAS_IRQ_MAP_VERSION_# */ +#include +#include +#include +#include + +#include "ia_css_types.h" +#include "ia_css_frame_format.h" + +/* Should be included without the path. + However, that requires adding the path to numerous makefiles + that have nothing to do with isp parameters. + */ +#include "runtime/isp_param/interface/ia_css_isp_param_types.h" + +/* Types for the acceleration API. + * These should be moved to sh_css_internal.h once the old acceleration + * argument handling has been completed. + * After that, interpretation of these structures is no longer needed + * in the kernel and HAL. +*/ + +/* Type of acceleration. + */ +enum ia_css_acc_type { + IA_CSS_ACC_NONE, /** Normal binary */ + IA_CSS_ACC_OUTPUT, /** Accelerator stage on output frame */ + IA_CSS_ACC_VIEWFINDER, /** Accelerator stage on viewfinder frame */ + IA_CSS_ACC_STANDALONE, /** Stand-alone acceleration */ +}; + +/* Cells types + */ +enum ia_css_cell_type { + IA_CSS_SP0 = 0, + IA_CSS_SP1, + IA_CSS_ISP, + MAX_NUM_OF_CELLS +}; + +/* Firmware types. + */ +enum ia_css_fw_type { + ia_css_sp_firmware, /** Firmware for the SP */ + ia_css_isp_firmware, /** Firmware for the ISP */ + ia_css_bootloader_firmware, /** Firmware for the BootLoader */ + ia_css_acc_firmware /** Firmware for accelrations */ +}; + +struct ia_css_blob_descr; + +/* Blob descriptor. + * This structure describes an SP or ISP blob. + * It describes the test, data and bss sections as well as position in a + * firmware file. + * For convenience, it contains dynamic data after loading. + */ +struct ia_css_blob_info { + /** Static blob data */ + u32 offset; /** Blob offset in fw file */ + struct ia_css_isp_param_memory_offsets + memory_offsets; /** offset wrt hdr in bytes */ + u32 prog_name_offset; /** offset wrt hdr in bytes */ + u32 size; /** Size of blob */ + u32 padding_size; /** total cummulative of bytes added due to section alignment */ + u32 icache_source; /** Position of icache in blob */ + u32 icache_size; /** Size of icache section */ + u32 icache_padding;/** bytes added due to icache section alignment */ + u32 text_source; /** Position of text in blob */ + u32 text_size; /** Size of text section */ + u32 text_padding; /** bytes added due to text section alignment */ + u32 data_source; /** Position of data in blob */ + u32 data_target; /** Start of data in SP dmem */ + u32 data_size; /** Size of text section */ + u32 data_padding; /** bytes added due to data section alignment */ + u32 bss_target; /** Start position of bss in SP dmem */ + u32 bss_size; /** Size of bss section */ + /** Dynamic data filled by loader */ + CSS_ALIGN(const void *code, + 8); /** Code section absolute pointer within fw, code = icache + text */ + CSS_ALIGN(const void *data, + 8); /** Data section absolute pointer within fw, data = data + bss */ +}; + +struct ia_css_binary_input_info { + u32 min_width; + u32 min_height; + u32 max_width; + u32 max_height; + u32 source; /* memory, sensor, variable */ +}; + +struct ia_css_binary_output_info { + u32 min_width; + u32 min_height; + u32 max_width; + u32 max_height; + u32 num_chunks; + u32 variable_format; +}; + +struct ia_css_binary_internal_info { + u32 max_width; + u32 max_height; +}; + +struct ia_css_binary_bds_info { + u32 supported_bds_factors; +}; + +struct ia_css_binary_dvs_info { + u32 max_envelope_width; + u32 max_envelope_height; +}; + +struct ia_css_binary_vf_dec_info { + u32 is_variable; + u32 max_log_downscale; +}; + +struct ia_css_binary_s3a_info { + u32 s3atbl_use_dmem; + u32 fixed_s3a_deci_log; +}; + +/* DPC related binary info */ +struct ia_css_binary_dpc_info { + u32 bnr_lite; /** bnr lite enable flag */ +}; + +struct ia_css_binary_iterator_info { + u32 num_stripes; + u32 row_stripes_height; + u32 row_stripes_overlap_lines; +}; + +struct ia_css_binary_address_info { + u32 isp_addresses; /* Address in ISP dmem */ + u32 main_entry; /* Address of entry fct */ + u32 in_frame; /* Address in ISP dmem */ + u32 out_frame; /* Address in ISP dmem */ + u32 in_data; /* Address in ISP dmem */ + u32 out_data; /* Address in ISP dmem */ + u32 sh_dma_cmd_ptr; /* In ISP dmem */ +}; + +struct ia_css_binary_uds_info { + u16 bpp; + u16 use_bci; + u16 use_str; + u16 woix; + u16 woiy; + u16 extra_out_vecs; + u16 vectors_per_line_in; + u16 vectors_per_line_out; + u16 vectors_c_per_line_in; + u16 vectors_c_per_line_out; + u16 vmem_gdc_in_block_height_y; + u16 vmem_gdc_in_block_height_c; + /* uint16_t padding; */ +}; + +struct ia_css_binary_pipeline_info { + u32 mode; + u32 isp_pipe_version; + u32 pipelining; + u32 c_subsampling; + u32 top_cropping; + u32 left_cropping; + u32 variable_resolution; +}; + +struct ia_css_binary_block_info { + u32 block_width; + u32 block_height; + u32 output_block_height; +}; + +/* Structure describing an ISP binary. + * It describes the capabilities of a binary, like the maximum resolution, + * support features, dma channels, uds features, etc. + * This part is to be used by the SP. + * Future refactoring should move binary properties to ia_css_binary_xinfo, + * thereby making the SP code more binary independent. + */ +struct ia_css_binary_info { + CSS_ALIGN(u32 id, 8); /* IA_CSS_BINARY_ID_* */ + struct ia_css_binary_pipeline_info pipeline; + struct ia_css_binary_input_info input; + struct ia_css_binary_output_info output; + struct ia_css_binary_internal_info internal; + struct ia_css_binary_bds_info bds; + struct ia_css_binary_dvs_info dvs; + struct ia_css_binary_vf_dec_info vf_dec; + struct ia_css_binary_s3a_info s3a; + struct ia_css_binary_dpc_info dpc_bnr; /** DPC related binary info */ + struct ia_css_binary_iterator_info iterator; + struct ia_css_binary_address_info addresses; + struct ia_css_binary_uds_info uds; + struct ia_css_binary_block_info block; + struct ia_css_isp_param_isp_segments mem_initializers; + /* MW: Packing (related) bools in an integer ?? */ + struct { + u8 reduced_pipe; + u8 vf_veceven; + u8 dis; + u8 dvs_envelope; + u8 uds; + u8 dvs_6axis; + u8 block_output; + u8 streaming_dma; + u8 ds; + u8 bayer_fir_6db; + u8 raw_binning; + u8 continuous; + u8 s3a; + u8 fpnr; + u8 sc; + u8 macc; + u8 output; + u8 ref_frame; + u8 tnr; + u8 xnr; + u8 params; + u8 ca_gdc; + u8 isp_addresses; + u8 in_frame; + u8 out_frame; + u8 high_speed; + u8 dpc; + u8 padding[2]; + } enable; + struct { + /* DMA channel ID: [0,...,HIVE_ISP_NUM_DMA_CHANNELS> */ + u8 ref_y_channel; + u8 ref_c_channel; + u8 tnr_channel; + u8 tnr_out_channel; + u8 dvs_coords_channel; + u8 output_channel; + u8 c_channel; + u8 vfout_channel; + u8 vfout_c_channel; + u8 vfdec_bits_per_pixel; + u8 claimed_by_isp; + u8 padding[2]; + } dma; +}; + +/* Structure describing an ISP binary. + * It describes the capabilities of a binary, like the maximum resolution, + * support features, dma channels, uds features, etc. + */ +struct ia_css_binary_xinfo { + /* Part that is of interest to the SP. */ + struct ia_css_binary_info sp; + + /* Rest of the binary info, only interesting to the host. */ + enum ia_css_acc_type type; + + CSS_ALIGN(s32 num_output_formats, 8); + enum ia_css_frame_format output_formats[IA_CSS_FRAME_FORMAT_NUM]; + + CSS_ALIGN(s32 num_vf_formats, 8); /** number of supported vf formats */ + enum ia_css_frame_format + vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /** types of supported vf formats */ + u8 num_output_pins; + ia_css_ptr xmem_addr; + + CSS_ALIGN(const struct ia_css_blob_descr *blob, 8); + CSS_ALIGN(u32 blob_index, 8); + CSS_ALIGN(union ia_css_all_memory_offsets mem_offsets, 8); + CSS_ALIGN(struct ia_css_binary_xinfo *next, 8); +}; + +/* Structure describing the Bootloader (an ISP binary). + * It contains several address, either in ddr, isp_dmem or + * the entry function in icache. + */ +struct ia_css_bl_info { + u32 num_dma_cmds; /** Number of cmds sent by CSS */ + u32 dma_cmd_list; /** Dma command list sent by CSS */ + u32 sw_state; /** Polled from css */ + /* Entry functions */ + u32 bl_entry; /** The SP entry function */ +}; + +/* Structure describing the SP binary. + * It contains several address, either in ddr, sp_dmem or + * the entry function in pmem. + */ +struct ia_css_sp_info { + u32 init_dmem_data; /** data sect config, stored to dmem */ + u32 per_frame_data; /** Per frame data, stored to dmem */ + u32 group; /** Per pipeline data, loaded by dma */ + u32 output; /** SP output data, loaded by dmem */ + u32 host_sp_queue; /** Host <-> SP queues */ + u32 host_sp_com;/** Host <-> SP commands */ + u32 isp_started; /** Polled from sensor thread, csim only */ + u32 sw_state; /** Polled from css */ + u32 host_sp_queues_initialized; /** Polled from the SP */ + u32 sleep_mode; /** different mode to halt SP */ + u32 invalidate_tlb; /** inform SP to invalidate mmu TLB */ + + /* ISP2400 */ + u32 stop_copy_preview; /** suspend copy and preview pipe when capture */ + + u32 debug_buffer_ddr_address; /** inform SP the address + of DDR debug queue */ + u32 perf_counter_input_system_error; /** input system perf + counter array */ +#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG + u32 debug_wait; /** thread/pipe post mortem debug */ + u32 debug_stage; /** thread/pipe post mortem debug */ + u32 debug_stripe; /** thread/pipe post mortem debug */ +#endif + u32 threads_stack; /** sp thread's stack pointers */ + u32 threads_stack_size; /** sp thread's stack sizes */ + u32 curr_binary_id; /** current binary id */ + u32 raw_copy_line_count; /** raw copy line counter */ + u32 ddr_parameter_address; /** acc param ddrptr, sp dmem */ + u32 ddr_parameter_size; /** acc param size, sp dmem */ + /* Entry functions */ + u32 sp_entry; /** The SP entry function */ + u32 tagger_frames_addr; /** Base address of tagger state */ +}; + +/* The following #if is there because this header file is also included + by SP and ISP code but they do not need this data and HIVECC has alignment + issue with the firmware struct/union's. + More permanent solution will be to refactor this include. +*/ + +/* Accelerator firmware information. + */ +struct ia_css_acc_info { + u32 per_frame_data; /** Dummy for now */ +}; + +/* Firmware information. + */ +union ia_css_fw_union { + struct ia_css_binary_xinfo isp; /** ISP info */ + struct ia_css_sp_info sp; /** SP info */ + struct ia_css_bl_info bl; /** Bootloader info */ + struct ia_css_acc_info acc; /** Accelerator info */ +}; + +/* Firmware information. + */ +struct ia_css_fw_info { + size_t header_size; /** size of fw header */ + + CSS_ALIGN(u32 type, 8); + union ia_css_fw_union info; /** Binary info */ + struct ia_css_blob_info blob; /** Blob info */ + /* Dynamic part */ + struct ia_css_fw_info *next; + + CSS_ALIGN(u32 loaded, 8); /** Firmware has been loaded */ + CSS_ALIGN(const u8 *isp_code, 8); /** ISP pointer to code */ + /** Firmware handle between user space and kernel */ + CSS_ALIGN(u32 handle, 8); + /** Sections to copy from/to ISP */ + struct ia_css_isp_param_css_segments mem_initializers; + /** Initializer for local ISP memories */ +}; + +struct ia_css_blob_descr { + const unsigned char *blob; + struct ia_css_fw_info header; + const char *name; + union ia_css_all_memory_offsets mem_offsets; +}; + +struct ia_css_acc_fw; + +/* Structure describing the SP binary of a stand-alone accelerator. + */ +struct ia_css_acc_sp { + void (*init)(struct ia_css_acc_fw *); /** init for crun */ + u32 sp_prog_name_offset; /** program name offset wrt hdr in bytes */ + u32 sp_blob_offset; /** blob offset wrt hdr in bytes */ + void *entry; /** Address of sp entry point */ + u32 *css_abort; /** SP dmem abort flag */ + void *isp_code; /** SP dmem address holding xmem + address of isp code */ + struct ia_css_fw_info fw; /** SP fw descriptor */ + const u8 *code; /** ISP pointer of allocated SP code */ +}; + +/* Acceleration firmware descriptor. + * This descriptor descibes either SP code (stand-alone), or + * ISP code (a separate pipeline stage). + */ +struct ia_css_acc_fw_hdr { + enum ia_css_acc_type type; /** Type of accelerator */ + u32 isp_prog_name_offset; /** program name offset wrt + header in bytes */ + u32 isp_blob_offset; /** blob offset wrt header + in bytes */ + u32 isp_size; /** Size of isp blob */ + const u8 *isp_code; /** ISP pointer to code */ + struct ia_css_acc_sp sp; /** Standalone sp code */ + /** Firmware handle between user space and kernel */ + u32 handle; + struct ia_css_data parameters; /** Current SP parameters */ +}; + +/* Firmware structure. + * This contains the header and actual blobs. + * For standalone, it contains SP and ISP blob. + * For a pipeline stage accelerator, it contains ISP code only. + * Since its members are variable size, their offsets are described in the + * header and computed using the access macros below. + */ +struct ia_css_acc_fw { + struct ia_css_acc_fw_hdr header; /** firmware header */ + /* + int8_t isp_progname[]; **< ISP program name + int8_t sp_progname[]; **< SP program name, stand-alone only + uint8_t sp_code[]; **< SP blob, stand-alone only + uint8_t isp_code[]; **< ISP blob + */ +}; + +/* Access macros for firmware */ +#define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f) + (f->header.n))) +#define IA_CSS_ACC_SP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ + sp.sp_prog_name_offset) +#define IA_CSS_ACC_ISP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ + isp_prog_name_offset) +#define IA_CSS_ACC_SP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t *, f, \ + sp.sp_blob_offset) +#define IA_CSS_ACC_SP_DATA(f) (IA_CSS_ACC_SP_CODE(f) + \ + (f)->header.sp.fw.blob.data_source) +#define IA_CSS_ACC_ISP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t*, f,\ + isp_blob_offset) +#define IA_CSS_ACC_ISP_SIZE(f) ((f)->header.isp_size) + +/* Binary name follows header immediately */ +#define IA_CSS_EXT_ISP_PROG_NAME(f) ((const char *)(f) + (f)->blob.prog_name_offset) +#define IA_CSS_EXT_ISP_MEM_OFFSETS(f) \ + ((const struct ia_css_memory_offsets *)((const char *)(f) + (f)->blob.mem_offsets)) + +enum ia_css_sp_sleep_mode { + SP_DISABLE_SLEEP_MODE = 0, + SP_SLEEP_AFTER_FRAME = BIT(0), + SP_SLEEP_AFTER_IRQ = BIT(1), +}; +#endif /* _IA_CSS_ACC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_buffer.h b/drivers/staging/media/atomisp/pci/ia_css_buffer.h new file mode 100644 index 000000000..b1e8357b9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_buffer.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BUFFER_H +#define __IA_CSS_BUFFER_H + +/* @file + * This file contains datastructures and types for buffers used in CSS + */ + +#include +#include "ia_css_types.h" +#include "ia_css_timer.h" + +/* Enumeration of buffer types. Buffers can be queued and de-queued + * to hand them over between IA and ISP. + */ +enum ia_css_buffer_type { + IA_CSS_BUFFER_TYPE_INVALID = -1, + IA_CSS_BUFFER_TYPE_3A_STATISTICS = 0, + IA_CSS_BUFFER_TYPE_DIS_STATISTICS, + IA_CSS_BUFFER_TYPE_LACE_STATISTICS, + IA_CSS_BUFFER_TYPE_INPUT_FRAME, + IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_CUSTOM_INPUT, + IA_CSS_BUFFER_TYPE_CUSTOM_OUTPUT, + IA_CSS_BUFFER_TYPE_METADATA, + IA_CSS_BUFFER_TYPE_PARAMETER_SET, + IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, + IA_CSS_NUM_DYNAMIC_BUFFER_TYPE, + IA_CSS_NUM_BUFFER_TYPE +}; + +/* Driver API is not SP/ISP visible, 64 bit types not supported on hivecc */ + +/* Buffer structure. This is a container structure that enables content + * independent buffer queues and access functions. + */ +struct ia_css_buffer { + enum ia_css_buffer_type type; /** Buffer type. */ + unsigned int exp_id; + /** exposure id for this buffer; 0 = not available + see ia_css_event_public.h for more detail. */ + union { + struct ia_css_isp_3a_statistics + *stats_3a; /** 3A statistics & optionally RGBY statistics. */ + struct ia_css_isp_dvs_statistics *stats_dvs; /** DVS statistics. */ + struct ia_css_isp_skc_dvs_statistics *stats_skc_dvs; /** SKC DVS statistics. */ + struct ia_css_frame *frame; /** Frame buffer. */ + struct ia_css_acc_param *custom_data; /** Custom buffer. */ + struct ia_css_metadata *metadata; /** Sensor metadata. */ + } data; /** Buffer data pointer. */ + u64 driver_cookie; /** cookie for the driver */ + struct ia_css_time_meas + timing_data; /** timing data (readings from the timer) */ + struct ia_css_clock_tick + isys_eof_clock_tick; /** ISYS's end of frame timer tick*/ +}; + +/* @brief Dequeue param buffers from sp2host_queue + * + * @return None + * + * This function must be called at every driver interrupt handler to prevent + * overflow of sp2host_queue. + */ +void +ia_css_dequeue_param_buffers(void); + +#endif /* __IA_CSS_BUFFER_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_control.h b/drivers/staging/media/atomisp/pci/ia_css_control.h new file mode 100644 index 000000000..88f031a63 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_control.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CONTROL_H +#define __IA_CSS_CONTROL_H + +/* @file + * This file contains functionality for starting and controlling CSS + */ + +#include +#include +#include +#include + +/* @brief Initialize the CSS API. + * @param[in] env Environment, provides functions to access the + * environment in which the CSS code runs. This is + * used for host side memory access and message + * printing. May not be NULL. + * @param[in] fw Firmware package containing the firmware for all + * predefined ISP binaries. + * if fw is NULL the firmware must be loaded before + * through a call of ia_css_load_firmware + * @param[in] l1_base Base index (isp2400) + * of the L1 page table. This is a physical + * address or index. + * @param[in] irq_type The type of interrupt to be used (edge or level) + * @return Returns -EINVAL in case of any + * errors and 0 otherwise. + * + * This function initializes the API which includes allocating and initializing + * internal data structures. This also interprets the firmware package. All + * contents of this firmware package are copied into local data structures, so + * the fw pointer could be freed after this function completes. + */ +int ia_css_init(struct device *dev, + const struct ia_css_env *env, + const struct ia_css_fw *fw, + u32 l1_base, + enum ia_css_irq_type irq_type); + +/* @brief Un-initialize the CSS API. + * @return None + * + * This function deallocates all memory that has been allocated by the CSS API + * Exception: if you explicitly loaded firmware through ia_css_load_firmware + * you need to call ia_css_unload_firmware to deallocate the memory reserved + * for the firmware. + * After this function is called, no other CSS functions should be called + * with the exception of ia_css_init which will re-initialize the CSS code, + * ia_css_unload_firmware to unload the firmware or ia_css_load_firmware + * to load new firmware + */ +void +ia_css_uninit(void); + +/* @brief Enable use of a separate queue for ISYS events. + * + * @param[in] enable: enable or disable use of separate ISYS event queues. + * @return error if called when SP is running. + * + * @deprecated{This is a temporary function that allows drivers to migrate to + * the use of the separate ISYS event queue. Once all drivers supports this, it + * will be made the default and this function will be removed. + * This function should only be called when the SP is not running, calling it + * when the SP is running will result in an error value being returned. } + */ +int +ia_css_enable_isys_event_queue(bool enable); + +/* @brief Test whether the ISP has started. + * + * @return Boolean flag true if the ISP has started or false otherwise. + * + * Temporary function to poll whether the ISP has been started. Once it has, + * the sensor can also be started. */ +bool +ia_css_isp_has_started(void); + +/* @brief Test whether the SP has initialized. + * + * @return Boolean flag true if the SP has initialized or false otherwise. + * + * Temporary function to poll whether the SP has been initialized. Once it has, + * we can enqueue buffers. */ +bool +ia_css_sp_has_initialized(void); + +/* @brief Test whether the SP has terminated. + * + * @return Boolean flag true if the SP has terminated or false otherwise. + * + * Temporary function to poll whether the SP has been terminated. Once it has, + * we can switch mode. */ +bool +ia_css_sp_has_terminated(void); + +/* @brief start SP hardware + * + * @return 0 or error code upon error. + * + * It will boot the SP hardware and start multi-threading infrastructure. + * All threads will be started and blocked by semaphore. This function should + * be called before any ia_css_stream_start(). + */ +int +ia_css_start_sp(void); + +/* @brief stop SP hardware + * + * @return 0 or error code upon error. + * + * This function will terminate all threads and shut down SP. It should be + * called after all ia_css_stream_stop(). + */ +int +ia_css_stop_sp(void); + +#endif /* __IA_CSS_CONTROL_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_device_access.c b/drivers/staging/media/atomisp/pci/ia_css_device_access.c new file mode 100644 index 000000000..9cd2d3caa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_device_access.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_device_access.h" +#include /* for uint*, size_t */ +#include /* for hrt_address */ +#include /* for ia_css_hw_access_env */ +#include /* for assert */ + +static struct ia_css_hw_access_env my_env; + +void +ia_css_device_access_init(const struct ia_css_hw_access_env *env) +{ + assert(env); + + my_env = *env; +} + +uint8_t +ia_css_device_load_uint8(const hrt_address addr) +{ + return my_env.load_8(addr); +} + +uint16_t +ia_css_device_load_uint16(const hrt_address addr) +{ + return my_env.load_16(addr); +} + +uint32_t +ia_css_device_load_uint32(const hrt_address addr) +{ + return my_env.load_32(addr); +} + +uint64_t +ia_css_device_load_uint64(const hrt_address addr) +{ + assert(0); + + (void)addr; + return 0; +} + +void +ia_css_device_store_uint8(const hrt_address addr, const uint8_t data) +{ + my_env.store_8(addr, data); +} + +void +ia_css_device_store_uint16(const hrt_address addr, const uint16_t data) +{ + my_env.store_16(addr, data); +} + +void +ia_css_device_store_uint32(const hrt_address addr, const uint32_t data) +{ + my_env.store_32(addr, data); +} + +void +ia_css_device_store_uint64(const hrt_address addr, const uint64_t data) +{ + assert(0); + + (void)addr; + (void)data; +} + +void +ia_css_device_load(const hrt_address addr, void *data, const size_t size) +{ + my_env.load(addr, data, (uint32_t)size); +} + +void +ia_css_device_store(const hrt_address addr, const void *data, const size_t size) +{ + my_env.store(addr, data, (uint32_t)size); +} diff --git a/drivers/staging/media/atomisp/pci/ia_css_device_access.h b/drivers/staging/media/atomisp/pci/ia_css_device_access.h new file mode 100644 index 000000000..07d611fdd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_device_access.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_DEVICE_ACCESS_H +#define _IA_CSS_DEVICE_ACCESS_H + +/* @file + * File containing internal functions for the CSS-API to access the CSS device. + */ + +#include /* for uint*, size_t */ +#include /* for hrt_address */ +#include /* for ia_css_hw_access_env */ + +void +ia_css_device_access_init(const struct ia_css_hw_access_env *env); + +uint8_t +ia_css_device_load_uint8(const hrt_address addr); + +uint16_t +ia_css_device_load_uint16(const hrt_address addr); + +uint32_t +ia_css_device_load_uint32(const hrt_address addr); + +uint64_t +ia_css_device_load_uint64(const hrt_address addr); + +void +ia_css_device_store_uint8(const hrt_address addr, const uint8_t data); + +void +ia_css_device_store_uint16(const hrt_address addr, const uint16_t data); + +void +ia_css_device_store_uint32(const hrt_address addr, const uint32_t data); + +void +ia_css_device_store_uint64(const hrt_address addr, const uint64_t data); + +void +ia_css_device_load(const hrt_address addr, void *data, const size_t size); + +void +ia_css_device_store(const hrt_address addr, const void *data, + const size_t size); + +#endif /* _IA_CSS_DEVICE_ACCESS_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_dvs.h b/drivers/staging/media/atomisp/pci/ia_css_dvs.h new file mode 100644 index 000000000..3367dfd64 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_dvs.h @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DVS_H +#define __IA_CSS_DVS_H + +/* @file + * This file contains types for DVS statistics + */ + +#include +#include "ia_css_types.h" +#include "ia_css_err.h" +#include "ia_css_stream_public.h" + +enum dvs_statistics_type { + DVS_STATISTICS, + DVS2_STATISTICS, + SKC_DVS_STATISTICS +}; + +/* Structure that holds DVS statistics in the ISP internal + * format. Use ia_css_get_dvs_statistics() to translate + * this to the format used on the host (DVS engine). + * */ +struct ia_css_isp_dvs_statistics { + ia_css_ptr hor_proj; + ia_css_ptr ver_proj; + u32 hor_size; + u32 ver_size; + u32 exp_id; /** see ia_css_event_public.h for more detail */ + ia_css_ptr data_ptr; /* base pointer containing all memory */ + u32 size; /* size of allocated memory in data_ptr */ +}; + +/* Structure that holds SKC DVS statistics in the ISP internal + * format. Use ia_css_dvs_statistics_get() to translate this to + * the format used on the host. + * */ +struct ia_css_isp_skc_dvs_statistics; + +#define SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT \ + ((3 * SIZE_OF_IA_CSS_PTR) + \ + (4 * sizeof(uint32_t))) + +/* Map with host-side pointers to ISP-format statistics. + * These pointers can either be copies of ISP data or memory mapped + * ISP pointers. + * All of the data behind these pointers is allocatd contiguously, the + * allocated pointer is stored in the data_ptr field. The other fields + * point into this one block of data. + */ +struct ia_css_isp_dvs_statistics_map { + void *data_ptr; + s32 *hor_proj; + s32 *ver_proj; + u32 size; /* total size in bytes */ + u32 data_allocated; /* indicate whether data was allocated */ +}; + +union ia_css_dvs_statistics_isp { + struct ia_css_isp_dvs_statistics *p_dvs_statistics_isp; + struct ia_css_isp_skc_dvs_statistics *p_skc_dvs_statistics_isp; +}; + +union ia_css_dvs_statistics_host { + struct ia_css_dvs_statistics *p_dvs_statistics_host; + struct ia_css_dvs2_statistics *p_dvs2_statistics_host; + struct ia_css_skc_dvs_statistics *p_skc_dvs_statistics_host; +}; + +/* @brief Copy DVS statistics from an ISP buffer to a host buffer. + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return error value if temporary memory cannot be allocated + * + * This may include a translation step as well depending + * on the ISP version. + * Always use this function, never copy the buffer directly. + * Note that this function uses the mem_load function from the CSS + * environment struct. + * In certain environments this may be slow. In those cases it is + * advised to map the ISP memory into a host-side pointer and use + * the ia_css_translate_dvs_statistics() function instead. + */ +int +ia_css_get_dvs_statistics(struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats); + +/* @brief Translate DVS statistics from ISP format to host format + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return None + * + * This function translates the dvs statistics from the ISP-internal + * format to the format used by the DVS library on the CPU. + * This function takes a host-side pointer as input. This can either + * point to a copy of the data or be a memory mapped pointer to the + * ISP memory pages. + */ +void +ia_css_translate_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats); + +/* @brief Copy DVS 2.0 statistics from an ISP buffer to a host buffer. + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return error value if temporary memory cannot be allocated + * + * This may include a translation step as well depending + * on the ISP version. + * Always use this function, never copy the buffer directly. + * Note that this function uses the mem_load function from the CSS + * environment struct. + * In certain environments this may be slow. In those cases it is + * advised to map the ISP memory into a host-side pointer and use + * the ia_css_translate_dvs2_statistics() function instead. + */ +int +ia_css_get_dvs2_statistics(struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats); + +/* @brief Translate DVS2 statistics from ISP format to host format + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return None + * + * This function translates the dvs2 statistics from the ISP-internal + * format to the format used by the DVS2 library on the CPU. + * This function takes a host-side pointer as input. This can either + * point to a copy of the data or be a memory mapped pointer to the + * ISP memory pages. + */ +void +ia_css_translate_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats); + +/* @brief Copy DVS statistics from an ISP buffer to a host buffer. + * @param[in] type - DVS statistics type + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return None + */ +void +ia_css_dvs_statistics_get(enum dvs_statistics_type type, + union ia_css_dvs_statistics_host *host_stats, + const union ia_css_dvs_statistics_isp *isp_stats); + +/* @brief Allocate the DVS statistics memory on the ISP + * @param[in] grid The grid. + * @return Pointer to the allocated DVS statistics buffer on the ISP +*/ +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid); + +/* @brief Free the DVS statistics memory on the ISP + * @param[in] me Pointer to the DVS statistics buffer on the ISP. + * @return None +*/ +void +ia_css_isp_dvs_statistics_free(struct ia_css_isp_dvs_statistics *me); + +/* @brief Allocate the DVS 2.0 statistics memory + * @param[in] grid The grid. + * @return Pointer to the allocated DVS statistics buffer on the ISP +*/ +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid); + +/* @brief Free the DVS 2.0 statistics memory + * @param[in] me Pointer to the DVS statistics buffer on the ISP. + * @return None +*/ +void +ia_css_isp_dvs2_statistics_free(struct ia_css_isp_dvs_statistics *me); + +/* @brief Allocate the DVS statistics memory on the host + * @param[in] grid The grid. + * @return Pointer to the allocated DVS statistics buffer on the host +*/ +struct ia_css_dvs_statistics * +ia_css_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid); + +/* @brief Free the DVS statistics memory on the host + * @param[in] me Pointer to the DVS statistics buffer on the host. + * @return None +*/ +void +ia_css_dvs_statistics_free(struct ia_css_dvs_statistics *me); + +/* @brief Allocate the DVS coefficients memory + * @param[in] grid The grid. + * @return Pointer to the allocated DVS coefficients buffer +*/ +struct ia_css_dvs_coefficients * +ia_css_dvs_coefficients_allocate(const struct ia_css_dvs_grid_info *grid); + +/* @brief Free the DVS coefficients memory + * @param[in] me Pointer to the DVS coefficients buffer. + * @return None + */ +void +ia_css_dvs_coefficients_free(struct ia_css_dvs_coefficients *me); + +/* @brief Allocate the DVS 2.0 statistics memory on the host + * @param[in] grid The grid. + * @return Pointer to the allocated DVS 2.0 statistics buffer on the host + */ +struct ia_css_dvs2_statistics * +ia_css_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid); + +/* @brief Free the DVS 2.0 statistics memory + * @param[in] me Pointer to the DVS 2.0 statistics buffer on the host. + * @return None +*/ +void +ia_css_dvs2_statistics_free(struct ia_css_dvs2_statistics *me); + +/* @brief Allocate the DVS 2.0 coefficients memory + * @param[in] grid The grid. + * @return Pointer to the allocated DVS 2.0 coefficients buffer +*/ +struct ia_css_dvs2_coefficients * +ia_css_dvs2_coefficients_allocate(const struct ia_css_dvs_grid_info *grid); + +/* @brief Free the DVS 2.0 coefficients memory + * @param[in] me Pointer to the DVS 2.0 coefficients buffer. + * @return None +*/ +void +ia_css_dvs2_coefficients_free(struct ia_css_dvs2_coefficients *me); + +/* @brief Allocate the DVS 2.0 6-axis config memory + * @param[in] stream The stream. + * @return Pointer to the allocated DVS 6axis configuration buffer +*/ +struct ia_css_dvs_6axis_config * +ia_css_dvs2_6axis_config_allocate(const struct ia_css_stream *stream); + +/* @brief Free the DVS 2.0 6-axis config memory + * @param[in] dvs_6axis_config Pointer to the DVS 6axis configuration buffer + * @return None + */ +void +ia_css_dvs2_6axis_config_free(struct ia_css_dvs_6axis_config *dvs_6axis_config); + +/* @brief Allocate a dvs statistics map structure + * @param[in] isp_stats pointer to ISP dvs statistis struct + * @param[in] data_ptr host-side pointer to ISP dvs statistics. + * @return Pointer to the allocated dvs statistics map + * + * This function allocates the ISP dvs statistics map structure + * and uses the data_ptr as base pointer to set the appropriate + * pointers to all relevant subsets of the dvs statistics (dmem, + * vmem, hmem). + * If the data_ptr is NULL, this function will allocate the host-side + * memory. This information is stored in the struct and used in the + * ia_css_isp_dvs_statistics_map_free() function to determine whether + * the memory should be freed or not. + * Note that this function does not allocate or map any ISP + * memory. +*/ +struct ia_css_isp_dvs_statistics_map * +ia_css_isp_dvs_statistics_map_allocate( + const struct ia_css_isp_dvs_statistics *isp_stats, + void *data_ptr); + +/* @brief Free the dvs statistics map + * @param[in] me Pointer to the dvs statistics map + * @return None + * + * This function frees the map struct. If the data_ptr inside it + * was allocated inside ia_css_isp_dvs_statistics_map_allocate(), it + * will be freed in this function. Otherwise it will not be freed. + */ +void +ia_css_isp_dvs_statistics_map_free(struct ia_css_isp_dvs_statistics_map *me); + +/* @brief Allocate memory for the SKC DVS statistics on the ISP + * @return Pointer to the allocated ACC DVS statistics buffer on the ISP +*/ +struct ia_css_isp_skc_dvs_statistics *ia_css_skc_dvs_statistics_allocate(void); + +#endif /* __IA_CSS_DVS_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_env.h b/drivers/staging/media/atomisp/pci/ia_css_env.h new file mode 100644 index 000000000..42bb1ec1c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_env.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ENV_H +#define __IA_CSS_ENV_H + +#include +#include /* va_list */ +#include +#include "ia_css_types.h" +#include "ia_css_acc_types.h" + +/* @file + * This file contains prototypes for functions that need to be provided to the + * CSS-API host-code by the environment in which the CSS-API code runs. + */ + +/* Memory allocation attributes, for use in ia_css_css_mem_env. */ +enum ia_css_mem_attr { + IA_CSS_MEM_ATTR_CACHED = BIT(0), + IA_CSS_MEM_ATTR_ZEROED = BIT(1), + IA_CSS_MEM_ATTR_PAGEALIGN = BIT(2), + IA_CSS_MEM_ATTR_CONTIGUOUS = BIT(3), +}; + +/* Environment with function pointers for local IA memory allocation. + * This provides the CSS code with environment specific functionality + * for memory allocation of small local buffers such as local data structures. + * This is never expected to allocate more than one page of memory (4K bytes). + */ +struct ia_css_cpu_mem_env { + void (*flush)(struct ia_css_acc_fw *fw); + /** Flush function to flush the cache for given accelerator. */ +}; + +/* Environment with function pointers to access the CSS hardware. This includes + * registers and local memories. + */ +struct ia_css_hw_access_env { + void (*store_8)(hrt_address addr, uint8_t data); + /** Store an 8 bit value into an address in the CSS HW address space. + The address must be an 8 bit aligned address. */ + void (*store_16)(hrt_address addr, uint16_t data); + /** Store a 16 bit value into an address in the CSS HW address space. + The address must be a 16 bit aligned address. */ + void (*store_32)(hrt_address addr, uint32_t data); + /** Store a 32 bit value into an address in the CSS HW address space. + The address must be a 32 bit aligned address. */ + uint8_t (*load_8)(hrt_address addr); + /** Load an 8 bit value from an address in the CSS HW address + space. The address must be an 8 bit aligned address. */ + uint16_t (*load_16)(hrt_address addr); + /** Load a 16 bit value from an address in the CSS HW address + space. The address must be a 16 bit aligned address. */ + uint32_t (*load_32)(hrt_address addr); + /** Load a 32 bit value from an address in the CSS HW address + space. The address must be a 32 bit aligned address. */ + void (*store)(hrt_address addr, const void *data, uint32_t bytes); + /** Store a number of bytes into a byte-aligned address in the CSS HW address space. */ + void (*load)(hrt_address addr, void *data, uint32_t bytes); + /** Load a number of bytes from a byte-aligned address in the CSS HW address space. */ +}; + +/* Environment with function pointers to print error and debug messages. + */ +struct ia_css_print_env { + int __printf(1, 0) (*debug_print)(const char *fmt, va_list args); + /** Print a debug message. */ + int __printf(1, 0) (*error_print)(const char *fmt, va_list args); + /** Print an error message.*/ +}; + +/* Environment structure. This includes function pointers to access several + * features provided by the environment in which the CSS API is used. + * This is used to run the camera IP in multiple platforms such as Linux, + * Windows and several simulation environments. + */ +struct ia_css_env { + struct ia_css_cpu_mem_env cpu_mem_env; /** local flush. */ + struct ia_css_hw_access_env hw_access_env; /** CSS HW access functions */ + struct ia_css_print_env print_env; /** Message printing env. */ +}; + +#endif /* __IA_CSS_ENV_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_err.h b/drivers/staging/media/atomisp/pci/ia_css_err.h new file mode 100644 index 000000000..98401a4a1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_err.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ERR_H +#define __IA_CSS_ERR_H + +/* @file + * This file contains possible return values for most + * functions in the CSS-API. + */ + +/* FW warnings. This enum contains a value for each warning that + * the SP FW could indicate potential performance issue + */ +enum ia_css_fw_warning { + IA_CSS_FW_WARNING_NONE, + IA_CSS_FW_WARNING_ISYS_QUEUE_FULL, /* < CSS system delayed because of insufficient space in the ISys queue. + This warning can be avoided by de-queuing ISYS buffers more timely. */ + IA_CSS_FW_WARNING_PSYS_QUEUE_FULL, /* < CSS system delayed because of insufficient space in the PSys queue. + This warning can be avoided by de-queuing PSYS buffers more timely. */ + IA_CSS_FW_WARNING_CIRCBUF_ALL_LOCKED, /* < CSS system delayed because of insufficient available buffers. + This warning can be avoided by unlocking locked frame-buffers more timely. */ + IA_CSS_FW_WARNING_EXP_ID_LOCKED, /* < Exposure ID skipped because the frame associated to it was still locked. + This warning can be avoided by unlocking locked frame-buffers more timely. */ + IA_CSS_FW_WARNING_TAG_EXP_ID_FAILED, /* < Exposure ID cannot be found on the circular buffer. + This warning can be avoided by unlocking locked frame-buffers more timely. */ + IA_CSS_FW_WARNING_FRAME_PARAM_MISMATCH, /* < Frame and param pair mismatched in tagger. + This warning can be avoided by providing a param set for each frame. */ +}; + +#endif /* __IA_CSS_ERR_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_event_public.h b/drivers/staging/media/atomisp/pci/ia_css_event_public.h new file mode 100644 index 000000000..b052648d4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_event_public.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EVENT_PUBLIC_H +#define __IA_CSS_EVENT_PUBLIC_H + +/* @file + * This file contains CSS-API events functionality + */ + +#include /* uint8_t */ +#include /* ia_css_err */ +#include /* ia_css_pipe */ +#include /* ia_css_timer */ +#include + +/* The event type, distinguishes the kind of events that + * can are generated by the CSS system. + * + * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: + * 1) "enum ia_css_event_type" (ia_css_event_public.h) + * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) + * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) + * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) + */ +enum ia_css_event_type { + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE = BIT(0), + /** Output frame ready. */ + IA_CSS_EVENT_TYPE_SECOND_OUTPUT_FRAME_DONE = BIT(1), + /** Second output frame ready. */ + IA_CSS_EVENT_TYPE_VF_OUTPUT_FRAME_DONE = BIT(2), + /** Viewfinder Output frame ready. */ + IA_CSS_EVENT_TYPE_SECOND_VF_OUTPUT_FRAME_DONE = BIT(3), + /** Second viewfinder Output frame ready. */ + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE = BIT(4), + /** Indication that 3A statistics are available. */ + IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE = BIT(5), + /** Indication that DIS statistics are available. */ + IA_CSS_EVENT_TYPE_PIPELINE_DONE = BIT(6), + /** Pipeline Done event, sent after last pipeline stage. */ + IA_CSS_EVENT_TYPE_FRAME_TAGGED = BIT(7), + /** Frame tagged. */ + IA_CSS_EVENT_TYPE_INPUT_FRAME_DONE = BIT(8), + /** Input frame ready. */ + IA_CSS_EVENT_TYPE_METADATA_DONE = BIT(9), + /** Metadata ready. */ + IA_CSS_EVENT_TYPE_LACE_STATISTICS_DONE = BIT(10), + /** Indication that LACE statistics are available. */ + IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE = BIT(11), + /** Extension stage complete. */ + IA_CSS_EVENT_TYPE_TIMER = BIT(12), + /** Timer event for measuring the SP side latencies. It contains the + 32-bit timer value from the SP */ + IA_CSS_EVENT_TYPE_PORT_EOF = BIT(13), + /** End Of Frame event, sent when in buffered sensor mode. */ + IA_CSS_EVENT_TYPE_FW_WARNING = BIT(14), + /** Performance warning encounter by FW */ + IA_CSS_EVENT_TYPE_FW_ASSERT = BIT(15), + /** Assertion hit by FW */ +}; + +#define IA_CSS_EVENT_TYPE_NONE 0 + +/* IA_CSS_EVENT_TYPE_ALL is a mask for all pipe related events. + * The other events (such as PORT_EOF) cannot be enabled/disabled + * and are hence excluded from this macro. + */ +#define IA_CSS_EVENT_TYPE_ALL \ + (IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_SECOND_OUTPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_VF_OUTPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_SECOND_VF_OUTPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE | \ + IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE | \ + IA_CSS_EVENT_TYPE_PIPELINE_DONE | \ + IA_CSS_EVENT_TYPE_FRAME_TAGGED | \ + IA_CSS_EVENT_TYPE_INPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_METADATA_DONE | \ + IA_CSS_EVENT_TYPE_LACE_STATISTICS_DONE | \ + IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE) + +/* The event struct, container for the event type and its related values. + * Depending on the event type, either pipe or port will be filled. + * Pipeline related events (like buffer/frame events) will return a valid and filled pipe handle. + * For non pipeline related events (but i.e. stream specific, like EOF event), the port will be + * filled. + */ +struct ia_css_event { + struct ia_css_pipe *pipe; + /** Pipe handle on which event happened, NULL for non pipe related + events. */ + enum ia_css_event_type type; + /** Type of Event, always valid/filled. */ + u8 port; + /** Port number for EOF event (not valid for other events). */ + u8 exp_id; + /** Exposure id for EOF/FRAME_TAGGED/FW_WARNING event (not valid for other events) + The exposure ID is unique only within a logical stream and it is + only generated on systems that have an input system (such as 2400 + and 2401). + Most outputs produced by the CSS are tagged with an exposure ID. + This allows users of the CSS API to keep track of which buffer + was generated from which sensor output frame. This includes: + EOF event, output frames, 3A statistics, DVS statistics and + sensor metadata. + Exposure IDs start at IA_CSS_MIN_EXPOSURE_ID, increment by one + until IA_CSS_MAX_EXPOSURE_ID is reached, after that they wrap + around to IA_CSS_MIN_EXPOSURE_ID again. + Note that in case frames are dropped, this will not be reflected + in the exposure IDs. Therefor applications should not use this + to detect frame drops. */ + u32 fw_handle; + /** Firmware Handle for ACC_STAGE_COMPLETE event (not valid for other + events). */ + enum ia_css_fw_warning fw_warning; + /** Firmware warning code, only for WARNING events. */ + u8 fw_assert_module_id; + /** Firmware module id, only for ASSERT events, should be logged by driver. */ + u16 fw_assert_line_no; + /** Firmware line number, only for ASSERT events, should be logged by driver. */ + clock_value_t timer_data; + /** For storing the full 32-bit of the timer value. Valid only for TIMER + event */ + u8 timer_code; + /** For storing the code of the TIMER event. Valid only for + TIMER event */ + u8 timer_subcode; + /** For storing the subcode of the TIMER event. Valid only + for TIMER event */ +}; + +/* @brief Dequeue a PSYS event from the CSS system. + * + * @param[out] event Pointer to the event struct which will be filled by + * this function if an event is available. + * @return -ENODATA if no events are + * available or + * 0 otherwise. + * + * This function dequeues an event from the PSYS event queue. The queue is + * between the Host CPU and the CSS system. This function can be + * called after an interrupt has been generated that signalled that a new event + * was available and can be used in a polling-like situation where the NO_EVENT + * return value is used to determine whether an event was available or not. + */ +int +ia_css_dequeue_psys_event(struct ia_css_event *event); + +/* @brief Dequeue an ISYS event from the CSS system. + * + * @param[out] event Pointer to the event struct which will be filled by + * this function if an event is available. + * @return -ENODATA if no events are + * available or + * 0 otherwise. + * + * This function dequeues an event from the ISYS event queue. The queue is + * between host and the CSS system. + * Unlike the ia_css_dequeue_psys_event() function, this function can be called + * directly from an interrupt service routine (ISR) and it is safe to call + * this function in parallel with other CSS API functions (but only one + * call to this function should be in flight at any point in time). + * + * The reason for having the ISYS events separate is to prevent them from + * incurring additional latency due to locks being held by other CSS API + * functions. + */ +int +ia_css_dequeue_isys_event(struct ia_css_event *event); + +#endif /* __IA_CSS_EVENT_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_firmware.h b/drivers/staging/media/atomisp/pci/ia_css_firmware.h new file mode 100644 index 000000000..01d2faf55 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_firmware.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FIRMWARE_H +#define __IA_CSS_FIRMWARE_H + +/* @file + * This file contains firmware loading/unloading support functionality + */ + +#include +#include "ia_css_err.h" +#include "ia_css_env.h" + +/* CSS firmware package structure. + */ +struct ia_css_fw { + void *data; /** pointer to the firmware data */ + unsigned int bytes; /** length in bytes of firmware data */ +}; + +struct device; + +/* @brief Loads the firmware + * @param[in] env Environment, provides functions to access the + * environment in which the CSS code runs. This is + * used for host side memory access and message + * printing. + * @param[in] fw Firmware package containing the firmware for all + * predefined ISP binaries. + * @return Returns -EINVAL in case of any + * errors and 0 otherwise. + * + * This function interprets the firmware package. All + * contents of this firmware package are copied into local data structures, so + * the fw pointer could be freed after this function completes. + * + * Rationale for this function is that it can be called before ia_css_init, and thus + * speeds up ia_css_init (ia_css_init is called each time a stream is created but the + * firmware only needs to be loaded once). + */ +int +ia_css_load_firmware(struct device *dev, const struct ia_css_env *env, + const struct ia_css_fw *fw); + +/* @brief Unloads the firmware + * @return None + * + * This function unloads the firmware loaded by ia_css_load_firmware. + * It is pointless to call this function if no firmware is loaded, + * but it won't harm. Use this to deallocate all memory associated with the firmware. + */ +void +ia_css_unload_firmware(void); + +#endif /* __IA_CSS_FIRMWARE_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_frac.h b/drivers/staging/media/atomisp/pci/ia_css_frac.h new file mode 100644 index 000000000..661af9225 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_frac.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_FRAC_H +#define _IA_CSS_FRAC_H + +/* @file + * This file contains typedefs used for fractional numbers + */ + +#include + +/* Fixed point types. + * NOTE: the 16 bit fixed point types actually occupy 32 bits + * to save on extension operations in the ISP code. + */ +/* Unsigned fixed point value, 0 integer bits, 16 fractional bits */ +typedef u32 ia_css_u0_16; +/* Unsigned fixed point value, 5 integer bits, 11 fractional bits */ +typedef u32 ia_css_u5_11; +/* Unsigned fixed point value, 8 integer bits, 8 fractional bits */ +typedef u32 ia_css_u8_8; +/* Signed fixed point value, 0 integer bits, 15 fractional bits */ +typedef s32 ia_css_s0_15; + +#endif /* _IA_CSS_FRAC_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_frame_format.h b/drivers/staging/media/atomisp/pci/ia_css_frame_format.h new file mode 100644 index 000000000..093e23a9b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_frame_format.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FRAME_FORMAT_H +#define __IA_CSS_FRAME_FORMAT_H + +/* @file + * This file contains information about formats supported in the ISP + */ + +/* Frame formats, some of these come from fourcc.org, others are + better explained by video4linux2. The NV11 seems to be described only + on MSDN pages, but even those seem to be gone now. + Frames can come in many forms, the main categories are RAW, RGB and YUV + (or YCbCr). The YUV frames come in 4 flavors, determined by how the U and V + values are subsampled: + 1. YUV420: hor = 2, ver = 2 + 2. YUV411: hor = 4, ver = 1 + 3. YUV422: hor = 2, ver = 1 + 4. YUV444: hor = 1, ver = 1 + + Warning: not all frame formats are supported as input or output to/from ISP. + Some of these formats are therefore not defined in the output table module. + Modifications in below frame format enum can require modifications in the + output table module. + + Warning2: Throughout the CSS code assumptions are made on the order + of formats in this enumeration type, or some sort of copy is maintained. + The following files are identified: + - FileSupport.h + - css/isp/kernels/fc/fc_1.0/formats.isp.c + - css/isp/kernels/output/output_1.0/output_table.isp.c + - css/isp/kernels/output/sc_output_1.0/formats.hive.c + - css/isp/modes/interface/isp_formats.isp.h + - css/bxt_sandbox/psyspoc/interface/ia_css_pg_info.h + - css/bxt_sandbox/psysapi/data/interface/ia_css_program_group_data.h + - css/bxt_sandbox/isysapi/interface/ia_css_isysapi_fw_types.h +*/ +enum ia_css_frame_format { + IA_CSS_FRAME_FORMAT_NV11 = 0, /** 12 bit YUV 411, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12, /** 12 bit YUV 420, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12_16, /** 16 bit YUV 420, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12_TILEY, /** 12 bit YUV 420, Intel proprietary tiled format, TileY */ + IA_CSS_FRAME_FORMAT_NV16, /** 16 bit YUV 422, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV21, /** 12 bit YUV 420, Y, VU plane */ + IA_CSS_FRAME_FORMAT_NV61, /** 16 bit YUV 422, Y, VU plane */ + IA_CSS_FRAME_FORMAT_YV12, /** 12 bit YUV 420, Y, V, U plane */ + IA_CSS_FRAME_FORMAT_YV16, /** 16 bit YUV 422, Y, V, U plane */ + IA_CSS_FRAME_FORMAT_YUV420, /** 12 bit YUV 420, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV420_16, /** yuv420, 16 bits per subpixel */ + IA_CSS_FRAME_FORMAT_YUV422, /** 16 bit YUV 422, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV422_16, /** yuv422, 16 bits per subpixel */ + IA_CSS_FRAME_FORMAT_UYVY, /** 16 bit YUV 422, UYVY interleaved */ + IA_CSS_FRAME_FORMAT_YUYV, /** 16 bit YUV 422, YUYV interleaved */ + IA_CSS_FRAME_FORMAT_YUV444, /** 24 bit YUV 444, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV_LINE, /** Internal format, 2 y lines followed + by a uvinterleaved line */ + IA_CSS_FRAME_FORMAT_RAW, /** RAW, 1 plane */ + IA_CSS_FRAME_FORMAT_RGB565, /** 16 bit RGB, 1 plane. Each 3 sub + pixels are packed into one 16 bit + value, 5 bits for R, 6 bits for G + and 5 bits for B. */ + IA_CSS_FRAME_FORMAT_PLANAR_RGB888, /** 24 bit RGB, 3 planes */ + IA_CSS_FRAME_FORMAT_RGBA888, /** 32 bit RGBA, 1 plane, A=Alpha + (alpha is unused) */ + IA_CSS_FRAME_FORMAT_QPLANE6, /** Internal, for advanced ISP */ + IA_CSS_FRAME_FORMAT_BINARY_8, /** byte stream, used for jpeg. For + frames of this type, we set the + height to 1 and the width to the + number of allocated bytes. */ + IA_CSS_FRAME_FORMAT_MIPI, /** MIPI frame, 1 plane */ + IA_CSS_FRAME_FORMAT_RAW_PACKED, /** RAW, 1 plane, packed */ + IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8, /** 8 bit per Y/U/V. + Y odd line; UYVY + interleaved even line */ + IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8, /** Legacy YUV420. UY odd + line; VY even line */ + IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10 /** 10 bit per Y/U/V. Y odd + line; UYVY interleaved + even line */ +}; + +/* NOTE: IA_CSS_FRAME_FORMAT_NUM was purposely defined outside of enum type ia_css_frame_format, */ +/* because of issues this would cause with the Clockwork code checking tool. */ +#define IA_CSS_FRAME_FORMAT_NUM (IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10 + 1) + +/* Number of valid output frame formats for ISP **/ +#define IA_CSS_FRAME_OUT_FORMAT_NUM (IA_CSS_FRAME_FORMAT_RGBA888 + 1) + +#endif /* __IA_CSS_FRAME_FORMAT_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_frame_public.h b/drivers/staging/media/atomisp/pci/ia_css_frame_public.h new file mode 100644 index 000000000..7ba464abf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_frame_public.h @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FRAME_PUBLIC_H +#define __IA_CSS_FRAME_PUBLIC_H + +/* @file + * This file contains structs to describe various frame-formats supported by the ISP. + */ + +#include +#include +#include "ia_css_err.h" +#include "ia_css_types.h" +#include "ia_css_frame_format.h" +#include "ia_css_buffer.h" + +/* For RAW input, the bayer order needs to be specified separately. There + * are 4 possible orders. The name is constructed by taking the first two + * colors on the first line and the first two colors from the second line. + */ +enum ia_css_bayer_order { + IA_CSS_BAYER_ORDER_GRBG, /** GRGRGRGRGR .. BGBGBGBGBG */ + IA_CSS_BAYER_ORDER_RGGB, /** RGRGRGRGRG .. GBGBGBGBGB */ + IA_CSS_BAYER_ORDER_BGGR, /** BGBGBGBGBG .. GRGRGRGRGR */ + IA_CSS_BAYER_ORDER_GBRG, /** GBGBGBGBGB .. RGRGRGRGRG */ +}; + +#define IA_CSS_BAYER_ORDER_NUM (IA_CSS_BAYER_ORDER_GBRG + 1) + +/* Frame plane structure. This describes one plane in an image + * frame buffer. + */ +struct ia_css_frame_plane { + unsigned int height; /** height of a plane in lines */ + unsigned int width; /** width of a line, in DMA elements, note that + for RGB565 the three subpixels are stored in + one element. For all other formats this is + the number of subpixels per line. */ + unsigned int stride; /** stride of a line in bytes */ + unsigned int offset; /** offset in bytes to start of frame data. + offset is wrt data field in ia_css_frame */ +}; + +/* Binary "plane". This is used to story binary streams such as jpeg + * images. This is not actually a real plane. + */ +struct ia_css_frame_binary_plane { + unsigned int size; /** number of bytes in the stream */ + struct ia_css_frame_plane data; /** plane */ +}; + +/* Container for planar YUV frames. This contains 3 planes. + */ +struct ia_css_frame_yuv_planes { + struct ia_css_frame_plane y; /** Y plane */ + struct ia_css_frame_plane u; /** U plane */ + struct ia_css_frame_plane v; /** V plane */ +}; + +/* Container for semi-planar YUV frames. + */ +struct ia_css_frame_nv_planes { + struct ia_css_frame_plane y; /** Y plane */ + struct ia_css_frame_plane uv; /** UV plane */ +}; + +/* Container for planar RGB frames. Each color has its own plane. + */ +struct ia_css_frame_rgb_planes { + struct ia_css_frame_plane r; /** Red plane */ + struct ia_css_frame_plane g; /** Green plane */ + struct ia_css_frame_plane b; /** Blue plane */ +}; + +/* Container for 6-plane frames. These frames are used internally + * in the advanced ISP only. + */ +struct ia_css_frame_plane6_planes { + struct ia_css_frame_plane r; /** Red plane */ + struct ia_css_frame_plane r_at_b; /** Red at blue plane */ + struct ia_css_frame_plane gr; /** Red-green plane */ + struct ia_css_frame_plane gb; /** Blue-green plane */ + struct ia_css_frame_plane b; /** Blue plane */ + struct ia_css_frame_plane b_at_r; /** Blue at red plane */ +}; + +/* Crop info struct - stores the lines to be cropped in isp */ +struct ia_css_crop_info { + /* the final start column and start line + * sum of lines to be cropped + bayer offset + */ + unsigned int start_column; + unsigned int start_line; +}; + +/* Frame info struct. This describes the contents of an image frame buffer. + */ +struct ia_css_frame_info { + struct ia_css_resolution res; /** Frame resolution (valid data) */ + unsigned int padded_width; /** stride of line in memory (in pixels) */ + enum ia_css_frame_format format; /** format of the frame data */ + unsigned int raw_bit_depth; /** number of valid bits per pixel, + only valid for RAW bayer frames */ + enum ia_css_bayer_order raw_bayer_order; /** bayer order, only valid + for RAW bayer frames */ + /* the params below are computed based on bayer_order + * we can remove the raw_bayer_order if it is redundant + * keeping it for now as bxt and fpn code seem to use it + */ + struct ia_css_crop_info crop_info; +}; + +#define IA_CSS_BINARY_DEFAULT_FRAME_INFO { \ + .format = IA_CSS_FRAME_FORMAT_NUM, \ + .raw_bayer_order = IA_CSS_BAYER_ORDER_NUM, \ +} + +/** + * Specifies the DVS loop delay in "frame periods" + */ +enum ia_css_frame_delay { + IA_CSS_FRAME_DELAY_0, /** Frame delay = 0 */ + IA_CSS_FRAME_DELAY_1, /** Frame delay = 1 */ + IA_CSS_FRAME_DELAY_2 /** Frame delay = 2 */ +}; + +enum ia_css_frame_flash_state { + IA_CSS_FRAME_FLASH_STATE_NONE, + IA_CSS_FRAME_FLASH_STATE_PARTIAL, + IA_CSS_FRAME_FLASH_STATE_FULL +}; + +/* Frame structure. This structure describes an image buffer or frame. + * This is the main structure used for all input and output images. + */ +struct ia_css_frame { + /* + * The videobuf2 core will allocate buffers including room for private + * data (the rest of struct ia_css_frame). The vb2_v4l2_buffer must + * be the first member for this to work! + * Note the atomisp code also uses ia_css_frame-s which are not used + * as v4l2-buffers in some places. In this case the vb2 member will + * be unused. + */ + struct vb2_v4l2_buffer vb; + /* List-head for linking into the activeq or buffers_waiting_for_param list */ + struct list_head queue; + struct ia_css_frame_info frame_info; /** info struct describing the frame */ + ia_css_ptr data; /** pointer to start of image data */ + unsigned int data_bytes; /** size of image data in bytes */ + /* LA: move this to ia_css_buffer */ + /* + * -1 if data address is static during life time of pipeline + * >=0 if data address can change per pipeline/frame iteration + * index to dynamic data: ia_css_frame_in, ia_css_frame_out + * ia_css_frame_out_vf + * index to host-sp queue id: queue_0, queue_1 etc. + */ + int dynamic_queue_id; + /* + * if it is dynamic frame, buf_type indicates which buffer type it + * should use for event generation. we have this because in vf_pp + * binary, we use output port, but we expect VF_OUTPUT_DONE event + */ + enum ia_css_buffer_type buf_type; + enum ia_css_frame_flash_state flash_state; + unsigned int exp_id; + /** exposure id, see ia_css_event_public.h for more detail */ + u32 isp_config_id; /** Unique ID to track which config was actually applied to a particular frame */ + bool valid; /** First video output frame is not valid */ + union { + unsigned int _initialisation_dummy; + struct ia_css_frame_plane raw; + struct ia_css_frame_plane rgb; + struct ia_css_frame_rgb_planes planar_rgb; + struct ia_css_frame_plane yuyv; + struct ia_css_frame_yuv_planes yuv; + struct ia_css_frame_nv_planes nv; + struct ia_css_frame_plane6_planes plane6; + struct ia_css_frame_binary_plane binary; + } planes; /** frame planes, select the right one based on + info.format */ +}; + +#define vb_to_frame(vb2) \ + container_of(to_vb2_v4l2_buffer(vb2), struct ia_css_frame, vb) + +#define DEFAULT_FRAME { \ + .frame_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + .dynamic_queue_id = SH_CSS_INVALID_QUEUE_ID, \ + .buf_type = IA_CSS_BUFFER_TYPE_INVALID, \ + .flash_state = IA_CSS_FRAME_FLASH_STATE_NONE, \ +} + +/* @brief Allocate a CSS frame structure + * + * @param frame The allocated frame. + * @param width The width (in pixels) of the frame. + * @param height The height (in lines) of the frame. + * @param format The frame format. + * @param stride The padded stride, in pixels. + * @param raw_bit_depth The raw bit depth, in bits. + * @return The error code. + * + * Allocate a CSS frame structure. The memory for the frame data will be + * allocated in the CSS address space. + */ +int +ia_css_frame_allocate(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int stride, + unsigned int raw_bit_depth); + +/* @brief Initialize a CSS frame structure using a frame info structure. + * + * @param frame The allocated frame. + * @param[in] info The frame info structure. + * @return The error code. + * + * Initialize a frame using the resolution and format from a frame info struct. + */ +int ia_css_frame_init_from_info(struct ia_css_frame *frame, + const struct ia_css_frame_info *info); + +/* @brief Allocate a CSS frame structure using a frame info structure. + * + * @param frame The allocated frame. + * @param[in] info The frame info structure. + * @return The error code. + * + * Allocate a frame using the resolution and format from a frame info struct. + * This is a convenience function, implemented on top of + * ia_css_frame_allocate(). + */ +int +ia_css_frame_allocate_from_info(struct ia_css_frame **frame, + const struct ia_css_frame_info *info); +/* @brief Free a CSS frame structure. + * + * @param[in] frame Pointer to the frame. + * @return None + * + * Free a CSS frame structure. This will free both the frame structure + * and the pixel data pointer contained within the frame structure. + */ +void +ia_css_frame_free(struct ia_css_frame *frame); + +static inline const struct ia_css_frame_info * +ia_css_frame_get_info(const struct ia_css_frame *frame) +{ + return frame ? &frame->frame_info : NULL; +} + +#endif /* __IA_CSS_FRAME_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_host_data.h b/drivers/staging/media/atomisp/pci/ia_css_host_data.h new file mode 100644 index 000000000..f54cc504f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_host_data.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_HOST_DATA_H +#define __SH_CSS_HOST_DATA_H + +#include /* ia_css_pipe */ + +/** + * @brief Allocate structure ia_css_host_data. + * + * @param[in] size Size of the requested host data + * + * @return + * - NULL, can't allocate requested size + * - pointer to structure, field address points to host data with size bytes + */ +struct ia_css_host_data * +ia_css_host_data_allocate(size_t size); + +/** + * @brief Free structure ia_css_host_data. + * + * @param[in] me Pointer to structure, if a NULL is passed functions + * returns without error. Otherwise a valid pointer to + * structure must be passed and a related memory + * is freed. + * + * @return + */ +void ia_css_host_data_free(struct ia_css_host_data *me); + +#endif /* __SH_CSS_HOST_DATA_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_input_port.h b/drivers/staging/media/atomisp/pci/ia_css_input_port.h new file mode 100644 index 000000000..9772b6928 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_input_port.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* For MIPI_PORT0_ID to MIPI_PORT2_ID */ +#include "system_global.h" + +#ifndef __IA_CSS_INPUT_PORT_H +#define __IA_CSS_INPUT_PORT_H + +/* @file + * This file contains information about the possible input ports for CSS + */ + +/* Backward compatible for CSS API 2.0 only + * TO BE REMOVED when all drivers move to CSS API 2.1 + */ +#define IA_CSS_CSI2_PORT_4LANE MIPI_PORT0_ID +#define IA_CSS_CSI2_PORT_1LANE MIPI_PORT1_ID +#define IA_CSS_CSI2_PORT_2LANE MIPI_PORT2_ID + +/* The CSI2 interface supports 2 types of compression or can + * be run without compression. + */ +enum ia_css_csi2_compression_type { + IA_CSS_CSI2_COMPRESSION_TYPE_NONE, /** No compression */ + IA_CSS_CSI2_COMPRESSION_TYPE_1, /** Compression scheme 1 */ + IA_CSS_CSI2_COMPRESSION_TYPE_2 /** Compression scheme 2 */ +}; + +struct ia_css_csi2_compression { + enum ia_css_csi2_compression_type type; + /** Compression used */ + unsigned int compressed_bits_per_pixel; + /** Compressed bits per pixel (only when compression is enabled) */ + unsigned int uncompressed_bits_per_pixel; + /** Uncompressed bits per pixel (only when compression is enabled) */ +}; + +/* Input port structure. + */ +struct ia_css_input_port { + enum mipi_port_id port; /** Physical CSI-2 port */ + unsigned int num_lanes; /** Number of lanes used (4-lane port only) */ + unsigned int timeout; /** Timeout value */ + unsigned int rxcount; /** Register value, should include all lanes */ + struct ia_css_csi2_compression compression; /** Compression used */ +}; + +#endif /* __IA_CSS_INPUT_PORT_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_irq.h b/drivers/staging/media/atomisp/pci/ia_css_irq.h new file mode 100644 index 000000000..26b1b3c8b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_irq.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_IRQ_H +#define __IA_CSS_IRQ_H + +/* @file + * This file contains information for Interrupts/IRQs from CSS + */ + +#include "ia_css_err.h" +#include "ia_css_pipe_public.h" +#include "ia_css_input_port.h" +#include + +/* Interrupt types, these enumerate all supported interrupt types. + */ +enum ia_css_irq_type { + IA_CSS_IRQ_TYPE_EDGE, /** Edge (level) sensitive interrupt */ + IA_CSS_IRQ_TYPE_PULSE /** Pulse-shaped interrupt */ +}; + +/* Interrupt request type. + * When the CSS hardware generates an interrupt, a function in this API + * needs to be called to retrieve information about the interrupt. + * This interrupt type is part of this information and indicates what + * type of information the interrupt signals. + * + * Note that one interrupt can carry multiple interrupt types. For + * example: the online video ISP will generate only 2 interrupts, one to + * signal that the statistics (3a and DIS) are ready and one to signal + * that all output frames are done (output and viewfinder). + * + * DEPRECATED, this interface is not portable it should only define user + * (SW) interrupts + */ +enum ia_css_irq_info { + IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR = BIT(0), + /** the css receiver has encountered an error */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW = BIT(1), + /** the FIFO in the csi receiver has overflown */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF = BIT(2), + /** the css receiver received the start of frame */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_EOF = BIT(3), + /** the css receiver received the end of frame */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_SOL = BIT(4), + /** the css receiver received the start of line */ + IA_CSS_IRQ_INFO_EVENTS_READY = BIT(5), + /** One or more events are available in the PSYS event queue */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_EOL = BIT(6), + /** the css receiver received the end of line */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_SIDEBAND_CHANGED = BIT(7), + /** the css receiver received a change in side band signals */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_GEN_SHORT_0 = BIT(8), + /** generic short packets (0) */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_GEN_SHORT_1 = BIT(9), + /** generic short packets (1) */ + IA_CSS_IRQ_INFO_IF_PRIM_ERROR = BIT(10), + /** the primary input formatter (A) has encountered an error */ + IA_CSS_IRQ_INFO_IF_PRIM_B_ERROR = BIT(11), + /** the primary input formatter (B) has encountered an error */ + IA_CSS_IRQ_INFO_IF_SEC_ERROR = BIT(12), + /** the secondary input formatter has encountered an error */ + IA_CSS_IRQ_INFO_STREAM_TO_MEM_ERROR = BIT(13), + /** the stream-to-memory device has encountered an error */ + IA_CSS_IRQ_INFO_SW_0 = BIT(14), + /** software interrupt 0 */ + IA_CSS_IRQ_INFO_SW_1 = BIT(15), + /** software interrupt 1 */ + IA_CSS_IRQ_INFO_SW_2 = BIT(16), + /** software interrupt 2 */ + IA_CSS_IRQ_INFO_ISP_BINARY_STATISTICS_READY = BIT(17), + /** ISP binary statistics are ready */ + IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR = BIT(18), + /** the input system in in error */ + IA_CSS_IRQ_INFO_IF_ERROR = BIT(19), + /** the input formatter in in error */ + IA_CSS_IRQ_INFO_DMA_ERROR = BIT(20), + /** the dma in in error */ + IA_CSS_IRQ_INFO_ISYS_EVENTS_READY = BIT(21), + /** end-of-frame events are ready in the isys_event queue */ +}; + +/* CSS receiver error types. Whenever the CSS receiver has encountered + * an error, this enumeration is used to indicate which errors have occurred. + * + * Note that multiple error flags can be enabled at once and that this is in + * fact common (whenever an error occurs, it usually results in multiple + * errors). + * + * DEPRECATED: This interface is not portable, different systems have + * different receiver types, or possibly none in case of tests systems. + */ +enum ia_css_rx_irq_info { + IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN = BIT(0), /** buffer overrun */ + IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE = BIT(1), /** entering sleep mode */ + IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE = BIT(2), /** exited sleep mode */ + IA_CSS_RX_IRQ_INFO_ECC_CORRECTED = BIT(3), /** ECC corrected */ + IA_CSS_RX_IRQ_INFO_ERR_SOT = BIT(4), + /** Start of transmission */ + IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC = BIT(5), /** SOT sync (??) */ + IA_CSS_RX_IRQ_INFO_ERR_CONTROL = BIT(6), /** Control (??) */ + IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE = BIT(7), /** Double ECC */ + IA_CSS_RX_IRQ_INFO_ERR_CRC = BIT(8), /** CRC error */ + IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID = BIT(9), /** Unknown ID */ + IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC = BIT(10), /** Frame sync error */ + IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA = BIT(11), /** Frame data error */ + IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT = BIT(12), /** Timeout occurred */ + IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC = BIT(13), /** Unknown escape seq. */ + IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC = BIT(14), /** Line Sync error */ + IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT = BIT(15), +}; + +/* Interrupt info structure. This structure contains information about an + * interrupt. This needs to be used after an interrupt is received on the IA + * to perform the correct action. + */ +struct ia_css_irq { + enum ia_css_irq_info type; /** Interrupt type. */ + unsigned int sw_irq_0_val; /** In case of SW interrupt 0, value. */ + unsigned int sw_irq_1_val; /** In case of SW interrupt 1, value. */ + unsigned int sw_irq_2_val; /** In case of SW interrupt 2, value. */ + struct ia_css_pipe *pipe; + /** The image pipe that generated the interrupt. */ +}; + +/* @brief Obtain interrupt information. + * + * @param[out] info Pointer to the interrupt info. The interrupt + * information wil be written to this info. + * @return If an error is encountered during the interrupt info + * and no interrupt could be translated successfully, this + * will return IA_CSS_INTERNAL_ERROR. Otherwise + * 0. + * + * This function is expected to be executed after an interrupt has been sent + * to the IA from the CSS. This function returns information about the interrupt + * which is needed by the IA code to properly handle the interrupt. This + * information includes the image pipe, buffer type etc. + */ +int +ia_css_irq_translate(unsigned int *info); + +/* @brief Get CSI receiver error info. + * + * @param[out] irq_bits Pointer to the interrupt bits. The interrupt + * bits will be written this info. + * This will be the error bits that are enabled in the CSI + * receiver error register. + * @return None + * + * This function should be used whenever a CSI receiver error interrupt is + * generated. It provides the detailed information (bits) on the exact error + * that occurred. + * + *@deprecated {this function is DEPRECATED since it only works on CSI port 1. + * Use the function below instead and specify the appropriate port.} + */ +void +ia_css_rx_get_irq_info(unsigned int *irq_bits); + +/* @brief Get CSI receiver error info. + * + * @param[in] port Input port identifier. + * @param[out] irq_bits Pointer to the interrupt bits. The interrupt + * bits will be written this info. + * This will be the error bits that are enabled in the CSI + * receiver error register. + * @return None + * + * This function should be used whenever a CSI receiver error interrupt is + * generated. It provides the detailed information (bits) on the exact error + * that occurred. + */ +void +ia_css_rx_port_get_irq_info(enum mipi_port_id port, unsigned int *irq_bits); + +/* @brief Clear CSI receiver error info. + * + * @param[in] irq_bits The bits that should be cleared from the CSI receiver + * interrupt bits register. + * @return None + * + * This function should be called after ia_css_rx_get_irq_info has been called + * and the error bits have been interpreted. It is advised to use the return + * value of that function as the argument to this function to make sure no new + * error bits get overwritten. + * + * @deprecated{this function is DEPRECATED since it only works on CSI port 1. + * Use the function below instead and specify the appropriate port.} + */ +void +ia_css_rx_clear_irq_info(unsigned int irq_bits); + +/* @brief Clear CSI receiver error info. + * + * @param[in] port Input port identifier. + * @param[in] irq_bits The bits that should be cleared from the CSI receiver + * interrupt bits register. + * @return None + * + * This function should be called after ia_css_rx_get_irq_info has been called + * and the error bits have been interpreted. It is advised to use the return + * value of that function as the argument to this function to make sure no new + * error bits get overwritten. + */ +void +ia_css_rx_port_clear_irq_info(enum mipi_port_id port, unsigned int irq_bits); + +/* @brief Enable or disable specific interrupts. + * + * @param[in] type The interrupt type that will be enabled/disabled. + * @param[in] enable enable or disable. + * @return Returns IA_CSS_INTERNAL_ERROR if this interrupt + * type cannot be enabled/disabled which is true for + * CSS internal interrupts. Otherwise returns + * 0. + */ +int +ia_css_irq_enable(enum ia_css_irq_info type, bool enable); + +#endif /* __IA_CSS_IRQ_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_isp_configs.c b/drivers/staging/media/atomisp/pci/ia_css_isp_configs.c new file mode 100644 index 000000000..d28a76a68 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_isp_configs.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_pipeline.h" +#include "ia_css_isp_configs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +int ia_css_configure_iterator(const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.iterator.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; + + ia_css_iterator_config((struct sh_css_isp_iterator_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_copy_output(const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; + + ia_css_copy_output_config((struct sh_css_isp_copy_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +int ia_css_configure_crop(const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.crop.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; + + ia_css_crop_config((struct sh_css_isp_crop_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_fpn(const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.fpn.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset; + ia_css_fpn_config((struct sh_css_isp_fpn_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_dvs(const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.dvs.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset; + ia_css_dvs_config((struct sh_css_isp_dvs_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_qplane(const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.qplane.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset; + ia_css_qplane_config((struct sh_css_isp_qplane_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + + return 0; +} + +int ia_css_configure_output0(const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.output0.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset; + + ia_css_output0_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_output1(const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.output1.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset; + + ia_css_output1_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_output(const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.output.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.output.offset; + + ia_css_output_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_raw(const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.raw.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset; + + ia_css_raw_config((struct sh_css_isp_raw_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_tnr(const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.tnr.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset; + + ia_css_tnr_config((struct sh_css_isp_tnr_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_ref(const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.ref.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset; + + ia_css_ref_config((struct sh_css_isp_ref_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} + +int ia_css_configure_vf(const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem) +{ + unsigned int offset = 0; + unsigned int size = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s:\n", __func__); + + if (!binary->info->mem_offsets.offsets.config) + return 0; + + size = binary->info->mem_offsets.offsets.config->dmem.vf.size; + if (!size) + return 0; + + offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset; + + ia_css_vf_config((struct sh_css_isp_vf_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/ia_css_isp_configs.h b/drivers/staging/media/atomisp/pci/ia_css_isp_configs.h new file mode 100644 index 000000000..fffcfc871 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_isp_configs.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifdef IA_CSS_INCLUDE_CONFIGURATIONS +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h" +#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h" +#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h" +#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h" +#endif + +#ifndef _IA_CSS_ISP_CONFIG_H +#define _IA_CSS_ISP_CONFIG_H + +enum ia_css_configuration_ids { + IA_CSS_ITERATOR_CONFIG_ID, + IA_CSS_COPY_OUTPUT_CONFIG_ID, + IA_CSS_CROP_CONFIG_ID, + IA_CSS_FPN_CONFIG_ID, + IA_CSS_DVS_CONFIG_ID, + IA_CSS_QPLANE_CONFIG_ID, + IA_CSS_OUTPUT0_CONFIG_ID, + IA_CSS_OUTPUT1_CONFIG_ID, + IA_CSS_OUTPUT_CONFIG_ID, + IA_CSS_RAW_CONFIG_ID, + IA_CSS_TNR_CONFIG_ID, + IA_CSS_REF_CONFIG_ID, + IA_CSS_VF_CONFIG_ID, + + /* ISP 2401 */ + IA_CSS_SC_CONFIG_ID, + + IA_CSS_NUM_CONFIGURATION_IDS +}; + +struct ia_css_config_memory_offsets { + struct { + struct ia_css_isp_parameter iterator; + struct ia_css_isp_parameter copy_output; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter dvs; + struct ia_css_isp_parameter qplane; + struct ia_css_isp_parameter output0; + struct ia_css_isp_parameter output1; + struct ia_css_isp_parameter output; + struct ia_css_isp_parameter raw; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + struct ia_css_isp_parameter vf; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_CONFIGURATIONS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ + +int ia_css_configure_iterator(const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem); + +int ia_css_configure_copy_output(const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem); + +int ia_css_configure_crop(const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem); + +int ia_css_configure_fpn(const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem); + +int ia_css_configure_dvs(const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem); + +int ia_css_configure_qplane(const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem); +int ia_css_configure_output0(const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem); + +int ia_css_configure_output1(const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem); + +int ia_css_configure_output(const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem); + +int ia_css_configure_raw(const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem); + +int ia_css_configure_tnr(const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem); + +int ia_css_configure_ref(const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem); + +int ia_css_configure_vf(const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem); + +#endif /* IA_CSS_INCLUDE_CONFIGURATION */ + +#endif /* _IA_CSS_ISP_CONFIG_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_isp_params.c b/drivers/staging/media/atomisp/pci/ia_css_isp_params.c new file mode 100644 index 000000000..503ac65da --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_isp_params.c @@ -0,0 +1,3344 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_PARAMETERS +#include "sh_css_params.h" +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/anr/anr_1.0/ia_css_anr.host.h" +#include "isp/kernels/anr/anr_2/ia_css_anr2.host.h" +#include "isp/kernels/bh/bh_2/ia_css_bh.host.h" +#include "isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h" +#include "isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/csc/csc_1.0/ia_css_csc.host.h" +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h" +#include "isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h" +#include "isp/kernels/ctc/ctc2/ia_css_ctc2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/de/de_2/ia_css_de2.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/gc/gc_1.0/ia_css_gc.host.h" +#include "isp/kernels/gc/gc_2/ia_css_gc2.host.h" +#include "isp/kernels/macc/macc_1.0/ia_css_macc.host.h" +#include "isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/ob/ob2/ia_css_ob2.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#include "isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h" +#include "isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/uds/uds_1.0/ia_css_uds_param.h" +#include "isp/kernels/wb/wb_1.0/ia_css_wb.host.h" +#include "isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h" +#include "isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h" +#include "isp/kernels/fc/fc_1.0/ia_css_formats.host.h" +#include "isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +#include "isp/kernels/bnlm/ia_css_bnlm.host.h" +#include "isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h" +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_params.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_aa( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; + + if (size) { + struct sh_css_isp_aa_params *t = (struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + t->strength = params->aa_config.strength; + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_anr() enter:\n"); + + ia_css_anr_encode((struct sh_css_isp_anr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->anr_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_anr() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr2( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_anr2() enter:\n"); + + ia_css_anr2_vmem_encode((struct ia_css_isp_anr2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->anr_thres, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_anr2() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bh( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.bh.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + ia_css_bh_encode((struct sh_css_isp_bh_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + } + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_HMEM0] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_cnr( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_cnr() enter:\n"); + + ia_css_cnr_encode((struct sh_css_isp_cnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cnr_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_cnr() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_crop( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.crop.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_crop() enter:\n"); + + ia_css_crop_encode((struct sh_css_isp_crop_isp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->crop_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_crop() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_csc( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.csc.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_csc() enter:\n"); + + ia_css_csc_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cc_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_csc() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_dp( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.dp.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() enter:\n"); + + ia_css_dp_encode((struct sh_css_isp_dp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dp_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bnr( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_bnr() enter:\n"); + + ia_css_bnr_encode((struct sh_css_isp_bnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_bnr() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_de( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.de.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.de.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() enter:\n"); + + ia_css_de_encode((struct sh_css_isp_de_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->de_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ecd( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_ecd() enter:\n"); + + ia_css_ecd_encode((struct sh_css_isp_ecd_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ecd_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_ecd() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_formats( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.formats.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_formats() enter:\n"); + + ia_css_formats_encode((struct sh_css_isp_formats_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->formats_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_formats() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fpn( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_fpn() enter:\n"); + + ia_css_fpn_encode((struct sh_css_isp_fpn_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fpn_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_fpn() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_gc( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.gc.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_encode((struct sh_css_isp_gc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->gc_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + } + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_vamem_encode((struct sh_css_isp_gc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->gc_table, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ce( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.ce.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() enter:\n"); + + ia_css_ce_encode((struct sh_css_isp_ce_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ce_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yuv2rgb( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_yuv2rgb() enter:\n"); + + ia_css_yuv2rgb_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yuv2rgb_cc_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_yuv2rgb() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_rgb2yuv( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_rgb2yuv() enter:\n"); + + ia_css_rgb2yuv_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->rgb2yuv_cc_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_rgb2yuv() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_r_gamma( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_r_gamma() enter:\n"); + + ia_css_r_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->r_gamma_table, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_r_gamma() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_g_gamma( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_g_gamma() enter:\n"); + + ia_css_g_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->g_gamma_table, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_g_gamma() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_b_gamma( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_b_gamma() enter:\n"); + + ia_css_b_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM2].address[offset], + ¶ms->b_gamma_table, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM2] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_b_gamma() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_uds( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.uds.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset; + + if (size) { + struct sh_css_sp_uds_params *p; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_uds() enter:\n"); + + p = (struct sh_css_sp_uds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + p->crop_pos = params->uds_config.crop_pos; + p->uds = params->uds_config.uds; + + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_uds() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_raa( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.raa.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_raa() enter:\n"); + + ia_css_raa_encode((struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->raa_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_raa() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_s3a( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_s3a() enter:\n"); + + ia_css_s3a_encode((struct sh_css_isp_s3a_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_s3a() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ob( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.ob.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_encode((struct sh_css_isp_ob_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ob_config, + ¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + } + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vmem.ob.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_vmem_encode((struct sh_css_isp_ob_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->ob_config, + ¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_output( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.output.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.output.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_output() enter:\n"); + + ia_css_output_encode((struct sh_css_isp_output_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->output_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_output() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sc( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.sc.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() enter:\n"); + + ia_css_sc_encode((struct sh_css_isp_sc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->sc_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bds( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.bds.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset; + + if (size) { + struct sh_css_isp_bds_params *p; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_bds() enter:\n"); + + p = (struct sh_css_isp_bds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + p->baf_strength = params->bds_config.strength; + + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_bds() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_tnr( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_tnr() enter:\n"); + + ia_css_tnr_encode((struct sh_css_isp_tnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->tnr_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_tnr() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_macc( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.macc.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_macc() enter:\n"); + + ia_css_macc_encode((struct sh_css_isp_macc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->macc_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_macc() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horicoef( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis_horicoef() enter:\n"); + + ia_css_sdis_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis_horicoef() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertcoef( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis_vertcoef() enter:\n"); + + ia_css_sdis_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis_vertcoef() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horiproj( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis_horiproj() enter:\n"); + + ia_css_sdis_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis_horiproj() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertproj( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis_vertproj() enter:\n"); + + ia_css_sdis_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis_vertproj() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horicoef( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis2_horicoef() enter:\n"); + + ia_css_sdis2_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis2_horicoef() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertcoef( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis2_vertcoef() enter:\n"); + + ia_css_sdis2_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis2_vertcoef() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horiproj( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis2_horiproj() enter:\n"); + + ia_css_sdis2_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis2_horiproj() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertproj( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis2_vertproj() enter:\n"); + + ia_css_sdis2_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_sdis2_vertproj() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_wb( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.wb.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() enter:\n"); + + ia_css_wb_encode((struct sh_css_isp_wb_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->wb_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_nr( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.nr.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() enter:\n"); + + ia_css_nr_encode((struct sh_css_isp_ynr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yee( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.yee.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_yee() enter:\n"); + + ia_css_yee_encode((struct sh_css_isp_yee_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yee_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_yee() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ynr( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_ynr() enter:\n"); + + ia_css_ynr_encode((struct sh_css_isp_yee2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ynr_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_ynr() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fc( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.fc.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() enter:\n"); + + ia_css_fc_encode((struct sh_css_isp_fc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fc_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ctc( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_encode((struct sh_css_isp_ctc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ctc_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_ctc() leave:\n"); + } + } + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_vamem_encode((struct sh_css_isp_ctc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->ctc_table, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_ctc() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr_table( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_xnr_table() enter:\n"); + + ia_css_xnr_table_vamem_encode((struct sh_css_isp_xnr_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->xnr_table, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_xnr_table() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_xnr() enter:\n"); + + ia_css_xnr_encode((struct sh_css_isp_xnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_xnr() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr3( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params); + + { + unsigned int size = + stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size; + + unsigned int offset = + stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_encode((struct sh_css_isp_xnr3_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr3_config, + size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = + true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_process_xnr3() leave:\n"); + } + } +} + +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) = { + ia_css_process_aa, + ia_css_process_anr, + ia_css_process_anr2, + ia_css_process_bh, + ia_css_process_cnr, + ia_css_process_crop, + ia_css_process_csc, + ia_css_process_dp, + ia_css_process_bnr, + ia_css_process_de, + ia_css_process_ecd, + ia_css_process_formats, + ia_css_process_fpn, + ia_css_process_gc, + ia_css_process_ce, + ia_css_process_yuv2rgb, + ia_css_process_rgb2yuv, + ia_css_process_r_gamma, + ia_css_process_g_gamma, + ia_css_process_b_gamma, + ia_css_process_uds, + ia_css_process_raa, + ia_css_process_s3a, + ia_css_process_ob, + ia_css_process_output, + ia_css_process_sc, + ia_css_process_bds, + ia_css_process_tnr, + ia_css_process_macc, + ia_css_process_sdis_horicoef, + ia_css_process_sdis_vertcoef, + ia_css_process_sdis_horiproj, + ia_css_process_sdis_vertproj, + ia_css_process_sdis2_horicoef, + ia_css_process_sdis2_vertcoef, + ia_css_process_sdis2_horiproj, + ia_css_process_sdis2_vertproj, + ia_css_process_wb, + ia_css_process_nr, + ia_css_process_yee, + ia_css_process_ynr, + ia_css_process_fc, + ia_css_process_ctc, + ia_css_process_xnr_table, + ia_css_process_xnr, + ia_css_process_xnr3, +}; + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_dp_config(const struct ia_css_isp_parameters *params, + struct ia_css_dp_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_dp_config() enter: config=%p\n", + config); + + *config = params->dp_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_dp_config() leave\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_dp_config() enter:\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dp_config = *config; + params->config_changed[IA_CSS_DP_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_dp_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_wb_config(const struct ia_css_isp_parameters *params, + struct ia_css_wb_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_wb_config() enter: config=%p\n", + config); + + *config = params->wb_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_wb_config() leave\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_wb_config() enter:\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->wb_config = *config; + params->config_changed[IA_CSS_WB_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_wb_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_tnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_tnr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_tnr_config() enter: config=%p\n", + config); + + *config = params->tnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_tnr_config() leave\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_tnr_config() enter:\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->tnr_config = *config; + params->config_changed[IA_CSS_TNR_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_tnr_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ob_config(const struct ia_css_isp_parameters *params, + struct ia_css_ob_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ob_config() enter: config=%p\n", + config); + + *config = params->ob_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ob_config() leave\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ob_config() enter:\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ob_config = *config; + params->config_changed[IA_CSS_OB_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_ob_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_de_config(const struct ia_css_isp_parameters *params, + struct ia_css_de_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_de_config() enter: config=%p\n", + config); + + *config = params->de_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_de_config() leave\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_de_config() enter:\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->de_config = *config; + params->config_changed[IA_CSS_DE_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_de_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_anr_config() enter: config=%p\n", + config); + + *config = params->anr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_anr_config() leave\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr_config() enter:\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_config = *config; + params->config_changed[IA_CSS_ANR_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_anr_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr2_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_thres *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_anr2_config() enter: config=%p\n", + config); + + *config = params->anr_thres; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_anr2_config() leave\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr2_config() enter:\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_thres = *config; + params->config_changed[IA_CSS_ANR2_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_anr2_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ce_config(const struct ia_css_isp_parameters *params, + struct ia_css_ce_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ce_config() enter: config=%p\n", + config); + + *config = params->ce_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ce_config() leave\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ce_config() enter:\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ce_config = *config; + params->config_changed[IA_CSS_CE_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_ce_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ecd_config(const struct ia_css_isp_parameters *params, + struct ia_css_ecd_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ecd_config() enter: config=%p\n", + config); + + *config = params->ecd_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ecd_config() leave\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ecd_config() enter:\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ecd_config = *config; + params->config_changed[IA_CSS_ECD_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_ecd_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ynr_config(const struct ia_css_isp_parameters *params, + struct ia_css_ynr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ynr_config() enter: config=%p\n", + config); + + *config = params->ynr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ynr_config() leave\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ynr_config() enter:\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ynr_config = *config; + params->config_changed[IA_CSS_YNR_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_ynr_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_fc_config(const struct ia_css_isp_parameters *params, + struct ia_css_fc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_fc_config() enter: config=%p\n", + config); + + *config = params->fc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_fc_config() leave\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_fc_config() enter:\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->fc_config = *config; + params->config_changed[IA_CSS_FC_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_fc_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_cnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_cnr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_cnr_config() enter: config=%p\n", + config); + + *config = params->cnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_cnr_config() leave\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_cnr_config() enter:\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cnr_config = *config; + params->config_changed[IA_CSS_CNR_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_cnr_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_macc_config(const struct ia_css_isp_parameters *params, + struct ia_css_macc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_macc_config() enter: config=%p\n", + config); + + *config = params->macc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_macc_config() leave\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_macc_config() enter:\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->macc_config = *config; + params->config_changed[IA_CSS_MACC_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_macc_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ctc_config(const struct ia_css_isp_parameters *params, + struct ia_css_ctc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ctc_config() enter: config=%p\n", + config); + + *config = params->ctc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_ctc_config() leave\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ctc_config() enter:\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ctc_config = *config; + params->config_changed[IA_CSS_CTC_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_ctc_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_aa_config(const struct ia_css_isp_parameters *params, + struct ia_css_aa_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_aa_config() enter: config=%p\n", + config); + + *config = params->aa_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_aa_config() leave\n"); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_aa_config() enter:\n"); + params->aa_config = *config; + params->config_changed[IA_CSS_AA_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_aa_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_yuv2rgb_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_yuv2rgb_config() enter: config=%p\n", + config); + + *config = params->yuv2rgb_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_yuv2rgb_config() leave\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_yuv2rgb_config() enter:\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->yuv2rgb_cc_config = *config; + params->config_changed[IA_CSS_YUV2RGB_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_yuv2rgb_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_rgb2yuv_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_rgb2yuv_config() enter: config=%p\n", + config); + + *config = params->rgb2yuv_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_rgb2yuv_config() leave\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_rgb2yuv_config() enter:\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->rgb2yuv_cc_config = *config; + params->config_changed[IA_CSS_RGB2YUV_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_rgb2yuv_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_csc_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_csc_config() enter: config=%p\n", + config); + + *config = params->cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_csc_config() leave\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_csc_config() enter:\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cc_config = *config; + params->config_changed[IA_CSS_CSC_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_csc_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_nr_config(const struct ia_css_isp_parameters *params, + struct ia_css_nr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_nr_config() enter: config=%p\n", + config); + + *config = params->nr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_nr_config() leave\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_nr_config() enter:\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->nr_config = *config; + params->config_changed[IA_CSS_BNR_ID] = true; + params->config_changed[IA_CSS_NR_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_nr_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_gc_config(const struct ia_css_isp_parameters *params, + struct ia_css_gc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_gc_config() enter: config=%p\n", + config); + + *config = params->gc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_gc_config() leave\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_gc_config() enter:\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->gc_config = *config; + params->config_changed[IA_CSS_GC_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_gc_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis_horicoef_config() enter: config=%p\n", + config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis_horicoef_config() leave\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_sdis_horicoef_config() enter:\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_sdis_horicoef_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis_vertcoef_config() enter: config=%p\n", + config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis_vertcoef_config() leave\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_sdis_vertcoef_config() enter:\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_sdis_vertcoef_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis_horiproj_config() enter: config=%p\n", + config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis_horiproj_config() leave\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_sdis_horiproj_config() enter:\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_sdis_horiproj_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis_vertproj_config() enter: config=%p\n", + config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis_vertproj_config() leave\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_sdis_vertproj_config() enter:\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_sdis_vertproj_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis2_horicoef_config() enter: config=%p\n", + config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis2_horicoef_config() leave\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_sdis2_horicoef_config() enter:\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_sdis2_horicoef_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis2_vertcoef_config() enter: config=%p\n", + config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis2_vertcoef_config() leave\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_sdis2_vertcoef_config() enter:\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_sdis2_vertcoef_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis2_horiproj_config() enter: config=%p\n", + config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis2_horiproj_config() leave\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_sdis2_horiproj_config() enter:\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_sdis2_horiproj_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis2_vertproj_config() enter: config=%p\n", + config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_sdis2_vertproj_config() leave\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_sdis2_vertproj_config() enter:\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_sdis2_vertproj_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_r_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_r_gamma_config() enter: config=%p\n", + config); + + *config = params->r_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_r_gamma_config() leave\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_r_gamma_config() enter:\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->r_gamma_table = *config; + params->config_changed[IA_CSS_R_GAMMA_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_r_gamma_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_g_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_g_gamma_config() enter: config=%p\n", + config); + + *config = params->g_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_g_gamma_config() leave\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_g_gamma_config() enter:\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->g_gamma_table = *config; + params->config_changed[IA_CSS_G_GAMMA_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_g_gamma_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_b_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_b_gamma_config() enter: config=%p\n", + config); + + *config = params->b_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_b_gamma_config() leave\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_b_gamma_config() enter:\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->b_gamma_table = *config; + params->config_changed[IA_CSS_B_GAMMA_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_b_gamma_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_table_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_table *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_xnr_table_config() enter: config=%p\n", + config); + + *config = params->xnr_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_xnr_table_config() leave\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_xnr_table_config() enter:\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_table = *config; + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_xnr_table_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_formats_config(const struct ia_css_isp_parameters *params, + struct ia_css_formats_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_formats_config() enter: config=%p\n", + config); + + *config = params->formats_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_formats_config() leave\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_formats_config() enter:\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->formats_config = *config; + params->config_changed[IA_CSS_FORMATS_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_formats_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_xnr_config() enter: config=%p\n", + config); + + *config = params->xnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_xnr_config() leave\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_config() enter:\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_config = *config; + params->config_changed[IA_CSS_XNR_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_xnr_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr3_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr3_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_xnr3_config() enter: config=%p\n", + config); + + *config = params->xnr3_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_xnr3_config() leave\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr3_config() enter:\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr3_config = *config; + params->config_changed[IA_CSS_XNR3_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_xnr3_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_s3a_config(const struct ia_css_isp_parameters *params, + struct ia_css_3a_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_s3a_config() enter: config=%p\n", + config); + + *config = params->s3a_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_s3a_config() leave\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_s3a_config() enter:\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->s3a_config = *config; + params->config_changed[IA_CSS_BH_ID] = true; + params->config_changed[IA_CSS_S3A_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_s3a_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_output_config(const struct ia_css_isp_parameters *params, + struct ia_css_output_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_output_config() enter: config=%p\n", + config); + + *config = params->output_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_get_output_config() leave\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config) +{ + if (!config) + return; + + assert(params); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_output_config() enter:\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->output_config = *config; + params->config_changed[IA_CSS_OUTPUT_ID] = true; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_set_output_config() leave: return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_get_dp_config(params, config->dp_config); + ia_css_get_wb_config(params, config->wb_config); + ia_css_get_tnr_config(params, config->tnr_config); + ia_css_get_ob_config(params, config->ob_config); + ia_css_get_de_config(params, config->de_config); + ia_css_get_anr_config(params, config->anr_config); + ia_css_get_anr2_config(params, config->anr_thres); + ia_css_get_ce_config(params, config->ce_config); + ia_css_get_ecd_config(params, config->ecd_config); + ia_css_get_ynr_config(params, config->ynr_config); + ia_css_get_fc_config(params, config->fc_config); + ia_css_get_cnr_config(params, config->cnr_config); + ia_css_get_macc_config(params, config->macc_config); + ia_css_get_ctc_config(params, config->ctc_config); + ia_css_get_aa_config(params, config->aa_config); + ia_css_get_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_get_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_get_csc_config(params, config->cc_config); + ia_css_get_nr_config(params, config->nr_config); + ia_css_get_gc_config(params, config->gc_config); + ia_css_get_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_get_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_get_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_get_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_get_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_get_r_gamma_config(params, config->r_gamma_table); + ia_css_get_g_gamma_config(params, config->g_gamma_table); + ia_css_get_b_gamma_config(params, config->b_gamma_table); + ia_css_get_xnr_table_config(params, config->xnr_table); + ia_css_get_formats_config(params, config->formats_config); + ia_css_get_xnr_config(params, config->xnr_config); + ia_css_get_xnr3_config(params, config->xnr3_config); + ia_css_get_s3a_config(params, config->s3a_config); + ia_css_get_output_config(params, config->output_config); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_set_dp_config(params, config->dp_config); + ia_css_set_wb_config(params, config->wb_config); + ia_css_set_tnr_config(params, config->tnr_config); + ia_css_set_ob_config(params, config->ob_config); + ia_css_set_de_config(params, config->de_config); + ia_css_set_anr_config(params, config->anr_config); + ia_css_set_anr2_config(params, config->anr_thres); + ia_css_set_ce_config(params, config->ce_config); + ia_css_set_ecd_config(params, config->ecd_config); + ia_css_set_ynr_config(params, config->ynr_config); + ia_css_set_fc_config(params, config->fc_config); + ia_css_set_cnr_config(params, config->cnr_config); + ia_css_set_macc_config(params, config->macc_config); + ia_css_set_ctc_config(params, config->ctc_config); + ia_css_set_aa_config(params, config->aa_config); + ia_css_set_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_set_csc_config(params, config->cc_config); + ia_css_set_nr_config(params, config->nr_config); + ia_css_set_gc_config(params, config->gc_config); + ia_css_set_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_set_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_set_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_set_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_set_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_set_r_gamma_config(params, config->r_gamma_table); + ia_css_set_g_gamma_config(params, config->g_gamma_table); + ia_css_set_b_gamma_config(params, config->b_gamma_table); + ia_css_set_xnr_table_config(params, config->xnr_table); + ia_css_set_formats_config(params, config->formats_config); + ia_css_set_xnr_config(params, config->xnr_config); + ia_css_set_xnr3_config(params, config->xnr3_config); + ia_css_set_s3a_config(params, config->s3a_config); + ia_css_set_output_config(params, config->output_config); +} diff --git a/drivers/staging/media/atomisp/pci/ia_css_isp_params.h b/drivers/staging/media/atomisp/pci/ia_css_isp_params.h new file mode 100644 index 000000000..c2de68987 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_isp_params.h @@ -0,0 +1,392 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_PARAM_H +#define _IA_CSS_ISP_PARAM_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_parameter_ids { + IA_CSS_AA_ID, + IA_CSS_ANR_ID, + IA_CSS_ANR2_ID, + IA_CSS_BH_ID, + IA_CSS_CNR_ID, + IA_CSS_CROP_ID, + IA_CSS_CSC_ID, + IA_CSS_DP_ID, + IA_CSS_BNR_ID, + IA_CSS_DE_ID, + IA_CSS_ECD_ID, + IA_CSS_FORMATS_ID, + IA_CSS_FPN_ID, + IA_CSS_GC_ID, + IA_CSS_CE_ID, + IA_CSS_YUV2RGB_ID, + IA_CSS_RGB2YUV_ID, + IA_CSS_R_GAMMA_ID, + IA_CSS_G_GAMMA_ID, + IA_CSS_B_GAMMA_ID, + IA_CSS_UDS_ID, + IA_CSS_RAA_ID, + IA_CSS_S3A_ID, + IA_CSS_OB_ID, + IA_CSS_OUTPUT_ID, + IA_CSS_SC_ID, + IA_CSS_BDS_ID, + IA_CSS_TNR_ID, + IA_CSS_MACC_ID, + IA_CSS_SDIS_HORICOEF_ID, + IA_CSS_SDIS_VERTCOEF_ID, + IA_CSS_SDIS_HORIPROJ_ID, + IA_CSS_SDIS_VERTPROJ_ID, + IA_CSS_SDIS2_HORICOEF_ID, + IA_CSS_SDIS2_VERTCOEF_ID, + IA_CSS_SDIS2_HORIPROJ_ID, + IA_CSS_SDIS2_VERTPROJ_ID, + IA_CSS_WB_ID, + IA_CSS_NR_ID, + IA_CSS_YEE_ID, + IA_CSS_YNR_ID, + IA_CSS_FC_ID, + IA_CSS_CTC_ID, + IA_CSS_XNR_TABLE_ID, + IA_CSS_XNR_ID, + IA_CSS_XNR3_ID, + IA_CSS_NUM_PARAMETER_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter anr; + struct ia_css_isp_parameter bh; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter csc; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter bnr; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ecd; + struct ia_css_isp_parameter formats; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter ce; + struct ia_css_isp_parameter yuv2rgb; + struct ia_css_isp_parameter rgb2yuv; + struct ia_css_isp_parameter uds; + struct ia_css_isp_parameter raa; + struct ia_css_isp_parameter s3a; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter output; + struct ia_css_isp_parameter sc; + struct ia_css_isp_parameter bds; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter macc; + struct ia_css_isp_parameter sdis_horiproj; + struct ia_css_isp_parameter sdis_vertproj; + struct ia_css_isp_parameter sdis2_horiproj; + struct ia_css_isp_parameter sdis2_vertproj; + struct ia_css_isp_parameter wb; + struct ia_css_isp_parameter nr; + struct ia_css_isp_parameter yee; + struct ia_css_isp_parameter ynr; + struct ia_css_isp_parameter fc; + struct ia_css_isp_parameter ctc; + struct ia_css_isp_parameter xnr; + struct ia_css_isp_parameter xnr3; + struct ia_css_isp_parameter get; + struct ia_css_isp_parameter put; + } dmem; + struct { + struct ia_css_isp_parameter anr2; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter sdis_horicoef; + struct ia_css_isp_parameter sdis_vertcoef; + struct ia_css_isp_parameter sdis2_horicoef; + struct ia_css_isp_parameter sdis2_vertcoef; + } vmem; + struct { + struct ia_css_isp_parameter bh; + } hmem0; + struct { + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter g_gamma; + struct ia_css_isp_parameter xnr_table; + } vamem1; + struct { + struct ia_css_isp_parameter r_gamma; + struct ia_css_isp_parameter ctc; + } vamem0; + struct { + struct ia_css_isp_parameter b_gamma; + } vamem2; +}; + +#if defined(IA_CSS_INCLUDE_PARAMETERS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +struct ia_css_pipeline_stage; /* forward declaration */ + +extern void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config); + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; + +#endif /* IA_CSS_INCLUDE_PARAMETER */ +#endif /* _IA_CSS_ISP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_isp_states.c b/drivers/staging/media/atomisp/pci/ia_css_isp_states.c new file mode 100644 index 000000000..a6bc2e9ed --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_isp_states.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_states.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_aa_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_aa_state() enter:\n"); + + { + unsigned int size = binary->info->mem_offsets.offsets.state->vmem.aa.size; + + unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset; + + if (size) + memset(&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + 0, size); + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_aa_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_cnr_state() enter:\n"); + + { + unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr.size; + + unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset; + + if (size) { + ia_css_init_cnr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_cnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr2_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_cnr2_state() enter:\n"); + + { + unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size; + + unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset; + + if (size) { + ia_css_init_cnr2_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_cnr2_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_dp_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_dp_state() enter:\n"); + + { + unsigned int size = binary->info->mem_offsets.offsets.state->vmem.dp.size; + + unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset; + + if (size) { + ia_css_init_dp_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_dp_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_de_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_de_state() enter:\n"); + + { + unsigned int size = binary->info->mem_offsets.offsets.state->vmem.de.size; + + unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.de.offset; + + if (size) { + ia_css_init_de_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_de_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_tnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_tnr_state() enter:\n"); + + { + unsigned int size = binary->info->mem_offsets.offsets.state->dmem.tnr.size; + + unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset; + + if (size) { + ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_tnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ref_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_ref_state() enter:\n"); + + { + unsigned int size = binary->info->mem_offsets.offsets.state->dmem.ref.size; + + unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset; + + if (size) { + ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_ref_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ynr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_ynr_state() enter:\n"); + + { + unsigned int size = binary->info->mem_offsets.offsets.state->vmem.ynr.size; + + unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset; + + if (size) { + ia_css_init_ynr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_initialize_ynr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +void (*ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])( + const struct ia_css_binary *binary) = { + ia_css_initialize_aa_state, + ia_css_initialize_cnr_state, + ia_css_initialize_cnr2_state, + ia_css_initialize_dp_state, + ia_css_initialize_de_state, + ia_css_initialize_tnr_state, + ia_css_initialize_ref_state, + ia_css_initialize_ynr_state, +}; diff --git a/drivers/staging/media/atomisp/pci/ia_css_isp_states.h b/drivers/staging/media/atomisp/pci/ia_css_isp_states.h new file mode 100644 index 000000000..9f6c342a1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_isp_states.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_STATES +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_STATE_H +#define _IA_CSS_ISP_STATE_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_state_ids { + IA_CSS_AA_STATE_ID, + IA_CSS_CNR_STATE_ID, + IA_CSS_CNR2_STATE_ID, + IA_CSS_DP_STATE_ID, + IA_CSS_DE_STATE_ID, + IA_CSS_TNR_STATE_ID, + IA_CSS_REF_STATE_ID, + IA_CSS_YNR_STATE_ID, + IA_CSS_NUM_STATE_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_state_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter cnr2; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ynr; + } vmem; + struct { + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_STATES) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +extern void (*ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])( + const struct ia_css_binary *binary); + +#endif /* IA_CSS_INCLUDE_STATE */ + +#endif /* _IA_CSS_ISP_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_metadata.h b/drivers/staging/media/atomisp/pci/ia_css_metadata.h new file mode 100644 index 000000000..9eb1b76a3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_metadata.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_METADATA_H +#define __IA_CSS_METADATA_H + +/* @file + * This file contains structure for processing sensor metadata. + */ + +#include +#include "ia_css_types.h" +#include "ia_css_stream_format.h" + +/* Metadata configuration. This data structure contains necessary info + * to process sensor metadata. + */ +struct ia_css_metadata_config { + enum atomisp_input_format data_type; /** Data type of CSI-2 embedded + data. The default value is ATOMISP_INPUT_FORMAT_EMBEDDED. For + certain sensors, user can choose non-default data type for embedded + data. */ + struct ia_css_resolution resolution; /** Resolution */ +}; + +struct ia_css_metadata_info { + struct ia_css_resolution resolution; /** Resolution */ + u32 stride; /** Stride in bytes */ + u32 size; /** Total size in bytes */ +}; + +struct ia_css_metadata { + struct ia_css_metadata_info info; /** Layout info */ + ia_css_ptr address; /** CSS virtual address */ + u32 exp_id; + /** Exposure ID, see ia_css_event_public.h for more detail */ +}; + +#define SIZE_OF_IA_CSS_METADATA_STRUCT sizeof(struct ia_css_metadata) + +/* @brief Allocate a metadata buffer. + * @param[in] metadata_info Metadata info struct, contains details on metadata buffers. + * @return Pointer of metadata buffer or NULL (if error) + * + * This function allocates a metadata buffer according to the properties + * specified in the metadata_info struct. + */ +struct ia_css_metadata * +ia_css_metadata_allocate(const struct ia_css_metadata_info *metadata_info); + +/* @brief Free a metadata buffer. + * + * @param[in] metadata Pointer of metadata buffer. + * @return None + * + * This function frees a metadata buffer. + */ +void +ia_css_metadata_free(struct ia_css_metadata *metadata); + +#endif /* __IA_CSS_METADATA_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_mipi.h b/drivers/staging/media/atomisp/pci/ia_css_mipi.h new file mode 100644 index 000000000..9e50e1c61 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_mipi.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MIPI_H +#define __IA_CSS_MIPI_H + +/* @file + * This file contains MIPI support functionality + */ + +#include +#include "ia_css_err.h" +#include "ia_css_stream_format.h" +#include "ia_css_input_port.h" + +/* @brief Register size of a CSS MIPI frame for check during capturing. + * + * @param[in] port CSI-2 port this check is registered. + * @param[in] size_mem_words The frame size in memory words (32B). + * @return Return the error in case of failure. E.g. MAX_NOF_ENTRIES REACHED + * + * Register size of a CSS MIPI frame to check during capturing. Up to + * IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES entries per port allowed. Entries are reset + * when stream is stopped. + * + * + */ +int +ia_css_mipi_frame_enable_check_on_size(const enum mipi_port_id port, + const unsigned int size_mem_words); + +/* @brief Calculate the size of a mipi frame. + * + * @param[in] width The width (in pixels) of the frame. + * @param[in] height The height (in lines) of the frame. + * @param[in] format The frame (MIPI) format. + * @param[in] hasSOLandEOL Whether frame (MIPI) contains (optional) SOL and EOF packets. + * @param[in] embedded_data_size_words Embedded data size in memory words. + * @param size_mem_words The mipi frame size in memory words (32B). + * @return The error code. + * + * Calculate the size of a mipi frame, based on the resolution and format. + */ +int +ia_css_mipi_frame_calculate_size(const unsigned int width, + const unsigned int height, + const enum atomisp_input_format format, + const bool hasSOLandEOL, + const unsigned int embedded_data_size_words, + unsigned int *size_mem_words); + +#endif /* __IA_CSS_MIPI_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_mmu.h b/drivers/staging/media/atomisp/pci/ia_css_mmu.h new file mode 100644 index 000000000..8f04d196c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_mmu.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MMU_H +#define __IA_CSS_MMU_H + +/* @file + * This file contains one support function for invalidating the CSS MMU cache + */ + +/* @brief Invalidate the MMU internal cache. + * @return None + * + * This function triggers an invalidation of the translate-look-aside + * buffer (TLB) that's inside the CSS MMU. This function should be called + * every time the page tables used by the MMU change. + */ +void +ia_css_mmu_invalidate_cache(void); + +#endif /* __IA_CSS_MMU_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_mmu_private.h b/drivers/staging/media/atomisp/pci/ia_css_mmu_private.h new file mode 100644 index 000000000..dc6542aa6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_mmu_private.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MMU_PRIVATE_H +#define __IA_CSS_MMU_PRIVATE_H + +#include "system_local.h" + +/* + * This function sets the L1 pagetable address. + * After power-up of the ISP the L1 pagetable can be set. + * Once being set the L1 pagetable is protected against + * further modifications. + */ +void +sh_css_mmu_set_page_table_base_index(hrt_data base_index); + +#endif /* __IA_CSS_MMU_PRIVATE_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_morph.h b/drivers/staging/media/atomisp/pci/ia_css_morph.h new file mode 100644 index 000000000..9c4b41b94 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_morph.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MORPH_H +#define __IA_CSS_MORPH_H + +/* @file + * This file contains supporting for morphing table + */ + +#include + +/* @brief Morphing table + * @param[in] width Width of the morphing table. + * @param[in] height Height of the morphing table. + * @return Pointer to the morphing table +*/ +struct ia_css_morph_table * +ia_css_morph_table_allocate(unsigned int width, unsigned int height); + +/* @brief Free the morph table + * @param[in] me Pointer to the morph table. + * @return None +*/ +void +ia_css_morph_table_free(struct ia_css_morph_table *me); + +#endif /* __IA_CSS_MORPH_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_pipe.h b/drivers/staging/media/atomisp/pci/ia_css_pipe.h new file mode 100644 index 000000000..22522968b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_pipe.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_H__ +#define __IA_CSS_PIPE_H__ + +#include +#include "ia_css_stream.h" +#include "ia_css_frame.h" +#include "ia_css_pipeline.h" +#include "ia_css_binary.h" +#include "sh_css_legacy.h" + +#define PIPE_ENTRY_EMPTY_TOKEN (~0U) +#define PIPE_ENTRY_RESERVED_TOKEN (0x1) + +struct ia_css_preview_settings { + struct ia_css_binary copy_binary; + struct ia_css_binary preview_binary; + struct ia_css_binary vf_pp_binary; + + /* 2401 only for these two - do we in fact use them for anything real */ + struct ia_css_frame *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; + struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; + + struct ia_css_pipe *copy_pipe; + struct ia_css_pipe *capture_pipe; +}; + +#define IA_CSS_DEFAULT_PREVIEW_SETTINGS { \ + .copy_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .preview_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .vf_pp_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ +} + +struct ia_css_capture_settings { + struct ia_css_binary copy_binary; + /* we extend primary binary to multiple stages because in ISP2.6.1 + * the computation load is too high to fit in one single binary. */ + struct ia_css_binary primary_binary[MAX_NUM_PRIMARY_STAGES]; + unsigned int num_primary_stage; + struct ia_css_binary pre_isp_binary; + struct ia_css_binary anr_gdc_binary; + struct ia_css_binary post_isp_binary; + struct ia_css_binary capture_pp_binary; + struct ia_css_binary vf_pp_binary; + struct ia_css_binary capture_ldc_binary; + struct ia_css_binary *yuv_scaler_binary; + struct ia_css_frame *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; + bool *is_output_stage; + unsigned int num_yuv_scaler; +}; + +#define IA_CSS_DEFAULT_CAPTURE_SETTINGS { \ + .copy_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .primary_binary = {IA_CSS_BINARY_DEFAULT_SETTINGS}, \ + .pre_isp_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .anr_gdc_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .post_isp_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .capture_pp_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .vf_pp_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .capture_ldc_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ +} + +struct ia_css_video_settings { + struct ia_css_binary copy_binary; + struct ia_css_binary video_binary; + struct ia_css_binary vf_pp_binary; + struct ia_css_binary *yuv_scaler_binary; + struct ia_css_frame *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; + struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; + struct ia_css_frame *vf_pp_in_frame; + struct ia_css_pipe *copy_pipe; + struct ia_css_pipe *capture_pipe; + bool *is_output_stage; + unsigned int num_yuv_scaler; +}; + +#define IA_CSS_DEFAULT_VIDEO_SETTINGS { \ + .copy_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .video_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ + .vf_pp_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ +} + +struct ia_css_yuvpp_settings { + struct ia_css_binary copy_binary; + struct ia_css_binary *yuv_scaler_binary; + struct ia_css_binary *vf_pp_binary; + bool *is_output_stage; + unsigned int num_yuv_scaler; + unsigned int num_vf_pp; + unsigned int num_output; +}; + +#define IA_CSS_DEFAULT_YUVPP_SETTINGS { \ + .copy_binary = IA_CSS_BINARY_DEFAULT_SETTINGS, \ +} + +struct osys_object; + +struct ia_css_pipe { + /* TODO: Remove stop_requested and use stop_requested in the pipeline */ + bool stop_requested; + struct ia_css_pipe_config config; + struct ia_css_pipe_extra_config extra_config; + struct ia_css_pipe_info info; + enum ia_css_pipe_id mode; + struct ia_css_shading_table *shading_table; + struct ia_css_pipeline pipeline; + struct ia_css_frame_info output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame_info bds_output_info; + struct ia_css_frame_info vf_output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame_info out_yuv_ds_input_info; + struct ia_css_frame_info vf_yuv_ds_input_info; + struct ia_css_fw_info *output_stage; /* extra output stage */ + struct ia_css_fw_info *vf_stage; /* extra vf_stage */ + unsigned int required_bds_factor; + unsigned int dvs_frame_delay; + int num_invalid_frames; + bool enable_viewfinder[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_stream *stream; + struct ia_css_frame in_frame_struct; + struct ia_css_frame out_frame_struct; + struct ia_css_frame vf_frame_struct; + struct ia_css_frame *continuous_frames[NUM_CONTINUOUS_FRAMES]; + struct ia_css_metadata *cont_md_buffers[NUM_CONTINUOUS_FRAMES]; + union { + struct ia_css_preview_settings preview; + struct ia_css_video_settings video; + struct ia_css_capture_settings capture; + struct ia_css_yuvpp_settings yuvpp; + } pipe_settings; + ia_css_ptr scaler_pp_lut; + struct osys_object *osys_obj; + + /* This number is unique per pipe each instance of css. This number is + * reused as pipeline number also. There is a 1-1 mapping between pipe_num + * and sp thread id. Current logic limits pipe_num to + * SH_CSS_MAX_SP_THREADS */ + unsigned int pipe_num; +}; + +#define IA_CSS_DEFAULT_PIPE { \ + .config = DEFAULT_PIPE_CONFIG, \ + .info = DEFAULT_PIPE_INFO, \ + .mode = IA_CSS_PIPE_ID_VIDEO, /* (pipe_id) */ \ + .pipeline = DEFAULT_PIPELINE, \ + .output_info = {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + .bds_output_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + .vf_output_info = {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + .out_yuv_ds_input_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + .vf_yuv_ds_input_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + .required_bds_factor = SH_CSS_BDS_FACTOR_1_00, \ + .dvs_frame_delay = 1, \ + .enable_viewfinder = {true}, \ + .in_frame_struct = DEFAULT_FRAME, \ + .out_frame_struct = DEFAULT_FRAME, \ + .vf_frame_struct = DEFAULT_FRAME, \ + .pipe_settings = { \ + .preview = IA_CSS_DEFAULT_PREVIEW_SETTINGS \ + }, \ + .pipe_num = PIPE_ENTRY_EMPTY_TOKEN, \ +} + +void ia_css_pipe_map_queue(struct ia_css_pipe *pipe, bool map); + +int +sh_css_param_update_isp_params(struct ia_css_pipe *curr_pipe, + struct ia_css_isp_parameters *params, + bool commit, struct ia_css_pipe *pipe); + +#endif /* __IA_CSS_PIPE_H__ */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_pipe_public.h b/drivers/staging/media/atomisp/pci/ia_css_pipe_public.h new file mode 100644 index 000000000..8ac1586dc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_pipe_public.h @@ -0,0 +1,473 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_PUBLIC_H +#define __IA_CSS_PIPE_PUBLIC_H + +/* @file + * This file contains the public interface for CSS pipes. + */ + +#include +#include +#include +#include +#include +/* ISP2401 */ +#include + +enum { + IA_CSS_PIPE_OUTPUT_STAGE_0 = 0, + IA_CSS_PIPE_OUTPUT_STAGE_1, + IA_CSS_PIPE_MAX_OUTPUT_STAGE, +}; + +/* Enumeration of pipe modes. This mode can be used to create + * an image pipe for this mode. These pipes can be combined + * to configure and run streams on the ISP. + * + * For example, one can create a preview and capture pipe to + * create a continuous capture stream. + */ +enum ia_css_pipe_mode { + IA_CSS_PIPE_MODE_PREVIEW, /** Preview pipe */ + IA_CSS_PIPE_MODE_VIDEO, /** Video pipe */ + IA_CSS_PIPE_MODE_CAPTURE, /** Still capture pipe */ + IA_CSS_PIPE_MODE_COPY, /** Copy pipe, only used for embedded/image data copying */ + IA_CSS_PIPE_MODE_YUVPP, /** YUV post processing pipe, used for all use cases with YUV input, + for SoC sensor and external ISP */ +}; + +/* Temporary define */ +#define IA_CSS_PIPE_MODE_NUM (IA_CSS_PIPE_MODE_YUVPP + 1) + +/** + * Enumeration of pipe versions. + * the order should match with definition in sh_css_defs.h + */ +enum ia_css_pipe_version { + IA_CSS_PIPE_VERSION_1 = 1, /** ISP1.0 pipe */ + IA_CSS_PIPE_VERSION_2_2 = 2, /** ISP2.2 pipe */ + IA_CSS_PIPE_VERSION_2_6_1 = 3, /** ISP2.6.1 pipe */ + IA_CSS_PIPE_VERSION_2_7 = 4 /** ISP2.7 pipe */ +}; + +/** + * Pipe configuration structure. + * Resolution properties are filled by Driver, kernel configurations are + * set by AIC + */ +struct ia_css_pipe_config { + enum ia_css_pipe_mode mode; + /** mode, indicates which mode the pipe should use. */ + enum ia_css_pipe_version isp_pipe_version; + /** pipe version, indicates which imaging pipeline the pipe should use. */ + struct ia_css_resolution input_effective_res; + /** input effective resolution */ + struct ia_css_resolution bayer_ds_out_res; + /** bayer down scaling */ + struct ia_css_resolution capt_pp_in_res; + /** capture post processing input resolution */ + struct ia_css_resolution vf_pp_in_res; + + /** ISP2401: view finder post processing input resolution */ + struct ia_css_resolution output_system_in_res; + /** For IPU3 only: use output_system_in_res to specify what input resolution + will OSYS receive, this resolution is equal to the output resolution of GDC + if not determined CSS will set output_system_in_res with main osys output pin resolution + All other IPUs may ignore this property */ + struct ia_css_resolution dvs_crop_out_res; + /** dvs crop, video only, not in use yet. Use dvs_envelope below. */ + struct ia_css_frame_info output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + /** output of YUV scaling */ + struct ia_css_frame_info vf_output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + /** output of VF YUV scaling */ + struct ia_css_capture_config default_capture_config; + /** Default capture config for initial capture pipe configuration. */ + struct ia_css_resolution dvs_envelope; /** temporary */ + enum ia_css_frame_delay dvs_frame_delay; + /** indicates the DVS loop delay in frame periods */ + bool enable_dz; + /** Disabling digital zoom for a pipeline, if this is set to false, + then setting a zoom factor will have no effect. + In some use cases this provides better performance. */ + bool enable_dpc; + /** Disabling "Defect Pixel Correction" for a pipeline, if this is set + to false. In some use cases this provides better performance. */ + bool enable_vfpp_bci; + /** Enabling BCI mode will cause yuv_scale binary to be picked up + instead of vf_pp. This only applies to viewfinder post + processing stages. */ + +/* ISP2401 */ + bool enable_tnr; + /** Enabling of TNR (temporal noise reduction). This is only applicable to video + pipes. Non video-pipes should always set this parameter to false. */ + + struct ia_css_isp_config *p_isp_config; + /** Pointer to ISP configuration */ + struct ia_css_resolution gdc_in_buffer_res; + /** GDC in buffer resolution. */ + struct ia_css_point gdc_in_buffer_offset; + /** GDC in buffer offset - indicates the pixel coordinates of the first valid pixel inside the buffer */ + +/* ISP2401 */ + struct ia_css_coordinate internal_frame_origin_bqs_on_sctbl; + /** Origin of internal frame positioned on shading table at shading correction in ISP. + NOTE: Shading table is larger than or equal to internal frame. + Shading table has shading gains and internal frame has bayer data. + The origin of internal frame is used in shading correction in ISP + to retrieve shading gains which correspond to bayer data. */ +}; + +/** + * Default settings for newly created pipe configurations. + */ +#define DEFAULT_PIPE_CONFIG { \ + .mode = IA_CSS_PIPE_MODE_PREVIEW, \ + .isp_pipe_version = 1, \ + .output_info = {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + .vf_output_info = {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + .default_capture_config = DEFAULT_CAPTURE_CONFIG, \ + .dvs_frame_delay = IA_CSS_FRAME_DELAY_1, \ +} + +/* Pipe info, this struct describes properties of a pipe after it's stream has + * been created. + * ~~~** DO NOT ADD NEW FIELD **~~~ This structure will be deprecated. + * - On the Behalf of CSS-API Committee. + */ +struct ia_css_pipe_info { + struct ia_css_frame_info output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + /** Info about output resolution. This contains the stride which + should be used for memory allocation. */ + struct ia_css_frame_info vf_output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + /** Info about viewfinder output resolution (optional). This contains + the stride that should be used for memory allocation. */ + struct ia_css_frame_info raw_output_info; + /** Raw output resolution. This indicates the resolution of the + RAW bayer output for pipes that support this. Currently, only the + still capture pipes support this feature. When this resolution is + smaller than the input resolution, cropping will be performed by + the ISP. The first cropping that will be performed is on the upper + left corner where we crop 8 lines and 8 columns to remove the + pixels normally used to initialize the ISP filters. + This is why the raw output resolution should normally be set to + the input resolution - 8x8. */ + /* ISP2401 */ + struct ia_css_resolution output_system_in_res_info; + /** For IPU3 only. Info about output system in resolution which is considered + as gdc out resolution. */ + struct ia_css_shading_info shading_info; + /** After an image pipe is created, this field will contain the info + for the shading correction. */ + struct ia_css_grid_info grid_info; + /** After an image pipe is created, this field will contain the grid + info for 3A and DVS. */ + int num_invalid_frames; + /** The very first frames in a started stream do not contain valid data. + In this field, the CSS-firmware communicates to the host-driver how + many initial frames will contain invalid data; this allows the + host-driver to discard those initial invalid frames and start it's + output at the first valid frame. */ +}; + +/** + * Defaults for ia_css_pipe_info structs. + */ +#define DEFAULT_PIPE_INFO {\ + .output_info = {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + .vf_output_info = {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + .raw_output_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + .shading_info = DEFAULT_SHADING_INFO, \ + .grid_info = DEFAULT_GRID_INFO, \ +} + +/* @brief Load default pipe configuration + * @param[out] pipe_config The pipe configuration. + * @return None + * + * This function will load the default pipe configuration: +@code + struct ia_css_pipe_config def_config = { + IA_CSS_PIPE_MODE_PREVIEW, // mode + 1, // isp_pipe_version + {0, 0}, // bayer_ds_out_res + {0, 0}, // capt_pp_in_res + {0, 0}, // vf_pp_in_res + {0, 0}, // dvs_crop_out_res + {{0, 0}, 0, 0, 0, 0}, // output_info + {{0, 0}, 0, 0, 0, 0}, // second_output_info + {{0, 0}, 0, 0, 0, 0}, // vf_output_info + {{0, 0}, 0, 0, 0, 0}, // second_vf_output_info + { + IA_CSS_CAPTURE_MODE_RAW, // mode + false, // enable_xnr + false // enable_raw_output + }, // default_capture_config + {0, 0}, // dvs_envelope + 1, // dvs_frame_delay + true, // enable_dz + NULL, // p_isp_config + }; +@endcode + */ +void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config); + +/* @brief Create a pipe + * @param[in] config The pipe configuration. + * @param[out] pipe The pipe. + * @return 0 or the error code. + * + * This function will create a pipe with the given + * configuration. + */ +int +ia_css_pipe_create(const struct ia_css_pipe_config *config, + struct ia_css_pipe **pipe); + +/* @brief Destroy a pipe + * @param[in] pipe The pipe. + * @return 0 or the error code. + * + * This function will destroy a given pipe. + */ +int +ia_css_pipe_destroy(struct ia_css_pipe *pipe); + +/* @brief Provides information about a pipe + * @param[in] pipe The pipe. + * @param[out] pipe_info The pipe information. + * @return 0 or -EINVAL. + * + * This function will provide information about a given pipe. + */ +int +ia_css_pipe_get_info(const struct ia_css_pipe *pipe, + struct ia_css_pipe_info *pipe_info); + +/* @brief Configure a pipe with filter coefficients. + * @param[in] pipe The pipe. + * @param[in] config The pointer to ISP configuration. + * @return 0 or error code upon error. + * + * This function configures the filter coefficients for an image + * pipe. + */ +int +ia_css_pipe_set_isp_config(struct ia_css_pipe *pipe, + struct ia_css_isp_config *config); + +/* @brief Controls when the Event generator raises an IRQ to the Host. + * + * @param[in] pipe The pipe. + * @param[in] or_mask Binary or of enum ia_css_event_irq_mask_type. Each pipe + related event that is part of this mask will directly + raise an IRQ to the Host when the event occurs in the + CSS. + * @param[in] and_mask Binary or of enum ia_css_event_irq_mask_type. An event + IRQ for the Host is only raised after all pipe related + events have occurred at least once for all the active + pipes. Events are remembered and don't need to occurred + at the same moment in time. There is no control over + the order of these events. Once an IRQ has been raised + all remembered events are reset. + * @return 0. + * + Controls when the Event generator in the CSS raises an IRQ to the Host. + The main purpose of this function is to reduce the amount of interrupts + between the CSS and the Host. This will help saving power as it wakes up the + Host less often. In case both or_mask and and_mask are + IA_CSS_EVENT_TYPE_NONE for all pipes, no event IRQ's will be raised. An + exception holds for IA_CSS_EVENT_TYPE_PORT_EOF, for this event an IRQ is always + raised. + Note that events are still queued and the Host can poll for them. The + or_mask and and_mask may be active at the same time\n + \n + Default values, for all pipe id's, after ia_css_init:\n + or_mask = IA_CSS_EVENT_TYPE_ALL\n + and_mask = IA_CSS_EVENT_TYPE_NONE\n + \n + Examples\n + \code + ia_css_pipe_set_irq_mask(h_pipe, + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE | + IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE , + IA_CSS_EVENT_TYPE_NONE); + \endcode + The event generator will only raise an interrupt to the Host when there are + 3A or DIS statistics available from the preview pipe. It will not generate + an interrupt for any other event of the preview pipe e.g when there is an + output frame available. + + \code + ia_css_pipe_set_irq_mask(h_pipe_preview, + IA_CSS_EVENT_TYPE_NONE, + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE | + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE ); + + ia_css_pipe_set_irq_mask(h_pipe_capture, + IA_CSS_EVENT_TYPE_NONE, + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE ); + \endcode + The event generator will only raise an interrupt to the Host when there is + both a frame done and 3A event available from the preview pipe AND when there + is a frame done available from the capture pipe. Note that these events + may occur at different moments in time. Also the order of the events is not + relevant. + + \code + ia_css_pipe_set_irq_mask(h_pipe_preview, + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE, + IA_CSS_EVENT_TYPE_ALL ); + + ia_css_pipe_set_irq_mask(h_pipe_capture, + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE, + IA_CSS_EVENT_TYPE_ALL ); + \endcode + The event generator will only raise an interrupt to the Host when there is an + output frame from the preview pipe OR an output frame from the capture pipe. + All other events (3A, VF output, pipeline done) will not raise an interrupt + to the Host. These events are not lost but always stored in the event queue. + */ +int +ia_css_pipe_set_irq_mask(struct ia_css_pipe *pipe, + unsigned int or_mask, + unsigned int and_mask); + +/* @brief Reads the current event IRQ mask from the CSS. + * + * @param[in] pipe The pipe. + * @param[out] or_mask Current or_mask. The bits in this mask are a binary or + of enum ia_css_event_irq_mask_type. Pointer may be NULL. + * @param[out] and_mask Current and_mask.The bits in this mask are a binary or + of enum ia_css_event_irq_mask_type. Pointer may be NULL. + * @return 0. + * + Reads the current event IRQ mask from the CSS. Reading returns the actual + values as used by the SP and not any mirrored values stored at the Host.\n +\n +Precondition:\n +SP must be running.\n + +*/ +int +ia_css_event_get_irq_mask(const struct ia_css_pipe *pipe, + unsigned int *or_mask, + unsigned int *and_mask); + +/* @brief Queue a buffer for an image pipe. + * + * @param[in] pipe The pipe that will own the buffer. + * @param[in] buffer Pointer to the buffer. + * Note that the caller remains owner of the buffer + * structure. Only the data pointer within it will + * be passed into the internal queues. + * @return IA_CSS_INTERNAL_ERROR in case of unexpected errors, + * 0 otherwise. + * + * This function adds a buffer (which has a certain buffer type) to the queue + * for this type. This queue is owned by the image pipe. After this function + * completes successfully, the buffer is now owned by the image pipe and should + * no longer be accessed by any other code until it gets dequeued. The image + * pipe will dequeue buffers from this queue, use them and return them to the + * host code via an interrupt. Buffers will be consumed in the same order they + * get queued, but may be returned to the host out of order. + */ +int +ia_css_pipe_enqueue_buffer(struct ia_css_pipe *pipe, + const struct ia_css_buffer *buffer); + +/* @brief Dequeue a buffer from an image pipe. + * + * @param[in] pipe The pipeline that the buffer queue belongs to. + * @param[in,out] buffer The buffer is used to lookup the type which determines + * which internal queue to use. + * The resulting buffer pointer is written into the dta + * field. + * @return IA_CSS_ERR_NO_BUFFER if the queue is empty or + * 0 otherwise. + * + * This function dequeues a buffer from a buffer queue. The queue is indicated + * by the buffer type argument. This function can be called after an interrupt + * has been generated that signalled that a new buffer was available and can + * be used in a polling-like situation where the NO_BUFFER return value is used + * to determine whether a buffer was available or not. + */ +int +ia_css_pipe_dequeue_buffer(struct ia_css_pipe *pipe, + struct ia_css_buffer *buffer); + +/* @brief Get selected configuration settings + * @param[in] pipe The pipe. + * @param[out] config Configuration settings. + * @return None + */ +void +ia_css_pipe_get_isp_config(struct ia_css_pipe *pipe, + struct ia_css_isp_config *config); + +/* @brief Set the scaler lut on this pipe. A copy of lut is made in the inuit + * address space. So the LUT can be freed by caller. + * @param[in] pipe Pipe handle. + * @param[in] lut Look up tabel + * + * @return + * 0 : Success + * -EINVAL : Invalid Parameters + * + * Note: + * 1) Note that both GDC's are programmed with the same table. + * 2) Current implementation ignores the pipe and overrides the + * global lut. This will be fixed in the future + * 3) This function must be called before stream start + * + */ +int +ia_css_pipe_set_bci_scaler_lut(struct ia_css_pipe *pipe, + const void *lut); +/* @brief Checking of DVS statistics ability + * @param[in] pipe_info The pipe info. + * @return true - has DVS statistics ability + * false - otherwise + */ +bool ia_css_pipe_has_dvs_stats(struct ia_css_pipe_info *pipe_info); + +/* ISP2401 */ +/* @brief Override the frameformat set on the output pins. + * @param[in] pipe Pipe handle. + * @param[in] output_pin Pin index to set the format on + * 0 - main output pin + * 1 - display output pin + * @param[in] format Format to set + * + * @return + * 0 : Success + * -EINVAL : Invalid Parameters + * -EINVAL : Pipe misses binary info + * + * Note: + * 1) This is an optional function to override the formats set in the pipe. + * 2) Only overriding with IA_CSS_FRAME_FORMAT_NV12_TILEY is currently allowed. + * 3) This function is only to be used on pipes that use the output system. + * 4) If this function is used, it MUST be called after ia_css_pipe_create. + * 5) If this function is used, this function MUST be called before ia_css_stream_start. + */ +int +ia_css_pipe_override_frame_format(struct ia_css_pipe *pipe, + int output_pin, + enum ia_css_frame_format format); + +#endif /* __IA_CSS_PIPE_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_prbs.h b/drivers/staging/media/atomisp/pci/ia_css_prbs.h new file mode 100644 index 000000000..53bbf1dce --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_prbs.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PRBS_H +#define __IA_CSS_PRBS_H + +/* @file + * This file contains support for Pseudo Random Bit Sequence (PRBS) inputs + */ + +/* Enumerate the PRBS IDs. + */ +enum ia_css_prbs_id { + IA_CSS_PRBS_ID0, + IA_CSS_PRBS_ID1, + IA_CSS_PRBS_ID2 +}; + +/** + * Maximum number of PRBS IDs. + * + * Make sure the value of this define gets changed to reflect the correct + * number of ia_css_prbs_id enum if you add/delete an item in the enum. + */ +#define N_CSS_PRBS_IDS (IA_CSS_PRBS_ID2 + 1) + +/** + * PRBS configuration structure. + * + * Seed the for the Pseudo Random Bit Sequence. + * + * @deprecated{This interface is deprecated, it is not portable -> move to input system API} + */ +struct ia_css_prbs_config { + enum ia_css_prbs_id id; + unsigned int h_blank; /** horizontal blank */ + unsigned int v_blank; /** vertical blank */ + int seed; /** random seed for the 1st 2-pixel-components/clock */ + int seed1; /** random seed for the 2nd 2-pixel-components/clock */ +}; + +#endif /* __IA_CSS_PRBS_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_properties.h b/drivers/staging/media/atomisp/pci/ia_css_properties.h new file mode 100644 index 000000000..2cd014f7a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_properties.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PROPERTIES_H +#define __IA_CSS_PROPERTIES_H + +/* @file + * This file contains support for retrieving properties of some hardware the CSS system + */ + +#include /* bool */ +#include /* ia_css_vamem_type */ + +struct ia_css_properties { + int gdc_coord_one; + bool l1_base_is_index; /** Indicate whether the L1 page base + is a page index or a byte address. */ + enum ia_css_vamem_type vamem_type; +}; + +/* @brief Get hardware properties + * @param[in,out] properties The hardware properties + * @return None + * + * This function returns a number of hardware properties. + */ +void +ia_css_get_properties(struct ia_css_properties *properties); + +#endif /* __IA_CSS_PROPERTIES_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_shading.h b/drivers/staging/media/atomisp/pci/ia_css_shading.h new file mode 100644 index 000000000..de7ae5cab --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_shading.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SHADING_H +#define __IA_CSS_SHADING_H + +/* @file + * This file contains support for setting the shading table for CSS + */ + +#include + +/* @brief Shading table + * @param[in] width Width of the shading table. + * @param[in] height Height of the shading table. + * @return Pointer to the shading table +*/ +struct ia_css_shading_table * +ia_css_shading_table_alloc(unsigned int width, + unsigned int height); + +/* @brief Free shading table + * @param[in] table Pointer to the shading table. + * @return None +*/ +void +ia_css_shading_table_free(struct ia_css_shading_table *table); + +#endif /* __IA_CSS_SHADING_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_stream.h b/drivers/staging/media/atomisp/pci/ia_css_stream.h new file mode 100644 index 000000000..cf847586d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_stream.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_STREAM_H_ +#define _IA_CSS_STREAM_H_ + +#include +#include +#include +#include "ia_css_types.h" +#include "ia_css_stream_public.h" + +/** + * structure to hold all internal stream related information + */ +struct ia_css_stream { + struct ia_css_stream_config config; + struct ia_css_stream_info info; + rx_cfg_t csi_rx_config; + bool reconfigure_css_rx; + struct ia_css_pipe *last_pipe; + int num_pipes; + struct ia_css_pipe **pipes; + struct ia_css_pipe *continuous_pipe; + struct ia_css_isp_parameters *isp_params_configs; + struct ia_css_isp_parameters *per_frame_isp_params_configs; + + bool cont_capt; + bool disable_cont_vf; + + /* ISP2401 */ + bool stop_copy_preview; + bool started; +}; + +/* @brief Get a binary in the stream, which binary has the shading correction. + * + * @param[in] stream: The stream. + * @return The binary which has the shading correction. + * + */ +struct ia_css_binary * +ia_css_stream_get_shading_correction_binary(const struct ia_css_stream *stream); + +struct ia_css_binary * +ia_css_stream_get_dvs_binary(const struct ia_css_stream *stream); + +struct ia_css_binary * +ia_css_stream_get_3a_binary(const struct ia_css_stream *stream); + +unsigned int +ia_css_stream_input_format_bits_per_pixel(struct ia_css_stream *stream); + +bool +sh_css_params_set_binning_factor(struct ia_css_stream *stream, + unsigned int sensor_binning); + +void +sh_css_invalidate_params(struct ia_css_stream *stream); + +/* The following functions are used for testing purposes only */ +const struct ia_css_fpn_table * +ia_css_get_fpn_table(struct ia_css_stream *stream); + +/* @brief Get a pointer to the shading table. + * + * @param[in] stream: The stream. + * @return The pointer to the shading table. + * + */ +struct ia_css_shading_table * +ia_css_get_shading_table(struct ia_css_stream *stream); + +void +ia_css_get_isp_dis_coefficients(struct ia_css_stream *stream, + short *horizontal_coefficients, + short *vertical_coefficients); + +void +ia_css_get_isp_dvs2_coefficients(struct ia_css_stream *stream, + short *hor_coefs_odd_real, + short *hor_coefs_odd_imag, + short *hor_coefs_even_real, + short *hor_coefs_even_imag, + short *ver_coefs_odd_real, + short *ver_coefs_odd_imag, + short *ver_coefs_even_real, + short *ver_coefs_even_imag); + +int +ia_css_stream_isp_parameters_init(struct ia_css_stream *stream); + +void +ia_css_stream_isp_parameters_uninit(struct ia_css_stream *stream); + +#endif /*_IA_CSS_STREAM_H_*/ diff --git a/drivers/staging/media/atomisp/pci/ia_css_stream_format.h b/drivers/staging/media/atomisp/pci/ia_css_stream_format.h new file mode 100644 index 000000000..aac22d858 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_stream_format.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_STREAM_FORMAT_H +#define __IA_CSS_STREAM_FORMAT_H + +/* @file + * This file contains formats usable for ISP streaming input + */ + +#include /* bool */ +#include "../../../include/linux/atomisp_platform.h" + +unsigned int ia_css_util_input_format_bpp( + enum atomisp_input_format format, + bool two_ppc); + +#endif /* __ATOMISP_INPUT_FORMAT_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_stream_public.h b/drivers/staging/media/atomisp/pci/ia_css_stream_public.h new file mode 100644 index 000000000..47846ece8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_stream_public.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_STREAM_PUBLIC_H +#define __IA_CSS_STREAM_PUBLIC_H + +/* @file + * This file contains support for configuring and controlling streams + */ + +#include +#include "ia_css_types.h" +#include "ia_css_pipe_public.h" +#include "ia_css_metadata.h" +#include "ia_css_tpg.h" +#include "ia_css_prbs.h" +#include "ia_css_input_port.h" + +/* Input modes, these enumerate all supported input modes. + * Note that not all ISP modes support all input modes. + */ +enum ia_css_input_mode { + IA_CSS_INPUT_MODE_SENSOR, /** data from sensor */ + IA_CSS_INPUT_MODE_FIFO, /** data from input-fifo */ + IA_CSS_INPUT_MODE_TPG, /** data from test-pattern generator */ + IA_CSS_INPUT_MODE_PRBS, /** data from pseudo-random bit stream */ + IA_CSS_INPUT_MODE_MEMORY, /** data from a frame in memory */ + IA_CSS_INPUT_MODE_BUFFERED_SENSOR /** data is sent through mipi buffer */ +}; + +/* Structure of the MIPI buffer configuration + */ +struct ia_css_mipi_buffer_config { + unsigned int size_mem_words; /** The frame size in the system memory + words (32B) */ + bool contiguous; /** Allocated memory physically + contiguously or not. \deprecated{Will be false always.}*/ + unsigned int nof_mipi_buffers; /** The number of MIPI buffers required for this + stream */ +}; + +enum { + IA_CSS_STREAM_ISYS_STREAM_0 = 0, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX = IA_CSS_STREAM_ISYS_STREAM_0, + IA_CSS_STREAM_ISYS_STREAM_1, + IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH +}; + +/* This is input data configuration for one MIPI data type. We can have + * multiple of this in one virtual channel. + */ +struct ia_css_stream_isys_stream_config { + struct ia_css_resolution input_res; /** Resolution of input data */ + enum atomisp_input_format format; /** Format of input stream. This data + format will be mapped to MIPI data + type internally. */ + int linked_isys_stream_id; /** default value is -1, other value means + current isys_stream shares the same buffer with + indicated isys_stream*/ + bool valid; /** indicate whether other fields have valid value */ +}; + +struct ia_css_stream_input_config { + struct ia_css_resolution input_res; /** Resolution of input data */ + struct ia_css_resolution effective_res; /** Resolution of input data. + Used for CSS 2400/1 System and deprecated for other + systems (replaced by input_effective_res in + ia_css_pipe_config) */ + enum atomisp_input_format format; /** Format of input stream. This data + format will be mapped to MIPI data + type internally. */ + enum ia_css_bayer_order bayer_order; /** Bayer order for RAW streams */ +}; + +/* Input stream description. This describes how input will flow into the + * CSS. This is used to program the CSS hardware. + */ +struct ia_css_stream_config { + enum ia_css_input_mode mode; /** Input mode */ + union { + struct ia_css_input_port port; /** Port, for sensor only. */ + struct ia_css_tpg_config tpg; /** TPG configuration */ + struct ia_css_prbs_config prbs; /** PRBS configuration */ + } source; /** Source of input data */ + unsigned int channel_id; /** Channel on which input data + will arrive. Use this field + to specify virtual channel id. + Valid values are: 0, 1, 2, 3 */ + struct ia_css_stream_isys_stream_config + isys_config[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; + struct ia_css_stream_input_config input_config; + + /* + * Currently, Linux and Windows platforms interpret the binning_factor + * parameter differently. In Linux, the binning factor is expressed + * in the form 2^N * 2^N + */ + /* ISP2401 */ + unsigned int sensor_binning_factor; /** Binning factor used by sensor + to produce image data. This is + used for shading correction. */ + unsigned int pixels_per_clock; /** Number of pixels per clock, which can be + 1, 2 or 4. */ + bool online; /** offline will activate RAW copy on SP, use this for + continuous capture. */ + /* ISYS2401 usage: ISP receives data directly from sensor, no copy. */ + unsigned int init_num_cont_raw_buf; /** initial number of raw buffers to + allocate */ + unsigned int target_num_cont_raw_buf; /** total number of raw buffers to + allocate */ + bool pack_raw_pixels; /** Pack pixels in the raw buffers */ + bool continuous; /** Use SP copy feature to continuously capture frames + to system memory and run pipes in offline mode */ + bool disable_cont_viewfinder; /** disable continuous viewfinder for ZSL use case */ + s32 flash_gpio_pin; /** pin on which the flash is connected, -1 for no flash */ + int left_padding; /** The number of input-formatter left-paddings, -1 for default from binary.*/ + struct ia_css_mipi_buffer_config + mipi_buffer_config; /** mipi buffer configuration */ + struct ia_css_metadata_config + metadata_config; /** Metadata configuration. */ + bool ia_css_enable_raw_buffer_locking; /** Enable Raw Buffer Locking for HALv3 Support */ + bool lock_all; + /** Lock all RAW buffers (true) or lock only buffers processed by + video or preview pipe (false). + This setting needs to be enabled to allow raw buffer locking + without continuous viewfinder. */ +}; + +struct ia_css_stream; + +/* Stream info, this struct describes properties of a stream after it has been + * created. + */ +struct ia_css_stream_info { + struct ia_css_metadata_info metadata_info; + /** Info about the metadata layout, this contains the stride. */ +}; + +/* @brief Load default stream configuration + * @param[in,out] stream_config The stream configuration. + * @return None + * + * This function will reset the stream configuration to the default state: +@code + memset(stream_config, 0, sizeof(*stream_config)); + stream_config->online = true; + stream_config->left_padding = -1; +@endcode + */ +void ia_css_stream_config_defaults(struct ia_css_stream_config *stream_config); + +/* + * create the internal structures and fill in the configuration data and pipes + */ + +/* @brief Creates a stream +* @param[in] stream_config The stream configuration. +* @param[in] num_pipes The number of pipes to incorporate in the stream. +* @param[in] pipes The pipes. +* @param[out] stream The stream. +* @return 0 or the error code. +* +* This function will create a stream with a given configuration and given pipes. +*/ +int +ia_css_stream_create(const struct ia_css_stream_config *stream_config, + int num_pipes, + struct ia_css_pipe *pipes[], + struct ia_css_stream **stream); + +/* @brief Destroys a stream + * @param[in] stream The stream. + * @return 0 or the error code. + * + * This function will destroy a given stream. + */ +int +ia_css_stream_destroy(struct ia_css_stream *stream); + +/* @brief Provides information about a stream + * @param[in] stream The stream. + * @param[out] stream_info The information about the stream. + * @return 0 or the error code. + * + * This function will destroy a given stream. + */ +int +ia_css_stream_get_info(const struct ia_css_stream *stream, + struct ia_css_stream_info *stream_info); + + +/* @brief Starts the stream. + * @param[in] stream The stream. + * @return 0 or the error code. + * + * The dynamic data in + * the buffers are not used and need to be queued with a separate call + * to ia_css_pipe_enqueue_buffer. + * NOTE: this function will only send start event to corresponding + * thread and will not start SP any more. + */ +int +ia_css_stream_start(struct ia_css_stream *stream); + +/* @brief Stop the stream. + * @param[in] stream The stream. + * @return 0 or the error code. + * + * NOTE: this function will send stop event to pipes belong to this + * stream but will not terminate threads. + */ +int +ia_css_stream_stop(struct ia_css_stream *stream); + +/* @brief Check if a stream has stopped + * @param[in] stream The stream. + * @return boolean flag + * + * This function will check if the stream has stopped and return the correspondent boolean flag. + */ +bool +ia_css_stream_has_stopped(struct ia_css_stream *stream); + +/* @brief destroy a stream according to the stream seed previosly saved in the seed array. + * @param[in] stream The stream. + * @return 0 (no other errors are generated now) + * + * Destroy the stream and all the pipes related to it. + */ +int +ia_css_stream_unload(struct ia_css_stream *stream); + +/* @brief Returns stream format + * @param[in] stream The stream. + * @return format of the string + * + * This function will return the stream format. + */ +enum atomisp_input_format +ia_css_stream_get_format(const struct ia_css_stream *stream); + +/* @brief Check if the stream is configured for 2 pixels per clock + * @param[in] stream The stream. + * @return boolean flag + * + * This function will check if the stream is configured for 2 pixels per clock and + * return the correspondent boolean flag. + */ +bool +ia_css_stream_get_two_pixels_per_clock(const struct ia_css_stream *stream); + +/* @brief Sets the output frame stride (at the last pipe) + * @param[in] stream The stream + * @param[in] output_padded_width - the output buffer stride. + * @return ia_css_err + * + * This function will Set the output frame stride (at the last pipe) + */ +int +ia_css_stream_set_output_padded_width(struct ia_css_stream *stream, + unsigned int output_padded_width); + +/* @brief Return max number of continuous RAW frames. + * @param[in] stream The stream. + * @param[out] buffer_depth The maximum number of continuous RAW frames. + * @return 0 or -EINVAL + * + * This function will return the maximum number of continuous RAW frames + * the system can support. + */ +int +ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, + int *buffer_depth); + +/* @brief Set nr of continuous RAW frames to use. + * + * @param[in] stream The stream. + * @param[in] buffer_depth Number of frames to set. + * @return 0 or error code upon error. + * + * Set the number of continuous frames to use during continuous modes. + */ +int +ia_css_stream_set_buffer_depth(struct ia_css_stream *stream, int buffer_depth); + +/* @brief Get number of continuous RAW frames to use. + * @param[in] stream The stream. + * @param[out] buffer_depth The number of frames to use + * @return 0 or -EINVAL + * + * Get the currently set number of continuous frames + * to use during continuous modes. + */ +int +ia_css_stream_get_buffer_depth(struct ia_css_stream *stream, int *buffer_depth); + +/* ===== CAPTURE ===== */ + +/* @brief Configure the continuous capture + * + * @param[in] stream The stream. + * @param[in] num_captures The number of RAW frames to be processed to + * YUV. Setting this to -1 will make continuous + * capture run until it is stopped. + * This number will also be used to allocate RAW + * buffers. To allow the viewfinder to also + * keep operating, 2 extra buffers will always be + * allocated. + * If the offset is negative and the skip setting + * is greater than 0, additional buffers may be + * needed. + * @param[in] skip Skip N frames in between captures. This can be + * used to select a slower capture frame rate than + * the sensor output frame rate. + * @param[in] offset Start the RAW-to-YUV processing at RAW buffer + * with this offset. This allows the user to + * process RAW frames that were captured in the + * past or future. + * @return 0 or error code upon error. + * + * For example, to capture the current frame plus the 2 previous + * frames and 2 subsequent frames, you would call + * ia_css_stream_capture(5, 0, -2). + */ +int +ia_css_stream_capture(struct ia_css_stream *stream, + int num_captures, + unsigned int skip, + int offset); + +/* @brief Specify which raw frame to tag based on exp_id found in frame info + * + * @param[in] stream The stream. + * @param[in] exp_id The exposure id of the raw frame to tag. + * + * @return 0 or error code upon error. + * + * This function allows the user to tag a raw frame based on the exposure id + * found in the viewfinder frames' frame info. + */ +int +ia_css_stream_capture_frame(struct ia_css_stream *stream, + unsigned int exp_id); + +/* ===== VIDEO ===== */ + +/* @brief Send streaming data into the css input FIFO + * + * @param[in] stream The stream. + * @param[in] data Pointer to the pixels to be send. + * @param[in] width Width of the input frame. + * @param[in] height Height of the input frame. + * @return None + * + * Send streaming data into the css input FIFO. This is for testing purposes + * only. This uses the channel ID and input format as set by the user with + * the regular functions for this. + * This function blocks until the entire frame has been written into the + * input FIFO. + * + * Note: + * For higher flexibility the ia_css_stream_send_input_frame is replaced by + * three separate functions: + * 1) ia_css_stream_start_input_frame + * 2) ia_css_stream_send_input_line + * 3) ia_css_stream_end_input_frame + * In this way it is possible to stream multiple frames on different + * channel ID's on a line basis. It will be possible to simulate + * line-interleaved Stereo 3D muxed on 1 mipi port. + * These 3 functions are for testing purpose only and can be used in + * conjunction with ia_css_stream_send_input_frame + */ +void +ia_css_stream_send_input_frame(const struct ia_css_stream *stream, + const unsigned short *data, + unsigned int width, + unsigned int height); + +/* @brief Start an input frame on the CSS input FIFO. + * + * @param[in] stream The stream. + * @return None + * + * Starts the streaming to mipi frame by sending SoF for channel channel_id. + * It will use the input_format and two_pixels_per_clock as provided by + * the user. + * For the "correct" use-case, input_format and two_pixels_per_clock must match + * with the values as set by the user with the regular functions. + * To simulate an error, the user can provide "incorrect" values for + * input_format and/or two_pixels_per_clock. + */ +void +ia_css_stream_start_input_frame(const struct ia_css_stream *stream); + +/* @brief Send a line of input data into the CSS input FIFO. + * + * @param[in] stream The stream. + * @param[in] data Array of the first line of image data. + * @param width The width (in pixels) of the first line. + * @param[in] data2 Array of the second line of image data. + * @param width2 The width (in pixels) of the second line. + * @return None + * + * Sends 1 frame line. Start with SoL followed by width bytes of data, followed + * by width2 bytes of data2 and followed by and EoL + * It will use the input_format and two_pixels_per_clock settings as provided + * with the ia_css_stream_start_input_frame function call. + * + * This function blocks until the entire line has been written into the + * input FIFO. + */ +void +ia_css_stream_send_input_line(const struct ia_css_stream *stream, + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2); + +/* @brief Send a line of input embedded data into the CSS input FIFO. + * + * @param[in] stream Pointer of the stream. + * @param[in] format Format of the embedded data. + * @param[in] data Pointer of the embedded data line. + * @param[in] width The width (in pixels) of the line. + * @return None + * + * Sends one embedded data line to input fifo. Start with SoL followed by + * width bytes of data, and followed by and EoL. + * It will use the two_pixels_per_clock settings as provided with the + * ia_css_stream_start_input_frame function call. + * + * This function blocks until the entire line has been written into the + * input FIFO. + */ +void +ia_css_stream_send_input_embedded_line(const struct ia_css_stream *stream, + enum atomisp_input_format format, + const unsigned short *data, + unsigned int width); + +/* @brief End an input frame on the CSS input FIFO. + * + * @param[in] stream The stream. + * @return None + * + * Send the end-of-frame signal into the CSS input FIFO. + */ +void +ia_css_stream_end_input_frame(const struct ia_css_stream *stream); + +/* @brief send a request flash command to SP + * + * @param[in] stream The stream. + * @return None + * + * Driver needs to call this function to send a flash request command + * to SP, SP will be responsible for switching on/off the flash at proper + * time. Due to the SP multi-threading environment, this request may have + * one-frame delay, the driver needs to check the flashed flag in frame info + * to determine which frame is being flashed. + */ +void +ia_css_stream_request_flash(struct ia_css_stream *stream); + +/* @brief Configure a stream with filter coefficients. + * @deprecated {Replaced by + * ia_css_pipe_set_isp_config_on_pipe()} + * + * @param[in] stream The stream. + * @param[in] config The set of filter coefficients. + * @param[in] pipe Pipe to be updated when set isp config, NULL means to + * update all pipes in the stream. + * @return 0 or error code upon error. + * + * This function configures the filter coefficients for an image + * stream. For image pipes that do not execute any ISP filters, this + * function will have no effect. + * It is safe to call this function while the image stream is running, + * in fact this is the expected behavior most of the time. Proper + * resource locking and double buffering is in place to allow for this. + */ +int +ia_css_stream_set_isp_config_on_pipe(struct ia_css_stream *stream, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe); + +/* @brief Configure a stream with filter coefficients. + * @deprecated {Replaced by + * ia_css_pipe_set_isp_config()} + * @param[in] stream The stream. + * @param[in] config The set of filter coefficients. + * @return 0 or error code upon error. + * + * This function configures the filter coefficients for an image + * stream. For image pipes that do not execute any ISP filters, this + * function will have no effect. All pipes of a stream will be updated. + * See ::ia_css_stream_set_isp_config_on_pipe() for the per-pipe alternative. + * It is safe to call this function while the image stream is running, + * in fact this is the expected behaviour most of the time. Proper + * resource locking and double buffering is in place to allow for this. + */ +int +ia_css_stream_set_isp_config( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config); + +/* @brief Get selected configuration settings + * @param[in] stream The stream. + * @param[out] config Configuration settings. + * @return None + */ +void +ia_css_stream_get_isp_config(const struct ia_css_stream *stream, + struct ia_css_isp_config *config); + +/* @brief allocate continuous raw frames for continuous capture + * @param[in] stream The stream. + * @return 0 or error code. + * + * because this allocation takes a long time (around 120ms per frame), + * we separate the allocation part and update part to let driver call + * this function without locking. This function is the allocation part + * and next one is update part + */ +int +ia_css_alloc_continuous_frame_remain(struct ia_css_stream *stream); + +/* @brief allocate continuous raw frames for continuous capture + * @param[in] stream The stream. + * @return 0 or error code. + * + * because this allocation takes a long time (around 120ms per frame), + * we separate the allocation part and update part to let driver call + * this function without locking. This function is the update part + */ +int +ia_css_update_continuous_frames(struct ia_css_stream *stream); + +/* @brief ia_css_unlock_raw_frame . unlock a raw frame (HALv3 Support) + * @param[in] stream The stream. + * @param[in] exp_id exposure id that uniquely identifies the locked Raw Frame Buffer + * @return ia_css_err 0 or error code + * + * As part of HALv3 Feature requirement, SP locks raw buffer until the Application + * releases its reference to a raw buffer (which are managed by SP), this function allows + * application to explicitly unlock that buffer in SP. + */ +int +ia_css_unlock_raw_frame(struct ia_css_stream *stream, uint32_t exp_id); + +/* @brief ia_css_en_dz_capt_pipe . Enable/Disable digital zoom for capture pipe + * @param[in] stream The stream. + * @param[in] enable - true, disable - false + * @return None + * + * Enables or disables digital zoom for capture pipe in provided stream, if capture pipe + * exists. This function sets enable_zoom flag in CAPTURE_PP stage of the capture pipe. + * In process_zoom_and_motion(), decision to enable or disable zoom for every stage depends + * on this flag. + */ +void +ia_css_en_dz_capt_pipe(struct ia_css_stream *stream, bool enable); +#endif /* __IA_CSS_STREAM_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_timer.h b/drivers/staging/media/atomisp/pci/ia_css_timer.h new file mode 100644 index 000000000..c78fbda90 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_timer.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_TIMER_H +#define __IA_CSS_TIMER_H + +/* @file + * Timer interface definitions + */ +#include /* for uint32_t */ +#include "ia_css_err.h" + +/* @brief timer reading definition */ +typedef u32 clock_value_t; + +/* @brief 32 bit clock tick,(timestamp based on timer-value of CSS-internal timer)*/ +struct ia_css_clock_tick { + clock_value_t ticks; /** measured time in ticks.*/ +}; + +/* @brief TIMER event codes */ +enum ia_css_tm_event { + IA_CSS_TM_EVENT_AFTER_INIT, + /** Timer Event after Initialization */ + IA_CSS_TM_EVENT_MAIN_END, + /** Timer Event after end of Main */ + IA_CSS_TM_EVENT_THREAD_START, + /** Timer Event after thread start */ + IA_CSS_TM_EVENT_FRAME_PROC_START, + /** Timer Event after Frame Process Start */ + IA_CSS_TM_EVENT_FRAME_PROC_END + /** Timer Event after Frame Process End */ +}; + +/* @brief code measurement common struct */ +struct ia_css_time_meas { + clock_value_t start_timer_value; /** measured time in ticks */ + clock_value_t end_timer_value; /** measured time in ticks */ +}; + +/**@brief SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT checks to ensure correct alignment for struct ia_css_clock_tick. */ +#define SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT sizeof(clock_value_t) +/* @brief checks to ensure correct alignment for ia_css_time_meas. */ +#define SIZE_OF_IA_CSS_TIME_MEAS_STRUCT (sizeof(clock_value_t) \ + + sizeof(clock_value_t)) + +/* @brief API to fetch timer count directly +* +* @param curr_ts [out] measured count value +* @return 0 if success +* +*/ +int +ia_css_timer_get_current_tick( + struct ia_css_clock_tick *curr_ts); + +#endif /* __IA_CSS_TIMER_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_tpg.h b/drivers/staging/media/atomisp/pci/ia_css_tpg.h new file mode 100644 index 000000000..8c744bedb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_tpg.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TPG_H +#define __IA_CSS_TPG_H + +/* @file + * This file contains support for the test pattern generator (TPG) + */ + +/* Enumerate the TPG IDs. + */ +enum ia_css_tpg_id { + IA_CSS_TPG_ID0, + IA_CSS_TPG_ID1, + IA_CSS_TPG_ID2 +}; + +/** + * Maximum number of TPG IDs. + * + * Make sure the value of this define gets changed to reflect the correct + * number of ia_css_tpg_id enum if you add/delete an item in the enum. + */ +#define N_CSS_TPG_IDS (IA_CSS_TPG_ID2 + 1) + +/* Enumerate the TPG modes. + */ +enum ia_css_tpg_mode { + IA_CSS_TPG_MODE_RAMP, + IA_CSS_TPG_MODE_CHECKERBOARD, + IA_CSS_TPG_MODE_FRAME_BASED_COLOR, + IA_CSS_TPG_MODE_MONO +}; + +/* @brief Configure the test pattern generator. + * + * Configure the Test Pattern Generator, the way these values are used to + * generate the pattern can be seen in the HRT extension for the test pattern + * generator: + * devices/test_pat_gen/hrt/include/test_pat_gen.h: hrt_calc_tpg_data(). + * + * This interface is deprecated, it is not portable -> move to input system API + * +@code +unsigned int test_pattern_value(unsigned int x, unsigned int y) +{ + unsigned int x_val, y_val; + if (x_delta > 0) (x_val = (x << x_delta) & x_mask; + else (x_val = (x >> -x_delta) & x_mask; + if (y_delta > 0) (y_val = (y << y_delta) & y_mask; + else (y_val = (y >> -y_delta) & x_mask; + return (x_val + y_val) & xy_mask; +} +@endcode + */ +struct ia_css_tpg_config { + enum ia_css_tpg_id id; + enum ia_css_tpg_mode mode; + unsigned int x_mask; + int x_delta; + unsigned int y_mask; + int y_delta; + unsigned int xy_mask; +}; + +#endif /* __IA_CSS_TPG_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_types.h b/drivers/staging/media/atomisp/pci/ia_css_types.h new file mode 100644 index 000000000..6e34d401f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_types.h @@ -0,0 +1,603 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_TYPES_H +#define _IA_CSS_TYPES_H + +/* @file + * This file contains types used for the ia_css parameters. + * These types are in a separate file because they are expected + * to be used in software layers that do not access the CSS API + * directly but still need to forward parameters for it. + */ + +#include + +#include "ia_css_frac.h" + +#include "isp/kernels/aa/aa_2/ia_css_aa2_types.h" +#include "isp/kernels/anr/anr_1.0/ia_css_anr_types.h" +#include "isp/kernels/anr/anr_2/ia_css_anr2_types.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h" +#include "isp/kernels/csc/csc_1.0/ia_css_csc_types.h" +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp_types.h" +#include "isp/kernels/de/de_1.0/ia_css_de_types.h" +#include "isp/kernels/de/de_2/ia_css_de2_types.h" +#include "isp/kernels/fc/fc_1.0/ia_css_formats_types.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn_types.h" +#include "isp/kernels/gc/gc_1.0/ia_css_gc_types.h" +#include "isp/kernels/gc/gc_2/ia_css_gc2_types.h" +#include "isp/kernels/macc/macc_1.0/ia_css_macc_types.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob_types.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h" +#include "isp/kernels/sc/sc_1.0/ia_css_sc_types.h" +#include "isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h" +#include "isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h" +#include "isp/kernels/wb/wb_1.0/ia_css_wb_types.h" +#include "isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h" +#include "isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h" + +/* ISP2401 */ +#include "isp/kernels/tnr/tnr3/ia_css_tnr3_types.h" + +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr_types.h" +#include "isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h" +#include "isp/kernels/output/output_1.0/ia_css_output_types.h" + +#define IA_CSS_DVS_STAT_GRID_INFO_SUPPORTED +/** Should be removed after Driver adaptation will be done */ + +#define IA_CSS_VERSION_MAJOR 2 +#define IA_CSS_VERSION_MINOR 0 +#define IA_CSS_VERSION_REVISION 2 + +#define IA_CSS_MORPH_TABLE_NUM_PLANES 6 + +/* Min and max exposure IDs. These macros are here to allow + * the drivers to get this information. Changing these macros + * constitutes a CSS API change. */ +#define IA_CSS_ISYS_MIN_EXPOSURE_ID 1 /** Minimum exposure ID */ +#define IA_CSS_ISYS_MAX_EXPOSURE_ID 250 /** Maximum exposure ID */ + +/* opaque types */ +struct ia_css_isp_parameters; +struct ia_css_pipe; +struct ia_css_memory_offsets; +struct ia_css_config_memory_offsets; +struct ia_css_state_memory_offsets; + +/* Virtual address within the CSS address space. */ +typedef u32 ia_css_ptr; + +/* Generic resolution structure. + */ +struct ia_css_resolution { + u32 width; /** Width */ + u32 height; /** Height */ +}; + +/* Generic coordinate structure. + */ +struct ia_css_coordinate { + s32 x; /** Value of a coordinate on the horizontal axis */ + s32 y; /** Value of a coordinate on the vertical axis */ +}; + +/* Vector with signed values. This is used to indicate motion for + * Digital Image Stabilization. + */ +struct ia_css_vector { + s32 x; /** horizontal motion (in pixels) */ + s32 y; /** vertical motion (in pixels) */ +}; + +/* Short hands */ +#define IA_CSS_ISP_DMEM IA_CSS_ISP_DMEM0 +#define IA_CSS_ISP_VMEM IA_CSS_ISP_VMEM0 + +/* CSS data descriptor */ +struct ia_css_data { + ia_css_ptr address; /** CSS virtual address */ + u32 size; /** Disabled if 0 */ +}; + +/* Host data descriptor */ +struct ia_css_host_data { + char *address; /** Host address */ + u32 size; /** Disabled if 0 */ +}; + +/* ISP data descriptor */ +struct ia_css_isp_data { + u32 address; /** ISP address */ + u32 size; /** Disabled if 0 */ +}; + +/* Shading Correction types. */ +enum ia_css_shading_correction_type { + IA_CSS_SHADING_CORRECTION_NONE, /** Shading Correction is not processed in the pipe. */ + IA_CSS_SHADING_CORRECTION_TYPE_1 /** Shading Correction 1.0 (pipe 1.0 on ISP2300, pipe 2.2 on ISP2400/2401) */ + + /** More shading correction types can be added in the future. */ +}; + +/* Shading Correction information. */ +struct ia_css_shading_info { + enum ia_css_shading_correction_type type; /** Shading Correction type. */ + + union { /* Shading Correction information of each Shading Correction types. */ + + /* Shading Correction information of IA_CSS_SHADING_CORRECTION_TYPE_1. + * + * This structure contains the information necessary to generate + * the shading table required in the isp. + * This structure is filled in the css, + * and the driver needs to get it to generate the shading table. + * + * Before the shading correction is applied, NxN-filter and/or scaling + * are applied in the isp, depending on the isp binaries. + * Then, these should be considered in generating the shading table. + * - Bad pixels on left/top sides generated by NxN-filter + * (Bad pixels are NOT considered currently, + * because they are subtle.) + * - Down-scaling/Up-scaling factor + * + * Shading correction is applied to the area + * which has real sensor data and margin. + * Then, the shading table should cover the area including margin. + * This structure has this information. + * - Origin coordinate of bayer (real sensor data) + * on the shading table + * + * ------------------------ISP 2401----------------------- + * + * the shading table directly required from ISP. + * This structure is filled in CSS, and the driver needs to get it to generate the shading table. + * + * The shading correction is applied to the bayer area which contains sensor data and padding data. + * The shading table should cover this bayer area. + * + * The shading table size directly required from ISP is expressed by these parameters. + * 1. uint32_t num_hor_grids; + * 2. uint32_t num_ver_grids; + * 3. uint32_t bqs_per_grid_cell; + * + * In some isp binaries, the bayer scaling is applied before the shading correction is applied. + * Then, this scaling factor should be considered in generating the shading table. + * The scaling factor is expressed by these parameters. + * 4. uint32_t bayer_scale_hor_ratio_in; + * 5. uint32_t bayer_scale_hor_ratio_out; + * 6. uint32_t bayer_scale_ver_ratio_in; + * 7. uint32_t bayer_scale_ver_ratio_out; + * + * The sensor data size inputted to ISP is expressed by this parameter. + * This is the size BEFORE the bayer scaling is applied. + * 8. struct ia_css_resolution isp_input_sensor_data_res_bqs; + * + * The origin of the sensor data area positioned on the shading table at the shading correction + * is expressed by this parameter. + * The size of this area assumes the size AFTER the bayer scaling is applied + * to the isp_input_sensor_data_resolution_bqs. + * 9. struct ia_css_coordinate sensor_data_origin_bqs_on_sctbl; + * + * ****** Definitions of the shading table and the sensor data at the shading correction ****** + * + * (0,0)--------------------- TW ------------------------------- + * | shading table | + * | (ox,oy)---------- W -------------------------- | + * | | sensor data | | + * | | | | + * TH H sensor data center | | + * | | (cx,cy) | | + * | | | | + * | | | | + * | | | | + * | ------------------------------------------- | + * | | + * ---------------------------------------------------------- + * + * Example of still mode for output 1080p: + * + * num_hor_grids = 66 + * num_ver_grids = 37 + * bqs_per_grid_cell = 16 + * bayer_scale_hor_ratio_in = 1 + * bayer_scale_hor_ratio_out = 1 + * bayer_scale_ver_ratio_in = 1 + * bayer_scale_ver_ratio_out = 1 + * isp_input_sensor_data_resolution_bqs = {966, 546} + * sensor_data_origin_bqs_on_sctbl = {61, 15} + * + * TW, TH [bqs]: width and height of shading table + * TW = (num_hor_grids - 1) * bqs_per_grid_cell = (66 - 1) * 16 = 1040 + * TH = (num_ver_grids - 1) * bqs_per_grid_cell = (37 - 1) * 16 = 576 + * + * W, H [bqs]: width and height of sensor data at shading correction + * W = sensor_data_res_bqs.width + * = isp_input_sensor_data_res_bqs.width + * * bayer_scale_hor_ratio_out / bayer_scale_hor_ratio_in + 0.5 = 966 + * H = sensor_data_res_bqs.height + * = isp_input_sensor_data_res_bqs.height + * * bayer_scale_ver_ratio_out / bayer_scale_ver_ratio_in + 0.5 = 546 + * + * (ox, oy) [bqs]: origin of sensor data positioned on shading table at shading correction + * ox = sensor_data_origin_bqs_on_sctbl.x = 61 + * oy = sensor_data_origin_bqs_on_sctbl.y = 15 + * + * (cx, cy) [bqs]: center of sensor data positioned on shading table at shading correction + * cx = ox + W/2 = 61 + 966/2 = 544 + * cy = oy + H/2 = 15 + 546/2 = 288 + * + * ****** Relation between the shading table and the sensor data ****** + * + * The origin of the sensor data should be on the shading table. + * 0 <= ox < TW, 0 <= oy < TH + * + * ****** How to center the shading table on the sensor data ****** + * + * To center the shading table on the sensor data, + * CSS decides the shading table size so that a certain grid point is positioned + * on the center of the sensor data at the shading correction. + * CSS expects the shading center is set on this grid point + * when the shading table data is calculated in AIC. + * + * W, H [bqs]: width and height of sensor data at shading correction + * W = sensor_data_res_bqs.width + * H = sensor_data_res_bqs.height + * + * (cx, cy) [bqs]: center of sensor data positioned on shading table at shading correction + * cx = sensor_data_origin_bqs_on_sctbl.x + W/2 + * cy = sensor_data_origin_bqs_on_sctbl.y + H/2 + * + * CSS decides the shading table size and the sensor data position + * so that the (cx, cy) satisfies this condition. + * mod(cx, bqs_per_grid_cell) = 0 + * mod(cy, bqs_per_grid_cell) = 0 + * + * ****** How to change the sensor data size by processes in the driver and ISP ****** + * + * 1. sensor data size: Physical sensor size + * (The struct ia_css_shading_info does not have this information.) + * 2. process: Driver applies the sensor cropping/binning/scaling to physical sensor size. + * 3. sensor data size: ISP input size (== shading_info.isp_input_sensor_data_res_bqs) + * (ISP assumes the ISP input sensor data is centered on the physical sensor.) + * 4. process: ISP applies the bayer scaling by the factor of shading_info.bayer_scale_*. + * 5. sensor data size: Scaling factor * ISP input size (== shading_info.sensor_data_res_bqs) + * 6. process: ISP applies the shading correction. + * + * ISP block: SC1 + * ISP1: SC1 is used. + * ISP2: SC1 is used. + */ + struct { + /* ISP2400 */ + u32 enable; /** Shading correction enabled. + 0:disabled, 1:enabled */ + + /* ISP2401 */ + u32 num_hor_grids; /** Number of data points per line per color on shading table. */ + u32 num_ver_grids; /** Number of lines of data points per color on shading table. */ + u32 bqs_per_grid_cell; /** Grid cell size in BQ unit. + NOTE: bqs = size in BQ(Bayer Quad) unit. + 1BQ means {Gr,R,B,Gb} (2x2 pixels). + Horizontal 1 bqs corresponds to horizontal 2 pixels. + Vertical 1 bqs corresponds to vertical 2 pixels. */ + u32 bayer_scale_hor_ratio_in; + u32 bayer_scale_hor_ratio_out; + + /** Horizontal ratio of bayer scaling between input width and output width, + for the scaling which should be done before shading correction. + output_width = input_width * bayer_scale_hor_ratio_out + / bayer_scale_hor_ratio_in + 0.5 */ + u32 bayer_scale_ver_ratio_in; + u32 bayer_scale_ver_ratio_out; + + /** Vertical ratio of bayer scaling + between input height and output height, for the scaling + which should be done before shading correction. + output_height = input_height * bayer_scale_ver_ratio_out + / bayer_scale_ver_ratio_in */ + /* ISP2400 */ + u32 sc_bayer_origin_x_bqs_on_shading_table; + /** X coordinate (in bqs) of bayer origin on shading table. + This indicates the left-most pixel of bayer + (not include margin) inputted to the shading correction. + This corresponds to the left-most pixel of bayer + inputted to isp from sensor. */ + /* ISP2400 */ + u32 sc_bayer_origin_y_bqs_on_shading_table; + /** Y coordinate (in bqs) of bayer origin on shading table. + This indicates the top pixel of bayer + (not include margin) inputted to the shading correction. + This corresponds to the top pixel of bayer + inputted to isp from sensor. */ + + /** Vertical ratio of bayer scaling between input height and output height, + for the scaling which should be done before shading correction. + output_height = input_height * bayer_scale_ver_ratio_out + / bayer_scale_ver_ratio_in + 0.5 */ + /* ISP2401 */ + struct ia_css_resolution isp_input_sensor_data_res_bqs; + /** Sensor data size (in bqs) inputted to ISP. This is the size BEFORE bayer scaling. + NOTE: This is NOT the size of the physical sensor size. + CSS requests the driver that ISP inputs sensor data + by the size of isp_input_sensor_data_res_bqs. + The driver sends the sensor data to ISP, + after the adequate cropping/binning/scaling + are applied to the physical sensor data area. + ISP assumes the area of isp_input_sensor_data_res_bqs + is centered on the physical sensor. */ + /* ISP2401 */ + struct ia_css_resolution sensor_data_res_bqs; + /** Sensor data size (in bqs) at shading correction. + This is the size AFTER bayer scaling. */ + /* ISP2401 */ + struct ia_css_coordinate sensor_data_origin_bqs_on_sctbl; + /** Origin of sensor data area positioned on shading table at shading correction. + The coordinate x,y should be positive values. */ + } type_1; + + /** More structures can be added here when more shading correction types will be added + in the future. */ + } info; +}; + +/* Default Shading Correction information of Shading Correction Type 1. */ +#define DEFAULT_SHADING_INFO_TYPE_1 \ +(struct ia_css_shading_info) { \ + .type = IA_CSS_SHADING_CORRECTION_TYPE_1, \ + .info = { \ + .type_1 = { \ + .bayer_scale_hor_ratio_in = 1, \ + .bayer_scale_hor_ratio_out = 1, \ + .bayer_scale_ver_ratio_in = 1, \ + .bayer_scale_ver_ratio_out = 1, \ + } \ + } \ +} + +/* Default Shading Correction information. */ +#define DEFAULT_SHADING_INFO DEFAULT_SHADING_INFO_TYPE_1 + +/* structure that describes the 3A and DIS grids */ +struct ia_css_grid_info { + /* \name ISP input size + * that is visible for user + * @{ + */ + u32 isp_in_width; + u32 isp_in_height; + /* @}*/ + + struct ia_css_3a_grid_info s3a_grid; /** 3A grid info */ + union ia_css_dvs_grid_u dvs_grid; + /** All types of DVS statistics grid info union */ + + enum ia_css_vamem_type vamem_type; +}; + +/* defaults for ia_css_grid_info structs */ +#define DEFAULT_GRID_INFO { \ + .dvs_grid = DEFAULT_DVS_GRID_INFO, \ + .vamem_type = IA_CSS_VAMEM_TYPE_1 \ +} + +/* Morphing table, used for geometric distortion and chromatic abberration + * correction (GDCAC, also called GDC). + * This table describes the imperfections introduced by the lens, the + * advanced ISP can correct for these imperfections using this table. + */ +struct ia_css_morph_table { + u32 enable; /** To disable GDC, set this field to false. The + coordinates fields can be set to NULL in this case. */ + u32 height; /** Table height */ + u32 width; /** Table width */ + u16 *coordinates_x[IA_CSS_MORPH_TABLE_NUM_PLANES]; + /** X coordinates that describe the sensor imperfection */ + u16 *coordinates_y[IA_CSS_MORPH_TABLE_NUM_PLANES]; + /** Y coordinates that describe the sensor imperfection */ +}; + +struct ia_css_dvs_6axis_config { + unsigned int exp_id; + /** Exposure ID, see ia_css_event_public.h for more detail */ + u32 width_y; + u32 height_y; + u32 width_uv; + u32 height_uv; + u32 *xcoords_y; + u32 *ycoords_y; + u32 *xcoords_uv; + u32 *ycoords_uv; +}; + +/** + * This specifies the coordinates (x,y) + */ +struct ia_css_point { + s32 x; /** x coordinate */ + s32 y; /** y coordinate */ +}; + +/** + * This specifies the region + */ +struct ia_css_region { + struct ia_css_point origin; /** Starting point coordinates for the region */ + struct ia_css_resolution resolution; /** Region resolution */ +}; + +/** + * Digital zoom: + * This feature is currently available only for video, but will become + * available for preview and capture as well. + * Set the digital zoom factor, this is a logarithmic scale. The actual zoom + * factor will be 64/x. + * Setting dx or dy to 0 disables digital zoom for that direction. + * New API change for Digital zoom:(added struct ia_css_region zoom_region) + * zoom_region specifies the origin of the zoom region and width and + * height of that region. + * origin : This is the coordinate (x,y) within the effective input resolution + * of the stream. where, x >= 0 and y >= 0. (0,0) maps to the upper left of the + * effective input resolution. + * resolution : This is resolution of zoom region. + * where, x + width <= effective input width + * y + height <= effective input height + */ +struct ia_css_dz_config { + u32 dx; /** Horizontal zoom factor */ + u32 dy; /** Vertical zoom factor */ + struct ia_css_region zoom_region; /** region for zoom */ +}; + +/* The still capture mode, this can be RAW (simply copy sensor input to DDR), + * Primary ISP, the Advanced ISP (GDC) or the low-light ISP (ANR). + */ +enum ia_css_capture_mode { + IA_CSS_CAPTURE_MODE_RAW, /** no processing, copy data only */ + IA_CSS_CAPTURE_MODE_BAYER, /** bayer processing, up to demosaic */ + IA_CSS_CAPTURE_MODE_PRIMARY, /** primary ISP */ + IA_CSS_CAPTURE_MODE_ADVANCED, /** advanced ISP (GDC) */ + IA_CSS_CAPTURE_MODE_LOW_LIGHT /** low light ISP (ANR) */ +}; + +struct ia_css_capture_config { + enum ia_css_capture_mode mode; /** Still capture mode */ + u32 enable_xnr; /** Enable/disable XNR */ + u32 enable_raw_output; + bool enable_capture_pp_bli; /** Enable capture_pp_bli mode */ +}; + +/* default settings for ia_css_capture_config structs */ +#define DEFAULT_CAPTURE_CONFIG { \ + .mode = IA_CSS_CAPTURE_MODE_PRIMARY, \ +} + +/* ISP filter configuration. This is a collection of configurations + * for each of the ISP filters (modules). + * + * NOTE! The contents of all pointers is copied when get or set with the + * exception of the shading and morph tables. For these we only copy the + * pointer, so the caller must make sure the memory contents of these pointers + * remain valid as long as they are used by the CSS. This will be fixed in the + * future by copying the contents instead of just the pointer. + * + * Comment: + * ["ISP block", 1&2] : ISP block is used both for ISP1 and ISP2. + * ["ISP block", 1only] : ISP block is used only for ISP1. + * ["ISP block", 2only] : ISP block is used only for ISP2. + */ +struct ia_css_isp_config { + struct ia_css_wb_config *wb_config; /** White Balance + [WB1, 1&2] */ + struct ia_css_cc_config *cc_config; /** Color Correction + [CSC1, 1only] */ + struct ia_css_tnr_config *tnr_config; /** Temporal Noise Reduction + [TNR1, 1&2] */ + struct ia_css_ecd_config *ecd_config; /** Eigen Color Demosaicing + [DE2, 2only] */ + struct ia_css_ynr_config *ynr_config; /** Y(Luma) Noise Reduction + [YNR2&YEE2, 2only] */ + struct ia_css_fc_config *fc_config; /** Fringe Control + [FC2, 2only] */ + struct ia_css_formats_config + *formats_config; /** Formats Control for main output + [FORMATS, 1&2] */ + struct ia_css_cnr_config *cnr_config; /** Chroma Noise Reduction + [CNR2, 2only] */ + struct ia_css_macc_config *macc_config; /** MACC + [MACC2, 2only] */ + struct ia_css_ctc_config *ctc_config; /** Chroma Tone Control + [CTC2, 2only] */ + struct ia_css_aa_config *aa_config; /** YUV Anti-Aliasing + [AA2, 2only] + (not used currently) */ + struct ia_css_aa_config *baa_config; /** Bayer Anti-Aliasing + [BAA2, 1&2] */ + struct ia_css_ce_config *ce_config; /** Chroma Enhancement + [CE1, 1only] */ + struct ia_css_dvs_6axis_config *dvs_6axis_config; + struct ia_css_ob_config *ob_config; /** Objective Black + [OB1, 1&2] */ + struct ia_css_dp_config *dp_config; /** Defect Pixel Correction + [DPC1/DPC2, 1&2] */ + struct ia_css_nr_config *nr_config; /** Noise Reduction + [BNR1&YNR1&CNR1, 1&2]*/ + struct ia_css_ee_config *ee_config; /** Edge Enhancement + [YEE1, 1&2] */ + struct ia_css_de_config *de_config; /** Demosaic + [DE1, 1only] */ + struct ia_css_gc_config *gc_config; /** Gamma Correction (for YUV) + [GC1, 1only] */ + struct ia_css_anr_config *anr_config; /** Advanced Noise Reduction */ + struct ia_css_3a_config *s3a_config; /** 3A Statistics config */ + struct ia_css_xnr_config *xnr_config; /** eXtra Noise Reduction */ + struct ia_css_dz_config *dz_config; /** Digital Zoom */ + struct ia_css_cc_config *yuv2rgb_cc_config; /** Color Correction + [CCM2, 2only] */ + struct ia_css_cc_config *rgb2yuv_cc_config; /** Color Correction + [CSC2, 2only] */ + struct ia_css_macc_table *macc_table; /** MACC + [MACC1/MACC2, 1&2]*/ + struct ia_css_gamma_table *gamma_table; /** Gamma Correction (for YUV) + [GC1, 1only] */ + struct ia_css_ctc_table *ctc_table; /** Chroma Tone Control + [CTC1, 1only] */ + + /* \deprecated */ + struct ia_css_xnr_table *xnr_table; /** eXtra Noise Reduction + [XNR1, 1&2] */ + struct ia_css_rgb_gamma_table *r_gamma_table;/** sRGB Gamma Correction + [GC2, 2only] */ + struct ia_css_rgb_gamma_table *g_gamma_table;/** sRGB Gamma Correction + [GC2, 2only] */ + struct ia_css_rgb_gamma_table *b_gamma_table;/** sRGB Gamma Correction + [GC2, 2only] */ + struct ia_css_vector *motion_vector; /** For 2-axis DVS */ + struct ia_css_shading_table *shading_table; + struct ia_css_morph_table *morph_table; + struct ia_css_dvs_coefficients *dvs_coefs; /** DVS 1.0 coefficients */ + struct ia_css_dvs2_coefficients *dvs2_coefs; /** DVS 2.0 coefficients */ + struct ia_css_capture_config *capture_config; + struct ia_css_anr_thres *anr_thres; + /* @deprecated{Old shading settings, see bugzilla bz675 for details} */ + struct ia_css_shading_settings *shading_settings; + struct ia_css_xnr3_config *xnr3_config; /** eXtreme Noise Reduction v3 */ + /* comment from Lasse: Be aware how this feature will affect coordinate + * normalization in different parts of the system. (e.g. face detection, + * touch focus, 3A statistics and windows of interest, shading correction, + * DVS, GDC) from IQ tool level and application level down-to ISP FW level. + * the risk for regression is not in the individual blocks, but how they + * integrate together. */ + struct ia_css_output_config + *output_config; /** Main Output Mirroring, flipping */ + + struct ia_css_scaler_config + *scaler_config; /** Skylake: scaler config (optional) */ + struct ia_css_formats_config + *formats_config_display;/** Formats control for viewfinder/display output (optional) + [OSYS, n/a] */ + struct ia_css_output_config + *output_config_display; /** Viewfinder/display output mirroring, flipping (optional) */ + + struct ia_css_frame + *output_frame; /** Output frame the config is to be applied to (optional) */ + u32 isp_config_id; /** Unique ID to track which config was actually applied to a particular frame */ +}; + +#endif /* _IA_CSS_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_version.h b/drivers/staging/media/atomisp/pci/ia_css_version.h new file mode 100644 index 000000000..cf1d010ba --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_version.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_VERSION_H +#define __IA_CSS_VERSION_H + +/* @file + * This file contains functions to retrieve CSS-API version information + */ + +#include + +/* a common size for the version arrays */ +#define MAX_VERSION_SIZE 500 + +/* @brief Retrieves the current CSS version + * @param[out] version A pointer to a buffer where to put the generated + * version string. NULL is ignored. + * @param[in] max_size Size of the version buffer. If version string + * would be larger than max_size, an error is + * returned by this function. + * + * This function generates and returns the version string. If FW is loaded, it + * attaches the FW version. + */ +int +ia_css_get_version(char *version, int max_size); + +#endif /* __IA_CSS_VERSION_H */ diff --git a/drivers/staging/media/atomisp/pci/ia_css_version_data.h b/drivers/staging/media/atomisp/pci/ia_css_version_data.h new file mode 100644 index 000000000..428d78e16 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/ia_css_version_data.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +// +// This file contains the version data for the CSS +// +// === Do not change - automatically generated === +// + +#ifndef __IA_CSS_VERSION_DATA_H +#define __IA_CSS_VERSION_DATA_H + +#define ISP2400_CSS_VERSION_STRING "REL:20150521_21.4_0539; API:2.1.15.3; GIT:irci_candrpv_0415_20150504_35b345#35b345be52ac575f8934abb3a88fea26a94e7343; SDK:/nfs/iir/disks/iir_hivepackages_003/iir_hivepkgs_disk017/Css_Mizuchi/packages/Css_Mizuchi/int_css_mizuchi_20140829_1053; USER:viedifw; " +#define ISP2401_CSS_VERSION_STRING "REL:20150911_37.5_1652; API:2.1.20.9; GIT:irci___#ebf437d53a8951bb7ff6d13fdb7270dab393a92a; SDK:; USER:viedifw; " + +#endif diff --git a/drivers/staging/media/atomisp/pci/if_defs.h b/drivers/staging/media/atomisp/pci/if_defs.h new file mode 100644 index 000000000..e21efa749 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/if_defs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IF_DEFS_H +#define _IF_DEFS_H + +#define HIVE_IF_FRAME_REQUEST 0xA000 +#define HIVE_IF_LINES_REQUEST 0xB000 +#define HIVE_IF_VECTORS_REQUEST 0xC000 + +#endif /* _IF_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/input_formatter_subsystem_defs.h b/drivers/staging/media/atomisp/pci/input_formatter_subsystem_defs.h new file mode 100644 index 000000000..594fc36a0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_formatter_subsystem_defs.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _if_subsystem_defs_h__ +#define _if_subsystem_defs_h__ + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8 +#define HIVE_IFMT_GP_REGS_SRST_IDX 9 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10 + +#define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11 + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 + +/* order of the input bits for the ifmt irq controller */ +#define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0 +#define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1 +#define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2 +#define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3 +#define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3 + +#endif /* _if_subsystem_defs_h__ */ diff --git a/drivers/staging/media/atomisp/pci/input_selector_defs.h b/drivers/staging/media/atomisp/pci/input_selector_defs.h new file mode 100644 index 000000000..61882e4cb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_selector_defs.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_selector_defs_h +#define _input_selector_defs_h + +#ifndef HIVE_ISP_ISEL_SEL_BITS +#define HIVE_ISP_ISEL_SEL_BITS 2 +#endif + +#ifndef HIVE_ISP_CH_ID_BITS +#define HIVE_ISP_CH_ID_BITS 2 +#endif + +#ifndef HIVE_ISP_FMT_TYPE_BITS +#define HIVE_ISP_FMT_TYPE_BITS 5 +#endif + +/* gp_register register id's -- Outputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1 +#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5 +#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7 + +#define HIVE_ISEL_GP_REGS_SOF_IDX 8 +#define HIVE_ISEL_GP_REGS_EOF_IDX 9 +#define HIVE_ISEL_GP_REGS_SOL_IDX 10 +#define HIVE_ISEL_GP_REGS_EOL_IDX 11 + +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12 +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13 +#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14 + +#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15 +#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18 +#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21 +#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22 +#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23 +#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24 +#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25 +#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26 +#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27 +#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28 + +#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29 +#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30 +#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31 +#define HIVE_ISEL_GP_REGS_SBAND_SEL_IDX 32 +#define HIVE_ISEL_GP_REGS_SYNC_SEL_IDX 33 +#define HIVE_ISEL_GP_REGS_SRST_IDX 37 + +#define HIVE_ISEL_GP_REGS_SRST_SYNCGEN_BIT 0 +#define HIVE_ISEL_GP_REGS_SRST_PRBS_BIT 1 +#define HIVE_ISEL_GP_REGS_SRST_TPG_BIT 2 +#define HIVE_ISEL_GP_REGS_SRST_FIFO_BIT 3 + +/* gp_register register id's -- Inputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_HOR_CNT_IDX 34 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VER_CNT_IDX 35 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FRAMES_CNT_IDX 36 + +/* irq sources isel irq controller */ +#define HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID 0 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID 1 +#define HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID 2 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID 3 +#define HIVE_ISEL_IRQ_NUM_IRQS 4 + +#endif /* _input_selector_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/input_switch_2400_defs.h b/drivers/staging/media/atomisp/pci/input_switch_2400_defs.h new file mode 100644 index 000000000..8ea1d7991 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_switch_2400_defs.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_switch_2400_defs_h +#define _input_switch_2400_defs_h + +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16)) +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2) + +#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3 +#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4 + +#endif /* _input_switch_2400_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/input_system_ctrl_defs.h b/drivers/staging/media/atomisp/pci/input_system_ctrl_defs.h new file mode 100644 index 000000000..b2076a969 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_system_ctrl_defs.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_ctrl_defs_h +#define _input_system_ctrl_defs_h + +#define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */ + +/* --------------------------------------------------*/ + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define ISYS_CTRL_NOF_REGS 23 + +// Register id's of MMIO slave accessible registers +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8 +#define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11 +#define ISYS_CTRL_INIT_REG_ID 12 +#define ISYS_CTRL_LAST_COMMAND_REG_ID 13 +#define ISYS_CTRL_NEXT_COMMAND_REG_ID 14 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16 +#define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22 + +/* register reset value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3 +#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ISYS_CTRL_INIT_REG_RSTVAL 0 +#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0 + +/* register width value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ISYS_CTRL_INIT_REG_WIDTH 3 +#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */ +#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1 + +/* bit definitions */ + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ + +/* +InpSysCaptFramesAcq 1/0 [3:0] - 'b0000 +[7:4] - CaptPortId, + CaptA-'b0000 + CaptB-'b0001 + CaptC-'b0010 +[31:16] - NOF_frames +InpSysCaptFrameExt 2/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + + 2/1 [31:0] - external capture address +InpSysAcqFrame 2/0 [3:0] - 'b0010, +[31:4] - NOF_ext_mem_words + 2/1 [31:0] - external memory read start address +InpSysOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + +InpSysOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + +InpSysOverruleCmd 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + 2/1 [31:0] - command token value for port opid + +acknowledge tokens: + +InpSysAckCFA 1/0 [3:0] - 'b0000 + [7:4] - CaptPortId, + CaptA-'b0000 + CaptB- 'b0001 + CaptC-'b0010 + [31:16] - NOF_frames +InpSysAckCFE 1/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + +InpSysAckAF 1/0 [3:0] - 'b0010 +InpSysAckOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + +InpSysAckOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + +InpSysAckOverrule 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + 2/1 [31:0] - acknowledge token value from port opid + +*/ + +/* Command and acknowledge tokens IDs */ +#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */ +#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */ +#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */ +#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */ +#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */ +#define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */ + +#define ISYS_CTRL_ACK_CFA_TOKEN_ID 0 +#define ISYS_CTRL_ACK_CFE_TOKEN_ID 1 +#define ISYS_CTRL_ACK_AF_TOKEN_ID 2 +#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3 +#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4 +#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5 +#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6 + +#define ISYS_CTRL_TOKEN_ID_MSB 3 +#define ISYS_CTRL_TOKEN_ID_LSB 0 +#define ISYS_CTRL_PORT_ID_TOKEN_MSB 7 +#define ISYS_CTRL_PORT_ID_TOKEN_LSB 4 +#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16 +#define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8 + +#define ISYS_CTRL_TOKEN_ID_IDX 0 +#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1) +#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS) +#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1) +#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB +#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1) +#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB +#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1) + +#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */ +#define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */ +#define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */ +#define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */ + +#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */ +#define ISYS_CTRL_NO_DMA_ACK 0 +#define ISYS_CTRL_NO_CAPT_ACK 16 + +#endif /* _input_system_ctrl_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/input_system_defs.h b/drivers/staging/media/atomisp/pci/input_system_defs.h new file mode 100644 index 000000000..0c6a74b18 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_system_defs.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_defs_h +#define _input_system_defs_h + +/* csi controller modes */ +#define HIVE_CSI_CONFIG_MAIN 0 +#define HIVE_CSI_CONFIG_STEREO1 4 +#define HIVE_CSI_CONFIG_STEREO2 8 + +/* general purpose register IDs */ + +/* Stream Multicast select modes */ +#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 +#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 +#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 + +/* Stream Mux select modes */ +#define HIVE_ISYS_GPREG_MUX_IDX 3 + +/* streaming monitor status and control */ +#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 +#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 +#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 +#define HIVE_ISYS_GPREG_SRST_IDX 7 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 +#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 +#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 + +/* Bit numbers of the soft reset register */ +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 +#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 +#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 +#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 +#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 +/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 +/* -- */ +#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 +#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 +#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 +#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv +#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 +#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 + +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 + +/* streaming monitor port id's */ +#define HIVE_ISYS_STR_MON_PORT_CAPA 0 +#define HIVE_ISYS_STR_MON_PORT_CAPB 1 +#define HIVE_ISYS_STR_MON_PORT_CAPC 2 +#define HIVE_ISYS_STR_MON_PORT_ACQ 3 +#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 +#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 +#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 +#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 +#define HIVE_ISYS_STR_MON_PORT_PIXA 8 +#define HIVE_ISYS_STR_MON_PORT_PIXB 9 + +/* interrupt bit ID's */ +#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 +#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 +#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 +#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 +#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 +#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ +#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 +/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ +#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 +#define HIVE_ISYS_IRQ_CIO2AHB 16 +#define HIVE_ISYS_IRQ_DMA_BIT_ID 17 +#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 +#define HIVE_ISYS_IRQ_NUM_BITS 19 + +/* DMA */ +#define HIVE_ISYS_DMA_CHANNEL 0 +#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 +#define HIVE_ISYS_DMA_HEIGHT 1 +#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ +#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ +#define HIVE_ISYS_DMA_CROP 0 /* no cropping */ +#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ + +#endif /* _input_system_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/input_system_global.h b/drivers/staging/media/atomisp/pci/input_system_global.h new file mode 100644 index 000000000..145096444 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_system_global.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (c) 2020 Mauro Carvalho Chehab + */ + + +#ifndef __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ +#define __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ +typedef enum { + INPUT_SYSTEM_ERR_NO_ERROR = 0, + /* ISP2401 */ + INPUT_SYSTEM_ERR_CREATE_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_CONFIGURE_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_OPEN_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_TRANSFER_FAIL, + INPUT_SYSTEM_ERR_CREATE_INPUT_PORT_FAIL, + INPUT_SYSTEM_ERR_CONFIGURE_INPUT_PORT_FAIL, + INPUT_SYSTEM_ERR_OPEN_INPUT_PORT_FAIL, + /* ISP2400 */ + INPUT_SYSTEM_ERR_GENERIC, + INPUT_SYSTEM_ERR_CHANNEL_ALREADY_SET, + INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE, + INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED, +} input_system_err_t; + +#include "isp2401_input_system_global.h" +#include "isp2400_input_system_global.h" + +#endif /* __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/input_system_local.h b/drivers/staging/media/atomisp/pci/input_system_local.h new file mode 100644 index 000000000..357987d62 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_system_local.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (c) 2020 Mauro Carvalho Chehab + */ + +#include "type_support.h" +#include "input_system_global.h" + +typedef enum { + INPUT_SYSTEM_PORT_A = 0, + INPUT_SYSTEM_PORT_B, + INPUT_SYSTEM_PORT_C, + N_INPUT_SYSTEM_PORTS +} input_system_csi_port_t; + +typedef struct ctrl_unit_cfg_s ctrl_unit_cfg_t; +typedef struct input_system_network_cfg_s input_system_network_cfg_t; +typedef struct target_cfg2400_s target_cfg2400_t; +typedef struct channel_cfg_s channel_cfg_t; +typedef struct backend_channel_cfg_s backend_channel_cfg_t; +typedef struct input_system_cfg2400_s input_system_cfg2400_t; +typedef struct mipi_port_state_s mipi_port_state_t; +typedef struct rx_channel_state_s rx_channel_state_t; +typedef struct input_switch_cfg_channel_s input_switch_cfg_channel_t; +typedef struct input_switch_cfg_s input_switch_cfg_t; + +struct ctrl_unit_cfg_s { + isp2400_ib_buffer_t buffer_mipi[N_CAPTURE_UNIT_ID]; + isp2400_ib_buffer_t buffer_acquire[N_ACQUISITION_UNIT_ID]; +}; + +struct input_system_network_cfg_s { + input_system_connection_t multicast_cfg[N_CAPTURE_UNIT_ID]; + input_system_multiplex_t mux_cfg; + ctrl_unit_cfg_t ctrl_unit_cfg[N_CTRL_UNIT_ID]; +}; + +typedef struct { +// TBD. + u32 dummy_parameter; +} target_isp_cfg_t; + +typedef struct { +// TBD. + u32 dummy_parameter; +} target_sp_cfg_t; + +typedef struct { +// TBD. + u32 dummy_parameter; +} target_strm2mem_cfg_t; + +struct input_switch_cfg_channel_s { + u32 hsync_data_reg[2]; + u32 vsync_data_reg; +}; + +struct backend_channel_cfg_s { + u32 fmt_control_word_1; // Format config. + u32 fmt_control_word_2; + u32 no_side_band; +}; + +typedef union { + csi_cfg_t csi_cfg; + tpg_cfg_t tpg_cfg; + prbs_cfg_t prbs_cfg; + gpfifo_cfg_t gpfifo_cfg; +} source_cfg_t; + +struct input_switch_cfg_s { + u32 hsync_data_reg[N_RX_CHANNEL_ID * 2]; + u32 vsync_data_reg; +}; + +/* + * In 2300 ports can be configured independently and stream + * formats need to be specified. In 2400, there are only 8 + * supported configurations but the HW is fused to support + * only a single one. + * + * In 2300 the compressed format types are programmed by the + * user. In 2400 all stream formats are encoded on the stream. + * + * Use the enum to check validity of a user configuration + */ +typedef enum { + MONO_4L_1L_0L = 0, + MONO_3L_1L_0L, + MONO_2L_1L_0L, + MONO_1L_1L_0L, + STEREO_2L_1L_2L, + STEREO_3L_1L_1L, + STEREO_2L_1L_1L, + STEREO_1L_1L_1L, + N_RX_MODE +} rx_mode_t; + +#define UNCOMPRESSED_BITS_PER_PIXEL_10 10 +#define UNCOMPRESSED_BITS_PER_PIXEL_12 12 +#define COMPRESSED_BITS_PER_PIXEL_6 6 +#define COMPRESSED_BITS_PER_PIXEL_7 7 +#define COMPRESSED_BITS_PER_PIXEL_8 8 +enum mipi_compressor { + MIPI_COMPRESSOR_NONE = 0, + MIPI_COMPRESSOR_10_6_10, + MIPI_COMPRESSOR_10_7_10, + MIPI_COMPRESSOR_10_8_10, + MIPI_COMPRESSOR_12_6_12, + MIPI_COMPRESSOR_12_7_12, + MIPI_COMPRESSOR_12_8_12, + N_MIPI_COMPRESSOR_METHODS +}; + +typedef enum mipi_compressor mipi_compressor_t; + +typedef enum { + MIPI_PREDICTOR_NONE = 0, + MIPI_PREDICTOR_TYPE1, + MIPI_PREDICTOR_TYPE2, + N_MIPI_PREDICTOR_TYPES +} mipi_predictor_t; + +typedef struct rx_cfg_s rx_cfg_t; + +/* + * Applied per port + */ +struct rx_cfg_s { + rx_mode_t mode; /* The HW config */ + enum mipi_port_id port; /* The port ID to apply the control on */ + unsigned int timeout; + unsigned int initcount; + unsigned int synccount; + unsigned int rxcount; + mipi_predictor_t comp; /* Just for backward compatibility */ + bool is_two_ppc; +}; + +#ifdef ISP2401 +# include "isp2401_input_system_local.h" +#else +# include "isp2400_input_system_local.h" +#endif diff --git a/drivers/staging/media/atomisp/pci/input_system_private.h b/drivers/staging/media/atomisp/pci/input_system_private.h new file mode 100644 index 000000000..889f204e7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_system_private.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (c) 2020 Mauro Carvalho Chehab + */ + +#ifdef ISP2401 +# include "isp2401_input_system_private.h" +#else +# include "isp2400_input_system_private.h" +#endif diff --git a/drivers/staging/media/atomisp/pci/input_system_public.h b/drivers/staging/media/atomisp/pci/input_system_public.h new file mode 100644 index 000000000..3f5167fd6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/input_system_public.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (c) 2020 Mauro Carvalho Chehab + */ + +#ifndef ISP2401 +# include "isp2400_input_system_public.h" +#endif diff --git a/drivers/staging/media/atomisp/pci/irq_controller_defs.h b/drivers/staging/media/atomisp/pci/irq_controller_defs.h new file mode 100644 index 000000000..e49e61e17 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/irq_controller_defs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _irq_controller_defs_h +#define _irq_controller_defs_h + +#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0 +#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1 +#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2 +#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3 +#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4 +#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5 +#define _HRT_IRQ_CONTROLLER_STR_OUT_ENABLE_REG_IDX 6 + +#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4 + +#endif /* _irq_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/irq_types_hrt.h b/drivers/staging/media/atomisp/pci/irq_types_hrt.h new file mode 100644 index 000000000..4212bb01c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/irq_types_hrt.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ +#define _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ + +/* + * These are the indices of each interrupt in the interrupt + * controller's registers. these can be used as the irq_id + * argument to the hrt functions irq_controller.h. + * + * The definitions are taken from _defs.h + */ +typedef enum hrt_isp_css_irq { + hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID, + hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID, + hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID, + hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID, + hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID, + hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID, + hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID, + hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID, + hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID, + hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID, + hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID, + hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID, + hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID, + hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID, + hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID, + hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID, + hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID, + hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID, + hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID, + hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID, + hrt_isp_css_irq_isp_pmem_error = HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID, + hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID, + hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID, + hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID, + hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID, + hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID, + hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID, + hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID, + hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID, + hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID, + hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID, + hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID, + /* this must (obviously) be the last on in the enum */ + hrt_isp_css_irq_num_irqs +} hrt_isp_css_irq_t; + +typedef enum hrt_isp_css_irq_status { + hrt_isp_css_irq_status_error, + hrt_isp_css_irq_status_more_irqs, + hrt_isp_css_irq_status_success +} hrt_isp_css_irq_status_t; + +#endif /* _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2.host.c new file mode 100644 index 000000000..daf2f25c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2.host.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif + +#include "ia_css_aa2.host.h" + +/* YUV Anti-Aliasing configuration. */ +const struct ia_css_aa_config default_aa_config = { + 8191 /* default should be 0 */ +}; + +/* Bayer Anti-Aliasing configuration. */ +const struct ia_css_aa_config default_baa_config = { + 8191 /* default should be 0 */ +}; diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2.host.h new file mode 100644 index 000000000..3abc125de --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2.host.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_AA_HOST_H +#define __IA_CSS_AA_HOST_H + +#include "ia_css_aa2_types.h" +#include "ia_css_aa2_param.h" + +/* YUV Anti-Aliasing configuration. */ +extern const struct ia_css_aa_config default_aa_config; + +/* Bayer Anti-Aliasing configuration. */ +extern const struct ia_css_aa_config default_baa_config; + +#endif /* __IA_CSS_AA_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2_param.h new file mode 100644 index 000000000..4f8bb4de4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2_param.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_AA_PARAM_H +#define __IA_CSS_AA_PARAM_H + +#include "type_support.h" + +struct sh_css_isp_aa_params { + s32 strength; +}; + +#endif /* __IA_CSS_AA_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2_types.h new file mode 100644 index 000000000..900ba8f5e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/aa/aa_2/ia_css_aa2_types.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_AA2_TYPES_H +#define __IA_CSS_AA2_TYPES_H + +/* @file +* CSS-API header file for Anti-Aliasing parameters. +*/ + +/* Anti-Aliasing configuration. + * + * This structure is used both for YUV AA and Bayer AA. + * + * 1. YUV Anti-Aliasing + * struct ia_css_aa_config *aa_config + * + * ISP block: AA2 + * (ISP1: AA2 is not used.) + * ISP2: AA2 should be used. But, AA2 is not used currently. + * + * 2. Bayer Anti-Aliasing + * struct ia_css_aa_config *baa_config + * + * ISP block: BAA2 + * ISP1: BAA2 is used. + * ISP2: BAA2 is used. + */ +struct ia_css_aa_config { + u16 strength; /** Strength of the filter. + u0.13, [0,8191], + default/ineffective 0 */ +}; + +#endif /* __IA_CSS_AA2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr.host.c new file mode 100644 index 000000000..3f079c954 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr.host.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_anr.host.h" + +const struct ia_css_anr_config default_anr_config = { + 10, + { + 0, 3, 1, 2, 3, 6, 4, 5, 1, 4, 2, 3, 2, 5, 3, 4, + 0, 3, 1, 2, 3, 6, 4, 5, 1, 4, 2, 3, 2, 5, 3, 4, + 0, 3, 1, 2, 3, 6, 4, 5, 1, 4, 2, 3, 2, 5, 3, 4, + 0, 3, 1, 2, 3, 6, 4, 5, 1, 4, 2, 3, 2, 5, 3, 4 + }, + {10, 20, 30} +}; + +void +ia_css_anr_encode( + struct sh_css_isp_anr_params *to, + const struct ia_css_anr_config *from, + unsigned int size) +{ + (void)size; + to->threshold = from->threshold; +} + +void +ia_css_anr_dump( + const struct sh_css_isp_anr_params *anr, + unsigned int level) +{ + if (!anr) return; + ia_css_debug_dtrace(level, "Advance Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "anr_threshold", anr->threshold); +} + +void +ia_css_anr_debug_dtrace( + const struct ia_css_anr_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.threshold=%d\n", + config->threshold); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr.host.h new file mode 100644 index 000000000..a4720c4a9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr.host.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR_HOST_H +#define __IA_CSS_ANR_HOST_H + +#include "ia_css_anr_types.h" +#include "ia_css_anr_param.h" + +extern const struct ia_css_anr_config default_anr_config; + +void +ia_css_anr_encode( + struct sh_css_isp_anr_params *to, + const struct ia_css_anr_config *from, + unsigned int size); + +void +ia_css_anr_dump( + const struct sh_css_isp_anr_params *anr, + unsigned int level); + +void +ia_css_anr_debug_dtrace( + const struct ia_css_anr_config *config, unsigned int level) +; + +#endif /* __IA_CSS_ANR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr_param.h new file mode 100644 index 000000000..37dcb013b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr_param.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR_PARAM_H +#define __IA_CSS_ANR_PARAM_H + +#include "type_support.h" + +/* ANR (Advanced Noise Reduction) */ +struct sh_css_isp_anr_params { + s32 threshold; +}; + +#endif /* __IA_CSS_ANR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr_types.h new file mode 100644 index 000000000..9b22f2da4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/ia_css_anr_types.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR_TYPES_H +#define __IA_CSS_ANR_TYPES_H + +/* @file + * CSS-API header file for Advanced Noise Reduction kernel v1 + */ + +/* Application specific DMA settings */ +#define ANR_BPP 10 +#define ANR_ELEMENT_BITS ((CEIL_DIV(ANR_BPP, 8)) * 8) + +/* Advanced Noise Reduction configuration. + * This is also known as Low-Light. + */ +struct ia_css_anr_config { + s32 threshold; /** Threshold */ + s32 thresholds[4 * 4 * 4]; + s32 factors[3]; +}; + +#endif /* __IA_CSS_ANR_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2.host.c new file mode 100644 index 000000000..9cdefedc6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2.host.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_anr2.host.h" + +void +ia_css_anr2_vmem_encode( + struct ia_css_isp_anr2_params *to, + const struct ia_css_anr_thres *from, + size_t size) +{ + unsigned int i; + + (void)size; + for (i = 0; i < ANR_PARAM_SIZE; i++) { + unsigned int j; + + for (j = 0; j < ISP_VEC_NELEMS; j++) { + to->data[i][j] = from->data[i * ISP_VEC_NELEMS + j]; + } + } +} + +void +ia_css_anr2_debug_dtrace( + const struct ia_css_anr_thres *config, + unsigned int level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2.host.h new file mode 100644 index 000000000..2b3ab01c2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2.host.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR2_HOST_H +#define __IA_CSS_ANR2_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_anr2_types.h" +#include "ia_css_anr2_param.h" +#include "ia_css_anr2_table.host.h" + +void +ia_css_anr2_vmem_encode( + struct ia_css_isp_anr2_params *to, + const struct ia_css_anr_thres *from, + size_t size); + +void +ia_css_anr2_debug_dtrace( + const struct ia_css_anr_thres *config, unsigned int level) +; + +#endif /* __IA_CSS_ANR2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_param.h new file mode 100644 index 000000000..4b83b8100 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_param.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR2_PARAM_H +#define __IA_CSS_ANR2_PARAM_H + +#include "vmem.h" +#include "ia_css_anr2_types.h" + +/* Advanced Noise Reduction (ANR) thresholds */ + +struct ia_css_isp_anr2_params { + VMEM_ARRAY(data, ANR_PARAM_SIZE * ISP_VEC_NELEMS); +}; + +#endif /* __IA_CSS_ANR2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_table.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_table.host.c new file mode 100644 index 000000000..649283bd4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_table.host.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" +#include "ia_css_types.h" +#include "ia_css_anr2_table.host.h" + +#if 1 +const struct ia_css_anr_thres default_anr_thres = { + { + 128, 384, 640, 896, 896, 640, 384, 128, 384, 1152, 1920, 2688, 2688, 1920, 1152, 384, 640, 1920, 3200, 4480, 4480, 3200, 1920, 640, 896, 2688, 4480, 6272, 6272, 4480, 2688, 896, 896, 2688, 4480, 6272, 6272, 4480, 2688, 896, 640, 1920, 3200, 4480, 4480, 3200, 1920, 640, 384, 1152, 1920, 2688, 2688, 1920, 1152, 384, 128, 384, 640, 896, 896, 640, 384, 128, + 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, + 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, + 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, + 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, + 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, + 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, + 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, + 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, + 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, + 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, + 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, + 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120 + } +}; +#else +const struct ia_css_anr_thres default_anr_thres = { + { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + } +}; +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_table.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_table.host.h new file mode 100644 index 000000000..9e383e030 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_table.host.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR2_TABLE_HOST_H +#define __IA_CSS_ANR2_TABLE_HOST_H + +#include "ia_css_anr2_types.h" + +extern const struct ia_css_anr_thres default_anr_thres; + +#endif /* __IA_CSS_ANR2_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_types.h new file mode 100644 index 000000000..e12aae819 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2_types.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR2_TYPES_H +#define __IA_CSS_ANR2_TYPES_H + +/* @file +* CSS-API header file for Advanced Noise Reduction kernel v2 +*/ + +#include "type_support.h" + +#define ANR_PARAM_SIZE 13 + +/* Advanced Noise Reduction (ANR) thresholds */ +struct ia_css_anr_thres { + s16 data[13 * 64]; +}; + +#endif /* __IA_CSS_ANR2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh.host.c new file mode 100644 index 000000000..2091f0015 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh.host.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + + +#include "ia_css_types.h" +#include "sh_css_internal.h" +#include "assert_support.h" +#include "sh_css_frac.h" + +#include "ia_css_bh.host.h" + +void +ia_css_bh_hmem_decode( + struct ia_css_3a_rgby_output *out_ptr, + const struct ia_css_bh_table *hmem_buf) +{ + int i; + + /* + * No weighted histogram, hence no grid definition + */ + if (!hmem_buf) + return; + assert(sizeof_hmem(HMEM0_ID) == sizeof(*hmem_buf)); + + /* Deinterleave */ + for (i = 0; i < HMEM_UNIT_SIZE; i++) { + out_ptr[i].r = hmem_buf->hmem[BH_COLOR_R][i]; + out_ptr[i].g = hmem_buf->hmem[BH_COLOR_G][i]; + out_ptr[i].b = hmem_buf->hmem[BH_COLOR_B][i]; + out_ptr[i].y = hmem_buf->hmem[BH_COLOR_Y][i]; + /* sh_css_print ("hmem[%d] = %d, %d, %d, %d\n", + i, out_ptr[i].r, out_ptr[i].g, out_ptr[i].b, out_ptr[i].y); */ + } +} + +void +ia_css_bh_encode( + struct sh_css_isp_bh_params *to, + const struct ia_css_3a_config *from, + unsigned int size) +{ + (void)size; + /* coefficients to calculate Y */ + to->y_coef_r = + uDIGIT_FITTING(from->ae_y_coef_r, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_g = + uDIGIT_FITTING(from->ae_y_coef_g, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_b = + uDIGIT_FITTING(from->ae_y_coef_b, 16, SH_CSS_AE_YCOEF_SHIFT); +} + diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh.host.h new file mode 100644 index 000000000..736b6e3f9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh.host.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BH_HOST_H +#define __IA_CSS_BH_HOST_H + +#include "ia_css_bh_param.h" +#include "s3a/s3a_1.0/ia_css_s3a_types.h" + +void +ia_css_bh_hmem_decode( + struct ia_css_3a_rgby_output *out_ptr, + const struct ia_css_bh_table *hmem_buf); + +void +ia_css_bh_encode( + struct sh_css_isp_bh_params *to, + const struct ia_css_3a_config *from, + unsigned int size); + +#endif /* __IA_CSS_BH_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh_param.h new file mode 100644 index 000000000..05d5c43e6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh_param.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_HB_PARAM_H +#define __IA_CSS_HB_PARAM_H + +#include "type_support.h" + +#ifndef PIPE_GENERATION +#define __INLINE_HMEM__ +#include "hmem.h" +#endif + +#include "ia_css_bh_types.h" + +/* AE (3A Support) */ +struct sh_css_isp_bh_params { + /* coefficients to calculate Y */ + s32 y_coef_r; + s32 y_coef_g; + s32 y_coef_b; +}; + +/* This should be hmem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_bh_hmem_params { + u32 bh[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE]; +}; + +#endif /* __IA_CSS_HB_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh_types.h new file mode 100644 index 000000000..4c0e92f13 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bh/bh_2/ia_css_bh_types.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BH_TYPES_H +#define __IA_CSS_BH_TYPES_H + +/* Number of elements in the BH table. + * Should be consistent with hmem.h + */ +#define IA_CSS_HMEM_BH_TABLE_SIZE ISP_HIST_DEPTH +#define IA_CSS_HMEM_BH_UNIT_SIZE (ISP_HIST_DEPTH / ISP_HIST_COMPONENTS) + +#define BH_COLOR_R (0) +#define BH_COLOR_G (1) +#define BH_COLOR_B (2) +#define BH_COLOR_Y (3) +#define BH_COLOR_NUM (4) + +/* BH table */ +struct ia_css_bh_table { + u32 hmem[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE]; +}; + +#endif /* __IA_CSS_BH_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm.host.c new file mode 100644 index 000000000..45e37dc4f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm.host.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "type_support.h" +#include "ia_css_bnlm.host.h" + +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" /* ia_css_debug_dtrace() */ +#endif +#include + +#define BNLM_DIV_LUT_SIZE (12) +static const s32 div_lut_nearests[BNLM_DIV_LUT_SIZE] = { + 0, 454, 948, 1484, 2070, 2710, 3412, 4184, 5035, 5978, 7025, 8191 +}; + +static const s32 div_lut_slopes[BNLM_DIV_LUT_SIZE] = { + -7760, -6960, -6216, -5536, -4912, -4344, -3832, -3360, -2936, -2552, -2208, -2208 + }; + +static const s32 div_lut_intercepts[BNLM_DIV_LUT_SIZE] = { + 8184, 7752, 7336, 6928, 6536, 6152, 5776, 5416, 5064, 4728, 4408, 4408 +}; + +/* Encodes a look-up table from BNLM public parameters to vmem parameters. + * Input: + * lut : bnlm_lut struct containing encoded vmem parameters look-up table + * lut_thr : array containing threshold values for lut + * lut_val : array containing output values related to lut_thr + * lut_size: Size of lut_val array + */ +static inline void +bnlm_lut_encode(struct bnlm_lut *lut, const int32_t *lut_thr, + const s32 *lut_val, const uint32_t lut_size) +{ + u32 blk, i; + const u32 block_size = 16; + const u32 total_blocks = ISP_VEC_NELEMS / block_size; + + /* Create VMEM LUTs from the threshold and value arrays. + * + * Min size of the LUT is 2 entries. + * + * Max size of the LUT is 16 entries, so that the LUT can fit into a + * single group of 16 elements inside a vector. + * Then these elements are copied into other groups inside the same + * vector. If the LUT size is less than 16, then remaining elements are + * set to 0. + */ + assert((lut_size >= 2) && (lut_size <= block_size)); + /* array lut_thr has (lut_size-1) entries */ + for (i = 0; i < lut_size - 2; i++) { + /* Check if the lut_thr is monotonically increasing */ + assert(lut_thr[i] <= lut_thr[i + 1]); + } + + /* Initialize */ + for (i = 0; i < total_blocks * block_size; i++) { + lut->thr[0][i] = 0; + lut->val[0][i] = 0; + } + + /* Copy all data */ + for (i = 0; i < lut_size - 1; i++) { + lut->thr[0][i] = lut_thr[i]; + lut->val[0][i] = lut_val[i]; + } + lut->val[0][i] = lut_val[i]; /* val has one more element than thr */ + + /* Copy data from first block to all blocks */ + for (blk = 1; blk < total_blocks; blk++) { + u32 blk_offset = blk * block_size; + + for (i = 1; i < lut_size; i++) { + lut->thr[0][blk_offset + i] = lut->thr[0][i]; + lut->val[0][blk_offset + i] = lut->val[0][i]; + } + } +} + +/* + * - Encodes BNLM public parameters into VMEM parameters + * - Generates VMEM parameters which will needed internally ISP + */ +void +ia_css_bnlm_vmem_encode( + struct bnlm_vmem_params *to, + const struct ia_css_bnlm_config *from, + size_t size) +{ + int i; + (void)size; + + /* Initialize LUTs in VMEM parameters */ + bnlm_lut_encode(&to->mu_root_lut, from->mu_root_lut_thr, from->mu_root_lut_val, + 16); + bnlm_lut_encode(&to->sad_norm_lut, from->sad_norm_lut_thr, + from->sad_norm_lut_val, 16); + bnlm_lut_encode(&to->sig_detail_lut, from->sig_detail_lut_thr, + from->sig_detail_lut_val, 16); + bnlm_lut_encode(&to->sig_rad_lut, from->sig_rad_lut_thr, from->sig_rad_lut_val, + 16); + bnlm_lut_encode(&to->rad_pow_lut, from->rad_pow_lut_thr, from->rad_pow_lut_val, + 16); + bnlm_lut_encode(&to->nl_0_lut, from->nl_0_lut_thr, from->nl_0_lut_val, 16); + bnlm_lut_encode(&to->nl_1_lut, from->nl_1_lut_thr, from->nl_1_lut_val, 16); + bnlm_lut_encode(&to->nl_2_lut, from->nl_2_lut_thr, from->nl_2_lut_val, 16); + bnlm_lut_encode(&to->nl_3_lut, from->nl_3_lut_thr, from->nl_3_lut_val, 16); + + /* Initialize arrays in VMEM parameters */ + memset(to->nl_th, 0, sizeof(to->nl_th)); + to->nl_th[0][0] = from->nl_th[0]; + to->nl_th[0][1] = from->nl_th[1]; + to->nl_th[0][2] = from->nl_th[2]; + + memset(to->match_quality_max_idx, 0, sizeof(to->match_quality_max_idx)); + to->match_quality_max_idx[0][0] = from->match_quality_max_idx[0]; + to->match_quality_max_idx[0][1] = from->match_quality_max_idx[1]; + to->match_quality_max_idx[0][2] = from->match_quality_max_idx[2]; + to->match_quality_max_idx[0][3] = from->match_quality_max_idx[3]; + + bnlm_lut_encode(&to->div_lut, div_lut_nearests, div_lut_slopes, + BNLM_DIV_LUT_SIZE); + memset(to->div_lut_intercepts, 0, sizeof(to->div_lut_intercepts)); + for (i = 0; i < BNLM_DIV_LUT_SIZE; i++) { + to->div_lut_intercepts[0][i] = div_lut_intercepts[i]; + } + + memset(to->power_of_2, 0, sizeof(to->power_of_2)); + for (i = 0; i < (ISP_VEC_ELEMBITS - 1); i++) { + to->power_of_2[0][i] = 1 << i; + } +} + +/* - Encodes BNLM public parameters into DMEM parameters */ +void +ia_css_bnlm_encode( + struct bnlm_dmem_params *to, + const struct ia_css_bnlm_config *from, + size_t size) +{ + (void)size; + to->rad_enable = from->rad_enable; + to->rad_x_origin = from->rad_x_origin; + to->rad_y_origin = from->rad_y_origin; + to->avg_min_th = from->avg_min_th; + to->max_min_th = from->max_min_th; + + to->exp_coeff_a = from->exp_coeff_a; + to->exp_coeff_b = from->exp_coeff_b; + to->exp_coeff_c = from->exp_coeff_c; + to->exp_exponent = from->exp_exponent; +} + +/* Prints debug traces for BNLM public parameters */ +void +ia_css_bnlm_debug_trace( + const struct ia_css_bnlm_config *config, + unsigned int level) +{ + if (!config) + return; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(level, "BNLM:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "rad_enable", config->rad_enable); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "rad_x_origin", + config->rad_x_origin); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "rad_y_origin", + config->rad_y_origin); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "avg_min_th", config->avg_min_th); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "max_min_th", config->max_min_th); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "exp_coeff_a", + config->exp_coeff_a); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "exp_coeff_b", + config->exp_coeff_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "exp_coeff_c", + config->exp_coeff_c); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "exp_exponent", + config->exp_exponent); + + /* ToDo: print traces for LUTs */ +#endif /* IA_CSS_NO_DEBUG */ +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm.host.h new file mode 100644 index 000000000..3632bf27c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm.host.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNLM_HOST_H +#define __IA_CSS_BNLM_HOST_H + +#include "ia_css_bnlm_types.h" +#include "ia_css_bnlm_param.h" + +void +ia_css_bnlm_vmem_encode( + struct bnlm_vmem_params *to, + const struct ia_css_bnlm_config *from, + size_t size); + +void +ia_css_bnlm_encode( + struct bnlm_dmem_params *to, + const struct ia_css_bnlm_config *from, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_bnlm_debug_trace( + const struct ia_css_bnlm_config *config, + unsigned int level); +#endif + +#endif /* __IA_CSS_BNLM_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm_param.h new file mode 100644 index 000000000..30672db26 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm_param.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNLM_PARAM_H +#define __IA_CSS_BNLM_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +struct bnlm_lut { + VMEM_ARRAY(thr, ISP_VEC_NELEMS); /* thresholds */ + VMEM_ARRAY(val, ISP_VEC_NELEMS); /* values */ +}; + +struct bnlm_vmem_params { + VMEM_ARRAY(nl_th, ISP_VEC_NELEMS); + VMEM_ARRAY(match_quality_max_idx, ISP_VEC_NELEMS); + struct bnlm_lut mu_root_lut; + struct bnlm_lut sad_norm_lut; + struct bnlm_lut sig_detail_lut; + struct bnlm_lut sig_rad_lut; + struct bnlm_lut rad_pow_lut; + struct bnlm_lut nl_0_lut; + struct bnlm_lut nl_1_lut; + struct bnlm_lut nl_2_lut; + struct bnlm_lut nl_3_lut; + + /* LUTs used for division approximiation */ + struct bnlm_lut div_lut; + + VMEM_ARRAY(div_lut_intercepts, ISP_VEC_NELEMS); + + /* 240x does not have an ISP instruction to left shift each element of a + * vector by different shift value. Hence it will be simulated by multiplying + * the elements by required 2^shift. */ + VMEM_ARRAY(power_of_2, ISP_VEC_NELEMS); +}; + +/* BNLM ISP parameters */ +struct bnlm_dmem_params { + bool rad_enable; + s32 rad_x_origin; + s32 rad_y_origin; + s32 avg_min_th; + s32 max_min_th; + + s32 exp_coeff_a; + u32 exp_coeff_b; + s32 exp_coeff_c; + u32 exp_exponent; +}; + +#endif /* __IA_CSS_BNLM_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm_types.h new file mode 100644 index 000000000..407b5a3b0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm_types.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNLM_TYPES_H +#define __IA_CSS_BNLM_TYPES_H + +/* @file +* CSS-API header file for Bayer Non-Linear Mean parameters. +*/ + +#include "type_support.h" /* int32_t */ + +/* Bayer Non-Linear Mean configuration + * + * \brief BNLM public parameters. + * \details Struct with all parameters for the BNLM kernel that can be set + * from the CSS API. + * + * ISP2.6.1: BNLM is used. + */ +struct ia_css_bnlm_config { + bool rad_enable; /** Enable a radial dependency in a weight calculation */ + s32 rad_x_origin; /** Initial x coordinate for a radius calculation */ + s32 rad_y_origin; /** Initial x coordinate for a radius calculation */ + /* a threshold for average of weights if this < Th, do not denoise pixel */ + s32 avg_min_th; + /* minimum weight for denoising if max < th, do not denoise pixel */ + s32 max_min_th; + + /**@{*/ + /* Coefficient for approximation, in the form of (1 + x / N)^N, + * that fits the first-order exp() to default exp_lut in BNLM sheet + * */ + s32 exp_coeff_a; + u32 exp_coeff_b; + s32 exp_coeff_c; + u32 exp_exponent; + /**@}*/ + + s32 nl_th[3]; /** Detail thresholds */ + + /* Index for n-th maximum candidate weight for each detail group */ + s32 match_quality_max_idx[4]; + + /**@{*/ + /* A lookup table for 1/sqrt(1+mu) approximation */ + s32 mu_root_lut_thr[15]; + s32 mu_root_lut_val[16]; + /**@}*/ + /**@{*/ + /* A lookup table for SAD normalization */ + s32 sad_norm_lut_thr[15]; + s32 sad_norm_lut_val[16]; + /**@}*/ + /**@{*/ + /* A lookup table that models a weight's dependency on textures */ + s32 sig_detail_lut_thr[15]; + s32 sig_detail_lut_val[16]; + /**@}*/ + /**@{*/ + /* A lookup table that models a weight's dependency on a pixel's radial distance */ + s32 sig_rad_lut_thr[15]; + s32 sig_rad_lut_val[16]; + /**@}*/ + /**@{*/ + /* A lookup table to control denoise power depending on a pixel's radial distance */ + s32 rad_pow_lut_thr[15]; + s32 rad_pow_lut_val[16]; + /**@}*/ + /**@{*/ + /* Non linear transfer functions to calculate the blending coefficient depending on detail group */ + /* detail group 0 */ + /**@{*/ + s32 nl_0_lut_thr[15]; + s32 nl_0_lut_val[16]; + /**@}*/ + /**@{*/ + /* detail group 1 */ + s32 nl_1_lut_thr[15]; + s32 nl_1_lut_val[16]; + /**@}*/ + /**@{*/ + /* detail group 2 */ + s32 nl_2_lut_thr[15]; + s32 nl_2_lut_val[16]; + /**@}*/ + /**@{*/ + /* detail group 3 */ + s32 nl_3_lut_thr[15]; + s32 nl_3_lut_val[16]; + /**@}*/ + /**@}*/ +}; + +#endif /* __IA_CSS_BNLM_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.c new file mode 100644 index 000000000..c42fcb1d9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "type_support.h" +#include "ia_css_bnr2_2.host.h" + +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" /* ia_css_debug_dtrace() */ +#endif + +/* Default kernel parameters. */ +const struct ia_css_bnr2_2_config default_bnr2_2_config = { + 200, + 200, + 200, + 0, + 0, + 0, + 200, + 200, + 200, + 0, + 0, + 0, + 0, + 4096, + 8191, + 128, + 1, + 0, + 0, + 0, + 8191, + 0, + 8191 +}; + +void +ia_css_bnr2_2_encode( + struct sh_css_isp_bnr2_2_params *to, + const struct ia_css_bnr2_2_config *from, + size_t size) +{ + (void)size; + to->d_var_gain_r = from->d_var_gain_r; + to->d_var_gain_g = from->d_var_gain_g; + to->d_var_gain_b = from->d_var_gain_b; + to->d_var_gain_slope_r = from->d_var_gain_slope_r; + to->d_var_gain_slope_g = from->d_var_gain_slope_g; + to->d_var_gain_slope_b = from->d_var_gain_slope_b; + + to->n_var_gain_r = from->n_var_gain_r; + to->n_var_gain_g = from->n_var_gain_g; + to->n_var_gain_b = from->n_var_gain_b; + to->n_var_gain_slope_r = from->n_var_gain_slope_r; + to->n_var_gain_slope_g = from->n_var_gain_slope_g; + to->n_var_gain_slope_b = from->n_var_gain_slope_b; + + to->dir_thres = from->dir_thres; + to->dir_thres_w = from->dir_thres_w; + to->var_offset_coef = from->var_offset_coef; + + to->dir_gain = from->dir_gain; + to->detail_gain = from->detail_gain; + to->detail_gain_divisor = from->detail_gain_divisor; + to->detail_level_offset = from->detail_level_offset; + + to->d_var_th_min = from->d_var_th_min; + to->d_var_th_max = from->d_var_th_max; + to->n_var_th_min = from->n_var_th_min; + to->n_var_th_max = from->n_var_th_max; +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_bnr2_2_debug_dtrace( + const struct ia_css_bnr2_2_config *bnr, + unsigned int level) +{ + if (!bnr) + return; + + ia_css_debug_dtrace(level, "Bayer Noise Reduction 2.2:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_r", bnr->d_var_gain_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_g", bnr->d_var_gain_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_b", bnr->d_var_gain_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_slope_r", + bnr->d_var_gain_slope_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_slope_g", + bnr->d_var_gain_slope_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_slope_b", + bnr->d_var_gain_slope_b); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_r", bnr->n_var_gain_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_g", bnr->n_var_gain_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_b", bnr->n_var_gain_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_slope_r", + bnr->n_var_gain_slope_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_slope_g", + bnr->n_var_gain_slope_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_slope_b", + bnr->n_var_gain_slope_b); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dir_thres", bnr->dir_thres); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dir_thres_w", bnr->dir_thres_w); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "var_offset_coef", + bnr->var_offset_coef); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dir_gain", bnr->dir_gain); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "detail_gain", bnr->detail_gain); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "detail_gain_divisor", + bnr->detail_gain_divisor); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "detail_level_offset", + bnr->detail_level_offset); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_th_min", bnr->d_var_th_min); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_th_max", bnr->d_var_th_max); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_th_min", bnr->n_var_th_min); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_th_max", bnr->n_var_th_max); +} +#endif /* IA_CSS_NO_DEBUG */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h new file mode 100644 index 000000000..f6ab5d2bb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __IA_CSS_BNR2_2_HOST_H +#define __IA_CSS_BNR2_2_HOST_H + +#include "ia_css_bnr2_2_types.h" +#include "ia_css_bnr2_2_param.h" + +extern const struct ia_css_bnr2_2_config default_bnr2_2_config; + +void +ia_css_bnr2_2_encode( + struct sh_css_isp_bnr2_2_params *to, + const struct ia_css_bnr2_2_config *from, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_bnr2_2_debug_dtrace( + const struct ia_css_bnr2_2_config *config, + unsigned int level); +#endif + +#endif /* __IA_CSS_BNR2_2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_param.h new file mode 100644 index 000000000..087723795 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_param.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNR2_2_PARAM_H +#define __IA_CSS_BNR2_2_PARAM_H + +#include "type_support.h" + +/* BNR (Bayer Noise Reduction) ISP parameters */ +struct sh_css_isp_bnr2_2_params { + s32 d_var_gain_r; + s32 d_var_gain_g; + s32 d_var_gain_b; + s32 d_var_gain_slope_r; + s32 d_var_gain_slope_g; + s32 d_var_gain_slope_b; + s32 n_var_gain_r; + s32 n_var_gain_g; + s32 n_var_gain_b; + s32 n_var_gain_slope_r; + s32 n_var_gain_slope_g; + s32 n_var_gain_slope_b; + s32 dir_thres; + s32 dir_thres_w; + s32 var_offset_coef; + s32 dir_gain; + s32 detail_gain; + s32 detail_gain_divisor; + s32 detail_level_offset; + s32 d_var_th_min; + s32 d_var_th_max; + s32 n_var_th_min; + s32 n_var_th_max; +}; + +#endif /* __IA_CSS_BNR2_2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h new file mode 100644 index 000000000..5f3dfa59f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNR2_2_TYPES_H +#define __IA_CSS_BNR2_2_TYPES_H + +/* @file +* CSS-API header file for Bayer Noise Reduction parameters. +*/ + +#include "type_support.h" /* int32_t */ + +/* Bayer Noise Reduction 2.2 configuration + * + * \brief BNR2_2 public parameters. + * \details Struct with all parameters for the BNR2.2 kernel that can be set + * from the CSS API. + * + * ISP2.6.1: BNR2.2 is used. + */ +struct ia_css_bnr2_2_config { + /**@{*/ + /* Directional variance gain for R/G/B components in dark region */ + s32 d_var_gain_r; + s32 d_var_gain_g; + s32 d_var_gain_b; + /**@}*/ + /**@{*/ + /* Slope of Directional variance gain between dark and bright region */ + s32 d_var_gain_slope_r; + s32 d_var_gain_slope_g; + s32 d_var_gain_slope_b; + /**@}*/ + /**@{*/ + /* Non-Directional variance gain for R/G/B components in dark region */ + s32 n_var_gain_r; + s32 n_var_gain_g; + s32 n_var_gain_b; + /**@}*/ + /**@{*/ + /* Slope of Non-Directional variance gain between dark and bright region */ + s32 n_var_gain_slope_r; + s32 n_var_gain_slope_g; + s32 n_var_gain_slope_b; + /**@}*/ + + s32 dir_thres; /** Threshold for directional filtering */ + s32 dir_thres_w; /** Threshold width for directional filtering */ + s32 var_offset_coef; /** Variance offset coefficient */ + s32 dir_gain; /** Gain for directional coefficient */ + s32 detail_gain; /** Gain for low contrast texture control */ + s32 detail_gain_divisor; /** Gain divisor for low contrast texture control */ + s32 detail_level_offset; /** Bias value for low contrast texture control */ + s32 d_var_th_min; /** Minimum clipping value for directional variance*/ + s32 d_var_th_max; /** Maximum clipping value for diretional variance*/ + s32 n_var_th_min; /** Minimum clipping value for non-directional variance*/ + s32 n_var_th_max; /** Maximum clipping value for non-directional variance*/ +}; + +#endif /* __IA_CSS_BNR2_2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.c new file mode 100644 index 000000000..457a004e1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "ia_css_bnr.host.h" + +void +ia_css_bnr_encode( + struct sh_css_isp_bnr_params *to, + const struct ia_css_nr_config *from, + unsigned int size) +{ + (void)size; + /* BNR (Bayer Noise Reduction) */ + to->threshold_low = + uDIGIT_FITTING(from->direction, 16, SH_CSS_BAYER_BITS); + to->threshold_width_log2 = uFRACTION_BITS_FITTING(8); + to->threshold_width = + 1 << to->threshold_width_log2; + to->gain_all = + uDIGIT_FITTING(from->bnr_gain, 16, SH_CSS_BNR_GAIN_SHIFT); + to->gain_dir = + uDIGIT_FITTING(from->bnr_gain, 16, SH_CSS_BNR_GAIN_SHIFT); + to->clip = uDIGIT_FITTING(16384U, 16, SH_CSS_BAYER_BITS); +} + +void +ia_css_bnr_dump( + const struct sh_css_isp_bnr_params *bnr, + unsigned int level) +{ + if (!bnr) return; + ia_css_debug_dtrace(level, "Bayer Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_gain_all", bnr->gain_all); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_gain_dir", bnr->gain_dir); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_threshold_low", + bnr->threshold_low); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_threshold_width_log2", + bnr->threshold_width_log2); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_threshold_width", + bnr->threshold_width); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_clip", bnr->clip); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h new file mode 100644 index 000000000..7fc2a728a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNR_HOST_H +#define __IA_CSS_BNR_HOST_H + +#include "sh_css_params.h" + +#include "ynr/ynr_1.0/ia_css_ynr_types.h" +#include "ia_css_bnr_param.h" + +void +ia_css_bnr_encode( + struct sh_css_isp_bnr_params *to, + const struct ia_css_nr_config *from, + unsigned int size); + +void +ia_css_bnr_dump( + const struct sh_css_isp_bnr_params *bnr, + unsigned int level); + +#endif /* __IA_CSS_DP_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr_param.h new file mode 100644 index 000000000..4f6469315 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr_1.0/ia_css_bnr_param.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNR_PARAM_H +#define __IA_CSS_BNR_PARAM_H + +#include "type_support.h" + +/* BNR (Bayer Noise Reduction) */ +struct sh_css_isp_bnr_params { + s32 gain_all; + s32 gain_dir; + s32 threshold_low; + s32 threshold_width_log2; + s32 threshold_width; + s32 clip; +}; + +#endif /* __IA_CSS_BNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.c new file mode 100644 index 000000000..0eb40517e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_cnr.host.h" + +/* keep the interface here, it is not enabled yet because host doesn't know the size of individual state */ +void +ia_css_init_cnr_state( + void/*struct sh_css_isp_cnr_vmem_state*/ * state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h new file mode 100644 index 000000000..4d046b730 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR_HOST_H +#define __IA_CSS_CNR_HOST_H + +#include "ia_css_cnr_param.h" + +void +ia_css_init_cnr_state( + void/*struct sh_css_isp_cnr_vmem_state*/ * state, + size_t size); + +#endif /* __IA_CSS_CNR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr_param.h new file mode 100644 index 000000000..971ab87af --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_1.0/ia_css_cnr_param.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR_PARAM_H +#define __IA_CSS_CNR_PARAM_H + +#include "type_support.h" + +/* CNR (Chroma Noise Reduction) */ +/* Reuse YNR1 param structure */ +#include "../../ynr/ynr_1.0/ia_css_ynr_param.h" + +#endif /* __IA_CSS_CNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.c new file mode 100644 index 000000000..495dc1f33 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_cnr2.host.h" + +const struct ia_css_cnr_config default_cnr_config = { + 0, + 0, + 100, + 100, + 100, + 50, + 50, + 50 +}; + +void +ia_css_cnr_encode( + struct sh_css_isp_cnr_params *to, + const struct ia_css_cnr_config *from, + unsigned int size) +{ + (void)size; + to->coring_u = from->coring_u; + to->coring_v = from->coring_v; + to->sense_gain_vy = from->sense_gain_vy; + to->sense_gain_vu = from->sense_gain_vu; + to->sense_gain_vv = from->sense_gain_vv; + to->sense_gain_hy = from->sense_gain_hy; + to->sense_gain_hu = from->sense_gain_hu; + to->sense_gain_hv = from->sense_gain_hv; +} + +void +ia_css_cnr_dump( + const struct sh_css_isp_cnr_params *cnr, + unsigned int level); + +void +ia_css_cnr_debug_dtrace( + const struct ia_css_cnr_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.coring_u=%d, config.coring_v=%d, config.sense_gain_vy=%d, config.sense_gain_hy=%d, config.sense_gain_vu=%d, config.sense_gain_hu=%d, config.sense_gain_vv=%d, config.sense_gain_hv=%d\n", + config->coring_u, config->coring_v, + config->sense_gain_vy, config->sense_gain_hy, + config->sense_gain_vu, config->sense_gain_hu, + config->sense_gain_vv, config->sense_gain_hv); +} + +void +ia_css_init_cnr2_state( + void/*struct sh_css_isp_cnr_vmem_state*/ * state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h new file mode 100644 index 000000000..38f848137 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR2_HOST_H +#define __IA_CSS_CNR2_HOST_H + +#include "ia_css_cnr2_types.h" +#include "ia_css_cnr2_param.h" + +extern const struct ia_css_cnr_config default_cnr_config; + +void +ia_css_cnr_encode( + struct sh_css_isp_cnr_params *to, + const struct ia_css_cnr_config *from, + unsigned int size); + +void +ia_css_cnr_dump( + const struct sh_css_isp_cnr_params *cnr, + unsigned int level); + +void +ia_css_cnr_debug_dtrace( + const struct ia_css_cnr_config *config, + unsigned int level); + +void +ia_css_init_cnr2_state( + void/*struct sh_css_isp_cnr_vmem_state*/ * state, + size_t size); +#endif /* __IA_CSS_CNR2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2_param.h new file mode 100644 index 000000000..3709aa4d3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2_param.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR2_PARAM_H +#define __IA_CSS_CNR2_PARAM_H + +#include "type_support.h" + +/* CNR (Chroma Noise Reduction) */ +struct sh_css_isp_cnr_params { + s32 coring_u; + s32 coring_v; + s32 sense_gain_vy; + s32 sense_gain_vu; + s32 sense_gain_vv; + s32 sense_gain_hy; + s32 sense_gain_hu; + s32 sense_gain_hv; +}; + +#endif /* __IA_CSS_CNR2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h new file mode 100644 index 000000000..d0a256167 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR2_TYPES_H +#define __IA_CSS_CNR2_TYPES_H + +/* @file +* CSS-API header file for Chroma Noise Reduction (CNR) parameters +*/ + +/* Chroma Noise Reduction configuration. + * + * Small sensitivity of edge means strong smoothness and NR performance. + * If you see blurred color on vertical edges, + * set higher values on sense_gain_h*. + * If you see blurred color on horizontal edges, + * set higher values on sense_gain_v*. + * + * ISP block: CNR2 + * (ISP1: CNR1 is used.) + * (ISP2: CNR1 is used for Preview/Video.) + * ISP2: CNR2 is used for Still. + */ +struct ia_css_cnr_config { + u16 coring_u; /** Coring level of U. + u0.13, [0,8191], default/ineffective 0 */ + u16 coring_v; /** Coring level of V. + u0.13, [0,8191], default/ineffective 0 */ + u16 sense_gain_vy; /** Sensitivity of horizontal edge of Y. + u13.0, [0,8191], default 100, ineffective 8191 */ + u16 sense_gain_vu; /** Sensitivity of horizontal edge of U. + u13.0, [0,8191], default 100, ineffective 8191 */ + u16 sense_gain_vv; /** Sensitivity of horizontal edge of V. + u13.0, [0,8191], default 100, ineffective 8191 */ + u16 sense_gain_hy; /** Sensitivity of vertical edge of Y. + u13.0, [0,8191], default 50, ineffective 8191 */ + u16 sense_gain_hu; /** Sensitivity of vertical edge of U. + u13.0, [0,8191], default 50, ineffective 8191 */ + u16 sense_gain_hv; /** Sensitivity of vertical edge of V. + u13.0, [0,8191], default 50, ineffective 8191 */ +}; + +#endif /* __IA_CSS_CNR2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.c new file mode 100644 index 000000000..ff452e2cc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "ia_css_conversion.host.h" + +const struct ia_css_conversion_config default_conversion_config = { + 0, + 0, + 0, + 0, +}; + +void +ia_css_conversion_encode( + struct sh_css_isp_conversion_params *to, + const struct ia_css_conversion_config *from, + unsigned int size) +{ + (void)size; + to->en = from->en; + to->dummy0 = from->dummy0; + to->dummy1 = from->dummy1; + to->dummy2 = from->dummy2; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h new file mode 100644 index 000000000..520623e27 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CONVERSION_HOST_H +#define __IA_CSS_CONVERSION_HOST_H + +#include "ia_css_conversion_types.h" +#include "ia_css_conversion_param.h" + +extern const struct ia_css_conversion_config default_conversion_config; + +void +ia_css_conversion_encode( + struct sh_css_isp_conversion_params *to, + const struct ia_css_conversion_config *from, + unsigned int size); + +#endif /* __IA_CSS_CONVERSION_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion_param.h new file mode 100644 index 000000000..fcbec189e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion_param.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CONVERSION_PARAM_H +#define __IA_CSS_CONVERSION_PARAM_H + +#include "type_support.h" + +/* CONVERSION */ +struct sh_css_isp_conversion_params { + u32 en; + u32 dummy0; + u32 dummy1; + u32 dummy2; +}; + +#endif /* __IA_CSS_CONVERSION_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h new file mode 100644 index 000000000..34152d6d0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CONVERSION_TYPES_H +#define __IA_CSS_CONVERSION_TYPES_H + +/** + * Conversion Kernel parameters. + * Deinterleave bayer quad into isys format + * + * ISP block: CONVERSION + * + */ +struct ia_css_conversion_config { + u32 en; /** en parameter */ + u32 dummy0; /** dummy0 dummy parameter 0 */ + u32 dummy1; /** dummy1 dummy parameter 1 */ + u32 dummy2; /** dummy2 dummy parameter 2 */ +}; + +#endif /* __IA_CSS_CONVERSION_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.c new file mode 100644 index 000000000..cc415c72a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_copy_output.host.h" +#include "ia_css_binary.h" +#include "type_support.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" + +static const struct ia_css_copy_output_configuration default_config = { + .enable = false, +}; + +void +ia_css_copy_output_config( + struct sh_css_isp_copy_output_isp_config *to, + const struct ia_css_copy_output_configuration *from, + unsigned int size) +{ + (void)size; + to->enable = from->enable; +} + +int ia_css_copy_output_configure(const struct ia_css_binary *binary, + bool enable) +{ + struct ia_css_copy_output_configuration config = default_config; + + config.enable = enable; + + return ia_css_configure_copy_output(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h new file mode 100644 index 000000000..44e3e45b0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_COPY_OUTPUT_HOST_H +#define __IA_CSS_COPY_OUTPUT_HOST_H + +#include "type_support.h" +#include "ia_css_binary.h" + +#include "ia_css_copy_output_param.h" + +void +ia_css_copy_output_config( + struct sh_css_isp_copy_output_isp_config *to, + const struct ia_css_copy_output_configuration *from, + unsigned int size); + +int ia_css_copy_output_configure(const struct ia_css_binary *binary, + bool enable); + +#endif /* __IA_CSS_COPY_OUTPUT_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output_param.h new file mode 100644 index 000000000..56daa1d96 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output_param.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_COPY_PARAM_H +#define __IA_CSS_COPY_PARAM_H + +struct ia_css_copy_output_configuration { + bool enable; +}; + +struct sh_css_isp_copy_output_isp_config { + u32 enable; +}; + +#endif /* __IA_CSS_COPY_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop.host.c new file mode 100644 index 000000000..8c1d50f7a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop.host.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" +#include "ia_css_crop.host.h" + +static const struct ia_css_crop_configuration default_config = { + .info = (struct ia_css_frame_info *)NULL, +}; + +void +ia_css_crop_encode( + struct sh_css_isp_crop_isp_params *to, + const struct ia_css_crop_config *from, + unsigned int size) +{ + (void)size; + to->crop_pos = from->crop_pos; +} + +int ia_css_crop_config(struct sh_css_isp_crop_isp_config *to, + const struct ia_css_crop_configuration *from, + unsigned int size) +{ + unsigned int elems_a = ISP_VEC_NELEMS; + int ret; + + ret = ia_css_dma_configure_from_info(&to->port_b, from->info); + if (ret) + return ret; + + to->width_a_over_b = elems_a / to->port_b.elems; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + if (elems_a % to->port_b.elems != 0) + return -EINVAL; + + return 0; +} + +int ia_css_crop_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + struct ia_css_crop_configuration config = default_config; + + config.info = info; + + return ia_css_configure_crop(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop.host.h new file mode 100644 index 000000000..e700149c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop.host.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CROP_HOST_H +#define __IA_CSS_CROP_HOST_H + +#include +#include + +#include "ia_css_crop_types.h" +#include "ia_css_crop_param.h" + +void +ia_css_crop_encode( + struct sh_css_isp_crop_isp_params *to, + const struct ia_css_crop_config *from, + unsigned int size); + +int ia_css_crop_config(struct sh_css_isp_crop_isp_config *to, + const struct ia_css_crop_configuration *from, + unsigned int size); + +int ia_css_crop_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +#endif /* __IA_CSS_CROP_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop_param.h new file mode 100644 index 000000000..7416e74dd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop_param.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CROP_PARAM_H +#define __IA_CSS_CROP_PARAM_H + +#include +#include "dma.h" +#include "sh_css_internal.h" /* sh_css_crop_pos */ + +/* Crop frame */ +struct sh_css_isp_crop_isp_config { + u32 width_a_over_b; + struct dma_port_config port_b; +}; + +struct sh_css_isp_crop_isp_params { + struct sh_css_crop_pos crop_pos; +}; + +#endif /* __IA_CSS_CROP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop_types.h new file mode 100644 index 000000000..aaaae5e2a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/crop/crop_1.0/ia_css_crop_types.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CROP_TYPES_H +#define __IA_CSS_CROP_TYPES_H + +/* Crop frame + * + * ISP block: crop frame + */ + +#include +#include "sh_css_uds.h" /* sh_css_crop_pos */ + +struct ia_css_crop_config { + struct sh_css_crop_pos crop_pos; +}; + +struct ia_css_crop_configuration { + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_CROP_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc.host.c new file mode 100644 index 000000000..284c17970 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc.host.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif + +#include "ia_css_csc.host.h" + +const struct ia_css_cc_config default_cc_config = { + 8, + {255, 29, 120, 0, -374, -342, 0, -672, 301}, +}; + +void +ia_css_encode_cc( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned int size) +{ + (void)size; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_encode_cc() enter:\n"); +#endif + + to->m_shift = (int16_t)from->fraction_bits; + to->m00 = (int16_t)from->matrix[0]; + to->m01 = (int16_t)from->matrix[1]; + to->m02 = (int16_t)from->matrix[2]; + to->m10 = (int16_t)from->matrix[3]; + to->m11 = (int16_t)from->matrix[4]; + to->m12 = (int16_t)from->matrix[5]; + to->m20 = (int16_t)from->matrix[6]; + to->m21 = (int16_t)from->matrix[7]; + to->m22 = (int16_t)from->matrix[8]; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_encode_cc() leave:\n"); +#endif +} + +void +ia_css_csc_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned int size) +{ + ia_css_encode_cc(to, from, size); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_cc_dump( + const struct sh_css_isp_csc_params *csc, + unsigned int level, + const char *name) +{ + if (!csc) return; + ia_css_debug_dtrace(level, "%s\n", name); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m_shift", + csc->m_shift); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m00", + csc->m00); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m01", + csc->m01); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m02", + csc->m02); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m10", + csc->m10); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m11", + csc->m11); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m12", + csc->m12); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m20", + csc->m20); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m21", + csc->m21); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m22", + csc->m22); +} + +void +ia_css_csc_dump( + const struct sh_css_isp_csc_params *csc, + unsigned int level) +{ + ia_css_cc_dump(csc, level, "Color Space Conversion"); +} + +void +ia_css_cc_config_debug_dtrace( + const struct ia_css_cc_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.m[0]=%d, config.m[1]=%d, config.m[2]=%d, config.m[3]=%d, config.m[4]=%d, config.m[5]=%d, config.m[6]=%d, config.m[7]=%d, config.m[8]=%d\n", + config->matrix[0], + config->matrix[1], config->matrix[2], + config->matrix[3], config->matrix[4], + config->matrix[5], config->matrix[6], + config->matrix[7], config->matrix[8]); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc.host.h new file mode 100644 index 000000000..6b0256a73 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc.host.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CSC_HOST_H +#define __IA_CSS_CSC_HOST_H + +#include "ia_css_csc_types.h" +#include "ia_css_csc_param.h" + +extern const struct ia_css_cc_config default_cc_config; + +void +ia_css_encode_cc( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned int size); + +void +ia_css_csc_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned int size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_cc_dump( + const struct sh_css_isp_csc_params *csc, unsigned int level, + const char *name); + +void +ia_css_csc_dump( + const struct sh_css_isp_csc_params *csc, + unsigned int level); + +void +ia_css_cc_config_debug_dtrace( + const struct ia_css_cc_config *config, + unsigned int level); + +#define ia_css_csc_debug_dtrace ia_css_cc_config_debug_dtrace +#endif + +#endif /* __IA_CSS_CSC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc_param.h new file mode 100644 index 000000000..3809ef73e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc_param.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CSC_PARAM_H +#define __IA_CSS_CSC_PARAM_H + +#include "type_support.h" +/* CSC (Color Space Conversion) */ +struct sh_css_isp_csc_params { + u16 m_shift; + s16 m00; + s16 m01; + s16 m02; + s16 m10; + s16 m11; + s16 m12; + s16 m20; + s16 m21; + s16 m22; +}; + +#endif /* __IA_CSS_CSC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc_types.h new file mode 100644 index 000000000..160f19bdf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/ia_css_csc_types.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CSC_TYPES_H +#define __IA_CSS_CSC_TYPES_H + +/* @file +* CSS-API header file for Color Space Conversion parameters. +*/ + +/* Color Correction configuration. + * + * This structure is used for 3 cases. + * ("YCgCo" is the output format of Demosaic.) + * + * 1. Color Space Conversion (YCgCo to YUV) for ISP1. + * ISP block: CSC1 (Color Space Conversion) + * struct ia_css_cc_config *cc_config + * + * 2. Color Correction Matrix (YCgCo to RGB) for ISP2. + * ISP block: CCM2 (Color Correction Matrix) + * struct ia_css_cc_config *yuv2rgb_cc_config + * + * 3. Color Space Conversion (RGB to YUV) for ISP2. + * ISP block: CSC2 (Color Space Conversion) + * struct ia_css_cc_config *rgb2yuv_cc_config + * + * default/ineffective: + * 1. YCgCo -> YUV + * 1 0.174 0.185 + * 0 -0.66252 -0.66874 + * 0 -0.83738 0.58131 + * + * fraction_bits = 12 + * 4096 713 758 + * 0 -2714 -2739 + * 0 -3430 2381 + * + * 2. YCgCo -> RGB + * 1 -1 1 + * 1 1 0 + * 1 -1 -1 + * + * fraction_bits = 12 + * 4096 -4096 4096 + * 4096 4096 0 + * 4096 -4096 -4096 + * + * 3. RGB -> YUV + * 0.299 0.587 0.114 + * -0.16874 -0.33126 0.5 + * 0.5 -0.41869 -0.08131 + * + * fraction_bits = 13 + * 2449 4809 934 + * -1382 -2714 4096 + * 4096 -3430 -666 + */ +struct ia_css_cc_config { + u32 fraction_bits;/** Fractional bits of matrix. + u8.0, [0,13] */ + s32 matrix[3 * 3]; /** Conversion matrix. + s[13-fraction_bits].[fraction_bits], + [-8192,8191] */ +}; + +#endif /* __IA_CSS_CSC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.c new file mode 100644 index 000000000..149adbc57 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +#include "ctc/ctc_1.0/ia_css_ctc.host.h" +#include "ia_css_ctc1_5.host.h" + +static void ctc_gradient( + int *dydx, int *shift, + int y1, int y0, int x1, int x0) +{ + int frc_bits = max(IA_CSS_CTC_COEF_SHIFT, 16); + int dy = y1 - y0; + int dx = x1 - x0; + int dydx_int; + int dydx_frc; + int sft; + /* max_dydx = the maxinum gradient = the maximum y (gain) */ + int max_dydx = (1 << IA_CSS_CTC_COEF_SHIFT) - 1; + + if (dx == 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ctc_gradient() error, illegal division operation\n"); + return; + } else { + dydx_int = dy / dx; + dydx_frc = ((dy - dydx_int * dx) << frc_bits) / dx; + } + + assert(y0 >= 0 && y0 <= max_dydx); + assert(y1 >= 0 && y1 <= max_dydx); + assert(x0 < x1); + assert(dydx); + assert(shift); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ctc_gradient() enter:\n"); + + /* search "sft" which meets this condition: + (1 << (IA_CSS_CTC_COEF_SHIFT - 1)) + <= (((float)dy / (float)dx) * (1 << sft)) + <= ((1 << IA_CSS_CTC_COEF_SHIFT) - 1) */ + for (sft = 0; sft <= IA_CSS_CTC_COEF_SHIFT; sft++) { + int tmp_dydx = (dydx_int << sft) + + (dydx_frc >> (frc_bits - sft)); + if (tmp_dydx <= max_dydx) { + *dydx = tmp_dydx; + *shift = sft; + } + if (tmp_dydx >= max_dydx) + break; + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ctc_gradient() leave:\n"); +} + +void +ia_css_ctc_encode( + struct sh_css_isp_ctc_params *to, + const struct ia_css_ctc_config *from, + unsigned int size) +{ + (void)size; + to->y0 = from->y0; + to->y1 = from->y1; + to->y2 = from->y2; + to->y3 = from->y3; + to->y4 = from->y4; + to->y5 = from->y5; + + to->ce_gain_exp = from->ce_gain_exp; + + to->x1 = from->x1; + to->x2 = from->x2; + to->x3 = from->x3; + to->x4 = from->x4; + + ctc_gradient(&to->dydx0, + &to->dydx0_shift, + from->y1, from->y0, + from->x1, 0); + + ctc_gradient(&to->dydx1, + &to->dydx1_shift, + from->y2, from->y1, + from->x2, from->x1); + + ctc_gradient(&to->dydx2, + &to->dydx2_shift, + from->y3, from->y2, + from->x3, from->x2); + + ctc_gradient(&to->dydx3, + &to->dydx3_shift, + from->y4, from->y3, + from->x4, from->x3); + + ctc_gradient(&to->dydx4, + &to->dydx4_shift, + from->y5, from->y4, + SH_CSS_BAYER_MAXVAL, from->x4); +} + +void +ia_css_ctc_dump( + const struct sh_css_isp_ctc_params *ctc, + unsigned int level); diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h new file mode 100644 index 000000000..8c17e7b92 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC1_5_HOST_H +#define __IA_CSS_CTC1_5_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_ctc1_5_param.h" + +void +ia_css_ctc_encode( + struct sh_css_isp_ctc_params *to, + const struct ia_css_ctc_config *from, + unsigned int size); + +void +ia_css_ctc_dump( + const struct sh_css_isp_ctc_params *ctc, + unsigned int level); + +#endif /* __IA_CSS_CTC1_5_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5_param.h new file mode 100644 index 000000000..c18cfc930 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5_param.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC1_5_PARAM_H +#define __IA_CSS_CTC1_5_PARAM_H + +#include "type_support.h" +#include "ctc/ctc_1.0/ia_css_ctc_param.h" /* vamem params */ + +/* CTC (Color Tone Control) */ +struct sh_css_isp_ctc_params { + s32 y0; + s32 y1; + s32 y2; + s32 y3; + s32 y4; + s32 y5; + s32 ce_gain_exp; + s32 x1; + s32 x2; + s32 x3; + s32 x4; + s32 dydx0; + s32 dydx0_shift; + s32 dydx1; + s32 dydx1_shift; + s32 dydx2; + s32 dydx2_shift; + s32 dydx3; + s32 dydx3_shift; + s32 dydx4; + s32 dydx4_shift; +}; + +#endif /* __IA_CSS_CTC1_5_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2.host.c new file mode 100644 index 000000000..e3d3f1253 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2.host.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "assert_support.h" + +#include "ia_css_ctc2.host.h" + +#define INEFFECTIVE_VAL 4096 +#define BASIC_VAL 819 + +/*Default configuration of parameters for Ctc2*/ +const struct ia_css_ctc2_config default_ctc2_config = { + INEFFECTIVE_VAL, INEFFECTIVE_VAL, INEFFECTIVE_VAL, + INEFFECTIVE_VAL, INEFFECTIVE_VAL, INEFFECTIVE_VAL, + BASIC_VAL * 2, BASIC_VAL * 4, BASIC_VAL * 6, + BASIC_VAL * 8, INEFFECTIVE_VAL, INEFFECTIVE_VAL, + BASIC_VAL >> 1, BASIC_VAL +}; + +/* (dydx) = ctc2_slope(y1, y0, x1, x0) + * ----------------------------------------------- + * Calculation of the Slope of a Line = ((y1 - y0) >> 8)/(x1 - x0) + * + * Note: y1, y0 , x1 & x0 must lie within the range 0 <-> 8191 + */ +static int ctc2_slope(int y1, int y0, int x1, int x0) +{ + const int shift_val = 8; + const int max_slope = (1 << IA_CSS_CTC_COEF_SHIFT) - 1; + int dy = y1 - y0; + int dx = x1 - x0; + int rounding = (dx + 1) >> 1; + int dy_shift = dy << shift_val; + int slope, dydx; + + /*Protection for parameter values, & avoiding zero divisions*/ + assert(y0 >= 0 && y0 <= max_slope); + assert(y1 >= 0 && y1 <= max_slope); + assert(x0 >= 0 && x0 <= max_slope); + assert(x1 > 0 && x1 <= max_slope); + assert(dx > 0); + + if (dy < 0) + rounding = -rounding; + slope = (int)(dy_shift + rounding) / dx; + + /*the slope must lie within the range + (-max_slope-1) >= (dydx) >= (max_slope) + */ + if (slope <= -max_slope - 1) { + dydx = -max_slope - 1; + } else if (slope >= max_slope) { + dydx = max_slope; + } else { + dydx = slope; + } + + return dydx; +} + +/* (void) = ia_css_ctc2_vmem_encode(*to, *from) + * ----------------------------------------------- + * VMEM Encode Function to translate Y parameters from userspace into ISP space + */ +void ia_css_ctc2_vmem_encode(struct ia_css_isp_ctc2_vmem_params *to, + const struct ia_css_ctc2_config *from, + size_t size) +{ + unsigned int i, j; + const unsigned int shffl_blck = 4; + const unsigned int length_zeros = 11; + short dydx0, dydx1, dydx2, dydx3, dydx4; + + (void)size; + /* + * Calculation of slopes of lines interconnecting + * 0.0 -> y_x1 -> y_x2 -> y _x3 -> y_x4 -> 1.0 + */ + dydx0 = ctc2_slope(from->y_y1, from->y_y0, + from->y_x1, 0); + dydx1 = ctc2_slope(from->y_y2, from->y_y1, + from->y_x2, from->y_x1); + dydx2 = ctc2_slope(from->y_y3, from->y_y2, + from->y_x3, from->y_x2); + dydx3 = ctc2_slope(from->y_y4, from->y_y3, + from->y_x4, from->y_x3); + dydx4 = ctc2_slope(from->y_y5, from->y_y4, + SH_CSS_BAYER_MAXVAL, from->y_x4); + + /*Fill 3 arrays with: + * - Luma input gain values y_y0, y_y1, y_y2, y_3, y_y4 + * - Luma kneepoints 0, y_x1, y_x2, y_x3, y_x4 + * - Calculated slopes dydx0, dyxd1, dydx2, dydx3, dydx4 + * + * - Each 64-element array is divided in blocks of 16 elements: + * the 5 parameters + zeros in the remaining 11 positions + * - All blocks of the same array will contain the same data + */ + for (i = 0; i < shffl_blck; i++) { + to->y_x[0][(i << shffl_blck)] = 0; + to->y_x[0][(i << shffl_blck) + 1] = from->y_x1; + to->y_x[0][(i << shffl_blck) + 2] = from->y_x2; + to->y_x[0][(i << shffl_blck) + 3] = from->y_x3; + to->y_x[0][(i << shffl_blck) + 4] = from->y_x4; + + to->y_y[0][(i << shffl_blck)] = from->y_y0; + to->y_y[0][(i << shffl_blck) + 1] = from->y_y1; + to->y_y[0][(i << shffl_blck) + 2] = from->y_y2; + to->y_y[0][(i << shffl_blck) + 3] = from->y_y3; + to->y_y[0][(i << shffl_blck) + 4] = from->y_y4; + + to->e_y_slope[0][(i << shffl_blck)] = dydx0; + to->e_y_slope[0][(i << shffl_blck) + 1] = dydx1; + to->e_y_slope[0][(i << shffl_blck) + 2] = dydx2; + to->e_y_slope[0][(i << shffl_blck) + 3] = dydx3; + to->e_y_slope[0][(i << shffl_blck) + 4] = dydx4; + + for (j = 0; j < length_zeros; j++) { + to->y_x[0][(i << shffl_blck) + 5 + j] = 0; + to->y_y[0][(i << shffl_blck) + 5 + j] = 0; + to->e_y_slope[0][(i << shffl_blck) + 5 + j] = 0; + } + } +} + +/* (void) = ia_css_ctc2_encode(*to, *from) + * ----------------------------------------------- + * DMEM Encode Function to translate UV parameters from userspace into ISP space + */ +void ia_css_ctc2_encode(struct ia_css_isp_ctc2_dmem_params *to, + struct ia_css_ctc2_config *from, + size_t size) +{ + (void)size; + + to->uv_y0 = from->uv_y0; + to->uv_y1 = from->uv_y1; + to->uv_x0 = from->uv_x0; + to->uv_x1 = from->uv_x1; + + /*Slope Calculation*/ + to->uv_dydx = ctc2_slope(from->uv_y1, from->uv_y0, + from->uv_x1, from->uv_x0); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2.host.h new file mode 100644 index 000000000..eb10c3884 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2.host.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC2_HOST_H +#define __IA_CSS_CTC2_HOST_H + +#include "ia_css_ctc2_param.h" +#include "ia_css_ctc2_types.h" + +extern const struct ia_css_ctc2_config default_ctc2_config; + +/*Encode Functions to translate parameters from userspace into ISP space*/ + +void ia_css_ctc2_vmem_encode(struct ia_css_isp_ctc2_vmem_params *to, + const struct ia_css_ctc2_config *from, + size_t size); + +void ia_css_ctc2_encode(struct ia_css_isp_ctc2_dmem_params *to, + struct ia_css_ctc2_config *from, + size_t size); + +#endif /* __IA_CSS_CTC2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h new file mode 100644 index 000000000..94844da66 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC2_PARAM_H +#define __IA_CSS_CTC2_PARAM_H + +#define IA_CSS_CTC_COEF_SHIFT 13 +#include "vmem.h" /* needed for VMEM_ARRAY */ + +/* CTC (Chroma Tone Control)ISP Parameters */ + +/*VMEM Luma params*/ +struct ia_css_isp_ctc2_vmem_params { + /** Gains by Y(Luma) at Y = 0.0,Y_X1, Y_X2, Y_X3, Y_X4*/ + VMEM_ARRAY(y_x, ISP_VEC_NELEMS); + /* kneepoints by Y(Luma) 0.0, y_x1, y_x2, y _x3, y_x4*/ + VMEM_ARRAY(y_y, ISP_VEC_NELEMS); + /* Slopes of lines interconnecting + * 0.0 -> y_x1 -> y_x2 -> y _x3 -> y_x4 -> 1.0*/ + VMEM_ARRAY(e_y_slope, ISP_VEC_NELEMS); +}; + +/*DMEM Chroma params*/ +struct ia_css_isp_ctc2_dmem_params { + /* Gains by UV(Chroma) under kneepoints uv_x0 and uv_x1*/ + s32 uv_y0; + s32 uv_y1; + + /* Kneepoints by UV(Chroma)- uv_x0 and uv_x1*/ + s32 uv_x0; + s32 uv_x1; + + /* Slope of line interconnecting uv_x0 -> uv_x1*/ + s32 uv_dydx; + +}; +#endif /* __IA_CSS_CTC2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h new file mode 100644 index 000000000..f9f329a58 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC2_TYPES_H +#define __IA_CSS_CTC2_TYPES_H + +/* Chroma Tone Control configuration. +* +* ISP block: CTC2 (CTC by polygonal approximation) +* (ISP1: CTC1 (CTC by look-up table) is used.) +* ISP2: CTC2 is used. +* ISP261: CTC2 (CTC by Fast Approximate Distance) +*/ +struct ia_css_ctc2_config { + /** Gains by Y(Luma) at Y =0.0,Y_X1, Y_X2, Y_X3, Y_X4 and Y_X5 + * --default/ineffective value: 4096(0.5f) + */ + s32 y_y0; + s32 y_y1; + s32 y_y2; + s32 y_y3; + s32 y_y4; + s32 y_y5; + /* 1st-4th kneepoints by Y(Luma) --default/ineffective value:n/a + * requirement: 0.0 < y_x1 < y_x2 ctc, &from->data, sizeof(to->ctc)); +} + +void +ia_css_ctc_debug_dtrace( + const struct ia_css_ctc_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.ce_gain_exp=%d, config.y0=%d, config.x1=%d, config.y1=%d, config.x2=%d, config.y2=%d, config.x3=%d, config.y3=%d, config.x4=%d, config.y4=%d\n", + config->ce_gain_exp, config->y0, + config->x1, config->y1, + config->x2, config->y2, + config->x3, config->y3, + config->x4, config->y4); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h new file mode 100644 index 000000000..57d1d08e1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC_HOST_H +#define __IA_CSS_CTC_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_ctc_param.h" +#include "ia_css_ctc_table.host.h" + +extern const struct ia_css_ctc_config default_ctc_config; + +void +ia_css_ctc_vamem_encode( + struct sh_css_isp_ctc_vamem_params *to, + const struct ia_css_ctc_table *from, + unsigned int size); + +void +ia_css_ctc_debug_dtrace( + const struct ia_css_ctc_config *config, unsigned int level) +; + +#endif /* __IA_CSS_CTC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_param.h new file mode 100644 index 000000000..eaad708c6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_param.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC_PARAM_H +#define __IA_CSS_CTC_PARAM_H + +#include "type_support.h" +#include + +#include "ia_css_ctc_types.h" + +#ifndef PIPE_GENERATION +#define SH_CSS_ISP_CTC_TABLE_SIZE_LOG2 IA_CSS_VAMEM_2_CTC_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_CTC_TABLE_SIZE IA_CSS_VAMEM_2_CTC_TABLE_SIZE + +#else +/* For pipe generation, the size is not relevant */ +#define SH_CSS_ISP_CTC_TABLE_SIZE 0 +#endif + +/* This should be vamem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_ctc_vamem_params { + u16 ctc[SH_CSS_ISP_CTC_TABLE_SIZE]; +}; + +#endif /* __IA_CSS_CTC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.c new file mode 100644 index 000000000..6a7925c84 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for memcpy() */ + +#include +#include "system_global.h" +#include "vamem.h" +#include "ia_css_types.h" +#include "ia_css_ctc_table.host.h" + +struct ia_css_ctc_table default_ctc_table; + + +static const uint16_t +default_ctc_table_data[IA_CSS_VAMEM_2_CTC_TABLE_SIZE] = { + 0, 384, 837, 957, 1011, 1062, 1083, 1080, + 1078, 1077, 1053, 1039, 1012, 992, 969, 951, + 929, 906, 886, 866, 845, 823, 809, 790, + 772, 758, 741, 726, 711, 701, 688, 675, + 666, 656, 648, 639, 633, 626, 618, 612, + 603, 594, 582, 572, 557, 545, 529, 516, + 504, 491, 480, 467, 459, 447, 438, 429, + 419, 412, 404, 397, 389, 382, 376, 368, + 363, 357, 351, 345, 340, 336, 330, 326, + 321, 318, 312, 308, 304, 300, 297, 294, + 291, 286, 284, 281, 278, 275, 271, 268, + 261, 257, 251, 245, 240, 235, 232, 225, + 223, 218, 213, 209, 206, 204, 199, 197, + 193, 189, 186, 185, 183, 179, 177, 175, + 172, 170, 169, 167, 164, 164, 162, 160, + 158, 157, 156, 154, 154, 152, 151, 150, + 149, 148, 146, 147, 146, 144, 143, 143, + 142, 141, 140, 141, 139, 138, 138, 138, + 137, 136, 136, 135, 134, 134, 134, 133, + 132, 132, 131, 130, 131, 130, 129, 128, + 129, 127, 127, 127, 127, 125, 125, 125, + 123, 123, 122, 120, 118, 115, 114, 111, + 110, 108, 106, 105, 103, 102, 100, 99, + 97, 97, 96, 95, 94, 93, 93, 91, + 91, 91, 90, 90, 89, 89, 88, 88, + 89, 88, 88, 87, 87, 87, 87, 86, + 87, 87, 86, 87, 86, 86, 84, 84, + 82, 80, 78, 76, 74, 72, 70, 68, + 67, 65, 62, 60, 58, 56, 55, 54, + 53, 51, 49, 49, 47, 45, 45, 45, + 41, 40, 39, 39, 34, 33, 34, 32, + 25, 23, 24, 20, 13, 9, 12, 0, + 0 +}; + + +void +ia_css_config_ctc_table(void) +{ + memcpy(default_ctc_table.data.vamem_2, default_ctc_table_data, + sizeof(default_ctc_table_data)); + default_ctc_table.vamem_type = IA_CSS_VAMEM_TYPE_2; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.h new file mode 100644 index 000000000..33e8a0545 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC_TABLE_HOST_H +#define __IA_CSS_CTC_TABLE_HOST_H + +#include "ia_css_ctc_types.h" + +extern struct ia_css_ctc_table default_ctc_table; + +void ia_css_config_ctc_table(void); + +#endif /* __IA_CSS_CTC_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h new file mode 100644 index 000000000..b2d42f3c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC_TYPES_H +#define __IA_CSS_CTC_TYPES_H + +#include + +/* @file +* CSS-API header file for Chroma Tone Control parameters. +*/ + +/* Fractional bits for CTC gain (used only for ISP1). + * + * IA_CSS_CTC_COEF_SHIFT(=13) includes not only the fractional bits + * of gain(=8), but also the bits(=5) to convert chroma + * from 13bit precision to 8bit precision. + * + * Gain (struct ia_css_ctc_table) : u5.8 + * Input(Chorma) : s0.12 (13bit precision) + * Output(Chorma): s0.7 (8bit precision) + * Output = (Input * Gain) >> IA_CSS_CTC_COEF_SHIFT + */ +#define IA_CSS_CTC_COEF_SHIFT 13 + +/* Number of elements in the CTC table. */ +#define IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2 10 +/* Number of elements in the CTC table. */ +#define IA_CSS_VAMEM_1_CTC_TABLE_SIZE BIT(IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2) + +/* Number of elements in the CTC table. */ +#define IA_CSS_VAMEM_2_CTC_TABLE_SIZE_LOG2 8 +/* Number of elements in the CTC table. */ +#define IA_CSS_VAMEM_2_CTC_TABLE_SIZE ((1U << IA_CSS_VAMEM_2_CTC_TABLE_SIZE_LOG2) + 1) + +enum ia_css_vamem_type { + IA_CSS_VAMEM_TYPE_1, + IA_CSS_VAMEM_TYPE_2 +}; + +/* Chroma Tone Control configuration. + * + * ISP block: CTC2 (CTC by polygonal line approximation) + * (ISP1: CTC1 (CTC by look-up table) is used.) + * ISP2: CTC2 is used. + */ +struct ia_css_ctc_config { + u16 y0; /** 1st kneepoint gain. + u[ce_gain_exp].[13-ce_gain_exp], [0,8191], + default/ineffective 4096(0.5) */ + u16 y1; /** 2nd kneepoint gain. + u[ce_gain_exp].[13-ce_gain_exp], [0,8191], + default/ineffective 4096(0.5) */ + u16 y2; /** 3rd kneepoint gain. + u[ce_gain_exp].[13-ce_gain_exp], [0,8191], + default/ineffective 4096(0.5) */ + u16 y3; /** 4th kneepoint gain. + u[ce_gain_exp].[13-ce_gain_exp], [0,8191], + default/ineffective 4096(0.5) */ + u16 y4; /** 5th kneepoint gain. + u[ce_gain_exp].[13-ce_gain_exp], [0,8191], + default/ineffective 4096(0.5) */ + u16 y5; /** 6th kneepoint gain. + u[ce_gain_exp].[13-ce_gain_exp], [0,8191], + default/ineffective 4096(0.5) */ + u16 ce_gain_exp; /** Common exponent of y-axis gain. + u8.0, [0,13], + default/ineffective 1 */ + u16 x1; /** 2nd kneepoint luma. + u0.13, [0,8191], constraints: 0pixelnoise = + uDIGIT_FITTING(from->pixelnoise, 16, SH_CSS_BAYER_BITS); + to->c1_coring_threshold = + uDIGIT_FITTING(from->c1_coring_threshold, 16, + SH_CSS_BAYER_BITS); + to->c2_coring_threshold = + uDIGIT_FITTING(from->c2_coring_threshold, 16, + SH_CSS_BAYER_BITS); +} + +void +ia_css_de_dump( + const struct sh_css_isp_de_params *de, + unsigned int level) +{ + if (!de) return; + ia_css_debug_dtrace(level, "Demosaic:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "de_pixelnoise", de->pixelnoise); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "de_c1_coring_threshold", + de->c1_coring_threshold); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "de_c2_coring_threshold", + de->c2_coring_threshold); +} + +void +ia_css_de_debug_dtrace( + const struct ia_css_de_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.pixelnoise=%d, config.c1_coring_threshold=%d, config.c2_coring_threshold=%d\n", + config->pixelnoise, + config->c1_coring_threshold, config->c2_coring_threshold); +} + +void +ia_css_init_de_state( + void/*struct sh_css_isp_de_vmem_state*/ * state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de.host.h new file mode 100644 index 000000000..cb9106202 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de.host.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE_HOST_H +#define __IA_CSS_DE_HOST_H + +#include "ia_css_de_types.h" +#include "ia_css_de_param.h" + +extern const struct ia_css_de_config default_de_config; + +void +ia_css_de_encode( + struct sh_css_isp_de_params *to, + const struct ia_css_de_config *from, + unsigned int size); + +void +ia_css_de_dump( + const struct sh_css_isp_de_params *de, + unsigned int level); + +void +ia_css_de_debug_dtrace( + const struct ia_css_de_config *config, + unsigned int level); + +void +ia_css_init_de_state( + void/*struct sh_css_isp_de_vmem_state*/ * state, + size_t size); + +#endif /* __IA_CSS_DE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de_param.h new file mode 100644 index 000000000..2070ce040 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de_param.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE_PARAM_H +#define __IA_CSS_DE_PARAM_H + +#include "type_support.h" + +/* DE (Demosaic) */ +struct sh_css_isp_de_params { + s32 pixelnoise; + s32 c1_coring_threshold; + s32 c2_coring_threshold; +}; + +#endif /* __IA_CSS_DE_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de_types.h new file mode 100644 index 000000000..daac1275c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_1.0/ia_css_de_types.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE_TYPES_H +#define __IA_CSS_DE_TYPES_H + +/* @file +* CSS-API header file for Demosaic (bayer-to-YCgCo) parameters. +*/ + +/* Demosaic (bayer-to-YCgCo) configuration. + * + * ISP block: DE1 + * ISP1: DE1 is used. + * (ISP2: DE2 is used.) + */ +struct ia_css_de_config { + ia_css_u0_16 pixelnoise; /** Pixel noise used in moire elimination. + u0.16, [0,65535], + default 0, ineffective 0 */ + ia_css_u0_16 c1_coring_threshold; /** Coring threshold for C1. + This is the same as nr_config.threshold_cb. + u0.16, [0,65535], + default 128(0.001953125), ineffective 0 */ + ia_css_u0_16 c2_coring_threshold; /** Coring threshold for C2. + This is the same as nr_config.threshold_cr. + u0.16, [0,65535], + default 128(0.001953125), ineffective 0 */ +}; + +#endif /* __IA_CSS_DE_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2.host.c new file mode 100644 index 000000000..f90da3929 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2.host.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_de2.host.h" + +const struct ia_css_ecd_config default_ecd_config = { + (1 << (ISP_VEC_ELEMBITS - 1)) * 2 / 3, /* 2/3 */ + (1 << (ISP_VEC_ELEMBITS - 1)) - 1, /* 1.0 */ + 0, /* 0.0 */ +}; + +void +ia_css_ecd_encode( + struct sh_css_isp_ecd_params *to, + const struct ia_css_ecd_config *from, + unsigned int size) +{ + (void)size; + to->zip_strength = from->zip_strength; + to->fc_strength = from->fc_strength; + to->fc_debias = from->fc_debias; +} + +void +ia_css_ecd_dump( + const struct sh_css_isp_ecd_params *ecd, + unsigned int level); + +void +ia_css_ecd_debug_dtrace( + const struct ia_css_ecd_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.zip_strength=%d, config.fc_strength=%d, config.fc_debias=%d\n", + config->zip_strength, + config->fc_strength, config->fc_debias); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2.host.h new file mode 100644 index 000000000..294f619a3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2.host.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE2_HOST_H +#define __IA_CSS_DE2_HOST_H + +#include "ia_css_de2_types.h" +#include "ia_css_de2_param.h" + +extern const struct ia_css_ecd_config default_ecd_config; + +void +ia_css_ecd_encode( + struct sh_css_isp_ecd_params *to, + const struct ia_css_ecd_config *from, + unsigned int size); + +void +ia_css_ecd_dump( + const struct sh_css_isp_ecd_params *ecd, + unsigned int level); + +void +ia_css_ecd_debug_dtrace( + const struct ia_css_ecd_config *config, unsigned int level); + +#endif /* __IA_CSS_DE2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2_param.h new file mode 100644 index 000000000..4c9d5c630 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2_param.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE2_PARAM_H +#define __IA_CSS_DE2_PARAM_H + +#include "type_support.h" + +/* Reuse DE1 params and extend them */ +#include "../de_1.0/ia_css_de_param.h" + +/* DE (Demosaic) */ +struct sh_css_isp_ecd_params { + s32 zip_strength; + s32 fc_strength; + s32 fc_debias; +}; + +#endif /* __IA_CSS_DE2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2_types.h new file mode 100644 index 000000000..372cd9d2b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/de/de_2/ia_css_de2_types.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE2_TYPES_H +#define __IA_CSS_DE2_TYPES_H + +/* @file +* CSS-API header file for Demosaicing parameters. +*/ + +/* Eigen Color Demosaicing configuration. + * + * ISP block: DE2 + * (ISP1: DE1 is used.) + * ISP2: DE2 is used. + */ +struct ia_css_ecd_config { + u16 zip_strength; /** Strength of zipper reduction. + u0.13, [0,8191], + default 5489(0.67), ineffective 0 */ + u16 fc_strength; /** Strength of false color reduction. + u0.13, [0,8191], + default 8191(almost 1.0), ineffective 0 */ + u16 fc_debias; /** Prevent color change + on noise or Gr/Gb imbalance. + u0.13, [0,8191], + default 0, ineffective 0 */ +}; + +#endif /* __IA_CSS_DE2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp.host.c new file mode 100644 index 000000000..eff428c67 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp.host.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "ia_css_dp.host.h" + +/* We use a different set of DPC configuration parameters when + * DPC is used before OBC and NORM. Currently these parameters + * are used in usecases which selects both BDS and DPC. + **/ +const struct ia_css_dp_config default_dp_10bpp_config = { + 1024, + 2048, + 32768, + 32768, + 32768, + 32768 +}; + +const struct ia_css_dp_config default_dp_config = { + 8192, + 2048, + 32768, + 32768, + 32768, + 32768 +}; + +void +ia_css_dp_encode( + struct sh_css_isp_dp_params *to, + const struct ia_css_dp_config *from, + unsigned int size) +{ + int gain = from->gain; + int gr = from->gr; + int r = from->r; + int b = from->b; + int gb = from->gb; + + (void)size; + to->threshold_single = + SH_CSS_BAYER_MAXVAL; + to->threshold_2adjacent = + uDIGIT_FITTING(from->threshold, 16, SH_CSS_BAYER_BITS); + to->gain = + uDIGIT_FITTING(from->gain, 8, SH_CSS_DP_GAIN_SHIFT); + + to->coef_rr_gr = + uDIGIT_FITTING(gain * gr / r, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_rr_gb = + uDIGIT_FITTING(gain * gb / r, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_bb_gb = + uDIGIT_FITTING(gain * gb / b, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_bb_gr = + uDIGIT_FITTING(gain * gr / b, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_gr_rr = + uDIGIT_FITTING(gain * r / gr, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_gr_bb = + uDIGIT_FITTING(gain * b / gr, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_gb_bb = + uDIGIT_FITTING(gain * b / gb, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_gb_rr = + uDIGIT_FITTING(gain * r / gb, 8, SH_CSS_DP_GAIN_SHIFT); +} + +void +ia_css_dp_dump( + const struct sh_css_isp_dp_params *dp, + unsigned int level) +{ + if (!dp) return; + ia_css_debug_dtrace(level, "Defect Pixel Correction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dp_threshold_single_w_2adj_on", + dp->threshold_single); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dp_threshold_2adj_w_2adj_on", + dp->threshold_2adjacent); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dp_gain", dp->gain); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_rr_gr", dp->coef_rr_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_rr_gb", dp->coef_rr_gb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_bb_gb", dp->coef_bb_gb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_bb_gr", dp->coef_bb_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_gr_rr", dp->coef_gr_rr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_gr_bb", dp->coef_gr_bb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_gb_bb", dp->coef_gb_bb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_gb_rr", dp->coef_gb_rr); +} + +void +ia_css_dp_debug_dtrace( + const struct ia_css_dp_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.threshold=%d, config.gain=%d\n", + config->threshold, config->gain); +} + +void +ia_css_init_dp_state( + void/*struct sh_css_isp_dp_vmem_state*/ * state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp.host.h new file mode 100644 index 000000000..e5f5a2716 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp.host.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DP_HOST_H +#define __IA_CSS_DP_HOST_H + +#include "ia_css_dp_types.h" +#include "ia_css_dp_param.h" + +extern const struct ia_css_dp_config default_dp_config; + +/* ISP2401 */ +extern const struct ia_css_dp_config default_dp_10bpp_config; + +void +ia_css_dp_encode( + struct sh_css_isp_dp_params *to, + const struct ia_css_dp_config *from, + unsigned int size); + +void +ia_css_dp_dump( + const struct sh_css_isp_dp_params *dp, + unsigned int level); + +void +ia_css_dp_debug_dtrace( + const struct ia_css_dp_config *config, + unsigned int level); + +void +ia_css_init_dp_state( + void/*struct sh_css_isp_dp_vmem_state*/ * state, + size_t size); + +#endif /* __IA_CSS_DP_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp_param.h new file mode 100644 index 000000000..e0e7f2d48 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp_param.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DP_PARAM_H +#define __IA_CSS_DP_PARAM_H + +#include "type_support.h" +#include "bnr/bnr_1.0/ia_css_bnr_param.h" + +/* DP (Defect Pixel Correction) */ +struct sh_css_isp_dp_params { + s32 threshold_single; + s32 threshold_2adjacent; + s32 gain; + s32 coef_rr_gr; + s32 coef_rr_gb; + s32 coef_bb_gb; + s32 coef_bb_gr; + s32 coef_gr_rr; + s32 coef_gr_bb; + s32 coef_gb_bb; + s32 coef_gb_rr; +}; + +#endif /* __IA_CSS_DP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp_types.h new file mode 100644 index 000000000..c1666ebf1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ia_css_dp_types.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DP_TYPES_H +#define __IA_CSS_DP_TYPES_H + +/* @file +* CSS-API header file for Defect Pixel Correction (DPC) parameters. +*/ + +/* Defect Pixel Correction configuration. + * + * ISP block: DPC1 (DPC after WB) + * DPC2 (DPC before WB) + * ISP1: DPC1 is used. + * ISP2: DPC2 is used. + */ +struct ia_css_dp_config { + ia_css_u0_16 threshold; /** The threshold of defect pixel correction, + representing the permissible difference of + intensity between one pixel and its + surrounding pixels. Smaller values result + in more frequent pixel corrections. + u0.16, [0,65535], + default 8192, ineffective 65535 */ + ia_css_u8_8 gain; /** The sensitivity of mis-correction. ISP will + miss a lot of defects if the value is set + too large. + u8.8, [0,65535], + default 4096, ineffective 65535 */ + u32 gr; /* unsigned .<16-integer_bits> */ + u32 r; /* unsigned .<16-integer_bits> */ + u32 b; /* unsigned .<16-integer_bits> */ + u32 gb; /* unsigned .<16-integer_bits> */ +}; + +#endif /* __IA_CSS_DP_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2.host.c new file mode 100644 index 000000000..f6fe064bd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2.host.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_dpc2.host.h" +#include "assert_support.h" + +void +ia_css_dpc2_encode( + struct ia_css_isp_dpc2_params *to, + const struct ia_css_dpc2_config *from, + size_t size) +{ + (void)size; + + assert((from->metric1 >= 0) && (from->metric1 <= METRIC1_ONE_FP)); + assert((from->metric3 >= 0) && (from->metric3 <= METRIC3_ONE_FP)); + assert((from->metric2 >= METRIC2_ONE_FP) && + (from->metric2 < 256 * METRIC2_ONE_FP)); + assert((from->wb_gain_gr > 0) && (from->wb_gain_gr < 16 * WBGAIN_ONE_FP)); + assert((from->wb_gain_r > 0) && (from->wb_gain_r < 16 * WBGAIN_ONE_FP)); + assert((from->wb_gain_b > 0) && (from->wb_gain_b < 16 * WBGAIN_ONE_FP)); + assert((from->wb_gain_gb > 0) && (from->wb_gain_gb < 16 * WBGAIN_ONE_FP)); + + to->metric1 = from->metric1; + to->metric2 = from->metric2; + to->metric3 = from->metric3; + + to->wb_gain_gr = from->wb_gain_gr; + to->wb_gain_r = from->wb_gain_r; + to->wb_gain_b = from->wb_gain_b; + to->wb_gain_gb = from->wb_gain_gb; +} + +/* TODO: AM: This needs a proper implementation. */ +void +ia_css_init_dpc2_state( + void *state, + size_t size) +{ + (void)state; + (void)size; +} + +#ifndef IA_CSS_NO_DEBUG +/* TODO: AM: This needs a proper implementation. */ +void +ia_css_dpc2_debug_dtrace( + const struct ia_css_dpc2_config *config, + unsigned int level) +{ + (void)config; + (void)level; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2.host.h new file mode 100644 index 000000000..f6e019a65 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2.host.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DPC2_HOST_H +#define __IA_CSS_DPC2_HOST_H + +#include "ia_css_dpc2_types.h" +#include "ia_css_dpc2_param.h" + +void +ia_css_dpc2_encode( + struct ia_css_isp_dpc2_params *to, + const struct ia_css_dpc2_config *from, + size_t size); + +void +ia_css_init_dpc2_state( + void *state, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_dpc2_debug_dtrace( + const struct ia_css_dpc2_config *config, + unsigned int level); +#endif + +#endif /* __IA_CSS_DPC2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2_param.h new file mode 100644 index 000000000..1ccceadbb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2_param.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DPC2_PARAM_H +#define __IA_CSS_DPC2_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* for VMEM_ARRAY*/ + +/* 4 planes : GR, R, B, GB */ +#define NUM_PLANES 4 + +/* ToDo: Move this to testsetup */ +#define MAX_FRAME_SIMDWIDTH 30 + +/* 3 lines state per color plane input_line_state */ +#define DPC2_STATE_INPUT_BUFFER_HEIGHT (3 * NUM_PLANES) +/* Each plane has width equal to half frame line */ +#define DPC2_STATE_INPUT_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line state per color plane for local deviation state*/ +#define DPC2_STATE_LOCAL_DEVIATION_BUFFER_HEIGHT (1 * NUM_PLANES) +/* Each plane has width equal to half frame line */ +#define DPC2_STATE_LOCAL_DEVIATION_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* MINMAX state buffer stores 1 full input line (GR-R color line) */ +#define DPC2_STATE_SECOND_MINMAX_BUFFER_HEIGHT 1 +#define DPC2_STATE_SECOND_MINMAX_BUFFER_WIDTH MAX_FRAME_SIMDWIDTH + +struct ia_css_isp_dpc2_params { + s32 metric1; + s32 metric2; + s32 metric3; + s32 wb_gain_gr; + s32 wb_gain_r; + s32 wb_gain_b; + s32 wb_gain_gb; +}; + +#endif /* __IA_CSS_DPC2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2_types.h new file mode 100644 index 000000000..f742a8dc1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/ia_css_dpc2_types.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DPC2_TYPES_H +#define __IA_CSS_DPC2_TYPES_H + +/* @file +* CSS-API header file for Defect Pixel Correction 2 (DPC2) parameters. +*/ + +#include "type_support.h" + +/**@{*/ +/* Floating point constants for different metrics. */ +#define METRIC1_ONE_FP BIT(12) +#define METRIC2_ONE_FP BIT(5) +#define METRIC3_ONE_FP BIT(12) +#define WBGAIN_ONE_FP BIT(9) +/**@}*/ + +/**@{*/ +/* Defect Pixel Correction 2 configuration. + * + * \brief DPC2 public parameters. + * \details Struct with all parameters for the Defect Pixel Correction 2 + * kernel that can be set from the CSS API. + * + * ISP block: DPC1 (DPC after WB) + * DPC2 (DPC before WB) + * ISP1: DPC1 is used. + * ISP2: DPC2 is used. + * + */ +struct ia_css_dpc2_config { + /**@{*/ + s32 metric1; + s32 metric2; + s32 metric3; + s32 wb_gain_gr; + s32 wb_gain_r; + s32 wb_gain_b; + s32 wb_gain_gb; + /**@}*/ +}; + +/**@}*/ + +#endif /* __IA_CSS_DPC2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.c new file mode 100644 index 000000000..07ce5b4f0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.c @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include "ia_css_frame_public.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" + +#include "ia_css_types.h" +#include "ia_css_host_data.h" +#include "sh_css_param_dvs.h" +#include "sh_css_params.h" +#include "ia_css_binary.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +#include "ia_css_dvs.host.h" + +static const struct ia_css_dvs_configuration default_config = { + .info = (struct ia_css_frame_info *)NULL, +}; + +void +ia_css_dvs_config( + struct sh_css_isp_dvs_isp_config *to, + const struct ia_css_dvs_configuration *from, + unsigned int size) +{ + (void)size; + to->num_horizontal_blocks = + DVS_NUM_BLOCKS_X(from->info->res.width); + to->num_vertical_blocks = + DVS_NUM_BLOCKS_Y(from->info->res.height); +} + +int ia_css_dvs_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + struct ia_css_dvs_configuration config = default_config; + + config.info = info; + + return ia_css_configure_dvs(binary, &config); +} + +static void +convert_coords_to_ispparams( + struct ia_css_host_data *gdc_warp_table, + const struct ia_css_dvs_6axis_config *config, + unsigned int i_stride, + unsigned int o_width, + unsigned int o_height, + unsigned int uv_flag) +{ + unsigned int i, j; + gdc_warp_param_mem_t s = { 0 }; + unsigned int x00, x01, x10, x11, + y00, y01, y10, y11; + + unsigned int xmin, ymin, xmax, ymax; + unsigned int topleft_x, topleft_y, bottom_x, bottom_y, + topleft_x_frac, topleft_y_frac; + unsigned int dvs_interp_envelope = (DVS_GDC_INTERP_METHOD == HRT_GDC_BLI_MODE ? + DVS_GDC_BLI_INTERP_ENVELOPE : DVS_GDC_BCI_INTERP_ENVELOPE); + + /* number of blocks per height and width */ + unsigned int num_blocks_y = (uv_flag ? DVS_NUM_BLOCKS_Y_CHROMA( + o_height) : DVS_NUM_BLOCKS_Y(o_height)); + unsigned int num_blocks_x = (uv_flag ? DVS_NUM_BLOCKS_X_CHROMA( + o_width) : DVS_NUM_BLOCKS_X( + o_width)); // round num_x up to blockdim_x, if it concerns the Y0Y1 block (uv_flag==0) round up to even + + unsigned int in_stride = i_stride * DVS_INPUT_BYTES_PER_PIXEL; + unsigned int width, height; + unsigned int *xbuff = NULL; + unsigned int *ybuff = NULL; + struct gdc_warp_param_mem_s *ptr; + + assert(config); + assert(gdc_warp_table); + assert(gdc_warp_table->address); + + ptr = (struct gdc_warp_param_mem_s *)gdc_warp_table->address; + + ptr += (2 * uv_flag); /* format is Y0 Y1 UV, so UV starts at 3rd position */ + + if (uv_flag == 0) { + xbuff = config->xcoords_y; + ybuff = config->ycoords_y; + width = config->width_y; + height = config->height_y; + } else { + xbuff = config->xcoords_uv; + ybuff = config->ycoords_uv; + width = config->width_uv; + height = config->height_uv; + } + + IA_CSS_LOG("blockdim_x %d blockdim_y %d", + DVS_BLOCKDIM_X, DVS_BLOCKDIM_Y_LUMA >> uv_flag); + IA_CSS_LOG("num_blocks_x %d num_blocks_y %d", num_blocks_x, num_blocks_y); + IA_CSS_LOG("width %d height %d", width, height); + + assert(width == num_blocks_x + + 1); // the width and height of the provided morphing table should be 1 more than the number of blocks + assert(height == num_blocks_y + 1); + + for (j = 0; j < num_blocks_y; j++) { + for (i = 0; i < num_blocks_x; i++) { + x00 = xbuff[j * width + i]; + x01 = xbuff[j * width + (i + 1)]; + x10 = xbuff[(j + 1) * width + i]; + x11 = xbuff[(j + 1) * width + (i + 1)]; + + y00 = ybuff[j * width + i]; + y01 = ybuff[j * width + (i + 1)]; + y10 = ybuff[(j + 1) * width + i]; + y11 = ybuff[(j + 1) * width + (i + 1)]; + + xmin = min(x00, x10); + xmax = max(x01, x11); + ymin = min(y00, y01); + ymax = max(y10, y11); + + /* Assert that right column's X is greater */ + assert(x01 >= xmin); + assert(x11 >= xmin); + /* Assert that bottom row's Y is greater */ + assert(y10 >= ymin); + assert(y11 >= ymin); + + topleft_y = ymin >> DVS_COORD_FRAC_BITS; + topleft_x = ((xmin >> DVS_COORD_FRAC_BITS) + >> XMEM_ALIGN_LOG2) + << (XMEM_ALIGN_LOG2); + s.in_addr_offset = topleft_y * in_stride + topleft_x; + + /* similar to topleft_y calculation, but round up if ymax + * has any fraction bits */ + bottom_y = CEIL_DIV(ymax, 1 << DVS_COORD_FRAC_BITS); + s.in_block_height = bottom_y - topleft_y + dvs_interp_envelope; + + bottom_x = CEIL_DIV(xmax, 1 << DVS_COORD_FRAC_BITS); + s.in_block_width = bottom_x - topleft_x + dvs_interp_envelope; + + topleft_x_frac = topleft_x << (DVS_COORD_FRAC_BITS); + topleft_y_frac = topleft_y << (DVS_COORD_FRAC_BITS); + + s.p0_x = x00 - topleft_x_frac; + s.p1_x = x01 - topleft_x_frac; + s.p2_x = x10 - topleft_x_frac; + s.p3_x = x11 - topleft_x_frac; + + s.p0_y = y00 - topleft_y_frac; + s.p1_y = y01 - topleft_y_frac; + s.p2_y = y10 - topleft_y_frac; + s.p3_y = y11 - topleft_y_frac; + + // block should fit within the boundingbox. + assert(s.p0_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); + assert(s.p1_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); + assert(s.p2_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); + assert(s.p3_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); + assert(s.p0_y < (s.in_block_height << DVS_COORD_FRAC_BITS)); + assert(s.p1_y < (s.in_block_height << DVS_COORD_FRAC_BITS)); + assert(s.p2_y < (s.in_block_height << DVS_COORD_FRAC_BITS)); + assert(s.p3_y < (s.in_block_height << DVS_COORD_FRAC_BITS)); + + // block size should be greater than zero. + assert(s.p0_x < s.p1_x); + assert(s.p2_x < s.p3_x); + assert(s.p0_y < s.p2_y); + assert(s.p1_y < s.p3_y); + +#if 0 + printf("j: %d\ti:%d\n", j, i); + printf("offset: %d\n", s.in_addr_offset); + printf("p0_x: %d\n", s.p0_x); + printf("p0_y: %d\n", s.p0_y); + printf("p1_x: %d\n", s.p1_x); + printf("p1_y: %d\n", s.p1_y); + printf("p2_x: %d\n", s.p2_x); + printf("p2_y: %d\n", s.p2_y); + printf("p3_x: %d\n", s.p3_x); + printf("p3_y: %d\n", s.p3_y); + + printf("p0_x_nofrac[0]: %d\n", s.p0_x >> DVS_COORD_FRAC_BITS); + printf("p0_y_nofrac[1]: %d\n", s.p0_y >> DVS_COORD_FRAC_BITS); + printf("p1_x_nofrac[2]: %d\n", s.p1_x >> DVS_COORD_FRAC_BITS); + printf("p1_y_nofrac[3]: %d\n", s.p1_y >> DVS_COORD_FRAC_BITS); + printf("p2_x_nofrac[0]: %d\n", s.p2_x >> DVS_COORD_FRAC_BITS); + printf("p2_y_nofrac[1]: %d\n", s.p2_y >> DVS_COORD_FRAC_BITS); + printf("p3_x_nofrac[2]: %d\n", s.p3_x >> DVS_COORD_FRAC_BITS); + printf("p3_y_nofrac[3]: %d\n", s.p3_y >> DVS_COORD_FRAC_BITS); + printf("\n"); +#endif + + *ptr = s; + + // storage format: + // Y0 Y1 UV0 Y2 Y3 UV1 + /* if uv_flag equals true increment with 2 incase x is odd, this to + skip the uv position. */ + if (uv_flag) + ptr += 3; + else + ptr += (1 + (i & 1)); + } + } +} + +struct ia_css_host_data * +convert_allocate_dvs_6axis_config( + const struct ia_css_dvs_6axis_config *dvs_6axis_config, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *dvs_in_frame_info) +{ + unsigned int i_stride; + unsigned int o_width; + unsigned int o_height; + struct ia_css_host_data *me; + + assert(binary); + assert(dvs_6axis_config); + assert(dvs_in_frame_info); + + me = ia_css_host_data_allocate((size_t)((DVS_6AXIS_BYTES(binary) / 2) * 3)); + + if (!me) + return NULL; + + /*DVS only supports input frame of YUV420 or NV12. Fail for all other cases*/ + assert((dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_NV12) + || (dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_YUV420)); + + i_stride = dvs_in_frame_info->padded_width; + + o_width = binary->out_frame_info[0].res.width; + o_height = binary->out_frame_info[0].res.height; + + /* Y plane */ + convert_coords_to_ispparams(me, dvs_6axis_config, + i_stride, o_width, o_height, 0); + + if (dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_YUV420) { + /*YUV420 has half the stride for U/V plane*/ + i_stride /= 2; + } + + /* UV plane (packed inside the y plane) */ + convert_coords_to_ispparams(me, dvs_6axis_config, + i_stride, o_width / 2, o_height / 2, 1); + + return me; +} + +int +store_dvs_6axis_config( + const struct ia_css_dvs_6axis_config *dvs_6axis_config, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *dvs_in_frame_info, + ia_css_ptr ddr_addr_y) { + struct ia_css_host_data *me; + + assert(dvs_6axis_config); + assert(ddr_addr_y != mmgr_NULL); + assert(dvs_in_frame_info); + + me = convert_allocate_dvs_6axis_config(dvs_6axis_config, + binary, + dvs_in_frame_info); + + if (!me) + { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + + ia_css_params_store_ia_css_host_data( + ddr_addr_y, + me); + ia_css_host_data_free(me); + + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h new file mode 100644 index 000000000..332aa5496 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DVS_HOST_H +#define __IA_CSS_DVS_HOST_H + +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" +#include "sh_css_params.h" + +#include "ia_css_types.h" +#include "ia_css_dvs_types.h" +#include "ia_css_dvs_param.h" + +/* For bilinear interpolation, we need to add +1 to input block height calculation. + * For bicubic interpolation, we will need to add +3 instaed */ +#define DVS_GDC_BLI_INTERP_ENVELOPE 1 +#define DVS_GDC_BCI_INTERP_ENVELOPE 3 + +void +ia_css_dvs_config( + struct sh_css_isp_dvs_isp_config *to, + const struct ia_css_dvs_configuration *from, + unsigned int size); + +int ia_css_dvs_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +void +convert_dvs_6axis_config( + struct ia_css_isp_parameters *params, + const struct ia_css_binary *binary); + +struct ia_css_host_data * +convert_allocate_dvs_6axis_config( + const struct ia_css_dvs_6axis_config *dvs_6axis_config, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *dvs_in_frame_info); + +int +store_dvs_6axis_config( + const struct ia_css_dvs_6axis_config *dvs_6axis_config, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *dvs_in_frame_info, + ia_css_ptr ddr_addr_y); + +#endif /* __IA_CSS_DVS_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs_param.h new file mode 100644 index 000000000..2963bb10b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs_param.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DVS_PARAM_H +#define __IA_CSS_DVS_PARAM_H + +#include + +#if !defined(ENABLE_TPROXY) && !defined(ENABLE_CRUN_FOR_TD) && !defined(PARAMBIN_GENERATION) +#include "dma.h" +#endif /* !defined(ENABLE_TPROXY) && !defined(ENABLE_CRUN_FOR_TD) */ + +#include "uds/uds_1.0/ia_css_uds_param.h" + +/* dvserence frame */ +struct sh_css_isp_dvs_isp_config { + u32 num_horizontal_blocks; + u32 num_vertical_blocks; +}; + +#endif /* __IA_CSS_DVS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs_types.h new file mode 100644 index 000000000..e99ff0ce8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/ia_css_dvs_types.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DVS_TYPES_H +#define __IA_CSS_DVS_TYPES_H + +/* DVS frame + * + * ISP block: dvs frame + */ + +#include "ia_css_frame_public.h" + +struct ia_css_dvs_configuration { + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_DVS_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8.host.c new file mode 100644 index 000000000..bfea78171 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8.host.c @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif + +#include "type_support.h" +#include "assert_support.h" +#include "math_support.h" /* for min and max */ + +#include "ia_css_eed1_8.host.h" + +/* WARNING1: Number of inv points should be less or equal to 16, + * due to implementation limitation. See kernel design document + * for more details. + * WARNING2: Do not modify the number of inv points without correcting + * the EED1_8 kernel implementation assumptions. + */ +#define NUMBER_OF_CHGRINV_POINTS 15 +#define NUMBER_OF_TCINV_POINTS 9 +#define NUMBER_OF_FCINV_POINTS 9 + +static const s16 chgrinv_x[NUMBER_OF_CHGRINV_POINTS] = { + 0, 16, 64, 144, 272, 448, 672, 976, + 1376, 1888, 2528, 3312, 4256, 5376, 6688 +}; + +static const s16 chgrinv_a[NUMBER_OF_CHGRINV_POINTS] = { + -7171, -256, -29, -3456, -1071, -475, -189, -102, + -48, -38, -10, -9, -7, -6, 0 + }; + +static const s16 chgrinv_b[NUMBER_OF_CHGRINV_POINTS] = { + 8191, 1021, 256, 114, 60, 37, 24, 17, + 12, 9, 6, 5, 4, 3, 2 +}; + +static const s16 chgrinv_c[NUMBER_OF_CHGRINV_POINTS] = { + 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0 +}; + +static const s16 tcinv_x[NUMBER_OF_TCINV_POINTS] = { + 0, 4, 11, 23, 42, 68, 102, 148, 205 +}; + +static const s16 tcinv_a[NUMBER_OF_TCINV_POINTS] = { + -6364, -631, -126, -34, -13, -6, -4452, -2156, 0 + }; + +static const s16 tcinv_b[NUMBER_OF_TCINV_POINTS] = { + 8191, 1828, 726, 352, 197, 121, 80, 55, 40 +}; + +static const s16 tcinv_c[NUMBER_OF_TCINV_POINTS] = { + 1, 1, 1, 1, 1, 1, 0, 0, 0 +}; + +static const s16 fcinv_x[NUMBER_OF_FCINV_POINTS] = { + 0, 80, 216, 456, 824, 1344, 2040, 2952, 4096 +}; + +static const s16 fcinv_a[NUMBER_OF_FCINV_POINTS] = { + -5244, -486, -86, -2849, -961, -400, -180, -86, 0 + }; + +static const s16 fcinv_b[NUMBER_OF_FCINV_POINTS] = { + 8191, 1637, 607, 287, 159, 98, 64, 44, 32 +}; + +static const s16 fcinv_c[NUMBER_OF_FCINV_POINTS] = { + 1, 1, 1, 0, 0, 0, 0, 0, 0 +}; + +void +ia_css_eed1_8_vmem_encode( + struct eed1_8_vmem_params *to, + const struct ia_css_eed1_8_config *from, + size_t size) +{ + unsigned int i, j, base; + const unsigned int total_blocks = 4; + const unsigned int shuffle_block = 16; + + (void)size; + + /* Init */ + for (i = 0; i < ISP_VEC_NELEMS; i++) { + to->e_dew_enh_x[0][i] = 0; + to->e_dew_enh_y[0][i] = 0; + to->e_dew_enh_a[0][i] = 0; + to->e_dew_enh_f[0][i] = 0; + to->chgrinv_x[0][i] = 0; + to->chgrinv_a[0][i] = 0; + to->chgrinv_b[0][i] = 0; + to->chgrinv_c[0][i] = 0; + to->tcinv_x[0][i] = 0; + to->tcinv_a[0][i] = 0; + to->tcinv_b[0][i] = 0; + to->tcinv_c[0][i] = 0; + to->fcinv_x[0][i] = 0; + to->fcinv_a[0][i] = 0; + to->fcinv_b[0][i] = 0; + to->fcinv_c[0][i] = 0; + } + + /* Constraints on dew_enhance_seg_x and dew_enhance_seg_y: + * - values should be greater or equal to 0. + * - values should be ascending. + * - value of index zero is equal to 0. + */ + + /* Checking constraints: */ + /* TODO: investigate if an assert is the right way to report that + * the constraints are violated. + */ + for (j = 0; j < IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS; j++) { + assert(from->dew_enhance_seg_x[j] > -1); + assert(from->dew_enhance_seg_y[j] > -1); + } + + for (j = 1; j < IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS; j++) { + assert(from->dew_enhance_seg_x[j] > from->dew_enhance_seg_x[j - 1]); + assert(from->dew_enhance_seg_y[j] > from->dew_enhance_seg_y[j - 1]); + } + + assert(from->dew_enhance_seg_x[0] == 0); + assert(from->dew_enhance_seg_y[0] == 0); + + /* Constraints on chgrinv_x, tcinv_x and fcinv_x: + * - values should be greater or equal to 0. + * - values should be ascending. + * - value of index zero is equal to 0. + */ + assert(chgrinv_x[0] == 0); + assert(tcinv_x[0] == 0); + assert(fcinv_x[0] == 0); + + for (j = 1; j < NUMBER_OF_CHGRINV_POINTS; j++) { + assert(chgrinv_x[j] > chgrinv_x[j - 1]); + } + + for (j = 1; j < NUMBER_OF_TCINV_POINTS; j++) { + assert(tcinv_x[j] > tcinv_x[j - 1]); + } + + for (j = 1; j < NUMBER_OF_FCINV_POINTS; j++) { + assert(fcinv_x[j] > fcinv_x[j - 1]); + } + + /* The implementation of the calulating 1/x is based on the availability + * of the OP_vec_shuffle16 operation. + * A 64 element vector is split up in 4 blocks of 16 element. Each array is copied to + * a vector 4 times, (starting at 0, 16, 32 and 48). All array elements are copied or + * initialised as described in the KFS. The remaining elements of a vector are set to 0. + */ + /* TODO: guard this code with above assumptions */ + for (i = 0; i < total_blocks; i++) { + base = shuffle_block * i; + + for (j = 0; j < IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS; j++) { + to->e_dew_enh_x[0][base + j] = min_t(int, max_t(int, + from->dew_enhance_seg_x[j], 0), + 8191); + to->e_dew_enh_y[0][base + j] = min_t(int, max_t(int, + from->dew_enhance_seg_y[j], -8192), + 8191); + } + + for (j = 0; j < (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1); j++) { + to->e_dew_enh_a[0][base + j] = min_t(int, max_t(int, + from->dew_enhance_seg_slope[j], + -8192), 8191); + /* Convert dew_enhance_seg_exp to flag: + * 0 -> 0 + * 1...13 -> 1 + */ + to->e_dew_enh_f[0][base + j] = (min_t(int, max_t(int, + from->dew_enhance_seg_exp[j], + 0), 13) > 0); + } + + /* Hard-coded to 0, in order to be able to handle out of + * range input in the same way as the other segments. + * See KFS for more details. + */ + to->e_dew_enh_a[0][base + (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)] = 0; + to->e_dew_enh_f[0][base + (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)] = 0; + + for (j = 0; j < NUMBER_OF_CHGRINV_POINTS; j++) { + to->chgrinv_x[0][base + j] = chgrinv_x[j]; + to->chgrinv_a[0][base + j] = chgrinv_a[j]; + to->chgrinv_b[0][base + j] = chgrinv_b[j]; + to->chgrinv_c[0][base + j] = chgrinv_c[j]; + } + + for (j = 0; j < NUMBER_OF_TCINV_POINTS; j++) { + to->tcinv_x[0][base + j] = tcinv_x[j]; + to->tcinv_a[0][base + j] = tcinv_a[j]; + to->tcinv_b[0][base + j] = tcinv_b[j]; + to->tcinv_c[0][base + j] = tcinv_c[j]; + } + + for (j = 0; j < NUMBER_OF_FCINV_POINTS; j++) { + to->fcinv_x[0][base + j] = fcinv_x[j]; + to->fcinv_a[0][base + j] = fcinv_a[j]; + to->fcinv_b[0][base + j] = fcinv_b[j]; + to->fcinv_c[0][base + j] = fcinv_c[j]; + } + } +} + +void +ia_css_eed1_8_encode( + struct eed1_8_dmem_params *to, + const struct ia_css_eed1_8_config *from, + size_t size) +{ + int i; + int min_exp = 0; + + (void)size; + + to->rbzp_strength = from->rbzp_strength; + + to->fcstrength = from->fcstrength; + to->fcthres_0 = from->fcthres_0; + to->fc_sat_coef = from->fc_sat_coef; + to->fc_coring_prm = from->fc_coring_prm; + to->fc_slope = from->fcthres_1 - from->fcthres_0; + + to->aerel_thres0 = from->aerel_thres0; + to->aerel_gain0 = from->aerel_gain0; + to->aerel_thres_diff = from->aerel_thres1 - from->aerel_thres0; + to->aerel_gain_diff = from->aerel_gain1 - from->aerel_gain0; + + to->derel_thres0 = from->derel_thres0; + to->derel_gain0 = from->derel_gain0; + to->derel_thres_diff = (from->derel_thres1 - from->derel_thres0); + to->derel_gain_diff = (from->derel_gain1 - from->derel_gain0); + + to->coring_pos0 = from->coring_pos0; + to->coring_pos_diff = (from->coring_pos1 - from->coring_pos0); + to->coring_neg0 = from->coring_neg0; + to->coring_neg_diff = (from->coring_neg1 - from->coring_neg0); + + /* Note: (ISP_VEC_ELEMBITS -1) + * TODO: currently the testbench does not support to use + * ISP_VEC_ELEMBITS. Investigate how to fix this + */ + to->gain_exp = (13 - from->gain_exp); + to->gain_pos0 = from->gain_pos0; + to->gain_pos_diff = (from->gain_pos1 - from->gain_pos0); + to->gain_neg0 = from->gain_neg0; + to->gain_neg_diff = (from->gain_neg1 - from->gain_neg0); + + to->margin_pos0 = from->pos_margin0; + to->margin_pos_diff = (from->pos_margin1 - from->pos_margin0); + to->margin_neg0 = from->neg_margin0; + to->margin_neg_diff = (from->neg_margin1 - from->neg_margin0); + + /* Encode DEWEnhance exp (e_dew_enh_asr) */ + for (i = 0; i < (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1); i++) { + min_exp = max(min_exp, from->dew_enhance_seg_exp[i]); + } + to->e_dew_enh_asr = 13 - min(max(min_exp, 0), 13); + + to->dedgew_max = from->dedgew_max; +} + +void +ia_css_init_eed1_8_state( + void *state, + size_t size) +{ + memset(state, 0, size); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_eed1_8_debug_dtrace( + const struct ia_css_eed1_8_config *eed, + unsigned int level) +{ + if (!eed) + return; + + ia_css_debug_dtrace(level, "Edge Enhancing Demosaic 1.8:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "rbzp_strength", + eed->rbzp_strength); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fcstrength", eed->fcstrength); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fcthres_0", eed->fcthres_0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fcthres_1", eed->fcthres_1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fc_sat_coef", eed->fc_sat_coef); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fc_coring_prm", + eed->fc_coring_prm); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "aerel_thres0", eed->aerel_thres0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "aerel_gain0", eed->aerel_gain0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "aerel_thres1", eed->aerel_thres1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "aerel_gain1", eed->aerel_gain1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "derel_thres0", eed->derel_thres0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "derel_gain0", eed->derel_gain0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "derel_thres1", eed->derel_thres1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "derel_gain1", eed->derel_gain1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "coring_pos0", eed->coring_pos0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "coring_pos1", eed->coring_pos1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "coring_neg0", eed->coring_neg0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "coring_neg1", eed->coring_neg1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_exp", eed->gain_exp); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_pos0", eed->gain_pos0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_pos1", eed->gain_pos1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_neg0", eed->gain_neg0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_neg1", eed->gain_neg1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "pos_margin0", eed->pos_margin0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "pos_margin1", eed->pos_margin1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "neg_margin0", eed->neg_margin0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "neg_margin1", eed->neg_margin1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dedgew_max", eed->dedgew_max); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8.host.h new file mode 100644 index 000000000..f1ad07e78 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8.host.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EED1_8_HOST_H +#define __IA_CSS_EED1_8_HOST_H + +#include "ia_css_eed1_8_types.h" +#include "ia_css_eed1_8_param.h" + +void +ia_css_eed1_8_vmem_encode( + struct eed1_8_vmem_params *to, + const struct ia_css_eed1_8_config *from, + size_t size); + +void +ia_css_eed1_8_encode( + struct eed1_8_dmem_params *to, + const struct ia_css_eed1_8_config *from, + size_t size); + +void +ia_css_init_eed1_8_state( + void *state, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_eed1_8_debug_dtrace( + const struct ia_css_eed1_8_config *config, + unsigned int level); +#endif + +#endif /* __IA_CSS_EED1_8_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8_param.h new file mode 100644 index 000000000..6fb3b38f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8_param.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EED1_8_PARAM_H +#define __IA_CSS_EED1_8_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +#include "ia_css_eed1_8_types.h" /* IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS */ + +/* Configuration parameters: */ + +/* Enable median for false color correction + * 0: Do not use median + * 1: Use median + * Default: 1 + */ +#define EED1_8_FC_ENABLE_MEDIAN 1 + +/* Coring Threshold minima + * Used in Tint color suppression. + * Default: 1 + */ +#define EED1_8_CORINGTHMIN 1 + +/* Define size of the state..... TODO: check if this is the correct place */ +/* 4 planes : GR, R, B, GB */ +#define NUM_PLANES 4 + +/* 5 lines state per color plane input_line_state */ +#define EED1_8_STATE_INPUT_BUFFER_HEIGHT (5 * NUM_PLANES) + +/* Each plane has width equal to half frame line */ +#define EED1_8_STATE_INPUT_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line state per color plane LD_H state */ +#define EED1_8_STATE_LD_H_HEIGHT (1 * NUM_PLANES) +#define EED1_8_STATE_LD_H_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line state per color plane LD_V state */ +#define EED1_8_STATE_LD_V_HEIGHT (1 * NUM_PLANES) +#define EED1_8_STATE_LD_V_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line (single plane) state for D_Hr state */ +#define EED1_8_STATE_D_HR_HEIGHT 1 +#define EED1_8_STATE_D_HR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line (single plane) state for D_Hb state */ +#define EED1_8_STATE_D_HB_HEIGHT 1 +#define EED1_8_STATE_D_HB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 2 lines (single plane) state for D_Vr state */ +#define EED1_8_STATE_D_VR_HEIGHT 2 +#define EED1_8_STATE_D_VR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 2 line (single plane) state for D_Vb state */ +#define EED1_8_STATE_D_VB_HEIGHT 2 +#define EED1_8_STATE_D_VB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 2 lines state for R and B (= 2 planes) rb_zipped_state */ +#define EED1_8_STATE_RB_ZIPPED_HEIGHT (2 * 2) +#define EED1_8_STATE_RB_ZIPPED_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +#if EED1_8_FC_ENABLE_MEDIAN +/* 1 full input line (GR-R color line) for Yc state */ +#define EED1_8_STATE_YC_HEIGHT 1 +#define EED1_8_STATE_YC_WIDTH MAX_FRAME_SIMDWIDTH + +/* 1 line state per color plane Cg_state */ +#define EED1_8_STATE_CG_HEIGHT (1 * NUM_PLANES) +#define EED1_8_STATE_CG_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line state per color plane Co_state */ +#define EED1_8_STATE_CO_HEIGHT (1 * NUM_PLANES) +#define EED1_8_STATE_CO_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 full input line (GR-R color line) for AbsK state */ +#define EED1_8_STATE_ABSK_HEIGHT 1 +#define EED1_8_STATE_ABSK_WIDTH MAX_FRAME_SIMDWIDTH +#endif + +struct eed1_8_vmem_params { + VMEM_ARRAY(e_dew_enh_x, ISP_VEC_NELEMS); + VMEM_ARRAY(e_dew_enh_y, ISP_VEC_NELEMS); + VMEM_ARRAY(e_dew_enh_a, ISP_VEC_NELEMS); + VMEM_ARRAY(e_dew_enh_f, ISP_VEC_NELEMS); + VMEM_ARRAY(chgrinv_x, ISP_VEC_NELEMS); + VMEM_ARRAY(chgrinv_a, ISP_VEC_NELEMS); + VMEM_ARRAY(chgrinv_b, ISP_VEC_NELEMS); + VMEM_ARRAY(chgrinv_c, ISP_VEC_NELEMS); + VMEM_ARRAY(fcinv_x, ISP_VEC_NELEMS); + VMEM_ARRAY(fcinv_a, ISP_VEC_NELEMS); + VMEM_ARRAY(fcinv_b, ISP_VEC_NELEMS); + VMEM_ARRAY(fcinv_c, ISP_VEC_NELEMS); + VMEM_ARRAY(tcinv_x, ISP_VEC_NELEMS); + VMEM_ARRAY(tcinv_a, ISP_VEC_NELEMS); + VMEM_ARRAY(tcinv_b, ISP_VEC_NELEMS); + VMEM_ARRAY(tcinv_c, ISP_VEC_NELEMS); +}; + +/* EED (Edge Enhancing Demosaic) ISP parameters */ +struct eed1_8_dmem_params { + s32 rbzp_strength; + + s32 fcstrength; + s32 fcthres_0; + s32 fc_sat_coef; + s32 fc_coring_prm; + s32 fc_slope; + + s32 aerel_thres0; + s32 aerel_gain0; + s32 aerel_thres_diff; + s32 aerel_gain_diff; + + s32 derel_thres0; + s32 derel_gain0; + s32 derel_thres_diff; + s32 derel_gain_diff; + + s32 coring_pos0; + s32 coring_pos_diff; + s32 coring_neg0; + s32 coring_neg_diff; + + s32 gain_exp; + s32 gain_pos0; + s32 gain_pos_diff; + s32 gain_neg0; + s32 gain_neg_diff; + + s32 margin_pos0; + s32 margin_pos_diff; + s32 margin_neg0; + s32 margin_neg_diff; + + s32 e_dew_enh_asr; + s32 dedgew_max; +}; + +#endif /* __IA_CSS_EED1_8_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8_types.h new file mode 100644 index 000000000..836e348c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8_types.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EED1_8_TYPES_H +#define __IA_CSS_EED1_8_TYPES_H + +/* @file +* CSS-API header file for Edge Enhanced Demosaic parameters. +*/ + +#include "type_support.h" + +/** + * \brief EED1_8 public parameters. + * \details Struct with all parameters for the EED1.8 kernel that can be set + * from the CSS API. + */ + +/* parameter list is based on ISP261 CSS API public parameter list_all.xlsx from 28-01-2015 */ + +/* Number of segments + 1 segment used in edge reliability enhancement + * Ineffective: N/A + * Default: 9 + */ +#define IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS 9 + +/* Edge Enhanced Demosaic configuration + * + * ISP2.6.1: EED1_8 is used. + */ + +struct ia_css_eed1_8_config { + s32 rbzp_strength; /** Strength of zipper reduction. */ + + s32 fcstrength; /** Strength of false color reduction. */ + s32 fcthres_0; /** Threshold to prevent chroma coring due to noise or green disparity in dark region. */ + s32 fcthres_1; /** Threshold to prevent chroma coring due to noise or green disparity in bright region. */ + s32 fc_sat_coef; /** How much color saturation to maintain in high color saturation region. */ + s32 fc_coring_prm; /** Chroma coring coefficient for tint color suppression. */ + + s32 aerel_thres0; /** Threshold for Non-Directional Reliability at dark region. */ + s32 aerel_gain0; /** Gain for Non-Directional Reliability at dark region. */ + s32 aerel_thres1; /** Threshold for Non-Directional Reliability at bright region. */ + s32 aerel_gain1; /** Gain for Non-Directional Reliability at bright region. */ + + s32 derel_thres0; /** Threshold for Directional Reliability at dark region. */ + s32 derel_gain0; /** Gain for Directional Reliability at dark region. */ + s32 derel_thres1; /** Threshold for Directional Reliability at bright region. */ + s32 derel_gain1; /** Gain for Directional Reliability at bright region. */ + + s32 coring_pos0; /** Positive Edge Coring Threshold in dark region. */ + s32 coring_pos1; /** Positive Edge Coring Threshold in bright region. */ + s32 coring_neg0; /** Negative Edge Coring Threshold in dark region. */ + s32 coring_neg1; /** Negative Edge Coring Threshold in bright region. */ + + s32 gain_exp; /** Common Exponent of Gain. */ + s32 gain_pos0; /** Gain for Positive Edge in dark region. */ + s32 gain_pos1; /** Gain for Positive Edge in bright region. */ + s32 gain_neg0; /** Gain for Negative Edge in dark region. */ + s32 gain_neg1; /** Gain for Negative Edge in bright region. */ + + s32 pos_margin0; /** Margin for Positive Edge in dark region. */ + s32 pos_margin1; /** Margin for Positive Edge in bright region. */ + s32 neg_margin0; /** Margin for Negative Edge in dark region. */ + s32 neg_margin1; /** Margin for Negative Edge in bright region. */ + + s32 dew_enhance_seg_x[IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS]; /** Segment data for directional edge weight: X. */ + s32 dew_enhance_seg_y[IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS]; /** Segment data for directional edge weight: Y. */ + s32 dew_enhance_seg_slope[(IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - + 1)]; /** Segment data for directional edge weight: Slope. */ + s32 dew_enhance_seg_exp[(IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - + 1)]; /** Segment data for directional edge weight: Exponent. */ + s32 dedgew_max; /** Max Weight for Directional Edge. */ +}; + +#endif /* __IA_CSS_EED1_8_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats.host.c new file mode 100644 index 000000000..bae1ca2cd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats.host.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_formats.host.h" +#include "ia_css_types.h" +#include "sh_css_defs.h" + +/*#include "sh_css_frac.h"*/ +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif + +const struct ia_css_formats_config default_formats_config = { + 1 +}; + +void +ia_css_formats_encode( + struct sh_css_isp_formats_params *to, + const struct ia_css_formats_config *from, + unsigned int size) +{ + (void)size; + to->video_full_range_flag = from->video_full_range_flag; +} + +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +void +ia_css_formats_dump( + const struct sh_css_isp_formats_params *formats, + unsigned int level) +{ + if (!formats) return; + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "video_full_range_flag", formats->video_full_range_flag); +} +#endif + +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +void +ia_css_formats_debug_dtrace( + const struct ia_css_formats_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.video_full_range_flag=%d\n", + config->video_full_range_flag); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats.host.h new file mode 100644 index 000000000..540423d85 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats.host.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FORMATS_HOST_H +#define __IA_CSS_FORMATS_HOST_H + +#include "ia_css_formats_types.h" +#include "ia_css_formats_param.h" + +extern const struct ia_css_formats_config default_formats_config; + +void +ia_css_formats_encode( + struct sh_css_isp_formats_params *to, + const struct ia_css_formats_config *from, + unsigned int size); +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +void +ia_css_formats_dump( + const struct sh_css_isp_formats_params *formats, + unsigned int level); +#endif + +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +void +ia_css_formats_debug_dtrace( + const struct ia_css_formats_config *formats, + unsigned int level); +#endif /*IA_CSS_NO_DEBUG*/ + +#endif /* __IA_CSS_FORMATS_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats_param.h new file mode 100644 index 000000000..5275a1dad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats_param.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FORMATS_PARAM_H +#define __IA_CSS_FORMATS_PARAM_H + +#include "type_support.h" + +/* FORMATS (Format conversion) */ +struct sh_css_isp_formats_params { + s32 video_full_range_flag; +}; + +#endif /* __IA_CSS_FORMATS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats_types.h new file mode 100644 index 000000000..16b6a3ddc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fc/fc_1.0/ia_css_formats_types.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FORMATS_TYPES_H +#define __IA_CSS_FORMATS_TYPES_H + +/* @file +* CSS-API header file for output format parameters. +*/ + +#include "type_support.h" + +/* Formats configuration. + * + * ISP block: FORMATS + * ISP1: FORMATS is used. + * ISP2: FORMATS is used. + */ +struct ia_css_formats_config { + u32 video_full_range_flag; /** selects the range of YUV output. + u8.0, [0,1], + default 1, ineffective n/a\n + 1 - full range, luma 0-255, chroma 0-255\n + 0 - reduced range, luma 16-235, chroma 16-240 */ +}; + +#endif /* __IA_CSS_FORMATS_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h new file mode 100644 index 000000000..6cd635f3e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FIXEDBDS_PARAM_H +#define __IA_CSS_FIXEDBDS_PARAM_H + +#include "type_support.h" + +/* ISP2401 */ +#define BDS_UNIT 8 +#define FRAC_LOG 3 +#define FRAC_ACC BIT(FRAC_LOG) +#if FRAC_ACC != BDS_UNIT +#error "FRAC_ACC and BDS_UNIT need to be merged into one define" +#endif + +struct sh_css_isp_bds_params { + int baf_strength; +}; + +#endif /* __IA_CSS_FIXEDBDS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_types.h new file mode 100644 index 000000000..3a55d4c69 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_types.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FIXEDBDS_TYPES_H +#define __IA_CSS_FIXEDBDS_TYPES_H + +struct sh_css_bds_factor { + unsigned int numerator; + unsigned int denominator; + unsigned int bds_factor; +}; + +#endif /*__IA_CSS_FIXEDBDS_TYPES_H*/ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.c new file mode 100644 index 000000000..57b5e11e1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" + +#include "ia_css_fpn.host.h" + +void +ia_css_fpn_encode( + struct sh_css_isp_fpn_params *to, + const struct ia_css_fpn_table *from, + unsigned int size) +{ + (void)size; + to->shift = from->shift; + to->enabled = from->data != NULL; +} + +void +ia_css_fpn_dump( + const struct sh_css_isp_fpn_params *fpn, + unsigned int level) +{ + if (!fpn) return; + ia_css_debug_dtrace(level, "Fixed Pattern Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "fpn_shift", fpn->shift); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "fpn_enabled", fpn->enabled); +} + +int ia_css_fpn_config(struct sh_css_isp_fpn_isp_config *to, + const struct ia_css_fpn_configuration *from, + unsigned int size) +{ + unsigned int elems_a = ISP_VEC_NELEMS; + int ret; + + ret = ia_css_dma_configure_from_info(&to->port_b, from->info); + if (ret) + return ret; + + to->width_a_over_b = elems_a / to->port_b.elems; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + if (elems_a % to->port_b.elems != 0) + return -EINVAL; + + return 0; +} + +int ia_css_fpn_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + struct ia_css_frame_info my_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + const struct ia_css_fpn_configuration config = { + &my_info + }; + + my_info.res.width = CEIL_DIV(info->res.width, 2); /* Packed by 2x */ + my_info.res.height = info->res.height; + my_info.padded_width = CEIL_DIV(info->padded_width, 2); /* Packed by 2x */ + my_info.format = info->format; + my_info.raw_bit_depth = FPN_BITS_PER_PIXEL; + my_info.raw_bayer_order = info->raw_bayer_order; + my_info.crop_info = info->crop_info; + + return ia_css_configure_fpn(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h new file mode 100644 index 000000000..bd341fa28 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FPN_HOST_H +#define __IA_CSS_FPN_HOST_H + +#include "ia_css_binary.h" +#include "ia_css_fpn_types.h" +#include "ia_css_fpn_param.h" + +void +ia_css_fpn_encode( + struct sh_css_isp_fpn_params *to, + const struct ia_css_fpn_table *from, + unsigned int size); + +void +ia_css_fpn_dump( + const struct sh_css_isp_fpn_params *fpn, + unsigned int level); + +int ia_css_fpn_config(struct sh_css_isp_fpn_isp_config *to, + const struct ia_css_fpn_configuration *from, + unsigned int size); + +int ia_css_fpn_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +#endif /* __IA_CSS_FPN_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn_param.h new file mode 100644 index 000000000..b21415743 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn_param.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FPN_PARAM_H +#define __IA_CSS_FPN_PARAM_H + +#include "type_support.h" + +#include "dma.h" + +#define FPN_BITS_PER_PIXEL 16 + +/* FPNR (Fixed Pattern Noise Reduction) */ +struct sh_css_isp_fpn_params { + s32 shift; + s32 enabled; +}; + +struct sh_css_isp_fpn_isp_config { + u32 width_a_over_b; + struct dma_port_config port_b; +}; + +#endif /* __IA_CSS_FPN_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn_types.h new file mode 100644 index 000000000..14dc5e183 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/fpn/fpn_1.0/ia_css_fpn_types.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FPN_TYPES_H +#define __IA_CSS_FPN_TYPES_H + +/* @file +* CSS-API header file for Fixed Pattern Noise parameters. +*/ + +/* Fixed Pattern Noise table. + * + * This contains the fixed patterns noise values + * obtained from a black frame capture. + * + * "shift" should be set as the smallest value + * which satisfies the requirement the maximum data is less than 64. + * + * ISP block: FPN1 + * ISP1: FPN1 is used. + * ISP2: FPN1 is used. + */ + +struct ia_css_fpn_table { + s16 *data; /** Table content (fixed patterns noise). + u0.[13-shift], [0,63] */ + u32 width; /** Table width (in pixels). + This is the input frame width. */ + u32 height; /** Table height (in pixels). + This is the input frame height. */ + u32 shift; /** Common exponent of table content. + u8.0, [0,13] */ + u32 enabled; /** Fpn is enabled. + bool */ +}; + +struct ia_css_fpn_configuration { + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_FPN_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc.host.c new file mode 100644 index 000000000..7f3f87920 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc.host.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif +#include "sh_css_frac.h" +#include "vamem.h" + +#include "ia_css_gc.host.h" + +const struct ia_css_gc_config default_gc_config = { + 0, + 0 +}; + +const struct ia_css_ce_config default_ce_config = { + 0, + 255 +}; + +void +ia_css_gc_encode( + struct sh_css_isp_gc_params *to, + const struct ia_css_gc_config *from, + unsigned int size) +{ + (void)size; + to->gain_k1 = + uDIGIT_FITTING((int)from->gain_k1, 16, + IA_CSS_GAMMA_GAIN_K_SHIFT); + to->gain_k2 = + uDIGIT_FITTING((int)from->gain_k2, 16, + IA_CSS_GAMMA_GAIN_K_SHIFT); +} + +void +ia_css_ce_encode( + struct sh_css_isp_ce_params *to, + const struct ia_css_ce_config *from, + unsigned int size) +{ + (void)size; + to->uv_level_min = from->uv_level_min; + to->uv_level_max = from->uv_level_max; +} + +void +ia_css_gc_vamem_encode( + struct sh_css_isp_gc_vamem_params *to, + const struct ia_css_gamma_table *from, + unsigned int size) +{ + (void)size; + memcpy(&to->gc, &from->data, sizeof(to->gc)); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_gc_dump( + const struct sh_css_isp_gc_params *gc, + unsigned int level) +{ + if (!gc) return; + ia_css_debug_dtrace(level, "Gamma Correction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "gamma_gain_k1", gc->gain_k1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "gamma_gain_k2", gc->gain_k2); +} + +void +ia_css_ce_dump( + const struct sh_css_isp_ce_params *ce, + unsigned int level) +{ + ia_css_debug_dtrace(level, "Chroma Enhancement:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ce_uv_level_min", ce->uv_level_min); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ce_uv_level_max", ce->uv_level_max); +} + +void +ia_css_gc_debug_dtrace( + const struct ia_css_gc_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.gain_k1=%d, config.gain_k2=%d\n", + config->gain_k1, config->gain_k2); +} + +void +ia_css_ce_debug_dtrace( + const struct ia_css_ce_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.uv_level_min=%d, config.uv_level_max=%d\n", + config->uv_level_min, config->uv_level_max); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc.host.h new file mode 100644 index 000000000..c2dc1574a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc.host.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC_HOST_H +#define __IA_CSS_GC_HOST_H + +#include "ia_css_gc_param.h" +#include "ia_css_gc_table.host.h" + +extern const struct ia_css_gc_config default_gc_config; +extern const struct ia_css_ce_config default_ce_config; + +void +ia_css_gc_encode( + struct sh_css_isp_gc_params *to, + const struct ia_css_gc_config *from, + unsigned int size); + +void +ia_css_gc_vamem_encode( + struct sh_css_isp_gc_vamem_params *to, + const struct ia_css_gamma_table *from, + unsigned int size); + +void +ia_css_ce_encode( + struct sh_css_isp_ce_params *to, + const struct ia_css_ce_config *from, + unsigned int size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_gc_dump( + const struct sh_css_isp_gc_params *gc, + unsigned int level); + +void +ia_css_ce_dump( + const struct sh_css_isp_ce_params *ce, + unsigned int level); + +void +ia_css_gc_debug_dtrace( + const struct ia_css_gc_config *config, + unsigned int level); + +void +ia_css_ce_debug_dtrace( + const struct ia_css_ce_config *config, + unsigned int level); + +#endif + +#endif /* __IA_CSS_GC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_param.h new file mode 100644 index 000000000..a81233add --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_param.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC_PARAM_H +#define __IA_CSS_GC_PARAM_H + +#include "type_support.h" +#ifndef PIPE_GENERATION +#ifdef __ISP +#define __INLINE_VAMEM__ +#endif +#include "vamem.h" +#include "ia_css_gc_types.h" + +#if defined(IS_VAMEM_VERSION_1) +#define SH_CSS_ISP_GAMMA_TABLE_SIZE_LOG2 IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_GC_TABLE_SIZE IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE +#elif defined(IS_VAMEM_VERSION_2) +#define SH_CSS_ISP_GAMMA_TABLE_SIZE_LOG2 IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_GC_TABLE_SIZE IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE +#else +#error "Undefined vamem version" +#endif + +#else +/* For pipe generation, the size is not relevant */ +#define SH_CSS_ISP_GC_TABLE_SIZE 0 +#endif + +#define GAMMA_OUTPUT_BITS 8 +#define GAMMA_OUTPUT_MAX_VAL ((1 << GAMMA_OUTPUT_BITS) - 1) + +/* GC (Gamma Correction) */ +struct sh_css_isp_gc_params { + s32 gain_k1; + s32 gain_k2; +}; + +/* CE (Chroma Enhancement) */ +struct sh_css_isp_ce_params { + s32 uv_level_min; + s32 uv_level_max; +}; + +/* This should be vamem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_gc_vamem_params { + u16 gc[SH_CSS_ISP_GC_TABLE_SIZE]; +}; + +#endif /* __IA_CSS_GC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.c new file mode 100644 index 000000000..7dbe2dc05 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for memcpy() */ + +#include +#include "system_global.h" +#include "vamem.h" +#include "ia_css_types.h" +#include "ia_css_gc_table.host.h" + + +struct ia_css_gamma_table default_gamma_table; + +static const uint16_t +default_gamma_table_data[IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE] = { + 0, 4, 8, 12, 17, 21, 27, 32, + 38, 44, 49, 55, 61, 66, 71, 76, + 80, 84, 88, 92, 95, 98, 102, 105, + 108, 110, 113, 116, 118, 121, 123, 126, + 128, 130, 132, 135, 137, 139, 141, 143, + 145, 146, 148, 150, 152, 153, 155, 156, + 158, 160, 161, 162, 164, 165, 166, 168, + 169, 170, 171, 172, 174, 175, 176, 177, + 178, 179, 180, 181, 182, 183, 184, 184, + 185, 186, 187, 188, 189, 189, 190, 191, + 192, 192, 193, 194, 195, 195, 196, 197, + 197, 198, 198, 199, 200, 200, 201, 201, + 202, 203, 203, 204, 204, 205, 205, 206, + 206, 207, 207, 208, 208, 209, 209, 210, + 210, 210, 211, 211, 212, 212, 213, 213, + 214, 214, 214, 215, 215, 216, 216, 216, + 217, 217, 218, 218, 218, 219, 219, 220, + 220, 220, 221, 221, 222, 222, 222, 223, + 223, 223, 224, 224, 225, 225, 225, 226, + 226, 226, 227, 227, 227, 228, 228, 228, + 229, 229, 229, 230, 230, 230, 231, 231, + 231, 232, 232, 232, 233, 233, 233, 234, + 234, 234, 234, 235, 235, 235, 236, 236, + 236, 237, 237, 237, 237, 238, 238, 238, + 239, 239, 239, 239, 240, 240, 240, 241, + 241, 241, 241, 242, 242, 242, 242, 243, + 243, 243, 243, 244, 244, 244, 245, 245, + 245, 245, 246, 246, 246, 246, 247, 247, + 247, 247, 248, 248, 248, 248, 249, 249, + 249, 249, 250, 250, 250, 250, 251, 251, + 251, 251, 252, 252, 252, 252, 253, 253, + 253, 253, 254, 254, 254, 254, 255, 255, + 255 +}; + + +void +ia_css_config_gamma_table(void) +{ + memcpy(default_gamma_table.data.vamem_2, default_gamma_table_data, + sizeof(default_gamma_table_data)); + default_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_2; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.h new file mode 100644 index 000000000..ee6fa07b3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC_TABLE_HOST_H +#define __IA_CSS_GC_TABLE_HOST_H + +#include "ia_css_gc_types.h" + +extern struct ia_css_gamma_table default_gamma_table; + +void ia_css_config_gamma_table(void); + +#endif /* __IA_CSS_GC_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_types.h new file mode 100644 index 000000000..ccd3d91a2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_1.0/ia_css_gc_types.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC_TYPES_H +#define __IA_CSS_GC_TYPES_H + +/* @file +* CSS-API header file for Gamma Correction parameters. +*/ + +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h" /* FIXME: Needed for ia_css_vamem_type */ + +/* Fractional bits for GAMMA gain */ +#define IA_CSS_GAMMA_GAIN_K_SHIFT 13 + +/* Number of elements in the gamma table. */ +#define IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE_LOG2 10 +#define IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE BIT(IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE_LOG2) + +/* Number of elements in the gamma table. */ +#define IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE_LOG2 8 +#define IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE ((1U << IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE_LOG2) + 1) + +/* Gamma table, used for Y(Luma) Gamma Correction. + * + * ISP block: GC1 (YUV Gamma Correction) + * ISP1: GC1 is used. + * (ISP2: GC2(sRGB Gamma Correction) is used.) + */ +/** IA_CSS_VAMEM_TYPE_1(ISP2300) or + IA_CSS_VAMEM_TYPE_2(ISP2400) */ +union ia_css_gc_data { + u16 vamem_1[IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE]; + /** Y(Luma) Gamma table on vamem type 1. u0.8, [0,255] */ + u16 vamem_2[IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE]; + /** Y(Luma) Gamma table on vamem type 2. u0.8, [0,255] */ +}; + +struct ia_css_gamma_table { + enum ia_css_vamem_type vamem_type; + union ia_css_gc_data data; +}; + +/* Gamma Correction configuration (used only for YUV Gamma Correction). + * + * ISP block: GC1 (YUV Gamma Correction) + * ISP1: GC1 is used. + * (ISP2: GC2 (sRGB Gamma Correction) is used.) + */ +struct ia_css_gc_config { + u16 gain_k1; /** Gain to adjust U after YUV Gamma Correction. + u0.16, [0,65535], + default/ineffective 19000(0.29) */ + u16 gain_k2; /** Gain to adjust V after YUV Gamma Correction. + u0.16, [0,65535], + default/ineffective 19000(0.29) */ +}; + +/* Chroma Enhancement configuration. + * + * This parameter specifies range of chroma output level. + * The standard range is [0,255] or [16,240]. + * + * ISP block: CE1 + * ISP1: CE1 is used. + * (ISP2: CE1 is not used.) + */ +struct ia_css_ce_config { + u8 uv_level_min; /** Minimum of chroma output level. + u0.8, [0,255], default/ineffective 0 */ + u8 uv_level_max; /** Maximum of chroma output level. + u0.8, [0,255], default/ineffective 255 */ +}; + +/* Multi-Axes Color Correction (MACC) configuration. + * + * ISP block: MACC2 (MACC by matrix and exponent(ia_css_macc_config)) + * (ISP1: MACC1 (MACC by only matrix) is used.) + * ISP2: MACC2 is used. + */ +struct ia_css_macc_config { + u8 exp; /** Common exponent of ia_css_macc_table. + u8.0, [0,13], default 1, ineffective 1 */ +}; + +#endif /* __IA_CSS_GC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2.host.c new file mode 100644 index 000000000..76209b7c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2.host.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif +#include "csc/csc_1.0/ia_css_csc.host.h" +#include "vamem.h" + +#include "ia_css_gc2.host.h" + +const struct ia_css_cc_config default_yuv2rgb_cc_config = { + 12, + {4096, -4096, 4096, 4096, 4096, 0, 4096, -4096, -4096} +}; + +const struct ia_css_cc_config default_rgb2yuv_cc_config = { + 13, + {2449, 4809, 934, -1382, -2714, 4096, 4096, -3430, -666} +}; + +void +ia_css_yuv2rgb_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned int size) +{ + ia_css_encode_cc(to, from, size); +} + +void +ia_css_rgb2yuv_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned int size) +{ + ia_css_encode_cc(to, from, size); +} + +void +ia_css_r_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned int size) +{ + (void)size; + memcpy(&to->gc, &from->data, sizeof(to->gc)); +} + +void +ia_css_g_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned int size) +{ + (void)size; + memcpy(&to->gc, &from->data, sizeof(to->gc)); +} + +void +ia_css_b_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned int size) +{ + (void)size; + memcpy(&to->gc, &from->data, sizeof(to->gc)); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_yuv2rgb_dump( + const struct sh_css_isp_csc_params *yuv2rgb, + unsigned int level) +{ + ia_css_cc_dump(yuv2rgb, level, "YUV to RGB Conversion"); +} + +void +ia_css_rgb2yuv_dump( + const struct sh_css_isp_csc_params *rgb2yuv, + unsigned int level) +{ + ia_css_cc_dump(rgb2yuv, level, "RGB to YUV Conversion"); +} + +void +ia_css_rgb_gamma_table_debug_dtrace( + const struct ia_css_rgb_gamma_table *config, + unsigned int level) +{ + (void)config; + (void)level; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2.host.h new file mode 100644 index 000000000..eabf78737 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2.host.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC2_HOST_H +#define __IA_CSS_GC2_HOST_H + +#include "ia_css_gc2_types.h" +#include "ia_css_gc2_param.h" +#include "ia_css_gc2_table.host.h" + +extern const struct ia_css_cc_config default_yuv2rgb_cc_config; +extern const struct ia_css_cc_config default_rgb2yuv_cc_config; + +void +ia_css_yuv2rgb_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned int size); + +void +ia_css_rgb2yuv_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned int size); + +void +ia_css_r_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned int size); + +void +ia_css_g_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned int size); + +void +ia_css_b_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned int size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_yuv2rgb_dump( + const struct sh_css_isp_csc_params *yuv2rgb, + unsigned int level); + +void +ia_css_rgb2yuv_dump( + const struct sh_css_isp_csc_params *rgb2yuv, + unsigned int level); + +void +ia_css_rgb_gamma_table_debug_dtrace( + const struct ia_css_rgb_gamma_table *config, + unsigned int level); + +#define ia_css_yuv2rgb_debug_dtrace ia_css_cc_config_debug_dtrace +#define ia_css_rgb2yuv_debug_dtrace ia_css_cc_config_debug_dtrace +#define ia_css_r_gamma_debug_dtrace ia_css_rgb_gamma_table_debug_dtrace +#define ia_css_g_gamma_debug_dtrace ia_css_rgb_gamma_table_debug_dtrace +#define ia_css_b_gamma_debug_dtrace ia_css_rgb_gamma_table_debug_dtrace + +#endif + +#endif /* __IA_CSS_GC2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_param.h new file mode 100644 index 000000000..af456e75e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_param.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC2_PARAM_H +#define __IA_CSS_GC2_PARAM_H + +#include "type_support.h" +/* Extend GC1 */ +#include "ia_css_gc2_types.h" +#include "gc/gc_1.0/ia_css_gc_param.h" +#include "csc/csc_1.0/ia_css_csc_param.h" + +#ifndef PIPE_GENERATION +#if defined(IS_VAMEM_VERSION_1) +#define SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE +#elif defined(IS_VAMEM_VERSION_2) +#define SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE +#else +#error "Undefined vamem version" +#endif + +#else +/* For pipe generation, the size is not relevant */ +#define SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE 0 +#endif + +/* This should be vamem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_rgb_gamma_vamem_params { + u16 gc[SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE]; +}; + +#endif /* __IA_CSS_GC2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_table.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_table.host.c new file mode 100644 index 000000000..347950119 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_table.host.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for memcpy() */ + +#include +#include "system_global.h" +#include "vamem.h" +#include "ia_css_types.h" +#include "ia_css_gc2_table.host.h" + +struct ia_css_rgb_gamma_table default_r_gamma_table; +struct ia_css_rgb_gamma_table default_g_gamma_table; +struct ia_css_rgb_gamma_table default_b_gamma_table; + +/* Identical default gamma table for R, G, and B. */ + + +static const uint16_t +default_gamma_table_data[IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE] = { + 0, 72, 144, 216, 288, 360, 426, 486, + 541, 592, 641, 687, 730, 772, 812, 850, + 887, 923, 958, 991, 1024, 1055, 1086, 1117, + 1146, 1175, 1203, 1230, 1257, 1284, 1310, 1335, + 1360, 1385, 1409, 1433, 1457, 1480, 1502, 1525, + 1547, 1569, 1590, 1612, 1632, 1653, 1674, 1694, + 1714, 1734, 1753, 1772, 1792, 1811, 1829, 1848, + 1866, 1884, 1902, 1920, 1938, 1955, 1973, 1990, + 2007, 2024, 2040, 2057, 2074, 2090, 2106, 2122, + 2138, 2154, 2170, 2185, 2201, 2216, 2231, 2247, + 2262, 2277, 2291, 2306, 2321, 2335, 2350, 2364, + 2378, 2393, 2407, 2421, 2435, 2449, 2462, 2476, + 2490, 2503, 2517, 2530, 2543, 2557, 2570, 2583, + 2596, 2609, 2622, 2634, 2647, 2660, 2673, 2685, + 2698, 2710, 2722, 2735, 2747, 2759, 2771, 2783, + 2795, 2807, 2819, 2831, 2843, 2855, 2867, 2878, + 2890, 2901, 2913, 2924, 2936, 2947, 2958, 2970, + 2981, 2992, 3003, 3014, 3025, 3036, 3047, 3058, + 3069, 3080, 3091, 3102, 3112, 3123, 3134, 3144, + 3155, 3165, 3176, 3186, 3197, 3207, 3217, 3228, + 3238, 3248, 3258, 3268, 3279, 3289, 3299, 3309, + 3319, 3329, 3339, 3349, 3358, 3368, 3378, 3388, + 3398, 3407, 3417, 3427, 3436, 3446, 3455, 3465, + 3474, 3484, 3493, 3503, 3512, 3521, 3531, 3540, + 3549, 3559, 3568, 3577, 3586, 3595, 3605, 3614, + 3623, 3632, 3641, 3650, 3659, 3668, 3677, 3686, + 3694, 3703, 3712, 3721, 3730, 3739, 3747, 3756, + 3765, 3773, 3782, 3791, 3799, 3808, 3816, 3825, + 3833, 3842, 3850, 3859, 3867, 3876, 3884, 3893, + 3901, 3909, 3918, 3926, 3934, 3942, 3951, 3959, + 3967, 3975, 3984, 3992, 4000, 4008, 4016, 4024, + 4032, 4040, 4048, 4056, 4064, 4072, 4080, 4088, + 4095 +}; + +void +ia_css_config_rgb_gamma_tables(void) +{ + default_r_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_2; + default_g_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_2; + default_b_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_2; + memcpy(default_r_gamma_table.data.vamem_2, default_gamma_table_data, + sizeof(default_gamma_table_data)); + memcpy(default_g_gamma_table.data.vamem_2, default_gamma_table_data, + sizeof(default_gamma_table_data)); + memcpy(default_b_gamma_table.data.vamem_2, default_gamma_table_data, + sizeof(default_gamma_table_data)); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_table.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_table.host.h new file mode 100644 index 000000000..13049fbfa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_table.host.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC2_TABLE_HOST_H +#define __IA_CSS_GC2_TABLE_HOST_H + +#include "ia_css_gc2_types.h" + +extern struct ia_css_rgb_gamma_table default_r_gamma_table; +extern struct ia_css_rgb_gamma_table default_g_gamma_table; +extern struct ia_css_rgb_gamma_table default_b_gamma_table; + +void ia_css_config_rgb_gamma_tables(void); + +#endif /* __IA_CSS_GC2_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_types.h new file mode 100644 index 000000000..ae16409d8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/gc/gc_2/ia_css_gc2_types.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC2_TYPES_H +#define __IA_CSS_GC2_TYPES_H + +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h" /* FIXME: needed for ia_css_vamem_type */ + +/* @file +* CSS-API header file for Gamma Correction parameters. +*/ + +/* sRGB Gamma table, used for sRGB Gamma Correction. + * + * ISP block: GC2 (sRGB Gamma Correction) + * (ISP1: GC1(YUV Gamma Correction) is used.) + * ISP2: GC2 is used. + */ + +/* Number of elements in the sRGB gamma table. */ +#define IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE_LOG2 8 +#define IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE BIT(IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE_LOG2) + +/* Number of elements in the sRGB gamma table. */ +#define IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE_LOG2 8 +#define IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE ((1U << IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE_LOG2) + 1) + +/** IA_CSS_VAMEM_TYPE_1(ISP2300) or + IA_CSS_VAMEM_TYPE_2(ISP2400) */ +union ia_css_rgb_gamma_data { + u16 vamem_1[IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE]; + /** RGB Gamma table on vamem type1. This table is not used, + because sRGB Gamma Correction is not implemented for ISP2300. */ + u16 vamem_2[IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE]; + /** RGB Gamma table on vamem type2. u0.12, [0,4095] */ +}; + +struct ia_css_rgb_gamma_table { + enum ia_css_vamem_type vamem_type; + union ia_css_rgb_gamma_data data; +}; + +#endif /* __IA_CSS_GC2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr.host.c new file mode 100644 index 000000000..85a02b6ad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr.host.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_hdr.host.h" + +void +ia_css_hdr_init_config( + struct sh_css_isp_hdr_params *to, + const struct ia_css_hdr_config *from, + unsigned int size) +{ + int i; + (void)size; + + for (i = 0; i < HDR_NUM_INPUT_FRAMES - 1; i++) { + to->irradiance.match_shift[i] = from->irradiance.match_shift[i]; + to->irradiance.match_mul[i] = from->irradiance.match_mul[i]; + to->irradiance.thr_low[i] = from->irradiance.thr_low[i]; + to->irradiance.thr_high[i] = from->irradiance.thr_high[i]; + to->irradiance.thr_coeff[i] = from->irradiance.thr_coeff[i]; + to->irradiance.thr_shift[i] = from->irradiance.thr_shift[i]; + } + to->irradiance.test_irr = from->irradiance.test_irr; + to->irradiance.weight_bpp = from->irradiance.weight_bpp; + + to->deghost.test_deg = from->deghost.test_deg; + to->exclusion.test_excl = from->exclusion.test_excl; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr.host.h new file mode 100644 index 000000000..83277b683 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr.host.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_HDR_HOST_H +#define __IA_CSS_HDR_HOST_H + +#include "ia_css_hdr_param.h" +#include "ia_css_hdr_types.h" + +extern const struct ia_css_hdr_config default_hdr_config; + +void +ia_css_hdr_init_config( + struct sh_css_isp_hdr_params *to, + const struct ia_css_hdr_config *from, + unsigned int size); + +#endif /* __IA_CSS_HDR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr_param.h new file mode 100644 index 000000000..998c6d801 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr_param.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_HDR_PARAMS_H +#define __IA_CSS_HDR_PARAMS_H + +#include "type_support.h" + +#define HDR_NUM_INPUT_FRAMES (3) + +/* HDR irradiance map parameters on ISP. */ +struct sh_css_hdr_irradiance_params { + s32 test_irr; + s32 match_shift[HDR_NUM_INPUT_FRAMES - + 1]; /* Histogram matching shift parameter */ + s32 match_mul[HDR_NUM_INPUT_FRAMES - + 1]; /* Histogram matching multiplication parameter */ + s32 thr_low[HDR_NUM_INPUT_FRAMES - + 1]; /* Weight map soft threshold low bound parameter */ + s32 thr_high[HDR_NUM_INPUT_FRAMES - + 1]; /* Weight map soft threshold high bound parameter */ + s32 thr_coeff[HDR_NUM_INPUT_FRAMES - + 1]; /* Soft threshold linear function coefficient */ + s32 thr_shift[HDR_NUM_INPUT_FRAMES - + 1]; /* Soft threshold precision shift parameter */ + s32 weight_bpp; /* Weight map bits per pixel */ +}; + +/* HDR deghosting parameters on ISP */ +struct sh_css_hdr_deghost_params { + s32 test_deg; +}; + +/* HDR exclusion parameters on ISP */ +struct sh_css_hdr_exclusion_params { + s32 test_excl; +}; + +/* HDR ISP parameters */ +struct sh_css_isp_hdr_params { + struct sh_css_hdr_irradiance_params irradiance; + struct sh_css_hdr_deghost_params deghost; + struct sh_css_hdr_exclusion_params exclusion; +}; + +#endif /* __IA_CSS_HDR_PARAMS_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr_types.h new file mode 100644 index 000000000..175c301ee --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/hdr/ia_css_hdr_types.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_HDR_TYPES_H +#define __IA_CSS_HDR_TYPES_H + +#define IA_CSS_HDR_MAX_NUM_INPUT_FRAMES (3) + +/** + * \brief HDR Irradiance Parameters + * \detail Currently HDR parameters are used only for testing purposes + */ +struct ia_css_hdr_irradiance_params { + int test_irr; /** Test parameter */ + int match_shift[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - + 1]; /** Histogram matching shift parameter */ + int match_mul[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - + 1]; /** Histogram matching multiplication parameter */ + int thr_low[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - + 1]; /** Weight map soft threshold low bound parameter */ + int thr_high[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - + 1]; /** Weight map soft threshold high bound parameter */ + int thr_coeff[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - + 1]; /** Soft threshold linear function coefficien */ + int thr_shift[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - + 1]; /** Soft threshold precision shift parameter */ + int weight_bpp; /** Weight map bits per pixel */ +}; + +/** + * \brief HDR Deghosting Parameters + * \detail Currently HDR parameters are used only for testing purposes + */ +struct ia_css_hdr_deghost_params { + int test_deg; /** Test parameter */ +}; + +/** + * \brief HDR Exclusion Parameters + * \detail Currently HDR parameters are used only for testing purposes + */ +struct ia_css_hdr_exclusion_params { + int test_excl; /** Test parameter */ +}; + +/** + * \brief HDR public paramterers. + * \details Struct with all parameters for HDR that can be seet from + * the CSS API. Currenly, only test parameters are defined. + */ +struct ia_css_hdr_config { + struct ia_css_hdr_irradiance_params irradiance; /** HDR irradiance parameters */ + struct ia_css_hdr_deghost_params deghost; /** HDR deghosting parameters */ + struct ia_css_hdr_exclusion_params exclusion; /** HDR exclusion parameters */ +}; + +#endif /* __IA_CSS_HDR_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.c new file mode 100644 index 000000000..0091e2a3d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_bayer_io.host.h" +#include "dma.h" +#include "math_support.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "ia_css_isp_params.h" +#include "ia_css_frame.h" + +int ia_css_bayer_io_config(const struct ia_css_binary *binary, + const struct sh_css_binary_args *args) +{ + const struct ia_css_frame *in_frame = args->in_frame; + const struct ia_css_frame **out_frames = (const struct ia_css_frame **) + &args->out_frame; + const struct ia_css_frame_info *in_frame_info = ia_css_frame_get_info(in_frame); + const unsigned int ddr_bits_per_element = sizeof(short) * 8; + const unsigned int ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, + ddr_bits_per_element); + unsigned int size_get = 0, size_put = 0; + unsigned int offset = 0; + int ret; + + if (binary->info->mem_offsets.offsets.param) { + size_get = binary->info->mem_offsets.offsets.param->dmem.get.size; + offset = binary->info->mem_offsets.offsets.param->dmem.get.offset; + } + + if (size_get) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_bayer_io_config() get part enter:\n"); +#endif + + ret = ia_css_dma_configure_from_info(&config, in_frame_info); + if (ret) + return ret; + // The base_address of the input frame will be set in the ISP + to->width = in_frame_info->res.width; + to->height = in_frame_info->res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_bayer_io_config() get part leave:\n"); +#endif + } + + if (binary->info->mem_offsets.offsets.param) { + size_put = binary->info->mem_offsets.offsets.param->dmem.put.size; + offset = binary->info->mem_offsets.offsets.param->dmem.put.offset; + } + + if (size_put) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_bayer_io_config() put part enter:\n"); +#endif + + ret = ia_css_dma_configure_from_info(&config, &out_frames[0]->frame_info); + if (ret) + return ret; + to->base_address = out_frames[0]->data; + to->width = out_frames[0]->frame_info.res.width; + to->height = out_frames[0]->frame_info.res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_bayer_io_config() put part leave:\n"); +#endif + } + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.h new file mode 100644 index 000000000..9c7e5a1ad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __BAYER_IO_HOST_H +#define __BAYER_IO_HOST_H + +#include "ia_css_bayer_io_param.h" +#include "ia_css_bayer_io_types.h" +#include "ia_css_binary.h" +#include "sh_css_internal.h" + +int ia_css_bayer_io_config(const struct ia_css_binary *binary, + const struct sh_css_binary_args *args); + +#endif /*__BAYER_IO_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_param.h new file mode 100644 index 000000000..283ace838 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_param.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BAYER_IO_PARAM +#define __IA_CSS_BAYER_IO_PARAM + +#include "../common/ia_css_common_io_param.h" + +#endif /* __IA_CSS_BAYER_IO_PARAM */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_types.h new file mode 100644 index 000000000..d06d25c9b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_types.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BAYER_IO_TYPES_H +#define __IA_CSS_BAYER_IO_TYPES_H + +#include "../common/ia_css_common_io_types.h" + +#endif /* __IA_CSS_BAYER_IO_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/common/ia_css_common_io_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/common/ia_css_common_io_param.h new file mode 100644 index 000000000..5e0e4cd5b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/common/ia_css_common_io_param.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_COMMON_IO_PARAM +#define __IA_CSS_COMMON_IO_PARAM + +#include "../common/ia_css_common_io_types.h" + +#endif /* __IA_CSS_COMMON_IO_PARAM */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/common/ia_css_common_io_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/common/ia_css_common_io_types.h new file mode 100644 index 000000000..0801481c4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/common/ia_css_common_io_types.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_COMMON_IO_TYPES +#define __IA_CSS_COMMON_IO_TYPES + +#define MAX_IO_DMA_CHANNELS 3 + +struct ia_css_common_io_config { + unsigned int base_address; + unsigned int width; + unsigned int height; + unsigned int stride; + unsigned int ddr_elems_per_word; + unsigned int dma_channel[MAX_IO_DMA_CHANNELS]; +}; + +#endif /* __IA_CSS_COMMON_IO_TYPES */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.c new file mode 100644 index 000000000..32c504a95 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#include "ia_css_yuv444_io.host.h" +#include "dma.h" +#include "math_support.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "ia_css_isp_params.h" +#include "ia_css_frame.h" + +int ia_css_yuv444_io_config(const struct ia_css_binary *binary, + const struct sh_css_binary_args *args) +{ + const struct ia_css_frame *in_frame = args->in_frame; + const struct ia_css_frame **out_frames = (const struct ia_css_frame **) + &args->out_frame; + const struct ia_css_frame_info *in_frame_info = ia_css_frame_get_info(in_frame); + const unsigned int ddr_bits_per_element = sizeof(short) * 8; + const unsigned int ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, + ddr_bits_per_element); + unsigned int size_get = 0, size_put = 0; + unsigned int offset = 0; + int ret; + + if (binary->info->mem_offsets.offsets.param) { + size_get = binary->info->mem_offsets.offsets.param->dmem.get.size; + offset = binary->info->mem_offsets.offsets.param->dmem.get.offset; + } + + if (size_get) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_yuv444_io_config() get part enter:\n"); +#endif + + ret = ia_css_dma_configure_from_info(&config, in_frame_info); + if (ret) + return ret; + + // The base_address of the input frame will be set in the ISP + to->width = in_frame_info->res.width; + to->height = in_frame_info->res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_yuv444_io_config() get part leave:\n"); +#endif + } + + if (binary->info->mem_offsets.offsets.param) { + size_put = binary->info->mem_offsets.offsets.param->dmem.put.size; + offset = binary->info->mem_offsets.offsets.param->dmem.put.offset; + } + + if (size_put) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_yuv444_io_config() put part enter:\n"); +#endif + + ret = ia_css_dma_configure_from_info(&config, &out_frames[0]->frame_info); + if (ret) + return ret; + + to->base_address = out_frames[0]->data; + to->width = out_frames[0]->frame_info.res.width; + to->height = out_frames[0]->frame_info.res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_yuv444_io_config() put part leave:\n"); +#endif + } + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.h new file mode 100644 index 000000000..13e50590f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __YUV444_IO_HOST_H +#define __YUV444_IO_HOST_H + +#include "ia_css_yuv444_io_param.h" +#include "ia_css_yuv444_io_types.h" +#include "ia_css_binary.h" +#include "sh_css_internal.h" + +int ia_css_yuv444_io_config(const struct ia_css_binary *binary, + const struct sh_css_binary_args *args); + +#endif /*__YUV44_IO_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h new file mode 100644 index 000000000..9b7537d50 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_YUV444_IO_PARAM +#define __IA_CSS_YUV444_IO_PARAM + +#include "../common/ia_css_common_io_param.h" + +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h new file mode 100644 index 000000000..137a2a05c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_YUV444_IO_TYPES +#define __IA_CSS_YUV444_IO_TYPES + +#include "../common/ia_css_common_io_types.h" + +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.c new file mode 100644 index 000000000..5f186fb03 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_iterator.host.h" +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" +#include "ia_css_err.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" + +static const struct ia_css_iterator_configuration default_config = { + .input_info = (struct ia_css_frame_info *)NULL, +}; + +void +ia_css_iterator_config( + struct sh_css_isp_iterator_isp_config *to, + const struct ia_css_iterator_configuration *from, + unsigned int size) +{ + (void)size; + ia_css_frame_info_to_frame_sp_info(&to->input_info, from->input_info); + ia_css_frame_info_to_frame_sp_info(&to->internal_info, from->internal_info); + ia_css_frame_info_to_frame_sp_info(&to->output_info, from->output_info); + ia_css_frame_info_to_frame_sp_info(&to->vf_info, from->vf_info); + ia_css_resolution_to_sp_resolution(&to->dvs_envelope, from->dvs_envelope); +} + +int ia_css_iterator_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *in_info) +{ + struct ia_css_frame_info my_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + struct ia_css_iterator_configuration config = default_config; + + config.input_info = &binary->in_frame_info; + config.internal_info = &binary->internal_frame_info; + config.output_info = &binary->out_frame_info[0]; + config.vf_info = &binary->vf_frame_info; + config.dvs_envelope = &binary->dvs_envelope; + + /* Use in_info iso binary->in_frame_info. + * They can differ in padded width in case of scaling, e.g. for capture_pp. + * Find out why. + */ + if (in_info) + config.input_info = in_info; + if (binary->out_frame_info[0].res.width == 0) + config.output_info = &binary->out_frame_info[1]; + my_info = *config.output_info; + config.output_info = &my_info; + /* we do this only for preview pipe because in fill_binary_info function + * we assign vf_out res to out res, but for ISP internal processing, we need + * the original out res. for video pipe, it has two output pins --- out and + * vf_out, so it can keep these two resolutions already. */ + if (binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_PREVIEW && + binary->vf_downscale_log2 > 0) + { + /* TODO: Remove this after preview output decimation is fixed + * by configuring out&vf info files properly */ + my_info.padded_width <<= binary->vf_downscale_log2; + my_info.res.width <<= binary->vf_downscale_log2; + my_info.res.height <<= binary->vf_downscale_log2; + } + + return ia_css_configure_iterator(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h new file mode 100644 index 000000000..1419fa9a0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ITERATOR_HOST_H +#define __IA_CSS_ITERATOR_HOST_H + +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" +#include "ia_css_err.h" +#include "ia_css_iterator_param.h" + +void +ia_css_iterator_config( + struct sh_css_isp_iterator_isp_config *to, + const struct ia_css_iterator_configuration *from, + unsigned int size); + +int +ia_css_iterator_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *in_info); + +#endif /* __IA_CSS_ITERATOR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator_param.h new file mode 100644 index 000000000..e062f8d06 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/iterator/iterator_1.0/ia_css_iterator_param.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ITERATOR_PARAM_H +#define __IA_CSS_ITERATOR_PARAM_H + +#include "ia_css_types.h" /* ia_css_resolution */ +#include "ia_css_frame_public.h" /* ia_css_frame_info */ +#include "ia_css_frame_comm.h" /* ia_css_frame_sp_info */ + +struct ia_css_iterator_configuration { + const struct ia_css_frame_info *input_info; + const struct ia_css_frame_info *internal_info; + const struct ia_css_frame_info *output_info; + const struct ia_css_frame_info *vf_info; + const struct ia_css_resolution *dvs_envelope; +}; + +struct sh_css_isp_iterator_isp_config { + struct ia_css_frame_sp_info input_info; + struct ia_css_frame_sp_info internal_info; + struct ia_css_frame_sp_info output_info; + struct ia_css_frame_sp_info vf_info; + struct ia_css_sp_resolution dvs_envelope; +}; + +#endif /* __IA_CSS_ITERATOR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c new file mode 100644 index 000000000..a70bce117 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" + +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif + +#include "ia_css_macc1_5.host.h" + +const struct ia_css_macc1_5_config default_macc1_5_config = { + 1 +}; + +void +ia_css_macc1_5_encode( + struct sh_css_isp_macc1_5_params *to, + const struct ia_css_macc1_5_config *from, + unsigned int size) +{ + (void)size; + to->exp = from->exp; +} + +void +ia_css_macc1_5_vmem_encode( + struct sh_css_isp_macc1_5_vmem_params *params, + const struct ia_css_macc1_5_table *from, + unsigned int size) +{ + unsigned int i, j, k, idx; + static const unsigned int idx_map[] = { + 0, 1, 3, 2, 6, 7, 5, 4, 12, 13, 15, 14, 10, 11, 9, 8 + }; + + (void)size; + + for (k = 0; k < 4; k++) + for (i = 0; i < IA_CSS_MACC_NUM_AXES; i++) { + idx = idx_map[i] + (k * IA_CSS_MACC_NUM_AXES); + j = 4 * i; + + params->data[0][(idx)] = from->data[j]; + params->data[1][(idx)] = from->data[j + 1]; + params->data[2][(idx)] = from->data[j + 2]; + params->data[3][(idx)] = from->data[j + 3]; + } +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_macc1_5_debug_dtrace( + const struct ia_css_macc1_5_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.exp=%d\n", + config->exp); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h new file mode 100644 index 000000000..6c1189e1d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC1_5_HOST_H +#define __IA_CSS_MACC1_5_HOST_H + +#include "ia_css_macc1_5_param.h" +#include "ia_css_macc1_5_table.host.h" + +extern const struct ia_css_macc1_5_config default_macc1_5_config; + +void +ia_css_macc1_5_encode( + struct sh_css_isp_macc1_5_params *to, + const struct ia_css_macc1_5_config *from, + unsigned int size); + +void +ia_css_macc1_5_vmem_encode( + struct sh_css_isp_macc1_5_vmem_params *params, + const struct ia_css_macc1_5_table *from, + unsigned int size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_macc1_5_debug_dtrace( + const struct ia_css_macc1_5_config *config, + unsigned int level); +#endif +#endif /* __IA_CSS_MACC1_5_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_param.h new file mode 100644 index 000000000..66b8fb259 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_param.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC1_5_PARAM_H +#define __IA_CSS_MACC1_5_PARAM_H + +#include "type_support.h" +#include "vmem.h" +#include "ia_css_macc1_5_types.h" + +/* MACC */ +struct sh_css_isp_macc1_5_params { + s32 exp; +}; + +struct sh_css_isp_macc1_5_vmem_params { + VMEM_ARRAY(data, IA_CSS_MACC_NUM_COEFS * ISP_NWAY); +}; + +#endif /* __IA_CSS_MACC1_5_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.c new file mode 100644 index 000000000..d205d64e0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" +#include "ia_css_types.h" +#include "ia_css_macc1_5_table.host.h" + +/* Multi-Axes Color Correction table for ISP2. + * 64values = 2x2matrix for 16area, [s1.12] + * ineffective: 16 of "identity 2x2 matix" {4096,0,0,4096} + */ +const struct ia_css_macc1_5_table default_macc1_5_table = { + { + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096 + } +}; diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.h new file mode 100644 index 000000000..d451efbaa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC1_5_TABLE_HOST_H +#define __IA_CSS_MACC1_5_TABLE_HOST_H + +#include "macc/macc1_5/ia_css_macc1_5_types.h" + +extern const struct ia_css_macc1_5_table default_macc1_5_table; + +#endif /* __IA_CSS_MACC1_5_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_types.h new file mode 100644 index 000000000..5492af0df --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5_types.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC1_5_TYPES_H +#define __IA_CSS_MACC1_5_TYPES_H + +/* @file +* CSS-API header file for Multi-Axis Color Conversion algorithm parameters. +*/ + +/* Multi-Axis Color Conversion configuration + * + * ISP2.6.1: MACC1_5 is used. + */ + +/* Number of axes in the MACC table. */ +#define IA_CSS_MACC_NUM_AXES 16 +/* Number of coefficients per MACC axes. */ +#define IA_CSS_MACC_NUM_COEFS 4 + +/* Multi-Axes Color Correction (MACC) table. + * + * ISP block: MACC (MACC by only matrix) + * MACC1_5 (MACC by matrix and exponent(ia_css_macc_config)) + * ISP1: MACC is used. + * ISP2: MACC1_5 is used. + * + * [MACC] + * OutU = (data00 * InU + data01 * InV) >> 13 + * OutV = (data10 * InU + data11 * InV) >> 13 + * + * default/ineffective: + * OutU = (8192 * InU + 0 * InV) >> 13 + * OutV = ( 0 * InU + 8192 * InV) >> 13 + * + * [MACC1_5] + * OutU = (data00 * InU + data01 * InV) >> (13 - exp) + * OutV = (data10 * InU + data11 * InV) >> (13 - exp) + * + * default/ineffective: (exp=1) + * OutU = (4096 * InU + 0 * InV) >> (13 - 1) + * OutV = ( 0 * InU + 4096 * InV) >> (13 - 1) + */ +struct ia_css_macc1_5_table { + s16 data[IA_CSS_MACC_NUM_COEFS * IA_CSS_MACC_NUM_AXES]; + /** 16 of 2x2 matix + MACC1_5: s[macc_config.exp].[13-macc_config.exp], [-8192,8191] + default/ineffective: (s1.12) + 16 of "identity 2x2 matix" {4096,0,0,4096} */ +}; + +/* Multi-Axes Color Correction (MACC) configuration. + * + * ISP block: MACC1_5 (MACC by matrix and exponent(ia_css_macc_config)) + * ISP2: MACC1_5 is used. + */ +struct ia_css_macc1_5_config { + u8 exp; /** Common exponent of ia_css_macc_table. + u8.0, [0,13], default 1, ineffective 1 */ +}; + +#endif /* __IA_CSS_MACC1_5_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc.host.c new file mode 100644 index 000000000..f2d3832a0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc.host.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "ia_css_macc.host.h" + +const struct ia_css_macc_config default_macc_config = { + 1, +}; + +void +ia_css_macc_encode( + struct sh_css_isp_macc_params *to, + const struct ia_css_macc_config *from, + unsigned int size) +{ + (void)size; + to->exp = from->exp; +} + +void +ia_css_macc_dump( + const struct sh_css_isp_macc_params *macc, + unsigned int level); + +void +ia_css_macc_debug_dtrace( + const struct ia_css_macc_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.exp=%d\n", + config->exp); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc.host.h new file mode 100644 index 000000000..912db9254 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc.host.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC_HOST_H +#define __IA_CSS_MACC_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_macc_param.h" +#include "ia_css_macc_table.host.h" + +extern const struct ia_css_macc_config default_macc_config; + +void +ia_css_macc_encode( + struct sh_css_isp_macc_params *to, + const struct ia_css_macc_config *from, + unsigned int size); + +void +ia_css_macc_dump( + const struct sh_css_isp_macc_params *macc, + unsigned int level); + +void +ia_css_macc_debug_dtrace( + const struct ia_css_macc_config *config, + unsigned int level); + +#endif /* __IA_CSS_MACC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_param.h new file mode 100644 index 000000000..71665204e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_param.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC_PARAM_H +#define __IA_CSS_MACC_PARAM_H + +#include "type_support.h" + +/* MACC */ +struct sh_css_isp_macc_params { + s32 exp; +}; + +#endif /* __IA_CSS_MACC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.c new file mode 100644 index 000000000..946b074e8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" +#include "ia_css_types.h" +#include "ia_css_macc_table.host.h" + +/* Multi-Axes Color Correction table for ISP1. + * 64values = 2x2matrix for 16area, [s2.13] + * ineffective: 16 of "identity 2x2 matix" {8192,0,0,8192} + */ +const struct ia_css_macc_table default_macc_table = { + { + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192 + } +}; + +/* Multi-Axes Color Correction table for ISP2. + * 64values = 2x2matrix for 16area, [s1.12] + * ineffective: 16 of "identity 2x2 matix" {4096,0,0,4096} + */ +const struct ia_css_macc_table default_macc2_table = { + { + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096 + } +}; diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.h new file mode 100644 index 000000000..35099cb79 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC_TABLE_HOST_H +#define __IA_CSS_MACC_TABLE_HOST_H + +#include "ia_css_macc_types.h" + +extern const struct ia_css_macc_table default_macc_table; +extern const struct ia_css_macc_table default_macc2_table; + +#endif /* __IA_CSS_MACC_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_types.h new file mode 100644 index 000000000..172a518cb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/macc/macc_1.0/ia_css_macc_types.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC_TYPES_H +#define __IA_CSS_MACC_TYPES_H + +/* @file +* CSS-API header file for Multi-Axis Color Correction (MACC) parameters. +*/ + +/* Number of axes in the MACC table. */ +#define IA_CSS_MACC_NUM_AXES 16 +/* Number of coefficients per MACC axes. */ +#define IA_CSS_MACC_NUM_COEFS 4 +/* The number of planes in the morphing table. */ + +/* Multi-Axis Color Correction (MACC) table. + * + * ISP block: MACC1 (MACC by only matrix) + * MACC2 (MACC by matrix and exponent(ia_css_macc_config)) + * ISP1: MACC1 is used. + * ISP2: MACC2 is used. + * + * [MACC1] + * OutU = (data00 * InU + data01 * InV) >> 13 + * OutV = (data10 * InU + data11 * InV) >> 13 + * + * default/ineffective: + * OutU = (8192 * InU + 0 * InV) >> 13 + * OutV = ( 0 * InU + 8192 * InV) >> 13 + * + * [MACC2] + * OutU = (data00 * InU + data01 * InV) >> (13 - exp) + * OutV = (data10 * InU + data11 * InV) >> (13 - exp) + * + * default/ineffective: (exp=1) + * OutU = (4096 * InU + 0 * InV) >> (13 - 1) + * OutV = ( 0 * InU + 4096 * InV) >> (13 - 1) + */ + +struct ia_css_macc_table { + s16 data[IA_CSS_MACC_NUM_COEFS * IA_CSS_MACC_NUM_AXES]; + /** 16 of 2x2 matix + MACC1: s2.13, [-65536,65535] + default/ineffective: + 16 of "identity 2x2 matix" {8192,0,0,8192} + MACC2: s[macc_config.exp].[13-macc_config.exp], [-8192,8191] + default/ineffective: (s1.12) + 16 of "identity 2x2 matix" {4096,0,0,4096} */ +}; + +#endif /* __IA_CSS_MACC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm.host.c new file mode 100644 index 000000000..69283b631 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm.host.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_norm.host.h" diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm.host.h new file mode 100644 index 000000000..3987abcae --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm.host.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_NORM_HOST_H +#define __IA_CSS_NORM_HOST_H + +#include "ia_css_norm_param.h" + +#endif /* __IA_CSS_NORM_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm_param.h new file mode 100644 index 000000000..06c39fdfc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/norm/norm_1.0/ia_css_norm_param.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_NORM_PARAM_H +#define __IA_CSS_NORM_PARAM_H + +#endif /* __IA_CSS_NORM_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2.host.c new file mode 100644 index 000000000..c4ffff630 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2.host.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "sh_css_frac.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "isp.h" +#include "ia_css_ob2.host.h" + +const struct ia_css_ob2_config default_ob2_config = { + 0, + 0, + 0, + 0 +}; + +void +ia_css_ob2_encode( + struct sh_css_isp_ob2_params *to, + const struct ia_css_ob2_config *from, + unsigned int size) +{ + (void)size; + + /* Blacklevels types are u0_16 */ + to->blacklevel_gr = uDIGIT_FITTING(from->level_gr, 16, SH_CSS_BAYER_BITS); + to->blacklevel_r = uDIGIT_FITTING(from->level_r, 16, SH_CSS_BAYER_BITS); + to->blacklevel_b = uDIGIT_FITTING(from->level_b, 16, SH_CSS_BAYER_BITS); + to->blacklevel_gb = uDIGIT_FITTING(from->level_gb, 16, SH_CSS_BAYER_BITS); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ob2_dump( + const struct sh_css_isp_ob2_params *ob2, + unsigned int level) +{ + if (!ob2) + return; + + ia_css_debug_dtrace(level, "Optical Black 2:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob2_blacklevel_gr", ob2->blacklevel_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob2_blacklevel_r", ob2->blacklevel_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob2_blacklevel_b", ob2->blacklevel_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob2_blacklevel_gb", ob2->blacklevel_gb); +} + +void +ia_css_ob2_debug_dtrace( + const struct ia_css_ob2_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.level_gr=%d, config.level_r=%d, config.level_b=%d, config.level_gb=%d, ", + config->level_gr, config->level_r, + config->level_b, config->level_gb); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2.host.h new file mode 100644 index 000000000..26c2e4320 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2.host.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB2_HOST_H +#define __IA_CSS_OB2_HOST_H + +#include "ia_css_ob2_types.h" +#include "ia_css_ob2_param.h" + +extern const struct ia_css_ob2_config default_ob2_config; + +void +ia_css_ob2_encode( + struct sh_css_isp_ob2_params *to, + const struct ia_css_ob2_config *from, + unsigned int size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ob2_dump( + const struct sh_css_isp_ob2_params *ob2, + unsigned int level); + +void +ia_css_ob2_debug_dtrace( + const struct ia_css_ob2_config *config, unsigned int level); +#endif + +#endif /* __IA_CSS_OB2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2_param.h new file mode 100644 index 000000000..c3c9fc3f9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2_param.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB2_PARAM_H +#define __IA_CSS_OB2_PARAM_H + +#include "type_support.h" + +/* OB2 (Optical Black) */ +struct sh_css_isp_ob2_params { + s32 blacklevel_gr; + s32 blacklevel_r; + s32 blacklevel_b; + s32 blacklevel_gb; +}; + +#endif /* __IA_CSS_OB2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2_types.h new file mode 100644 index 000000000..51e4c35cf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob2/ia_css_ob2_types.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB2_TYPES_H +#define __IA_CSS_OB2_TYPES_H + +/* @file +* CSS-API header file for Optical Black algorithm parameters. +*/ + +/* Optical Black configuration + * + * ISP2.6.1: OB2 is used. + */ + +#include "ia_css_frac.h" + +struct ia_css_ob2_config { + ia_css_u0_16 level_gr; /** Black level for GR pixels. + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_r; /** Black level for R pixels. + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_b; /** Black level for B pixels. + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_gb; /** Black level for GB pixels. + u0.16, [0,65535], + default/ineffective 0 */ +}; + +#endif /* __IA_CSS_OB2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob.host.c new file mode 100644 index 000000000..12191cd36 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob.host.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "isp.h" + +#include "ia_css_ob.host.h" + +const struct ia_css_ob_config default_ob_config = { + IA_CSS_OB_MODE_NONE, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* TODO: include ob.isp.h to get isp knowledge and + add assert on platform restrictions */ + +void +ia_css_ob_configure( + struct sh_css_isp_ob_stream_config *config, + unsigned int isp_pipe_version, + unsigned int raw_bit_depth) +{ + config->isp_pipe_version = isp_pipe_version; + config->raw_bit_depth = raw_bit_depth; +} + +void +ia_css_ob_encode( + struct sh_css_isp_ob_params *to, + const struct ia_css_ob_config *from, + const struct sh_css_isp_ob_stream_config *config, + unsigned int size) +{ + unsigned int ob_bit_depth + = config->isp_pipe_version == 2 ? SH_CSS_BAYER_BITS : config->raw_bit_depth; + unsigned int scale = 16 - ob_bit_depth; + + (void)size; + switch (from->mode) { + case IA_CSS_OB_MODE_FIXED: + to->blacklevel_gr = from->level_gr >> scale; + to->blacklevel_r = from->level_r >> scale; + to->blacklevel_b = from->level_b >> scale; + to->blacklevel_gb = from->level_gb >> scale; + to->area_start_bq = 0; + to->area_length_bq = 0; + to->area_length_bq_inverse = 0; + break; + case IA_CSS_OB_MODE_RASTER: + to->blacklevel_gr = 0; + to->blacklevel_r = 0; + to->blacklevel_b = 0; + to->blacklevel_gb = 0; + to->area_start_bq = from->start_position; + to->area_length_bq = + (from->end_position - from->start_position) + 1; + to->area_length_bq_inverse = AREA_LENGTH_UNIT / to->area_length_bq; + break; + default: + to->blacklevel_gr = 0; + to->blacklevel_r = 0; + to->blacklevel_b = 0; + to->blacklevel_gb = 0; + to->area_start_bq = 0; + to->area_length_bq = 0; + to->area_length_bq_inverse = 0; + break; + } +} + +void +ia_css_ob_vmem_encode( + struct sh_css_isp_ob_vmem_params *to, + const struct ia_css_ob_config *from, + const struct sh_css_isp_ob_stream_config *config, + unsigned int size) +{ + struct sh_css_isp_ob_params tmp; + struct sh_css_isp_ob_params *ob = &tmp; + + (void)size; + ia_css_ob_encode(&tmp, from, config, sizeof(tmp)); + + { + unsigned int i; + unsigned int sp_obarea_start_bq = ob->area_start_bq; + unsigned int sp_obarea_length_bq = ob->area_length_bq; + unsigned int low = sp_obarea_start_bq; + unsigned int high = low + sp_obarea_length_bq; + u16 all_ones = ~0; + + for (i = 0; i < OBAREA_MASK_SIZE; i++) { + if (i >= low && i < high) + to->vmask[i / ISP_VEC_NELEMS][i % ISP_VEC_NELEMS] = all_ones; + else + to->vmask[i / ISP_VEC_NELEMS][i % ISP_VEC_NELEMS] = 0; + } + } +} + +void +ia_css_ob_dump( + const struct sh_css_isp_ob_params *ob, + unsigned int level) +{ + if (!ob) return; + ia_css_debug_dtrace(level, "Optical Black:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob_blacklevel_gr", ob->blacklevel_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob_blacklevel_r", ob->blacklevel_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob_blacklevel_b", ob->blacklevel_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob_blacklevel_gb", ob->blacklevel_gb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "obarea_start_bq", ob->area_start_bq); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "obarea_length_bq", ob->area_length_bq); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "obarea_length_bq_inverse", + ob->area_length_bq_inverse); +} + +void +ia_css_ob_debug_dtrace( + const struct ia_css_ob_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.mode=%d, config.level_gr=%d, config.level_r=%d, config.level_b=%d, config.level_gb=%d, config.start_position=%d, config.end_position=%d\n", + config->mode, + config->level_gr, config->level_r, + config->level_b, config->level_gb, + config->start_position, config->end_position); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob.host.h new file mode 100644 index 000000000..dfcac0c64 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob.host.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB_HOST_H +#define __IA_CSS_OB_HOST_H + +#include "ia_css_ob_types.h" +#include "ia_css_ob_param.h" + +extern const struct ia_css_ob_config default_ob_config; + +void +ia_css_ob_configure( + struct sh_css_isp_ob_stream_config *config, + unsigned int isp_pipe_version, + unsigned int raw_bit_depth); + +void +ia_css_ob_encode( + struct sh_css_isp_ob_params *to, + const struct ia_css_ob_config *from, + const struct sh_css_isp_ob_stream_config *config, + unsigned int size); + +void +ia_css_ob_vmem_encode( + struct sh_css_isp_ob_vmem_params *to, + const struct ia_css_ob_config *from, + const struct sh_css_isp_ob_stream_config *config, + unsigned int size); + +void +ia_css_ob_dump( + const struct sh_css_isp_ob_params *ob, + unsigned int level); + +void +ia_css_ob_debug_dtrace( + const struct ia_css_ob_config *config, unsigned int level) +; + +#endif /* __IA_CSS_OB_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob_param.h new file mode 100644 index 000000000..991aa3c40 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob_param.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB_PARAM_H +#define __IA_CSS_OB_PARAM_H + +#include "type_support.h" +#include "vmem.h" + +#define OBAREA_MASK_SIZE 64 +#define OBAREA_LENGTHBQ_INVERSE_SHIFT 12 + +/* AREA_LENGTH_UNIT is dependent on NWAY, requires rewrite */ +#define AREA_LENGTH_UNIT BIT(12) + +/* OB (Optical Black) */ +struct sh_css_isp_ob_stream_config { + unsigned int isp_pipe_version; + unsigned int raw_bit_depth; +}; + +struct sh_css_isp_ob_params { + s32 blacklevel_gr; + s32 blacklevel_r; + s32 blacklevel_b; + s32 blacklevel_gb; + s32 area_start_bq; + s32 area_length_bq; + s32 area_length_bq_inverse; +}; + +struct sh_css_isp_ob_vmem_params { + VMEM_ARRAY(vmask, OBAREA_MASK_SIZE); +}; + +#endif /* __IA_CSS_OB_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob_types.h new file mode 100644 index 000000000..b74296517 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ob/ob_1.0/ia_css_ob_types.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB_TYPES_H +#define __IA_CSS_OB_TYPES_H + +/* @file +* CSS-API header file for Optical Black level parameters. +*/ + +#include "ia_css_frac.h" + +/* Optical black mode. + */ +enum ia_css_ob_mode { + IA_CSS_OB_MODE_NONE, /** OB has no effect. */ + IA_CSS_OB_MODE_FIXED, /** Fixed OB */ + IA_CSS_OB_MODE_RASTER /** Raster OB */ +}; + +/* Optical Black level configuration. + * + * ISP block: OB1 + * ISP1: OB1 is used. + * ISP2: OB1 is used. + */ +struct ia_css_ob_config { + enum ia_css_ob_mode mode; /** Mode (None / Fixed / Raster). + enum, [0,2], + default 1, ineffective 0 */ + ia_css_u0_16 level_gr; /** Black level for GR pixels + (used for Fixed Mode only). + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_r; /** Black level for R pixels + (used for Fixed Mode only). + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_b; /** Black level for B pixels + (used for Fixed Mode only). + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_gb; /** Black level for GB pixels + (used for Fixed Mode only). + u0.16, [0,65535], + default/ineffective 0 */ + u16 start_position; /** Start position of OB area + (used for Raster Mode only). + u16.0, [0,63], + default/ineffective 0 */ + u16 end_position; /** End position of OB area + (used for Raster Mode only). + u16.0, [0,63], + default/ineffective 0 */ +}; + +#endif /* __IA_CSS_OB_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output.host.c new file mode 100644 index 000000000..be9e4ef29 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output.host.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_frame.h" +#include "ia_css_debug.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "ia_css_output.host.h" +#include "isp.h" + +#include "assert_support.h" + +const struct ia_css_output_config default_output_config = { + 0, + 0 +}; + +static const struct ia_css_output_configuration default_output_configuration = { + .info = (struct ia_css_frame_info *)NULL, +}; + +static const struct ia_css_output0_configuration default_output0_configuration + = { + .info = (struct ia_css_frame_info *)NULL, +}; + +static const struct ia_css_output1_configuration default_output1_configuration + = { + .info = (struct ia_css_frame_info *)NULL, +}; + +void +ia_css_output_encode( + struct sh_css_isp_output_params *to, + const struct ia_css_output_config *from, + unsigned int size) +{ + (void)size; + to->enable_hflip = from->enable_hflip; + to->enable_vflip = from->enable_vflip; +} + +int ia_css_output_config(struct sh_css_isp_output_isp_config *to, + const struct ia_css_output_configuration *from, + unsigned int size) +{ + unsigned int elems_a = ISP_VEC_NELEMS; + int ret; + + ret = ia_css_dma_configure_from_info(&to->port_b, from->info); + if (ret) + return ret; + + to->width_a_over_b = elems_a / to->port_b.elems; + to->height = from->info ? from->info->res.height : 0; + to->enable = from->info != NULL; + ia_css_frame_info_to_frame_sp_info(&to->info, from->info); + + /* Assume divisiblity here, may need to generalize to fixed point. */ + if (elems_a % to->port_b.elems != 0) + return -EINVAL; + + return 0; +} + +int ia_css_output0_config(struct sh_css_isp_output_isp_config *to, + const struct ia_css_output0_configuration *from, + unsigned int size) +{ + return ia_css_output_config(to, (const struct ia_css_output_configuration *)from, size); +} + +int ia_css_output1_config(struct sh_css_isp_output_isp_config *to, + const struct ia_css_output1_configuration *from, + unsigned int size) +{ + return ia_css_output_config(to, (const struct ia_css_output_configuration *)from, size); +} + +int ia_css_output_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + if (info) { + struct ia_css_output_configuration config = + default_output_configuration; + + config.info = info; + + return ia_css_configure_output(binary, &config); + } + return 0; +} + +int ia_css_output0_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + if (info) { + struct ia_css_output0_configuration config = + default_output0_configuration; + + config.info = info; + + return ia_css_configure_output0(binary, &config); + } + return 0; +} + +int ia_css_output1_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + if (info) { + struct ia_css_output1_configuration config = + default_output1_configuration; + + config.info = info; + + return ia_css_configure_output1(binary, &config); + } + return 0; +} + +void +ia_css_output_dump( + const struct sh_css_isp_output_params *output, + unsigned int level) +{ + if (!output) return; + ia_css_debug_dtrace(level, "Horizontal Output Flip:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "enable", output->enable_hflip); + ia_css_debug_dtrace(level, "Vertical Output Flip:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "enable", output->enable_vflip); +} + +void +ia_css_output_debug_dtrace( + const struct ia_css_output_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.enable_hflip=%d", + config->enable_hflip); + ia_css_debug_dtrace(level, + "config.enable_vflip=%d", + config->enable_vflip); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output.host.h new file mode 100644 index 000000000..c8523e95a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output.host.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OUTPUT_HOST_H +#define __IA_CSS_OUTPUT_HOST_H + +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" + +#include "ia_css_output_types.h" +#include "ia_css_output_param.h" + +extern const struct ia_css_output_config default_output_config; + +void +ia_css_output_encode( + struct sh_css_isp_output_params *to, + const struct ia_css_output_config *from, + unsigned int size); + +int ia_css_output_config(struct sh_css_isp_output_isp_config *to, + const struct ia_css_output_configuration *from, + unsigned int size); + +int ia_css_output0_config(struct sh_css_isp_output_isp_config *to, + const struct ia_css_output0_configuration *from, + unsigned int size); + +int ia_css_output1_config(struct sh_css_isp_output_isp_config *to, + const struct ia_css_output1_configuration *from, + unsigned int size); + +int ia_css_output_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +int ia_css_output0_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +int ia_css_output1_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +void +ia_css_output_dump( + const struct sh_css_isp_output_params *output, + unsigned int level); + +void +ia_css_output_debug_dtrace( + const struct ia_css_output_config *config, + unsigned int level); + +#endif /* __IA_CSS_OUTPUT_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output_param.h new file mode 100644 index 000000000..df125674b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output_param.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OUTPUT_PARAM_H +#define __IA_CSS_OUTPUT_PARAM_H + +#include +#include "dma.h" +#include "ia_css_frame_comm.h" /* ia_css_frame_sp_info */ + +/* output frame */ +struct sh_css_isp_output_isp_config { + u32 width_a_over_b; + u32 height; + u32 enable; + struct ia_css_frame_sp_info info; + struct dma_port_config port_b; +}; + +struct sh_css_isp_output_params { + u8 enable_hflip; + u8 enable_vflip; +}; + +#endif /* __IA_CSS_OUTPUT_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output_types.h new file mode 100644 index 000000000..e5f9c05d2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/output/output_1.0/ia_css_output_types.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OUTPUT_TYPES_H +#define __IA_CSS_OUTPUT_TYPES_H + +/* @file +* CSS-API header file for parameters of output frames. +*/ + +/* Output frame + * + * ISP block: output frame + */ + +//#include "ia_css_frame_public.h" +struct ia_css_frame_info; + +struct ia_css_output_configuration { + const struct ia_css_frame_info *info; +}; + +struct ia_css_output0_configuration { + const struct ia_css_frame_info *info; +}; + +struct ia_css_output1_configuration { + const struct ia_css_frame_info *info; +}; + +struct ia_css_output_config { + u8 enable_hflip; /** enable horizontal output mirroring */ + u8 enable_vflip; /** enable vertical output mirroring */ +}; + +#endif /* __IA_CSS_OUTPUT_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane.host.c new file mode 100644 index 000000000..9fd4435e9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane.host.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_frame.h" +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" + +#include "ia_css_qplane.host.h" + +static const struct ia_css_qplane_configuration default_config = { + .pipe = (struct sh_css_sp_pipeline *)NULL, +}; + +int ia_css_qplane_config(struct sh_css_isp_qplane_isp_config *to, + const struct ia_css_qplane_configuration *from, + unsigned int size) +{ + unsigned int elems_a = ISP_VEC_NELEMS; + int ret; + + ret = ia_css_dma_configure_from_info(&to->port_b, from->info); + if (ret) + return ret; + + to->width_a_over_b = elems_a / to->port_b.elems; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + if (elems_a % to->port_b.elems != 0) + return -EINVAL; + + to->inout_port_config = from->pipe->inout_port_config; + to->format = from->info->format; + + return 0; +} + +int ia_css_qplane_configure(const struct sh_css_sp_pipeline *pipe, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + struct ia_css_qplane_configuration config = default_config; + + config.pipe = pipe; + config.info = info; + + return ia_css_configure_qplane(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane.host.h new file mode 100644 index 000000000..b3f8fa30c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane.host.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_QPLANE_HOST_H +#define __IA_CSS_QPLANE_HOST_H + +#include +#include + +#if 0 +/* Cannot be included, since sh_css_internal.h is too generic + * e.g. for FW generation. +*/ +#include "sh_css_internal.h" /* sh_css_sp_pipeline */ +#endif + +#include "ia_css_qplane_types.h" +#include "ia_css_qplane_param.h" + +int ia_css_qplane_config(struct sh_css_isp_qplane_isp_config *to, + const struct ia_css_qplane_configuration *from, + unsigned int size); + +int ia_css_qplane_configure(const struct sh_css_sp_pipeline *pipe, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +#endif /* __IA_CSS_QPLANE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane_param.h new file mode 100644 index 000000000..9ae290450 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane_param.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_QPLANE_PARAM_H +#define __IA_CSS_QPLANE_PARAM_H + +#include +#include "dma.h" + +/* qplane channel */ +struct sh_css_isp_qplane_isp_config { + u32 width_a_over_b; + struct dma_port_config port_b; + u32 inout_port_config; + u32 input_needs_raw_binning; + u32 format; /* enum ia_css_frame_format */ +}; + +#endif /* __IA_CSS_QPLANE_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane_types.h new file mode 100644 index 000000000..549f1a36b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/qplane/qplane_2/ia_css_qplane_types.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_QPLANE_TYPES_H +#define __IA_CSS_QPLANE_TYPES_H + +#include +#include "sh_css_internal.h" + +/* qplane frame + * + * ISP block: qplane frame + */ + +struct ia_css_qplane_configuration { + const struct sh_css_sp_pipeline *pipe; + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_QPLANE_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw.host.c new file mode 100644 index 000000000..646d6e39c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw.host.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_frame.h" +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" +#include "isp/modes/interface/isp_types.h" + +#include "ia_css_raw.host.h" + +static const struct ia_css_raw_configuration default_config = { + .pipe = (struct sh_css_sp_pipeline *)NULL, +}; + +/* MW: These areMIPI / ISYS properties, not camera function properties */ +static enum sh_stream_format +css2isp_stream_format(enum atomisp_input_format from) { + switch (from) + { + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: + return sh_stream_format_yuv420_legacy; + case ATOMISP_INPUT_FORMAT_YUV420_8: + case ATOMISP_INPUT_FORMAT_YUV420_10: + case ATOMISP_INPUT_FORMAT_YUV420_16: + return sh_stream_format_yuv420; + case ATOMISP_INPUT_FORMAT_YUV422_8: + case ATOMISP_INPUT_FORMAT_YUV422_10: + case ATOMISP_INPUT_FORMAT_YUV422_16: + return sh_stream_format_yuv422; + case ATOMISP_INPUT_FORMAT_RGB_444: + case ATOMISP_INPUT_FORMAT_RGB_555: + case ATOMISP_INPUT_FORMAT_RGB_565: + case ATOMISP_INPUT_FORMAT_RGB_666: + case ATOMISP_INPUT_FORMAT_RGB_888: + return sh_stream_format_rgb; + case ATOMISP_INPUT_FORMAT_RAW_6: + case ATOMISP_INPUT_FORMAT_RAW_7: + case ATOMISP_INPUT_FORMAT_RAW_8: + case ATOMISP_INPUT_FORMAT_RAW_10: + case ATOMISP_INPUT_FORMAT_RAW_12: + case ATOMISP_INPUT_FORMAT_RAW_14: + case ATOMISP_INPUT_FORMAT_RAW_16: + return sh_stream_format_raw; + case ATOMISP_INPUT_FORMAT_BINARY_8: + default: + return sh_stream_format_raw; + } +} + +int ia_css_raw_config(struct sh_css_isp_raw_isp_config *to, + const struct ia_css_raw_configuration *from, + unsigned int size) +{ + unsigned int elems_a = ISP_VEC_NELEMS; + const struct ia_css_frame_info *in_info = from->in_info; + const struct ia_css_frame_info *internal_info = from->internal_info; + int ret; + +#if !defined(ISP2401) + /* 2401 input system uses input width width */ + in_info = internal_info; +#else + /*in some cases, in_info is NULL*/ + if (in_info) + (void)internal_info; + else + in_info = internal_info; + +#endif + ret = ia_css_dma_configure_from_info(&to->port_b, in_info); + if (ret) + return ret; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert((in_info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED) || + (elems_a % to->port_b.elems == 0)); + + to->width_a_over_b = elems_a / to->port_b.elems; + to->inout_port_config = from->pipe->inout_port_config; + to->format = in_info->format; + to->required_bds_factor = from->pipe->required_bds_factor; + to->two_ppc = from->two_ppc; + to->stream_format = css2isp_stream_format(from->stream_format); + to->deinterleaved = from->deinterleaved; +#if defined(ISP2401) + to->start_column = in_info->crop_info.start_column; + to->start_line = in_info->crop_info.start_line; + to->enable_left_padding = from->enable_left_padding; +#endif + + return 0; +} + +int ia_css_raw_configure(const struct sh_css_sp_pipeline *pipe, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *in_info, + const struct ia_css_frame_info *internal_info, + bool two_ppc, + bool deinterleaved) +{ + u8 enable_left_padding = (uint8_t)((binary->left_padding) ? 1 : 0); + struct ia_css_raw_configuration config = default_config; + + config.pipe = pipe; + config.in_info = in_info; + config.internal_info = internal_info; + config.two_ppc = two_ppc; + config.stream_format = binary->input_format; + config.deinterleaved = deinterleaved; + config.enable_left_padding = enable_left_padding; + + return ia_css_configure_raw(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw.host.h new file mode 100644 index 000000000..23da51aab --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw.host.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_RAW_HOST_H +#define __IA_CSS_RAW_HOST_H + +#include "ia_css_binary.h" + +#include "ia_css_raw_types.h" +#include "ia_css_raw_param.h" + +int ia_css_raw_config(struct sh_css_isp_raw_isp_config *to, + const struct ia_css_raw_configuration *from, + unsigned int size); + +int ia_css_raw_configure(const struct sh_css_sp_pipeline *pipe, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *in_info, + const struct ia_css_frame_info *internal_info, + bool two_ppc, + bool deinterleaved); + +#endif /* __IA_CSS_RAW_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw_param.h new file mode 100644 index 000000000..c4b5f719a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw_param.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_RAW_PARAM_H +#define __IA_CSS_RAW_PARAM_H + +#include "type_support.h" + +#include "dma.h" + +/* Raw channel */ +struct sh_css_isp_raw_isp_config { + u32 width_a_over_b; + struct dma_port_config port_b; + u32 inout_port_config; + u32 input_needs_raw_binning; + u32 format; /* enum ia_css_frame_format */ + u32 required_bds_factor; + u32 two_ppc; + u32 stream_format; /* enum sh_stream_format */ + u32 deinterleaved; + u32 start_column; /*left crop offset*/ + u32 start_line; /*top crop offset*/ + u8 enable_left_padding; /*need this for multiple binary case*/ +}; + +#endif /* __IA_CSS_RAW_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw_types.h new file mode 100644 index 000000000..1ccaa3c48 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw_types.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_RAW_TYPES_H +#define __IA_CSS_RAW_TYPES_H + +#include +#include "sh_css_internal.h" + +/* Raw frame + * + * ISP block: Raw frame + */ + +struct ia_css_raw_configuration { + const struct sh_css_sp_pipeline *pipe; + const struct ia_css_frame_info *in_info; + const struct ia_css_frame_info *internal_info; + bool two_ppc; + enum atomisp_input_format stream_format; + bool deinterleaved; + u8 enable_left_padding; +}; + +#endif /* __IA_CSS_RAW_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.c new file mode 100644 index 000000000..9b756dadd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + + +#include "ia_css_types.h" +#include "sh_css_internal.h" +#include "sh_css_frac.h" + +#include "ia_css_raa.host.h" + +void +ia_css_raa_encode( + struct sh_css_isp_aa_params *to, + const struct ia_css_aa_config *from, + unsigned int size) +{ + (void)size; + (void)to; + (void)from; +} + diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h new file mode 100644 index 000000000..4c2b3de72 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_RAA_HOST_H +#define __IA_CSS_RAA_HOST_H + +#include "aa/aa_2/ia_css_aa2_types.h" +#include "aa/aa_2/ia_css_aa2_param.h" + +void +ia_css_raa_encode( + struct sh_css_isp_aa_params *to, + const struct ia_css_aa_config *from, + unsigned int size); + +#endif /* __IA_CSS_RAA_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref.host.c new file mode 100644 index 000000000..9288a7a37 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref.host.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" +#include "ia_css_ref.host.h" + +int ia_css_ref_config(struct sh_css_isp_ref_isp_config *to, + const struct ia_css_ref_configuration *from, + unsigned int size) +{ + unsigned int elems_a = ISP_VEC_NELEMS, i; + int ret; + + if (from->ref_frames[0]) { + ret = ia_css_dma_configure_from_info(&to->port_b, &from->ref_frames[0]->frame_info); + if (ret) + return ret; + to->width_a_over_b = elems_a / to->port_b.elems; + to->dvs_frame_delay = from->dvs_frame_delay; + } else { + to->width_a_over_b = 1; + to->dvs_frame_delay = 0; + to->port_b.elems = elems_a; + } + for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) { + if (from->ref_frames[i]) { + to->ref_frame_addr_y[i] = from->ref_frames[i]->data + + from->ref_frames[i]->planes.yuv.y.offset; + to->ref_frame_addr_c[i] = from->ref_frames[i]->data + + from->ref_frames[i]->planes.yuv.u.offset; + } else { + to->ref_frame_addr_y[i] = 0; + to->ref_frame_addr_c[i] = 0; + } + } + + /* Assume divisiblity here, may need to generalize to fixed point. */ + if (elems_a % to->port_b.elems != 0) + return -EINVAL; + + return 0; +} + +int ia_css_ref_configure(const struct ia_css_binary *binary, + const struct ia_css_frame * const *ref_frames, + const uint32_t dvs_frame_delay) +{ + struct ia_css_ref_configuration config; + unsigned int i; + + for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) + config.ref_frames[i] = ref_frames[i]; + + config.dvs_frame_delay = dvs_frame_delay; + + return ia_css_configure_ref(binary, &config); +} + +void +ia_css_init_ref_state( + struct sh_css_isp_ref_dmem_state *state, + unsigned int size) +{ + (void)size; + assert(MAX_NUM_VIDEO_DELAY_FRAMES >= 2); + state->ref_in_buf_idx = 0; + state->ref_out_buf_idx = 1; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref.host.h new file mode 100644 index 000000000..388cd4c36 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref.host.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_REF_HOST_H +#define __IA_CSS_REF_HOST_H + +#include +#include + +#include "ia_css_ref_types.h" +#include "ia_css_ref_param.h" +#include "ia_css_ref_state.h" + +int ia_css_ref_config(struct sh_css_isp_ref_isp_config *to, + const struct ia_css_ref_configuration *from, + unsigned int size); + +int ia_css_ref_configure(const struct ia_css_binary *binary, + const struct ia_css_frame * const *ref_frames, + const uint32_t dvs_frame_delay); + +void +ia_css_init_ref_state( + struct sh_css_isp_ref_dmem_state *state, + unsigned int size); +#endif /* __IA_CSS_REF_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_param.h new file mode 100644 index 000000000..c727e27a8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_param.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_REF_PARAM_H +#define __IA_CSS_REF_PARAM_H + +#include +#include "sh_css_defs.h" +#include "dma.h" + +/* Reference frame */ +struct ia_css_ref_configuration { + const struct ia_css_frame *ref_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; + u32 dvs_frame_delay; +}; + +struct sh_css_isp_ref_isp_config { + u32 width_a_over_b; + struct dma_port_config port_b; + ia_css_ptr ref_frame_addr_y[MAX_NUM_VIDEO_DELAY_FRAMES]; + ia_css_ptr ref_frame_addr_c[MAX_NUM_VIDEO_DELAY_FRAMES]; + u32 dvs_frame_delay; +}; + +#endif /* __IA_CSS_REF_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_state.h b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_state.h new file mode 100644 index 000000000..d4f7a6676 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_state.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_REF_STATE_H +#define __IA_CSS_REF_STATE_H + +#include "type_support.h" + +/* REF (temporal noise reduction) */ +struct sh_css_isp_ref_dmem_state { + s32 ref_in_buf_idx; + s32 ref_out_buf_idx; +}; + +#endif /* __IA_CSS_REF_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_types.h new file mode 100644 index 000000000..07d040bcf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ref/ref_1.0/ia_css_ref_types.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_REF_TYPES_H +#define __IA_CSS_REF_TYPES_H + +/* Reference frame + * + * ISP block: reference frame + */ + +#include + +#endif /* __IA_CSS_REF_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c new file mode 100644 index 000000000..bd7b89d94 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "sh_css_frac.h" +#include "assert_support.h" + +#include "bh/bh_2/ia_css_bh.host.h" +#include "ia_css_s3a.host.h" + +const struct ia_css_3a_config default_3a_config = { + 25559, + 32768, + 7209, + 65535, + 0, + 65535, + {-3344, -6104, -19143, 19143, 6104, 3344, 0}, + {1027, 0, -9219, 16384, -9219, 1027, 0} +}; + +static unsigned int s3a_raw_bit_depth; + +void +ia_css_s3a_configure(unsigned int raw_bit_depth) +{ + s3a_raw_bit_depth = raw_bit_depth; +} + +static void +ia_css_ae_encode( + struct sh_css_isp_ae_params *to, + const struct ia_css_3a_config *from, + unsigned int size) +{ + (void)size; + /* coefficients to calculate Y */ + to->y_coef_r = + uDIGIT_FITTING(from->ae_y_coef_r, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_g = + uDIGIT_FITTING(from->ae_y_coef_g, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_b = + uDIGIT_FITTING(from->ae_y_coef_b, 16, SH_CSS_AE_YCOEF_SHIFT); +} + +static void +ia_css_awb_encode( + struct sh_css_isp_awb_params *to, + const struct ia_css_3a_config *from, + unsigned int size) +{ + (void)size; + /* AWB level gate */ + to->lg_high_raw = + uDIGIT_FITTING(from->awb_lg_high_raw, 16, s3a_raw_bit_depth); + to->lg_low = + uDIGIT_FITTING(from->awb_lg_low, 16, SH_CSS_BAYER_BITS); + to->lg_high = + uDIGIT_FITTING(from->awb_lg_high, 16, SH_CSS_BAYER_BITS); +} + +static void +ia_css_af_encode( + struct sh_css_isp_af_params *to, + const struct ia_css_3a_config *from, + unsigned int size) +{ + unsigned int i; + (void)size; + + /* af fir coefficients */ + for (i = 0; i < 7; ++i) { + to->fir1[i] = + sDIGIT_FITTING(from->af_fir1_coef[i], 15, + SH_CSS_AF_FIR_SHIFT); + to->fir2[i] = + sDIGIT_FITTING(from->af_fir2_coef[i], 15, + SH_CSS_AF_FIR_SHIFT); + } +} + +void +ia_css_s3a_encode( + struct sh_css_isp_s3a_params *to, + const struct ia_css_3a_config *from, + unsigned int size) +{ + (void)size; + + ia_css_ae_encode(&to->ae, from, sizeof(to->ae)); + ia_css_awb_encode(&to->awb, from, sizeof(to->awb)); + ia_css_af_encode(&to->af, from, sizeof(to->af)); +} + +#if 0 +void +ia_css_process_s3a( + unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + short dmem_offset = stage->binary->info->mem_offsets->dmem.s3a; + + assert(params); + + if (dmem_offset >= 0) { + ia_css_s3a_encode((struct sh_css_isp_s3a_params *) + &stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset], + ¶ms->s3a_config); + ia_css_bh_encode((struct sh_css_isp_bh_params *) + &stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset], + ¶ms->s3a_config); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM0] = + true; + } + + params->isp_params_changed = true; +} +#endif + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ae_dump( + const struct sh_css_isp_ae_params *ae, + unsigned int level) +{ + if (!ae) return; + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_r", ae->y_coef_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_g", ae->y_coef_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_b", ae->y_coef_b); +} + +void +ia_css_awb_dump( + const struct sh_css_isp_awb_params *awb, + unsigned int level) +{ + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_high_raw", awb->lg_high_raw); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_low", awb->lg_low); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_high", awb->lg_high); +} + +void +ia_css_af_dump( + const struct sh_css_isp_af_params *af, + unsigned int level) +{ + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[0]", af->fir1[0]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[1]", af->fir1[1]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[2]", af->fir1[2]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[3]", af->fir1[3]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[4]", af->fir1[4]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[5]", af->fir1[5]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[6]", af->fir1[6]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[0]", af->fir2[0]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[1]", af->fir2[1]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[2]", af->fir2[2]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[3]", af->fir2[3]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[4]", af->fir2[4]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[5]", af->fir2[5]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[6]", af->fir2[6]); +} + +void +ia_css_s3a_dump( + const struct sh_css_isp_s3a_params *s3a, + unsigned int level) +{ + ia_css_debug_dtrace(level, "S3A Support:\n"); + ia_css_ae_dump(&s3a->ae, level); + ia_css_awb_dump(&s3a->awb, level); + ia_css_af_dump(&s3a->af, level); +} + +void +ia_css_s3a_debug_dtrace( + const struct ia_css_3a_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.ae_y_coef_r=%d, config.ae_y_coef_g=%d, config.ae_y_coef_b=%d, config.awb_lg_high_raw=%d, config.awb_lg_low=%d, config.awb_lg_high=%d\n", + config->ae_y_coef_r, config->ae_y_coef_g, + config->ae_y_coef_b, config->awb_lg_high_raw, + config->awb_lg_low, config->awb_lg_high); +} +#endif + +void +ia_css_s3a_hmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_bh_table *hmem_buf) +{ + struct ia_css_3a_rgby_output *out_ptr; + int i; + + /* pixel counts(BQ) for 3A area */ + int count_for_3a; + int sum_r, diff; + + assert(host_stats); + assert(host_stats->rgby_data); + assert(hmem_buf); + + count_for_3a = host_stats->grid.width * host_stats->grid.height + * host_stats->grid.bqs_per_grid_cell + * host_stats->grid.bqs_per_grid_cell; + + out_ptr = host_stats->rgby_data; + + ia_css_bh_hmem_decode(out_ptr, hmem_buf); + + /* Calculate sum of histogram of R, + which should not be less than count_for_3a */ + sum_r = 0; + for (i = 0; i < HMEM_UNIT_SIZE; i++) { + sum_r += out_ptr[i].r; + } + if (sum_r < count_for_3a) { + /* histogram is invalid */ + return; + } + + /* Verify for sum of histogram of R/G/B/Y */ +#if 0 + { + int sum_g = 0; + int sum_b = 0; + int sum_y = 0; + + for (i = 0; i < HMEM_UNIT_SIZE; i++) { + sum_g += out_ptr[i].g; + sum_b += out_ptr[i].b; + sum_y += out_ptr[i].y; + } + if (sum_g != sum_r || sum_b != sum_r || sum_y != sum_r) { + /* histogram is invalid */ + return; + } + } +#endif + + /* + * Limit the histogram area only to 3A area. + * In DSP, the histogram of 0 is incremented for pixels + * which are outside of 3A area. That amount should be subtracted here. + * hist[0] = hist[0] - ((sum of all hist[]) - (pixel count for 3A area)) + */ + diff = sum_r - count_for_3a; + out_ptr[0].r -= diff; + out_ptr[0].g -= diff; + out_ptr[0].b -= diff; + out_ptr[0].y -= diff; +} + +void +ia_css_s3a_dmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_3a_output *isp_stats) +{ + int isp_width, host_width, height, i; + struct ia_css_3a_output *host_ptr; + + assert(host_stats); + assert(host_stats->data); + assert(isp_stats); + + isp_width = host_stats->grid.aligned_width; + host_width = host_stats->grid.width; + height = host_stats->grid.height; + host_ptr = host_stats->data; + + /* Getting 3A statistics from DMEM does not involve any + * transformation (like the VMEM version), we just copy the data + * using a different output width. */ + for (i = 0; i < height; i++) { + memcpy(host_ptr, isp_stats, host_width * sizeof(*host_ptr)); + isp_stats += isp_width; + host_ptr += host_width; + } +} + +/* MW: this is an ISP function */ +static inline int +merge_hi_lo_14(unsigned short hi, unsigned short lo) +{ + int val = (int)((((unsigned int)hi << 14) & 0xfffc000) | + ((unsigned int)lo & 0x3fff)); + return val; +} + +void +ia_css_s3a_vmem_decode( + struct ia_css_3a_statistics *host_stats, + const u16 *isp_stats_hi, + const uint16_t *isp_stats_lo) +{ + int out_width, out_height, chunk, rest, kmax, y, x, k, elm_start, elm, ofs; + const u16 *hi, *lo; + struct ia_css_3a_output *output; + + assert(host_stats); + assert(host_stats->data); + assert(isp_stats_hi); + assert(isp_stats_lo); + + output = host_stats->data; + out_width = host_stats->grid.width; + out_height = host_stats->grid.height; + hi = isp_stats_hi; + lo = isp_stats_lo; + + chunk = ISP_VEC_NELEMS >> host_stats->grid.deci_factor_log2; + chunk = max(chunk, 1); + + for (y = 0; y < out_height; y++) { + elm_start = y * ISP_S3ATBL_HI_LO_STRIDE; + rest = out_width; + x = 0; + while (x < out_width) { + kmax = (rest > chunk) ? chunk : rest; + ofs = y * out_width + x; + elm = elm_start + x * sizeof(*output) / sizeof(int32_t); + for (k = 0; k < kmax; k++, elm++) { + output[ofs + k].ae_y = merge_hi_lo_14( + hi[elm + chunk * 0], lo[elm + chunk * 0]); + output[ofs + k].awb_cnt = merge_hi_lo_14( + hi[elm + chunk * 1], lo[elm + chunk * 1]); + output[ofs + k].awb_gr = merge_hi_lo_14( + hi[elm + chunk * 2], lo[elm + chunk * 2]); + output[ofs + k].awb_r = merge_hi_lo_14( + hi[elm + chunk * 3], lo[elm + chunk * 3]); + output[ofs + k].awb_b = merge_hi_lo_14( + hi[elm + chunk * 4], lo[elm + chunk * 4]); + output[ofs + k].awb_gb = merge_hi_lo_14( + hi[elm + chunk * 5], lo[elm + chunk * 5]); + output[ofs + k].af_hpf1 = merge_hi_lo_14( + hi[elm + chunk * 6], lo[elm + chunk * 6]); + output[ofs + k].af_hpf2 = merge_hi_lo_14( + hi[elm + chunk * 7], lo[elm + chunk * 7]); + } + x += chunk; + rest -= chunk; + } + } +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h new file mode 100644 index 000000000..f9926e297 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_HOST_H +#define __IA_CSS_S3A_HOST_H + +#include "ia_css_s3a_types.h" +#include "ia_css_s3a_param.h" +#include "bh/bh_2/ia_css_bh.host.h" + +extern const struct ia_css_3a_config default_3a_config; + +void +ia_css_s3a_configure( + unsigned int raw_bit_depth); + +void +ia_css_s3a_encode( + struct sh_css_isp_s3a_params *to, + const struct ia_css_3a_config *from, + unsigned int size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ae_dump( + const struct sh_css_isp_ae_params *ae, + unsigned int level); + +void +ia_css_awb_dump( + const struct sh_css_isp_awb_params *awb, + unsigned int level); + +void +ia_css_af_dump( + const struct sh_css_isp_af_params *af, + unsigned int level); + +void +ia_css_s3a_dump( + const struct sh_css_isp_s3a_params *s3a, + unsigned int level); + +void +ia_css_s3a_debug_dtrace( + const struct ia_css_3a_config *config, + unsigned int level); +#endif + +void +ia_css_s3a_hmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_bh_table *hmem_buf); + +void +ia_css_s3a_dmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_3a_output *isp_stats); + +void +ia_css_s3a_vmem_decode( + struct ia_css_3a_statistics *host_stats, + const u16 *isp_stats_hi, + const uint16_t *isp_stats_lo); + +#endif /* __IA_CSS_S3A_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h new file mode 100644 index 000000000..9cb75b220 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_PARAM_H +#define __IA_CSS_S3A_PARAM_H + +#include "type_support.h" + +/* AE (3A Support) */ +struct sh_css_isp_ae_params { + /* coefficients to calculate Y */ + s32 y_coef_r; + s32 y_coef_g; + s32 y_coef_b; +}; + +/* AWB (3A Support) */ +struct sh_css_isp_awb_params { + s32 lg_high_raw; + s32 lg_low; + s32 lg_high; +}; + +/* AF (3A Support) */ +struct sh_css_isp_af_params { + s32 fir1[7]; + s32 fir2[7]; +}; + +/* S3A (3A Support) */ +struct sh_css_isp_s3a_params { + /* coefficients to calculate Y */ + struct sh_css_isp_ae_params ae; + + /* AWB level gate */ + struct sh_css_isp_awb_params awb; + + /* af fir coefficients */ + struct sh_css_isp_af_params af; +}; + +#endif /* __IA_CSS_S3A_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h new file mode 100644 index 000000000..f369e9b95 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_TYPES_H +#define __IA_CSS_S3A_TYPES_H + +/* @file +* CSS-API header file for 3A statistics parameters. +*/ + +#include + +#if (defined(SYSTEM_css_skycam_c0_system)) && (!defined(PIPE_GENERATION)) +#include "../../../../components/stats_3a/src/stats_3a_public.h" +#endif + +/* 3A configuration. This configures the 3A statistics collection + * module. + */ + +/* 3A statistics grid + * + * ISP block: S3A1 (3A Support for 3A ver.1 (Histogram is not used for AE)) + * S3A2 (3A Support for 3A ver.2 (Histogram is used for AE)) + * ISP1: S3A1 is used. + * ISP2: S3A2 is used. + */ +struct ia_css_3a_grid_info { +#if defined(SYSTEM_css_skycam_c0_system) + u32 ae_enable; /** ae enabled in binary, + 0:disabled, 1:enabled */ + struct ae_public_config_grid_config + ae_grd_info; /** see description in ae_public.h*/ + + u32 awb_enable; /** awb enabled in binary, + 0:disabled, 1:enabled */ + struct awb_public_config_grid_config + awb_grd_info; /** see description in awb_public.h*/ + + u32 af_enable; /** af enabled in binary, + 0:disabled, 1:enabled */ + struct af_public_grid_config af_grd_info; /** see description in af_public.h*/ + + u32 awb_fr_enable; /** awb_fr enabled in binary, + 0:disabled, 1:enabled */ + struct awb_fr_public_grid_config + awb_fr_grd_info;/** see description in awb_fr_public.h*/ + + u32 elem_bit_depth; /** TODO:Taken from BYT - need input from AIQ + if needed for SKC + Bit depth of element used + to calculate 3A statistics. + This is 13, which is the normalized + bayer bit depth in DSP. */ + +#else + u32 enable; /** 3A statistics enabled. + 0:disabled, 1:enabled */ + u32 use_dmem; /** DMEM or VMEM determines layout. + 0:3A statistics are stored to VMEM, + 1:3A statistics are stored to DMEM */ + u32 has_histogram; /** Statistics include histogram. + 0:no histogram, 1:has histogram */ + u32 width; /** Width of 3A grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) */ + u32 height; /** Height of 3A grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) */ + u32 aligned_width; /** Horizontal stride (for alloc). + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + u32 aligned_height; /** Vertical stride (for alloc). + (= Vertical number of grid cells + in table, which means + the allocated height.) */ + u32 bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit. + (1BQ means {Gr,R,B,Gb}(2x2 pixels).) + Valid values are 8,16,32,64. */ + u32 deci_factor_log2; /** log2 of bqs_per_grid_cell. */ + u32 elem_bit_depth; /** Bit depth of element used + to calculate 3A statistics. + This is 13, which is the normalized + bayer bit depth in DSP. */ +#endif +}; + +/* This struct should be split into 3, for AE, AWB and AF. + * However, that will require driver/ 3A lib modifications. + */ + +/* 3A configuration. This configures the 3A statistics collection + * module. + * + * ae_y_*: Coefficients to calculate luminance from bayer. + * awb_lg_*: Thresholds to check the saturated bayer pixels for AWB. + * Condition of effective pixel for AWB level gate check: + * bayer(sensor) <= awb_lg_high_raw && + * bayer(when AWB statisitcs is calculated) >= awb_lg_low && + * bayer(when AWB statisitcs is calculated) <= awb_lg_high + * af_fir*: Coefficients of high pass filter to calculate AF statistics. + * + * ISP block: S3A1(ae_y_* for AE/AF, awb_lg_* for AWB) + * S3A2(ae_y_* for AF, awb_lg_* for AWB) + * SDVS1(ae_y_*) + * SDVS2(ae_y_*) + * ISP1: S3A1 and SDVS1 are used. + * ISP2: S3A2 and SDVS2 are used. + */ +struct ia_css_3a_config { + ia_css_u0_16 ae_y_coef_r; /** Weight of R for Y. + u0.16, [0,65535], + default/ineffective 25559 */ + ia_css_u0_16 ae_y_coef_g; /** Weight of G for Y. + u0.16, [0,65535], + default/ineffective 32768 */ + ia_css_u0_16 ae_y_coef_b; /** Weight of B for Y. + u0.16, [0,65535], + default/ineffective 7209 */ + ia_css_u0_16 awb_lg_high_raw; /** AWB level gate high for raw. + u0.16, [0,65535], + default 65472(=1023*64), + ineffective 65535 */ + ia_css_u0_16 awb_lg_low; /** AWB level gate low. + u0.16, [0,65535], + default 64(=1*64), + ineffective 0 */ + ia_css_u0_16 awb_lg_high; /** AWB level gate high. + u0.16, [0,65535], + default 65535, + ineffective 65535 */ + ia_css_s0_15 af_fir1_coef[7]; /** AF FIR coefficients of fir1. + s0.15, [-32768,32767], + default/ineffective + -6689,-12207,-32768,32767,12207,6689,0 */ + ia_css_s0_15 af_fir2_coef[7]; /** AF FIR coefficients of fir2. + s0.15, [-32768,32767], + default/ineffective + 2053,0,-18437,32767,-18437,2053,0 */ +}; + +/* 3A statistics. This structure describes the data stored + * in each 3A grid point. + * + * ISP block: S3A1 (3A Support for 3A ver.1) (Histogram is not used for AE) + * S3A2 (3A Support for 3A ver.2) (Histogram is used for AE) + * - ae_y is used only for S3A1. + * - awb_* and af_* are used both for S3A1 and S3A2. + * ISP1: S3A1 is used. + * ISP2: S3A2 is used. + */ +struct ia_css_3a_output { + s32 ae_y; /** Sum of Y in a statistics window, for AE. + (u19.13) */ + s32 awb_cnt; /** Number of effective pixels + in a statistics window. + Pixels passed by the AWB level gate check are + judged as "effective". (u32) */ + s32 awb_gr; /** Sum of Gr in a statistics window, for AWB. + All Gr pixels (not only for effective pixels) + are summed. (u19.13) */ + s32 awb_r; /** Sum of R in a statistics window, for AWB. + All R pixels (not only for effective pixels) + are summed. (u19.13) */ + s32 awb_b; /** Sum of B in a statistics window, for AWB. + All B pixels (not only for effective pixels) + are summed. (u19.13) */ + s32 awb_gb; /** Sum of Gb in a statistics window, for AWB. + All Gb pixels (not only for effective pixels) + are summed. (u19.13) */ + s32 af_hpf1; /** Sum of |Y| following high pass filter af_fir1 + within a statistics window, for AF. (u19.13) */ + s32 af_hpf2; /** Sum of |Y| following high pass filter af_fir2 + within a statistics window, for AF. (u19.13) */ +}; + +/* 3A Statistics. This structure describes the statistics that are generated + * using the provided configuration (ia_css_3a_config). + */ +struct ia_css_3a_statistics { + struct ia_css_3a_grid_info + grid; /** grid info contains the dimensions of the 3A grid */ + struct ia_css_3a_output + *data; /** the pointer to 3a_output[grid.width * grid.height] + containing the 3A statistics */ + struct ia_css_3a_rgby_output *rgby_data;/** the pointer to 3a_rgby_output[256] + containing the histogram */ +}; + +/* Histogram (Statistics for AE). + * + * 4 histograms(r,g,b,y), + * 256 bins for each histogram, unsigned 24bit value for each bin. + * struct ia_css_3a_rgby_output data[256]; + + * ISP block: HIST2 + * (ISP1: HIST2 is not used.) + * ISP2: HIST2 is used. + */ +struct ia_css_3a_rgby_output { + u32 r; /** Number of R of one bin of the histogram R. (u24) */ + u32 g; /** Number of G of one bin of the histogram G. (u24) */ + u32 b; /** Number of B of one bin of the histogram B. (u24) */ + u32 y; /** Number of Y of one bin of the histogram Y. (u24) */ +}; + +#endif /* __IA_CSS_S3A_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc.host.c new file mode 100644 index 000000000..6974b3424 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc.host.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" + +#include "ia_css_sc.host.h" + +void +ia_css_sc_encode( + struct sh_css_isp_sc_params *to, + struct ia_css_shading_table **from, + unsigned int size) +{ + (void)size; + to->gain_shift = (*from)->fraction_bits; +} + +void +ia_css_sc_dump( + const struct sh_css_isp_sc_params *sc, + unsigned int level) +{ + if (!sc) return; + ia_css_debug_dtrace(level, "Shading Correction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "sc_gain_shift", sc->gain_shift); +} + +/* ------ deprecated(bz675) : from ------ */ +/* It looks like @parameter{} (in *.pipe) is used to generate the process/get/set functions, + for parameters which should be used in the isp kernels. + However, the ia_css_shading_settings structure has a parameter which is used only in the css, + and does not have a parameter which is used in the isp kernels. + Then, I did not use @parameter{} to generate the get/set function + for the ia_css_shading_settings structure. (michie) */ +void +sh_css_get_shading_settings(const struct ia_css_isp_parameters *params, + struct ia_css_shading_settings *settings) +{ + if (!settings) + return; + assert(params); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_get_shading_settings() enter: settings=%p\n", settings); + + *settings = params->shading_settings; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_get_shading_settings() leave: settings.enable_shading_table_conversion=%d\n", + settings->enable_shading_table_conversion); +} + +void +sh_css_set_shading_settings(struct ia_css_isp_parameters *params, + const struct ia_css_shading_settings *settings) +{ + if (!settings) + return; + assert(params); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_shading_settings() enter: settings.enable_shading_table_conversion=%d\n", + settings->enable_shading_table_conversion); + + params->shading_settings = *settings; + params->shading_settings_changed = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_shading_settings() leave: return_void\n"); +} + +/* ------ deprecated(bz675) : to ------ */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc.host.h new file mode 100644 index 000000000..d103103c9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc.host.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SC_HOST_H +#define __IA_CSS_SC_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_sc_types.h" +#include "ia_css_sc_param.h" + +void +ia_css_sc_encode( + struct sh_css_isp_sc_params *to, + struct ia_css_shading_table **from, + unsigned int size); + +void +ia_css_sc_dump( + const struct sh_css_isp_sc_params *sc, + unsigned int level); + +/* ------ deprecated(bz675) : from ------ */ +void +sh_css_get_shading_settings(const struct ia_css_isp_parameters *params, + struct ia_css_shading_settings *settings); + +void +sh_css_set_shading_settings(struct ia_css_isp_parameters *params, + const struct ia_css_shading_settings *settings); +/* ------ deprecated(bz675) : to ------ */ + +#endif /* __IA_CSS_SC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc_param.h new file mode 100644 index 000000000..fab11d335 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc_param.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SC_PARAM_H +#define __IA_CSS_SC_PARAM_H + +#include "type_support.h" + +/* SC (Shading Corrction) */ +struct sh_css_isp_sc_params { + s32 gain_shift; +}; + +/* Number of horizontal slice times for interpolated gain: + * + * The start position of the internal frame does not match the start position of the shading table. + * To get a vector of shading gains (interpolated horizontally and vertically) + * which matches a vector on the internal frame, + * vec_slice is used for 2 adjacent vectors of shading gains. + * The number of shift times by vec_slice is 8. + * Max grid cell bqs to support the shading table centerting: N = 32 + * CEIL_DIV(N-1, ISP_SLICE_NELEMS) = CEIL_DIV(31, 4) = 8 + */ +#define SH_CSS_SC_INTERPED_GAIN_HOR_SLICE_TIMES 8 + +struct sh_css_isp_sc_isp_config { + u32 interped_gain_hor_slice_bqs[SH_CSS_SC_INTERPED_GAIN_HOR_SLICE_TIMES]; + u32 internal_frame_origin_y_bqs_on_sctbl; +}; + +#endif /* __IA_CSS_SC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc_types.h new file mode 100644 index 000000000..1d70f6b9a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sc/sc_1.0/ia_css_sc_types.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SC_TYPES_H +#define __IA_CSS_SC_TYPES_H + +/* @file +* CSS-API header file for Lens Shading Correction (SC) parameters. +*/ + +/* Number of color planes in the shading table. */ +#define IA_CSS_SC_NUM_COLORS 4 + +/* The 4 colors that a shading table consists of. + * For each color we store a grid of values. + */ +enum ia_css_sc_color { + IA_CSS_SC_COLOR_GR, /** Green on a green-red line */ + IA_CSS_SC_COLOR_R, /** Red */ + IA_CSS_SC_COLOR_B, /** Blue */ + IA_CSS_SC_COLOR_GB /** Green on a green-blue line */ +}; + +/* Lens Shading Correction table. + * + * This describes the color shading artefacts + * introduced by lens imperfections. To correct artefacts, + * bayer values should be multiplied by gains in this table. + * + *------------ deprecated(bz675) : from --------------------------- + * When shading_settings.enable_shading_table_conversion is set as 0, + * this shading table is directly sent to the isp. This table should contain + * the data based on the ia_css_shading_info information filled in the css. + * So, the driver needs to get the ia_css_shading_info information + * from the css, prior to generating the shading table. + * + * When shading_settings.enable_shading_table_conversion is set as 1, + * this shading table is converted in the legacy way in the css + * before it is sent to the isp. + * The driver does not need to get the ia_css_shading_info information. + * + * NOTE: + * The shading table conversion will be removed from the css in the near future, + * because it does not support the bayer scaling by sensor. + * Also, we had better generate the shading table only in one place(AIC). + * At the moment, to support the old driver which assumes the conversion is done in the css, + * shading_settings.enable_shading_table_conversion is set as 1 by default. + *------------ deprecated(bz675) : to --------------------------- + * + * ISP block: SC1 + * ISP1: SC1 is used. + * ISP2: SC1 is used. + */ +struct ia_css_shading_table { + u32 enable; /** Set to false for no shading correction. + The data field can be NULL when enable == true */ + /* ------ deprecated(bz675) : from ------ */ + u32 sensor_width; /** Native sensor width in pixels. */ + u32 sensor_height; /** Native sensor height in lines. + When shading_settings.enable_shading_table_conversion is set + as 0, sensor_width and sensor_height are NOT used. + These are used only in the legacy shading table conversion + in the css, when shading_settings. + enable_shading_table_conversion is set as 1. */ + /* ------ deprecated(bz675) : to ------ */ + u32 width; /** Number of data points per line per color. + u8.0, [0,81] */ + u32 height; /** Number of lines of data points per color. + u8.0, [0,61] */ + u32 fraction_bits; /** Bits of fractional part in the data + points. + u8.0, [0,13] */ + u16 *data[IA_CSS_SC_NUM_COLORS]; + /** Table data, one array for each color. + Use ia_css_sc_color to index this array. + u[13-fraction_bits].[fraction_bits], [0,8191] */ +}; + +/* ------ deprecated(bz675) : from ------ */ +/* Shading Correction settings. + * + * NOTE: + * This structure should be removed when the shading table conversion is + * removed from the css. + */ +struct ia_css_shading_settings { + u32 enable_shading_table_conversion; /** Set to 0, + if the conversion of the shading table should be disabled + in the css. (default 1) + 0: The shading table is directly sent to the isp. + The shading table should contain the data based on the + ia_css_shading_info information filled in the css. + 1: The shading table is converted in the css, to be fitted + to the shading table definition required in the isp. + NOTE: + Previously, the shading table was always converted in the css + before it was sent to the isp, and this config was not defined. + Currently, the driver is supposed to pass the shading table + which should be directly sent to the isp. + However, some drivers may still pass the shading table which + needs the conversion without setting this config as 1. + To support such an unexpected case for the time being, + enable_shading_table_conversion is set as 1 by default + in the css. */ +}; + +/* ------ deprecated(bz675) : to ------ */ + +#endif /* __IA_CSS_SC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sdis/common/ia_css_sdis_common.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/common/ia_css_sdis_common.host.h new file mode 100644 index 000000000..7b661e49b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/common/ia_css_sdis_common.host.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_SDIS_COMMON_HOST_H +#define _IA_CSS_SDIS_COMMON_HOST_H + +#define ISP_MAX_SDIS_HOR_PROJ_NUM_ISP \ + __ISP_SDIS_HOR_PROJ_NUM_ISP(ISP_MAX_INTERNAL_WIDTH, ISP_MAX_INTERNAL_HEIGHT, \ + SH_CSS_DIS_DECI_FACTOR_LOG2, ISP_PIPE_VERSION) +#define ISP_MAX_SDIS_VER_PROJ_NUM_ISP \ + __ISP_SDIS_VER_PROJ_NUM_ISP(ISP_MAX_INTERNAL_WIDTH, \ + SH_CSS_DIS_DECI_FACTOR_LOG2) + +#define _ISP_SDIS_HOR_COEF_NUM_VECS \ + __ISP_SDIS_HOR_COEF_NUM_VECS(ISP_INTERNAL_WIDTH) +#define ISP_MAX_SDIS_HOR_COEF_NUM_VECS \ + __ISP_SDIS_HOR_COEF_NUM_VECS(ISP_MAX_INTERNAL_WIDTH) +#define ISP_MAX_SDIS_VER_COEF_NUM_VECS \ + __ISP_SDIS_VER_COEF_NUM_VECS(ISP_MAX_INTERNAL_HEIGHT) + +/* SDIS Coefficients: */ +/* The ISP uses vectors to store the coefficients, so we round + the number of coefficients up to vectors. */ +#define __ISP_SDIS_HOR_COEF_NUM_VECS(in_width) _ISP_VECS(_ISP_BQS(in_width)) +#define __ISP_SDIS_VER_COEF_NUM_VECS(in_height) _ISP_VECS(_ISP_BQS(in_height)) + +/* SDIS Projections: + * SDIS1: Horizontal projections are calculated for each line. + * Vertical projections are calculated for each column. + * SDIS2: Projections are calculated for each grid cell. + * Grid cells that do not fall completely within the image are not + * valid. The host needs to use the bigger one for the stride but + * should only return the valid ones to the 3A. */ +#define __ISP_SDIS_HOR_PROJ_NUM_ISP(in_width, in_height, deci_factor_log2, \ + isp_pipe_version) \ + ((isp_pipe_version == 1) ? \ + CEIL_SHIFT(_ISP_BQS(in_height), deci_factor_log2) : \ + CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2)) + +#define __ISP_SDIS_VER_PROJ_NUM_ISP(in_width, deci_factor_log2) \ + CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2) + +#define SH_CSS_DIS_VER_NUM_COEF_TYPES(b) \ + (((b)->info->sp.pipeline.isp_pipe_version == 2) ? \ + IA_CSS_DVS2_NUM_COEF_TYPES : \ + IA_CSS_DVS_NUM_COEF_TYPES) + +#ifndef PIPE_GENERATION +#if defined(__ISP) || defined(MK_FIRMWARE) + +/* Array cannot be 2-dimensional, since driver ddr allocation does not know stride */ +struct sh_css_isp_sdis_hori_proj_tbl { + s32 tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_HOR_PROJ_NUM_ISP]; +#if DVS2_PROJ_MARGIN > 0 + s32 margin[DVS2_PROJ_MARGIN]; +#endif +}; + +struct sh_css_isp_sdis_vert_proj_tbl { + s32 tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_VER_PROJ_NUM_ISP]; +#if DVS2_PROJ_MARGIN > 0 + s32 margin[DVS2_PROJ_MARGIN]; +#endif +}; + +struct sh_css_isp_sdis_hori_coef_tbl { + VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], + ISP_MAX_SDIS_HOR_COEF_NUM_VECS * ISP_NWAY); +}; + +struct sh_css_isp_sdis_vert_coef_tbl { + VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], + ISP_MAX_SDIS_VER_COEF_NUM_VECS * ISP_NWAY); +}; + +#endif /* defined(__ISP) || defined (MK_FIRMWARE) */ +#endif /* PIPE_GENERATION */ + +#ifndef PIPE_GENERATION +struct s_sdis_config { + unsigned int horicoef_vectors; + unsigned int vertcoef_vectors; + unsigned int horiproj_num; + unsigned int vertproj_num; +}; + +extern struct s_sdis_config sdis_config; +#endif + +#endif /* _IA_CSS_SDIS_COMMON_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sdis/common/ia_css_sdis_common_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/common/ia_css_sdis_common_types.h new file mode 100644 index 000000000..c2ec30b4a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/common/ia_css_sdis_common_types.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_COMMON_TYPES_H +#define __IA_CSS_SDIS_COMMON_TYPES_H + +/* @file +* CSS-API header file for DVS statistics parameters. +*/ + +#include + +/* DVS statistics grid dimensions in number of cells. + */ + +struct ia_css_dvs_grid_dim { + u32 width; /** Width of DVS grid table in cells */ + u32 height; /** Height of DVS grid table in cells */ +}; + +/* DVS statistics dimensions in number of cells for + * grid, coeffieicient and projection. + */ + +struct ia_css_sdis_info { + struct { + struct ia_css_dvs_grid_dim dim; /* Dimensions */ + struct ia_css_dvs_grid_dim pad; /* Padded dimensions */ + } grid, coef, proj; + u32 deci_factor_log2; +}; + +/* DVS statistics grid + * + * ISP block: SDVS1 (DIS/DVS Support for DIS/DVS ver.1 (2-axes)) + * SDVS2 (DVS Support for DVS ver.2 (6-axes)) + * ISP1: SDVS1 is used. + * ISP2: SDVS2 is used. + */ +struct ia_css_dvs_grid_res { + u32 width; /** Width of DVS grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) + For DVS1, this is equal to + the number of vertical statistics. */ + u32 aligned_width; /** Stride of each grid line. + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + u32 height; /** Height of DVS grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) + For DVS1, This is equal to + the number of horizontal statistics. */ + u32 aligned_height;/** Stride of each grid column. + (= Vertical number of grid cells + in table, which means + the allocated height.) */ +}; + +/* TODO: use ia_css_dvs_grid_res in here. + * However, that implies driver I/F changes + */ +struct ia_css_dvs_grid_info { + u32 enable; /** DVS statistics enabled. + 0:disabled, 1:enabled */ + u32 width; /** Width of DVS grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) + For DVS1, this is equal to + the number of vertical statistics. */ + u32 aligned_width; /** Stride of each grid line. + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + u32 height; /** Height of DVS grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) + For DVS1, This is equal to + the number of horizontal statistics. */ + u32 aligned_height;/** Stride of each grid column. + (= Vertical number of grid cells + in table, which means + the allocated height.) */ + u32 bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit. + (1BQ means {Gr,R,B,Gb}(2x2 pixels).) + For DVS1, valid value is 64. + For DVS2, valid value is only 64, + currently. */ + u32 num_hor_coefs; /** Number of horizontal coefficients. */ + u32 num_ver_coefs; /** Number of vertical coefficients. */ +}; + +/* Number of DVS statistics levels + */ +#define IA_CSS_DVS_STAT_NUM_OF_LEVELS 3 + +/* DVS statistics generated by accelerator global configuration + */ +struct dvs_stat_public_dvs_global_cfg { + unsigned char kappa; + /** DVS statistics global configuration - kappa */ + unsigned char match_shift; + /** DVS statistics global configuration - match_shift */ + unsigned char ybin_mode; + /** DVS statistics global configuration - y binning mode */ +}; + +/* DVS statistics generated by accelerator level grid + * configuration + */ +struct dvs_stat_public_dvs_level_grid_cfg { + unsigned char grid_width; + /** DVS statistics grid width */ + unsigned char grid_height; + /** DVS statistics grid height */ + unsigned char block_width; + /** DVS statistics block width */ + unsigned char block_height; + /** DVS statistics block height */ +}; + +/* DVS statistics generated by accelerator level grid start + * configuration + */ +struct dvs_stat_public_dvs_level_grid_start { + unsigned short x_start; + /** DVS statistics level x start */ + unsigned short y_start; + /** DVS statistics level y start */ + unsigned char enable; + /** DVS statistics level enable */ +}; + +/* DVS statistics generated by accelerator level grid end + * configuration + */ +struct dvs_stat_public_dvs_level_grid_end { + unsigned short x_end; + /** DVS statistics level x end */ + unsigned short y_end; + /** DVS statistics level y end */ +}; + +/* DVS statistics generated by accelerator Feature Extraction + * Region Of Interest (FE-ROI) configuration + */ +struct dvs_stat_public_dvs_level_fe_roi_cfg { + unsigned char x_start; + /** DVS statistics fe-roi level x start */ + unsigned char y_start; + /** DVS statistics fe-roi level y start */ + unsigned char x_end; + /** DVS statistics fe-roi level x end */ + unsigned char y_end; + /** DVS statistics fe-roi level y end */ +}; + +/* DVS statistics generated by accelerator public configuration + */ +struct dvs_stat_public_dvs_grd_cfg { + struct dvs_stat_public_dvs_level_grid_cfg grd_cfg; + /** DVS statistics level grid configuration */ + struct dvs_stat_public_dvs_level_grid_start grd_start; + /** DVS statistics level grid start configuration */ + struct dvs_stat_public_dvs_level_grid_end grd_end; + /** DVS statistics level grid end configuration */ +}; + +/* DVS statistics grid generated by accelerator + */ +struct ia_css_dvs_stat_grid_info { + struct dvs_stat_public_dvs_global_cfg dvs_gbl_cfg; + /** DVS statistics global configuration (kappa, match, binning) */ + struct dvs_stat_public_dvs_grd_cfg grd_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; + /** DVS statistics grid configuration (blocks and grids) */ + struct dvs_stat_public_dvs_level_fe_roi_cfg + fe_roi_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; + /** DVS statistics FE ROI (region of interest) configuration */ +}; + +/* DVS statistics generated by accelerator default grid info + */ +#define DEFAULT_DVS_GRID_INFO { \ + .dvs_stat_grid_info = { \ + .fe_roi_cfg = { \ + [1] = { \ + .x_start = 4 \ + } \ + } \ + } \ +} + +/* Union that holds all types of DVS statistics grid info in + * CSS format + * */ +union ia_css_dvs_grid_u { + struct ia_css_dvs_stat_grid_info dvs_stat_grid_info; + /** DVS statistics produced by accelerator grid info */ + struct ia_css_dvs_grid_info dvs_grid_info; + /** DVS (DVS1/DVS2) grid info */ +}; + +#endif /* __IA_CSS_SDIS_COMMON_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.c new file mode 100644 index 000000000..bf0a768f8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.c @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include "assert_support.h" +#include "ia_css_debug.h" +#include "ia_css_sdis_types.h" +#include "sdis/common/ia_css_sdis_common.host.h" +#include "ia_css_sdis.host.h" + +const struct ia_css_dvs_coefficients default_sdis_config = { + .grid = { 0, 0, 0, 0, 0, 0, 0, 0 }, + .hor_coefs = NULL, + .ver_coefs = NULL +}; + +static void +fill_row(short *private, const short *public, unsigned int width, + unsigned int padding) +{ + assert((int)width >= 0); + assert((int)padding >= 0); + memcpy(private, public, width * sizeof(short)); + memset(&private[width], 0, padding * sizeof(short)); +} + +void ia_css_sdis_horicoef_vmem_encode( + struct sh_css_isp_sdis_hori_coef_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned int size) +{ + unsigned int aligned_width = from->grid.aligned_width * + from->grid.bqs_per_grid_cell; + unsigned int width = from->grid.num_hor_coefs; + int padding = aligned_width - width; + unsigned int stride = size / IA_CSS_DVS_NUM_COEF_TYPES / sizeof(short); + unsigned int total_bytes = aligned_width * IA_CSS_DVS_NUM_COEF_TYPES * sizeof( + short); + short *public = from->hor_coefs; + short *private = (short *)to; + unsigned int type; + + /* Copy the table, add padding */ + assert(padding >= 0); + assert(total_bytes <= size); + assert(size % (IA_CSS_DVS_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof( + short)) == 0); + + for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++) { + fill_row(&private[type * stride], &public[type * width], width, padding); + } +} + +void ia_css_sdis_vertcoef_vmem_encode( + struct sh_css_isp_sdis_vert_coef_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned int size) +{ + unsigned int aligned_height = from->grid.aligned_height * + from->grid.bqs_per_grid_cell; + unsigned int height = from->grid.num_ver_coefs; + int padding = aligned_height - height; + unsigned int stride = size / IA_CSS_DVS_NUM_COEF_TYPES / sizeof(short); + unsigned int total_bytes = aligned_height * IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(short); + short *public = from->ver_coefs; + short *private = (short *)to; + unsigned int type; + + /* Copy the table, add padding */ + assert(padding >= 0); + assert(total_bytes <= size); + assert(size % (IA_CSS_DVS_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof( + short)) == 0); + + for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++) { + fill_row(&private[type * stride], &public[type * height], height, padding); + } +} + +void ia_css_sdis_horiproj_encode( + struct sh_css_isp_sdis_hori_proj_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned int size) +{ + (void)to; + (void)from; + (void)size; +} + +void ia_css_sdis_vertproj_encode( + struct sh_css_isp_sdis_vert_proj_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned int size) +{ + (void)to; + (void)from; + (void)size; +} + +void ia_css_get_isp_dis_coefficients( + struct ia_css_stream *stream, + short *horizontal_coefficients, + short *vertical_coefficients) +{ + struct ia_css_isp_parameters *params; + unsigned int hor_num_isp, ver_num_isp; + unsigned int hor_num_3a, ver_num_3a; + int i; + struct ia_css_binary *dvs_binary; + + IA_CSS_ENTER("void"); + + assert(horizontal_coefficients); + assert(vertical_coefficients); + + params = stream->isp_params_configs; + + /* Only video pipe supports DVS */ + dvs_binary = ia_css_stream_get_dvs_binary(stream); + if (!dvs_binary) + return; + + hor_num_isp = dvs_binary->dis.coef.pad.width; + ver_num_isp = dvs_binary->dis.coef.pad.height; + hor_num_3a = dvs_binary->dis.coef.dim.width; + ver_num_3a = dvs_binary->dis.coef.dim.height; + + for (i = 0; i < IA_CSS_DVS_NUM_COEF_TYPES; i++) { + fill_row(&horizontal_coefficients[i * hor_num_isp], + ¶ms->dvs_coefs.hor_coefs[i * hor_num_3a], hor_num_3a, + hor_num_isp - hor_num_3a); + } + for (i = 0; i < SH_CSS_DIS_VER_NUM_COEF_TYPES(dvs_binary); i++) { + fill_row(&vertical_coefficients[i * ver_num_isp], + ¶ms->dvs_coefs.ver_coefs[i * ver_num_3a], ver_num_3a, + ver_num_isp - ver_num_3a); + } + + IA_CSS_LEAVE("void"); +} + +size_t +ia_css_sdis_hor_coef_tbl_bytes( + const struct ia_css_binary *binary) +{ + if (binary->info->sp.pipeline.isp_pipe_version == 1) + return sizeof(short) * IA_CSS_DVS_NUM_COEF_TYPES * binary->dis.coef.pad.width; + else + return sizeof(short) * IA_CSS_DVS2_NUM_COEF_TYPES * binary->dis.coef.pad.width; +} + +size_t +ia_css_sdis_ver_coef_tbl_bytes( + const struct ia_css_binary *binary) +{ + return sizeof(short) * SH_CSS_DIS_VER_NUM_COEF_TYPES(binary) * + binary->dis.coef.pad.height; +} + +void +ia_css_sdis_init_info( + struct ia_css_sdis_info *dis, + unsigned int sc_3a_dis_width, + unsigned int sc_3a_dis_padded_width, + unsigned int sc_3a_dis_height, + unsigned int isp_pipe_version, + unsigned int enabled) +{ + if (!enabled) { + *dis = (struct ia_css_sdis_info) { }; + return; + } + + dis->deci_factor_log2 = SH_CSS_DIS_DECI_FACTOR_LOG2; + + dis->grid.dim.width = + _ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->grid.dim.height = + _ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->grid.pad.width = + CEIL_SHIFT(_ISP_BQS(sc_3a_dis_padded_width), SH_CSS_DIS_DECI_FACTOR_LOG2); + dis->grid.pad.height = + CEIL_SHIFT(_ISP_BQS(sc_3a_dis_height), SH_CSS_DIS_DECI_FACTOR_LOG2); + + dis->coef.dim.width = + (_ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2) << + SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->coef.dim.height = + (_ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2) << + SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->coef.pad.width = + __ISP_SDIS_HOR_COEF_NUM_VECS(sc_3a_dis_padded_width) * ISP_VEC_NELEMS; + dis->coef.pad.height = + __ISP_SDIS_VER_COEF_NUM_VECS(sc_3a_dis_height) * ISP_VEC_NELEMS; + if (isp_pipe_version == 1) { + dis->proj.dim.width = + _ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->proj.dim.height = + _ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2; + } else { + dis->proj.dim.width = + (_ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2) * + (_ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2); + dis->proj.dim.height = + (_ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2) * + (_ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2); + } + dis->proj.pad.width = + __ISP_SDIS_HOR_PROJ_NUM_ISP(sc_3a_dis_padded_width, + sc_3a_dis_height, + SH_CSS_DIS_DECI_FACTOR_LOG2, + isp_pipe_version); + dis->proj.pad.height = + __ISP_SDIS_VER_PROJ_NUM_ISP(sc_3a_dis_padded_width, + SH_CSS_DIS_DECI_FACTOR_LOG2); +} + +void ia_css_sdis_clear_coefficients( + struct ia_css_dvs_coefficients *dvs_coefs) +{ + dvs_coefs->hor_coefs = NULL; + dvs_coefs->ver_coefs = NULL; +} + +int +ia_css_get_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats) { + struct ia_css_isp_dvs_statistics_map *map; + int ret = 0; + + IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats); + + assert(host_stats); + assert(isp_stats); + + map = ia_css_isp_dvs_statistics_map_allocate(isp_stats, NULL); + if (map) + { + hmm_load(isp_stats->data_ptr, map->data_ptr, isp_stats->size); + ia_css_translate_dvs_statistics(host_stats, map); + ia_css_isp_dvs_statistics_map_free(map); + } else + { + IA_CSS_ERROR("out of memory"); + ret = -ENOMEM; + } + + IA_CSS_LEAVE_ERR(ret); + return ret; +} + +void +ia_css_translate_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats) +{ + unsigned int hor_num_isp, ver_num_isp, hor_num_dvs, ver_num_dvs, i; + s32 *hor_ptr_dvs, *ver_ptr_dvs, *hor_ptr_isp, *ver_ptr_isp; + + assert(host_stats); + assert(host_stats->hor_proj); + assert(host_stats->ver_proj); + assert(isp_stats); + assert(isp_stats->hor_proj); + assert(isp_stats->ver_proj); + + IA_CSS_ENTER("hproj=%p, vproj=%p, haddr=%p, vaddr=%p", + host_stats->hor_proj, host_stats->ver_proj, + isp_stats->hor_proj, isp_stats->ver_proj); + + hor_num_isp = host_stats->grid.aligned_height; + ver_num_isp = host_stats->grid.aligned_width; + hor_ptr_isp = isp_stats->hor_proj; + ver_ptr_isp = isp_stats->ver_proj; + hor_num_dvs = host_stats->grid.height; + ver_num_dvs = host_stats->grid.width; + hor_ptr_dvs = host_stats->hor_proj; + ver_ptr_dvs = host_stats->ver_proj; + + for (i = 0; i < IA_CSS_DVS_NUM_COEF_TYPES; i++) { + memcpy(hor_ptr_dvs, hor_ptr_isp, hor_num_dvs * sizeof(int32_t)); + hor_ptr_isp += hor_num_isp; + hor_ptr_dvs += hor_num_dvs; + + memcpy(ver_ptr_dvs, ver_ptr_isp, ver_num_dvs * sizeof(int32_t)); + ver_ptr_isp += ver_num_isp; + ver_ptr_dvs += ver_num_dvs; + } + + IA_CSS_LEAVE("void"); +} + +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs_statistics_allocate( + const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_isp_dvs_statistics *me; + int hor_size, ver_size; + + assert(grid); + + IA_CSS_ENTER("grid=%p", grid); + + if (!grid->enable) + return NULL; + + me = kvcalloc(1, sizeof(*me), GFP_KERNEL); + if (!me) + goto err; + + hor_size = CEIL_MUL(sizeof(int) * IA_CSS_DVS_NUM_COEF_TYPES * + grid->aligned_height, + HIVE_ISP_DDR_WORD_BYTES); + ver_size = CEIL_MUL(sizeof(int) * IA_CSS_DVS_NUM_COEF_TYPES * + grid->aligned_width, + HIVE_ISP_DDR_WORD_BYTES); + + me->size = hor_size + ver_size; + me->data_ptr = hmm_alloc(me->size); + if (me->data_ptr == mmgr_NULL) + goto err; + me->hor_size = hor_size; + me->hor_proj = me->data_ptr; + me->ver_size = ver_size; + me->ver_proj = me->data_ptr + hor_size; + + IA_CSS_LEAVE("return=%p", me); + + return me; +err: + ia_css_isp_dvs_statistics_free(me); + + IA_CSS_LEAVE("return=%p", NULL); + + return NULL; +} + +struct ia_css_isp_dvs_statistics_map * +ia_css_isp_dvs_statistics_map_allocate( + const struct ia_css_isp_dvs_statistics *isp_stats, + void *data_ptr) +{ + struct ia_css_isp_dvs_statistics_map *me; + /* Windows compiler does not like adding sizes to a void * + * so we use a local char * instead. */ + char *base_ptr; + + me = kvmalloc(sizeof(*me), GFP_KERNEL); + if (!me) { + IA_CSS_LOG("cannot allocate memory"); + goto err; + } + + me->data_ptr = data_ptr; + me->data_allocated = !data_ptr; + + if (!me->data_ptr) { + me->data_ptr = kvmalloc(isp_stats->size, GFP_KERNEL); + if (!me->data_ptr) { + IA_CSS_LOG("cannot allocate memory"); + goto err; + } + } + base_ptr = me->data_ptr; + + me->size = isp_stats->size; + /* GCC complains when we assign a char * to a void *, so these + * casts are necessary unfortunately. */ + me->hor_proj = (void *)base_ptr; + me->ver_proj = (void *)(base_ptr + isp_stats->hor_size); + + return me; +err: + kvfree(me); + return NULL; +} + +void +ia_css_isp_dvs_statistics_map_free(struct ia_css_isp_dvs_statistics_map *me) +{ + if (me) { + if (me->data_allocated) + kvfree(me->data_ptr); + kvfree(me); + } +} + +void +ia_css_isp_dvs_statistics_free(struct ia_css_isp_dvs_statistics *me) +{ + if (me) { + hmm_free(me->data_ptr); + kvfree(me); + } +} + +void ia_css_sdis_horicoef_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned int level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis_vertcoef_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned int level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis_horiproj_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned int level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis_vertproj_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned int level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h new file mode 100644 index 000000000..0d0ed96e0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_HOST_H +#define __IA_CSS_SDIS_HOST_H + +#include "ia_css_sdis_types.h" +#include "ia_css_binary.h" +#include "ia_css_stream.h" +#include "sh_css_params.h" + +extern const struct ia_css_dvs_coefficients default_sdis_config; + +/* Opaque here, since size is binary dependent. */ +struct sh_css_isp_sdis_hori_coef_tbl; +struct sh_css_isp_sdis_vert_coef_tbl; +struct sh_css_isp_sdis_hori_proj_tbl; +struct sh_css_isp_sdis_vert_proj_tbl; + +void ia_css_sdis_horicoef_vmem_encode( + struct sh_css_isp_sdis_hori_coef_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned int size); + +void ia_css_sdis_vertcoef_vmem_encode( + struct sh_css_isp_sdis_vert_coef_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned int size); + +void ia_css_sdis_horiproj_encode( + struct sh_css_isp_sdis_hori_proj_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned int size); + +void ia_css_sdis_vertproj_encode( + struct sh_css_isp_sdis_vert_proj_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned int size); + +void ia_css_get_isp_dis_coefficients( + struct ia_css_stream *stream, + short *horizontal_coefficients, + short *vertical_coefficients); + +int +ia_css_get_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats); + +void +ia_css_translate_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats); + +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs_statistics_allocate( + const struct ia_css_dvs_grid_info *grid); + +void +ia_css_isp_dvs_statistics_free( + struct ia_css_isp_dvs_statistics *me); + +size_t ia_css_sdis_hor_coef_tbl_bytes(const struct ia_css_binary *binary); +size_t ia_css_sdis_ver_coef_tbl_bytes(const struct ia_css_binary *binary); + +void +ia_css_sdis_init_info( + struct ia_css_sdis_info *dis, + unsigned int sc_3a_dis_width, + unsigned int sc_3a_dis_padded_width, + unsigned int sc_3a_dis_height, + unsigned int isp_pipe_version, + unsigned int enabled); + +void ia_css_sdis_clear_coefficients( + struct ia_css_dvs_coefficients *dvs_coefs); + +void ia_css_sdis_horicoef_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned int level); + +void ia_css_sdis_vertcoef_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned int level); + +void ia_css_sdis_horiproj_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned int level); + +void ia_css_sdis_vertproj_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned int level); + +#endif /* __IA_CSS_SDIS_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h new file mode 100644 index 000000000..a8f2b8afc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_TYPES_H +#define __IA_CSS_SDIS_TYPES_H + +/* @file +* CSS-API header file for DVS statistics parameters. +*/ + +/* Number of DVS coefficient types */ +#define IA_CSS_DVS_NUM_COEF_TYPES 6 + +#ifndef PIPE_GENERATION +#include "isp/kernels/sdis/common/ia_css_sdis_common_types.h" +#endif + +/* DVS 1.0 Coefficients. + * This structure describes the coefficients that are needed for the dvs statistics. + */ + +struct ia_css_dvs_coefficients { + struct ia_css_dvs_grid_info + grid;/** grid info contains the dimensions of the dvs grid */ + s16 *hor_coefs; /** the pointer to int16_t[grid.num_hor_coefs * IA_CSS_DVS_NUM_COEF_TYPES] + containing the horizontal coefficients */ + s16 *ver_coefs; /** the pointer to int16_t[grid.num_ver_coefs * IA_CSS_DVS_NUM_COEF_TYPES] + containing the vertical coefficients */ +}; + +/* DVS 1.0 Statistics. + * This structure describes the statistics that are generated using the provided coefficients. + */ + +struct ia_css_dvs_statistics { + struct ia_css_dvs_grid_info + grid;/** grid info contains the dimensions of the dvs grid */ + s32 *hor_proj; /** the pointer to int16_t[grid.height * IA_CSS_DVS_NUM_COEF_TYPES] + containing the horizontal projections */ + s32 *ver_proj; /** the pointer to int16_t[grid.width * IA_CSS_DVS_NUM_COEF_TYPES] + containing the vertical projections */ +}; + +#endif /* __IA_CSS_SDIS_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.c new file mode 100644 index 000000000..c13de289a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include +#include "ia_css_debug.h" +#include "ia_css_sdis2.host.h" + +const struct ia_css_dvs2_coefficients default_sdis2_config = { + .grid = { 0, 0, 0, 0, 0, 0, 0, 0 }, + .hor_coefs = { NULL, NULL, NULL, NULL }, + .ver_coefs = { NULL, NULL, NULL, NULL }, +}; + +static void +fill_row(short *private, const short *public, unsigned int width, + unsigned int padding) +{ + memcpy(private, public, width * sizeof(short)); + memset(&private[width], 0, padding * sizeof(short)); +} + +void ia_css_sdis2_horicoef_vmem_encode( + struct sh_css_isp_sdis_hori_coef_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned int size) +{ + unsigned int aligned_width = from->grid.aligned_width * + from->grid.bqs_per_grid_cell; + unsigned int width = from->grid.num_hor_coefs; + int padding = aligned_width - width; + unsigned int stride = size / IA_CSS_DVS2_NUM_COEF_TYPES / sizeof(short); + unsigned int total_bytes = aligned_width * IA_CSS_DVS2_NUM_COEF_TYPES * + sizeof(short); + short *private = (short *)to; + + /* Copy the table, add padding */ + assert(padding >= 0); + assert(total_bytes <= size); + assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof( + short)) == 0); + fill_row(&private[0 * stride], from->hor_coefs.odd_real, width, padding); + fill_row(&private[1 * stride], from->hor_coefs.odd_imag, width, padding); + fill_row(&private[2 * stride], from->hor_coefs.even_real, width, padding); + fill_row(&private[3 * stride], from->hor_coefs.even_imag, width, padding); +} + +void ia_css_sdis2_vertcoef_vmem_encode( + struct sh_css_isp_sdis_vert_coef_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned int size) +{ + unsigned int aligned_height = from->grid.aligned_height * + from->grid.bqs_per_grid_cell; + unsigned int height = from->grid.num_ver_coefs; + int padding = aligned_height - height; + unsigned int stride = size / IA_CSS_DVS2_NUM_COEF_TYPES / sizeof(short); + unsigned int total_bytes = aligned_height * IA_CSS_DVS2_NUM_COEF_TYPES * + sizeof(short); + short *private = (short *)to; + + /* Copy the table, add padding */ + assert(padding >= 0); + assert(total_bytes <= size); + assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof( + short)) == 0); + fill_row(&private[0 * stride], from->ver_coefs.odd_real, height, padding); + fill_row(&private[1 * stride], from->ver_coefs.odd_imag, height, padding); + fill_row(&private[2 * stride], from->ver_coefs.even_real, height, padding); + fill_row(&private[3 * stride], from->ver_coefs.even_imag, height, padding); +} + +void ia_css_sdis2_horiproj_encode( + struct sh_css_isp_sdis_hori_proj_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned int size) +{ + (void)to; + (void)from; + (void)size; +} + +void ia_css_sdis2_vertproj_encode( + struct sh_css_isp_sdis_vert_proj_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned int size) +{ + (void)to; + (void)from; + (void)size; +} + +void ia_css_get_isp_dvs2_coefficients( + struct ia_css_stream *stream, + short *hor_coefs_odd_real, + short *hor_coefs_odd_imag, + short *hor_coefs_even_real, + short *hor_coefs_even_imag, + short *ver_coefs_odd_real, + short *ver_coefs_odd_imag, + short *ver_coefs_even_real, + short *ver_coefs_even_imag) +{ + struct ia_css_isp_parameters *params; + unsigned int hor_num_3a, ver_num_3a; + struct ia_css_binary *dvs_binary; + + IA_CSS_ENTER("void"); + + assert(stream); + assert(hor_coefs_odd_real); + assert(hor_coefs_odd_imag); + assert(hor_coefs_even_real); + assert(hor_coefs_even_imag); + assert(ver_coefs_odd_real); + assert(ver_coefs_odd_imag); + assert(ver_coefs_even_real); + assert(ver_coefs_even_imag); + + params = stream->isp_params_configs; + + /* Only video pipe supports DVS */ + dvs_binary = ia_css_stream_get_dvs_binary(stream); + if (!dvs_binary) + return; + + hor_num_3a = dvs_binary->dis.coef.dim.width; + ver_num_3a = dvs_binary->dis.coef.dim.height; + + memcpy(hor_coefs_odd_real, params->dvs2_coefs.hor_coefs.odd_real, + hor_num_3a * sizeof(short)); + memcpy(hor_coefs_odd_imag, params->dvs2_coefs.hor_coefs.odd_imag, + hor_num_3a * sizeof(short)); + memcpy(hor_coefs_even_real, params->dvs2_coefs.hor_coefs.even_real, + hor_num_3a * sizeof(short)); + memcpy(hor_coefs_even_imag, params->dvs2_coefs.hor_coefs.even_imag, + hor_num_3a * sizeof(short)); + memcpy(ver_coefs_odd_real, params->dvs2_coefs.ver_coefs.odd_real, + ver_num_3a * sizeof(short)); + memcpy(ver_coefs_odd_imag, params->dvs2_coefs.ver_coefs.odd_imag, + ver_num_3a * sizeof(short)); + memcpy(ver_coefs_even_real, params->dvs2_coefs.ver_coefs.even_real, + ver_num_3a * sizeof(short)); + memcpy(ver_coefs_even_imag, params->dvs2_coefs.ver_coefs.even_imag, + ver_num_3a * sizeof(short)); + + IA_CSS_LEAVE("void"); +} + +void ia_css_sdis2_clear_coefficients( + struct ia_css_dvs2_coefficients *dvs2_coefs) +{ + dvs2_coefs->hor_coefs.odd_real = NULL; + dvs2_coefs->hor_coefs.odd_imag = NULL; + dvs2_coefs->hor_coefs.even_real = NULL; + dvs2_coefs->hor_coefs.even_imag = NULL; + dvs2_coefs->ver_coefs.odd_real = NULL; + dvs2_coefs->ver_coefs.odd_imag = NULL; + dvs2_coefs->ver_coefs.even_real = NULL; + dvs2_coefs->ver_coefs.even_imag = NULL; +} + +int +ia_css_get_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats) { + struct ia_css_isp_dvs_statistics_map *map; + int ret = 0; + + IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats); + + assert(host_stats); + assert(isp_stats); + + map = ia_css_isp_dvs_statistics_map_allocate(isp_stats, NULL); + if (map) + { + hmm_load(isp_stats->data_ptr, map->data_ptr, isp_stats->size); + ia_css_translate_dvs2_statistics(host_stats, map); + ia_css_isp_dvs_statistics_map_free(map); + } else + { + IA_CSS_ERROR("out of memory"); + ret = -ENOMEM; + } + + IA_CSS_LEAVE_ERR(ret); + return ret; +} + +void +ia_css_translate_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats) +{ + unsigned int size_bytes, table_width, table_size, height; + unsigned int src_offset = 0, dst_offset = 0; + s32 *htemp_ptr, *vtemp_ptr; + + assert(host_stats); + assert(host_stats->hor_prod.odd_real); + assert(host_stats->hor_prod.odd_imag); + assert(host_stats->hor_prod.even_real); + assert(host_stats->hor_prod.even_imag); + assert(host_stats->ver_prod.odd_real); + assert(host_stats->ver_prod.odd_imag); + assert(host_stats->ver_prod.even_real); + assert(host_stats->ver_prod.even_imag); + assert(isp_stats); + assert(isp_stats->hor_proj); + assert(isp_stats->ver_proj); + + IA_CSS_ENTER("hor_coefs.odd_real=%p, hor_coefs.odd_imag=%p, hor_coefs.even_real=%p, hor_coefs.even_imag=%p, ver_coefs.odd_real=%p, ver_coefs.odd_imag=%p, ver_coefs.even_real=%p, ver_coefs.even_imag=%p, haddr=%p, vaddr=%p", + host_stats->hor_prod.odd_real, host_stats->hor_prod.odd_imag, + host_stats->hor_prod.even_real, host_stats->hor_prod.even_imag, + host_stats->ver_prod.odd_real, host_stats->ver_prod.odd_imag, + host_stats->ver_prod.even_real, host_stats->ver_prod.even_imag, + isp_stats->hor_proj, isp_stats->ver_proj); + + /* Host side: reflecting the true width in bytes */ + size_bytes = host_stats->grid.aligned_width * sizeof(*htemp_ptr); + + /* DDR side: need to be aligned to the system bus width */ + /* statistics table width in terms of 32-bit words*/ + table_width = CEIL_MUL(size_bytes, + HIVE_ISP_DDR_WORD_BYTES) / sizeof(*htemp_ptr); + table_size = table_width * host_stats->grid.aligned_height; + + htemp_ptr = isp_stats->hor_proj; /* horizontal stats */ + vtemp_ptr = isp_stats->ver_proj; /* vertical stats */ + for (height = 0; height < host_stats->grid.aligned_height; height++) { + /* hor stats */ + memcpy(host_stats->hor_prod.odd_real + dst_offset, + &htemp_ptr[0 * table_size + src_offset], size_bytes); + memcpy(host_stats->hor_prod.odd_imag + dst_offset, + &htemp_ptr[1 * table_size + src_offset], size_bytes); + memcpy(host_stats->hor_prod.even_real + dst_offset, + &htemp_ptr[2 * table_size + src_offset], size_bytes); + memcpy(host_stats->hor_prod.even_imag + dst_offset, + &htemp_ptr[3 * table_size + src_offset], size_bytes); + + /* ver stats */ + memcpy(host_stats->ver_prod.odd_real + dst_offset, + &vtemp_ptr[0 * table_size + src_offset], size_bytes); + memcpy(host_stats->ver_prod.odd_imag + dst_offset, + &vtemp_ptr[1 * table_size + src_offset], size_bytes); + memcpy(host_stats->ver_prod.even_real + dst_offset, + &vtemp_ptr[2 * table_size + src_offset], size_bytes); + memcpy(host_stats->ver_prod.even_imag + dst_offset, + &vtemp_ptr[3 * table_size + src_offset], size_bytes); + + src_offset += table_width; /* aligned table width */ + dst_offset += host_stats->grid.aligned_width; + } + + IA_CSS_LEAVE("void"); +} + +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs2_statistics_allocate( + const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_isp_dvs_statistics *me; + int size; + + assert(grid); + + IA_CSS_ENTER("grid=%p", grid); + + if (!grid->enable) + return NULL; + + me = kvcalloc(1, sizeof(*me), GFP_KERNEL); + if (!me) + goto err; + + /* on ISP 2 SDIS DMA model, every row of projection table width must be + aligned to HIVE_ISP_DDR_WORD_BYTES + */ + size = CEIL_MUL(sizeof(int) * grid->aligned_width, HIVE_ISP_DDR_WORD_BYTES) + * grid->aligned_height * IA_CSS_DVS2_NUM_COEF_TYPES; + + me->size = 2 * size; + me->data_ptr = hmm_alloc(me->size); + if (me->data_ptr == mmgr_NULL) + goto err; + me->hor_proj = me->data_ptr; + me->hor_size = size; + me->ver_proj = me->data_ptr + size; + me->ver_size = size; + + IA_CSS_LEAVE("return=%p", me); + return me; +err: + ia_css_isp_dvs2_statistics_free(me); + IA_CSS_LEAVE("return=%p", NULL); + + return NULL; +} + +void +ia_css_isp_dvs2_statistics_free(struct ia_css_isp_dvs_statistics *me) +{ + if (me) { + hmm_free(me->data_ptr); + kvfree(me); + } +} + +void ia_css_sdis2_horicoef_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned int level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis2_vertcoef_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned int level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis2_horiproj_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned int level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis2_vertproj_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned int level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h new file mode 100644 index 000000000..e0e6b9c33 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS2_HOST_H +#define __IA_CSS_SDIS2_HOST_H + +#include "ia_css_sdis2_types.h" +#include "ia_css_binary.h" +#include "ia_css_stream.h" +#include "sh_css_params.h" + +extern const struct ia_css_dvs2_coefficients default_sdis2_config; + +/* Opaque here, since size is binary dependent. */ +struct sh_css_isp_sdis_hori_coef_tbl; +struct sh_css_isp_sdis_vert_coef_tbl; +struct sh_css_isp_sdis_hori_proj_tbl; +struct sh_css_isp_sdis_vert_proj_tbl; + +void ia_css_sdis2_horicoef_vmem_encode( + struct sh_css_isp_sdis_hori_coef_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned int size); + +void ia_css_sdis2_vertcoef_vmem_encode( + struct sh_css_isp_sdis_vert_coef_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned int size); + +void ia_css_sdis2_horiproj_encode( + struct sh_css_isp_sdis_hori_proj_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned int size); + +void ia_css_sdis2_vertproj_encode( + struct sh_css_isp_sdis_vert_proj_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned int size); + +void ia_css_get_isp_dvs2_coefficients( + struct ia_css_stream *stream, + short *hor_coefs_odd_real, + short *hor_coefs_odd_imag, + short *hor_coefs_even_real, + short *hor_coefs_even_imag, + short *ver_coefs_odd_real, + short *ver_coefs_odd_imag, + short *ver_coefs_even_real, + short *ver_coefs_even_imag); + +void ia_css_sdis2_clear_coefficients( + struct ia_css_dvs2_coefficients *dvs2_coefs); + +int +ia_css_get_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats); + +void +ia_css_translate_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats); + +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs2_statistics_allocate( + const struct ia_css_dvs_grid_info *grid); + +void +ia_css_isp_dvs2_statistics_free( + struct ia_css_isp_dvs_statistics *me); + +void ia_css_sdis2_horicoef_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned int level); + +void ia_css_sdis2_vertcoef_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned int level); + +void ia_css_sdis2_horiproj_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned int level); + +void ia_css_sdis2_vertproj_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned int level); + +#endif /* __IA_CSS_SDIS2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h new file mode 100644 index 000000000..d75b72e95 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS2_TYPES_H +#define __IA_CSS_SDIS2_TYPES_H + +/* @file +* CSS-API header file for DVS statistics parameters. +*/ + +/* Number of DVS coefficient types */ +#define IA_CSS_DVS2_NUM_COEF_TYPES 4 + +#ifndef PIPE_GENERATION +#include "isp/kernels/sdis/common/ia_css_sdis_common_types.h" +#endif + +/* DVS 2.0 Coefficient types. This structure contains 4 pointers to + * arrays that contain the coeffients for each type. + */ +struct ia_css_dvs2_coef_types { + s16 *odd_real; /** real part of the odd coefficients*/ + s16 *odd_imag; /** imaginary part of the odd coefficients*/ + s16 *even_real;/** real part of the even coefficients*/ + s16 *even_imag;/** imaginary part of the even coefficients*/ +}; + +/* DVS 2.0 Coefficients. This structure describes the coefficients that are needed for the dvs statistics. + * e.g. hor_coefs.odd_real is the pointer to int16_t[grid.num_hor_coefs] containing the horizontal odd real + * coefficients. + */ +struct ia_css_dvs2_coefficients { + struct ia_css_dvs_grid_info + grid; /** grid info contains the dimensions of the dvs grid */ + struct ia_css_dvs2_coef_types + hor_coefs; /** struct with pointers that contain the horizontal coefficients */ + struct ia_css_dvs2_coef_types + ver_coefs; /** struct with pointers that contain the vertical coefficients */ +}; + +/* DVS 2.0 Statistic types. This structure contains 4 pointers to + * arrays that contain the statistics for each type. + */ +struct ia_css_dvs2_stat_types { + s32 *odd_real; /** real part of the odd statistics*/ + s32 *odd_imag; /** imaginary part of the odd statistics*/ + s32 *even_real;/** real part of the even statistics*/ + s32 *even_imag;/** imaginary part of the even statistics*/ +}; + +/* DVS 2.0 Statistics. This structure describes the statistics that are generated using the provided coefficients. + * e.g. hor_prod.odd_real is the pointer to int16_t[grid.aligned_height][grid.aligned_width] containing + * the horizontal odd real statistics. Valid statistics data area is int16_t[0..grid.height-1][0..grid.width-1] + */ +struct ia_css_dvs2_statistics { + struct ia_css_dvs_grid_info + grid; /** grid info contains the dimensions of the dvs grid */ + struct ia_css_dvs2_stat_types + hor_prod; /** struct with pointers that contain the horizontal statistics */ + struct ia_css_dvs2_stat_types + ver_prod; /** struct with pointers that contain the vertical statistics */ +}; + +#endif /* __IA_CSS_SDIS2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.c new file mode 100644 index 000000000..fef8c5457 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_debug.h" +#include "ia_css_tdf.host.h" + +static const s16 g_pyramid[8][8] = { + {128, 384, 640, 896, 896, 640, 384, 128}, + {384, 1152, 1920, 2688, 2688, 1920, 1152, 384}, + {640, 1920, 3200, 4480, 4480, 3200, 1920, 640}, + {896, 2688, 4480, 6272, 6272, 4480, 2688, 896}, + {896, 2688, 4480, 6272, 6272, 4480, 2688, 896}, + {640, 1920, 3200, 4480, 4480, 3200, 1920, 640}, + {384, 1152, 1920, 2688, 2688, 1920, 1152, 384}, + {128, 384, 640, 896, 896, 640, 384, 128} +}; + +void +ia_css_tdf_vmem_encode( + struct ia_css_isp_tdf_vmem_params *to, + const struct ia_css_tdf_config *from, + size_t size) +{ + unsigned int i; + (void)size; + + for (i = 0; i < ISP_VEC_NELEMS; i++) { + to->pyramid[0][i] = g_pyramid[i / 8][i % 8]; + to->threshold_flat[0][i] = from->thres_flat_table[i]; + to->threshold_detail[0][i] = from->thres_detail_table[i]; + } +} + +void +ia_css_tdf_encode( + struct ia_css_isp_tdf_dmem_params *to, + const struct ia_css_tdf_config *from, + size_t size) +{ + (void)size; + to->Epsilon_0 = from->epsilon_0; + to->Epsilon_1 = from->epsilon_1; + to->EpsScaleText = from->eps_scale_text; + to->EpsScaleEdge = from->eps_scale_edge; + to->Sepa_flat = from->sepa_flat; + to->Sepa_Edge = from->sepa_edge; + to->Blend_Flat = from->blend_flat; + to->Blend_Text = from->blend_text; + to->Blend_Edge = from->blend_edge; + to->Shading_Gain = from->shading_gain; + to->Shading_baseGain = from->shading_base_gain; + to->LocalY_Gain = from->local_y_gain; + to->LocalY_baseGain = from->local_y_base_gain; +} + +void +ia_css_tdf_debug_dtrace( + const struct ia_css_tdf_config *config, + unsigned int level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h new file mode 100644 index 000000000..7e44d78c5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TDF_HOST_H +#define __IA_CSS_TDF_HOST_H + +#include "ia_css_tdf_types.h" +#include "ia_css_tdf_param.h" + +void +ia_css_tdf_vmem_encode( + struct ia_css_isp_tdf_vmem_params *to, + const struct ia_css_tdf_config *from, + size_t size); + +void +ia_css_tdf_encode( + struct ia_css_isp_tdf_dmem_params *to, + const struct ia_css_tdf_config *from, + size_t size); + +void +ia_css_tdf_debug_dtrace( + const struct ia_css_tdf_config *config, unsigned int level) +; + +#endif /* __IA_CSS_TDF_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf_param.h new file mode 100644 index 000000000..e904f7122 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf_param.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TDF_PARAM_H +#define __IA_CSS_TDF_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +struct ia_css_isp_tdf_vmem_params { + VMEM_ARRAY(pyramid, ISP_VEC_NELEMS); + VMEM_ARRAY(threshold_flat, ISP_VEC_NELEMS); + VMEM_ARRAY(threshold_detail, ISP_VEC_NELEMS); +}; + +struct ia_css_isp_tdf_dmem_params { + s32 Epsilon_0; + s32 Epsilon_1; + s32 EpsScaleText; + s32 EpsScaleEdge; + s32 Sepa_flat; + s32 Sepa_Edge; + s32 Blend_Flat; + s32 Blend_Text; + s32 Blend_Edge; + s32 Shading_Gain; + s32 Shading_baseGain; + s32 LocalY_Gain; + s32 LocalY_baseGain; +}; + +#endif /* __IA_CSS_TDF_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h new file mode 100644 index 000000000..0f69f9128 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TDF_TYPES_H +#define __IA_CSS_TDF_TYPES_H + +/* @file +* CSS-API header file for Transform Domain Filter parameters. +*/ + +#include "type_support.h" + +/* Transform Domain Filter configuration + * + * \brief TDF public parameters. + * \details Struct with all parameters for the TDF kernel that can be set + * from the CSS API. + * + * ISP2.6.1: TDF is used. + */ +struct ia_css_tdf_config { + s32 thres_flat_table[64]; /** Final optimized strength table of NR for flat region. */ + s32 thres_detail_table[64]; /** Final optimized strength table of NR for detail region. */ + s32 epsilon_0; /** Coefficient to control variance for dark area (for flat region). */ + s32 epsilon_1; /** Coefficient to control variance for bright area (for flat region). */ + s32 eps_scale_text; /** Epsilon scaling coefficient for texture region. */ + s32 eps_scale_edge; /** Epsilon scaling coefficient for edge region. */ + s32 sepa_flat; /** Threshold to judge flat (edge < m_Flat_thre). */ + s32 sepa_edge; /** Threshold to judge edge (edge > m_Edge_thre). */ + s32 blend_flat; /** Blending ratio at flat region. */ + s32 blend_text; /** Blending ratio at texture region. */ + s32 blend_edge; /** Blending ratio at edge region. */ + s32 shading_gain; /** Gain of Shading control. */ + s32 shading_base_gain; /** Base Gain of Shading control. */ + s32 local_y_gain; /** Gain of local luminance control. */ + s32 local_y_base_gain; /** Base gain of local luminance control. */ + s32 rad_x_origin; /** Initial x coord. for radius computation. */ + s32 rad_y_origin; /** Initial y coord. for radius computation. */ +}; + +#endif /* __IA_CSS_TDF_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h new file mode 100644 index 000000000..4b53fddfc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef _IA_CSS_TNR3_TYPES_H +#define _IA_CSS_TNR3_TYPES_H + +/* @file +* CSS-API header file for Temporal Noise Reduction v3 (TNR3) kernel +*/ + +/** + * \brief Number of piecewise linear segments. + * \details The parameters to TNR3 are specified as a piecewise linear segment. + * The number of such segments is fixed at 3. + */ +#define TNR3_NUM_SEGMENTS 3 + +/* Temporal Noise Reduction v3 (TNR3) configuration. + * The parameter to this kernel is fourfold + * 1. Three piecewise linear graphs (one for each plane) with three segments + * each. Each line graph has Luma values on the x axis and sigma values for + * each plane on the y axis. The three linear segments may have a different + * slope and the point of Luma value which where the slope may change is called + * a "Knee" point. As there are three such segments, four points need to be + * specified each on the Luma axis and the per plane Sigma axis. On the Luma + * axis two points are fixed (namely 0 and maximum luma value - depending on + * ISP bit depth). The other two points are the points where the slope may + * change its value. These two points are called knee points. The four points on + * the per plane sigma axis are also specified at the interface. + * 2. One rounding adjustment parameter for each plane + * 3. One maximum feedback threshold value for each plane + * 4. Selection of the reference frame buffer to be used for noise reduction. + */ +struct ia_css_tnr3_kernel_config { + unsigned int maxfb_y; /** Maximum Feedback Gain for Y */ + unsigned int maxfb_u; /** Maximum Feedback Gain for U */ + unsigned int maxfb_v; /** Maximum Feedback Gain for V */ + unsigned int round_adj_y; /** Rounding Adjust for Y */ + unsigned int round_adj_u; /** Rounding Adjust for U */ + unsigned int round_adj_v; /** Rounding Adjust for V */ + unsigned int knee_y[TNR3_NUM_SEGMENTS - 1]; /** Knee points */ + unsigned int sigma_y[TNR3_NUM_SEGMENTS + + 1]; /** Standard deviation for Y at points Y0, Y1, Y2, Y3 */ + unsigned int sigma_u[TNR3_NUM_SEGMENTS + + 1]; /** Standard deviation for U at points U0, U1, U2, U3 */ + unsigned int sigma_v[TNR3_NUM_SEGMENTS + + 1]; /** Standard deviation for V at points V0, V1, V2, V3 */ + unsigned int + ref_buf_select; /** Selection of the reference buffer */ +}; + +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.c new file mode 100644 index 000000000..a5fea753e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "ia_css_frame.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" +#include "assert_support.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" + +#include "ia_css_tnr.host.h" +const struct ia_css_tnr_config default_tnr_config = { + 32768, + 32, + 32, +}; + +void +ia_css_tnr_encode( + struct sh_css_isp_tnr_params *to, + const struct ia_css_tnr_config *from, + unsigned int size) +{ + (void)size; + to->coef = + uDIGIT_FITTING(from->gain, 16, SH_CSS_TNR_COEF_SHIFT); + to->threshold_Y = + uDIGIT_FITTING(from->threshold_y, 16, SH_CSS_ISP_YUV_BITS); + to->threshold_C = + uDIGIT_FITTING(from->threshold_uv, 16, SH_CSS_ISP_YUV_BITS); +} + +void +ia_css_tnr_dump( + const struct sh_css_isp_tnr_params *tnr, + unsigned int level) +{ + if (!tnr) return; + ia_css_debug_dtrace(level, "Temporal Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "tnr_coef", tnr->coef); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "tnr_threshold_Y", tnr->threshold_Y); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "tnr_threshold_C", tnr->threshold_C); +} + +void +ia_css_tnr_debug_dtrace( + const struct ia_css_tnr_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.gain=%d, config.threshold_y=%d, config.threshold_uv=%d\n", + config->gain, + config->threshold_y, config->threshold_uv); +} + +int ia_css_tnr_config(struct sh_css_isp_tnr_isp_config *to, + const struct ia_css_tnr_configuration *from, + unsigned int size) +{ + unsigned int elems_a = ISP_VEC_NELEMS; + unsigned int i; + int ret; + + ret = ia_css_dma_configure_from_info(&to->port_b, &from->tnr_frames[0]->frame_info); + if (ret) + return ret; + to->width_a_over_b = elems_a / to->port_b.elems; + to->frame_height = from->tnr_frames[0]->frame_info.res.height; + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) { + to->tnr_frame_addr[i] = from->tnr_frames[i]->data + + from->tnr_frames[i]->planes.yuyv.offset; + } + + /* Assume divisiblity here, may need to generalize to fixed point. */ + if (elems_a % to->port_b.elems != 0) + return -EINVAL; + + return 0; +} + +int ia_css_tnr_configure(const struct ia_css_binary *binary, + const struct ia_css_frame * const *frames) +{ + struct ia_css_tnr_configuration config; + unsigned int i; + + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) + config.tnr_frames[i] = frames[i]; + + return ia_css_configure_tnr(binary, &config); +} + +void +ia_css_init_tnr_state( + struct sh_css_isp_tnr_dmem_state *state, + size_t size) +{ + (void)size; + + assert(NUM_VIDEO_TNR_FRAMES >= 2); + assert(sizeof(*state) == size); + state->tnr_in_buf_idx = 0; + state->tnr_out_buf_idx = 1; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h new file mode 100644 index 000000000..acf92052b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TNR_HOST_H +#define __IA_CSS_TNR_HOST_H + +#include "ia_css_binary.h" +#include "ia_css_tnr_state.h" +#include "ia_css_tnr_types.h" +#include "ia_css_tnr_param.h" + +extern const struct ia_css_tnr_config default_tnr_config; + +void +ia_css_tnr_encode( + struct sh_css_isp_tnr_params *to, + const struct ia_css_tnr_config *from, + unsigned int size); + +void +ia_css_tnr_dump( + const struct sh_css_isp_tnr_params *tnr, + unsigned int level); + +void +ia_css_tnr_debug_dtrace( + const struct ia_css_tnr_config *config, + unsigned int level); + +int ia_css_tnr_config(struct sh_css_isp_tnr_isp_config *to, + const struct ia_css_tnr_configuration *from, + unsigned int size); + +int ia_css_tnr_configure(const struct ia_css_binary *binary, + const struct ia_css_frame * const *frames); + +void +ia_css_init_tnr_state( + struct sh_css_isp_tnr_dmem_state *state, + size_t size); +#endif /* __IA_CSS_TNR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_param.h new file mode 100644 index 000000000..551dd5cfa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_param.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TNR_PARAM_H +#define __IA_CSS_TNR_PARAM_H + +#include "type_support.h" +#include "sh_css_defs.h" +#include "dma.h" + +/* TNR (Temporal Noise Reduction) */ +struct sh_css_isp_tnr_params { + s32 coef; + s32 threshold_Y; + s32 threshold_C; +}; + +struct ia_css_tnr_configuration { + const struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; +}; + +struct sh_css_isp_tnr_isp_config { + u32 width_a_over_b; + u32 frame_height; + struct dma_port_config port_b; + ia_css_ptr tnr_frame_addr[NUM_VIDEO_TNR_FRAMES]; +}; + +#endif /* __IA_CSS_TNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_state.h b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_state.h new file mode 100644 index 000000000..d57238423 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_state.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TNR_STATE_H +#define __IA_CSS_TNR_STATE_H + +#include "type_support.h" + +/* TNR (temporal noise reduction) */ +struct sh_css_isp_tnr_dmem_state { + u32 tnr_in_buf_idx; + u32 tnr_out_buf_idx; +}; + +#endif /* __IA_CSS_TNR_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h new file mode 100644 index 000000000..92dbe1389 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TNR_TYPES_H +#define __IA_CSS_TNR_TYPES_H + +/* @file +* CSS-API header file for Temporal Noise Reduction (TNR) parameters. +*/ + +/* Temporal Noise Reduction (TNR) configuration. + * + * When difference between current frame and previous frame is less than or + * equal to threshold, TNR works and current frame is mixed + * with previous frame. + * When difference between current frame and previous frame is greater + * than threshold, we judge motion is detected. Then, TNR does not work and + * current frame is outputted as it is. + * Therefore, when threshold_y and threshold_uv are set as 0, TNR can be disabled. + * + * ISP block: TNR1 + * ISP1: TNR1 is used. + * ISP2: TNR1 is used. + */ + +struct ia_css_tnr_config { + ia_css_u0_16 gain; /** Interpolation ratio of current frame + and previous frame. + gain=0.0 -> previous frame is outputted. + gain=1.0 -> current frame is outputted. + u0.16, [0,65535], + default 32768(0.5), ineffective 65535(almost 1.0) */ + ia_css_u0_16 threshold_y; /** Threshold to enable interpolation of Y. + If difference between current frame and + previous frame is greater than threshold_y, + TNR for Y is disabled. + u0.16, [0,65535], default/ineffective 0 */ + ia_css_u0_16 threshold_uv; /** Threshold to enable interpolation of + U/V. + If difference between current frame and + previous frame is greater than threshold_uv, + TNR for UV is disabled. + u0.16, [0,65535], default/ineffective 0 */ +}; + +#endif /* __IA_CSS_TNR_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/uds/uds_1.0/ia_css_uds_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/uds/uds_1.0/ia_css_uds_param.h new file mode 100644 index 000000000..784b5c4fa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/uds/uds_1.0/ia_css_uds_param.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_UDS_PARAM_H +#define __IA_CSS_UDS_PARAM_H + +#include "sh_css_uds.h" + +/* uds (Up and Down scaling) */ +struct ia_css_uds_config { + struct sh_css_crop_pos crop_pos; + struct sh_css_uds_info uds; +}; + +struct sh_css_sp_uds_params { + struct sh_css_crop_pos crop_pos; + struct sh_css_uds_info uds; +}; + +#endif /* __IA_CSS_UDS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf.host.c new file mode 100644 index 000000000..aecdcbe04 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf.host.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "atomisp_internal.h" + +#include "ia_css_vf.host.h" +#include +#include +#include +#include +#include +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" + +#include "isp.h" + +int ia_css_vf_config(struct sh_css_isp_vf_isp_config *to, + const struct ia_css_vf_configuration *from, + unsigned int size) +{ + unsigned int elems_a = ISP_VEC_NELEMS; + int ret; + + to->vf_downscale_bits = from->vf_downscale_bits; + to->enable = from->info != NULL; + + if (from->info) { + ia_css_frame_info_to_frame_sp_info(&to->info, from->info); + ret = ia_css_dma_configure_from_info(&to->dma.port_b, from->info); + if (ret) + return ret; + to->dma.width_a_over_b = elems_a / to->dma.port_b.elems; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + if (elems_a % to->dma.port_b.elems != 0) + return -EINVAL; + } + return 0; +} + +/* compute the log2 of the downscale factor needed to get closest + * to the requested viewfinder resolution on the upper side. The output cannot + * be smaller than the requested viewfinder resolution. + */ +int +sh_css_vf_downscale_log2( + const struct ia_css_frame_info *out_info, + const struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2) { + unsigned int ds_log2 = 0; + unsigned int out_width; + + if ((!out_info) || (!vf_info)) + return -EINVAL; + + out_width = out_info->res.width; + + if (out_width == 0) + return -EINVAL; + + /* downscale until width smaller than the viewfinder width. We don't + * test for the height since the vmem buffers only put restrictions on + * the width of a line, not on the number of lines in a frame. + */ + while (out_width >= vf_info->res.width) + { + ds_log2++; + out_width /= 2; + } + /* now width is smaller, so we go up one step */ + if ((ds_log2 > 0) && (out_width < ia_css_binary_max_vf_width())) + ds_log2--; + /* TODO: use actual max input resolution of vf_pp binary */ + if ((out_info->res.width >> ds_log2) >= 2 * ia_css_binary_max_vf_width()) + return -EINVAL; + *downscale_log2 = ds_log2; + return 0; +} + +static int +configure_kernel( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *out_info, + const struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2, + struct ia_css_vf_configuration *config) { + int err; + unsigned int vf_log_ds = 0; + + /* First compute value */ + if (vf_info) + { + err = sh_css_vf_downscale_log2(out_info, vf_info, &vf_log_ds); + if (err) + return err; + } + vf_log_ds = min(vf_log_ds, info->vf_dec.max_log_downscale); + *downscale_log2 = vf_log_ds; + + /* Then store it in isp config section */ + config->vf_downscale_bits = vf_log_ds; + return 0; +} + +static void +configure_dma( + struct ia_css_vf_configuration *config, + const struct ia_css_frame_info *vf_info) +{ + config->info = vf_info; +} + +int ia_css_vf_configure(const struct ia_css_binary *binary, + const struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2) +{ + int err; + struct ia_css_vf_configuration config; + const struct ia_css_binary_info *info = &binary->info->sp; + + err = configure_kernel(info, out_info, vf_info, downscale_log2, &config); + if (err) + dev_warn(atomisp_dev, "Couldn't setup downscale\n"); + + configure_dma(&config, vf_info); + + if (vf_info) + vf_info->raw_bit_depth = info->dma.vfdec_bits_per_pixel; + + return ia_css_configure_vf(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf.host.h new file mode 100644 index 000000000..d6b45d375 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf.host.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_VF_HOST_H +#define __IA_CSS_VF_HOST_H + +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" + +#include "ia_css_vf_types.h" +#include "ia_css_vf_param.h" + +/* compute the log2 of the downscale factor needed to get closest + * to the requested viewfinder resolution on the upper side. The output cannot + * be smaller than the requested viewfinder resolution. + */ +int +sh_css_vf_downscale_log2( + const struct ia_css_frame_info *out_info, + const struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2); + +int ia_css_vf_config(struct sh_css_isp_vf_isp_config *to, + const struct ia_css_vf_configuration *from, + unsigned int size); + +int +ia_css_vf_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2); + +#endif /* __IA_CSS_VF_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf_param.h new file mode 100644 index 000000000..487ddf163 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf_param.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_VF_PARAM_H +#define __IA_CSS_VF_PARAM_H + +#include "type_support.h" +#include "dma.h" +#include "gc/gc_1.0/ia_css_gc_param.h" /* GAMMA_OUTPUT_BITS */ +#include "ia_css_frame_comm.h" /* ia_css_frame_sp_info */ +#include "ia_css_vf_types.h" + +#define VFDEC_BITS_PER_PIXEL GAMMA_OUTPUT_BITS + +/* Viewfinder decimation */ +struct sh_css_isp_vf_isp_config { + u32 vf_downscale_bits; /** Log VF downscale value */ + u32 enable; + struct ia_css_frame_sp_info info; + struct { + u32 width_a_over_b; + struct dma_port_config port_b; + } dma; +}; + +#endif /* __IA_CSS_VF_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf_types.h new file mode 100644 index 000000000..24fbb61d3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/vf/vf_1.0/ia_css_vf_types.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_VF_TYPES_H +#define __IA_CSS_VF_TYPES_H + +/* Viewfinder decimation + * + * ISP block: vfeven_horizontal_downscale + */ + +#include +#include + +struct ia_css_vf_configuration { + u32 vf_downscale_bits; /** Log VF downscale value */ + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_VF_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb.host.c new file mode 100644 index 000000000..01d1a2d36 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb.host.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "sh_css_frac.h" + +#include "ia_css_wb.host.h" + +const struct ia_css_wb_config default_wb_config = { + 1, + 32768, + 32768, + 32768, + 32768 +}; + +void +ia_css_wb_encode( + struct sh_css_isp_wb_params *to, + const struct ia_css_wb_config *from, + unsigned int size) +{ + (void)size; + to->gain_shift = + uISP_REG_BIT - from->integer_bits; + to->gain_gr = + uDIGIT_FITTING(from->gr, 16 - from->integer_bits, + to->gain_shift); + to->gain_r = + uDIGIT_FITTING(from->r, 16 - from->integer_bits, + to->gain_shift); + to->gain_b = + uDIGIT_FITTING(from->b, 16 - from->integer_bits, + to->gain_shift); + to->gain_gb = + uDIGIT_FITTING(from->gb, 16 - from->integer_bits, + to->gain_shift); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_wb_dump( + const struct sh_css_isp_wb_params *wb, + unsigned int level) +{ + if (!wb) return; + ia_css_debug_dtrace(level, "White Balance:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_shift", wb->gain_shift); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_gr", wb->gain_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_r", wb->gain_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_b", wb->gain_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_gb", wb->gain_gb); +} + +void +ia_css_wb_debug_dtrace( + const struct ia_css_wb_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.integer_bits=%d, config.gr=%d, config.r=%d, config.b=%d, config.gb=%d\n", + config->integer_bits, + config->gr, config->r, + config->b, config->gb); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb.host.h new file mode 100644 index 000000000..ffd75c8a6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb.host.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_WB_HOST_H +#define __IA_CSS_WB_HOST_H + +#include "ia_css_wb_types.h" +#include "ia_css_wb_param.h" + +extern const struct ia_css_wb_config default_wb_config; + +void +ia_css_wb_encode( + struct sh_css_isp_wb_params *to, + const struct ia_css_wb_config *from, + unsigned int size); + +void +ia_css_wb_dump( + const struct sh_css_isp_wb_params *wb, + unsigned int level); + +void +ia_css_wb_debug_dtrace( + const struct ia_css_wb_config *wb, + unsigned int level); + +#endif /* __IA_CSS_WB_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb_param.h new file mode 100644 index 000000000..51b2ba8ef --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb_param.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_WB_PARAM_H +#define __IA_CSS_WB_PARAM_H + +#include "type_support.h" + +/* WB (White Balance) */ +struct sh_css_isp_wb_params { + s32 gain_shift; + s32 gain_gr; + s32 gain_r; + s32 gain_b; + s32 gain_gb; +}; + +#endif /* __IA_CSS_WB_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb_types.h new file mode 100644 index 000000000..20ae73c0e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ia_css_wb_types.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_WB_TYPES_H +#define __IA_CSS_WB_TYPES_H + +/* @file +* CSS-API header file for White Balance parameters. +*/ + +/* White Balance configuration (Gain Adjust). + * + * ISP block: WB1 + * ISP1: WB1 is used. + * ISP2: WB1 is used. + */ +struct ia_css_wb_config { + u32 integer_bits; /** Common exponent of gains. + u8.0, [0,3], + default 1, ineffective 1 */ + u32 gr; /** Significand of Gr gain. + u[integer_bits].[16-integer_bits], [0,65535], + default/ineffective 32768(u1.15, 1.0) */ + u32 r; /** Significand of R gain. + u[integer_bits].[16-integer_bits], [0,65535], + default/ineffective 32768(u1.15, 1.0) */ + u32 b; /** Significand of B gain. + u[integer_bits].[16-integer_bits], [0,65535], + default/ineffective 32768(u1.15, 1.0) */ + u32 gb; /** Significand of Gb gain. + u[integer_bits].[16-integer_bits], [0,65535], + default/ineffective 32768(u1.15, 1.0) */ +}; + +#endif /* __IA_CSS_WB_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c new file mode 100644 index 000000000..1cd596608 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "ia_css_xnr.host.h" + +const struct ia_css_xnr_config default_xnr_config = { + /* default threshold 6400 translates to 25 on ISP. */ + 6400 +}; + +void +ia_css_xnr_table_vamem_encode( + struct sh_css_isp_xnr_vamem_params *to, + const struct ia_css_xnr_table *from, + unsigned int size) +{ + (void)size; + memcpy(&to->xnr, &from->data, sizeof(to->xnr)); +} + +void +ia_css_xnr_encode( + struct sh_css_isp_xnr_params *to, + const struct ia_css_xnr_config *from, + unsigned int size) +{ + (void)size; + + to->threshold = + (uint16_t)uDIGIT_FITTING(from->threshold, 16, SH_CSS_ISP_YUV_BITS); +} + +void +ia_css_xnr_table_debug_dtrace( + const struct ia_css_xnr_table *config, + unsigned int level) +{ + (void)config; + (void)level; +} + +void +ia_css_xnr_debug_dtrace( + const struct ia_css_xnr_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.threshold=%d\n", config->threshold); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h new file mode 100644 index 000000000..686101c0b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR_HOST_H +#define __IA_CSS_XNR_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_xnr_param.h" +#include "ia_css_xnr_table.host.h" + +extern const struct ia_css_xnr_config default_xnr_config; + +void +ia_css_xnr_table_vamem_encode( + struct sh_css_isp_xnr_vamem_params *to, + const struct ia_css_xnr_table *from, + unsigned int size); + +void +ia_css_xnr_encode( + struct sh_css_isp_xnr_params *to, + const struct ia_css_xnr_config *from, + unsigned int size); + +void +ia_css_xnr_table_debug_dtrace( + const struct ia_css_xnr_table *s3a, + unsigned int level); + +void +ia_css_xnr_debug_dtrace( + const struct ia_css_xnr_config *config, + unsigned int level); + +#endif /* __IA_CSS_XNR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h new file mode 100644 index 000000000..93754f7c7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR_PARAM_H +#define __IA_CSS_XNR_PARAM_H + +#include "type_support.h" +#include + +#ifndef PIPE_GENERATION +#define SH_CSS_ISP_XNR_TABLE_SIZE_LOG2 IA_CSS_VAMEM_2_XNR_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_XNR_TABLE_SIZE IA_CSS_VAMEM_2_XNR_TABLE_SIZE + +#else +/* For pipe generation, the size is not relevant */ +#define SH_CSS_ISP_XNR_TABLE_SIZE 0 +#endif + +/* This should be vamem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_xnr_vamem_params { + u16 xnr[SH_CSS_ISP_XNR_TABLE_SIZE]; +}; + +struct sh_css_isp_xnr_params { + /* XNR threshold. + * type:u0.16 but actual valid range is:[0,255] + * valid range is dependent on SH_CSS_ISP_YUV_BITS (currently 8bits) + * default: 25 */ + u16 threshold; +}; + +#endif /* __IA_CSS_XNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.c new file mode 100644 index 000000000..e5c153086 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for memcpy() */ + +#include +#include "system_global.h" +#include "vamem.h" +#include "ia_css_types.h" +#include "ia_css_xnr_table.host.h" + +struct ia_css_xnr_table default_xnr_table; + + +static const uint16_t +default_xnr_table_data[IA_CSS_VAMEM_2_XNR_TABLE_SIZE] = { + /* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 */ + 8191 >> 1, 4096 >> 1, 2730 >> 1, 2048 >> 1, 1638 >> 1, 1365 >> 1, 1170 >> 1, 1024 >> 1, 910 >> 1, 819 >> 1, 744 >> 1, 682 >> 1, 630 >> 1, 585 >> 1, + 546 >> 1, 512 >> 1, + + /* 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 */ + 481 >> 1, 455 >> 1, 431 >> 1, 409 >> 1, 390 >> 1, 372 >> 1, 356 >> 1, 341 >> 1, 327 >> 1, 315 >> 1, 303 >> 1, 292 >> 1, 282 >> 1, 273 >> 1, 264 >> 1, + 256 >> 1, + + /* 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 */ + 248 >> 1, 240 >> 1, 234 >> 1, 227 >> 1, 221 >> 1, 215 >> 1, 210 >> 1, 204 >> 1, 199 >> 1, 195 >> 1, 190 >> 1, 186 >> 1, 182 >> 1, 178 >> 1, 174 >> 1, + 170 >> 1, + + /* 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 */ + 167 >> 1, 163 >> 1, 160 >> 1, 157 >> 1, 154 >> 1, 151 >> 1, 148 >> 1, 146 >> 1, 143 >> 1, 141 >> 1, 138 >> 1, 136 >> 1, 134 >> 1, 132 >> 1, 130 >> 1, 128 >> 1 +}; + + +void +ia_css_config_xnr_table(void) +{ + memcpy(default_xnr_table.data.vamem_2, default_xnr_table_data, + sizeof(default_xnr_table_data)); + default_xnr_table.vamem_type = IA_CSS_VAMEM_TYPE_2; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.h new file mode 100644 index 000000000..2f4ab8ad4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR_TABLE_HOST_H +#define __IA_CSS_XNR_TABLE_HOST_H + +extern struct ia_css_xnr_table default_xnr_table; + +void ia_css_config_xnr_table(void); + +#endif /* __IA_CSS_XNR_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h new file mode 100644 index 000000000..9a4d2e470 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR_TYPES_H +#define __IA_CSS_XNR_TYPES_H + +/* @file +* CSS-API header file for Extra Noise Reduction (XNR) parameters. +*/ + +/* XNR table. + * + * NOTE: The driver does not need to set this table, + * because the default values are set inside the css. + * + * This table contains coefficients used for division in XNR. + * + * u0.12, [0,4095], + * {4095, 2048, 1365, .........., 65, 64} + * ({1/1, 1/2, 1/3, ............., 1/63, 1/64}) + * + * ISP block: XNR1 + * ISP1: XNR1 is used. + * ISP2: XNR1 is used. + * + */ + +/* Number of elements in the xnr table. */ +#define IA_CSS_VAMEM_1_XNR_TABLE_SIZE_LOG2 6 +/* Number of elements in the xnr table. */ +#define IA_CSS_VAMEM_1_XNR_TABLE_SIZE BIT(IA_CSS_VAMEM_1_XNR_TABLE_SIZE_LOG2) + +/* Number of elements in the xnr table. */ +#define IA_CSS_VAMEM_2_XNR_TABLE_SIZE_LOG2 6 +/* Number of elements in the xnr table. */ +#define IA_CSS_VAMEM_2_XNR_TABLE_SIZE BIT(IA_CSS_VAMEM_2_XNR_TABLE_SIZE_LOG2) + +/** IA_CSS_VAMEM_TYPE_1(ISP2300) or + IA_CSS_VAMEM_TYPE_2(ISP2400) */ +union ia_css_xnr_data { + u16 vamem_1[IA_CSS_VAMEM_1_XNR_TABLE_SIZE]; + /** Coefficients table on vamem type1. u0.12, [0,4095] */ + u16 vamem_2[IA_CSS_VAMEM_2_XNR_TABLE_SIZE]; + /** Coefficients table on vamem type2. u0.12, [0,4095] */ +}; + +struct ia_css_xnr_table { + enum ia_css_vamem_type vamem_type; + union ia_css_xnr_data data; +}; + +struct ia_css_xnr_config { + /* XNR threshold. + * type:u0.16 valid range:[0,65535] + * default: 6400 */ + u16 threshold; +}; + +#endif /* __IA_CSS_XNR_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.c new file mode 100644 index 000000000..9c9d9b9a4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "type_support.h" +#include "math_support.h" +#include "sh_css_defs.h" +#include "ia_css_types.h" +#include "assert_support.h" +#include "ia_css_xnr3.host.h" + +/* Maximum value for alpha on ISP interface */ +#define XNR_MAX_ALPHA ((1 << (ISP_VEC_ELEMBITS - 1)) - 1) + +/* Minimum value for sigma on host interface. Lower values translate to + * max_alpha. + */ +#define XNR_MIN_SIGMA (IA_CSS_XNR3_SIGMA_SCALE / 100) + +/* + * division look-up table + * Refers to XNR3.0.5 + */ +#define XNR3_LOOK_UP_TABLE_POINTS 16 + +static const s16 x[XNR3_LOOK_UP_TABLE_POINTS] = { + 1024, 1164, 1320, 1492, 1680, 1884, 2108, 2352, + 2616, 2900, 3208, 3540, 3896, 4276, 4684, 5120 +}; + +static const s16 a[XNR3_LOOK_UP_TABLE_POINTS] = { + -7213, -5580, -4371, -3421, -2722, -2159, -6950, -5585, + -4529, -3697, -3010, -2485, -2070, -1727, -1428, 0 + }; + +static const s16 b[XNR3_LOOK_UP_TABLE_POINTS] = { + 4096, 3603, 3178, 2811, 2497, 2226, 1990, 1783, + 1603, 1446, 1307, 1185, 1077, 981, 895, 819 +}; + +static const s16 c[XNR3_LOOK_UP_TABLE_POINTS] = { + 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* + * Default kernel parameters. In general, default is bypass mode or as close + * to the ineffective values as possible. Due to the chroma down+upsampling, + * perfect bypass mode is not possible for xnr3 filter itself. Instead, the + * 'blending' parameter is used to create a bypass. + */ +const struct ia_css_xnr3_config default_xnr3_config = { + /* sigma */ + { 0, 0, 0, 0, 0, 0 }, + /* coring */ + { 0, 0, 0, 0 }, + /* blending */ + { 0 } +}; + +/* + * Compute an alpha value for the ISP kernel from sigma value on the host + * parameter interface as: alpha_scale * 1/(sigma/sigma_scale) + */ +static int32_t +compute_alpha(int sigma) +{ + s32 alpha; + int offset = sigma / 2; + + if (sigma < XNR_MIN_SIGMA) { + alpha = XNR_MAX_ALPHA; + } else { + alpha = ((IA_CSS_XNR3_SIGMA_SCALE * XNR_ALPHA_SCALE_FACTOR) + offset) / sigma; + + if (alpha > XNR_MAX_ALPHA) + alpha = XNR_MAX_ALPHA; + } + + return alpha; +} + +/* + * Compute the scaled coring value for the ISP kernel from the value on the + * host parameter interface. + */ +static int32_t +compute_coring(int coring) +{ + s32 isp_coring; + s32 isp_scale = XNR_CORING_SCALE_FACTOR; + s32 host_scale = IA_CSS_XNR3_CORING_SCALE; + s32 offset = host_scale / 2; /* fixed-point 0.5 */ + + /* Convert from public host-side scale factor to isp-side scale + * factor. Clip to [0, isp_scale-1). + */ + isp_coring = ((coring * isp_scale) + offset) / host_scale; + return min(max(isp_coring, 0), isp_scale - 1); +} + +/* + * Compute the scaled blending strength for the ISP kernel from the value on + * the host parameter interface. + */ +static int32_t +compute_blending(int strength) +{ + s32 isp_strength; + s32 isp_scale = XNR_BLENDING_SCALE_FACTOR; + s32 host_scale = IA_CSS_XNR3_BLENDING_SCALE; + s32 offset = host_scale / 2; /* fixed-point 0.5 */ + + /* Convert from public host-side scale factor to isp-side scale + * factor. The blending factor is positive on the host side, but + * negative on the ISP side because +1.0 cannot be represented + * exactly as s0.11 fixed point, but -1.0 can. + */ + isp_strength = -(((strength * isp_scale) + offset) / host_scale); + return MAX(MIN(isp_strength, 0), -isp_scale); +} + +void +ia_css_xnr3_encode( + struct sh_css_isp_xnr3_params *to, + const struct ia_css_xnr3_config *from, + unsigned int size) +{ + int kernel_size = XNR_FILTER_SIZE; + /* The adjust factor is the next power of 2 + w.r.t. the kernel size*/ + int adjust_factor = ceil_pow2(kernel_size); + s32 max_diff = (1 << (ISP_VEC_ELEMBITS - 1)) - 1; + s32 min_diff = -(1 << (ISP_VEC_ELEMBITS - 1)); + + s32 alpha_y0 = compute_alpha(from->sigma.y0); + s32 alpha_y1 = compute_alpha(from->sigma.y1); + s32 alpha_u0 = compute_alpha(from->sigma.u0); + s32 alpha_u1 = compute_alpha(from->sigma.u1); + s32 alpha_v0 = compute_alpha(from->sigma.v0); + s32 alpha_v1 = compute_alpha(from->sigma.v1); + s32 alpha_ydiff = (alpha_y1 - alpha_y0) * adjust_factor / kernel_size; + s32 alpha_udiff = (alpha_u1 - alpha_u0) * adjust_factor / kernel_size; + s32 alpha_vdiff = (alpha_v1 - alpha_v0) * adjust_factor / kernel_size; + + s32 coring_u0 = compute_coring(from->coring.u0); + s32 coring_u1 = compute_coring(from->coring.u1); + s32 coring_v0 = compute_coring(from->coring.v0); + s32 coring_v1 = compute_coring(from->coring.v1); + s32 coring_udiff = (coring_u1 - coring_u0) * adjust_factor / kernel_size; + s32 coring_vdiff = (coring_v1 - coring_v0) * adjust_factor / kernel_size; + + s32 blending = compute_blending(from->blending.strength); + + (void)size; + + /* alpha's are represented in qN.5 format */ + to->alpha.y0 = alpha_y0; + to->alpha.u0 = alpha_u0; + to->alpha.v0 = alpha_v0; + to->alpha.ydiff = min(max(alpha_ydiff, min_diff), max_diff); + to->alpha.udiff = min(max(alpha_udiff, min_diff), max_diff); + to->alpha.vdiff = min(max(alpha_vdiff, min_diff), max_diff); + + /* coring parameters are expressed in q1.NN format */ + to->coring.u0 = coring_u0; + to->coring.v0 = coring_v0; + to->coring.udiff = min(max(coring_udiff, min_diff), max_diff); + to->coring.vdiff = min(max(coring_vdiff, min_diff), max_diff); + + /* blending strength is expressed in q1.NN format */ + to->blending.strength = blending; +} + +/* ISP2401 */ +/* (void) = ia_css_xnr3_vmem_encode(*to, *from) + * ----------------------------------------------- + * VMEM Encode Function to translate UV parameters from userspace into ISP space +*/ +void +ia_css_xnr3_vmem_encode( + struct sh_css_isp_xnr3_vmem_params *to, + const struct ia_css_xnr3_config *from, + unsigned int size) +{ + unsigned int i, j, base; + const unsigned int total_blocks = 4; + const unsigned int shuffle_block = 16; + + (void)from; + (void)size; + + /* Init */ + for (i = 0; i < ISP_VEC_NELEMS; i++) { + to->x[0][i] = 0; + to->a[0][i] = 0; + to->b[0][i] = 0; + to->c[0][i] = 0; + } + + /* Constraints on "x": + * - values should be greater or equal to 0. + * - values should be ascending. + */ + assert(x[0] >= 0); + + for (j = 1; j < XNR3_LOOK_UP_TABLE_POINTS; j++) { + assert(x[j] >= 0); + assert(x[j] > x[j - 1]); + } + + /* The implementation of the calulating 1/x is based on the availability + * of the OP_vec_shuffle16 operation. + * A 64 element vector is split up in 4 blocks of 16 element. Each array is copied to + * a vector 4 times, (starting at 0, 16, 32 and 48). All array elements are copied or + * initialised as described in the KFS. The remaining elements of a vector are set to 0. + */ + /* TODO: guard this code with above assumptions */ + for (i = 0; i < total_blocks; i++) { + base = shuffle_block * i; + + for (j = 0; j < XNR3_LOOK_UP_TABLE_POINTS; j++) { + to->x[0][base + j] = x[j]; + to->a[0][base + j] = a[j]; + to->b[0][base + j] = b[j]; + to->c[0][base + j] = c[j]; + } + } +} + +/* Dummy Function added as the tool expects it*/ +void +ia_css_xnr3_debug_dtrace( + const struct ia_css_xnr3_config *config, + unsigned int level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h new file mode 100644 index 000000000..6b57990b7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_HOST_H +#define __IA_CSS_XNR3_HOST_H + +#include "ia_css_xnr3_param.h" +#include "ia_css_xnr3_types.h" + +extern const struct ia_css_xnr3_config default_xnr3_config; + +void +ia_css_xnr3_encode( + struct sh_css_isp_xnr3_params *to, + const struct ia_css_xnr3_config *from, + unsigned int size); + +/* ISP2401 */ +void +ia_css_xnr3_vmem_encode( + struct sh_css_isp_xnr3_vmem_params *to, + const struct ia_css_xnr3_config *from, + unsigned int size); + +void +ia_css_xnr3_debug_dtrace( + const struct ia_css_xnr3_config *config, + unsigned int level); + +#endif /* __IA_CSS_XNR3_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_param.h new file mode 100644 index 000000000..c728db7ce --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_param.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_PARAM_H +#define __IA_CSS_XNR3_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* ISP2401: needed for VMEM_ARRAY */ + +/* Scaling factor of the alpha values: which fixed-point value represents 1.0? + * It must be chosen such that 1/min_sigma still fits in an ISP vector + * element. */ +#define XNR_ALPHA_SCALE_LOG2 5 +#define XNR_ALPHA_SCALE_FACTOR BIT(XNR_ALPHA_SCALE_LOG2) + +/* Scaling factor of the coring values on the ISP. */ +#define XNR_CORING_SCALE_LOG2 (ISP_VEC_ELEMBITS - 1) +#define XNR_CORING_SCALE_FACTOR BIT(XNR_CORING_SCALE_LOG2) + +/* Scaling factor of the blending strength on the ISP. */ +#define XNR_BLENDING_SCALE_LOG2 (ISP_VEC_ELEMBITS - 1) +#define XNR_BLENDING_SCALE_FACTOR BIT(XNR_BLENDING_SCALE_LOG2) + +/* XNR3 filter size. Must be 11x11, 9x9 or 5x5. */ +#define XNR_FILTER_SIZE 5 + +/* XNR3 alpha (1/sigma) parameters on the ISP, expressed as a base (0) value + * for dark areas, and a scaled diff towards the value for bright areas. */ +struct sh_css_xnr3_alpha_params { + s32 y0; + s32 u0; + s32 v0; + s32 ydiff; + s32 udiff; + s32 vdiff; +}; + +/* XNR3 coring parameters on the ISP, expressed as a base (0) value + * for dark areas, and a scaled diff towards the value for bright areas. */ +struct sh_css_xnr3_coring_params { + s32 u0; + s32 v0; + s32 udiff; + s32 vdiff; +}; + +/* XNR3 blending strength on the ISP. */ +struct sh_css_xnr3_blending_params { + s32 strength; +}; + +/* XNR3 ISP parameters */ +struct sh_css_isp_xnr3_params { + struct sh_css_xnr3_alpha_params alpha; + struct sh_css_xnr3_coring_params coring; + struct sh_css_xnr3_blending_params blending; +}; + +/* ISP2401 */ +/* + * STRUCT sh_css_isp_xnr3_vmem_params + * ----------------------------------------------- + * ISP VMEM parameters + */ +struct sh_css_isp_xnr3_vmem_params { + VMEM_ARRAY(x, ISP_VEC_NELEMS); + VMEM_ARRAY(a, ISP_VEC_NELEMS); + VMEM_ARRAY(b, ISP_VEC_NELEMS); + VMEM_ARRAY(c, ISP_VEC_NELEMS); +}; + +#endif /*__IA_CSS_XNR3_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h new file mode 100644 index 000000000..4447ba31a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_TYPES_H +#define __IA_CSS_XNR3_TYPES_H + +/* @file +* CSS-API header file for Extra Noise Reduction (XNR) parameters. +*/ + +/** + * \brief Scale of the XNR sigma parameters. + * \details The define specifies which fixed-point value represents 1.0. + */ +#define IA_CSS_XNR3_SIGMA_SCALE BIT(10) + +/** + * \brief Scale of the XNR coring parameters. + * \details The define specifies which fixed-point value represents 1.0. + */ +#define IA_CSS_XNR3_CORING_SCALE BIT(15) + +/** + * \brief Scale of the XNR blending parameter. + * \details The define specifies which fixed-point value represents 1.0. + */ +#define IA_CSS_XNR3_BLENDING_SCALE BIT(11) + +/** + * \brief XNR3 Sigma Parameters. + * \details Sigma parameters define the strength of the XNR filter. + * A higher number means stronger filtering. There are two values for each of + * the three YUV planes: one for dark areas and one for bright areas. All + * sigma parameters are fixed-point values between 0.0 and 1.0, scaled with + * IA_CSS_XNR3_SIGMA_SCALE. + */ +struct ia_css_xnr3_sigma_params { + int y0; /** Sigma for Y range similarity in dark area */ + int y1; /** Sigma for Y range similarity in bright area */ + int u0; /** Sigma for U range similarity in dark area */ + int u1; /** Sigma for U range similarity in bright area */ + int v0; /** Sigma for V range similarity in dark area */ + int v1; /** Sigma for V range similarity in bright area */ +}; + +/** + * \brief XNR3 Coring Parameters + * \details Coring parameters define the "coring" strength, which is a soft + * thresholding technique to avoid false coloring. There are two values for + * each of the two chroma planes: one for dark areas and one for bright areas. + * All coring parameters are fixed-point values between 0.0 and 1.0, scaled + * with IA_CSS_XNR3_CORING_SCALE. The ineffective value is 0. + */ +struct ia_css_xnr3_coring_params { + int u0; /** Coring threshold of U channel in dark area */ + int u1; /** Coring threshold of U channel in bright area */ + int v0; /** Coring threshold of V channel in dark area */ + int v1; /** Coring threshold of V channel in bright area */ +}; + +/** + * \brief XNR3 Blending Parameters + * \details Blending parameters define the blending strength of filtered + * output pixels with the original chroma pixels from before xnr3. The + * blending strength is a fixed-point value between 0.0 and 1.0 (inclusive), + * scaled with IA_CSS_XNR3_BLENDING_SCALE. + * A higher number applies xnr filtering more strongly. A value of 1.0 + * disables the blending and returns the xnr3 filtered output, while a + * value of 0.0 bypasses the entire xnr3 filter. + */ +struct ia_css_xnr3_blending_params { + int strength; /** Blending strength */ +}; + +/** + * \brief XNR3 public parameters. + * \details Struct with all parameters for the XNR3 kernel that can be set + * from the CSS API. + */ +struct ia_css_xnr3_config { + struct ia_css_xnr3_sigma_params sigma; /** XNR3 sigma parameters */ + struct ia_css_xnr3_coring_params coring; /** XNR3 coring parameters */ + struct ia_css_xnr3_blending_params blending; /** XNR3 blending parameters */ +}; + +#endif /* __IA_CSS_XNR3_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.c new file mode 100644 index 000000000..048ffbc90 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "bnr/bnr_1.0/ia_css_bnr.host.h" +#include "ia_css_ynr.host.h" + +const struct ia_css_nr_config default_nr_config = { + 16384, + 8192, + 1280, + 0, + 0 +}; + +const struct ia_css_ee_config default_ee_config = { + 8192, + 128, + 2048 +}; + +void +ia_css_nr_encode( + struct sh_css_isp_ynr_params *to, + const struct ia_css_nr_config *from, + unsigned int size) +{ + (void)size; + /* YNR (Y Noise Reduction) */ + to->threshold = + uDIGIT_FITTING(8192U, 16, SH_CSS_BAYER_BITS); + to->gain_all = + uDIGIT_FITTING(from->ynr_gain, 16, SH_CSS_YNR_GAIN_SHIFT); + to->gain_dir = + uDIGIT_FITTING(from->ynr_gain, 16, SH_CSS_YNR_GAIN_SHIFT); + to->threshold_cb = + uDIGIT_FITTING(from->threshold_cb, 16, SH_CSS_BAYER_BITS); + to->threshold_cr = + uDIGIT_FITTING(from->threshold_cr, 16, SH_CSS_BAYER_BITS); +} + +void +ia_css_yee_encode( + struct sh_css_isp_yee_params *to, + const struct ia_css_yee_config *from, + unsigned int size) +{ + int asiWk1 = (int)from->ee.gain; + int asiWk2 = asiWk1 / 8; + int asiWk3 = asiWk1 / 4; + + (void)size; + /* YEE (Y Edge Enhancement) */ + to->dirthreshold_s = + min((uDIGIT_FITTING(from->nr.direction, 16, SH_CSS_BAYER_BITS) + << 1), + SH_CSS_BAYER_MAXVAL); + to->dirthreshold_g = + min((uDIGIT_FITTING(from->nr.direction, 16, SH_CSS_BAYER_BITS) + << 4), + SH_CSS_BAYER_MAXVAL); + to->dirthreshold_width_log2 = + uFRACTION_BITS_FITTING(8); + to->dirthreshold_width = + 1 << to->dirthreshold_width_log2; + to->detailgain = + uDIGIT_FITTING(from->ee.detail_gain, 11, + SH_CSS_YEE_DETAIL_GAIN_SHIFT); + to->coring_s = + (uDIGIT_FITTING(56U, 16, SH_CSS_BAYER_BITS) * + from->ee.threshold) >> 8; + to->coring_g = + (uDIGIT_FITTING(224U, 16, SH_CSS_BAYER_BITS) * + from->ee.threshold) >> 8; + /* 8; // *1.125 ->[s4.8] */ + to->scale_plus_s = + (asiWk1 + asiWk2) >> (11 - SH_CSS_YEE_SCALE_SHIFT); + /* 8; // ( * -.25)->[s4.8] */ + to->scale_plus_g = + (0 - asiWk3) >> (11 - SH_CSS_YEE_SCALE_SHIFT); + /* 8; // *0.875 ->[s4.8] */ + to->scale_minus_s = + (asiWk1 - asiWk2) >> (11 - SH_CSS_YEE_SCALE_SHIFT); + /* 8; // ( *.25 ) ->[s4.8] */ + to->scale_minus_g = + (asiWk3) >> (11 - SH_CSS_YEE_SCALE_SHIFT); + to->clip_plus_s = + uDIGIT_FITTING(32760U, 16, SH_CSS_BAYER_BITS); + to->clip_plus_g = 0; + to->clip_minus_s = + uDIGIT_FITTING(504U, 16, SH_CSS_BAYER_BITS); + to->clip_minus_g = + uDIGIT_FITTING(32256U, 16, SH_CSS_BAYER_BITS); + to->Yclip = SH_CSS_BAYER_MAXVAL; +} + +void +ia_css_nr_dump( + const struct sh_css_isp_ynr_params *ynr, + unsigned int level) +{ + if (!ynr) return; + ia_css_debug_dtrace(level, + "Y Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_threshold", ynr->threshold); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_gain_all", ynr->gain_all); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_gain_dir", ynr->gain_dir); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_threshold_cb", ynr->threshold_cb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_threshold_cr", ynr->threshold_cr); +} + +void +ia_css_yee_dump( + const struct sh_css_isp_yee_params *yee, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "Y Edge Enhancement:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_dirthreshold_s", + yee->dirthreshold_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_dirthreshold_g", + yee->dirthreshold_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_dirthreshold_width_log2", + yee->dirthreshold_width_log2); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_dirthreshold_width", + yee->dirthreshold_width); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_detailgain", + yee->detailgain); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_coring_s", + yee->coring_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_coring_g", + yee->coring_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_scale_plus_s", + yee->scale_plus_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_scale_plus_g", + yee->scale_plus_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_scale_minus_s", + yee->scale_minus_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_scale_minus_g", + yee->scale_minus_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_clip_plus_s", + yee->clip_plus_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_clip_plus_g", + yee->clip_plus_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_clip_minus_s", + yee->clip_minus_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_clip_minus_g", + yee->clip_minus_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_Yclip", + yee->Yclip); +} + +void +ia_css_nr_debug_dtrace( + const struct ia_css_nr_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.direction=%d, config.bnr_gain=%d, config.ynr_gain=%d, config.threshold_cb=%d, config.threshold_cr=%d\n", + config->direction, + config->bnr_gain, config->ynr_gain, + config->threshold_cb, config->threshold_cr); +} + +void +ia_css_ee_debug_dtrace( + const struct ia_css_ee_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.threshold=%d, config.gain=%d, config.detail_gain=%d\n", + config->threshold, config->gain, config->detail_gain); +} + +void +ia_css_init_ynr_state( + void/*struct sh_css_isp_ynr_vmem_state*/ * state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h new file mode 100644 index 000000000..049706e1f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR_HOST_H +#define __IA_CSS_YNR_HOST_H + +#include "ia_css_ynr_types.h" +#include "ia_css_ynr_param.h" + +extern const struct ia_css_nr_config default_nr_config; +extern const struct ia_css_ee_config default_ee_config; + +void +ia_css_nr_encode( + struct sh_css_isp_ynr_params *to, + const struct ia_css_nr_config *from, + unsigned int size); + +void +ia_css_yee_encode( + struct sh_css_isp_yee_params *to, + const struct ia_css_yee_config *from, + unsigned int size); + +void +ia_css_nr_dump( + const struct sh_css_isp_ynr_params *ynr, + unsigned int level); + +void +ia_css_yee_dump( + const struct sh_css_isp_yee_params *yee, + unsigned int level); + +void +ia_css_nr_debug_dtrace( + const struct ia_css_nr_config *config, + unsigned int level); + +void +ia_css_ee_debug_dtrace( + const struct ia_css_ee_config *config, + unsigned int level); + +void +ia_css_init_ynr_state( + void/*struct sh_css_isp_ynr_vmem_state*/ * state, + size_t size); +#endif /* __IA_CSS_YNR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr_param.h new file mode 100644 index 000000000..8d9069ec2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr_param.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR_PARAM_H +#define __IA_CSS_YNR_PARAM_H + +#include "type_support.h" + +/* YNR (Y Noise Reduction) */ +struct sh_css_isp_ynr_params { + s32 threshold; + s32 gain_all; + s32 gain_dir; + s32 threshold_cb; + s32 threshold_cr; +}; + +/* YEE (Y Edge Enhancement) */ +struct sh_css_isp_yee_params { + s32 dirthreshold_s; + s32 dirthreshold_g; + s32 dirthreshold_width_log2; + s32 dirthreshold_width; + s32 detailgain; + s32 coring_s; + s32 coring_g; + s32 scale_plus_s; + s32 scale_plus_g; + s32 scale_minus_s; + s32 scale_minus_g; + s32 clip_plus_s; + s32 clip_plus_g; + s32 clip_minus_s; + s32 clip_minus_g; + s32 Yclip; +}; + +#endif /* __IA_CSS_YNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr_types.h new file mode 100644 index 000000000..da1ba21a0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/ia_css_ynr_types.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR_TYPES_H +#define __IA_CSS_YNR_TYPES_H + +/* @file +* CSS-API header file for Noise Reduction (BNR) and YCC Noise Reduction (YNR,CNR). +*/ + +/* Configuration used by Bayer Noise Reduction (BNR) and + * YCC Noise Reduction (YNR,CNR). + * + * ISP block: BNR1, YNR1, CNR1 + * ISP1: BNR1,YNR1,CNR1 are used. + * ISP2: BNR1,YNR1,CNR1 are used for Preview/Video. + * BNR1,YNR2,CNR2 are used for Still. + */ +struct ia_css_nr_config { + ia_css_u0_16 bnr_gain; /** Strength of noise reduction (BNR). + u0.16, [0,65535], + default 14336(0.21875), ineffective 0 */ + ia_css_u0_16 ynr_gain; /** Strength of noise reduction (YNR). + u0.16, [0,65535], + default 14336(0.21875), ineffective 0 */ + ia_css_u0_16 direction; /** Sensitivity of edge (BNR). + u0.16, [0,65535], + default 512(0.0078125), ineffective 0 */ + ia_css_u0_16 threshold_cb; /** Coring threshold for Cb (CNR). + This is the same as + de_config.c1_coring_threshold. + u0.16, [0,65535], + default 0(0), ineffective 0 */ + ia_css_u0_16 threshold_cr; /** Coring threshold for Cr (CNR). + This is the same as + de_config.c2_coring_threshold. + u0.16, [0,65535], + default 0(0), ineffective 0 */ +}; + +/* Edge Enhancement (sharpen) configuration. + * + * ISP block: YEE1 + * ISP1: YEE1 is used. + * ISP2: YEE1 is used for Preview/Video. + * (YEE2 is used for Still.) + */ +struct ia_css_ee_config { + ia_css_u5_11 gain; /** The strength of sharpness. + u5.11, [0,65535], + default 8192(4.0), ineffective 0 */ + ia_css_u8_8 threshold; /** The threshold that divides noises from + edge. + u8.8, [0,65535], + default 256(1.0), ineffective 65535 */ + ia_css_u5_11 detail_gain; /** The strength of sharpness in pell-mell + area. + u5.11, [0,65535], + default 2048(1.0), ineffective 0 */ +}; + +/* YNR and YEE (sharpen) configuration. + */ +struct ia_css_yee_config { + struct ia_css_nr_config nr; /** The NR configuration. */ + struct ia_css_ee_config ee; /** The EE configuration. */ +}; + +#endif /* __IA_CSS_YNR_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.c b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.c new file mode 100644 index 000000000..08e9d72c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +#include "ia_css_ynr2.host.h" + +const struct ia_css_ynr_config default_ynr_config = { + 0, + 0, + 0, + 0, +}; + +const struct ia_css_fc_config default_fc_config = { + 1, + 0, /* 0 -> ineffective */ + 0, /* 0 -> ineffective */ + 0, /* 0 -> ineffective */ + 0, /* 0 -> ineffective */ + (1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */ + (1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */ + (1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */ + (1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */ + (1 << (ISP_VEC_ELEMBITS - 1)) - 1, /* 1 */ + (1 << (ISP_VEC_ELEMBITS - 1)) - 1, /* 1 */ + (int16_t)-(1 << (ISP_VEC_ELEMBITS - 1)), /* -1 */ + (int16_t)-(1 << (ISP_VEC_ELEMBITS - 1)), /* -1 */ +}; + +void +ia_css_ynr_encode( + struct sh_css_isp_yee2_params *to, + const struct ia_css_ynr_config *from, + unsigned int size) +{ + (void)size; + to->edge_sense_gain_0 = from->edge_sense_gain_0; + to->edge_sense_gain_1 = from->edge_sense_gain_1; + to->corner_sense_gain_0 = from->corner_sense_gain_0; + to->corner_sense_gain_1 = from->corner_sense_gain_1; +} + +void +ia_css_fc_encode( + struct sh_css_isp_fc_params *to, + const struct ia_css_fc_config *from, + unsigned int size) +{ + (void)size; + to->gain_exp = from->gain_exp; + + to->coring_pos_0 = from->coring_pos_0; + to->coring_pos_1 = from->coring_pos_1; + to->coring_neg_0 = from->coring_neg_0; + to->coring_neg_1 = from->coring_neg_1; + + to->gain_pos_0 = from->gain_pos_0; + to->gain_pos_1 = from->gain_pos_1; + to->gain_neg_0 = from->gain_neg_0; + to->gain_neg_1 = from->gain_neg_1; + + to->crop_pos_0 = from->crop_pos_0; + to->crop_pos_1 = from->crop_pos_1; + to->crop_neg_0 = from->crop_neg_0; + to->crop_neg_1 = from->crop_neg_1; +} + +void +ia_css_ynr_dump( + const struct sh_css_isp_yee2_params *yee2, + unsigned int level); + +void +ia_css_fc_dump( + const struct sh_css_isp_fc_params *fc, + unsigned int level); + +void +ia_css_fc_debug_dtrace( + const struct ia_css_fc_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.gain_exp=%d, config.coring_pos_0=%d, config.coring_pos_1=%d, config.coring_neg_0=%d, config.coring_neg_1=%d, config.gain_pos_0=%d, config.gain_pos_1=%d, config.gain_neg_0=%d, config.gain_neg_1=%d, config.crop_pos_0=%d, config.crop_pos_1=%d, config.crop_neg_0=%d, config.crop_neg_1=%d\n", + config->gain_exp, + config->coring_pos_0, config->coring_pos_1, + config->coring_neg_0, config->coring_neg_1, + config->gain_pos_0, config->gain_pos_1, + config->gain_neg_0, config->gain_neg_1, + config->crop_pos_0, config->crop_pos_1, + config->crop_neg_0, config->crop_neg_1); +} + +void +ia_css_ynr_debug_dtrace( + const struct ia_css_ynr_config *config, + unsigned int level) +{ + ia_css_debug_dtrace(level, + "config.edge_sense_gain_0=%d, config.edge_sense_gain_1=%d, config.corner_sense_gain_0=%d, config.corner_sense_gain_1=%d\n", + config->edge_sense_gain_0, config->edge_sense_gain_1, + config->corner_sense_gain_0, config->corner_sense_gain_1); +} diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h new file mode 100644 index 000000000..eaf253d59 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR2_HOST_H +#define __IA_CSS_YNR2_HOST_H + +#include "ia_css_ynr2_types.h" +#include "ia_css_ynr2_param.h" + +extern const struct ia_css_ynr_config default_ynr_config; +extern const struct ia_css_fc_config default_fc_config; + +void +ia_css_ynr_encode( + struct sh_css_isp_yee2_params *to, + const struct ia_css_ynr_config *from, + unsigned int size); + +void +ia_css_fc_encode( + struct sh_css_isp_fc_params *to, + const struct ia_css_fc_config *from, + unsigned int size); + +void +ia_css_ynr_dump( + const struct sh_css_isp_yee2_params *yee2, + unsigned int level); + +void +ia_css_fc_dump( + const struct sh_css_isp_fc_params *fc, + unsigned int level); + +void +ia_css_fc_debug_dtrace( + const struct ia_css_fc_config *config, + unsigned int level); + +void +ia_css_ynr_debug_dtrace( + const struct ia_css_ynr_config *config, + unsigned int level); + +#endif /* __IA_CSS_YNR2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2_param.h b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2_param.h new file mode 100644 index 000000000..96c80b3af --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2_param.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR2_PARAM_H +#define __IA_CSS_YNR2_PARAM_H + +#include "type_support.h" + +/* YNR (Y Noise Reduction), YEE (Y Edge Enhancement) */ +struct sh_css_isp_yee2_params { + s32 edge_sense_gain_0; + s32 edge_sense_gain_1; + s32 corner_sense_gain_0; + s32 corner_sense_gain_1; +}; + +/* Fringe Control */ +struct sh_css_isp_fc_params { + s32 gain_exp; + u16 coring_pos_0; + u16 coring_pos_1; + u16 coring_neg_0; + u16 coring_neg_1; + s32 gain_pos_0; + s32 gain_pos_1; + s32 gain_neg_0; + s32 gain_neg_1; + s32 crop_pos_0; + s32 crop_pos_1; + s32 crop_neg_0; + s32 crop_neg_1; +}; + +#endif /* __IA_CSS_YNR2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h new file mode 100644 index 000000000..ab77f4e85 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR2_TYPES_H +#define __IA_CSS_YNR2_TYPES_H + +/* @file +* CSS-API header file for Y(Luma) Noise Reduction. +*/ + +/* Y(Luma) Noise Reduction configuration. + * + * ISP block: YNR2 & YEE2 + * (ISP1: YNR1 and YEE1 are used.) + * (ISP2: YNR1 and YEE1 are used for Preview/Video.) + * ISP2: YNR2 and YEE2 are used for Still. + */ +struct ia_css_ynr_config { + u16 edge_sense_gain_0; /** Sensitivity of edge in dark area. + u13.0, [0,8191], + default 1000, ineffective 0 */ + u16 edge_sense_gain_1; /** Sensitivity of edge in bright area. + u13.0, [0,8191], + default 1000, ineffective 0 */ + u16 corner_sense_gain_0; /** Sensitivity of corner in dark area. + u13.0, [0,8191], + default 1000, ineffective 0 */ + u16 corner_sense_gain_1; /** Sensitivity of corner in bright area. + u13.0, [0,8191], + default 1000, ineffective 0 */ +}; + +/* Fringe Control configuration. + * + * ISP block: FC2 (FC2 is used with YNR2/YEE2.) + * (ISP1: FC2 is not used.) + * (ISP2: FC2 is not for Preview/Video.) + * ISP2: FC2 is used for Still. + */ +struct ia_css_fc_config { + u8 gain_exp; /** Common exponent of gains. + u8.0, [0,13], + default 1, ineffective 0 */ + u16 coring_pos_0; /** Coring threshold for positive edge in dark area. + u0.13, [0,8191], + default 0(0), ineffective 0 */ + u16 coring_pos_1; /** Coring threshold for positive edge in bright area. + u0.13, [0,8191], + default 0(0), ineffective 0 */ + u16 coring_neg_0; /** Coring threshold for negative edge in dark area. + u0.13, [0,8191], + default 0(0), ineffective 0 */ + u16 coring_neg_1; /** Coring threshold for negative edge in bright area. + u0.13, [0,8191], + default 0(0), ineffective 0 */ + u16 gain_pos_0; /** Gain for positive edge in dark area. + u0.13, [0,8191], + default 4096(0.5), ineffective 0 */ + u16 gain_pos_1; /** Gain for positive edge in bright area. + u0.13, [0,8191], + default 4096(0.5), ineffective 0 */ + u16 gain_neg_0; /** Gain for negative edge in dark area. + u0.13, [0,8191], + default 4096(0.5), ineffective 0 */ + u16 gain_neg_1; /** Gain for negative edge in bright area. + u0.13, [0,8191], + default 4096(0.5), ineffective 0 */ + u16 crop_pos_0; /** Limit for positive edge in dark area. + u0.13, [0,8191], + default/ineffective 8191(almost 1.0) */ + u16 crop_pos_1; /** Limit for positive edge in bright area. + u0.13, [0,8191], + default/ineffective 8191(almost 1.0) */ + s16 crop_neg_0; /** Limit for negative edge in dark area. + s0.13, [-8192,0], + default/ineffective -8192(-1.0) */ + s16 crop_neg_1; /** Limit for negative edge in bright area. + s0.13, [-8192,0], + default/ineffective -8192(-1.0) */ +}; + +#endif /* __IA_CSS_YNR2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/isp/modes/interface/input_buf.isp.h b/drivers/staging/media/atomisp/pci/isp/modes/interface/input_buf.isp.h new file mode 100644 index 000000000..f86cf9bf1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/modes/interface/input_buf.isp.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef _INPUT_BUF_ISP_H_ +#define _INPUT_BUF_ISP_H_ + +/* Temporary include, since IA_CSS_BINARY_MODE_COPY is still needed */ +#include "sh_css_defs.h" +#include "isp_const.h" /* MAX_VECTORS_PER_INPUT_LINE */ + +#define INPUT_BUF_HEIGHT 2 /* double buffer */ +#define INPUT_BUF_LINES 2 + +#ifndef ENABLE_CONTINUOUS +#define ENABLE_CONTINUOUS 0 +#endif + +/* In continuous mode, the input buffer must be a fixed size for all binaries + * and at a fixed address since it will be used by the SP. */ +#define EXTRA_INPUT_VECTORS 2 /* For left padding */ +#define MAX_VECTORS_PER_INPUT_LINE_CONT (CEIL_DIV(SH_CSS_MAX_SENSOR_WIDTH, ISP_NWAY) + EXTRA_INPUT_VECTORS) + +/* The input buffer should be on a fixed address in vmem, for continuous capture */ +#define INPUT_BUF_ADDR 0x0 + +#endif /* _INPUT_BUF_ISP_H_ */ diff --git a/drivers/staging/media/atomisp/pci/isp/modes/interface/isp_const.h b/drivers/staging/media/atomisp/pci/isp/modes/interface/isp_const.h new file mode 100644 index 000000000..73432dc35 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/modes/interface/isp_const.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef _COMMON_ISP_CONST_H_ +#define _COMMON_ISP_CONST_H_ + +/*#include "isp.h"*/ /* ISP_VEC_NELEMS */ + +/* Binary independent constants */ + +#ifndef NO_HOIST +# define NO_HOIST HIVE_ATTRIBUTE((no_hoist)) +#endif + +#define NO_HOIST_CSE HIVE_ATTRIBUTE((no_hoist, no_cse)) + +#define UNION struct /* Union constructors not allowed in C++ */ + +#define XMEM_WIDTH_BITS HIVE_ISP_DDR_WORD_BITS +#define XMEM_SHORTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 16) +#define XMEM_INTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 32) +#define XMEM_POW2_BYTES_PER_WORD HIVE_ISP_DDR_WORD_BYTES + +#define BITS8_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 8) +#define BITS16_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 16) + +#define ISP_NWAY_LOG2 6 + +/* ***************************** + * ISP input/output buffer sizes + * ****************************/ +/* input image */ +#define INPUT_BUF_DMA_HEIGHT 2 +#define INPUT_BUF_HEIGHT 2 /* double buffer */ +#define OUTPUT_BUF_DMA_HEIGHT 2 +#define OUTPUT_BUF_HEIGHT 2 /* double buffer */ +#define OUTPUT_NUM_TRANSFERS 4 + +/* GDC accelerator: Up/Down Scaling */ +/* These should be moved to the gdc_defs.h in the device */ +#define UDS_SCALING_N HRT_GDC_N +/* AB: This should cover the zooming up to 16MP */ +#define UDS_MAX_OXDIM 5000 +/* We support maximally 2 planes with different parameters + - luma and chroma (YUV420) */ +#define UDS_MAX_PLANES 2 +#define UDS_BLI_BLOCK_HEIGHT 2 +#define UDS_BCI_BLOCK_HEIGHT 4 +#define UDS_BLI_INTERP_ENVELOPE 1 +#define UDS_BCI_INTERP_ENVELOPE 3 +#define UDS_MAX_ZOOM_FAC 64 +/* Make it always one FPGA vector. + Four FPGA vectors are required and + four of them fit in one ASIC vector.*/ +#define UDS_MAX_CHUNKS 16 + +#define ISP_LEFT_PADDING _ISP_LEFT_CROP_EXTRA(ISP_LEFT_CROPPING) +#define ISP_LEFT_PADDING_VECS CEIL_DIV(ISP_LEFT_PADDING, ISP_VEC_NELEMS) +/* in case of continuous the croppong of the current binary doesn't matter for the buffer calculation, but the cropping of the sp copy should be used */ +#define ISP_LEFT_PADDING_CONT _ISP_LEFT_CROP_EXTRA(SH_CSS_MAX_LEFT_CROPPING) +#define ISP_LEFT_PADDING_VECS_CONT CEIL_DIV(ISP_LEFT_PADDING_CONT, ISP_VEC_NELEMS) + +#define CEIL_ROUND_DIV_STRIPE(width, stripe, padding) \ + CEIL_MUL(padding + CEIL_DIV(width - padding, stripe), ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2)) + +/* output (Y,U,V) image, 4:2:0 */ +#define MAX_VECTORS_PER_LINE \ + CEIL_ROUND_DIV_STRIPE(CEIL_DIV(ISP_MAX_INTERNAL_WIDTH, ISP_VEC_NELEMS), \ + ISP_NUM_STRIPES, \ + ISP_LEFT_PADDING_VECS) + +/* + * ITERATOR_VECTOR_INCREMENT' explanation: + * when striping an even number of iterations, one of the stripes is + * one iteration wider than the other to account for overlap + * so the calc for the output buffer vmem size is: + * ((width[vectors]/num_of_stripes) + 2[vectors]) + */ +#define MAX_VECTORS_PER_OUTPUT_LINE \ + CEIL_DIV(CEIL_DIV(ISP_MAX_OUTPUT_WIDTH, ISP_NUM_STRIPES) + ISP_LEFT_PADDING, ISP_VEC_NELEMS) + +/* Must be even due to interlaced bayer input */ +#define MAX_VECTORS_PER_INPUT_LINE CEIL_MUL((CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + ISP_LEFT_PADDING_VECS), 2) +#define MAX_VECTORS_PER_INPUT_STRIPE CEIL_ROUND_DIV_STRIPE(MAX_VECTORS_PER_INPUT_LINE, \ + ISP_NUM_STRIPES, \ + ISP_LEFT_PADDING_VECS) + +/* Add 2 for left croppping */ +#define MAX_SP_RAW_COPY_VECTORS_PER_INPUT_LINE (CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + 2) + +#define MAX_VECTORS_PER_BUF_LINE \ + (MAX_VECTORS_PER_LINE + DUMMY_BUF_VECTORS) +#define MAX_VECTORS_PER_BUF_INPUT_LINE \ + (MAX_VECTORS_PER_INPUT_STRIPE + DUMMY_BUF_VECTORS) +#define MAX_OUTPUT_Y_FRAME_WIDTH \ + (MAX_VECTORS_PER_LINE * ISP_VEC_NELEMS) +#define MAX_OUTPUT_Y_FRAME_SIMDWIDTH \ + MAX_VECTORS_PER_LINE +#define MAX_OUTPUT_C_FRAME_WIDTH \ + (MAX_OUTPUT_Y_FRAME_WIDTH / 2) +#define MAX_OUTPUT_C_FRAME_SIMDWIDTH \ + CEIL_DIV(MAX_OUTPUT_C_FRAME_WIDTH, ISP_VEC_NELEMS) + +/* should be even */ +#define NO_CHUNKING (OUTPUT_NUM_CHUNKS == 1) + +#define MAX_VECTORS_PER_CHUNK \ + (NO_CHUNKING ? MAX_VECTORS_PER_LINE \ + : 2 * CEIL_DIV(MAX_VECTORS_PER_LINE, \ + 2 * OUTPUT_NUM_CHUNKS)) + +#define MAX_C_VECTORS_PER_CHUNK \ + (MAX_VECTORS_PER_CHUNK / 2) + +/* should be even */ +#define MAX_VECTORS_PER_OUTPUT_CHUNK \ + (NO_CHUNKING ? MAX_VECTORS_PER_OUTPUT_LINE \ + : 2 * CEIL_DIV(MAX_VECTORS_PER_OUTPUT_LINE, \ + 2 * OUTPUT_NUM_CHUNKS)) + +#define MAX_C_VECTORS_PER_OUTPUT_CHUNK \ + (MAX_VECTORS_PER_OUTPUT_CHUNK / 2) + +/* should be even */ +#define MAX_VECTORS_PER_INPUT_CHUNK \ + (INPUT_NUM_CHUNKS == 1 ? MAX_VECTORS_PER_INPUT_STRIPE \ + : 2 * CEIL_DIV(MAX_VECTORS_PER_INPUT_STRIPE, \ + 2 * OUTPUT_NUM_CHUNKS)) + +#define DEFAULT_C_SUBSAMPLING 2 + +/****** DMA buffer properties */ + +#define RAW_BUF_LINES ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2) + +/* [isp vmem] table size[vectors] per line per color (GR,R,B,GB), + multiples of NWAY */ +#define ISP2400_SCTBL_VECTORS_PER_LINE_PER_COLOR \ + CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) +#define ISP2401_SCTBL_VECTORS_PER_LINE_PER_COLOR \ + CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) +/* [isp vmem] table size[vectors] per line for 4colors (GR,R,B,GB), + multiples of NWAY */ +#define SCTBL_VECTORS_PER_LINE \ + (SCTBL_VECTORS_PER_LINE_PER_COLOR * IA_CSS_SC_NUM_COLORS) + +/*************/ + +/* Format for fixed primaries */ + +#define ISP_FIXED_PRIMARY_FORMAT IA_CSS_FRAME_FORMAT_NV12 + +#endif /* _COMMON_ISP_CONST_H_ */ diff --git a/drivers/staging/media/atomisp/pci/isp/modes/interface/isp_types.h b/drivers/staging/media/atomisp/pci/isp/modes/interface/isp_types.h new file mode 100644 index 000000000..d1c42c77f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp/modes/interface/isp_types.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ISP_TYPES_H_ +#define _ISP_TYPES_H_ + +/* + * Workaround: hivecc complains about "tag "sh_css_3a_output" already declared" + * without this extra decl. + */ +struct ia_css_3a_output; + +/* + * Input stream formats, these correspond to the MIPI formats and the way + * the CSS receiver sends these to the input formatter. + * The bit depth of each pixel element is stored in the global variable + * isp_bits_per_pixel. + * NOTE: for rgb565, we set isp_bits_per_pixel to 565, for all other rgb + * formats it's the actual depth (4, for 444, 8 for 888 etc). + */ +enum sh_stream_format { + sh_stream_format_yuv420_legacy, + sh_stream_format_yuv420, + sh_stream_format_yuv422, + sh_stream_format_rgb, + sh_stream_format_raw, + sh_stream_format_binary, /* bytestream such as jpeg */ +}; + +struct s_isp_frames { + /* + * Global variables that are written to by either the SP or the host, + * every ISP binary needs these. + */ + /* output frame */ + char *xmem_base_addr_y; + char *xmem_base_addr_uv; + char *xmem_base_addr_u; + char *xmem_base_addr_v; + /* 2nd output frame */ + char *xmem_base_addr_second_out_y; + char *xmem_base_addr_second_out_u; + char *xmem_base_addr_second_out_v; + /* input yuv frame */ + char *xmem_base_addr_y_in; + char *xmem_base_addr_u_in; + char *xmem_base_addr_v_in; + /* input raw frame */ + char *xmem_base_addr_raw; + /* output raw frame */ + char *xmem_base_addr_raw_out; + /* viewfinder output (vf_veceven) */ + char *xmem_base_addr_vfout_y; + char *xmem_base_addr_vfout_u; + char *xmem_base_addr_vfout_v; + /* overlay frame (for vf_pp) */ + char *xmem_base_addr_overlay_y; + char *xmem_base_addr_overlay_u; + char *xmem_base_addr_overlay_v; + /* pre-gdc output frame (gdc input) */ + char *xmem_base_addr_qplane_r; + char *xmem_base_addr_qplane_ratb; + char *xmem_base_addr_qplane_gr; + char *xmem_base_addr_qplane_gb; + char *xmem_base_addr_qplane_b; + char *xmem_base_addr_qplane_batr; + /* YUV as input, used by postisp binary */ + char *xmem_base_addr_yuv_16_y; + char *xmem_base_addr_yuv_16_u; + char *xmem_base_addr_yuv_16_v; +}; + +#endif /* _ISP_TYPES_H_ */ diff --git a/drivers/staging/media/atomisp/pci/isp2400_input_system_global.h b/drivers/staging/media/atomisp/pci/isp2400_input_system_global.h new file mode 100644 index 000000000..61f23814e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp2400_input_system_global.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +//CSI reveiver has 3 ports. +#define N_CSI_PORTS (3) +//AM: Use previous define for this. + +//MIPI allows upto 4 channels. +#define N_CHANNELS (4) +// 12KB = 256bit x 384 words +#define IB_CAPACITY_IN_WORDS (384) + +typedef enum { + MIPI_0LANE_CFG = 0, + MIPI_1LANE_CFG = 1, + MIPI_2LANE_CFG = 2, + MIPI_3LANE_CFG = 3, + MIPI_4LANE_CFG = 4 +} mipi_lane_cfg_t; + +typedef enum { + INPUT_SYSTEM_SOURCE_SENSOR = 0, + INPUT_SYSTEM_SOURCE_FIFO, + INPUT_SYSTEM_SOURCE_TPG, + INPUT_SYSTEM_SOURCE_PRBS, + INPUT_SYSTEM_SOURCE_MEMORY, + N_INPUT_SYSTEM_SOURCE +} input_system_source_t; + +/* internal routing configuration */ +typedef enum { + INPUT_SYSTEM_DISCARD_ALL = 0, + INPUT_SYSTEM_CSI_BACKEND = 1, + INPUT_SYSTEM_INPUT_BUFFER = 2, + INPUT_SYSTEM_MULTICAST = 3, + N_INPUT_SYSTEM_CONNECTION +} input_system_connection_t; + +typedef enum { + INPUT_SYSTEM_MIPI_PORT0, + INPUT_SYSTEM_MIPI_PORT1, + INPUT_SYSTEM_MIPI_PORT2, + INPUT_SYSTEM_ACQUISITION_UNIT, + N_INPUT_SYSTEM_MULTIPLEX +} input_system_multiplex_t; + +typedef enum { + INPUT_SYSTEM_SINK_MEMORY = 0, + INPUT_SYSTEM_SINK_ISP, + INPUT_SYSTEM_SINK_SP, + N_INPUT_SYSTEM_SINK +} input_system_sink_t; + +typedef enum { + INPUT_SYSTEM_FIFO_CAPTURE = 0, + INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING, + INPUT_SYSTEM_SRAM_BUFFERING, + INPUT_SYSTEM_XMEM_BUFFERING, + INPUT_SYSTEM_XMEM_CAPTURE, + INPUT_SYSTEM_XMEM_ACQUIRE, + N_INPUT_SYSTEM_BUFFERING_MODE +} buffering_mode_t; + +typedef struct isp2400_input_system_cfg_s input_system_cfg_t; +typedef struct sync_generator_cfg_s sync_generator_cfg_t; +typedef struct tpg_cfg_s tpg_cfg_t; +typedef struct prbs_cfg_s prbs_cfg_t; + +/* MW: uint16_t should be sufficient */ +struct isp2400_input_system_cfg_s { + u32 no_side_band; + u32 fmt_type; + u32 ch_id; + u32 input_mode; +}; + +struct sync_generator_cfg_s { + u32 width; + u32 height; + u32 hblank_cycles; + u32 vblank_cycles; +}; + +/* MW: tpg & prbs are exclusive */ +struct tpg_cfg_s { + u32 x_mask; + u32 y_mask; + u32 x_delta; + u32 y_delta; + u32 xy_mask; + sync_generator_cfg_t sync_gen_cfg; +}; + +struct prbs_cfg_s { + u32 seed; + sync_generator_cfg_t sync_gen_cfg; +}; + +struct gpfifo_cfg_s { +// TBD. + sync_generator_cfg_t sync_gen_cfg; +}; + +typedef struct gpfifo_cfg_s gpfifo_cfg_t; + +//ALX:Commented out to pass the compilation. +//typedef struct isp2400_input_system_cfg_s input_system_cfg_t; + +struct ib_buffer_s { + u32 mem_reg_size; + u32 nof_mem_regs; + u32 mem_reg_addr; +}; + +typedef struct ib_buffer_s isp2400_ib_buffer_t; + +struct csi_cfg_s { + u32 csi_port; + buffering_mode_t buffering_mode; + isp2400_ib_buffer_t csi_buffer; + isp2400_ib_buffer_t acquisition_buffer; + u32 nof_xmem_buffers; +}; + +typedef struct csi_cfg_s csi_cfg_t; + +typedef enum { + INPUT_SYSTEM_CFG_FLAG_RESET = 0, + INPUT_SYSTEM_CFG_FLAG_SET = 1U << 0, + INPUT_SYSTEM_CFG_FLAG_BLOCKED = 1U << 1, + INPUT_SYSTEM_CFG_FLAG_REQUIRED = 1U << 2, + INPUT_SYSTEM_CFG_FLAG_CONFLICT = 1U << 3 // To mark a conflicting configuration. +} isp2400_input_system_cfg_flag_t; + +typedef u32 input_system_config_flags_t; diff --git a/drivers/staging/media/atomisp/pci/isp2400_input_system_local.h b/drivers/staging/media/atomisp/pci/isp2400_input_system_local.h new file mode 100644 index 000000000..c3ae5014a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp2400_input_system_local.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_LOCAL_H_INCLUDED__ +#define __INPUT_SYSTEM_LOCAL_H_INCLUDED__ + +#include "input_system_defs.h" /* HIVE_ISYS_GPREG_MULTICAST_A_IDX,... */ + +/* + * _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX, + * _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX,... + */ +#include "css_receiver_2400_defs.h" + +#include "isp_capture_defs.h" + +#include "isp_acquisition_defs.h" +#include "input_system_ctrl_defs.h" + +struct target_cfg2400_s { + input_switch_cfg_channel_t input_switch_channel_cfg; + target_isp_cfg_t target_isp_cfg; + target_sp_cfg_t target_sp_cfg; + target_strm2mem_cfg_t target_strm2mem_cfg; +}; + +// Configuration of a channel. +struct channel_cfg_s { + u32 ch_id; + backend_channel_cfg_t backend_ch; + input_system_source_t source_type; + source_cfg_t source_cfg; + target_cfg2400_t target_cfg; +}; + +// Complete configuration for input system. +struct input_system_cfg2400_s { + input_system_source_t source_type; + input_system_config_flags_t source_type_flags; + //channel_cfg_t channel[N_CHANNELS]; + input_system_config_flags_t ch_flags[N_CHANNELS]; + // This is the place where the buffers' settings are collected, as given. + csi_cfg_t csi_value[N_CSI_PORTS]; + input_system_config_flags_t csi_flags[N_CSI_PORTS]; + + // Possible another struct for ib. + // This buffers set at the end, based on the all configurations. + isp2400_ib_buffer_t csi_buffer[N_CSI_PORTS]; + input_system_config_flags_t csi_buffer_flags[N_CSI_PORTS]; + isp2400_ib_buffer_t acquisition_buffer_unique; + input_system_config_flags_t acquisition_buffer_unique_flags; + u32 unallocated_ib_mem_words; // Used for check.DEFAULT = IB_CAPACITY_IN_WORDS. + //uint32_t acq_allocated_ib_mem_words; + + input_system_connection_t multicast[N_CSI_PORTS]; + input_system_multiplex_t multiplexer; + input_system_config_flags_t multiplexer_flags; + + tpg_cfg_t tpg_value; + input_system_config_flags_t tpg_flags; + prbs_cfg_t prbs_value; + input_system_config_flags_t prbs_flags; + gpfifo_cfg_t gpfifo_value; + input_system_config_flags_t gpfifo_flags; + + input_switch_cfg_t input_switch_cfg; + + target_isp_cfg_t target_isp[N_CHANNELS]; + input_system_config_flags_t target_isp_flags[N_CHANNELS]; + target_sp_cfg_t target_sp[N_CHANNELS]; + input_system_config_flags_t target_sp_flags[N_CHANNELS]; + target_strm2mem_cfg_t target_strm2mem[N_CHANNELS]; + input_system_config_flags_t target_strm2mem_flags[N_CHANNELS]; + + input_system_config_flags_t session_flags; + +}; + +/* + * For each MIPI port + */ +#define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX +#define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX +#define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX +#define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX +#define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX +/* new regs for each MIPI port w.r.t. 2300 */ +#define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX +#define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX +#define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX + +/* _HRT_CSS_RECEIVER_2400_COMP_FORMAT_REG_IDX is not defined per MIPI port but per channel */ +/* _HRT_CSS_RECEIVER_2400_COMP_PREDICT_REG_IDX is not defined per MIPI port but per channel */ +#define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX +#define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX +#define _HRT_CSS_RECEIVER_RAW18_REG_IDX _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX +#define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX +#define _HRT_CSS_RECEIVER_RAW16_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX + +/* Previously MIPI port regs, now 2x2 logical channel regs */ +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX + +/* Second backend is at offset 0x0700 w.r.t. the first port at offset 0x0100 */ +#define _HRT_CSS_BE_OFFSET 448 +#define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET) + +#define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT +#define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT +#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT +#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT +#define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT + +#define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX +#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX +#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS + +typedef struct capture_unit_state_s capture_unit_state_t; +typedef struct acquisition_unit_state_s acquisition_unit_state_t; +typedef struct ctrl_unit_state_s ctrl_unit_state_t; + +typedef enum { + MIPI_FORMAT_RGB888 = 0, + MIPI_FORMAT_RGB555, + MIPI_FORMAT_RGB444, + MIPI_FORMAT_RGB565, + MIPI_FORMAT_RGB666, + MIPI_FORMAT_RAW8, /* 5 */ + MIPI_FORMAT_RAW10, + MIPI_FORMAT_RAW6, + MIPI_FORMAT_RAW7, + MIPI_FORMAT_RAW12, + MIPI_FORMAT_RAW14, /* 10 */ + MIPI_FORMAT_YUV420_8, + MIPI_FORMAT_YUV420_10, + MIPI_FORMAT_YUV422_8, + MIPI_FORMAT_YUV422_10, + MIPI_FORMAT_CUSTOM0, /* 15 */ + MIPI_FORMAT_YUV420_8_LEGACY, + MIPI_FORMAT_EMBEDDED, + MIPI_FORMAT_CUSTOM1, + MIPI_FORMAT_CUSTOM2, + MIPI_FORMAT_CUSTOM3, /* 20 */ + MIPI_FORMAT_CUSTOM4, + MIPI_FORMAT_CUSTOM5, + MIPI_FORMAT_CUSTOM6, + MIPI_FORMAT_CUSTOM7, + MIPI_FORMAT_YUV420_8_SHIFT, /* 25 */ + MIPI_FORMAT_YUV420_10_SHIFT, + MIPI_FORMAT_RAW16, + MIPI_FORMAT_RAW18, + N_MIPI_FORMAT, +} mipi_format_t; + +#define MIPI_FORMAT_JPEG MIPI_FORMAT_CUSTOM0 +#define MIPI_FORMAT_BINARY_8 MIPI_FORMAT_CUSTOM0 +#define N_MIPI_FORMAT_CUSTOM 8 + +/* The number of stores for compressed format types */ +#define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM) + +typedef enum { + RX_IRQ_INFO_BUFFER_OVERRUN = 1UL << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT, + RX_IRQ_INFO_INIT_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT, + RX_IRQ_INFO_ENTER_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT, + RX_IRQ_INFO_EXIT_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT, + RX_IRQ_INFO_ECC_CORRECTED = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT, + RX_IRQ_INFO_ERR_SOT = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT, + RX_IRQ_INFO_ERR_SOT_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT, + RX_IRQ_INFO_ERR_CONTROL = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT, + RX_IRQ_INFO_ERR_ECC_DOUBLE = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT, + /* RX_IRQ_INFO_NO_ERR = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT, */ + RX_IRQ_INFO_ERR_CRC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT, + RX_IRQ_INFO_ERR_UNKNOWN_ID = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT, + RX_IRQ_INFO_ERR_FRAME_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT, + RX_IRQ_INFO_ERR_FRAME_DATA = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT, + RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT, + RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT, + RX_IRQ_INFO_ERR_LINE_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT, +} rx_irq_info_t; + +/* NOTE: The base has already an offset of 0x0100 */ +static const hrt_address __maybe_unused MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = { + 0x00000000UL, + 0x00000100UL, + 0x00000200UL +}; + +static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = { + 0x00001000UL, + 0x00002000UL, + 0x00003000UL, + 0x00004000UL, + 0x00005000UL, + 0x00009000UL, + 0x0000A000UL, + 0x0000B000UL, + 0x0000C000UL +}; + +struct capture_unit_state_s { + int Packet_Length; + int Received_Length; + int Received_Short_Packets; + int Received_Long_Packets; + int Last_Command; + int Next_Command; + int Last_Acknowledge; + int Next_Acknowledge; + int FSM_State_Info; + int StartMode; + int Start_Addr; + int Mem_Region_Size; + int Num_Mem_Regions; + /* int Init; write-only registers + int Start; + int Stop; */ +}; + +struct acquisition_unit_state_s { + /* int Init; write-only register */ + int Received_Short_Packets; + int Received_Long_Packets; + int Last_Command; + int Next_Command; + int Last_Acknowledge; + int Next_Acknowledge; + int FSM_State_Info; + int Int_Cntr_Info; + int Start_Addr; + int Mem_Region_Size; + int Num_Mem_Regions; +}; + +struct ctrl_unit_state_s { + int last_cmd; + int next_cmd; + int last_ack; + int next_ack; + int top_fsm_state; + int captA_fsm_state; + int captB_fsm_state; + int captC_fsm_state; + int acq_fsm_state; + int captA_start_addr; + int captB_start_addr; + int captC_start_addr; + int captA_mem_region_size; + int captB_mem_region_size; + int captC_mem_region_size; + int captA_num_mem_regions; + int captB_num_mem_regions; + int captC_num_mem_regions; + int acq_start_addr; + int acq_mem_region_size; + int acq_num_mem_regions; + /* int ctrl_init; write only register */ + int capt_reserve_one_mem_region; +}; + +struct input_system_state_s { + int str_multicastA_sel; + int str_multicastB_sel; + int str_multicastC_sel; + int str_mux_sel; + int str_mon_status; + int str_mon_irq_cond; + int str_mon_irq_en; + int isys_srst; + int isys_slv_reg_srst; + int str_deint_portA_cnt; + int str_deint_portB_cnt; + struct capture_unit_state_s capture_unit[N_CAPTURE_UNIT_ID]; + struct acquisition_unit_state_s acquisition_unit[N_ACQUISITION_UNIT_ID]; + struct ctrl_unit_state_s ctrl_unit_state[N_CTRL_UNIT_ID]; +}; + +struct mipi_port_state_s { + int device_ready; + int irq_status; + int irq_enable; + u32 timeout_count; + u16 init_count; + u16 raw16_18; + u32 sync_count; /*4 x uint8_t */ + u32 rx_count; /*4 x uint8_t */ + u8 lane_sync_count[MIPI_4LANE_CFG]; + u8 lane_rx_count[MIPI_4LANE_CFG]; +}; + +struct rx_channel_state_s { + u32 comp_scheme0; + u32 comp_scheme1; + mipi_predictor_t pred[N_MIPI_FORMAT_CUSTOM]; + mipi_compressor_t comp[N_MIPI_FORMAT_CUSTOM]; +}; + +struct receiver_state_s { + u8 fs_to_ls_delay; + u8 ls_to_data_delay; + u8 data_to_le_delay; + u8 le_to_fe_delay; + u8 fe_to_fs_delay; + u8 le_to_fs_delay; + bool is_two_ppc; + int backend_rst; + u16 raw18; + bool force_raw8; + u16 raw16; + struct mipi_port_state_s mipi_port_state[N_MIPI_PORT_ID]; + struct rx_channel_state_s rx_channel_state[N_RX_CHANNEL_ID]; + int be_gsp_acc_ovl; + int be_srst; + int be_is_two_ppc; + int be_comp_format0; + int be_comp_format1; + int be_comp_format2; + int be_comp_format3; + int be_sel; + int be_raw16_config; + int be_raw18_config; + int be_force_raw8; + int be_irq_status; + int be_irq_clear; +}; + +#endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/isp2400_input_system_private.h b/drivers/staging/media/atomisp/pci/isp2400_input_system_private.h new file mode 100644 index 000000000..9c39ca2da --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp2400_input_system_private.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ +#define __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ + +#include "input_system_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_INPUT_SYSTEM_C void input_system_reg_store( + const input_system_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof(hrt_data), + value); + return; +} + +STORAGE_CLASS_INPUT_SYSTEM_C hrt_data input_system_reg_load( + const input_system_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof( + hrt_data)); +} + +STORAGE_CLASS_INPUT_SYSTEM_C void receiver_reg_store( + const rx_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_RX_ID); + assert(RX_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(RX_BASE[ID] + reg * sizeof(hrt_data), value); + return; +} + +STORAGE_CLASS_INPUT_SYSTEM_C hrt_data receiver_reg_load( + const rx_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_RX_ID); + assert(RX_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(RX_BASE[ID] + reg * sizeof(hrt_data)); +} + +STORAGE_CLASS_INPUT_SYSTEM_C void receiver_port_reg_store( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_RX_ID); + assert(port_ID < N_MIPI_PORT_ID); + assert(RX_BASE[ID] != (hrt_address)-1); + assert(MIPI_PORT_OFFSET[port_ID] != (hrt_address)-1); + ia_css_device_store_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg * + sizeof(hrt_data), value); + return; +} + +STORAGE_CLASS_INPUT_SYSTEM_C hrt_data receiver_port_reg_load( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const hrt_address reg) +{ + assert(ID < N_RX_ID); + assert(port_ID < N_MIPI_PORT_ID); + assert(RX_BASE[ID] != (hrt_address)-1); + assert(MIPI_PORT_OFFSET[port_ID] != (hrt_address)-1); + return ia_css_device_load_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg * + sizeof(hrt_data)); +} + +STORAGE_CLASS_INPUT_SYSTEM_C void input_system_sub_system_reg_store( + const input_system_ID_t ID, + const sub_system_ID_t sub_ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(sub_ID < N_SUB_SYSTEM_ID); + assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); + assert(SUB_SYSTEM_OFFSET[sub_ID] != (hrt_address)-1); + ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + SUB_SYSTEM_OFFSET[sub_ID] + + reg * sizeof(hrt_data), value); + return; +} + +STORAGE_CLASS_INPUT_SYSTEM_C hrt_data input_system_sub_system_reg_load( + const input_system_ID_t ID, + const sub_system_ID_t sub_ID, + const hrt_address reg) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(sub_ID < N_SUB_SYSTEM_ID); + assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); + assert(SUB_SYSTEM_OFFSET[sub_ID] != (hrt_address)-1); + return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + + SUB_SYSTEM_OFFSET[sub_ID] + reg * sizeof(hrt_data)); +} + +#endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/isp2400_input_system_public.h b/drivers/staging/media/atomisp/pci/isp2400_input_system_public.h new file mode 100644 index 000000000..85cb61e34 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp2400_input_system_public.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ +#define __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ + +#include +#ifdef ISP2401 +#include "isys_public.h" +#else + +typedef struct input_system_state_s input_system_state_t; +typedef struct receiver_state_s receiver_state_t; + +/*! Read the state of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param state[out] input system state structure + + \return none, state = INPUT_SYSTEM[ID].state + */ +void input_system_get_state( + const input_system_ID_t ID, + input_system_state_t *state); + +/*! Read the state of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param state[out] receiver state structure + + \return none, state = RECEIVER[ID].state + */ +void receiver_get_state( + const rx_ID_t ID, + receiver_state_t *state); + +/*! Flag whether a MIPI format is YUV420 + + \param mipi_format[in] MIPI format + + \return mipi_format == YUV420 + */ +bool is_mipi_format_yuv420( + const mipi_format_t mipi_format); + +/*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param cfg_ID[in] Configuration identifier + \param comp[in] Compression method + \param pred[in] Predictor method + + \NOTE: the storage of compression configuration is + implementation specific. The config can be + carried either on MIPI ports or on MIPI channels + + \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred} + */ +void receiver_set_compression( + const rx_ID_t ID, + const unsigned int cfg_ID, + const mipi_compressor_t comp, + const mipi_predictor_t pred); + +/*! Enable PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param cnd[in] irq predicate + + \return None, enable(RECEIVER[ID].PORT[port_ID]) + */ +void receiver_port_enable( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const bool cnd); + +/*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + + \return enable(RECEIVER[ID].PORT[port_ID]) == true + */ +bool is_receiver_port_enabled( + const rx_ID_t ID, + const enum mipi_port_id port_ID); + +/*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param irq_info[in] irq channels + + \return None, enable(RECEIVER[ID].PORT[port_ID].irq_info) + */ +void receiver_irq_enable( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const rx_irq_info_t irq_info); + +/*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + + \return RECEIVER[ID].PORT[port_ID].irq_info + */ +rx_irq_info_t receiver_get_irq_info( + const rx_ID_t ID, + const enum mipi_port_id port_ID); + +/*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param irq_info[in] irq status + + \return None, clear(RECEIVER[ID].PORT[port_ID].irq_info) + */ +void receiver_irq_clear( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const rx_irq_info_t irq_info); + +/*! Write to a control register of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, INPUT_SYSTEM[ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_SYSTEM_H void input_system_reg_store( + const input_system_ID_t ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from a control register of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param reg[in] register index + \param value[in] The data to be written + + \return INPUT_SYSTEM[ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_reg_load( + const input_system_ID_t ID, + const hrt_address reg); + +/*! Write to a control register of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, RECEIVER[ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_SYSTEM_H void receiver_reg_store( + const rx_ID_t ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from a control register of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param reg[in] register index + \param value[in] The data to be written + + \return RECEIVER[ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_reg_load( + const rx_ID_t ID, + const hrt_address reg); + +/*! Write to a control register of PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_SYSTEM_H void receiver_port_reg_store( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from a control register PORT[port_ID] of of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param reg[in] register index + \param value[in] The data to be written + + \return RECEIVER[ID].PORT[port_ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_port_reg_load( + const rx_ID_t ID, + const enum mipi_port_id port_ID, + const hrt_address reg); + +/*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param port_ID[in] sub system identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_SYSTEM_H void input_system_sub_system_reg_store( + const input_system_ID_t ID, + const sub_system_ID_t sub_ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param port_ID[in] sub system identifier + \param reg[in] register index + \param value[in] The data to be written + + \return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_sub_system_reg_load( + const input_system_ID_t ID, + const sub_system_ID_t sub_ID, + const hrt_address reg); + +/////////////////////////////////////////////////////////////////////////// +// +// Functions for configuration phase on input system. +// +/////////////////////////////////////////////////////////////////////////// + +// Function that resets current configuration. +// remove the argument since it should be private. +input_system_err_t input_system_configuration_reset(void); + +// Function that commits current configuration. +// remove the argument since it should be private. +input_system_err_t input_system_configuration_commit(void); + +/////////////////////////////////////////////////////////////////////////// +// +// User functions: +// (encoded generic function) +// - no checking +// - decoding name and agruments into the generic (channel) configuration +// function. +// +/////////////////////////////////////////////////////////////////////////// + +// FIFO channel config function user + +input_system_err_t input_system_csi_fifo_channel_cfg( + u32 ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + target_cfg2400_t target +); + +input_system_err_t input_system_csi_fifo_channel_with_counting_cfg( + u32 ch_id, + u32 nof_frame, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + u32 mem_region_size, + u32 nof_mem_regions, + target_cfg2400_t target +); + +// SRAM channel config function user + +input_system_err_t input_system_csi_sram_channel_cfg( + u32 ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + u32 csi_mem_region_size, + u32 csi_nof_mem_regions, + target_cfg2400_t target +); + +//XMEM channel config function user + +input_system_err_t input_system_csi_xmem_channel_cfg( + u32 ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + u32 mem_region_size, + u32 nof_mem_regions, + u32 acq_mem_region_size, + u32 acq_nof_mem_regions, + target_cfg2400_t target, + uint32_t nof_xmem_buffers +); + +input_system_err_t input_system_csi_xmem_capture_only_channel_cfg( + u32 ch_id, + u32 nof_frames, + input_system_csi_port_t port, + u32 csi_mem_region_size, + u32 csi_nof_mem_regions, + u32 acq_mem_region_size, + u32 acq_nof_mem_regions, + target_cfg2400_t target +); + +input_system_err_t input_system_csi_xmem_acquire_only_channel_cfg( + u32 ch_id, + u32 nof_frames, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + u32 acq_mem_region_size, + u32 acq_nof_mem_regions, + target_cfg2400_t target +); + +// Non - CSI channel config function user + +input_system_err_t input_system_prbs_channel_cfg( + u32 ch_id, + u32 nof_frames, + u32 seed, + u32 sync_gen_width, + u32 sync_gen_height, + u32 sync_gen_hblank_cycles, + u32 sync_gen_vblank_cycles, + target_cfg2400_t target +); + +input_system_err_t input_system_tpg_channel_cfg( + u32 ch_id, + u32 nof_frames,//not used yet + u32 x_mask, + u32 y_mask, + u32 x_delta, + u32 y_delta, + u32 xy_mask, + u32 sync_gen_width, + u32 sync_gen_height, + u32 sync_gen_hblank_cycles, + u32 sync_gen_vblank_cycles, + target_cfg2400_t target +); + +input_system_err_t input_system_gpfifo_channel_cfg( + u32 ch_id, + u32 nof_frames, + target_cfg2400_t target +); +#endif /* #ifdef ISP2401 */ + +#endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/isp2400_support.h b/drivers/staging/media/atomisp/pci/isp2400_support.h new file mode 100644 index 000000000..06d04853d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp2400_support.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp2400_support_h +#define _isp2400_support_h + +#ifndef ISP2400_VECTOR_TYPES +/* This typedef is to be able to include hive header files + in the host code which is useful in crun */ +typedef char *tmemvectors, *tmemvectoru, *tvector; +#endif + +#define hrt_isp_vamem1_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem1), addr, val) +#define hrt_isp_vamem2_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem2), addr, val) + +#define hrt_isp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _base_dmem) +#define hrt_isp_vmem(cell) HRT_PROC_TYPE_PROP(cell, _simd_vmem) + +#define hrt_isp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_dmem(cell)) +#define hrt_isp_vmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_vmem(cell)) + +#if ISP_HAS_HIST +#define hrt_isp_hist(cell) HRT_PROC_TYPE_PROP(cell, _simd_histogram) +#define hrt_isp_hist_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_hist(cell)) +#endif + +#endif /* _isp2400_support_h */ diff --git a/drivers/staging/media/atomisp/pci/isp2401_input_system_global.h b/drivers/staging/media/atomisp/pci/isp2401_input_system_global.h new file mode 100644 index 000000000..e3c86069b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp2401_input_system_global.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* CSI reveiver has 3 ports. */ +#define N_CSI_PORTS (3) + +#include "system_local.h" +#include "isys_dma_global.h" /* isys2401_dma_channel, + * isys2401_dma_cfg_t + */ + +#include "ibuf_ctrl_local.h" /* ibuf_cfg_t, + * ibuf_ctrl_cfg_t + */ + +#include "isys_stream2mmio.h" /* stream2mmio_cfg_t */ + +#include "csi_rx.h" /* csi_rx_frontend_cfg_t, + * csi_rx_backend_cfg_t, + * csi_rx_backend_lut_entry_t + */ +#include "pixelgen.h" + +#define INPUT_SYSTEM_N_STREAM_ID 6 /* maximum number of simultaneous + virtual channels supported*/ + +typedef enum { + INPUT_SYSTEM_SOURCE_TYPE_UNDEFINED = 0, + INPUT_SYSTEM_SOURCE_TYPE_SENSOR, + INPUT_SYSTEM_SOURCE_TYPE_TPG, + INPUT_SYSTEM_SOURCE_TYPE_PRBS, + N_INPUT_SYSTEM_SOURCE_TYPE +} input_system_source_type_t; + +typedef struct input_system_channel_s input_system_channel_t; +struct input_system_channel_s { + stream2mmio_ID_t stream2mmio_id; + stream2mmio_sid_ID_t stream2mmio_sid_id; + + ibuf_ctrl_ID_t ibuf_ctrl_id; + isp2401_ib_buffer_t ib_buffer; + + isys2401_dma_ID_t dma_id; + isys2401_dma_channel dma_channel; +}; + +typedef struct input_system_channel_cfg_s input_system_channel_cfg_t; +struct input_system_channel_cfg_s { + stream2mmio_cfg_t stream2mmio_cfg; + ibuf_ctrl_cfg_t ibuf_ctrl_cfg; + isys2401_dma_cfg_t dma_cfg; + isys2401_dma_port_cfg_t dma_src_port_cfg; + isys2401_dma_port_cfg_t dma_dest_port_cfg; +}; + +typedef struct input_system_input_port_s input_system_input_port_t; +struct input_system_input_port_s { + input_system_source_type_t source_type; + + struct { + csi_rx_frontend_ID_t frontend_id; + csi_rx_backend_ID_t backend_id; + csi_mipi_packet_type_t packet_type; + csi_rx_backend_lut_entry_t backend_lut_entry; + } csi_rx; + + struct { + csi_mipi_packet_type_t packet_type; + csi_rx_backend_lut_entry_t backend_lut_entry; + } metadata; + + struct { + pixelgen_ID_t pixelgen_id; + } pixelgen; +}; + +typedef struct input_system_input_port_cfg_s input_system_input_port_cfg_t; +struct input_system_input_port_cfg_s { + struct { + csi_rx_frontend_cfg_t frontend_cfg; + csi_rx_backend_cfg_t backend_cfg; + csi_rx_backend_cfg_t md_backend_cfg; + } csi_rx_cfg; + + struct { + pixelgen_tpg_cfg_t tpg_cfg; + pixelgen_prbs_cfg_t prbs_cfg; + } pixelgen_cfg; +}; + +typedef struct isp2401_input_system_cfg_s isp2401_input_system_cfg_t; +struct isp2401_input_system_cfg_s { + input_system_input_port_ID_t input_port_id; + + input_system_source_type_t mode; + + bool online; + bool raw_packed; + s8 linked_isys_stream_id; + + struct { + bool comp_enable; + s32 active_lanes; + s32 fmt_type; + s32 ch_id; + s32 comp_predictor; + s32 comp_scheme; + } csi_port_attr; + + pixelgen_tpg_cfg_t tpg_port_attr; + + pixelgen_prbs_cfg_t prbs_port_attr; + + struct { + s32 align_req_in_bytes; + s32 bits_per_pixel; + s32 pixels_per_line; + s32 lines_per_frame; + } input_port_resolution; + + struct { + s32 left_padding; + s32 max_isp_input_width; + } output_port_attr; + + struct { + bool enable; + s32 fmt_type; + s32 align_req_in_bytes; + s32 bits_per_pixel; + s32 pixels_per_line; + s32 lines_per_frame; + } metadata; +}; + +typedef struct virtual_input_system_stream_s virtual_input_system_stream_t; +struct virtual_input_system_stream_s { + u32 id; /*Used when multiple MIPI data types and/or virtual channels are used. + Must be unique within one CSI RX + and lower than SH_CSS_MAX_ISYS_CHANNEL_NODES */ + u8 enable_metadata; + input_system_input_port_t input_port; + input_system_channel_t channel; + input_system_channel_t md_channel; /* metadata channel */ + u8 online; + s8 linked_isys_stream_id; + u8 valid; +}; + +typedef struct virtual_input_system_stream_cfg_s + virtual_input_system_stream_cfg_t; +struct virtual_input_system_stream_cfg_s { + u8 enable_metadata; + input_system_input_port_cfg_t input_port_cfg; + input_system_channel_cfg_t channel_cfg; + input_system_channel_cfg_t md_channel_cfg; + u8 valid; +}; + +#define ISP_INPUT_BUF_START_ADDR 0 +#define NUM_OF_INPUT_BUF 2 +#define NUM_OF_LINES_PER_BUF 2 +#define LINES_OF_ISP_INPUT_BUF (NUM_OF_INPUT_BUF * NUM_OF_LINES_PER_BUF) +#define ISP_INPUT_BUF_STRIDE SH_CSS_MAX_SENSOR_WIDTH diff --git a/drivers/staging/media/atomisp/pci/isp2401_input_system_local.h b/drivers/staging/media/atomisp/pci/isp2401_input_system_local.h new file mode 100644 index 000000000..74bfa10e6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp2401_input_system_local.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_LOCAL_H_INCLUDED__ +#define __INPUT_SYSTEM_LOCAL_H_INCLUDED__ + +#include "csi_rx.h" +#include "pixelgen.h" +#include "isys_stream2mmio.h" +#include "isys_irq.h" + +typedef enum { + MIPI_FORMAT_SHORT1 = 0x08, + MIPI_FORMAT_SHORT2, + MIPI_FORMAT_SHORT3, + MIPI_FORMAT_SHORT4, + MIPI_FORMAT_SHORT5, + MIPI_FORMAT_SHORT6, + MIPI_FORMAT_SHORT7, + MIPI_FORMAT_SHORT8, + MIPI_FORMAT_EMBEDDED = 0x12, + MIPI_FORMAT_YUV420_8 = 0x18, + MIPI_FORMAT_YUV420_10, + MIPI_FORMAT_YUV420_8_LEGACY, + MIPI_FORMAT_YUV420_8_SHIFT = 0x1C, + MIPI_FORMAT_YUV420_10_SHIFT, + MIPI_FORMAT_YUV422_8 = 0x1E, + MIPI_FORMAT_YUV422_10, + MIPI_FORMAT_RGB444 = 0x20, + MIPI_FORMAT_RGB555, + MIPI_FORMAT_RGB565, + MIPI_FORMAT_RGB666, + MIPI_FORMAT_RGB888, + MIPI_FORMAT_RAW6 = 0x28, + MIPI_FORMAT_RAW7, + MIPI_FORMAT_RAW8, + MIPI_FORMAT_RAW10, + MIPI_FORMAT_RAW12, + MIPI_FORMAT_RAW14, + MIPI_FORMAT_CUSTOM0 = 0x30, + MIPI_FORMAT_CUSTOM1, + MIPI_FORMAT_CUSTOM2, + MIPI_FORMAT_CUSTOM3, + MIPI_FORMAT_CUSTOM4, + MIPI_FORMAT_CUSTOM5, + MIPI_FORMAT_CUSTOM6, + MIPI_FORMAT_CUSTOM7, + //MIPI_FORMAT_RAW16, /*not supported by 2401*/ + //MIPI_FORMAT_RAW18, + N_MIPI_FORMAT +} mipi_format_t; + +#define N_MIPI_FORMAT_CUSTOM 8 + +/* The number of stores for compressed format types */ +#define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM) +typedef struct input_system_state_s input_system_state_t; +struct input_system_state_s { + ibuf_ctrl_state_t ibuf_ctrl_state[N_IBUF_CTRL_ID]; + csi_rx_fe_ctrl_state_t csi_rx_fe_ctrl_state[N_CSI_RX_FRONTEND_ID]; + csi_rx_be_ctrl_state_t csi_rx_be_ctrl_state[N_CSI_RX_BACKEND_ID]; + pixelgen_ctrl_state_t pixelgen_ctrl_state[N_PIXELGEN_ID]; + stream2mmio_state_t stream2mmio_state[N_STREAM2MMIO_ID]; + isys_irqc_state_t isys_irqc_state[N_ISYS_IRQ_ID]; +}; +#endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/isp2401_input_system_private.h b/drivers/staging/media/atomisp/pci/isp2401_input_system_private.h new file mode 100644 index 000000000..e4c76428f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp2401_input_system_private.h @@ -0,0 +1,342 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ +#define __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ + +#include "input_system_public.h" + +#include "device_access.h" /* ia_css_device_load_uint32 */ + +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + +/* Load the register value */ +static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_IBUF_CTRL_ID); + assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data)); +} + +/* Store a value to the register */ +static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_IBUF_CTRL_ID); + assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); +} + +/* Get the state of the ibuf-controller process */ +static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID, + const u32 proc_id, + ibuf_ctrl_proc_state_t *state) +{ + hrt_address reg_bank_offset; + + reg_bank_offset = + _IBUF_CNTRL_PROC_REG_ALIGN * (1 + proc_id); + + state->num_items = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE); + + state->num_stores = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_STORES_PER_FRAME); + + state->dma_channel = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CHANNEL); + + state->dma_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CMD); + + state->ibuf_st_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_START_ADDRESS); + + state->ibuf_stride = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_STRIDE); + + state->ibuf_end_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_END_ADDRESS); + + state->dest_st_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_START_ADDRESS); + + state->dest_stride = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_STRIDE); + + state->dest_end_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_END_ADDRESS); + + state->sync_frame = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SYNC_FRAME); + + state->sync_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_SYNC_CMD); + + state->store_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_STORE_CMD); + + state->shift_returned_items = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SHIFT_ITEMS); + + state->elems_ibuf = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_IBUF); + + state->elems_dest = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_DEST); + + state->cur_stores = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_STORES); + + state->cur_acks = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ACKS); + + state->cur_s2m_ibuf_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_S2M_IBUF_ADDR); + + state->cur_dma_ibuf_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_IBUF_ADDR); + + state->cur_dma_dest_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_DEST_ADDR); + + state->cur_isp_dest_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ISP_DEST_ADDR); + + state->dma_cmds_send = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND); + + state->main_cntrl_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_MAIN_CNTRL_STATE); + + state->dma_sync_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_SYNC_STATE); + + state->isp_sync_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE); +} + +/* Get the ibuf-controller state. */ +static inline void ibuf_ctrl_get_state(const ibuf_ctrl_ID_t ID, + ibuf_ctrl_state_t *state) +{ + u32 i; + + state->recalc_words = + ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS); + state->arbiters = + ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_ARBITERS_STATUS); + + /* + * Get the values of the register-set per + * ibuf-controller process. + */ + for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { + ibuf_ctrl_get_proc_state( + ID, + i, + &state->proc_state[i]); + } +} + +/* Dump the ibuf-controller state */ +static inline void ibuf_ctrl_dump_state(const ibuf_ctrl_ID_t ID, + ibuf_ctrl_state_t *state) +{ + u32 i; + + ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID, + state->recalc_words); + ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters); + + /* + * Dump the values of the register-set per + * ibuf-controller process. + */ + for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { + ia_css_print("IBUF controller ID %d Process ID %d num_items 0x%x\n", ID, i, + state->proc_state[i].num_items); + ia_css_print("IBUF controller ID %d Process ID %d num_stores 0x%x\n", ID, i, + state->proc_state[i].num_stores); + ia_css_print("IBUF controller ID %d Process ID %d dma_channel 0x%x\n", ID, i, + state->proc_state[i].dma_channel); + ia_css_print("IBUF controller ID %d Process ID %d dma_command 0x%x\n", ID, i, + state->proc_state[i].dma_command); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_st_addr 0x%x\n", ID, i, + state->proc_state[i].ibuf_st_addr); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_stride 0x%x\n", ID, i, + state->proc_state[i].ibuf_stride); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_end_addr 0x%x\n", ID, i, + state->proc_state[i].ibuf_end_addr); + ia_css_print("IBUF controller ID %d Process ID %d dest_st_addr 0x%x\n", ID, i, + state->proc_state[i].dest_st_addr); + ia_css_print("IBUF controller ID %d Process ID %d dest_stride 0x%x\n", ID, i, + state->proc_state[i].dest_stride); + ia_css_print("IBUF controller ID %d Process ID %d dest_end_addr 0x%x\n", ID, i, + state->proc_state[i].dest_end_addr); + ia_css_print("IBUF controller ID %d Process ID %d sync_frame 0x%x\n", ID, i, + state->proc_state[i].sync_frame); + ia_css_print("IBUF controller ID %d Process ID %d sync_command 0x%x\n", ID, i, + state->proc_state[i].sync_command); + ia_css_print("IBUF controller ID %d Process ID %d store_command 0x%x\n", ID, i, + state->proc_state[i].store_command); + ia_css_print("IBUF controller ID %d Process ID %d shift_returned_items 0x%x\n", + ID, i, + state->proc_state[i].shift_returned_items); + ia_css_print("IBUF controller ID %d Process ID %d elems_ibuf 0x%x\n", ID, i, + state->proc_state[i].elems_ibuf); + ia_css_print("IBUF controller ID %d Process ID %d elems_dest 0x%x\n", ID, i, + state->proc_state[i].elems_dest); + ia_css_print("IBUF controller ID %d Process ID %d cur_stores 0x%x\n", ID, i, + state->proc_state[i].cur_stores); + ia_css_print("IBUF controller ID %d Process ID %d cur_acks 0x%x\n", ID, i, + state->proc_state[i].cur_acks); + ia_css_print("IBUF controller ID %d Process ID %d cur_s2m_ibuf_addr 0x%x\n", ID, + i, + state->proc_state[i].cur_s2m_ibuf_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_dma_ibuf_addr 0x%x\n", ID, + i, + state->proc_state[i].cur_dma_ibuf_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_dma_dest_addr 0x%x\n", ID, + i, + state->proc_state[i].cur_dma_dest_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_isp_dest_addr 0x%x\n", ID, + i, + state->proc_state[i].cur_isp_dest_addr); + ia_css_print("IBUF controller ID %d Process ID %d dma_cmds_send 0x%x\n", ID, i, + state->proc_state[i].dma_cmds_send); + ia_css_print("IBUF controller ID %d Process ID %d main_cntrl_state 0x%x\n", ID, + i, + state->proc_state[i].main_cntrl_state); + ia_css_print("IBUF controller ID %d Process ID %d dma_sync_state 0x%x\n", ID, i, + state->proc_state[i].dma_sync_state); + ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i, + state->proc_state[i].isp_sync_state); + } +} + +static inline input_system_err_t +input_system_get_state(const input_system_ID_t ID, + input_system_state_t *state) +{ + u32 i; + + (void)(ID); + + /* get the states of all CSI RX frontend devices */ + for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) { + csi_rx_fe_ctrl_get_state( + (csi_rx_frontend_ID_t)i, + &state->csi_rx_fe_ctrl_state[i]); + } + + /* get the states of all CIS RX backend devices */ + for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) { + csi_rx_be_ctrl_get_state( + (csi_rx_backend_ID_t)i, + &state->csi_rx_be_ctrl_state[i]); + } + + /* get the states of all pixelgen devices */ + for (i = 0; i < N_PIXELGEN_ID; i++) { + pixelgen_ctrl_get_state( + (pixelgen_ID_t)i, + &state->pixelgen_ctrl_state[i]); + } + + /* get the states of all stream2mmio devices */ + for (i = 0; i < N_STREAM2MMIO_ID; i++) { + stream2mmio_get_state( + (stream2mmio_ID_t)i, + &state->stream2mmio_state[i]); + } + + /* get the states of all ibuf-controller devices */ + for (i = 0; i < N_IBUF_CTRL_ID; i++) { + ibuf_ctrl_get_state( + (ibuf_ctrl_ID_t)i, + &state->ibuf_ctrl_state[i]); + } + + /* get the states of all isys irq controllers */ + for (i = 0; i < N_ISYS_IRQ_ID; i++) { + isys_irqc_state_get((isys_irq_ID_t)i, &state->isys_irqc_state[i]); + } + + /* TODO: get the states of all ISYS2401 DMA devices */ + for (i = 0; i < N_ISYS2401_DMA_ID; i++) { + } + + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +static inline void input_system_dump_state(const input_system_ID_t ID, + input_system_state_t *state) +{ + u32 i; + + (void)(ID); + + /* dump the states of all CSI RX frontend devices */ + for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) { + csi_rx_fe_ctrl_dump_state( + (csi_rx_frontend_ID_t)i, + &state->csi_rx_fe_ctrl_state[i]); + } + + /* dump the states of all CIS RX backend devices */ + for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) { + csi_rx_be_ctrl_dump_state( + (csi_rx_backend_ID_t)i, + &state->csi_rx_be_ctrl_state[i]); + } + + /* dump the states of all pixelgen devices */ + for (i = 0; i < N_PIXELGEN_ID; i++) { + pixelgen_ctrl_dump_state( + (pixelgen_ID_t)i, + &state->pixelgen_ctrl_state[i]); + } + + /* dump the states of all st2mmio devices */ + for (i = 0; i < N_STREAM2MMIO_ID; i++) { + stream2mmio_dump_state( + (stream2mmio_ID_t)i, + &state->stream2mmio_state[i]); + } + + /* dump the states of all ibuf-controller devices */ + for (i = 0; i < N_IBUF_CTRL_ID; i++) { + ibuf_ctrl_dump_state( + (ibuf_ctrl_ID_t)i, + &state->ibuf_ctrl_state[i]); + } + + /* dump the states of all isys irq controllers */ + for (i = 0; i < N_ISYS_IRQ_ID; i++) { + isys_irqc_state_dump((isys_irq_ID_t)i, &state->isys_irqc_state[i]); + } + + /* TODO: dump the states of all ISYS2401 DMA devices */ + for (i = 0; i < N_ISYS2401_DMA_ID; i++) { + } + + return; +} +#endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/isp_acquisition_defs.h b/drivers/staging/media/atomisp/pci/isp_acquisition_defs.h new file mode 100644 index 000000000..7e8f6f217 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp_acquisition_defs.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_acquisition_defs_h +#define _isp_acquisition_defs_h + +#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_ACQUISITION_BYTES_PER_ELEM 4 + +/* --------------------------------------------------*/ + +#define NOF_ACQ_IRQS 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define MEM2STREAM_FSM_STATE_BITS 2 +#define ACQ_SYNCHRONIZER_FSM_STATE_BITS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +#define NOF_ACQ_REGS 12 + +// Register id's of MMIO slave accessible registers +#define ACQ_START_ADDR_REG_ID 0 +#define ACQ_MEM_REGION_SIZE_REG_ID 1 +#define ACQ_NUM_MEM_REGIONS_REG_ID 2 +#define ACQ_INIT_REG_ID 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4 +#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5 +#define ACQ_LAST_COMMAND_REG_ID 6 +#define ACQ_NEXT_COMMAND_REG_ID 7 +#define ACQ_LAST_ACKNOWLEDGE_REG_ID 8 +#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9 +#define ACQ_FSM_STATE_INFO_REG_ID 10 +#define ACQ_INT_CNTR_INFO_REG_ID 11 + +// Register width +#define ACQ_START_ADDR_REG_WIDTH 9 +#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ACQ_INIT_REG_WIDTH 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define ACQ_LAST_COMMAND_REG_WIDTH 32 +#define ACQ_NEXT_COMMAND_REG_WIDTH 32 +#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS * 3)) +#define ACQ_INT_CNTR_INFO_REG_WIDTH 32 + +/* register reset value */ +#define ACQ_START_ADDR_REG_RSTVAL 0 +#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ACQ_INIT_REG_RSTVAL 0 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define ACQ_LAST_COMMAND_REG_RSTVAL 0 +#define ACQ_NEXT_COMMAND_REG_RSTVAL 0 +#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define ACQ_INIT_RST_REG_BIT 0 +#define ACQ_INIT_RESYNC_BIT 2 +#define ACQ_INIT_RST_IDX ACQ_INIT_RST_REG_BIT +#define ACQ_INIT_RST_BITS 1 +#define ACQ_INIT_RESYNC_IDX ACQ_INIT_RESYNC_BIT +#define ACQ_INIT_RESYNC_BITS 1 + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define ACQ_TOKEN_ID_LSB 0 +#define ACQ_TOKEN_ID_MSB 3 +#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4 +#define ACQ_TOKEN_ID_IDX 0 +#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH +#define ACQ_INIT_CMD_INIT_IDX 4 +#define ACQ_INIT_CMD_INIT_BITS 3 +#define ACQ_CMD_START_ADDR_IDX 4 +#define ACQ_CMD_START_ADDR_BITS 9 +#define ACQ_CMD_NOFWORDS_IDX 13 +#define ACQ_CMD_NOFWORDS_BITS 9 +#define ACQ_MEM_REGION_ID_IDX 22 +#define ACQ_MEM_REGION_ID_BITS 9 +#define ACQ_PACKET_LENGTH_TOKEN_MSB 21 +#define ACQ_PACKET_LENGTH_TOKEN_LSB 13 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_LSB 4 +#define ACQ_PACKET_CH_ID_TOKEN_MSB 11 +#define ACQ_PACKET_CH_ID_TOKEN_LSB 10 +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */ +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */ + +/* Command tokens IDs */ +#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b +#define ACQ_READ_REGION_TOKEN_ID 1 //0001b +#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b +#define ACQ_INIT_TOKEN_ID 8 //1000b + +/* Acknowledge token IDs */ +#define ACQ_READ_REGION_ACK_TOKEN_ID 0 //0000b +#define ACQ_END_OF_PACKET_TOKEN_ID 4 //0100b +#define ACQ_END_OF_REGION_TOKEN_ID 5 //0101b +#define ACQ_SOP_MISMATCH_TOKEN_ID 6 //0110b +#define ACQ_UNDEF_PH_TOKEN_ID 7 //0111b + +#define ACQ_TOKEN_MEMREGIONID_MSB 30 +#define ACQ_TOKEN_MEMREGIONID_LSB 22 +#define ACQ_TOKEN_NOFWORDS_MSB 21 +#define ACQ_TOKEN_NOFWORDS_LSB 13 +#define ACQ_TOKEN_STARTADDR_MSB 12 +#define ACQ_TOKEN_STARTADDR_LSB 4 + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define WORD_COUNT_WIDTH 16 +#define PKT_CODE_WIDTH 6 +#define CHN_NO_WIDTH 2 +#define ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + +#define EOF_CODE 1 + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define ACQ_START_OF_FRAME 0 +#define ACQ_END_OF_FRAME 1 +#define ACQ_START_OF_LINE 2 +#define ACQ_END_OF_LINE 3 +#define ACQ_LINE_PAYLOAD 4 +#define ACQ_GEN_SH_PKT 5 + +/* bit definition */ +#define ACQ_PKT_TYPE_IDX 16 +#define ACQ_PKT_TYPE_BITS 6 +#define ACQ_PKT_SOP_IDX 32 +#define ACQ_WORD_CNT_IDX 0 +#define ACQ_WORD_CNT_BITS 16 +#define ACQ_PKT_INFO_IDX 16 +#define ACQ_PKT_INFO_BITS 8 +#define ACQ_HEADER_DATA_IDX 0 +#define ACQ_HEADER_DATA_BITS 16 +#define ACQ_ACK_TOKEN_ID_IDX ACQ_TOKEN_ID_IDX +#define ACQ_ACK_TOKEN_ID_BITS ACQ_TOKEN_ID_BITS +#define ACQ_ACK_NOFWORDS_IDX 13 +#define ACQ_ACK_NOFWORDS_BITS 9 +#define ACQ_ACK_PKT_LEN_IDX 4 +#define ACQ_ACK_PKT_LEN_BITS 16 + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + +#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define ACQ_SOF_DATA 0 /* 00 0000 frame start */ +#define ACQ_EOF_DATA 1 /* 00 0001 frame end */ +#define ACQ_SOL_DATA 2 /* 00 0010 line start */ +#define ACQ_EOL_DATA 3 /* 00 0011 line end */ +#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_RESERVED_DATA_TYPE_MIN 56 +#define ACQ_RESERVED_DATA_TYPE_MAX 63 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define ACQ_YUV_RESERVED_DATA_TYPE 27 +#define ACQ_RGB_RESERVED_DATA_TYPE_MIN 37 +#define ACQ_RGB_RESERVED_DATA_TYPE_MAX 39 +#define ACQ_RAW_RESERVED_DATA_TYPE_MIN 46 +#define ACQ_RAW_RESERVED_DATA_TYPE_MAX 47 + +/* --------------------------------------------------*/ + +#endif /* _isp_acquisition_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/isp_capture_defs.h b/drivers/staging/media/atomisp/pci/isp_capture_defs.h new file mode 100644 index 000000000..b9e5ed932 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/isp_capture_defs.h @@ -0,0 +1,279 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_capture_defs_h +#define _isp_capture_defs_h + +#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */ +#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM / 8) +#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */ +#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM + +/* --------------------------------------------------*/ + +#define NOF_IRQS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define CAPT_NOF_REGS 16 + +// Register id's of MMIO slave accessible registers +#define CAPT_START_MODE_REG_ID 0 +#define CAPT_START_ADDR_REG_ID 1 +#define CAPT_MEM_REGION_SIZE_REG_ID 2 +#define CAPT_NUM_MEM_REGIONS_REG_ID 3 +#define CAPT_INIT_REG_ID 4 +#define CAPT_START_REG_ID 5 +#define CAPT_STOP_REG_ID 6 + +#define CAPT_PACKET_LENGTH_REG_ID 7 +#define CAPT_RECEIVED_LENGTH_REG_ID 8 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9 +#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10 +#define CAPT_LAST_COMMAND_REG_ID 11 +#define CAPT_NEXT_COMMAND_REG_ID 12 +#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13 +#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14 +#define CAPT_FSM_STATE_INFO_REG_ID 15 + +// Register width +#define CAPT_START_MODE_REG_WIDTH 1 + +#define CAPT_START_REG_WIDTH 1 +#define CAPT_STOP_REG_WIDTH 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define CAPT_WRITE2MEM_FSM_STATE_BITS 2 +#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3 + +#define CAPT_PACKET_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define CAPT_LAST_COMMAND_REG_WIDTH 32 +#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3)) + +/* register reset value */ +#define CAPT_START_MODE_REG_RSTVAL 0 +#define CAPT_START_ADDR_REG_RSTVAL 0 +#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128 +#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define CAPT_INIT_REG_RSTVAL 0 + +#define CAPT_START_REG_RSTVAL 0 +#define CAPT_STOP_REG_RSTVAL 0 + +#define CAPT_PACKET_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define CAPT_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define CAPT_LAST_COMMAND_REG_RSTVAL 0 +#define CAPT_NEXT_COMMAND_REG_RSTVAL 0 +#define CAPT_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_FSM_STATE_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define CAPT_INIT_RST_REG_BIT 0 +#define CAPT_INIT_FLUSH_BIT 1 +#define CAPT_INIT_RESYNC_BIT 2 +#define CAPT_INIT_RESTART_BIT 3 +#define CAPT_INIT_RESTART_MEM_ADDR_LSB 4 + +#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT +#define CAPT_INIT_RST_REG_BITS 1 +#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT +#define CAPT_INIT_FLUSH_BITS 1 +#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT +#define CAPT_INIT_RESYNC_BITS 1 +#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT +#define CAPT_INIT_RESTART_BITS 1 +#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define CAPT_TOKEN_ID_LSB 0 +#define CAPT_TOKEN_ID_MSB 3 +#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */ + +/* Command tokens IDs */ +#define CAPT_START_TOKEN_ID 0 /* 0000b */ +#define CAPT_STOP_TOKEN_ID 1 /* 0001b */ +#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */ +#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */ +#define CAPT_INIT_TOKEN_ID 8 /* 1000b */ + +#define CAPT_START_TOKEN_BIT 0 +#define CAPT_STOP_TOKEN_BIT 0 +#define CAPT_FREEZE_TOKEN_BIT 0 +#define CAPT_RESUME_TOKEN_BIT 0 +#define CAPT_INIT_TOKEN_BIT 0 + +/* Acknowledge token IDs */ +#define CAPT_END_OF_PACKET_RECEIVED_TOKEN_ID 0 /* 0000b */ +#define CAPT_END_OF_PACKET_WRITTEN_TOKEN_ID 1 /* 0001b */ +#define CAPT_END_OF_REGION_WRITTEN_TOKEN_ID 2 /* 0010b */ +#define CAPT_FLUSH_DONE_TOKEN_ID 3 /* 0011b */ +#define CAPT_PREMATURE_SOP_TOKEN_ID 4 /* 0100b */ +#define CAPT_MISSING_SOP_TOKEN_ID 5 /* 0101b */ +#define CAPT_UNDEF_PH_TOKEN_ID 6 /* 0110b */ +#define CAPT_STOP_ACK_TOKEN_ID 7 /* 0111b */ + +#define CAPT_PACKET_LENGTH_TOKEN_MSB 19 +#define CAPT_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB 20 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB 25 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20 +#define CAPT_PACKET_CH_ID_TOKEN_MSB 27 +#define CAPT_PACKET_CH_ID_TOKEN_LSB 26 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21 + +/* bit definition */ +#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB +#define CAPT_CMD_BITS (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) +#define CAPT_SOP_IDX 32 +#define CAPT_SOP_BITS 1 +#define CAPT_PKT_INFO_IDX 16 +#define CAPT_PKT_INFO_BITS 8 +#define CAPT_PKT_TYPE_IDX 0 +#define CAPT_PKT_TYPE_BITS 6 +#define CAPT_HEADER_DATA_IDX 0 +#define CAPT_HEADER_DATA_BITS 16 +#define CAPT_PKT_DATA_IDX 0 +#define CAPT_PKT_DATA_BITS 32 +#define CAPT_WORD_CNT_IDX 0 +#define CAPT_WORD_CNT_BITS 16 +#define CAPT_ACK_TOKEN_ID_IDX 0 +#define CAPT_ACK_TOKEN_ID_BITS 4 +//#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +//#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +//#define CAPT_ACK_PKT_INFO_IDX 20 +//#define CAPT_ACK_PKT_INFO_BITS 8 +//#define CAPT_ACK_MEM_REG_ID1_IDX 20 /* for capt_end_of_packet_written */ +//#define CAPT_ACK_MEM_REG_ID2_IDX 4 /* for capt_end_of_region_written */ +#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_SUPER_PKT_LEN_IDX CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_SUPER_PKT_LEN_BITS (CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB - CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_INFO_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_INFO_BITS (CAPT_PACKET_CH_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_ACK_MEM_REGION_ID_IDX CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB +#define CAPT_ACK_MEM_REGION_ID_BITS (CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB - CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_TYPE_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_TYPE_BITS (CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_INIT_TOKEN_INIT_IDX 4 +#define CAPT_INIT_TOKEN_INIT_BITS 22 + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define CAPT_WORD_COUNT_WIDTH 16 +#define CAPT_PKT_CODE_WIDTH 6 +#define CAPT_CHN_NO_WIDTH 2 +#define CAPT_ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define CAPT_START_OF_FRAME 0 +#define CAPT_END_OF_FRAME 1 +#define CAPT_START_OF_LINE 2 +#define CAPT_END_OF_LINE 3 +#define CAPT_LINE_PAYLOAD 4 +#define CAPT_GEN_SH_PKT 5 + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + +#define CAPT_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define CAPT_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define CAPT_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define CAPT_SOF_DATA 0 /* 00 0000 frame start */ +#define CAPT_EOF_DATA 1 /* 00 0001 frame end */ +#define CAPT_SOL_DATA 2 /* 00 0010 line start */ +#define CAPT_EOL_DATA 3 /* 00 0011 line end */ +#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_RESERVED_DATA_TYPE_MIN 56 +#define CAPT_RESERVED_DATA_TYPE_MAX 63 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define CAPT_YUV_RESERVED_DATA_TYPE 27 +#define CAPT_RGB_RESERVED_DATA_TYPE_MIN 37 +#define CAPT_RGB_RESERVED_DATA_TYPE_MAX 39 +#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46 +#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47 + +/* --------------------------------------------------*/ +/* Capture Unit State */ +/* --------------------------------------------------*/ +#define CAPT_FREE_RUN 0 +#define CAPT_NO_SYNC 1 +#define CAPT_SYNC_SWP 2 +#define CAPT_SYNC_MWP 3 +#define CAPT_SYNC_WAIT 4 +#define CAPT_FREEZE 5 +#define CAPT_RUN 6 + +/* --------------------------------------------------*/ + +#endif /* _isp_capture_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/mamoiada_params.h b/drivers/staging/media/atomisp/pci/mamoiada_params.h new file mode 100644 index 000000000..e18e5f357 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/mamoiada_params.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Version */ +#define RTL_VERSION + +/* instruction pipeline depth */ +#define ISP_BRANCHDELAY 5 + +/* bus */ +#define ISP_BUS_WIDTH 32 +#define ISP_BUS_ADDR_WIDTH 32 +#define ISP_BUS_BURST_SIZE 1 + +/* data-path */ +#define ISP_SCALAR_WIDTH 32 +#define ISP_SLICE_NELEMS 4 +#define ISP_VEC_NELEMS 64 +#define ISP_VEC_ELEMBITS 14 +#define ISP_VEC_ELEM8BITS 16 +#define ISP_CLONE_DATAPATH_IS_16 1 + +/* memories */ +#define ISP_DMEM_DEPTH 4096 +#define ISP_DMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_DEPTH 3072 +#define ISP_VMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_ELEMBITS 14 +#define ISP_VMEM_ELEM_PRECISION 14 +#define ISP_PMEM_DEPTH 2048 +#define ISP_PMEM_WIDTH 640 +#define ISP_VAMEM_ADDRESS_BITS 12 +#define ISP_VAMEM_ELEMBITS 12 +#define ISP_VAMEM_DEPTH 2048 +#define ISP_VAMEM_ALIGNMENT 2 +#define ISP_VA_ADDRESS_WIDTH 896 +#define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS +#define ISP_HIST_ADDRESS_BITS 12 +#define ISP_HIST_ALIGNMENT 4 +#define ISP_HIST_COMP_IN_PREC 12 +#define ISP_HIST_DEPTH 1024 +#define ISP_HIST_WIDTH 24 +#define ISP_HIST_COMPONENTS 4 + +/* program counter */ +#define ISP_PC_WIDTH 13 + +/* Template switches */ +#define ISP_SHIELD_INPUT_DMEM 0 +#define ISP_SHIELD_OUTPUT_DMEM 1 +#define ISP_SHIELD_INPUT_VMEM 0 +#define ISP_SHIELD_OUTPUT_VMEM 0 +#define ISP_SHIELD_INPUT_PMEM 1 +#define ISP_SHIELD_OUTPUT_PMEM 1 +#define ISP_SHIELD_INPUT_HIST 1 +#define ISP_SHIELD_OUTPUT_HIST 1 +/* When LUT is select the shielding is always on */ +#define ISP_SHIELD_INPUT_VAMEM 1 +#define ISP_SHIELD_OUTPUT_VAMEM 1 + +#define ISP_HAS_IRQ 1 +#define ISP_HAS_SOFT_RESET 1 +#define ISP_HAS_VEC_DIV 0 +#define ISP_HAS_VFU_W_2O 1 +#define ISP_HAS_DEINT3 1 +#define ISP_HAS_LUT 1 +#define ISP_HAS_HIST 1 +#define ISP_HAS_VALSU 1 +#define ISP_HAS_3rdVALSU 1 +#define ISP_VRF1_HAS_2P 1 + +#define ISP_SRU_GUARDING 1 +#define ISP_VLSU_GUARDING 1 + +#define ISP_VRF_RAM 1 +#define ISP_SRF_RAM 1 + +#define ISP_SPLIT_VMUL_VADD_IS 0 +#define ISP_RFSPLIT_FPGA 0 + +/* RSN or Bus pipelining */ +#define ISP_RSN_PIPE 1 +#define ISP_VSF_BUS_PIPE 0 + +/* extra slave port to vmem */ +#define ISP_IF_VMEM 0 +#define ISP_GDC_VMEM 0 + +/* Streaming ports */ +#define ISP_IF 1 +#define ISP_IF_B 1 +#define ISP_GDC 1 +#define ISP_SCL 1 +#define ISP_GPFIFO 1 +#define ISP_SP 1 + +/* Removing Issue Slot(s) */ +#define ISP_HAS_NOT_SIMD_IS2 0 +#define ISP_HAS_NOT_SIMD_IS3 0 +#define ISP_HAS_NOT_SIMD_IS4 0 +#define ISP_HAS_NOT_SIMD_IS4_VADD 0 +#define ISP_HAS_NOT_SIMD_IS5 0 +#define ISP_HAS_NOT_SIMD_IS6 0 +#define ISP_HAS_NOT_SIMD_IS7 0 +#define ISP_HAS_NOT_SIMD_IS8 0 + +/* ICache */ +#define ISP_ICACHE 1 +#define ISP_ICACHE_ONLY 0 +#define ISP_ICACHE_PREFETCH 1 +#define ISP_ICACHE_INDEX_BITS 8 +#define ISP_ICACHE_SET_BITS 5 +#define ISP_ICACHE_BLOCKS_PER_SET_BITS 1 + +/* Experimental Flags */ +#define ISP_EXP_1 0 +#define ISP_EXP_2 0 +#define ISP_EXP_3 0 +#define ISP_EXP_4 0 +#define ISP_EXP_5 0 +#define ISP_EXP_6 0 + +/* Derived values */ +#define ISP_LOG2_PMEM_WIDTH 10 +#define ISP_VEC_WIDTH 896 +#define ISP_SLICE_WIDTH 56 +#define ISP_VMEM_WIDTH 896 +#define ISP_VMEM_ALIGN 128 +#define ISP_SIMDLSU 1 +#define ISP_LSU_IMM_BITS 12 + +/* convenient shortcuts for software*/ +#define ISP_NWAY ISP_VEC_NELEMS +#define NBITS ISP_VEC_ELEMBITS + +#define _isp_ceil_div(a, b) (((a) + (b) - 1) / (b)) + +#define ISP_VEC_ALIGN ISP_VMEM_ALIGN + +/* register file sizes */ +#define ISP_RF0_SIZE 64 +#define ISP_RF1_SIZE 16 +#define ISP_RF2_SIZE 64 +#define ISP_RF3_SIZE 4 +#define ISP_RF4_SIZE 64 +#define ISP_RF5_SIZE 16 +#define ISP_RF6_SIZE 16 +#define ISP_RF7_SIZE 16 +#define ISP_RF8_SIZE 16 +#define ISP_RF9_SIZE 16 +#define ISP_RF10_SIZE 16 +#define ISP_RF11_SIZE 16 + +#define ISP_SRF1_SIZE 4 +#define ISP_SRF2_SIZE 64 +#define ISP_SRF3_SIZE 64 +#define ISP_SRF4_SIZE 32 +#define ISP_SRF5_SIZE 64 +#define ISP_FRF0_SIZE 16 +#define ISP_FRF1_SIZE 4 +#define ISP_FRF2_SIZE 16 +#define ISP_FRF3_SIZE 4 +#define ISP_FRF4_SIZE 4 +#define ISP_FRF5_SIZE 8 +#define ISP_FRF6_SIZE 4 +/* register file read latency */ +#define ISP_VRF1_READ_LAT 1 +#define ISP_VRF2_READ_LAT 1 +#define ISP_VRF3_READ_LAT 1 +#define ISP_VRF4_READ_LAT 1 +#define ISP_VRF5_READ_LAT 1 +#define ISP_VRF6_READ_LAT 1 +#define ISP_VRF7_READ_LAT 1 +#define ISP_VRF8_READ_LAT 1 +#define ISP_SRF1_READ_LAT 1 +#define ISP_SRF2_READ_LAT 1 +#define ISP_SRF3_READ_LAT 1 +#define ISP_SRF4_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +/* immediate sizes */ +#define ISP_IS1_IMM_BITS 14 +#define ISP_IS2_IMM_BITS 13 +#define ISP_IS3_IMM_BITS 14 +#define ISP_IS4_IMM_BITS 14 +#define ISP_IS5_IMM_BITS 9 +#define ISP_IS6_IMM_BITS 16 +#define ISP_IS7_IMM_BITS 9 +#define ISP_IS8_IMM_BITS 16 +#define ISP_IS9_IMM_BITS 11 +/* fifo depths */ +#define ISP_IF_FIFO_DEPTH 0 +#define ISP_IF_B_FIFO_DEPTH 0 +#define ISP_DMA_FIFO_DEPTH 0 +#define ISP_OF_FIFO_DEPTH 0 +#define ISP_GDC_FIFO_DEPTH 0 +#define ISP_SCL_FIFO_DEPTH 0 +#define ISP_GPFIFO_FIFO_DEPTH 0 +#define ISP_SP_FIFO_DEPTH 0 diff --git a/drivers/staging/media/atomisp/pci/mmu/isp_mmu.c b/drivers/staging/media/atomisp/pci/mmu/isp_mmu.c new file mode 100644 index 000000000..72287de75 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/mmu/isp_mmu.c @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +/* + * ISP MMU management wrap code + */ +#include +#include +#include +#include /* for GFP_ATOMIC */ +#include /* for kmalloc */ +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_X86 +#include +#endif + +#include "atomisp_internal.h" +#include "mmu/isp_mmu.h" + +/* + * 64-bit x86 processor physical address layout: + * 0 - 0x7fffffff DDR RAM (2GB) + * 0x80000000 - 0xffffffff MMIO (2GB) + * 0x100000000 - 0x3fffffffffff DDR RAM (64TB) + * So if the system has more than 2GB DDR memory, the lower 2GB occupies the + * physical address 0 - 0x7fffffff and the rest will start from 0x100000000. + * We have to make sure memory is allocated from the lower 2GB for devices + * that are only 32-bit capable(e.g. the ISP MMU). + * + * For any confusion, contact bin.gao@intel.com. + */ +#define NR_PAGES_2GB (SZ_2G / PAGE_SIZE) + +static void free_mmu_map(struct isp_mmu *mmu, unsigned int start_isp_virt, + unsigned int end_isp_virt); + +static unsigned int atomisp_get_pte(phys_addr_t pt, unsigned int idx) +{ + unsigned int *pt_virt = phys_to_virt(pt); + + return *(pt_virt + idx); +} + +static void atomisp_set_pte(phys_addr_t pt, + unsigned int idx, unsigned int pte) +{ + unsigned int *pt_virt = phys_to_virt(pt); + *(pt_virt + idx) = pte; +} + +static void *isp_pt_phys_to_virt(phys_addr_t phys) +{ + return phys_to_virt(phys); +} + +static phys_addr_t isp_pte_to_pgaddr(struct isp_mmu *mmu, + unsigned int pte) +{ + return mmu->driver->pte_to_phys(mmu, pte); +} + +static unsigned int isp_pgaddr_to_pte_valid(struct isp_mmu *mmu, + phys_addr_t phys) +{ + unsigned int pte = mmu->driver->phys_to_pte(mmu, phys); + + return (unsigned int)(pte | ISP_PTE_VALID_MASK(mmu)); +} + +/* + * allocate a uncacheable page table. + * return physical address. + */ +static phys_addr_t alloc_page_table(struct isp_mmu *mmu) +{ + int i; + phys_addr_t page; + void *virt; + + virt = (void *)__get_free_page(GFP_KERNEL | GFP_DMA32); + + if (!virt) + return (phys_addr_t)NULL_PAGE; + + /* + * we need a uncacheable page table. + */ +#ifdef CONFIG_X86 + set_memory_uc((unsigned long)virt, 1); +#endif + + page = virt_to_phys(virt); + + for (i = 0; i < 1024; i++) { + /* NEED CHECK */ + atomisp_set_pte(page, i, mmu->driver->null_pte); + } + + return page; +} + +static void free_page_table(struct isp_mmu *mmu, phys_addr_t page) +{ + void *virt; + + page &= ISP_PAGE_MASK; + /* + * reset the page to write back before free + */ + virt = phys_to_virt(page); + +#ifdef CONFIG_X86 + set_memory_wb((unsigned long)virt, 1); +#endif + + free_page((unsigned long)virt); +} + +static void mmu_remap_error(struct isp_mmu *mmu, + phys_addr_t l1_pt, unsigned int l1_idx, + phys_addr_t l2_pt, unsigned int l2_idx, + unsigned int isp_virt, phys_addr_t old_phys, + phys_addr_t new_phys) +{ + dev_err(atomisp_dev, "address remap:\n\n" + "\tL1 PT: virt = %p, phys = 0x%llx, idx = %d\n" + "\tL2 PT: virt = %p, phys = 0x%llx, idx = %d\n" + "\told: isp_virt = 0x%x, phys = 0x%llx\n" + "\tnew: isp_virt = 0x%x, phys = 0x%llx\n", + isp_pt_phys_to_virt(l1_pt), + (u64)l1_pt, l1_idx, + isp_pt_phys_to_virt(l2_pt), + (u64)l2_pt, l2_idx, isp_virt, + (u64)old_phys, isp_virt, + (u64)new_phys); +} + +static void mmu_unmap_l2_pte_error(struct isp_mmu *mmu, + phys_addr_t l1_pt, unsigned int l1_idx, + phys_addr_t l2_pt, unsigned int l2_idx, + unsigned int isp_virt, unsigned int pte) +{ + dev_err(atomisp_dev, "unmap invalid L2 pte:\n\n" + "\tL1 PT: virt = %p, phys = 0x%llx, idx = %d\n" + "\tL2 PT: virt = %p, phys = 0x%llx, idx = %d\n" + "\tisp_virt = 0x%x, pte(page phys) = 0x%x\n", + isp_pt_phys_to_virt(l1_pt), + (u64)l1_pt, l1_idx, + isp_pt_phys_to_virt(l2_pt), + (u64)l2_pt, l2_idx, isp_virt, + pte); +} + +static void mmu_unmap_l1_pte_error(struct isp_mmu *mmu, + phys_addr_t l1_pt, unsigned int l1_idx, + unsigned int isp_virt, unsigned int pte) +{ + dev_err(atomisp_dev, "unmap invalid L1 pte (L2 PT):\n\n" + "\tL1 PT: virt = %p, phys = 0x%llx, idx = %d\n" + "\tisp_virt = 0x%x, l1_pte(L2 PT) = 0x%x\n", + isp_pt_phys_to_virt(l1_pt), + (u64)l1_pt, l1_idx, (unsigned int)isp_virt, + pte); +} + +static void mmu_unmap_l1_pt_error(struct isp_mmu *mmu, unsigned int pte) +{ + dev_err(atomisp_dev, "unmap invalid L1PT:\n\n" + "L1PT = 0x%x\n", (unsigned int)pte); +} + +/* + * Update L2 page table according to isp virtual address and page physical + * address + */ +static int mmu_l2_map(struct isp_mmu *mmu, phys_addr_t l1_pt, + unsigned int l1_idx, phys_addr_t l2_pt, + unsigned int start, unsigned int end, phys_addr_t phys) +{ + unsigned int ptr; + unsigned int idx; + unsigned int pte; + + l2_pt &= ISP_PAGE_MASK; + + start = start & ISP_PAGE_MASK; + end = ISP_PAGE_ALIGN(end); + phys &= ISP_PAGE_MASK; + + ptr = start; + do { + idx = ISP_PTR_TO_L2_IDX(ptr); + + pte = atomisp_get_pte(l2_pt, idx); + + if (ISP_PTE_VALID(mmu, pte)) { + mmu_remap_error(mmu, l1_pt, l1_idx, + l2_pt, idx, ptr, pte, phys); + + /* free all mapped pages */ + free_mmu_map(mmu, start, ptr); + + return -EINVAL; + } + + pte = isp_pgaddr_to_pte_valid(mmu, phys); + + atomisp_set_pte(l2_pt, idx, pte); + mmu->l2_pgt_refcount[l1_idx]++; + ptr += (1U << ISP_L2PT_OFFSET); + phys += (1U << ISP_L2PT_OFFSET); + } while (ptr < end && idx < ISP_L2PT_PTES - 1); + + return 0; +} + +/* + * Update L1 page table according to isp virtual address and page physical + * address + */ +static int mmu_l1_map(struct isp_mmu *mmu, phys_addr_t l1_pt, + unsigned int start, unsigned int end, + phys_addr_t phys) +{ + phys_addr_t l2_pt; + unsigned int ptr, l1_aligned; + unsigned int idx; + unsigned int l2_pte; + int ret; + + l1_pt &= ISP_PAGE_MASK; + + start = start & ISP_PAGE_MASK; + end = ISP_PAGE_ALIGN(end); + phys &= ISP_PAGE_MASK; + + ptr = start; + do { + idx = ISP_PTR_TO_L1_IDX(ptr); + + l2_pte = atomisp_get_pte(l1_pt, idx); + + if (!ISP_PTE_VALID(mmu, l2_pte)) { + l2_pt = alloc_page_table(mmu); + if (l2_pt == NULL_PAGE) { + dev_err(atomisp_dev, + "alloc page table fail.\n"); + + /* free all mapped pages */ + free_mmu_map(mmu, start, ptr); + + return -ENOMEM; + } + + l2_pte = isp_pgaddr_to_pte_valid(mmu, l2_pt); + + atomisp_set_pte(l1_pt, idx, l2_pte); + mmu->l2_pgt_refcount[idx] = 0; + } + + l2_pt = isp_pte_to_pgaddr(mmu, l2_pte); + + l1_aligned = (ptr & ISP_PAGE_MASK) + (1U << ISP_L1PT_OFFSET); + + if (l1_aligned < end) { + ret = mmu_l2_map(mmu, l1_pt, idx, + l2_pt, ptr, l1_aligned, phys); + phys += (l1_aligned - ptr); + ptr = l1_aligned; + } else { + ret = mmu_l2_map(mmu, l1_pt, idx, + l2_pt, ptr, end, phys); + phys += (end - ptr); + ptr = end; + } + + if (ret) { + dev_err(atomisp_dev, "setup mapping in L2PT fail.\n"); + + /* free all mapped pages */ + free_mmu_map(mmu, start, ptr); + + return -EINVAL; + } + } while (ptr < end && idx < ISP_L1PT_PTES); + + return 0; +} + +/* + * Update page table according to isp virtual address and page physical + * address + */ +static int mmu_map(struct isp_mmu *mmu, unsigned int isp_virt, + phys_addr_t phys, unsigned int pgnr) +{ + unsigned int start, end; + phys_addr_t l1_pt; + int ret; + + mutex_lock(&mmu->pt_mutex); + if (!ISP_PTE_VALID(mmu, mmu->l1_pte)) { + /* + * allocate 1 new page for L1 page table + */ + l1_pt = alloc_page_table(mmu); + if (l1_pt == NULL_PAGE) { + dev_err(atomisp_dev, "alloc page table fail.\n"); + mutex_unlock(&mmu->pt_mutex); + return -ENOMEM; + } + + /* + * setup L1 page table physical addr to MMU + */ + mmu->base_address = l1_pt; + mmu->l1_pte = isp_pgaddr_to_pte_valid(mmu, l1_pt); + memset(mmu->l2_pgt_refcount, 0, sizeof(int) * ISP_L1PT_PTES); + } + + l1_pt = isp_pte_to_pgaddr(mmu, mmu->l1_pte); + + start = (isp_virt) & ISP_PAGE_MASK; + end = start + (pgnr << ISP_PAGE_OFFSET); + phys &= ISP_PAGE_MASK; + + ret = mmu_l1_map(mmu, l1_pt, start, end, phys); + + if (ret) + dev_err(atomisp_dev, "setup mapping in L1PT fail.\n"); + + mutex_unlock(&mmu->pt_mutex); + return ret; +} + +/* + * Free L2 page table according to isp virtual address and page physical + * address + */ +static void mmu_l2_unmap(struct isp_mmu *mmu, phys_addr_t l1_pt, + unsigned int l1_idx, phys_addr_t l2_pt, + unsigned int start, unsigned int end) +{ + unsigned int ptr; + unsigned int idx; + unsigned int pte; + + l2_pt &= ISP_PAGE_MASK; + + start = start & ISP_PAGE_MASK; + end = ISP_PAGE_ALIGN(end); + + ptr = start; + do { + idx = ISP_PTR_TO_L2_IDX(ptr); + + pte = atomisp_get_pte(l2_pt, idx); + + if (!ISP_PTE_VALID(mmu, pte)) + mmu_unmap_l2_pte_error(mmu, l1_pt, l1_idx, + l2_pt, idx, ptr, pte); + + atomisp_set_pte(l2_pt, idx, mmu->driver->null_pte); + mmu->l2_pgt_refcount[l1_idx]--; + ptr += (1U << ISP_L2PT_OFFSET); + } while (ptr < end && idx < ISP_L2PT_PTES - 1); + + if (mmu->l2_pgt_refcount[l1_idx] == 0) { + free_page_table(mmu, l2_pt); + atomisp_set_pte(l1_pt, l1_idx, mmu->driver->null_pte); + } +} + +/* + * Free L1 page table according to isp virtual address and page physical + * address + */ +static void mmu_l1_unmap(struct isp_mmu *mmu, phys_addr_t l1_pt, + unsigned int start, unsigned int end) +{ + phys_addr_t l2_pt; + unsigned int ptr, l1_aligned; + unsigned int idx; + unsigned int l2_pte; + + l1_pt &= ISP_PAGE_MASK; + + start = start & ISP_PAGE_MASK; + end = ISP_PAGE_ALIGN(end); + + ptr = start; + do { + idx = ISP_PTR_TO_L1_IDX(ptr); + + l2_pte = atomisp_get_pte(l1_pt, idx); + + if (!ISP_PTE_VALID(mmu, l2_pte)) { + mmu_unmap_l1_pte_error(mmu, l1_pt, idx, ptr, l2_pte); + continue; + } + + l2_pt = isp_pte_to_pgaddr(mmu, l2_pte); + + l1_aligned = (ptr & ISP_PAGE_MASK) + (1U << ISP_L1PT_OFFSET); + + if (l1_aligned < end) { + mmu_l2_unmap(mmu, l1_pt, idx, l2_pt, ptr, l1_aligned); + ptr = l1_aligned; + } else { + mmu_l2_unmap(mmu, l1_pt, idx, l2_pt, ptr, end); + ptr = end; + } + /* + * use the same L2 page next time, so we don't + * need to invalidate and free this PT. + */ + /* atomisp_set_pte(l1_pt, idx, NULL_PTE); */ + } while (ptr < end && idx < ISP_L1PT_PTES); +} + +/* + * Free page table according to isp virtual address and page physical + * address + */ +static void mmu_unmap(struct isp_mmu *mmu, unsigned int isp_virt, + unsigned int pgnr) +{ + unsigned int start, end; + phys_addr_t l1_pt; + + mutex_lock(&mmu->pt_mutex); + if (!ISP_PTE_VALID(mmu, mmu->l1_pte)) { + mmu_unmap_l1_pt_error(mmu, mmu->l1_pte); + mutex_unlock(&mmu->pt_mutex); + return; + } + + l1_pt = isp_pte_to_pgaddr(mmu, mmu->l1_pte); + + start = (isp_virt) & ISP_PAGE_MASK; + end = start + (pgnr << ISP_PAGE_OFFSET); + + mmu_l1_unmap(mmu, l1_pt, start, end); + mutex_unlock(&mmu->pt_mutex); +} + +/* + * Free page tables according to isp start virtual address and end virtual + * address. + */ +static void free_mmu_map(struct isp_mmu *mmu, unsigned int start_isp_virt, + unsigned int end_isp_virt) +{ + unsigned int pgnr; + unsigned int start, end; + + start = (start_isp_virt) & ISP_PAGE_MASK; + end = (end_isp_virt) & ISP_PAGE_MASK; + pgnr = (end - start) >> ISP_PAGE_OFFSET; + mmu_unmap(mmu, start, pgnr); +} + +int isp_mmu_map(struct isp_mmu *mmu, unsigned int isp_virt, + phys_addr_t phys, unsigned int pgnr) +{ + return mmu_map(mmu, isp_virt, phys, pgnr); +} + +void isp_mmu_unmap(struct isp_mmu *mmu, unsigned int isp_virt, + unsigned int pgnr) +{ + mmu_unmap(mmu, isp_virt, pgnr); +} + +static void isp_mmu_flush_tlb_range_default(struct isp_mmu *mmu, + unsigned int start, + unsigned int size) +{ + isp_mmu_flush_tlb(mmu); +} + +/*MMU init for internal structure*/ +int isp_mmu_init(struct isp_mmu *mmu, struct isp_mmu_client *driver) +{ + if (!mmu) /* error */ + return -EINVAL; + if (!driver) /* error */ + return -EINVAL; + + if (!driver->name) + dev_warn(atomisp_dev, "NULL name for MMU driver...\n"); + + mmu->driver = driver; + + if (!driver->tlb_flush_all) { + dev_err(atomisp_dev, "tlb_flush_all operation not provided.\n"); + return -EINVAL; + } + + if (!driver->tlb_flush_range) + driver->tlb_flush_range = isp_mmu_flush_tlb_range_default; + + if (!driver->pte_valid_mask) { + dev_err(atomisp_dev, "PTE_MASK is missing from mmu driver\n"); + return -EINVAL; + } + + mmu->l1_pte = driver->null_pte; + + mutex_init(&mmu->pt_mutex); + + return 0; +} + +/*Free L1 and L2 page table*/ +void isp_mmu_exit(struct isp_mmu *mmu) +{ + unsigned int idx; + unsigned int pte; + phys_addr_t l1_pt, l2_pt; + + if (!mmu) + return; + + if (!ISP_PTE_VALID(mmu, mmu->l1_pte)) { + dev_warn(atomisp_dev, "invalid L1PT: pte = 0x%x\n", + (unsigned int)mmu->l1_pte); + return; + } + + l1_pt = isp_pte_to_pgaddr(mmu, mmu->l1_pte); + + for (idx = 0; idx < ISP_L1PT_PTES; idx++) { + pte = atomisp_get_pte(l1_pt, idx); + + if (ISP_PTE_VALID(mmu, pte)) { + l2_pt = isp_pte_to_pgaddr(mmu, pte); + + free_page_table(mmu, l2_pt); + } + } + + free_page_table(mmu, l1_pt); +} diff --git a/drivers/staging/media/atomisp/pci/mmu/sh_mmu_mrfld.c b/drivers/staging/media/atomisp/pci/mmu/sh_mmu_mrfld.c new file mode 100644 index 000000000..0fbb361f5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/mmu/sh_mmu_mrfld.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Merrifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2012 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#include "type_support.h" +#include "mmu/isp_mmu.h" +#include "mmu/sh_mmu_mrfld.h" +#include "atomisp_compat.h" + +#define MERR_VALID_PTE_MASK 0x80000000 + +/* + * include SH header file here + */ + +static unsigned int sh_phys_to_pte(struct isp_mmu *mmu, + phys_addr_t phys) +{ + return phys >> ISP_PAGE_OFFSET; +} + +static phys_addr_t sh_pte_to_phys(struct isp_mmu *mmu, + unsigned int pte) +{ + unsigned int mask = mmu->driver->pte_valid_mask; + + return (phys_addr_t)((pte & ~mask) << ISP_PAGE_OFFSET); +} + +static unsigned int sh_get_pd_base(struct isp_mmu *mmu, + phys_addr_t phys) +{ + unsigned int pte = sh_phys_to_pte(mmu, phys); + + return HOST_ADDRESS(pte); +} + +/* + * callback to flush tlb. + * + * tlb_flush_range will at least flush TLBs containing + * address mapping from addr to addr + size. + * + * tlb_flush_all will flush all TLBs. + * + * tlb_flush_all is must be provided. if tlb_flush_range is + * not valid, it will set to tlb_flush_all by default. + */ +static void sh_tlb_flush(struct isp_mmu *mmu) +{ + ia_css_mmu_invalidate_cache(); +} + +struct isp_mmu_client sh_mmu_mrfld = { + .name = "Silicon Hive ISP3000 MMU", + .pte_valid_mask = MERR_VALID_PTE_MASK, + .null_pte = ~MERR_VALID_PTE_MASK, + .get_pd_base = sh_get_pd_base, + .tlb_flush_all = sh_tlb_flush, + .phys_to_pte = sh_phys_to_pte, + .pte_to_phys = sh_pte_to_phys, +}; diff --git a/drivers/staging/media/atomisp/pci/mmu_defs.h b/drivers/staging/media/atomisp/pci/mmu_defs.h new file mode 100644 index 000000000..03cfb5833 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/mmu_defs.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _mmu_defs_h +#define _mmu_defs_h + +#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0 +#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1 + +#define _HRT_MMU_REG_ALIGN 4 + +#endif /* _mmu_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/runtime/binary/interface/ia_css_binary.h b/drivers/staging/media/atomisp/pci/runtime/binary/interface/ia_css_binary.h new file mode 100644 index 000000000..9935ac860 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/binary/interface/ia_css_binary.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef _IA_CSS_BINARY_H_ +#define _IA_CSS_BINARY_H_ + +#include +#include "ia_css_types.h" +#include "ia_css_err.h" +#include "ia_css_stream_format.h" +#include "ia_css_stream_public.h" +#include "ia_css_frame_public.h" +#include "sh_css_metrics.h" +#include "isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_types.h" + +/* The binary mode is used in pre-processor expressions so we cannot + * use an enum here. */ +#define IA_CSS_BINARY_MODE_COPY 0 +#define IA_CSS_BINARY_MODE_PREVIEW 1 +#define IA_CSS_BINARY_MODE_PRIMARY 2 +#define IA_CSS_BINARY_MODE_VIDEO 3 +#define IA_CSS_BINARY_MODE_PRE_ISP 4 +#define IA_CSS_BINARY_MODE_GDC 5 +#define IA_CSS_BINARY_MODE_POST_ISP 6 +#define IA_CSS_BINARY_MODE_ANR 7 +#define IA_CSS_BINARY_MODE_CAPTURE_PP 8 +#define IA_CSS_BINARY_MODE_VF_PP 9 +#define IA_CSS_BINARY_MODE_PRE_DE 10 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE0 11 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE1 12 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE2 13 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE3 14 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE4 15 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE5 16 +#define IA_CSS_BINARY_NUM_MODES 17 + +#define MAX_NUM_PRIMARY_STAGES 6 +#define NUM_PRIMARY_HQ_STAGES 6 /* number of primary stages for ISP2.6.1 high quality pipe */ +#define NUM_PRIMARY_STAGES 1 /* number of primary satges for ISP1/ISP2.2 pipe */ + +/* Indicate where binaries can read input from */ +#define IA_CSS_BINARY_INPUT_SENSOR 0 +#define IA_CSS_BINARY_INPUT_MEMORY 1 +#define IA_CSS_BINARY_INPUT_VARIABLE 2 + +/* Should be included without the path. + However, that requires adding the path to numerous makefiles + that have nothing to do with isp parameters. + */ +#include "runtime/isp_param/interface/ia_css_isp_param_types.h" + +/* now these ports only include output ports but not vf output ports */ +enum { + IA_CSS_BINARY_OUTPUT_PORT_0 = 0, + IA_CSS_BINARY_OUTPUT_PORT_1 = 1, + IA_CSS_BINARY_MAX_OUTPUT_PORTS = 2 +}; + +struct ia_css_cas_binary_descr { + unsigned int num_stage; + unsigned int num_output_stage; + struct ia_css_frame_info *in_info; + struct ia_css_frame_info *internal_out_info; + struct ia_css_frame_info *out_info; + struct ia_css_frame_info *vf_info; + bool *is_output_stage; +}; + +struct ia_css_binary_descr { + int mode; + bool online; + bool continuous; + bool striped; + bool two_ppc; + bool enable_yuv_ds; + bool enable_high_speed; + bool enable_dvs_6axis; + bool enable_reduced_pipe; + bool enable_dz; + bool enable_xnr; + bool enable_fractional_ds; + bool enable_dpc; + + /* ISP2401 */ + bool enable_tnr; + + bool enable_capture_pp_bli; + struct ia_css_resolution dvs_env; + enum atomisp_input_format stream_format; + struct ia_css_frame_info *in_info; /* the info of the input-frame with the + ISP required resolution. */ + struct ia_css_frame_info *bds_out_info; + struct ia_css_frame_info *out_info[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame_info *vf_info; + unsigned int isp_pipe_version; + unsigned int required_bds_factor; + int stream_config_left_padding; +}; + +struct ia_css_binary { + const struct ia_css_binary_xinfo *info; + enum atomisp_input_format input_format; + struct ia_css_frame_info in_frame_info; + struct ia_css_frame_info internal_frame_info; + struct ia_css_frame_info out_frame_info[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_resolution effective_in_frame_res; + struct ia_css_frame_info vf_frame_info; + int input_buf_vectors; + int deci_factor_log2; + int vf_downscale_log2; + int s3atbl_width; + int s3atbl_height; + int s3atbl_isp_width; + int s3atbl_isp_height; + unsigned int morph_tbl_width; + unsigned int morph_tbl_aligned_width; + unsigned int morph_tbl_height; + int sctbl_width_per_color; + int sctbl_aligned_width_per_color; + int sctbl_height; + struct ia_css_sdis_info dis; + struct ia_css_resolution dvs_envelope; + bool online; + unsigned int uds_xc; + unsigned int uds_yc; + unsigned int left_padding; + struct sh_css_binary_metrics metrics; + struct ia_css_isp_param_host_segments mem_params; + struct ia_css_isp_param_css_segments css_params; +}; + +#define IA_CSS_BINARY_DEFAULT_SETTINGS { \ + .input_format = ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY, \ + .in_frame_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + .internal_frame_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + .out_frame_info = {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + .vf_frame_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ +} + +int +ia_css_binary_init_infos(void); + +int +ia_css_binary_uninit(void); + +int +ia_css_binary_fill_info(const struct ia_css_binary_xinfo *xinfo, + bool online, + bool two_ppc, + enum atomisp_input_format stream_format, + const struct ia_css_frame_info *in_info, + const struct ia_css_frame_info *bds_out_info, + const struct ia_css_frame_info *out_info[], + const struct ia_css_frame_info *vf_info, + struct ia_css_binary *binary, + struct ia_css_resolution *dvs_env, + int stream_config_left_padding, + bool accelerator); + +int +ia_css_binary_find(struct ia_css_binary_descr *descr, + struct ia_css_binary *binary); + +/* @brief Get the shading information of the specified shading correction type. + * + * @param[in] binary: The isp binary which has the shading correction. + * @param[in] type: The shading correction type. + * @param[in] required_bds_factor: The bayer downscaling factor required in the pipe. + * @param[in] stream_config: The stream configuration. + * @param[out] shading_info: The shading information. + * The shading information necessary as API is stored in the shading_info. + * The driver needs to get this information to generate + * the shading table directly required from ISP. + * @param[out] pipe_config: The pipe configuration. + * The shading information related to ISP (but, not necessary as API) is stored in the pipe_config. + * @return 0 or error code upon error. + * + */ +int +ia_css_binary_get_shading_info(const struct ia_css_binary *binary, + enum ia_css_shading_correction_type type, + unsigned int required_bds_factor, + const struct ia_css_stream_config *stream_config, + struct ia_css_shading_info *shading_info, + struct ia_css_pipe_config *pipe_config); + +int +ia_css_binary_3a_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe); + +void +ia_css_binary_dvs_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe); + +void +ia_css_binary_dvs_stat_grid_info( + const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe); + +unsigned +ia_css_binary_max_vf_width(void); + +void +ia_css_binary_destroy_isp_parameters(struct ia_css_binary *binary); + +void +ia_css_binary_get_isp_binaries(struct ia_css_binary_xinfo **binaries, + uint32_t *num_isp_binaries); + +#endif /* _IA_CSS_BINARY_H_ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/binary/src/binary.c b/drivers/staging/media/atomisp/pci/runtime/binary/src/binary.c new file mode 100644 index 000000000..768da86b8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/binary/src/binary.c @@ -0,0 +1,1361 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include +#include /* HR_GDC_N */ + +#include "hmm.h" + +#include "isp.h" /* ISP_VEC_NELEMS */ + +#include "ia_css_binary.h" +#include "ia_css_debug.h" +#include "ia_css_util.h" +#include "ia_css_isp_param.h" +#include "sh_css_internal.h" +#include "sh_css_sp.h" +#include "sh_css_firmware.h" +#include "sh_css_defs.h" +#include "sh_css_legacy.h" + +#include "atomisp_internal.h" + +#include "vf/vf_1.0/ia_css_vf.host.h" +#include "sc/sc_1.0/ia_css_sc.host.h" +#include "sdis/sdis_1.0/ia_css_sdis.host.h" +#include "fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h" /* FRAC_ACC */ + +#include "camera/pipe/interface/ia_css_pipe_binarydesc.h" + +#include "assert_support.h" + +#define IMPLIES(a, b) (!(a) || (b)) /* A => B */ + +static struct ia_css_binary_xinfo *all_binaries; /* ISP binaries only (no SP) */ +static struct ia_css_binary_xinfo + *binary_infos[IA_CSS_BINARY_NUM_MODES] = { NULL, }; + +static void +ia_css_binary_dvs_env(const struct ia_css_binary_info *info, + const struct ia_css_resolution *dvs_env, + struct ia_css_resolution *binary_dvs_env) +{ + if (info->enable.dvs_envelope) { + assert(dvs_env); + binary_dvs_env->width = max(dvs_env->width, SH_CSS_MIN_DVS_ENVELOPE); + binary_dvs_env->height = max(dvs_env->height, SH_CSS_MIN_DVS_ENVELOPE); + } +} + +static void +ia_css_binary_internal_res(const struct ia_css_frame_info *in_info, + const struct ia_css_frame_info *bds_out_info, + const struct ia_css_frame_info *out_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_binary_info *info, + struct ia_css_resolution *internal_res) +{ + unsigned int isp_tmp_internal_width = 0, + isp_tmp_internal_height = 0; + bool binary_supports_yuv_ds = info->enable.ds & 2; + struct ia_css_resolution binary_dvs_env; + + binary_dvs_env.width = 0; + binary_dvs_env.height = 0; + ia_css_binary_dvs_env(info, dvs_env, &binary_dvs_env); + + if (binary_supports_yuv_ds) { + if (in_info) { + isp_tmp_internal_width = in_info->res.width + + info->pipeline.left_cropping + binary_dvs_env.width; + isp_tmp_internal_height = in_info->res.height + + info->pipeline.top_cropping + binary_dvs_env.height; + } + } else if ((bds_out_info) && (out_info) && + /* TODO: hack to make video_us case work. this should be reverted after + a nice solution in ISP */ + (bds_out_info->res.width >= out_info->res.width)) { + isp_tmp_internal_width = bds_out_info->padded_width; + isp_tmp_internal_height = bds_out_info->res.height; + } else { + if (out_info) { + isp_tmp_internal_width = out_info->padded_width; + isp_tmp_internal_height = out_info->res.height; + } + } + + /* We first calculate the resolutions used by the ISP. After that, + * we use those resolutions to compute sizes for tables etc. */ + internal_res->width = __ISP_INTERNAL_WIDTH(isp_tmp_internal_width, + (int)binary_dvs_env.width, + info->pipeline.left_cropping, info->pipeline.mode, + info->pipeline.c_subsampling, + info->output.num_chunks, info->pipeline.pipelining); + internal_res->height = __ISP_INTERNAL_HEIGHT(isp_tmp_internal_height, + info->pipeline.top_cropping, + binary_dvs_env.height); +} + +/* Computation results of the origin coordinate of bayer on the shading table. */ +struct sh_css_shading_table_bayer_origin_compute_results { + u32 bayer_scale_hor_ratio_in; /* Horizontal ratio (in) of bayer scaling. */ + u32 bayer_scale_hor_ratio_out; /* Horizontal ratio (out) of bayer scaling. */ + u32 bayer_scale_ver_ratio_in; /* Vertical ratio (in) of bayer scaling. */ + u32 bayer_scale_ver_ratio_out; /* Vertical ratio (out) of bayer scaling. */ + u32 sc_bayer_origin_x_bqs_on_shading_table; /* X coordinate (in bqs) of bayer origin on shading table. */ + u32 sc_bayer_origin_y_bqs_on_shading_table; /* Y coordinate (in bqs) of bayer origin on shading table. */ +}; + +/* Get the requirements for the shading correction. */ +static int +ia_css_binary_compute_shading_table_bayer_origin( + const struct ia_css_binary *binary, /* [in] */ + unsigned int required_bds_factor, /* [in] */ + const struct ia_css_stream_config *stream_config, /* [in] */ + struct sh_css_shading_table_bayer_origin_compute_results *res) /* [out] */ +{ + int err; + + /* Rational fraction of the fixed bayer downscaling factor. */ + struct u32_fract bds; + + /* Left padding set by InputFormatter. */ + unsigned int left_padding_bqs; /* in bqs */ + + /* Flag for the NEED_BDS_FACTOR_2_00 macro defined in isp kernels. */ + unsigned int need_bds_factor_2_00; + + /* Left padding adjusted inside the isp. */ + unsigned int left_padding_adjusted_bqs; /* in bqs */ + + /* Bad pixels caused by filters. + NxN-filter (before/after bayer scaling) moves the image position + to right/bottom directions by a few pixels. + It causes bad pixels at left/top sides, + and effective bayer size decreases. */ + unsigned int bad_bqs_on_left_before_bs; /* in bqs */ + unsigned int bad_bqs_on_left_after_bs; /* in bqs */ + unsigned int bad_bqs_on_top_before_bs; /* in bqs */ + unsigned int bad_bqs_on_top_after_bs; /* in bqs */ + + /* Get the rational fraction of bayer downscaling factor. */ + err = sh_css_bds_factor_get_fract(required_bds_factor, &bds); + if (err) + return err; + + /* Set the left padding set by InputFormatter. (ifmtr.c) */ + if (stream_config->left_padding == -1) + left_padding_bqs = _ISP_BQS(binary->left_padding); + else + left_padding_bqs = (unsigned int)((int)ISP_VEC_NELEMS + - _ISP_BQS(stream_config->left_padding)); + + /* Set the left padding adjusted inside the isp. + When bds_factor 2.00 is needed, some padding is added to left_padding + inside the isp, before bayer downscaling. (raw.isp.c) + (Hopefully, left_crop/left_padding/top_crop should be defined in css + appropriately, depending on bds_factor.) + */ + need_bds_factor_2_00 = ((binary->info->sp.bds.supported_bds_factors & + (PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_2_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_2_50) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_3_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_4_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_4_50) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_5_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_6_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_8_00))) != 0); + + if (need_bds_factor_2_00 && binary->info->sp.pipeline.left_cropping > 0) + left_padding_adjusted_bqs = left_padding_bqs + ISP_VEC_NELEMS; + else + left_padding_adjusted_bqs = left_padding_bqs; + + /* Currently, the bad pixel caused by filters before bayer scaling + is NOT considered, because the bad pixel is subtle. + When some large filter is used in the future, + we need to consider the bad pixel. + + Currently, when bds_factor isn't 1.00, 3x3 anti-alias filter is applied + to each color plane(Gr/R/B/Gb) before bayer downscaling. + This filter moves each color plane to right/bottom directions + by 1 pixel at the most, depending on downscaling factor. + */ + bad_bqs_on_left_before_bs = 0; + bad_bqs_on_top_before_bs = 0; + + /* Currently, the bad pixel caused by filters after bayer scaling + is NOT considered, because the bad pixel is subtle. + When some large filter is used in the future, + we need to consider the bad pixel. + + Currently, when DPC&BNR is processed between bayer scaling and + shading correction, DPC&BNR moves each color plane to + right/bottom directions by 1 pixel. + */ + bad_bqs_on_left_after_bs = 0; + bad_bqs_on_top_after_bs = 0; + + /* Calculate the origin of bayer (real sensor data area) + located on the shading table during the shading correction. */ + res->sc_bayer_origin_x_bqs_on_shading_table = + ((left_padding_adjusted_bqs + bad_bqs_on_left_before_bs) + * bds.denominator + bds.numerator / 2) / bds.numerator + + bad_bqs_on_left_after_bs; + /* "+ bds.numerator / 2": rounding for division by bds.numerator */ + res->sc_bayer_origin_y_bqs_on_shading_table = + (bad_bqs_on_top_before_bs * bds.denominator + bds.numerator / 2) / bds.numerator + + bad_bqs_on_top_after_bs; + /* "+ bds.numerator / 2": rounding for division by bds.numerator */ + + res->bayer_scale_hor_ratio_in = bds.numerator; + res->bayer_scale_hor_ratio_out = bds.denominator; + res->bayer_scale_ver_ratio_in = bds.numerator; + res->bayer_scale_ver_ratio_out = bds.denominator; + + return err; +} + +/* Get the shading information of Shading Correction Type 1. */ +static int +binary_get_shading_info_type_1(const struct ia_css_binary *binary, /* [in] */ + unsigned int required_bds_factor, /* [in] */ + const struct ia_css_stream_config *stream_config, /* [in] */ + struct ia_css_shading_info *info) /* [out] */ +{ + int err; + struct sh_css_shading_table_bayer_origin_compute_results res; + + assert(binary); + assert(info); + + info->type = IA_CSS_SHADING_CORRECTION_TYPE_1; + + info->info.type_1.enable = binary->info->sp.enable.sc; + info->info.type_1.num_hor_grids = binary->sctbl_width_per_color; + info->info.type_1.num_ver_grids = binary->sctbl_height; + info->info.type_1.bqs_per_grid_cell = (1 << binary->deci_factor_log2); + + /* Initialize by default values. */ + info->info.type_1.bayer_scale_hor_ratio_in = 1; + info->info.type_1.bayer_scale_hor_ratio_out = 1; + info->info.type_1.bayer_scale_ver_ratio_in = 1; + info->info.type_1.bayer_scale_ver_ratio_out = 1; + info->info.type_1.sc_bayer_origin_x_bqs_on_shading_table = 0; + info->info.type_1.sc_bayer_origin_y_bqs_on_shading_table = 0; + + err = ia_css_binary_compute_shading_table_bayer_origin( + binary, + required_bds_factor, + stream_config, + &res); + if (err) + return err; + + info->info.type_1.bayer_scale_hor_ratio_in = res.bayer_scale_hor_ratio_in; + info->info.type_1.bayer_scale_hor_ratio_out = res.bayer_scale_hor_ratio_out; + info->info.type_1.bayer_scale_ver_ratio_in = res.bayer_scale_ver_ratio_in; + info->info.type_1.bayer_scale_ver_ratio_out = res.bayer_scale_ver_ratio_out; + info->info.type_1.sc_bayer_origin_x_bqs_on_shading_table = res.sc_bayer_origin_x_bqs_on_shading_table; + info->info.type_1.sc_bayer_origin_y_bqs_on_shading_table = res.sc_bayer_origin_y_bqs_on_shading_table; + + return err; +} + + +int +ia_css_binary_get_shading_info(const struct ia_css_binary *binary, /* [in] */ + enum ia_css_shading_correction_type type, /* [in] */ + unsigned int required_bds_factor, /* [in] */ + const struct ia_css_stream_config *stream_config, /* [in] */ + struct ia_css_shading_info *shading_info, /* [out] */ + struct ia_css_pipe_config *pipe_config) /* [out] */ +{ + int err; + + assert(binary); + assert(shading_info); + + IA_CSS_ENTER_PRIVATE("binary=%p, type=%d, required_bds_factor=%d, stream_config=%p", + binary, type, required_bds_factor, stream_config); + + if (type == IA_CSS_SHADING_CORRECTION_TYPE_1) + err = binary_get_shading_info_type_1(binary, + required_bds_factor, + stream_config, + shading_info); + else + err = -ENOTSUPP; + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static void sh_css_binary_common_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info) +{ + assert(binary); + assert(info); + + info->isp_in_width = binary->internal_frame_info.res.width; + info->isp_in_height = binary->internal_frame_info.res.height; + + info->vamem_type = IA_CSS_VAMEM_TYPE_2; +} + +void +ia_css_binary_dvs_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe) +{ + struct ia_css_dvs_grid_info *dvs_info; + + (void)pipe; + assert(binary); + assert(info); + + dvs_info = &info->dvs_grid.dvs_grid_info; + + /* for DIS, we use a division instead of a ceil_div. If this is smaller + * than the 3a grid size, it indicates that the outer values are not + * valid for DIS. + */ + dvs_info->enable = binary->info->sp.enable.dis; + dvs_info->width = binary->dis.grid.dim.width; + dvs_info->height = binary->dis.grid.dim.height; + dvs_info->aligned_width = binary->dis.grid.pad.width; + dvs_info->aligned_height = binary->dis.grid.pad.height; + dvs_info->bqs_per_grid_cell = 1 << binary->dis.deci_factor_log2; + dvs_info->num_hor_coefs = binary->dis.coef.dim.width; + dvs_info->num_ver_coefs = binary->dis.coef.dim.height; + + sh_css_binary_common_grid_info(binary, info); +} + +void +ia_css_binary_dvs_stat_grid_info( + const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe) +{ + (void)pipe; + sh_css_binary_common_grid_info(binary, info); + return; +} + +int +ia_css_binary_3a_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe) { + struct ia_css_3a_grid_info *s3a_info; + int err = 0; + + IA_CSS_ENTER_PRIVATE("binary=%p, info=%p, pipe=%p", + binary, info, pipe); + + assert(binary); + assert(info); + s3a_info = &info->s3a_grid; + + /* 3A statistics grid */ + s3a_info->enable = binary->info->sp.enable.s3a; + s3a_info->width = binary->s3atbl_width; + s3a_info->height = binary->s3atbl_height; + s3a_info->aligned_width = binary->s3atbl_isp_width; + s3a_info->aligned_height = binary->s3atbl_isp_height; + s3a_info->bqs_per_grid_cell = (1 << binary->deci_factor_log2); + s3a_info->deci_factor_log2 = binary->deci_factor_log2; + s3a_info->elem_bit_depth = SH_CSS_BAYER_BITS; + s3a_info->use_dmem = binary->info->sp.s3a.s3atbl_use_dmem; + s3a_info->has_histogram = 0; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static void +binary_init_pc_histogram(struct sh_css_pc_histogram *histo) +{ + assert(histo); + + histo->length = 0; + histo->run = NULL; + histo->stall = NULL; +} + +static void +binary_init_metrics(struct sh_css_binary_metrics *metrics, + const struct ia_css_binary_info *info) +{ + assert(metrics); + assert(info); + + metrics->mode = info->pipeline.mode; + metrics->id = info->id; + metrics->next = NULL; + binary_init_pc_histogram(&metrics->isp_histogram); + binary_init_pc_histogram(&metrics->sp_histogram); +} + +/* move to host part of output module */ +static bool +binary_supports_output_format(const struct ia_css_binary_xinfo *info, + enum ia_css_frame_format format) +{ + int i; + + assert(info); + + for (i = 0; i < info->num_output_formats; i++) { + if (info->output_formats[i] == format) + return true; + } + return false; +} + +static bool +binary_supports_vf_format(const struct ia_css_binary_xinfo *info, + enum ia_css_frame_format format) +{ + int i; + + assert(info); + + for (i = 0; i < info->num_vf_formats; i++) { + if (info->vf_formats[i] == format) + return true; + } + return false; +} + +/* move to host part of bds module */ +static bool +supports_bds_factor(u32 supported_factors, + uint32_t bds_factor) +{ + return ((supported_factors & PACK_BDS_FACTOR(bds_factor)) != 0); +} + +static int +binary_init_info(struct ia_css_binary_xinfo *info, unsigned int i, + bool *binary_found) { + const unsigned char *blob = sh_css_blob_info[i].blob; + unsigned int size = sh_css_blob_info[i].header.blob.size; + + if ((!info) || (!binary_found)) + return -EINVAL; + + *info = sh_css_blob_info[i].header.info.isp; + *binary_found = blob; + info->blob_index = i; + /* we don't have this binary, skip it */ + if (!size) + return 0; + + info->xmem_addr = sh_css_load_blob(blob, size); + if (!info->xmem_addr) + return -ENOMEM; + return 0; +} + +/* When binaries are put at the beginning, they will only + * be selected if no other primary matches. + */ +int +ia_css_binary_init_infos(void) { + unsigned int i; + unsigned int num_of_isp_binaries = sh_css_num_binaries - NUM_OF_SPS - NUM_OF_BLS; + + if (num_of_isp_binaries == 0) + return 0; + + all_binaries = kvmalloc(num_of_isp_binaries * sizeof(*all_binaries), + GFP_KERNEL); + if (!all_binaries) + return -ENOMEM; + + for (i = 0; i < num_of_isp_binaries; i++) + { + int ret; + struct ia_css_binary_xinfo *binary = &all_binaries[i]; + bool binary_found; + + ret = binary_init_info(binary, i, &binary_found); + if (ret) + return ret; + if (!binary_found) + continue; + /* Prepend new binary information */ + binary->next = binary_infos[binary->sp.pipeline.mode]; + binary_infos[binary->sp.pipeline.mode] = binary; + binary->blob = &sh_css_blob_info[i]; + binary->mem_offsets = sh_css_blob_info[i].mem_offsets; + } + return 0; +} + +int +ia_css_binary_uninit(void) { + unsigned int i; + struct ia_css_binary_xinfo *b; + + for (i = 0; i < IA_CSS_BINARY_NUM_MODES; i++) + { + for (b = binary_infos[i]; b; b = b->next) { + if (b->xmem_addr) + hmm_free(b->xmem_addr); + b->xmem_addr = mmgr_NULL; + } + binary_infos[i] = NULL; + } + kvfree(all_binaries); + return 0; +} + +/* @brief Compute decimation factor for 3A statistics and shading correction. + * + * @param[in] width Frame width in pixels. + * @param[in] height Frame height in pixels. + * @return Log2 of decimation factor (= grid cell size) in bayer quads. + */ +static int +binary_grid_deci_factor_log2(int width, int height) +{ + /* 3A/Shading decimation factor spcification (at August 2008) + * ------------------------------------------------------------------ + * [Image Width (BQ)] [Decimation Factor (BQ)] [Resulting grid cells] + * 1280 ?c 32 40 ?c + * 640 ?c 1279 16 40 ?c 80 + * ?c 639 8 ?c 80 + * ------------------------------------------------------------------ + */ + /* Maximum and minimum decimation factor by the specification */ +#define MAX_SPEC_DECI_FACT_LOG2 5 +#define MIN_SPEC_DECI_FACT_LOG2 3 + /* the smallest frame width in bayer quads when decimation factor (log2) is 5 or 4, by the specification */ +#define DECI_FACT_LOG2_5_SMALLEST_FRAME_WIDTH_BQ 1280 +#define DECI_FACT_LOG2_4_SMALLEST_FRAME_WIDTH_BQ 640 + + int smallest_factor; /* the smallest factor (log2) where the number of cells does not exceed the limitation */ + int spec_factor; /* the factor (log2) which satisfies the specification */ + + /* Currently supported maximum width and height are 5120(=80*64) and 3840(=60*64). */ + assert(ISP_BQ_GRID_WIDTH(width, + MAX_SPEC_DECI_FACT_LOG2) <= SH_CSS_MAX_BQ_GRID_WIDTH); + assert(ISP_BQ_GRID_HEIGHT(height, + MAX_SPEC_DECI_FACT_LOG2) <= SH_CSS_MAX_BQ_GRID_HEIGHT); + + /* Compute the smallest factor. */ + smallest_factor = MAX_SPEC_DECI_FACT_LOG2; + while (ISP_BQ_GRID_WIDTH(width, + smallest_factor - 1) <= SH_CSS_MAX_BQ_GRID_WIDTH && + ISP_BQ_GRID_HEIGHT(height, smallest_factor - 1) <= SH_CSS_MAX_BQ_GRID_HEIGHT + && smallest_factor > MIN_SPEC_DECI_FACT_LOG2) + smallest_factor--; + + /* Get the factor by the specification. */ + if (_ISP_BQS(width) >= DECI_FACT_LOG2_5_SMALLEST_FRAME_WIDTH_BQ) + spec_factor = 5; + else if (_ISP_BQS(width) >= DECI_FACT_LOG2_4_SMALLEST_FRAME_WIDTH_BQ) + spec_factor = 4; + else + spec_factor = 3; + + /* If smallest_factor is smaller than or equal to spec_factor, choose spec_factor to follow the specification. + If smallest_factor is larger than spec_factor, choose smallest_factor. + + ex. width=2560, height=1920 + smallest_factor=4, spec_factor=5 + smallest_factor < spec_factor -> return spec_factor + + ex. width=300, height=3000 + smallest_factor=5, spec_factor=3 + smallest_factor > spec_factor -> return smallest_factor + */ + return max(smallest_factor, spec_factor); + +#undef MAX_SPEC_DECI_FACT_LOG2 +#undef MIN_SPEC_DECI_FACT_LOG2 +#undef DECI_FACT_LOG2_5_SMALLEST_FRAME_WIDTH_BQ +#undef DECI_FACT_LOG2_4_SMALLEST_FRAME_WIDTH_BQ +} + +static int +binary_in_frame_padded_width(int in_frame_width, + int isp_internal_width, + int dvs_env_width, + int stream_config_left_padding, + int left_cropping, + bool need_scaling) +{ + int rval; + int nr_of_left_paddings; /* number of paddings pixels on the left of an image line */ + +#if defined(ISP2401) + /* the output image line of Input System 2401 does not have the left paddings */ + nr_of_left_paddings = 0; +#else + /* in other cases, the left padding pixels are always 128 */ + nr_of_left_paddings = 2 * ISP_VEC_NELEMS; +#endif + if (need_scaling) { + /* In SDV use-case, we need to match left-padding of + * primary and the video binary. */ + if (stream_config_left_padding != -1) { + /* Different than before, we do left&right padding. */ + rval = + CEIL_MUL(in_frame_width + nr_of_left_paddings, + 2 * ISP_VEC_NELEMS); + } else { + /* Different than before, we do left&right padding. */ + in_frame_width += dvs_env_width; + rval = + CEIL_MUL(in_frame_width + + (left_cropping ? nr_of_left_paddings : 0), + 2 * ISP_VEC_NELEMS); + } + } else { + rval = isp_internal_width; + } + + return rval; +} + +int +ia_css_binary_fill_info(const struct ia_css_binary_xinfo *xinfo, + bool online, + bool two_ppc, + enum atomisp_input_format stream_format, + const struct ia_css_frame_info *in_info, /* can be NULL */ + const struct ia_css_frame_info *bds_out_info, /* can be NULL */ + const struct ia_css_frame_info *out_info[], /* can be NULL */ + const struct ia_css_frame_info *vf_info, /* can be NULL */ + struct ia_css_binary *binary, + struct ia_css_resolution *dvs_env, + int stream_config_left_padding, + bool accelerator) { + const struct ia_css_binary_info *info = &xinfo->sp; + unsigned int dvs_env_width = 0, + dvs_env_height = 0, + vf_log_ds = 0, + s3a_log_deci = 0, + bits_per_pixel = 0, + /* Resolution at SC/3A/DIS kernel. */ + sc_3a_dis_width = 0, + /* Resolution at SC/3A/DIS kernel. */ + sc_3a_dis_padded_width = 0, + /* Resolution at SC/3A/DIS kernel. */ + sc_3a_dis_height = 0, + isp_internal_width = 0, + isp_internal_height = 0, + s3a_isp_width = 0; + + bool need_scaling = false; + struct ia_css_resolution binary_dvs_env, internal_res; + int err; + unsigned int i; + const struct ia_css_frame_info *bin_out_info = NULL; + + assert(info); + assert(binary); + + binary->info = xinfo; + if (!accelerator) + { + /* binary->css_params has been filled by accelerator itself. */ + err = ia_css_isp_param_allocate_isp_parameters( + &binary->mem_params, &binary->css_params, + &info->mem_initializers); + if (err) { + return err; + } + } + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + { + if (out_info[i] && (out_info[i]->res.width != 0)) { + bin_out_info = out_info[i]; + break; + } + } + if (in_info && bin_out_info) + { + need_scaling = (in_info->res.width != bin_out_info->res.width) || + (in_info->res.height != bin_out_info->res.height); + } + + /* binary_dvs_env has to be equal or larger than SH_CSS_MIN_DVS_ENVELOPE */ + binary_dvs_env.width = 0; + binary_dvs_env.height = 0; + ia_css_binary_dvs_env(info, dvs_env, &binary_dvs_env); + dvs_env_width = binary_dvs_env.width; + dvs_env_height = binary_dvs_env.height; + binary->dvs_envelope.width = dvs_env_width; + binary->dvs_envelope.height = dvs_env_height; + + /* internal resolution calculation */ + internal_res.width = 0; + internal_res.height = 0; + ia_css_binary_internal_res(in_info, bds_out_info, bin_out_info, dvs_env, + info, &internal_res); + isp_internal_width = internal_res.width; + isp_internal_height = internal_res.height; + + /* internal frame info */ + if (bin_out_info) /* { */ + binary->internal_frame_info.format = bin_out_info->format; + /* } */ + binary->internal_frame_info.res.width = isp_internal_width; + binary->internal_frame_info.padded_width = CEIL_MUL(isp_internal_width, 2 * ISP_VEC_NELEMS); + binary->internal_frame_info.res.height = isp_internal_height; + binary->internal_frame_info.raw_bit_depth = bits_per_pixel; + + if (in_info) + { + binary->effective_in_frame_res.width = in_info->res.width; + binary->effective_in_frame_res.height = in_info->res.height; + + bits_per_pixel = in_info->raw_bit_depth; + + /* input info */ + binary->in_frame_info.res.width = in_info->res.width + + info->pipeline.left_cropping; + binary->in_frame_info.res.height = in_info->res.height + + info->pipeline.top_cropping; + + binary->in_frame_info.res.width += dvs_env_width; + binary->in_frame_info.res.height += dvs_env_height; + + binary->in_frame_info.padded_width = + binary_in_frame_padded_width(in_info->res.width, + isp_internal_width, + dvs_env_width, + stream_config_left_padding, + info->pipeline.left_cropping, + need_scaling); + + binary->in_frame_info.format = in_info->format; + binary->in_frame_info.raw_bayer_order = in_info->raw_bayer_order; + binary->in_frame_info.crop_info = in_info->crop_info; + } + + if (online) + { + bits_per_pixel = ia_css_util_input_format_bpp( + stream_format, two_ppc); + } + binary->in_frame_info.raw_bit_depth = bits_per_pixel; + + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + { + if (out_info[i]) { + binary->out_frame_info[i].res.width = out_info[i]->res.width; + binary->out_frame_info[i].res.height = out_info[i]->res.height; + binary->out_frame_info[i].padded_width = out_info[i]->padded_width; + if (info->pipeline.mode == IA_CSS_BINARY_MODE_COPY) { + binary->out_frame_info[i].raw_bit_depth = bits_per_pixel; + } else { + /* Only relevant for RAW format. + * At the moment, all outputs are raw, 16 bit per pixel, except for copy. + * To do this cleanly, the binary should specify in its info + * the bit depth per output channel. + */ + binary->out_frame_info[i].raw_bit_depth = 16; + } + binary->out_frame_info[i].format = out_info[i]->format; + } + } + + if (vf_info && (vf_info->res.width != 0)) + { + err = ia_css_vf_configure(binary, bin_out_info, + (struct ia_css_frame_info *)vf_info, &vf_log_ds); + if (err) { + if (!accelerator) { + ia_css_isp_param_destroy_isp_parameters( + &binary->mem_params, + &binary->css_params); + } + return err; + } + } + binary->vf_downscale_log2 = vf_log_ds; + + binary->online = online; + binary->input_format = stream_format; + + /* viewfinder output info */ + if ((vf_info) && (vf_info->res.width != 0)) + { + unsigned int vf_out_vecs, vf_out_width, vf_out_height; + + binary->vf_frame_info.format = vf_info->format; + if (!bin_out_info) + return -EINVAL; + vf_out_vecs = __ISP_VF_OUTPUT_WIDTH_VECS(bin_out_info->padded_width, + vf_log_ds); + vf_out_width = _ISP_VF_OUTPUT_WIDTH(vf_out_vecs); + vf_out_height = _ISP_VF_OUTPUT_HEIGHT(bin_out_info->res.height, + vf_log_ds); + + /* For preview mode, output pin is used instead of vf. */ + if (info->pipeline.mode == IA_CSS_BINARY_MODE_PREVIEW) { + binary->out_frame_info[0].res.width = + (bin_out_info->res.width >> vf_log_ds); + binary->out_frame_info[0].padded_width = vf_out_width; + binary->out_frame_info[0].res.height = vf_out_height; + + binary->vf_frame_info.res.width = 0; + binary->vf_frame_info.padded_width = 0; + binary->vf_frame_info.res.height = 0; + } else { + /* we also store the raw downscaled width. This is + * used for digital zoom in preview to zoom only on + * the width that we actually want to keep, not on + * the aligned width. */ + binary->vf_frame_info.res.width = + (bin_out_info->res.width >> vf_log_ds); + binary->vf_frame_info.padded_width = vf_out_width; + binary->vf_frame_info.res.height = vf_out_height; + } + } else + { + binary->vf_frame_info.res.width = 0; + binary->vf_frame_info.padded_width = 0; + binary->vf_frame_info.res.height = 0; + } + + if (info->enable.ca_gdc) + { + binary->morph_tbl_width = + _ISP_MORPH_TABLE_WIDTH(isp_internal_width); + binary->morph_tbl_aligned_width = + _ISP_MORPH_TABLE_ALIGNED_WIDTH(isp_internal_width); + binary->morph_tbl_height = + _ISP_MORPH_TABLE_HEIGHT(isp_internal_height); + } else + { + binary->morph_tbl_width = 0; + binary->morph_tbl_aligned_width = 0; + binary->morph_tbl_height = 0; + } + + sc_3a_dis_width = binary->in_frame_info.res.width; + sc_3a_dis_padded_width = binary->in_frame_info.padded_width; + sc_3a_dis_height = binary->in_frame_info.res.height; + if (bds_out_info && in_info && + bds_out_info->res.width != in_info->res.width) + { + /* TODO: Next, "internal_frame_info" should be derived from + * bds_out. So this part will change once it is in place! */ + sc_3a_dis_width = bds_out_info->res.width + info->pipeline.left_cropping; + sc_3a_dis_padded_width = isp_internal_width; + sc_3a_dis_height = isp_internal_height; + } + + s3a_isp_width = _ISP_S3A_ELEMS_ISP_WIDTH(sc_3a_dis_padded_width, + info->pipeline.left_cropping); + if (info->s3a.fixed_s3a_deci_log) + { + s3a_log_deci = info->s3a.fixed_s3a_deci_log; + } else + { + s3a_log_deci = binary_grid_deci_factor_log2(s3a_isp_width, + sc_3a_dis_height); + } + binary->deci_factor_log2 = s3a_log_deci; + + if (info->enable.s3a) + { + binary->s3atbl_width = + _ISP_S3ATBL_WIDTH(sc_3a_dis_width, + s3a_log_deci); + binary->s3atbl_height = + _ISP_S3ATBL_HEIGHT(sc_3a_dis_height, + s3a_log_deci); + binary->s3atbl_isp_width = + _ISP_S3ATBL_ISP_WIDTH(s3a_isp_width, + s3a_log_deci); + binary->s3atbl_isp_height = + _ISP_S3ATBL_ISP_HEIGHT(sc_3a_dis_height, + s3a_log_deci); + } else + { + binary->s3atbl_width = 0; + binary->s3atbl_height = 0; + binary->s3atbl_isp_width = 0; + binary->s3atbl_isp_height = 0; + } + + if (info->enable.sc) + { + binary->sctbl_width_per_color = _ISP_SCTBL_WIDTH_PER_COLOR(sc_3a_dis_padded_width, s3a_log_deci); + binary->sctbl_aligned_width_per_color = SH_CSS_MAX_SCTBL_ALIGNED_WIDTH_PER_COLOR; + binary->sctbl_height = _ISP_SCTBL_HEIGHT(sc_3a_dis_height, s3a_log_deci); + } else + { + binary->sctbl_width_per_color = 0; + binary->sctbl_aligned_width_per_color = 0; + binary->sctbl_height = 0; + } + ia_css_sdis_init_info(&binary->dis, + sc_3a_dis_width, + sc_3a_dis_padded_width, + sc_3a_dis_height, + info->pipeline.isp_pipe_version, + info->enable.dis); + if (info->pipeline.left_cropping) + binary->left_padding = 2 * ISP_VEC_NELEMS - info->pipeline.left_cropping; + else + binary->left_padding = 0; + + return 0; +} + +static int __ia_css_binary_find(struct ia_css_binary_descr *descr, + struct ia_css_binary *binary) { + int mode; + bool online; + bool two_ppc; + enum atomisp_input_format stream_format; + const struct ia_css_frame_info *req_in_info, + *req_bds_out_info, + *req_out_info[IA_CSS_BINARY_MAX_OUTPUT_PORTS], + *req_bin_out_info = NULL, + *req_vf_info; + + struct ia_css_binary_xinfo *xcandidate; + bool need_ds, need_dz, need_dvs, need_xnr, need_dpc; + bool striped; + bool enable_yuv_ds; + bool enable_high_speed; + bool enable_dvs_6axis; + bool enable_reduced_pipe; + bool enable_capture_pp_bli; + int err = -EINVAL; + bool continuous; + unsigned int isp_pipe_version; + struct ia_css_resolution dvs_env, internal_res; + unsigned int i; + + assert(descr); + /* MW: used after an error check, may accept NULL, but doubtfull */ + assert(binary); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() enter: descr=%p, (mode=%d), binary=%p\n", + descr, descr->mode, + binary); + + mode = descr->mode; + online = descr->online; + two_ppc = descr->two_ppc; + stream_format = descr->stream_format; + req_in_info = descr->in_info; + req_bds_out_info = descr->bds_out_info; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + req_out_info[i] = descr->out_info[i]; + if (req_out_info[i] && (req_out_info[i]->res.width != 0)) + req_bin_out_info = req_out_info[i]; + } + if (!req_bin_out_info) + return -EINVAL; + req_vf_info = descr->vf_info; + + need_xnr = descr->enable_xnr; + need_ds = descr->enable_fractional_ds; + need_dz = false; + need_dvs = false; + need_dpc = descr->enable_dpc; + + enable_yuv_ds = descr->enable_yuv_ds; + enable_high_speed = descr->enable_high_speed; + enable_dvs_6axis = descr->enable_dvs_6axis; + enable_reduced_pipe = descr->enable_reduced_pipe; + enable_capture_pp_bli = descr->enable_capture_pp_bli; + continuous = descr->continuous; + striped = descr->striped; + isp_pipe_version = descr->isp_pipe_version; + + dvs_env.width = 0; + dvs_env.height = 0; + internal_res.width = 0; + internal_res.height = 0; + + if (mode == IA_CSS_BINARY_MODE_VIDEO) { + dvs_env = descr->dvs_env; + need_dz = descr->enable_dz; + /* Video is the only mode that has a nodz variant. */ + need_dvs = dvs_env.width || dvs_env.height; + } + + /* print a map of the binary file */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "BINARY INFO:\n"); + for (i = 0; i < IA_CSS_BINARY_NUM_MODES; i++) { + xcandidate = binary_infos[i]; + if (xcandidate) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%d:\n", i); + while (xcandidate) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " Name:%s Type:%d Cont:%d\n", + xcandidate->blob->name, xcandidate->type, + xcandidate->sp.enable.continuous); + xcandidate = xcandidate->next; + } + } + } + + /* printf("sh_css_binary_find: pipe version %d\n", isp_pipe_version); */ + for (xcandidate = binary_infos[mode]; xcandidate; + xcandidate = xcandidate->next) { + struct ia_css_binary_info *candidate = &xcandidate->sp; + /* printf("sh_css_binary_find: evaluating candidate: + * %d\n",candidate->id); */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() candidate = %p, mode = %d ID = %d\n", + candidate, candidate->pipeline.mode, candidate->id); + + /* + * MW: Only a limited set of jointly configured binaries can + * be used in a continuous preview/video mode unless it is + * the copy mode and runs on SP. + */ + if (!candidate->enable.continuous && + continuous && (mode != IA_CSS_BINARY_MODE_COPY)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d && (%d != %d)\n", + __LINE__, candidate->enable.continuous, + continuous, mode, + IA_CSS_BINARY_MODE_COPY); + continue; + } + if (striped && candidate->iterator.num_stripes == 1) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: binary is not striped\n", + __LINE__); + continue; + } + + if (candidate->pipeline.isp_pipe_version != isp_pipe_version && + (mode != IA_CSS_BINARY_MODE_COPY) && + (mode != IA_CSS_BINARY_MODE_CAPTURE_PP) && + (mode != IA_CSS_BINARY_MODE_VF_PP)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d != %d)\n", + __LINE__, + candidate->pipeline.isp_pipe_version, isp_pipe_version); + continue; + } + if (!candidate->enable.reduced_pipe && enable_reduced_pipe) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, + candidate->enable.reduced_pipe, + enable_reduced_pipe); + continue; + } + if (!candidate->enable.dvs_6axis && enable_dvs_6axis) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, + candidate->enable.dvs_6axis, + enable_dvs_6axis); + continue; + } + if (candidate->enable.high_speed && !enable_high_speed) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d && !%d\n", + __LINE__, + candidate->enable.high_speed, + enable_high_speed); + continue; + } + if (!candidate->enable.xnr && need_xnr) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d && !%d\n", + __LINE__, + candidate->enable.xnr, + need_xnr); + continue; + } + if (!(candidate->enable.ds & 2) && enable_yuv_ds) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, + ((candidate->enable.ds & 2) != 0), + enable_yuv_ds); + continue; + } + if ((candidate->enable.ds & 2) && !enable_yuv_ds) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d && !%d\n", + __LINE__, + ((candidate->enable.ds & 2) != 0), + enable_yuv_ds); + continue; + } + + if (mode == IA_CSS_BINARY_MODE_VIDEO && + candidate->enable.ds && need_ds) + need_dz = false; + + /* when we require vf output, we need to have vf_veceven */ + if ((req_vf_info) && !(candidate->enable.vf_veceven || + /* or variable vf vec even */ + candidate->vf_dec.is_variable || + /* or more than one output pin. */ + xcandidate->num_output_pins > 1)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%p != NULL) && !(%d || %d || (%d >%d))\n", + __LINE__, req_vf_info, + candidate->enable.vf_veceven, + candidate->vf_dec.is_variable, + xcandidate->num_output_pins, 1); + continue; + } + if (!candidate->enable.dvs_envelope && need_dvs) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, + candidate->enable.dvs_envelope, (int)need_dvs); + continue; + } + /* internal_res check considers input, output, and dvs envelope sizes */ + ia_css_binary_internal_res(req_in_info, req_bds_out_info, + req_bin_out_info, &dvs_env, candidate, &internal_res); + if (internal_res.width > candidate->internal.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d)\n", + __LINE__, internal_res.width, + candidate->internal.max_width); + continue; + } + if (internal_res.height > candidate->internal.max_height) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d)\n", + __LINE__, internal_res.height, + candidate->internal.max_height); + continue; + } + if (!candidate->enable.ds && need_ds && !(xcandidate->num_output_pins > 1)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, candidate->enable.ds, (int)need_ds); + continue; + } + if (!candidate->enable.uds && !candidate->enable.dvs_6axis && need_dz) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && !%d && %d\n", + __LINE__, candidate->enable.uds, + candidate->enable.dvs_6axis, (int)need_dz); + continue; + } + if (online && candidate->input.source == IA_CSS_BINARY_INPUT_MEMORY) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d && (%d == %d)\n", + __LINE__, online, candidate->input.source, + IA_CSS_BINARY_INPUT_MEMORY); + continue; + } + if (!online && candidate->input.source == IA_CSS_BINARY_INPUT_SENSOR) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && (%d == %d)\n", + __LINE__, online, candidate->input.source, + IA_CSS_BINARY_INPUT_SENSOR); + continue; + } + if (req_bin_out_info->res.width < candidate->output.min_width || + req_bin_out_info->res.width > candidate->output.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d) || (%d < %d)\n", + __LINE__, + req_bin_out_info->padded_width, + candidate->output.min_width, + req_bin_out_info->padded_width, + candidate->output.max_width); + continue; + } + if (xcandidate->num_output_pins > 1 && + /* in case we have a second output pin, */ + req_vf_info) { /* and we need vf output. */ + if (req_vf_info->res.width > candidate->output.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d < %d)\n", + __LINE__, + req_vf_info->res.width, + candidate->output.max_width); + continue; + } + } + if (req_in_info->padded_width > candidate->input.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d)\n", + __LINE__, req_in_info->padded_width, + candidate->input.max_width); + continue; + } + if (!binary_supports_output_format(xcandidate, req_bin_out_info->format)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d\n", + __LINE__, + binary_supports_output_format(xcandidate, req_bin_out_info->format)); + continue; + } + if (xcandidate->num_output_pins > 1 && + /* in case we have a second output pin, */ + req_vf_info && /* and we need vf output. */ + /* check if the required vf format + is supported. */ + !binary_supports_output_format(xcandidate, req_vf_info->format)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d) && (%p != NULL) && !%d\n", + __LINE__, xcandidate->num_output_pins, 1, + req_vf_info, + binary_supports_output_format(xcandidate, req_vf_info->format)); + continue; + } + + /* Check if vf_veceven supports the requested vf format */ + if (xcandidate->num_output_pins == 1 && + req_vf_info && candidate->enable.vf_veceven && + !binary_supports_vf_format(xcandidate, req_vf_info->format)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d == %d) && (%p != NULL) && %d && !%d\n", + __LINE__, xcandidate->num_output_pins, 1, + req_vf_info, candidate->enable.vf_veceven, + binary_supports_vf_format(xcandidate, req_vf_info->format)); + continue; + } + + /* Check if vf_veceven supports the requested vf width */ + if (xcandidate->num_output_pins == 1 && + req_vf_info && candidate->enable.vf_veceven) { /* and we need vf output. */ + if (req_vf_info->res.width > candidate->output.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d < %d)\n", + __LINE__, + req_vf_info->res.width, + candidate->output.max_width); + continue; + } + } + + if (!supports_bds_factor(candidate->bds.supported_bds_factors, + descr->required_bds_factor)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: 0x%x & 0x%x)\n", + __LINE__, candidate->bds.supported_bds_factors, + descr->required_bds_factor); + continue; + } + + if (!candidate->enable.dpc && need_dpc) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: 0x%x & 0x%x)\n", + __LINE__, candidate->enable.dpc, + descr->enable_dpc); + continue; + } + + if (candidate->uds.use_bci && enable_capture_pp_bli) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: 0x%x & 0x%x)\n", + __LINE__, candidate->uds.use_bci, + descr->enable_capture_pp_bli); + continue; + } + + /* reconfigure any variable properties of the binary */ + err = ia_css_binary_fill_info(xcandidate, online, two_ppc, + stream_format, req_in_info, + req_bds_out_info, + req_out_info, req_vf_info, + binary, &dvs_env, + descr->stream_config_left_padding, + false); + + if (err) + break; + binary_init_metrics(&binary->metrics, &binary->info->sp); + break; + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() selected = %p, mode = %d ID = %d\n", + xcandidate, xcandidate ? xcandidate->sp.pipeline.mode : 0, xcandidate ? xcandidate->sp.id : 0); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() leave: return_err=%d\n", err); + + if (!err && xcandidate) + dev_dbg(atomisp_dev, + "Using binary %s (id %d), type %d, mode %d, continuous %s\n", + xcandidate->blob->name, + xcandidate->sp.id, + xcandidate->type, + xcandidate->sp.pipeline.mode, + xcandidate->sp.enable.continuous ? "true" : "false"); + + + return err; +} + +int ia_css_binary_find(struct ia_css_binary_descr *descr, + struct ia_css_binary *binary) +{ + int ret = __ia_css_binary_find(descr, binary); + + if (unlikely(ret)) { + dev_dbg(atomisp_dev, "Seeking for binary failed at:"); + dump_stack(); + } + + return ret; +} + +unsigned +ia_css_binary_max_vf_width(void) +{ + /* This is (should be) true for IPU1 and IPU2 */ + /* For IPU3 (SkyCam) this pointer is guaranteed to be NULL simply because such a binary does not exist */ + if (binary_infos[IA_CSS_BINARY_MODE_VF_PP]) + return binary_infos[IA_CSS_BINARY_MODE_VF_PP]->sp.output.max_width; + return 0; +} + +void +ia_css_binary_destroy_isp_parameters(struct ia_css_binary *binary) +{ + if (binary) { + ia_css_isp_param_destroy_isp_parameters(&binary->mem_params, + &binary->css_params); + } +} + +void +ia_css_binary_get_isp_binaries(struct ia_css_binary_xinfo **binaries, + uint32_t *num_isp_binaries) +{ + assert(binaries); + + if (num_isp_binaries) + *num_isp_binaries = 0; + + *binaries = all_binaries; + if (all_binaries && num_isp_binaries) { + /* -1 to account for sp binary which is not stored in all_binaries */ + if (sh_css_num_binaries > 0) + *num_isp_binaries = sh_css_num_binaries - 1; + } +} diff --git a/drivers/staging/media/atomisp/pci/runtime/bufq/interface/ia_css_bufq.h b/drivers/staging/media/atomisp/pci/runtime/bufq/interface/ia_css_bufq.h new file mode 100644 index 000000000..a461b0ed0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/bufq/interface/ia_css_bufq.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_BUFQ_H +#define _IA_CSS_BUFQ_H + +#include +#include "ia_css_bufq_comm.h" +#include "ia_css_buffer.h" +#include "ia_css_err.h" +#define BUFQ_EVENT_SIZE 4 + +/** + * @brief Query the internal frame ID. + * + * @param[in] key The query key. + * @param[out] val The query value. + * + * @return + * true, if the query succeeds; + * false, if the query fails. + */ +bool ia_css_query_internal_queue_id( + enum ia_css_buffer_type buf_type, + unsigned int thread_id, + enum sh_css_queue_id *val +); + +/** + * @brief Map buffer type to a internal queue id. + * + * @param[in] thread id Thread in which the buffer type has to be mapped or unmapped + * @param[in] buf_type buffer type. + * @param[in] map boolean flag to specify map or unmap + * @return none + */ +void ia_css_queue_map( + unsigned int thread_id, + enum ia_css_buffer_type buf_type, + bool map +); + +/** + * @brief Initialize buffer type to a queue id mapping + * @return none + */ +void ia_css_queue_map_init(void); + +/** + * @brief initializes bufq module + * It create instances of + * -host to SP buffer queue which is a list with predefined size, + * MxN queues where M is the number threads and N is the number queues per thread + *-SP to host buffer queue , is a list with N queues + *-host to SP event communication queue + * -SP to host event communication queue + * -queue for tagger commands + * @return none + */ +void ia_css_bufq_init(void); + +/** +* @brief Enqueues an item into host to SP buffer queue + * + * @param thread_index[in] Thread in which the item to be enqueued + * + * @param queue_id[in] Index of the queue in the specified thread + * @param item[in] Object to enqueue. + * @return 0 or error code upon error. + * +*/ +int ia_css_bufq_enqueue_buffer( + int thread_index, + int queue_id, + uint32_t item); + +/** +* @brief Dequeues an item from SP to host buffer queue. + * + * @param queue_id[in] Specifies the index of the queue in the list where + * the item has to be read. + * @paramitem [out] Object to be dequeued into this item. + * @return 0 or error code upon error. + * +*/ +int ia_css_bufq_dequeue_buffer( + int queue_id, + uint32_t *item); + +/** +* @brief Enqueue an event item into host to SP communication event queue. + * + * @param[in] evt_id The event ID. + * @param[in] evt_payload_0 The event payload. + * @param[in] evt_payload_1 The event payload. + * @param[in] evt_payload_2 The event payload. + * @return 0 or error code upon error. + * +*/ +int ia_css_bufq_enqueue_psys_event( + u8 evt_id, + u8 evt_payload_0, + u8 evt_payload_1, + uint8_t evt_payload_2 +); + +/** + * @brief Dequeue an item from SP to host communication event queue. + * + * @param item Object to be dequeued into this item. + * @return 0 or error code upon error. + * +*/ +int ia_css_bufq_dequeue_psys_event( + u8 item[BUFQ_EVENT_SIZE] + +); + +/** + * @brief Enqueue an event item into host to SP EOF event queue. + * + * @param[in] evt_id The event ID. + * @return 0 or error code upon error. + * + */ +int ia_css_bufq_enqueue_isys_event( + uint8_t evt_id); + +/** +* @brief Dequeue an item from SP to host communication EOF event queue. + + * + * @param item Object to be dequeued into this item. + * @return 0 or error code upon error. + * + */ +int ia_css_bufq_dequeue_isys_event( + u8 item[BUFQ_EVENT_SIZE]); + +/** +* @brief Enqueue a tagger command item into tagger command queue.. + * + * @param item Object to be enqueue. + * @return 0 or error code upon error. + * +*/ +int ia_css_bufq_enqueue_tag_cmd( + uint32_t item); + +/** +* @brief Uninitializes bufq module. + * + * @return 0 or error code upon error. + * +*/ +int ia_css_bufq_deinit(void); + +/** +* @brief Dump queue states + * + * @return None + * +*/ +void ia_css_bufq_dump_queue_info(void); + +#endif /* _IA_CSS_BUFQ_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/bufq/interface/ia_css_bufq_comm.h b/drivers/staging/media/atomisp/pci/runtime/bufq/interface/ia_css_bufq_comm.h new file mode 100644 index 000000000..567d94d91 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/bufq/interface/ia_css_bufq_comm.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_BUFQ_COMM_H +#define _IA_CSS_BUFQ_COMM_H + +#include "system_global.h" + +enum sh_css_queue_id { + SH_CSS_INVALID_QUEUE_ID = -1, + SH_CSS_QUEUE_A_ID = 0, + SH_CSS_QUEUE_B_ID, + SH_CSS_QUEUE_C_ID, + SH_CSS_QUEUE_D_ID, + SH_CSS_QUEUE_E_ID, + SH_CSS_QUEUE_F_ID, + SH_CSS_QUEUE_G_ID, + SH_CSS_QUEUE_H_ID, /* for metadata */ + +#define SH_CSS_MAX_NUM_QUEUES (SH_CSS_QUEUE_H_ID + 1) + +}; + +#define SH_CSS_MAX_DYNAMIC_BUFFERS_PER_THREAD SH_CSS_MAX_NUM_QUEUES +/* for now we staticaly assign queue 0 & 1 to parameter sets */ +#define IA_CSS_PARAMETER_SET_QUEUE_ID SH_CSS_QUEUE_A_ID +#define IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID SH_CSS_QUEUE_B_ID + +#endif diff --git a/drivers/staging/media/atomisp/pci/runtime/bufq/src/bufq.c b/drivers/staging/media/atomisp/pci/runtime/bufq/src/bufq.c new file mode 100644 index 000000000..6a75cba48 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/bufq/src/bufq.c @@ -0,0 +1,532 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "assert_support.h" /* assert */ +#include "ia_css_buffer.h" +#include "sp.h" +#include "ia_css_bufq.h" /* Bufq API's */ +#include "ia_css_queue.h" /* ia_css_queue_t */ +#include "sw_event_global.h" /* Event IDs.*/ +#include "ia_css_eventq.h" /* ia_css_eventq_recv()*/ +#include "ia_css_debug.h" /* ia_css_debug_dtrace*/ +#include "sh_css_internal.h" /* sh_css_queue_type */ +#include "sp_local.h" /* sp_address_of */ +#include "sh_css_firmware.h" /* sh_css_sp_fw*/ + +#define BUFQ_DUMP_FILE_NAME_PREFIX_SIZE 256 + +static char prefix[BUFQ_DUMP_FILE_NAME_PREFIX_SIZE] = {0}; + +/*********************************************************/ +/* Global Queue objects used by CSS */ +/*********************************************************/ + +struct sh_css_queues { + /* Host2SP buffer queue */ + ia_css_queue_t host2sp_buffer_queue_handles + [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; + /* SP2Host buffer queue */ + ia_css_queue_t sp2host_buffer_queue_handles + [SH_CSS_MAX_NUM_QUEUES]; + + /* Host2SP event queue */ + ia_css_queue_t host2sp_psys_event_queue_handle; + + /* SP2Host event queue */ + ia_css_queue_t sp2host_psys_event_queue_handle; + + /* Host2SP ISYS event queue */ + ia_css_queue_t host2sp_isys_event_queue_handle; + + /* SP2Host ISYS event queue */ + ia_css_queue_t sp2host_isys_event_queue_handle; + /* Tagger command queue */ + ia_css_queue_t host2sp_tag_cmd_queue_handle; +}; + +/******************************************************* +*** Static variables +********************************************************/ +static struct sh_css_queues css_queues; + +static int +buffer_type_to_queue_id_map[SH_CSS_MAX_SP_THREADS][IA_CSS_NUM_DYNAMIC_BUFFER_TYPE]; +static bool queue_availability[SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; + +/******************************************************* +*** Static functions +********************************************************/ +static void map_buffer_type_to_queue_id( + unsigned int thread_id, + enum ia_css_buffer_type buf_type +); +static void unmap_buffer_type_to_queue_id( + unsigned int thread_id, + enum ia_css_buffer_type buf_type +); + +static ia_css_queue_t *bufq_get_qhandle( + enum sh_css_queue_type type, + enum sh_css_queue_id id, + int thread +); + +/******************************************************* +*** Public functions +********************************************************/ +void ia_css_queue_map_init(void) +{ + unsigned int i, j; + + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) { + for (j = 0; j < SH_CSS_MAX_NUM_QUEUES; j++) + queue_availability[i][j] = true; + } + + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) { + for (j = 0; j < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE; j++) + buffer_type_to_queue_id_map[i][j] = SH_CSS_INVALID_QUEUE_ID; + } +} + +void ia_css_queue_map( + unsigned int thread_id, + enum ia_css_buffer_type buf_type, + bool map) +{ + assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE); + assert(thread_id < SH_CSS_MAX_SP_THREADS); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_queue_map() enter: buf_type=%d, thread_id=%d\n", buf_type, thread_id); + + if (map) + map_buffer_type_to_queue_id(thread_id, buf_type); + else + unmap_buffer_type_to_queue_id(thread_id, buf_type); +} + +/* + * @brief Query the internal queue ID. + */ +bool ia_css_query_internal_queue_id( + enum ia_css_buffer_type buf_type, + unsigned int thread_id, + enum sh_css_queue_id *val) +{ + IA_CSS_ENTER("buf_type=%d, thread_id=%d, val = %p", buf_type, thread_id, val); + + if ((!val) || (thread_id >= SH_CSS_MAX_SP_THREADS) || + (buf_type >= IA_CSS_NUM_DYNAMIC_BUFFER_TYPE)) { + IA_CSS_LEAVE("return_val = false"); + return false; + } + + *val = buffer_type_to_queue_id_map[thread_id][buf_type]; + if ((*val == SH_CSS_INVALID_QUEUE_ID) || (*val >= SH_CSS_MAX_NUM_QUEUES)) { + IA_CSS_LOG("INVALID queue ID MAP = %d\n", *val); + IA_CSS_LEAVE("return_val = false"); + return false; + } + IA_CSS_LEAVE("return_val = true"); + return true; +} + +/******************************************************* +*** Static functions +********************************************************/ +static void map_buffer_type_to_queue_id( + unsigned int thread_id, + enum ia_css_buffer_type buf_type) +{ + unsigned int i; + + assert(thread_id < SH_CSS_MAX_SP_THREADS); + assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE); + assert(buffer_type_to_queue_id_map[thread_id][buf_type] == + SH_CSS_INVALID_QUEUE_ID); + + /* queue 0 is reserved for parameters because it doesn't depend on events */ + if (buf_type == IA_CSS_BUFFER_TYPE_PARAMETER_SET) { + assert(queue_availability[thread_id][IA_CSS_PARAMETER_SET_QUEUE_ID]); + queue_availability[thread_id][IA_CSS_PARAMETER_SET_QUEUE_ID] = false; + buffer_type_to_queue_id_map[thread_id][buf_type] = + IA_CSS_PARAMETER_SET_QUEUE_ID; + return; + } + + /* queue 1 is reserved for per frame parameters because it doesn't depend on events */ + if (buf_type == IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET) { + assert(queue_availability[thread_id][IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID]); + queue_availability[thread_id][IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID] = false; + buffer_type_to_queue_id_map[thread_id][buf_type] = + IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID; + return; + } + + for (i = SH_CSS_QUEUE_C_ID; i < SH_CSS_MAX_NUM_QUEUES; i++) { + if (queue_availability[thread_id][i]) { + queue_availability[thread_id][i] = false; + buffer_type_to_queue_id_map[thread_id][buf_type] = i; + break; + } + } + + assert(i != SH_CSS_MAX_NUM_QUEUES); + return; +} + +static void unmap_buffer_type_to_queue_id( + unsigned int thread_id, + enum ia_css_buffer_type buf_type) +{ + int queue_id; + + assert(thread_id < SH_CSS_MAX_SP_THREADS); + assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE); + assert(buffer_type_to_queue_id_map[thread_id][buf_type] != + SH_CSS_INVALID_QUEUE_ID); + + queue_id = buffer_type_to_queue_id_map[thread_id][buf_type]; + buffer_type_to_queue_id_map[thread_id][buf_type] = SH_CSS_INVALID_QUEUE_ID; + queue_availability[thread_id][queue_id] = true; +} + +static ia_css_queue_t *bufq_get_qhandle( + enum sh_css_queue_type type, + enum sh_css_queue_id id, + int thread) +{ + ia_css_queue_t *q = NULL; + + switch (type) { + case sh_css_host2sp_buffer_queue: + if ((thread >= SH_CSS_MAX_SP_THREADS) || (thread < 0) || + (id == SH_CSS_INVALID_QUEUE_ID)) + break; + q = &css_queues.host2sp_buffer_queue_handles[thread][id]; + break; + case sh_css_sp2host_buffer_queue: + if (id == SH_CSS_INVALID_QUEUE_ID) + break; + q = &css_queues.sp2host_buffer_queue_handles[id]; + break; + case sh_css_host2sp_psys_event_queue: + q = &css_queues.host2sp_psys_event_queue_handle; + break; + case sh_css_sp2host_psys_event_queue: + q = &css_queues.sp2host_psys_event_queue_handle; + break; + case sh_css_host2sp_isys_event_queue: + q = &css_queues.host2sp_isys_event_queue_handle; + break; + case sh_css_sp2host_isys_event_queue: + q = &css_queues.sp2host_isys_event_queue_handle; + break; + case sh_css_host2sp_tag_cmd_queue: + q = &css_queues.host2sp_tag_cmd_queue_handle; + break; + default: + break; + } + + return q; +} + +/* Local function to initialize a buffer queue. This reduces + * the chances of copy-paste errors or typos. + */ +static inline void +init_bufq(unsigned int desc_offset, + unsigned int elems_offset, + ia_css_queue_t *handle) +{ + const struct ia_css_fw_info *fw; + unsigned int q_base_addr; + ia_css_queue_remote_t remoteq; + + fw = &sh_css_sp_fw; + q_base_addr = fw->info.sp.host_sp_queue; + + /* Setup queue location as SP and proc id as SP0_ID */ + remoteq.location = IA_CSS_QUEUE_LOC_SP; + remoteq.proc_id = SP0_ID; + remoteq.cb_desc_addr = q_base_addr + desc_offset; + remoteq.cb_elems_addr = q_base_addr + elems_offset; + /* Initialize the queue instance and obtain handle */ + ia_css_queue_remote_init(handle, &remoteq); +} + +void ia_css_bufq_init(void) +{ + int i, j; + + IA_CSS_ENTER_PRIVATE(""); + + /* Setup all the local queue descriptors for Host2SP Buffer Queues */ + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) + for (j = 0; j < SH_CSS_MAX_NUM_QUEUES; j++) { + init_bufq((uint32_t)offsetof(struct host_sp_queues, + host2sp_buffer_queues_desc[i][j]), + (uint32_t)offsetof(struct host_sp_queues, host2sp_buffer_queues_elems[i][j]), + &css_queues.host2sp_buffer_queue_handles[i][j]); + } + + /* Setup all the local queue descriptors for SP2Host Buffer Queues */ + for (i = 0; i < SH_CSS_MAX_NUM_QUEUES; i++) { + init_bufq(offsetof(struct host_sp_queues, sp2host_buffer_queues_desc[i]), + offsetof(struct host_sp_queues, sp2host_buffer_queues_elems[i]), + &css_queues.sp2host_buffer_queue_handles[i]); + } + + /* Host2SP event queue*/ + init_bufq((uint32_t)offsetof(struct host_sp_queues, + host2sp_psys_event_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, host2sp_psys_event_queue_elems), + &css_queues.host2sp_psys_event_queue_handle); + + /* SP2Host event queue */ + init_bufq((uint32_t)offsetof(struct host_sp_queues, + sp2host_psys_event_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, sp2host_psys_event_queue_elems), + &css_queues.sp2host_psys_event_queue_handle); + + /* Host2SP ISYS event queue */ + init_bufq((uint32_t)offsetof(struct host_sp_queues, + host2sp_isys_event_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, host2sp_isys_event_queue_elems), + &css_queues.host2sp_isys_event_queue_handle); + + /* SP2Host ISYS event queue*/ + init_bufq((uint32_t)offsetof(struct host_sp_queues, + sp2host_isys_event_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, sp2host_isys_event_queue_elems), + &css_queues.sp2host_isys_event_queue_handle); + + /* Host2SP tagger command queue */ + init_bufq((uint32_t)offsetof(struct host_sp_queues, host2sp_tag_cmd_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, host2sp_tag_cmd_queue_elems), + &css_queues.host2sp_tag_cmd_queue_handle); + + IA_CSS_LEAVE_PRIVATE(""); +} + +int ia_css_bufq_enqueue_buffer( + int thread_index, + int queue_id, + uint32_t item) +{ + ia_css_queue_t *q; + int error; + + IA_CSS_ENTER_PRIVATE("queue_id=%d", queue_id); + if ((thread_index >= SH_CSS_MAX_SP_THREADS) || (thread_index < 0) || + (queue_id == SH_CSS_INVALID_QUEUE_ID)) + return -EINVAL; + + /* Get the queue for communication */ + q = bufq_get_qhandle(sh_css_host2sp_buffer_queue, + queue_id, + thread_index); + if (q) { + error = ia_css_queue_enqueue(q, item); + } else { + IA_CSS_ERROR("queue is not initialized"); + error = -EBUSY; + } + + IA_CSS_LEAVE_ERR_PRIVATE(error); + return error; +} + +int ia_css_bufq_dequeue_buffer( + int queue_id, + uint32_t *item) +{ + int error; + ia_css_queue_t *q; + + IA_CSS_ENTER_PRIVATE("queue_id=%d", queue_id); + if ((!item) || + (queue_id <= SH_CSS_INVALID_QUEUE_ID) || + (queue_id >= SH_CSS_MAX_NUM_QUEUES) + ) + return -EINVAL; + + q = bufq_get_qhandle(sh_css_sp2host_buffer_queue, + queue_id, + -1); + if (q) { + error = ia_css_queue_dequeue(q, item); + } else { + IA_CSS_ERROR("queue is not initialized"); + error = -EBUSY; + } + + IA_CSS_LEAVE_ERR_PRIVATE(error); + return error; +} + +int ia_css_bufq_enqueue_psys_event( + u8 evt_id, + u8 evt_payload_0, + u8 evt_payload_1, + uint8_t evt_payload_2) +{ + int error = 0; + ia_css_queue_t *q; + + IA_CSS_ENTER_PRIVATE("evt_id=%d", evt_id); + q = bufq_get_qhandle(sh_css_host2sp_psys_event_queue, -1, -1); + if (!q) { + IA_CSS_ERROR("queue is not initialized"); + return -EBUSY; + } + + error = ia_css_eventq_send(q, + evt_id, evt_payload_0, evt_payload_1, evt_payload_2); + + IA_CSS_LEAVE_ERR_PRIVATE(error); + return error; +} + +int ia_css_bufq_dequeue_psys_event( + u8 item[BUFQ_EVENT_SIZE]) +{ + int error = 0; + ia_css_queue_t *q; + + /* No ENTER/LEAVE in this function since this is polled + * by some test apps. Enablign logging here floods the log + * files which may cause timeouts. */ + if (!item) + return -EINVAL; + + q = bufq_get_qhandle(sh_css_sp2host_psys_event_queue, -1, -1); + if (!q) { + IA_CSS_ERROR("queue is not initialized"); + return -EBUSY; + } + error = ia_css_eventq_recv(q, item); + + return error; +} + +int ia_css_bufq_dequeue_isys_event( + u8 item[BUFQ_EVENT_SIZE]) +{ + int error = 0; + ia_css_queue_t *q; + + /* No ENTER/LEAVE in this function since this is polled + * by some test apps. Enablign logging here floods the log + * files which may cause timeouts. */ + if (!item) + return -EINVAL; + + q = bufq_get_qhandle(sh_css_sp2host_isys_event_queue, -1, -1); + if (!q) { + IA_CSS_ERROR("queue is not initialized"); + return -EBUSY; + } + error = ia_css_eventq_recv(q, item); + return error; +} + +int ia_css_bufq_enqueue_isys_event(uint8_t evt_id) +{ + int error = 0; + ia_css_queue_t *q; + + IA_CSS_ENTER_PRIVATE("event_id=%d", evt_id); + q = bufq_get_qhandle(sh_css_host2sp_isys_event_queue, -1, -1); + if (!q) { + IA_CSS_ERROR("queue is not initialized"); + return -EBUSY; + } + + error = ia_css_eventq_send(q, evt_id, 0, 0, 0); + + IA_CSS_LEAVE_ERR_PRIVATE(error); + return error; +} + +int ia_css_bufq_enqueue_tag_cmd( + uint32_t item) +{ + int error; + ia_css_queue_t *q; + + IA_CSS_ENTER_PRIVATE("item=%d", item); + q = bufq_get_qhandle(sh_css_host2sp_tag_cmd_queue, -1, -1); + if (!q) { + IA_CSS_ERROR("queue is not initialized"); + return -EBUSY; + } + error = ia_css_queue_enqueue(q, item); + + IA_CSS_LEAVE_ERR_PRIVATE(error); + return error; +} + +int ia_css_bufq_deinit(void) +{ + return 0; +} + +static void bufq_dump_queue_info(const char *prefix, ia_css_queue_t *qhandle) +{ + u32 free = 0, used = 0; + + assert(prefix && qhandle); + ia_css_queue_get_used_space(qhandle, &used); + ia_css_queue_get_free_space(qhandle, &free); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: used=%u free=%u\n", + prefix, used, free); +} + +void ia_css_bufq_dump_queue_info(void) +{ + int i, j; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Queue Information:\n"); + + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) { + for (j = 0; j < SH_CSS_MAX_NUM_QUEUES; j++) { + snprintf(prefix, BUFQ_DUMP_FILE_NAME_PREFIX_SIZE, + "host2sp_buffer_queue[%u][%u]", i, j); + bufq_dump_queue_info(prefix, + &css_queues.host2sp_buffer_queue_handles[i][j]); + } + } + + for (i = 0; i < SH_CSS_MAX_NUM_QUEUES; i++) { + snprintf(prefix, BUFQ_DUMP_FILE_NAME_PREFIX_SIZE, + "sp2host_buffer_queue[%u]", i); + bufq_dump_queue_info(prefix, + &css_queues.sp2host_buffer_queue_handles[i]); + } + bufq_dump_queue_info("host2sp_psys_event", + &css_queues.host2sp_psys_event_queue_handle); + bufq_dump_queue_info("sp2host_psys_event", + &css_queues.sp2host_psys_event_queue_handle); + + bufq_dump_queue_info("host2sp_isys_event", + &css_queues.host2sp_isys_event_queue_handle); + bufq_dump_queue_info("sp2host_isys_event", + &css_queues.sp2host_isys_event_queue_handle); + bufq_dump_queue_info("host2sp_tag_cmd", + &css_queues.host2sp_tag_cmd_queue_handle); +} diff --git a/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug.h b/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug.h new file mode 100644 index 000000000..fff89e9b4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug.h @@ -0,0 +1,500 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_DEBUG_H_ +#define _IA_CSS_DEBUG_H_ + +/*! \file */ + +#include +#include +#include +#include "ia_css_types.h" +#include "ia_css_binary.h" +#include "ia_css_frame_public.h" +#include "ia_css_pipe_public.h" +#include "ia_css_stream_public.h" +#include "ia_css_metadata.h" +#include "sh_css_internal.h" +/* ISP2500 */ +#include "ia_css_pipe.h" + +/* available levels */ +/*! Level for tracing errors */ +#define IA_CSS_DEBUG_ERROR 1 +/*! Level for tracing warnings */ +#define IA_CSS_DEBUG_WARNING 3 +/*! Level for tracing debug messages */ +#define IA_CSS_DEBUG_VERBOSE 5 +/*! Level for tracing trace messages a.o. ia_css public function calls */ +#define IA_CSS_DEBUG_TRACE 6 +/*! Level for tracing trace messages a.o. ia_css private function calls */ +#define IA_CSS_DEBUG_TRACE_PRIVATE 7 +/*! Level for tracing parameter messages e.g. in and out params of functions */ +#define IA_CSS_DEBUG_PARAM 8 +/*! Level for tracing info messages */ +#define IA_CSS_DEBUG_INFO 9 + +/* Global variable which controls the verbosity levels of the debug tracing */ +extern int dbg_level; + +/*! @brief Enum defining the different isp parameters to dump. + * Values can be combined to dump a combination of sets. + */ +enum ia_css_debug_enable_param_dump { + IA_CSS_DEBUG_DUMP_FPN = BIT(0), /** FPN table */ + IA_CSS_DEBUG_DUMP_OB = BIT(1), /** OB table */ + IA_CSS_DEBUG_DUMP_SC = BIT(2), /** Shading table */ + IA_CSS_DEBUG_DUMP_WB = BIT(3), /** White balance */ + IA_CSS_DEBUG_DUMP_DP = BIT(4), /** Defect Pixel */ + IA_CSS_DEBUG_DUMP_BNR = BIT(5), /** Bayer Noise Reductions */ + IA_CSS_DEBUG_DUMP_S3A = BIT(6), /** 3A Statistics */ + IA_CSS_DEBUG_DUMP_DE = BIT(7), /** De Mosaicing */ + IA_CSS_DEBUG_DUMP_YNR = BIT(8), /** Luma Noise Reduction */ + IA_CSS_DEBUG_DUMP_CSC = BIT(9), /** Color Space Conversion */ + IA_CSS_DEBUG_DUMP_GC = BIT(10), /** Gamma Correction */ + IA_CSS_DEBUG_DUMP_TNR = BIT(11), /** Temporal Noise Reduction */ + IA_CSS_DEBUG_DUMP_ANR = BIT(12), /** Advanced Noise Reduction */ + IA_CSS_DEBUG_DUMP_CE = BIT(13), /** Chroma Enhancement */ + IA_CSS_DEBUG_DUMP_ALL = BIT(14), /** Dump all device parameters */ +}; + +#define IA_CSS_ERROR(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, \ + "%s() %d: error: " fmt "\n", __func__, __LINE__, ##__VA_ARGS__) + +#define IA_CSS_WARNING(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_WARNING, \ + "%s() %d: warning: " fmt "\n", __func__, __LINE__, ##__VA_ARGS__) + +/* Logging macros for public functions (API functions) */ +#define IA_CSS_ENTER(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \ + "%s(): enter: " fmt "\n", __func__, ##__VA_ARGS__) + +/* Use this macro for small functions that do not call other functions. */ +#define IA_CSS_ENTER_LEAVE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \ + "%s(): enter: leave: " fmt "\n", __func__, ##__VA_ARGS__) + +#define IA_CSS_LEAVE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \ + "%s(): leave: " fmt "\n", __func__, ##__VA_ARGS__) + +/* Shorthand for returning an int return value */ +#define IA_CSS_LEAVE_ERR(__err) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \ + "%s() %d: leave: return_err=%d\n", __func__, __LINE__, __err) + +/* Use this macro for logging other than enter/leave. + * Note that this macro always uses the PRIVATE logging level. + */ +#define IA_CSS_LOG(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s(): " fmt "\n", __func__, ##__VA_ARGS__) + +/* Logging macros for non-API functions. These have a lower trace level */ +#define IA_CSS_ENTER_PRIVATE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s(): enter: " fmt "\n", __func__, ##__VA_ARGS__) + +#define IA_CSS_LEAVE_PRIVATE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s(): leave: " fmt "\n", __func__, ##__VA_ARGS__) + +/* Shorthand for returning an int return value */ +#define IA_CSS_LEAVE_ERR_PRIVATE(__err) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s() %d: leave: return_err=%d\n", __func__, __LINE__, __err) + +/* Use this macro for small functions that do not call other functions. */ +#define IA_CSS_ENTER_LEAVE_PRIVATE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s(): enter: leave: " fmt "\n", __func__, ##__VA_ARGS__) + +/*! @brief Function for tracing to the provided printf function in the + * environment. + * @param[in] level Level of the message. + * @param[in] fmt printf like format string + * @param[in] args arguments for the format string + */ +static inline void __printf(2, 0) ia_css_debug_vdtrace(unsigned int level, + const char *fmt, + va_list args) +{ + if (dbg_level >= level) + sh_css_vprint(fmt, args); +} + +__printf(2, 3) void ia_css_debug_dtrace(unsigned int level, + const char *fmt, ...); + +/*! @brief Dump sp thread's stack contents + * SP thread's stack contents are set to 0xcafecafe. This function dumps the + * stack to inspect if the stack's boundaries are compromised. + * @return None + */ +void ia_css_debug_dump_sp_stack_info(void); + +/*! @brief Function to set the global dtrace verbosity level. + * @param[in] trace_level Maximum level of the messages to be traced. + * @return None + */ +void ia_css_debug_set_dtrace_level( + const unsigned int trace_level); + +/*! @brief Function to get the global dtrace verbosity level. + * @return global dtrace verbosity level + */ +unsigned int ia_css_debug_get_dtrace_level(void); + +/*! @brief Dump isp hardware state. + * Dumps the isp hardware state to tracing output. + * @return None + */ +void ia_css_debug_dump_isp_state(void); + +/*! @brief Dump sp hardware state. + * Dumps the sp hardware state to tracing output. + * @return None + */ +void ia_css_debug_dump_sp_state(void); + +/* ISP2401 */ +/*! @brief Dump GAC hardware state. + * Dumps the GAC ACB hardware registers. may be useful for + * detecting a GAC which got hang. + * @return None + */ +void ia_css_debug_dump_gac_state(void); + +/*! @brief Dump dma controller state. + * Dumps the dma controller state to tracing output. + * @return None + */ +void ia_css_debug_dump_dma_state(void); + +/*! @brief Dump internal sp software state. + * Dumps the sp software state to tracing output. + * @return None + */ +void ia_css_debug_dump_sp_sw_debug_info(void); + +/*! @brief Dump all related hardware state to the trace output + * @param[in] context String to identify context in output. + * @return None + */ +void ia_css_debug_dump_debug_info( + const char *context); + +#if SP_DEBUG != SP_DEBUG_NONE +void ia_css_debug_print_sp_debug_state( + const struct sh_css_sp_debug_state *state); +#endif + +/*! @brief Dump all related binary info data + * @param[in] bi Binary info struct. + * @return None + */ +void ia_css_debug_binary_print( + const struct ia_css_binary *bi); + +void ia_css_debug_sp_dump_mipi_fifo_high_water(void); + +/*! @brief Dump isp gdc fifo state to the trace output + * Dumps the isp gdc fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_isp_gdc_fifo_state(void); + +/*! @brief Dump dma isp fifo state + * Dumps the dma isp fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_dma_isp_fifo_state(void); + +/*! @brief Dump dma sp fifo state + * Dumps the dma sp fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_dma_sp_fifo_state(void); + +/*! \brief Dump pif A isp fifo state + * Dumps the primary input formatter state to tracing output. + * @return None + */ +void ia_css_debug_dump_pif_a_isp_fifo_state(void); + +/*! \brief Dump pif B isp fifo state + * Dumps the primary input formatter state to tracing output. + * \return None + */ +void ia_css_debug_dump_pif_b_isp_fifo_state(void); + +/*! @brief Dump stream-to-memory sp fifo state + * Dumps the stream-to-memory block state to tracing output. + * @return None + */ +void ia_css_debug_dump_str2mem_sp_fifo_state(void); + +/*! @brief Dump isp sp fifo state + * Dumps the isp sp fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_isp_sp_fifo_state(void); + +/*! @brief Dump all fifo state info to the output + * Dumps all fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_all_fifo_state(void); + +/*! @brief Dump the rx state to the output + * Dumps the rx state to tracing output. + * @return None + */ +void ia_css_debug_dump_rx_state(void); + +/*! @brief Dump the input system state to the output + * Dumps the input system state to tracing output. + * @return None + */ +void ia_css_debug_dump_isys_state(void); + +/*! @brief Dump the frame info to the trace output + * Dumps the frame info to tracing output. + * @param[in] frame pointer to struct ia_css_frame + * @param[in] descr description output along with the frame info + * @return None + */ +void ia_css_debug_frame_print( + const struct ia_css_frame *frame, + const char *descr); + +/*! @brief Function to enable sp sleep mode. + * Function that enables sp sleep mode + * @param[in] mode indicates when to put sp to sleep + * @return None + */ +void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode); + +/*! @brief Function to wake up sp when in sleep mode. + * After sp has been put to sleep, use this function to let it continue + * to run again. + * @return None + */ +void ia_css_debug_wake_up_sp(void); + +/*! @brief Function to dump isp parameters. + * Dump isp parameters to tracing output + * @param[in] stream pointer to ia_css_stream struct + * @param[in] enable flag indicating which parameters to dump. + * @return None + */ +void ia_css_debug_dump_isp_params(struct ia_css_stream *stream, + unsigned int enable); + +/*! @brief Function to dump some sp performance counters. + * Dump sp performance counters, currently input system errors. + * @return None + */ +void ia_css_debug_dump_perf_counters(void); + +#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG +void sh_css_dump_thread_wait_info(void); +void sh_css_dump_pipe_stage_info(void); +void sh_css_dump_pipe_stripe_info(void); +#endif + +void ia_css_debug_dump_isp_binary(void); + +void sh_css_dump_sp_raw_copy_linecount(bool reduced); + +/*! @brief Dump the resolution info to the trace output + * Dumps the resolution info to the trace output. + * @param[in] res pointer to struct ia_css_resolution + * @param[in] label description of resolution output + * @return None + */ +void ia_css_debug_dump_resolution( + const struct ia_css_resolution *res, + const char *label); + +/*! @brief Dump the frame info to the trace output + * Dumps the frame info to the trace output. + * @param[in] info pointer to struct ia_css_frame_info + * @param[in] label description of frame_info output + * @return None + */ +void ia_css_debug_dump_frame_info( + const struct ia_css_frame_info *info, + const char *label); + +/*! @brief Dump the capture config info to the trace output + * Dumps the capture config info to the trace output. + * @param[in] config pointer to struct ia_css_capture_config + * @return None + */ +void ia_css_debug_dump_capture_config( + const struct ia_css_capture_config *config); + +/*! @brief Dump the pipe extra config info to the trace output + * Dumps the pipe extra config info to the trace output. + * @param[in] extra_config pointer to struct ia_css_pipe_extra_config + * @return None + */ +void ia_css_debug_dump_pipe_extra_config( + const struct ia_css_pipe_extra_config *extra_config); + +/*! @brief Dump the pipe config info to the trace output + * Dumps the pipe config info to the trace output. + * @param[in] config pointer to struct ia_css_pipe_config + * @return None + */ +void ia_css_debug_dump_pipe_config( + const struct ia_css_pipe_config *config); + +/*! @brief Dump the stream config source info to the trace output + * Dumps the stream config source info to the trace output. + * @param[in] config pointer to struct ia_css_stream_config + * @return None + */ +void ia_css_debug_dump_stream_config_source( + const struct ia_css_stream_config *config); + +/*! @brief Dump the mipi buffer config info to the trace output + * Dumps the mipi buffer config info to the trace output. + * @param[in] config pointer to struct ia_css_mipi_buffer_config + * @return None + */ +void ia_css_debug_dump_mipi_buffer_config( + const struct ia_css_mipi_buffer_config *config); + +/*! @brief Dump the metadata config info to the trace output + * Dumps the metadata config info to the trace output. + * @param[in] config pointer to struct ia_css_metadata_config + * @return None + */ +void ia_css_debug_dump_metadata_config( + const struct ia_css_metadata_config *config); + +/*! @brief Dump the stream config info to the trace output + * Dumps the stream config info to the trace output. + * @param[in] config pointer to struct ia_css_stream_config + * @param[in] num_pipes number of pipes for the stream + * @return None + */ +void ia_css_debug_dump_stream_config( + const struct ia_css_stream_config *config, + int num_pipes); + +/*! @brief Dump the state of the SP tagger + * Dumps the internal state of the SP tagger + * @return None + */ +void ia_css_debug_tagger_state(void); + +/** + * @brief Initialize the debug mode. + * + * WARNING: + * This API should be called ONLY once in the debug mode. + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool ia_css_debug_mode_init(void); + +/** + * @brief Disable the DMA channel. + * + * @param[in] dma_ID The ID of the target DMA. + * @param[in] channel_id The ID of the target DMA channel. + * @param[in] request_type The type of the DMA request. + * For example: + * - "0" indicates the writing request. + * - "1" indicates the reading request. + * + * This is part of the DMA API -> dma.h + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool ia_css_debug_mode_disable_dma_channel( + int dma_ID, + int channel_id, + int request_type); +/** + * @brief Enable the DMA channel. + * + * @param[in] dma_ID The ID of the target DMA. + * @param[in] channel_id The ID of the target DMA channel. + * @param[in] request_type The type of the DMA request. + * For example: + * - "0" indicates the writing request. + * - "1" indicates the reading request. + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool ia_css_debug_mode_enable_dma_channel( + int dma_ID, + int channel_id, + int request_type); + +/** + * @brief Dump tracer data. + * [Currently support is only for SKC] + * + * @return + * - none. + */ +void ia_css_debug_dump_trace(void); + +/* ISP2401 */ +/** + * @brief Program counter dumping (in loop) + * + * @param[in] id The ID of the SP + * @param[in] num_of_dumps The number of dumps + * + * @return + * - none + */ +void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps); + +/* ISP2500 */ +/*! @brief Dump all states for ISP hang case. + * Dumps the ISP previous and current configurations + * GACs status, SP0/1 statuses. + * + * @param[in] pipe The current pipe + * + * @return None + */ +void ia_css_debug_dump_hang_status( + struct ia_css_pipe *pipe); + +/*! @brief External command handler + * External command handler + * + * @return None + */ +void ia_css_debug_ext_command_handler(void); + +#endif /* _IA_CSS_DEBUG_H_ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug_internal.h b/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug_internal.h new file mode 100644 index 000000000..8ec487ad4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug_internal.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* TO DO: Move debug related code from ia_css_internal.h in */ diff --git a/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug_pipe.h b/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug_pipe.h new file mode 100644 index 000000000..538918cfb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug_pipe.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_DEBUG_PIPE_H_ +#define _IA_CSS_DEBUG_PIPE_H_ + +/*! \file */ + +#include +#include +#include "ia_css_pipeline.h" + +/** + * @brief Internal debug support for constructing a pipe graph. + * + * @return None + */ +void ia_css_debug_pipe_graph_dump_prologue(void); + +/** + * @brief Internal debug support for constructing a pipe graph. + * + * @return None + */ +void ia_css_debug_pipe_graph_dump_epilogue(void); + +/** + * @brief Internal debug support for constructing a pipe graph. + * @param[in] stage Pipeline stage. + * @param[in] id Pipe id. + * + * @return None + */ +void ia_css_debug_pipe_graph_dump_stage( + struct ia_css_pipeline_stage *stage, + enum ia_css_pipe_id id); + +/** + * @brief Internal debug support for constructing a pipe graph. + * @param[in] out_frame Output frame of SP raw copy. + * + * @return None + */ +void ia_css_debug_pipe_graph_dump_sp_raw_copy( + struct ia_css_frame *out_frame); + +/** + * @brief Internal debug support for constructing a pipe graph. + * @param[in] stream_config info about sensor and input formatter. + * + * @return None + */ +void ia_css_debug_pipe_graph_dump_stream_config( + const struct ia_css_stream_config *stream_config); + +#endif /* _IA_CSS_DEBUG_PIPE_H_ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/debug/src/ia_css_debug.c b/drivers/staging/media/atomisp/pci/runtime/debug/src/ia_css_debug.c new file mode 100644 index 000000000..bb6204cb4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/debug/src/ia_css_debug.c @@ -0,0 +1,3403 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "debug.h" + +#ifndef __INLINE_INPUT_SYSTEM__ +#define __INLINE_INPUT_SYSTEM__ +#endif +#ifndef __INLINE_IBUF_CTRL__ +#define __INLINE_IBUF_CTRL__ +#endif +#ifndef __INLINE_CSI_RX__ +#define __INLINE_CSI_RX__ +#endif +#ifndef __INLINE_PIXELGEN__ +#define __INLINE_PIXELGEN__ +#endif +#ifndef __INLINE_STREAM2MMIO__ +#define __INLINE_STREAM2MMIO__ +#endif + +#include /* for strscpy() */ + +#include "ia_css_debug.h" +#include "ia_css_debug_pipe.h" +#include "ia_css_irq.h" +#include "ia_css_stream.h" +#include "ia_css_pipeline.h" +#include "ia_css_isp_param.h" +#include "sh_css_params.h" +#include "ia_css_bufq.h" +/* ISP2401 */ +#include "ia_css_queue.h" + +#include "ia_css_isp_params.h" + +#include "system_local.h" +#include "assert_support.h" +#include "print_support.h" + +#include "fifo_monitor.h" + +#include "input_formatter.h" +#include "dma.h" +#include "irq.h" +#include "gp_device.h" +#include "sp.h" +#include "isp.h" +#include "type_support.h" +#include "math_support.h" /* CEIL_DIV */ +#include "input_system.h" /* input_formatter_reg_load */ +#include "ia_css_tagger_common.h" + +#include "sh_css_internal.h" +#include "ia_css_isys.h" +#include "sh_css_sp.h" /* sh_css_sp_get_debug_state() */ + +#include "css_trace.h" /* tracer */ + +#include "device_access.h" /* for ia_css_device_load_uint32 */ + +/* Include all kernel host interfaces for ISP1 */ +#include "anr/anr_1.0/ia_css_anr.host.h" +#include "cnr/cnr_1.0/ia_css_cnr.host.h" +#include "csc/csc_1.0/ia_css_csc.host.h" +#include "de/de_1.0/ia_css_de.host.h" +#include "dp/dp_1.0/ia_css_dp.host.h" +#include "bnr/bnr_1.0/ia_css_bnr.host.h" +#include "fpn/fpn_1.0/ia_css_fpn.host.h" +#include "gc/gc_1.0/ia_css_gc.host.h" +#include "ob/ob_1.0/ia_css_ob.host.h" +#include "s3a/s3a_1.0/ia_css_s3a.host.h" +#include "sc/sc_1.0/ia_css_sc.host.h" +#include "tnr/tnr_1.0/ia_css_tnr.host.h" +#include "uds/uds_1.0/ia_css_uds_param.h" +#include "wb/wb_1.0/ia_css_wb.host.h" +#include "ynr/ynr_1.0/ia_css_ynr.host.h" + +/* Include additional kernel host interfaces for ISP2 */ +#include "aa/aa_2/ia_css_aa2.host.h" +#include "anr/anr_2/ia_css_anr2.host.h" +#include "cnr/cnr_2/ia_css_cnr2.host.h" +#include "de/de_2/ia_css_de2.host.h" +#include "gc/gc_2/ia_css_gc2.host.h" +#include "ynr/ynr_2/ia_css_ynr2.host.h" + +#define DPG_START "ia_css_debug_pipe_graph_dump_start " +#define DPG_END " ia_css_debug_pipe_graph_dump_end\n" + +#define ENABLE_LINE_MAX_LENGTH (25) + +/* + * TODO:SH_CSS_MAX_SP_THREADS is not the max number of sp threads + * future rework should fix this and remove the define MAX_THREAD_NUM + */ +#define MAX_THREAD_NUM (SH_CSS_MAX_SP_THREADS + SH_CSS_MAX_SP_INTERNAL_THREADS) + +static struct pipe_graph_class { + bool do_init; + int height; + int width; + int eff_height; + int eff_width; + enum atomisp_input_format stream_format; +} pg_inst = {true, 0, 0, 0, 0, N_ATOMISP_INPUT_FORMAT}; + +static const char *const queue_id_to_str[] = { + /* [SH_CSS_QUEUE_A_ID] =*/ "queue_A", + /* [SH_CSS_QUEUE_B_ID] =*/ "queue_B", + /* [SH_CSS_QUEUE_C_ID] =*/ "queue_C", + /* [SH_CSS_QUEUE_D_ID] =*/ "queue_D", + /* [SH_CSS_QUEUE_E_ID] =*/ "queue_E", + /* [SH_CSS_QUEUE_F_ID] =*/ "queue_F", + /* [SH_CSS_QUEUE_G_ID] =*/ "queue_G", + /* [SH_CSS_QUEUE_H_ID] =*/ "queue_H" +}; + +static const char *const pipe_id_to_str[] = { + /* [IA_CSS_PIPE_ID_PREVIEW] =*/ "preview", + /* [IA_CSS_PIPE_ID_COPY] =*/ "copy", + /* [IA_CSS_PIPE_ID_VIDEO] =*/ "video", + /* [IA_CSS_PIPE_ID_CAPTURE] =*/ "capture", + /* [IA_CSS_PIPE_ID_YUVPP] =*/ "yuvpp", +}; + +static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME + 10]; +static char ring_buffer[200]; + +void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + ia_css_debug_vdtrace(level, fmt, ap); + va_end(ap); +} + +static void debug_dump_long_array_formatted( + const sp_ID_t sp_id, + hrt_address stack_sp_addr, + unsigned int stack_size) +{ + unsigned int i; + u32 val; + u32 addr = (uint32_t)stack_sp_addr; + u32 stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t)); + + /* When size is not multiple of four, last word is only relevant for + * remaining bytes */ + for (i = 0; i < stack_size_words; i++) { + val = sp_dmem_load_uint32(sp_id, (hrt_address)addr); + if ((i % 8) == 0) + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n"); + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "0x%08x ", val); + addr += sizeof(uint32_t); + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n"); +} + +static void debug_dump_sp_stack_info( + const sp_ID_t sp_id) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_threads_stack; + unsigned int HIVE_ADDR_sp_threads_stack_size; + u32 stack_sizes[MAX_THREAD_NUM]; + u32 stack_sp_addr[MAX_THREAD_NUM]; + unsigned int i; + + fw = &sh_css_sp_fw; + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "sp_id(%u) stack info\n", sp_id); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "from objects stack_addr_offset:0x%x stack_size_offset:0x%x\n", + fw->info.sp.threads_stack, + fw->info.sp.threads_stack_size); + + HIVE_ADDR_sp_threads_stack = fw->info.sp.threads_stack; + HIVE_ADDR_sp_threads_stack_size = fw->info.sp.threads_stack_size; + + if (fw->info.sp.threads_stack == 0 || + fw->info.sp.threads_stack_size == 0) + return; + + (void)HIVE_ADDR_sp_threads_stack; + (void)HIVE_ADDR_sp_threads_stack_size; + + sp_dmem_load(sp_id, + (unsigned int)sp_address_of(sp_threads_stack), + &stack_sp_addr, sizeof(stack_sp_addr)); + sp_dmem_load(sp_id, + (unsigned int)sp_address_of(sp_threads_stack_size), + &stack_sizes, sizeof(stack_sizes)); + + for (i = 0 ; i < MAX_THREAD_NUM; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "thread: %u stack_addr: 0x%08x stack_size: %u\n", + i, stack_sp_addr[i], stack_sizes[i]); + debug_dump_long_array_formatted(sp_id, (hrt_address)stack_sp_addr[i], + stack_sizes[i]); + } +} + +void ia_css_debug_dump_sp_stack_info(void) +{ + debug_dump_sp_stack_info(SP0_ID); +} + +void ia_css_debug_set_dtrace_level(const unsigned int trace_level) +{ + dbg_level = trace_level; + return; +} + +unsigned int ia_css_debug_get_dtrace_level(void) +{ + return dbg_level; +} + +static const char *debug_stream_format2str(const enum atomisp_input_format + stream_format) +{ + switch (stream_format) { + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: + return "yuv420-8-legacy"; + case ATOMISP_INPUT_FORMAT_YUV420_8: + return "yuv420-8"; + case ATOMISP_INPUT_FORMAT_YUV420_10: + return "yuv420-10"; + case ATOMISP_INPUT_FORMAT_YUV420_16: + return "yuv420-16"; + case ATOMISP_INPUT_FORMAT_YUV422_8: + return "yuv422-8"; + case ATOMISP_INPUT_FORMAT_YUV422_10: + return "yuv422-10"; + case ATOMISP_INPUT_FORMAT_YUV422_16: + return "yuv422-16"; + case ATOMISP_INPUT_FORMAT_RGB_444: + return "rgb444"; + case ATOMISP_INPUT_FORMAT_RGB_555: + return "rgb555"; + case ATOMISP_INPUT_FORMAT_RGB_565: + return "rgb565"; + case ATOMISP_INPUT_FORMAT_RGB_666: + return "rgb666"; + case ATOMISP_INPUT_FORMAT_RGB_888: + return "rgb888"; + case ATOMISP_INPUT_FORMAT_RAW_6: + return "raw6"; + case ATOMISP_INPUT_FORMAT_RAW_7: + return "raw7"; + case ATOMISP_INPUT_FORMAT_RAW_8: + return "raw8"; + case ATOMISP_INPUT_FORMAT_RAW_10: + return "raw10"; + case ATOMISP_INPUT_FORMAT_RAW_12: + return "raw12"; + case ATOMISP_INPUT_FORMAT_RAW_14: + return "raw14"; + case ATOMISP_INPUT_FORMAT_RAW_16: + return "raw16"; + case ATOMISP_INPUT_FORMAT_BINARY_8: + return "binary8"; + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT1: + return "generic-short1"; + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT2: + return "generic-short2"; + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT3: + return "generic-short3"; + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT4: + return "generic-short4"; + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT5: + return "generic-short5"; + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT6: + return "generic-short6"; + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT7: + return "generic-short7"; + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT8: + return "generic-short8"; + case ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT: + return "yuv420-8-shift"; + case ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT: + return "yuv420-10-shift"; + case ATOMISP_INPUT_FORMAT_EMBEDDED: + return "embedded-8"; + case ATOMISP_INPUT_FORMAT_USER_DEF1: + return "user-def-8-type-1"; + case ATOMISP_INPUT_FORMAT_USER_DEF2: + return "user-def-8-type-2"; + case ATOMISP_INPUT_FORMAT_USER_DEF3: + return "user-def-8-type-3"; + case ATOMISP_INPUT_FORMAT_USER_DEF4: + return "user-def-8-type-4"; + case ATOMISP_INPUT_FORMAT_USER_DEF5: + return "user-def-8-type-5"; + case ATOMISP_INPUT_FORMAT_USER_DEF6: + return "user-def-8-type-6"; + case ATOMISP_INPUT_FORMAT_USER_DEF7: + return "user-def-8-type-7"; + case ATOMISP_INPUT_FORMAT_USER_DEF8: + return "user-def-8-type-8"; + + default: + assert(!"Unknown stream format"); + return "unknown-stream-format"; + } +}; + +static const char *debug_frame_format2str(const enum ia_css_frame_format + frame_format) +{ + switch (frame_format) { + case IA_CSS_FRAME_FORMAT_NV11: + return "NV11"; + case IA_CSS_FRAME_FORMAT_NV12: + return "NV12"; + case IA_CSS_FRAME_FORMAT_NV12_16: + return "NV12_16"; + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + return "NV12_TILEY"; + case IA_CSS_FRAME_FORMAT_NV16: + return "NV16"; + case IA_CSS_FRAME_FORMAT_NV21: + return "NV21"; + case IA_CSS_FRAME_FORMAT_NV61: + return "NV61"; + case IA_CSS_FRAME_FORMAT_YV12: + return "YV12"; + case IA_CSS_FRAME_FORMAT_YV16: + return "YV16"; + case IA_CSS_FRAME_FORMAT_YUV420: + return "YUV420"; + case IA_CSS_FRAME_FORMAT_YUV420_16: + return "YUV420_16"; + case IA_CSS_FRAME_FORMAT_YUV422: + return "YUV422"; + case IA_CSS_FRAME_FORMAT_YUV422_16: + return "YUV422_16"; + case IA_CSS_FRAME_FORMAT_UYVY: + return "UYVY"; + case IA_CSS_FRAME_FORMAT_YUYV: + return "YUYV"; + case IA_CSS_FRAME_FORMAT_YUV444: + return "YUV444"; + case IA_CSS_FRAME_FORMAT_YUV_LINE: + return "YUV_LINE"; + case IA_CSS_FRAME_FORMAT_RAW: + return "RAW"; + case IA_CSS_FRAME_FORMAT_RGB565: + return "RGB565"; + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + return "PLANAR_RGB888"; + case IA_CSS_FRAME_FORMAT_RGBA888: + return "RGBA888"; + case IA_CSS_FRAME_FORMAT_QPLANE6: + return "QPLANE6"; + case IA_CSS_FRAME_FORMAT_BINARY_8: + return "BINARY_8"; + case IA_CSS_FRAME_FORMAT_MIPI: + return "MIPI"; + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + return "RAW_PACKED"; + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + return "CSI_MIPI_YUV420_8"; + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + return "CSI_MIPI_LEGACY_YUV420_8"; + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10: + return "CSI_MIPI_YUV420_10"; + + default: + assert(!"Unknown frame format"); + return "unknown-frame-format"; + } +} + +static void debug_print_sp_state(const sp_state_t *state, const char *cell) +{ + assert(cell); + assert(state); + + ia_css_debug_dtrace(2, "%s state:\n", cell); + ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc); + ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register", + state->status_register); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping", + state->is_sleeping); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling", + state->is_stalling); + return; +} + +static void debug_print_isp_state(const isp_state_t *state, const char *cell) +{ + assert(state); + assert(cell); + + ia_css_debug_dtrace(2, "%s state:\n", cell); + ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc); + ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register", + state->status_register); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping", + state->is_sleeping); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling", + state->is_stalling); + return; +} + +void ia_css_debug_dump_isp_state(void) +{ + isp_state_t state; + isp_stall_t stall; + + isp_get_state(ISP0_ID, &state, &stall); + + debug_print_isp_state(&state, "ISP"); + + if (state.is_stalling) { + if (!IS_ISP2401) { + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "[0] if_prim_a_FIFO stalled", stall.fifo0); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "[1] if_prim_b_FIFO stalled", stall.fifo1); + } + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[2] dma_FIFO stalled", + stall.fifo2); + + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[3] gdc0_FIFO stalled", + stall.fifo3); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[4] gdc1_FIFO stalled", + stall.fifo4); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[5] gpio_FIFO stalled", + stall.fifo5); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[6] sp_FIFO stalled", + stall.fifo6); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "status & control stalled", + stall.stat_ctrl); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled", + stall.dmem); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vmem stalled", + stall.vmem); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem1 stalled", + stall.vamem1); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem2 stalled", + stall.vamem2); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem3 stalled", + stall.vamem3); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "hmem stalled", + stall.hmem); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "pmem stalled", + stall.pmem); + } + return; +} + +void ia_css_debug_dump_sp_state(void) +{ + sp_state_t state; + sp_stall_t stall; + + sp_get_state(SP0_ID, &state, &stall); + debug_print_sp_state(&state, "SP"); + if (state.is_stalling) { + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isys_FIFO stalled", + stall.fifo0); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "if_sec_FIFO stalled", + stall.fifo1); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "str_to_mem_FIFO stalled", stall.fifo2); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dma_FIFO stalled", + stall.fifo3); + if (!IS_ISP2401) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "if_prim_a_FIFO stalled", stall.fifo4); + + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isp_FIFO stalled", + stall.fifo5); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gp_FIFO stalled", + stall.fifo6); + if (!IS_ISP2401) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "if_prim_b_FIFO stalled", stall.fifo7); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc0_FIFO stalled", + stall.fifo8); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc1_FIFO stalled", + stall.fifo9); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "irq FIFO stalled", + stall.fifoa); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled", + stall.dmem); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "control master stalled", + stall.control_master); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "i-cache master stalled", + stall.icache_master); + } + ia_css_debug_dump_trace(); + return; +} + +static void debug_print_fifo_channel_state(const fifo_channel_state_t *state, + const char *descr) +{ + assert(state); + assert(descr); + + ia_css_debug_dtrace(2, "FIFO channel: %s\n", descr); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "source valid", + state->src_valid); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo accept", + state->fifo_accept); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo valid", + state->fifo_valid); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "sink accept", + state->sink_accept); + return; +} + +void ia_css_debug_dump_pif_a_isp_fifo_state(void) +{ + fifo_channel_state_t pif_to_isp, isp_to_pif; + + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_IF0_TO_ISP0, &pif_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_IF0, &isp_to_pif); + debug_print_fifo_channel_state(&pif_to_isp, "Primary IF A to ISP"); + debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF A"); +} + +void ia_css_debug_dump_pif_b_isp_fifo_state(void) +{ + fifo_channel_state_t pif_to_isp, isp_to_pif; + + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_IF1_TO_ISP0, &pif_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_IF1, &isp_to_pif); + debug_print_fifo_channel_state(&pif_to_isp, "Primary IF B to ISP"); + debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF B"); +} + +void ia_css_debug_dump_str2mem_sp_fifo_state(void) +{ + fifo_channel_state_t s2m_to_sp, sp_to_s2m; + + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_STREAM2MEM0_TO_SP0, &s2m_to_sp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_SP0_TO_STREAM2MEM0, &sp_to_s2m); + debug_print_fifo_channel_state(&s2m_to_sp, "Stream-to-memory to SP"); + debug_print_fifo_channel_state(&sp_to_s2m, "SP to stream-to-memory"); +} + +#ifndef ISP2401 +static void debug_print_if_state(input_formatter_state_t *state, const char *id) +{ + unsigned int val; + + const char *st_vsync_active_low = + (state->vsync_active_low ? "low" : "high"); + const char *st_hsync_active_low = + (state->hsync_active_low ? "low" : "high"); + + const char *fsm_sync_status_str = "unknown"; + const char *fsm_crop_status_str = "unknown"; + const char *fsm_padding_status_str = "unknown"; + + int st_stline = state->start_line; + int st_stcol = state->start_column; + int st_crpht = state->cropped_height; + int st_crpwd = state->cropped_width; + int st_verdcm = state->ver_decimation; + int st_hordcm = state->hor_decimation; + int st_ver_deinterleaving = state->ver_deinterleaving; + int st_hor_deinterleaving = state->hor_deinterleaving; + int st_leftpd = state->left_padding; + int st_eoloff = state->eol_offset; + int st_vmstartaddr = state->vmem_start_address; + int st_vmendaddr = state->vmem_end_address; + int st_vmincr = state->vmem_increment; + int st_yuv420 = state->is_yuv420; + int st_allow_fifo_overflow = state->allow_fifo_overflow; + int st_block_fifo_when_no_req = state->block_fifo_when_no_req; + + assert(state); + ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id); + + ia_css_debug_dtrace(2, "\tConfiguration:\n"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start line", st_stline); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start column", st_stcol); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped height", st_crpht); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped width", st_crpwd); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Ver decimation", st_verdcm); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Hor decimation", st_hordcm); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Ver deinterleaving", st_ver_deinterleaving); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Hor deinterleaving", st_hor_deinterleaving); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Left padding", st_leftpd); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "EOL offset (bytes)", st_eoloff); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", + "VMEM start address", st_vmstartaddr); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", + "VMEM end address", st_vmendaddr); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", + "VMEM increment", st_vmincr); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "YUV 420 format", st_yuv420); + ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n", + "Vsync", st_vsync_active_low); + ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n", + "Hsync", st_hsync_active_low); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Allow FIFO overflow", st_allow_fifo_overflow); + /* Flag that tells whether the IF gives backpressure on frames */ + /* + * FYI, this is only on the frame request (indicate), when the IF has + * synch'd on a frame it will always give back pressure + */ + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Block when no request", st_block_fifo_when_no_req); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "IF_BLOCKED_FIFO_NO_REQ_ADDRESS", + input_formatter_reg_load(INPUT_FORMATTER0_ID, + HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS) + ); + + ia_css_debug_dtrace(2, "\t%-32s:\n", "InputSwitch State"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg0", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg0)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg1", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg1)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg2", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg2)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg3", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg3)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg4", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg4)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg5", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg5)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg6", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg6)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg7", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg7)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_fsync_lut", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_fsync_lut)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_srst", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_srst)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_slv_reg_srst", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_slv_reg_srst)); + + ia_css_debug_dtrace(2, "\tFSM Status:\n"); + + val = state->fsm_sync_status; + + if (val > 7) + fsm_sync_status_str = "ERROR"; + + switch (val & 0x7) { + case 0: + fsm_sync_status_str = "idle"; + break; + case 1: + fsm_sync_status_str = "request frame"; + break; + case 2: + fsm_sync_status_str = "request lines"; + break; + case 3: + fsm_sync_status_str = "request vectors"; + break; + case 4: + fsm_sync_status_str = "send acknowledge"; + break; + default: + fsm_sync_status_str = "unknown"; + break; + } + + ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", + "FSM Synchronization Status", val, + fsm_sync_status_str); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Synchronization Counter", + state->fsm_sync_counter); + + val = state->fsm_crop_status; + + if (val > 7) + fsm_crop_status_str = "ERROR"; + + switch (val & 0x7) { + case 0: + fsm_crop_status_str = "idle"; + break; + case 1: + fsm_crop_status_str = "wait line"; + break; + case 2: + fsm_crop_status_str = "crop line"; + break; + case 3: + fsm_crop_status_str = "crop pixel"; + break; + case 4: + fsm_crop_status_str = "pass pixel"; + break; + case 5: + fsm_crop_status_str = "pass line"; + break; + case 6: + fsm_crop_status_str = "lost line"; + break; + default: + fsm_crop_status_str = "unknown"; + break; + } + ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", + "FSM Crop Status", val, fsm_crop_status_str); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Crop Line Counter", + state->fsm_crop_line_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Crop Pixel Counter", + state->fsm_crop_pixel_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Deinterleaving idx buffer", + state->fsm_deinterleaving_index); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM H decimation counter", + state->fsm_dec_h_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM V decimation counter", + state->fsm_dec_v_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM block V decimation counter", + state->fsm_dec_block_v_counter); + + val = state->fsm_padding_status; + + if (val > 7) + fsm_padding_status_str = "ERROR"; + + switch (val & 0x7) { + case 0: + fsm_padding_status_str = "idle"; + break; + case 1: + fsm_padding_status_str = "left pad"; + break; + case 2: + fsm_padding_status_str = "write"; + break; + case 3: + fsm_padding_status_str = "right pad"; + break; + case 4: + fsm_padding_status_str = "send end of line"; + break; + default: + fsm_padding_status_str = "unknown"; + break; + } + + ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", "FSM Padding Status", + val, fsm_padding_status_str); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Padding element idx counter", + state->fsm_padding_elem_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support error", + state->fsm_vector_support_error); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support buf full", + state->fsm_vector_buffer_full); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support", + state->vector_support); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Fifo sensor data lost", + state->sensor_data_lost); +} + +static void debug_print_if_bin_state(input_formatter_bin_state_t *state) +{ + ia_css_debug_dtrace(2, "Stream-to-memory state:\n"); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "reset", state->reset); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "input endianness", + state->input_endianness); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "output endianness", + state->output_endianness); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "bitswap", state->bitswap); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "block_synch", + state->block_synch); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "packet_synch", + state->packet_synch); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "readpostwrite_sync", + state->readpostwrite_synch); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "is_2ppc", state->is_2ppc); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "en_status_update", + state->en_status_update); +} + +static void ia_css_debug_dump_if_state(void) +{ + input_formatter_state_t if_state; + input_formatter_bin_state_t if_bin_state; + + input_formatter_get_state(INPUT_FORMATTER0_ID, &if_state); + debug_print_if_state(&if_state, "Primary IF A"); + ia_css_debug_dump_pif_a_isp_fifo_state(); + + input_formatter_get_state(INPUT_FORMATTER1_ID, &if_state); + debug_print_if_state(&if_state, "Primary IF B"); + ia_css_debug_dump_pif_b_isp_fifo_state(); + + input_formatter_bin_get_state(INPUT_FORMATTER3_ID, &if_bin_state); + debug_print_if_bin_state(&if_bin_state); + ia_css_debug_dump_str2mem_sp_fifo_state(); +} +#endif + +void ia_css_debug_dump_dma_state(void) +{ + /* note: the var below is made static as it is quite large; + if it is not static it ends up on the stack which could + cause issues for drivers + */ + static dma_state_t state; + int i, ch_id; + + const char *fsm_cmd_st_lbl = "FSM Command flag state"; + const char *fsm_ctl_st_lbl = "FSM Control flag state"; + const char *fsm_ctl_state = NULL; + const char *fsm_ctl_flag = NULL; + const char *fsm_pack_st = NULL; + const char *fsm_read_st = NULL; + const char *fsm_write_st = NULL; + char last_cmd_str[64]; + + dma_get_state(DMA0_ID, &state); + /* Print header for DMA dump status */ + ia_css_debug_dtrace(2, "DMA dump status:\n"); + + /* Print FSM command flag state */ + if (state.fsm_command_idle) + ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "IDLE"); + if (state.fsm_command_run) + ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "RUN"); + if (state.fsm_command_stalling) + ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, + "STALL"); + if (state.fsm_command_error) + ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, + "ERROR"); + + /* Print last command along with the channel */ + ch_id = state.last_command_channel; + + switch (state.last_command) { + case DMA_COMMAND_READ: + snprintf(last_cmd_str, 64, + "Read 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_WRITE: + snprintf(last_cmd_str, 64, + "Write 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_SET_CHANNEL: + snprintf(last_cmd_str, 64, "Set Channel [Channel: %d]", ch_id); + break; + case DMA_COMMAND_SET_PARAM: + snprintf(last_cmd_str, 64, + "Set Param: %d [Channel: %d]", + state.last_command_param, ch_id); + break; + case DMA_COMMAND_READ_SPECIFIC: + snprintf(last_cmd_str, 64, + "Read Specific 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_WRITE_SPECIFIC: + snprintf(last_cmd_str, 64, + "Write Specific 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_INIT: + snprintf(last_cmd_str, 64, + "Init 2D Block on Device A [Channel: %d]", ch_id); + break; + case DMA_COMMAND_INIT_SPECIFIC: + snprintf(last_cmd_str, 64, + "Init Specific 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_RST: + snprintf(last_cmd_str, 64, "DMA SW Reset"); + break; + case N_DMA_COMMANDS: + snprintf(last_cmd_str, 64, "UNKNOWN"); + break; + default: + snprintf(last_cmd_str, 64, + "unknown [Channel: %d]", ch_id); + break; + } + ia_css_debug_dtrace(2, "\t%-32s: (0x%X : %s)\n", + "last command received", state.last_command, + last_cmd_str); + + /* Print DMA registers */ + ia_css_debug_dtrace(2, "\t%-32s\n", + "DMA registers, connection group 0"); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Command", + state.current_command); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address A", + state.current_addr_a); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address B", + state.current_addr_b); + + if (state.fsm_ctrl_idle) + fsm_ctl_flag = "IDLE"; + else if (state.fsm_ctrl_run) + fsm_ctl_flag = "RUN"; + else if (state.fsm_ctrl_stalling) + fsm_ctl_flag = "STAL"; + else if (state.fsm_ctrl_error) + fsm_ctl_flag = "ERROR"; + else + fsm_ctl_flag = "UNKNOWN"; + + switch (state.fsm_ctrl_state) { + case DMA_CTRL_STATE_IDLE: + fsm_ctl_state = "Idle state"; + break; + case DMA_CTRL_STATE_REQ_RCV: + fsm_ctl_state = "Req Rcv state"; + break; + case DMA_CTRL_STATE_RCV: + fsm_ctl_state = "Rcv state"; + break; + case DMA_CTRL_STATE_RCV_REQ: + fsm_ctl_state = "Rcv Req state"; + break; + case DMA_CTRL_STATE_INIT: + fsm_ctl_state = "Init state"; + break; + case N_DMA_CTRL_STATES: + fsm_ctl_state = "Unknown"; + break; + } + + ia_css_debug_dtrace(2, "\t\t%-32s: %s -> %s\n", fsm_ctl_st_lbl, + fsm_ctl_flag, fsm_ctl_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source dev", + state.fsm_ctrl_source_dev); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source addr", + state.fsm_ctrl_source_addr); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source stride", + state.fsm_ctrl_source_stride); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source width", + state.fsm_ctrl_source_width); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source height", + state.fsm_ctrl_source_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source dev", + state.fsm_ctrl_pack_source_dev); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest dev", + state.fsm_ctrl_pack_dest_dev); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest addr", + state.fsm_ctrl_dest_addr); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest stride", + state.fsm_ctrl_dest_stride); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source width", + state.fsm_ctrl_pack_source_width); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest height", + state.fsm_ctrl_pack_dest_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest width", + state.fsm_ctrl_pack_dest_width); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source elems", + state.fsm_ctrl_pack_source_elems); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest elems", + state.fsm_ctrl_pack_dest_elems); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack extension", + state.fsm_ctrl_pack_extension); + + if (state.pack_idle) + fsm_pack_st = "IDLE"; + if (state.pack_run) + fsm_pack_st = "RUN"; + if (state.pack_stalling) + fsm_pack_st = "STALL"; + if (state.pack_error) + fsm_pack_st = "ERROR"; + + ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Pack flag state", + fsm_pack_st); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack cnt height", + state.pack_cnt_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack src cnt width", + state.pack_src_cnt_width); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack dest cnt width", + state.pack_dest_cnt_width); + + if (state.read_state == DMA_RW_STATE_IDLE) + fsm_read_st = "Idle state"; + if (state.read_state == DMA_RW_STATE_REQ) + fsm_read_st = "Req state"; + if (state.read_state == DMA_RW_STATE_NEXT_LINE) + fsm_read_st = "Next line"; + if (state.read_state == DMA_RW_STATE_UNLOCK_CHANNEL) + fsm_read_st = "Unlock channel"; + + ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Read state", + fsm_read_st); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt height", + state.read_cnt_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt width", + state.read_cnt_width); + + if (state.write_state == DMA_RW_STATE_IDLE) + fsm_write_st = "Idle state"; + if (state.write_state == DMA_RW_STATE_REQ) + fsm_write_st = "Req state"; + if (state.write_state == DMA_RW_STATE_NEXT_LINE) + fsm_write_st = "Next line"; + if (state.write_state == DMA_RW_STATE_UNLOCK_CHANNEL) + fsm_write_st = "Unlock channel"; + + ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Write state", + fsm_write_st); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write height", + state.write_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write width", + state.write_width); + + for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) { + dma_port_state_t *port = &state.port_states[i]; + + ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i); + ia_css_debug_dtrace(2, "\t\tDMA internal side state\n"); + ia_css_debug_dtrace(2, + "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n", + port->req_cs, port->req_we_n, port->req_run, + port->req_ack); + ia_css_debug_dtrace(2, "\t\tMaster Output side state\n"); + ia_css_debug_dtrace(2, + "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n", + port->send_cs, port->send_we_n, + port->send_run, port->send_ack); + ia_css_debug_dtrace(2, "\t\tFifo state\n"); + if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL) + ia_css_debug_dtrace(2, "\t\t\tFiFo will be full\n"); + else if (port->fifo_state == DMA_FIFO_STATE_FULL) + ia_css_debug_dtrace(2, "\t\t\tFifo Full\n"); + else if (port->fifo_state == DMA_FIFO_STATE_EMPTY) + ia_css_debug_dtrace(2, "\t\t\tFifo Empty\n"); + else + ia_css_debug_dtrace(2, "\t\t\tFifo state unknown\n"); + + ia_css_debug_dtrace(2, "\t\tFifo counter %d\n\n", + port->fifo_counter); + } + + for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) { + dma_channel_state_t *ch = &state.channel_states[i]; + + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register", + i); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection", + ch->connection); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Sign extend", + ch->sign_extend); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev A", + ch->stride_a); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev A", + ch->elems_a); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev A", + ch->cropping_a); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev A", + ch->width_a); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev B", + ch->stride_b); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev B", + ch->elems_b); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev B", + ch->cropping_b); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev B", + ch->width_b); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Height", ch->height); + } + ia_css_debug_dtrace(2, "\n"); + return; +} + +void ia_css_debug_dump_dma_sp_fifo_state(void) +{ + fifo_channel_state_t dma_to_sp, sp_to_dma; + + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_SP0_TO_DMA0, &sp_to_dma); + debug_print_fifo_channel_state(&dma_to_sp, "DMA to SP"); + debug_print_fifo_channel_state(&sp_to_dma, "SP to DMA"); + return; +} + +void ia_css_debug_dump_dma_isp_fifo_state(void) +{ + fifo_channel_state_t dma_to_isp, isp_to_dma; + + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_DMA0, &isp_to_dma); + debug_print_fifo_channel_state(&dma_to_isp, "DMA to ISP"); + debug_print_fifo_channel_state(&isp_to_dma, "ISP to DMA"); + return; +} + +void ia_css_debug_dump_isp_sp_fifo_state(void) +{ + fifo_channel_state_t sp_to_isp, isp_to_sp; + + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_SP0, &isp_to_sp); + debug_print_fifo_channel_state(&sp_to_isp, "SP to ISP"); + debug_print_fifo_channel_state(&isp_to_sp, "ISP to SP"); + return; +} + +void ia_css_debug_dump_isp_gdc_fifo_state(void) +{ + fifo_channel_state_t gdc_to_isp, isp_to_gdc; + + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_GDC0_TO_ISP0, &gdc_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_GDC0, &isp_to_gdc); + debug_print_fifo_channel_state(&gdc_to_isp, "GDC to ISP"); + debug_print_fifo_channel_state(&isp_to_gdc, "ISP to GDC"); + return; +} + +void ia_css_debug_dump_all_fifo_state(void) +{ + int i; + fifo_monitor_state_t state; + + fifo_monitor_get_state(FIFO_MONITOR0_ID, &state); + + for (i = 0; i < N_FIFO_CHANNEL; i++) + debug_print_fifo_channel_state(&state.fifo_channels[i], + "squepfstqkt"); + return; +} + +static void debug_binary_info_print(const struct ia_css_binary_xinfo *info) +{ + assert(info); + ia_css_debug_dtrace(2, "id = %d\n", info->sp.id); + ia_css_debug_dtrace(2, "mode = %d\n", info->sp.pipeline.mode); + ia_css_debug_dtrace(2, "max_input_width = %d\n", info->sp.input.max_width); + ia_css_debug_dtrace(2, "min_output_width = %d\n", + info->sp.output.min_width); + ia_css_debug_dtrace(2, "max_output_width = %d\n", + info->sp.output.max_width); + ia_css_debug_dtrace(2, "top_cropping = %d\n", info->sp.pipeline.top_cropping); + ia_css_debug_dtrace(2, "left_cropping = %d\n", info->sp.pipeline.left_cropping); + ia_css_debug_dtrace(2, "xmem_addr = %d\n", info->xmem_addr); + ia_css_debug_dtrace(2, "enable_vf_veceven = %d\n", + info->sp.enable.vf_veceven); + ia_css_debug_dtrace(2, "enable_dis = %d\n", info->sp.enable.dis); + ia_css_debug_dtrace(2, "enable_uds = %d\n", info->sp.enable.uds); + ia_css_debug_dtrace(2, "enable ds = %d\n", info->sp.enable.ds); + ia_css_debug_dtrace(2, "s3atbl_use_dmem = %d\n", info->sp.s3a.s3atbl_use_dmem); + return; +} + +void ia_css_debug_binary_print(const struct ia_css_binary *bi) +{ + unsigned int i; + + debug_binary_info_print(bi->info); + ia_css_debug_dtrace(2, + "input: %dx%d, format = %d, padded width = %d\n", + bi->in_frame_info.res.width, + bi->in_frame_info.res.height, + bi->in_frame_info.format, + bi->in_frame_info.padded_width); + ia_css_debug_dtrace(2, + "internal :%dx%d, format = %d, padded width = %d\n", + bi->internal_frame_info.res.width, + bi->internal_frame_info.res.height, + bi->internal_frame_info.format, + bi->internal_frame_info.padded_width); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (bi->out_frame_info[i].res.width != 0) { + ia_css_debug_dtrace(2, + "out%d: %dx%d, format = %d, padded width = %d\n", + i, + bi->out_frame_info[i].res.width, + bi->out_frame_info[i].res.height, + bi->out_frame_info[i].format, + bi->out_frame_info[i].padded_width); + } + } + ia_css_debug_dtrace(2, + "vf out: %dx%d, format = %d, padded width = %d\n", + bi->vf_frame_info.res.width, + bi->vf_frame_info.res.height, + bi->vf_frame_info.format, + bi->vf_frame_info.padded_width); + ia_css_debug_dtrace(2, "online = %d\n", bi->online); + ia_css_debug_dtrace(2, "input_buf_vectors = %d\n", + bi->input_buf_vectors); + ia_css_debug_dtrace(2, "deci_factor_log2 = %d\n", bi->deci_factor_log2); + ia_css_debug_dtrace(2, "vf_downscale_log2 = %d\n", + bi->vf_downscale_log2); + ia_css_debug_dtrace(2, "dis_deci_factor_log2 = %d\n", + bi->dis.deci_factor_log2); + ia_css_debug_dtrace(2, "dis hor coef num = %d\n", + bi->dis.coef.pad.width); + ia_css_debug_dtrace(2, "dis ver coef num = %d\n", + bi->dis.coef.pad.height); + ia_css_debug_dtrace(2, "dis hor proj num = %d\n", + bi->dis.proj.pad.height); + ia_css_debug_dtrace(2, "sctbl_width_per_color = %d\n", + bi->sctbl_width_per_color); + ia_css_debug_dtrace(2, "s3atbl_width = %d\n", bi->s3atbl_width); + ia_css_debug_dtrace(2, "s3atbl_height = %d\n", bi->s3atbl_height); + return; +} + +void ia_css_debug_frame_print(const struct ia_css_frame *frame, + const char *descr) +{ + char *data = NULL; + + assert(frame); + assert(descr); + + data = (char *)HOST_ADDRESS(frame->data); + ia_css_debug_dtrace(2, "frame %s (%p):\n", descr, frame); + ia_css_debug_dtrace(2, " resolution = %dx%d\n", + frame->frame_info.res.width, frame->frame_info.res.height); + ia_css_debug_dtrace(2, " padded width = %d\n", + frame->frame_info.padded_width); + ia_css_debug_dtrace(2, " format = %d\n", frame->frame_info.format); + switch (frame->frame_info.format) { + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV61: + ia_css_debug_dtrace(2, " Y = %p\n", + data + frame->planes.nv.y.offset); + ia_css_debug_dtrace(2, " UV = %p\n", + data + frame->planes.nv.uv.offset); + break; + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + ia_css_debug_dtrace(2, " YUYV = %p\n", + data + frame->planes.yuyv.offset); + break; + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUV422: + case IA_CSS_FRAME_FORMAT_YUV444: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_YV16: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_YUV422_16: + ia_css_debug_dtrace(2, " Y = %p\n", + data + frame->planes.yuv.y.offset); + ia_css_debug_dtrace(2, " U = %p\n", + data + frame->planes.yuv.u.offset); + ia_css_debug_dtrace(2, " V = %p\n", + data + frame->planes.yuv.v.offset); + break; + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + ia_css_debug_dtrace(2, " RAW PACKED = %p\n", + data + frame->planes.raw.offset); + break; + case IA_CSS_FRAME_FORMAT_RAW: + ia_css_debug_dtrace(2, " RAW = %p\n", + data + frame->planes.raw.offset); + break; + case IA_CSS_FRAME_FORMAT_RGBA888: + case IA_CSS_FRAME_FORMAT_RGB565: + ia_css_debug_dtrace(2, " RGB = %p\n", + data + frame->planes.rgb.offset); + break; + case IA_CSS_FRAME_FORMAT_QPLANE6: + ia_css_debug_dtrace(2, " R = %p\n", + data + frame->planes.plane6.r.offset); + ia_css_debug_dtrace(2, " RatB = %p\n", + data + frame->planes.plane6.r_at_b.offset); + ia_css_debug_dtrace(2, " Gr = %p\n", + data + frame->planes.plane6.gr.offset); + ia_css_debug_dtrace(2, " Gb = %p\n", + data + frame->planes.plane6.gb.offset); + ia_css_debug_dtrace(2, " B = %p\n", + data + frame->planes.plane6.b.offset); + ia_css_debug_dtrace(2, " BatR = %p\n", + data + frame->planes.plane6.b_at_r.offset); + break; + case IA_CSS_FRAME_FORMAT_BINARY_8: + ia_css_debug_dtrace(2, " Binary data = %p\n", + data + frame->planes.binary.data.offset); + break; + default: + ia_css_debug_dtrace(2, " unknown frame type\n"); + break; + } + return; +} + +#if SP_DEBUG != SP_DEBUG_NONE + +void ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state + *state) +{ +#endif + +#if SP_DEBUG == SP_DEBUG_DUMP + + assert(state); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "current SP software counter: %d\n", + state->debug[0]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty output buffer queue head: 0x%x\n", + state->debug[1]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty output buffer queue tail: 0x%x\n", + state->debug[2]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a buffer queue head: 0x%x\n", + state->debug[3]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a buffer queue tail: 0x%x\n", + state->debug[4]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "full output buffer queue head: 0x%x\n", + state->debug[5]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "full output buffer queue tail: 0x%x\n", + state->debug[6]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "full s3a buffer queue head: 0x%x\n", + state->debug[7]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "full s3a buffer queue tail: 0x%x\n", + state->debug[8]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue head: 0x%x\n", + state->debug[9]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue tail: 0x%x\n", + state->debug[10]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "num of stages of current pipeline: 0x%x\n", + state->debug[11]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 1: 0x%x\n", + state->debug[12]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 2: 0x%x\n", + state->debug[13]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "current stage out_vf buffer idx: 0x%x\n", + state->debug[14]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "current stage output buffer idx: 0x%x\n", + state->debug[15]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "current stage s3a buffer idx: 0x%x\n", + state->debug[16]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first char of current stage name: 0x%x\n", + state->debug[17]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "current SP thread id: 0x%x\n", + state->debug[18]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty output buffer address 1: 0x%x\n", + state->debug[19]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty output buffer address 2: 0x%x\n", + state->debug[20]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty out_vf buffer address 1: 0x%x\n", + state->debug[21]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty out_vf buffer address 2: 0x%x\n", + state->debug[22]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a_hi buffer address 1: 0x%x\n", + state->debug[23]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a_hi buffer address 2: 0x%x\n", + state->debug[24]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a_lo buffer address 1: 0x%x\n", + state->debug[25]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a_lo buffer address 2: 0x%x\n", + state->debug[26]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty dis_hor buffer address 1: 0x%x\n", + state->debug[27]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty dis_hor buffer address 2: 0x%x\n", + state->debug[28]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty dis_ver buffer address 1: 0x%x\n", + state->debug[29]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty dis_ver buffer address 2: 0x%x\n", + state->debug[30]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty param buffer address: 0x%x\n", + state->debug[31]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect frame address: 0x%x\n", + state->debug[32]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect frame container address: 0x%x\n", + state->debug[33]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect frame container payload: 0x%x\n", + state->debug[34]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_hi address: 0x%x\n", + state->debug[35]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_hi container address: 0x%x\n", + state->debug[36]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_hi container payload: 0x%x\n", + state->debug[37]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_lo address: 0x%x\n", + state->debug[38]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_lo container address: 0x%x\n", + state->debug[39]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_lo container payload: 0x%x\n", + state->debug[40]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "number of calling flash start function: 0x%x\n", + state->debug[41]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "number of calling flash close function: 0x%x\n", + state->debug[42]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "number of flashed frame: 0x%x\n", + state->debug[43]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "flash in use flag: 0x%x\n", + state->debug[44]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "number of update frame flashed flag: 0x%x\n", + state->debug[46]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "number of active threads: 0x%x\n", + state->debug[45]); + +#elif SP_DEBUG == SP_DEBUG_COPY + + /* Remember last_index because we only want to print new entries */ + static int last_index; + int sp_index = state->index; + int n; + + assert(state); + if (sp_index < last_index) { + /* SP has been reset */ + last_index = 0; + } + + if (last_index == 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "copy-trace init: sp_dbg_if_start_line=%d, sp_dbg_if_start_column=%d, sp_dbg_if_cropped_height=%d, sp_debg_if_cropped_width=%d\n", + state->if_start_line, + state->if_start_column, + state->if_cropped_height, + state->if_cropped_width); + } + + if ((last_index + SH_CSS_SP_DBG_TRACE_DEPTH) < sp_index) { + /* last index can be multiple rounds behind */ + /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */ + last_index = sp_index - SH_CSS_SP_DBG_TRACE_DEPTH; + } + + for (n = last_index; n < sp_index; n++) { + int i = n % SH_CSS_SP_DBG_TRACE_DEPTH; + + if (state->trace[i].frame != 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "copy-trace: frame=%d, line=%d, pixel_distance=%d, mipi_used_dword=%d, sp_index=%d\n", + state->trace[i].frame, + state->trace[i].line, + state->trace[i].pixel_distance, + state->trace[i].mipi_used_dword, + state->trace[i].sp_index); + } + } + + last_index = sp_index; + +#elif SP_DEBUG == SP_DEBUG_TRACE + + /* + * This is just an example how TRACE_FILE_ID (see ia_css_debug.sp.h) will + * me mapped on the file name string. + * + * Adjust this to your trace case! + */ + static char const *const id2filename[8] = { + "param_buffer.sp.c | tagger.sp.c | pipe_data.sp.c", + "isp_init.sp.c", + "sp_raw_copy.hive.c", + "dma_configure.sp.c", + "sp.hive.c", + "event_proxy_sp.hive.c", + "circular_buffer.sp.c", + "frame_buffer.sp.c" + }; + + /* Example SH_CSS_SP_DBG_NR_OF_TRACES==1 */ + /* Adjust this to your trace case */ + static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = { + "default" + }; + + /* Remember host_index_last because we only want to print new entries */ + static int host_index_last[SH_CSS_SP_DBG_NR_OF_TRACES] = { 0 }; + int t, n; + + assert(state); + + for (t = 0; t < SH_CSS_SP_DBG_NR_OF_TRACES; t++) { + int sp_index_last = state->index_last[t]; + + if (sp_index_last < host_index_last[t]) { + /* SP has been reset */ + host_index_last[t] = 0; + } + + if ((host_index_last[t] + SH_CSS_SP_DBG_TRACE_DEPTH) < + sp_index_last) { + /* last index can be multiple rounds behind */ + /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */ + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "Warning: trace %s has gap of %d traces\n", + trace_name[t], + (sp_index_last - + (host_index_last[t] + + SH_CSS_SP_DBG_TRACE_DEPTH))); + + host_index_last[t] = + sp_index_last - SH_CSS_SP_DBG_TRACE_DEPTH; + } + + for (n = host_index_last[t]; n < sp_index_last; n++) { + int i = n % SH_CSS_SP_DBG_TRACE_DEPTH; + int l = state->trace[t][i].location & + ((1 << SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS) - 1); + int fid = state->trace[t][i].location >> + SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS; + int ts = state->trace[t][i].time_stamp; + + if (ts) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "%05d trace=%s, file=%s:%d, data=0x%08x\n", + ts, + trace_name[t], + id2filename[fid], l, + state->trace[t][i].data); + } + } + host_index_last[t] = sp_index_last; + } + +#elif SP_DEBUG == SP_DEBUG_MINIMAL + int i; + int base = 0; + int limit = SH_CSS_NUM_SP_DEBUG; + int step = 1; + + assert(state); + + for (i = base; i < limit; i += step) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "sp_dbg_trace[%d] = %d\n", + i, state->debug[i]); + } +#endif + +#if SP_DEBUG != SP_DEBUG_NONE + + return; +} +#endif + +#if !defined(ISP2401) +static void debug_print_rx_mipi_port_state(mipi_port_state_t *state) +{ + int i; + unsigned int bits, infos; + + assert(state); + + bits = state->irq_status; + infos = ia_css_isys_rx_translate_irq_infos(bits); + + ia_css_debug_dtrace(2, "\t\t%-32s: (irq reg = 0x%X)\n", + "receiver errors", bits); + + if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN) + ia_css_debug_dtrace(2, "\t\t\tbuffer overrun\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT) + ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC) + ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission sync error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL) + ia_css_debug_dtrace(2, "\t\t\tcontrol error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) + ia_css_debug_dtrace(2, "\t\t\t2 or more ECC errors\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC) + ia_css_debug_dtrace(2, "\t\t\tCRC mismatch\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) + ia_css_debug_dtrace(2, "\t\t\tunknown error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) + ia_css_debug_dtrace(2, "\t\t\tframe sync error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA) + ia_css_debug_dtrace(2, "\t\t\tframe data error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) + ia_css_debug_dtrace(2, "\t\t\tdata timeout\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) + ia_css_debug_dtrace(2, "\t\t\tunknown escape command entry\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC) + ia_css_debug_dtrace(2, "\t\t\tline sync error\n"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "device_ready", state->device_ready); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_status", state->irq_status); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_enable", state->irq_enable); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "timeout_count", state->timeout_count); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "init_count", state->init_count); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16_18", state->raw16_18); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "sync_count", state->sync_count); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "rx_count", state->rx_count); + + for (i = 0; i < MIPI_4LANE_CFG; i++) { + ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n", + "lane_sync_count[", i, "]", + state->lane_sync_count[i]); + } + + for (i = 0; i < MIPI_4LANE_CFG; i++) { + ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n", + "lane_rx_count[", i, "]", + state->lane_rx_count[i]); + } + + return; +} + +static void debug_print_rx_channel_state(rx_channel_state_t *state) +{ + int i; + + assert(state); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "compression_scheme0", state->comp_scheme0); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "compression_scheme1", state->comp_scheme1); + + for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) { + ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n", + "MIPI Predictor ", i, state->pred[i]); + } + + for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) { + ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n", + "MIPI Compressor ", i, state->comp[i]); + } + + return; +} + +static void debug_print_rx_state(receiver_state_t *state) +{ + int i; + + assert(state); + ia_css_debug_dtrace(2, "CSI Receiver State:\n"); + + ia_css_debug_dtrace(2, "\tConfiguration:\n"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "fs_to_ls_delay", state->fs_to_ls_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "ls_to_data_delay", state->ls_to_data_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "data_to_le_delay", state->data_to_le_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "le_to_fe_delay", state->le_to_fe_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "fe_to_fs_delay", state->fe_to_fs_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "le_to_fs_delay", state->le_to_fs_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "is_two_ppc", state->is_two_ppc); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "backend_rst", state->backend_rst); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw18", state->raw18); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "force_raw8", state->force_raw8); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16", state->raw16); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_gsp_acc_ovl", state->be_gsp_acc_ovl); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_srst", state->be_srst); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_is_two_ppc", state->be_is_two_ppc); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_comp_format0", state->be_comp_format0); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_comp_format1", state->be_comp_format1); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_comp_format2", state->be_comp_format2); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_comp_format3", state->be_comp_format3); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_sel", state->be_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_raw16_config", state->be_raw16_config); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_raw18_config", state->be_raw18_config); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_force_raw8", state->be_force_raw8); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_irq_status", state->be_irq_status); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_irq_clear", state->be_irq_clear); + + /* mipi port state */ + for (i = 0; i < N_MIPI_PORT_ID; i++) { + ia_css_debug_dtrace(2, "\tMIPI Port %d State:\n", i); + + debug_print_rx_mipi_port_state(&state->mipi_port_state[i]); + } + /* end of mipi port state */ + + /* rx channel state */ + for (i = 0; i < N_RX_CHANNEL_ID; i++) { + ia_css_debug_dtrace(2, "\tRX Channel %d State:\n", i); + + debug_print_rx_channel_state(&state->rx_channel_state[i]); + } + /* end of rx channel state */ + + return; +} +#endif + +void ia_css_debug_dump_rx_state(void) +{ +#if !defined(ISP2401) + receiver_state_t state; + + receiver_get_state(RX0_ID, &state); + debug_print_rx_state(&state); +#endif +} + +void ia_css_debug_dump_sp_sw_debug_info(void) +{ +#if SP_DEBUG != SP_DEBUG_NONE + struct sh_css_sp_debug_state state; + + sh_css_sp_get_debug_state(&state); + ia_css_debug_print_sp_debug_state(&state); +#endif + ia_css_bufq_dump_queue_info(); + ia_css_pipeline_dump_thread_map_info(); + return; +} + +#if !defined(ISP2401) +static void debug_print_isys_capture_unit_state(capture_unit_state_t *state) +{ + assert(state); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Packet_Length", state->Packet_Length); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Length", state->Received_Length); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Short_Packets", + state->Received_Short_Packets); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Long_Packets", + state->Received_Long_Packets); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Last_Command", state->Last_Command); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Next_Command", state->Next_Command); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Last_Acknowledge", state->Last_Acknowledge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Next_Acknowledge", state->Next_Acknowledge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM_State_Info", state->FSM_State_Info); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "StartMode", state->StartMode); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Start_Addr", state->Start_Addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Mem_Region_Size", state->Mem_Region_Size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Num_Mem_Regions", state->Num_Mem_Regions); + return; +} + +static void debug_print_isys_acquisition_unit_state( + acquisition_unit_state_t *state) +{ + assert(state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Short_Packets", + state->Received_Short_Packets); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Long_Packets", + state->Received_Long_Packets); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Last_Command", state->Last_Command); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Next_Command", state->Next_Command); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Last_Acknowledge", state->Last_Acknowledge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Next_Acknowledge", state->Next_Acknowledge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM_State_Info", state->FSM_State_Info); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Int_Cntr_Info", state->Int_Cntr_Info); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Start_Addr", state->Start_Addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Mem_Region_Size", state->Mem_Region_Size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Num_Mem_Regions", state->Num_Mem_Regions); +} + +static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state) +{ + assert(state); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_cmd", state->last_cmd); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_cmd", state->next_cmd); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_ack", state->last_ack); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_ack", state->next_ack); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "top_fsm_state", state->top_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captA_fsm_state", state->captA_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captB_fsm_state", state->captB_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captC_fsm_state", state->captC_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "acq_fsm_state", state->acq_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captA_start_addr", state->captA_start_addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captB_start_addr", state->captB_start_addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captC_start_addr", state->captC_start_addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captA_mem_region_size", + state->captA_mem_region_size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captB_mem_region_size", + state->captB_mem_region_size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captC_mem_region_size", + state->captC_mem_region_size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captA_num_mem_regions", + state->captA_num_mem_regions); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captB_num_mem_regions", + state->captB_num_mem_regions); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captC_num_mem_regions", + state->captC_num_mem_regions); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "acq_start_addr", state->acq_start_addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "acq_mem_region_size", state->acq_mem_region_size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "acq_num_mem_regions", state->acq_num_mem_regions); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "capt_reserve_one_mem_region", + state->capt_reserve_one_mem_region); + + return; +} + +static void debug_print_isys_state(input_system_state_t *state) +{ + int i; + + assert(state); + ia_css_debug_dtrace(2, "InputSystem State:\n"); + + /* configuration */ + ia_css_debug_dtrace(2, "\tConfiguration:\n"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_multiCastA_sel", state->str_multicastA_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_multicastB_sel", state->str_multicastB_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_multicastC_sel", state->str_multicastC_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_mux_sel", state->str_mux_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_mon_status", state->str_mon_status); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_mon_irq_cond", state->str_mon_irq_cond); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_mon_irq_en", state->str_mon_irq_en); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "isys_srst", state->isys_srst); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "isys_slv_reg_srst", state->isys_slv_reg_srst); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_deint_portA_cnt", state->str_deint_portA_cnt); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_deint_portB_cnd", state->str_deint_portB_cnt); + /* end of configuration */ + + /* capture unit state */ + for (i = 0; i < N_CAPTURE_UNIT_ID; i++) { + capture_unit_state_t *capture_unit_state; + + ia_css_debug_dtrace(2, "\tCaptureUnit %d State:\n", i); + + capture_unit_state = &state->capture_unit[i]; + debug_print_isys_capture_unit_state(capture_unit_state); + } + /* end of capture unit state */ + + /* acquisition unit state */ + for (i = 0; i < N_ACQUISITION_UNIT_ID; i++) { + acquisition_unit_state_t *acquisition_unit_state; + + ia_css_debug_dtrace(2, "\tAcquisitionUnit %d State:\n", i); + + acquisition_unit_state = &state->acquisition_unit[i]; + debug_print_isys_acquisition_unit_state(acquisition_unit_state); + } + /* end of acquisition unit state */ + + /* control unit state */ + for (i = 0; i < N_CTRL_UNIT_ID; i++) { + ia_css_debug_dtrace(2, "\tControlUnit %d State:\n", i); + + debug_print_isys_ctrl_unit_state(&state->ctrl_unit_state[i]); + } + /* end of control unit state */ +} +#endif + +void ia_css_debug_dump_isys_state(void) +{ + static input_system_state_t state; + + input_system_get_state(INPUT_SYSTEM0_ID, &state); + +#ifndef ISP2401 + debug_print_isys_state(&state); +#else + input_system_dump_state(INPUT_SYSTEM0_ID, &state); +#endif +} + +void ia_css_debug_dump_debug_info(const char *context) +{ + if (!context) + context = "No Context provided"; + + ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context); + if (!IS_ISP2401) + ia_css_debug_dump_rx_state(); + +#ifndef ISP2401 + ia_css_debug_dump_if_state(); +#endif + ia_css_debug_dump_isp_state(); + ia_css_debug_dump_isp_sp_fifo_state(); + ia_css_debug_dump_isp_gdc_fifo_state(); + ia_css_debug_dump_sp_state(); + ia_css_debug_dump_perf_counters(); + +#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG + sh_css_dump_thread_wait_info(); + sh_css_dump_pipe_stage_info(); + sh_css_dump_pipe_stripe_info(); +#endif + ia_css_debug_dump_dma_isp_fifo_state(); + ia_css_debug_dump_dma_sp_fifo_state(); + ia_css_debug_dump_dma_state(); + + if (!IS_ISP2401) { + struct irq_controller_state state; + + ia_css_debug_dump_isys_state(); + + irq_controller_get_state(IRQ2_ID, &state); + + ia_css_debug_dtrace(2, "\t%-32s:\n", + "Input System IRQ Controller State"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_edge", state.irq_edge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_mask", state.irq_mask); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_status", state.irq_status); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_enable", state.irq_enable); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_level_not_pulse", + state.irq_level_not_pulse); + } else { + ia_css_debug_dump_isys_state(); + } + + ia_css_debug_tagger_state(); + + return; +} + +/* this function is for debug use, it can make SP go to sleep + state after each frame, then user can dump the stable SP dmem. + this function can be called after ia_css_start_sp() + and before sh_css_init_buffer_queues() +*/ +void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_sleep_mode; + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode; + + (void)HIVE_ADDR_sp_sleep_mode; /* Suppres warnings in CRUN */ + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(sp_sleep_mode), + (uint32_t)mode); +} + +void ia_css_debug_wake_up_sp(void) +{ + /*hrt_ctl_start(SP); */ + sp_ctrl_setbit(SP0_ID, SP_SC_REG, SP_START_BIT); +} + +#define FIND_DMEM_PARAMS_TYPE(stream, kernel, type) \ + (struct HRTCAT(HRTCAT(sh_css_isp_, type), _params) *) \ + findf_dmem_params(stream, offsetof(struct ia_css_memory_offsets, dmem.kernel)) + +#define FIND_DMEM_PARAMS(stream, kernel) FIND_DMEM_PARAMS_TYPE(stream, kernel, kernel) + +/* Find a stage that support the kernel and return the parameters for that kernel */ +static char * +findf_dmem_params(struct ia_css_stream *stream, short idx) +{ + int i; + + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *pipe = stream->pipes[i]; + struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe); + struct ia_css_pipeline_stage *stage; + + for (stage = pipeline->stages; stage; stage = stage->next) { + struct ia_css_binary *binary = stage->binary; + short *offsets = (short *)&binary->info->mem_offsets.offsets.param->dmem; + short dmem_offset = offsets[idx]; + const struct ia_css_host_data *isp_data = + ia_css_isp_param_get_mem_init(&binary->mem_params, + IA_CSS_PARAM_CLASS_PARAM, IA_CSS_ISP_DMEM0); + if (dmem_offset < 0) + continue; + return &isp_data->address[dmem_offset]; + } + } + return NULL; +} + +void ia_css_debug_dump_isp_params(struct ia_css_stream *stream, + unsigned int enable) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "ISP PARAMETERS:\n"); + + assert(stream); + if ((enable & IA_CSS_DEBUG_DUMP_FPN) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_fpn_dump(FIND_DMEM_PARAMS(stream, fpn), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_OB) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_ob_dump(FIND_DMEM_PARAMS(stream, ob), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_SC) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_sc_dump(FIND_DMEM_PARAMS(stream, sc), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_WB) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_wb_dump(FIND_DMEM_PARAMS(stream, wb), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_DP) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_dp_dump(FIND_DMEM_PARAMS(stream, dp), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_BNR) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_bnr_dump(FIND_DMEM_PARAMS(stream, bnr), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_S3A) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_s3a_dump(FIND_DMEM_PARAMS(stream, s3a), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_DE) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_de_dump(FIND_DMEM_PARAMS(stream, de), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_YNR) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_nr_dump(FIND_DMEM_PARAMS_TYPE(stream, nr, ynr), IA_CSS_DEBUG_VERBOSE); + ia_css_yee_dump(FIND_DMEM_PARAMS(stream, yee), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_CSC) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_csc_dump(FIND_DMEM_PARAMS(stream, csc), IA_CSS_DEBUG_VERBOSE); + ia_css_yuv2rgb_dump(FIND_DMEM_PARAMS_TYPE(stream, yuv2rgb, csc), + IA_CSS_DEBUG_VERBOSE); + ia_css_rgb2yuv_dump(FIND_DMEM_PARAMS_TYPE(stream, rgb2yuv, csc), + IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_GC) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_gc_dump(FIND_DMEM_PARAMS(stream, gc), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_TNR) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_tnr_dump(FIND_DMEM_PARAMS(stream, tnr), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_ANR) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_anr_dump(FIND_DMEM_PARAMS(stream, anr), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_CE) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_ce_dump(FIND_DMEM_PARAMS(stream, ce), IA_CSS_DEBUG_VERBOSE); + } +} + +void sh_css_dump_sp_raw_copy_linecount(bool reduced) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_raw_copy_line_count; + s32 raw_copy_line_count; + static s32 prev_raw_copy_line_count = -1; + + fw = &sh_css_sp_fw; + HIVE_ADDR_raw_copy_line_count = + fw->info.sp.raw_copy_line_count; + + (void)HIVE_ADDR_raw_copy_line_count; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(raw_copy_line_count), + &raw_copy_line_count, + sizeof(raw_copy_line_count)); + + /* only indicate if copy loop is active */ + if (reduced) + raw_copy_line_count = (raw_copy_line_count < 0) ? raw_copy_line_count : 1; + /* do the handling */ + if (prev_raw_copy_line_count != raw_copy_line_count) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "sh_css_dump_sp_raw_copy_linecount() line_count=%d\n", + raw_copy_line_count); + prev_raw_copy_line_count = raw_copy_line_count; + } +} + +void ia_css_debug_dump_isp_binary(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_pipeline_sp_curr_binary_id; + u32 curr_binary_id; + static u32 prev_binary_id = 0xFFFFFFFF; + static u32 sample_count; + + fw = &sh_css_sp_fw; + HIVE_ADDR_pipeline_sp_curr_binary_id = fw->info.sp.curr_binary_id; + + (void)HIVE_ADDR_pipeline_sp_curr_binary_id; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(pipeline_sp_curr_binary_id), + &curr_binary_id, + sizeof(curr_binary_id)); + + /* do the handling */ + sample_count++; + if (prev_binary_id != curr_binary_id) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "sh_css_dump_isp_binary() pipe_id=%d, binary_id=%d, sample_count=%d\n", + (curr_binary_id >> 16), + (curr_binary_id & 0x0ffff), + sample_count); + sample_count = 0; + prev_binary_id = curr_binary_id; + } +} + +void ia_css_debug_dump_perf_counters(void) +{ + const struct ia_css_fw_info *fw; + int i; + unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt; + /* N_MIPI_PORT_ID + 1: 3 Capture Units and 1 Acquire Unit. */ + s32 ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1]; + + if (IS_ISP2401) + return; + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_ia_css_isys_sp_error_cnt = + fw->info.sp.perf_counter_input_system_error; + + (void)HIVE_ADDR_ia_css_isys_sp_error_cnt; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(ia_css_isys_sp_error_cnt), + &ia_css_sp_input_system_error_cnt, + sizeof(ia_css_sp_input_system_error_cnt)); + + for (i = 0; i < N_MIPI_PORT_ID + 1; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\tport[%d] = %d\n", + i, ia_css_sp_input_system_error_cnt[i]); + } +} + +/* + * @brief Initialize the debug mode. + * Refer to "ia_css_debug.h" for more details. + */ +bool ia_css_debug_mode_init(void) +{ + bool rc; + + rc = sh_css_sp_init_dma_sw_reg(0); + return rc; +} + +/* + * @brief Disable the DMA channel. + * Refer to "ia_css_debug.h" for more details. + */ +bool +ia_css_debug_mode_disable_dma_channel(int dma_id, + int channel_id, int request_type) +{ + bool rc; + + rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, false); + + return rc; +} + +/* + * @brief Enable the DMA channel. + * Refer to "ia_css_debug.h" for more details. + */ +bool +ia_css_debug_mode_enable_dma_channel(int dma_id, + int channel_id, int request_type) +{ + bool rc; + + rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, true); + + return rc; +} + +static void __printf(1, 2) dtrace_dot(const char *fmt, ...) +{ + va_list ap; + + assert(fmt); + va_start(ap, fmt); + + ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START); + ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap); + ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END); + va_end(ap); +} + +#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG +void sh_css_dump_thread_wait_info(void) +{ + const struct ia_css_fw_info *fw; + int i; + unsigned int HIVE_ADDR_sp_thread_wait; + s32 sp_thread_wait[MAX_THREAD_NUM]; + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "SEM WAITS:\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_thread_wait = + fw->info.sp.debug_wait; + + (void)HIVE_ADDR_sp_thread_wait; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_thread_wait), + &sp_thread_wait, + sizeof(sp_thread_wait)); + for (i = 0; i < MAX_THREAD_NUM; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "\twait[%d] = 0x%X\n", + i, sp_thread_wait[i]); + } +} + +void sh_css_dump_pipe_stage_info(void) +{ + const struct ia_css_fw_info *fw; + int i; + unsigned int HIVE_ADDR_sp_pipe_stage; + s32 sp_pipe_stage[MAX_THREAD_NUM]; + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STAGE:\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_pipe_stage = + fw->info.sp.debug_stage; + + (void)HIVE_ADDR_sp_pipe_stage; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_pipe_stage), + &sp_pipe_stage, + sizeof(sp_pipe_stage)); + for (i = 0; i < MAX_THREAD_NUM; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "\tstage[%d] = %d\n", + i, sp_pipe_stage[i]); + } +} + +void sh_css_dump_pipe_stripe_info(void) +{ + const struct ia_css_fw_info *fw; + int i; + unsigned int HIVE_ADDR_sp_pipe_stripe; + s32 sp_pipe_stripe[MAX_THREAD_NUM]; + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STRIPE:\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_pipe_stripe = + fw->info.sp.debug_stripe; + + (void)HIVE_ADDR_sp_pipe_stripe; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_pipe_stripe), + &sp_pipe_stripe, + sizeof(sp_pipe_stripe)); + for (i = 0; i < MAX_THREAD_NUM; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "\tstripe[%d] = %d\n", + i, sp_pipe_stripe[i]); + } +} +#endif + +static void +ia_css_debug_pipe_graph_dump_frame( + const struct ia_css_frame *frame, + enum ia_css_pipe_id id, + char const *blob_name, + char const *frame_name, + bool in_frame) +{ + char bufinfo[100]; + + if (frame->dynamic_queue_id == SH_CSS_INVALID_QUEUE_ID) { + snprintf(bufinfo, sizeof(bufinfo), "Internal"); + } else { + snprintf(bufinfo, sizeof(bufinfo), "Queue: %s %s", + pipe_id_to_str[id], + queue_id_to_str[frame->dynamic_queue_id]); + } + dtrace_dot( + "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];", + frame, + debug_frame_format2str(frame->frame_info.format), + frame->frame_info.res.width, + frame->frame_info.padded_width, + frame->frame_info.res.height, + frame->frame_info.raw_bit_depth, + bufinfo); + + if (in_frame) { + dtrace_dot( + "\"%p\"->\"%s(pipe%d)\" [label = %s_frame];", + frame, + blob_name, id, frame_name); + } else { + dtrace_dot( + "\"%s(pipe%d)\"->\"%p\" [label = %s_frame];", + blob_name, id, + frame, + frame_name); + } +} + +void +ia_css_debug_pipe_graph_dump_prologue(void) +{ + dtrace_dot("digraph sh_css_pipe_graph {"); + dtrace_dot("rankdir=LR;"); + + dtrace_dot("fontsize=9;"); + dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, fbds=fixed_bayer_ds, bf6=bayer_fir_6db, rawb=raw_binning, cont=continuous, disc=dis_crop\\n" + "dp2a=dp_2adjacent, outp=output, outt=out_table, reff=ref_frame, par=params, gam=gamma, cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, outf=out_frame, hs=high_speed, inpc=input_chunking\""); +} + +void ia_css_debug_pipe_graph_dump_epilogue(void) +{ + if (strlen(ring_buffer) > 0) { + dtrace_dot(ring_buffer); + } + + if (pg_inst.stream_format != N_ATOMISP_INPUT_FORMAT) { + /* An input stream format has been set so assume we have + * an input system and sensor + */ + + dtrace_dot( + "node [shape = doublecircle, fixedsize=true, width=2.5]; \"input_system\" [label = \"Input system\"];"); + + dtrace_dot( + "\"input_system\"->\"%s\" [label = \"%s\"];", + dot_id_input_bin, debug_stream_format2str(pg_inst.stream_format)); + + dtrace_dot( + "node [shape = doublecircle, fixedsize=true, width=2.5]; \"sensor\" [label = \"Sensor\"];"); + + dtrace_dot( + "\"sensor\"->\"input_system\" [label = \"%s\\n%d x %d\\n(%d x %d)\"];", + debug_stream_format2str(pg_inst.stream_format), + pg_inst.width, pg_inst.height, + pg_inst.eff_width, pg_inst.eff_height); + } + + dtrace_dot("}"); + + /* Reset temp strings */ + memset(dot_id_input_bin, 0, sizeof(dot_id_input_bin)); + memset(ring_buffer, 0, sizeof(ring_buffer)); + + pg_inst.do_init = true; + pg_inst.width = 0; + pg_inst.height = 0; + pg_inst.eff_width = 0; + pg_inst.eff_height = 0; + pg_inst.stream_format = N_ATOMISP_INPUT_FORMAT; +} + +void +ia_css_debug_pipe_graph_dump_stage( + struct ia_css_pipeline_stage *stage, + enum ia_css_pipe_id id) +{ + char blob_name[SH_CSS_MAX_BINARY_NAME + 10] = ""; + char const *bin_type = ""; + int i; + + assert(stage); + if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC) + return; + + if (pg_inst.do_init) { + ia_css_debug_pipe_graph_dump_prologue(); + pg_inst.do_init = false; + } + + if (stage->binary) { + bin_type = "binary"; + if (stage->binary->info->blob) + snprintf(blob_name, sizeof(blob_name), "%s_stage%d", + stage->binary->info->blob->name, stage->stage_num); + } else if (stage->firmware) { + bin_type = "firmware"; + + strscpy(blob_name, IA_CSS_EXT_ISP_PROG_NAME(stage->firmware), + sizeof(blob_name)); + } + + /* Guard in case of binaries that don't have any binary_info */ + if (stage->binary_info) { + char enable_info1[100]; + char enable_info2[100]; + char enable_info3[100]; + char enable_info[200]; + struct ia_css_binary_info *bi = stage->binary_info; + + /* Split it in 2 function-calls to keep the amount of + * parameters per call "reasonable" + */ + snprintf(enable_info1, sizeof(enable_info1), + "%s%s%s%s%s%s%s%s%s%s%s%s%s%s", + bi->enable.reduced_pipe ? "rp," : "", + bi->enable.vf_veceven ? "vfve," : "", + bi->enable.dis ? "dis," : "", + bi->enable.dvs_envelope ? "dvse," : "", + bi->enable.uds ? "uds," : "", + bi->enable.dvs_6axis ? "dvs6," : "", + bi->enable.block_output ? "bo," : "", + bi->enable.ds ? "ds," : "", + bi->enable.bayer_fir_6db ? "bf6," : "", + bi->enable.raw_binning ? "rawb," : "", + bi->enable.continuous ? "cont," : "", + bi->enable.s3a ? "s3a," : "", + bi->enable.fpnr ? "fpnr," : "", + bi->enable.sc ? "sc," : "" + ); + + snprintf(enable_info2, sizeof(enable_info2), + "%s%s%s%s%s%s%s%s%s%s%s", + bi->enable.macc ? "macc," : "", + bi->enable.output ? "outp," : "", + bi->enable.ref_frame ? "reff," : "", + bi->enable.tnr ? "tnr," : "", + bi->enable.xnr ? "xnr," : "", + bi->enable.params ? "par," : "", + bi->enable.ca_gdc ? "cagdc," : "", + bi->enable.isp_addresses ? "ispa," : "", + bi->enable.in_frame ? "inf," : "", + bi->enable.out_frame ? "outf," : "", + bi->enable.high_speed ? "hs," : "" + ); + + /* And merge them into one string */ + snprintf(enable_info, sizeof(enable_info), "%s%s", + enable_info1, enable_info2); + { + int l, p; + char *ei = enable_info; + + l = strlen(ei); + + /* Replace last ',' with \0 if present */ + if (l && enable_info[l - 1] == ',') + enable_info[--l] = '\0'; + + if (l > ENABLE_LINE_MAX_LENGTH) { + /* Too big for one line, find last comma */ + p = ENABLE_LINE_MAX_LENGTH; + while (ei[p] != ',') + p--; + /* Last comma found, copy till that comma */ + strscpy(enable_info1, ei, + p > sizeof(enable_info1) ? sizeof(enable_info1) : p); + + ei += p + 1; + l = strlen(ei); + + if (l <= ENABLE_LINE_MAX_LENGTH) { + /* The 2nd line fits */ + /* we cannot use ei as argument because + * it is not guaranteed dword aligned + */ + + strscpy(enable_info2, ei, + l > sizeof(enable_info2) ? sizeof(enable_info2) : l); + + snprintf(enable_info, sizeof(enable_info), "%s\\n%s", + enable_info1, enable_info2); + + } else { + /* 2nd line is still too long */ + p = ENABLE_LINE_MAX_LENGTH; + while (ei[p] != ',') + p--; + + strscpy(enable_info2, ei, + p > sizeof(enable_info2) ? sizeof(enable_info2) : p); + + ei += p + 1; + l = strlen(ei); + + if (l <= ENABLE_LINE_MAX_LENGTH) { + /* The 3rd line fits */ + /* we cannot use ei as argument because + * it is not guaranteed dword aligned + */ + strscpy(enable_info3, ei, + sizeof(enable_info3)); + snprintf(enable_info, sizeof(enable_info), + "%s\\n%s\\n%s", + enable_info1, enable_info2, + enable_info3); + } else { + /* 3rd line is still too long */ + p = ENABLE_LINE_MAX_LENGTH; + while (ei[p] != ',') + p--; + strscpy(enable_info3, ei, + p > sizeof(enable_info3) ? sizeof(enable_info3) : p); + ei += p + 1; + strscpy(enable_info3, ei, + sizeof(enable_info3)); + snprintf(enable_info, sizeof(enable_info), + "%s\\n%s\\n%s", + enable_info1, enable_info2, + enable_info3); + } + } + } + } + + dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"", + bin_type, blob_name, enable_info, blob_name, id); + } else { + dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"", + bin_type, blob_name, blob_name, id); + } + + if (stage->stage_num == 0) { + /* + * There are some implicite assumptions about which bin is the + * input binary e.g. which one is connected to the input system + * Priority: + * 1) sp_raw_copy bin has highest priority + * 2) First stage==0 binary of preview, video or capture + */ + if (strlen(dot_id_input_bin) == 0) { + snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), + "%s(pipe%d)", blob_name, id); + } + } + + if (stage->args.in_frame) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.in_frame, id, blob_name, + "in", true); + } + + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) { + if (stage->args.tnr_frames[i]) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.tnr_frames[i], id, + blob_name, "tnr_frame", true); + } + } + + for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) { + if (stage->args.delay_frames[i]) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.delay_frames[i], id, + blob_name, "delay_frame", true); + } + } + + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (stage->args.out_frame[i]) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.out_frame[i], id, blob_name, + "out", false); + } + } + + if (stage->args.out_vf_frame) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.out_vf_frame, id, blob_name, + "out_vf", false); + } +} + +void +ia_css_debug_pipe_graph_dump_sp_raw_copy( + struct ia_css_frame *out_frame) +{ + assert(out_frame); + if (pg_inst.do_init) { + ia_css_debug_pipe_graph_dump_prologue(); + pg_inst.do_init = false; + } + + dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\"]; \"%s(pipe%d)\"", + "sp-binary", "sp_raw_copy", "sp_raw_copy", 1); + + snprintf(ring_buffer, sizeof(ring_buffer), + "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];", + out_frame, + debug_frame_format2str(out_frame->frame_info.format), + out_frame->frame_info.res.width, + out_frame->frame_info.padded_width, + out_frame->frame_info.res.height); + + dtrace_dot(ring_buffer); + + dtrace_dot( + "\"%s(pipe%d)\"->\"%p\" [label = out_frame];", + "sp_raw_copy", 1, out_frame); + + snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), "%s(pipe%d)", + "sp_raw_copy", 1); +} + +void +ia_css_debug_pipe_graph_dump_stream_config( + const struct ia_css_stream_config *stream_config) +{ + pg_inst.width = stream_config->input_config.input_res.width; + pg_inst.height = stream_config->input_config.input_res.height; + pg_inst.eff_width = stream_config->input_config.effective_res.width; + pg_inst.eff_height = stream_config->input_config.effective_res.height; + pg_inst.stream_format = stream_config->input_config.format; +} + +void +ia_css_debug_dump_resolution( + const struct ia_css_resolution *res, + const char *label) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: =%d x =%d\n", + label, res->width, res->height); +} + +void +ia_css_debug_dump_frame_info( + const struct ia_css_frame_info *info, + const char *label) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", label); + ia_css_debug_dump_resolution(&info->res, "res"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "padded_width: %d\n", + info->padded_width); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", info->format); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bit_depth: %d\n", + info->raw_bit_depth); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bayer_order: %d\n", + info->raw_bayer_order); +} + +void +ia_css_debug_dump_capture_config( + const struct ia_css_capture_config *config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_xnr: %d\n", + config->enable_xnr); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_raw_output: %d\n", + config->enable_raw_output); +} + +void +ia_css_debug_dump_pipe_extra_config( + const struct ia_css_pipe_extra_config *extra_config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); + if (extra_config) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_raw_binning: %d\n", + extra_config->enable_raw_binning); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_yuv_ds: %d\n", + extra_config->enable_yuv_ds); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_high_speed: %d\n", + extra_config->enable_high_speed); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_dvs_6axis: %d\n", + extra_config->enable_dvs_6axis); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_reduced_pipe: %d\n", + extra_config->enable_reduced_pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_fractional_ds: %d\n", + extra_config->enable_fractional_ds); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "disable_vf_pp: %d\n", + extra_config->disable_vf_pp); + } +} + +void +ia_css_debug_dump_pipe_config( + const struct ia_css_pipe_config *config) +{ + unsigned int i; + + IA_CSS_ENTER_PRIVATE("config = %p", config); + if (!config) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE(""); + return; + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "isp_pipe_version: %d\n", + config->isp_pipe_version); + ia_css_debug_dump_resolution(&config->bayer_ds_out_res, + "bayer_ds_out_res"); + ia_css_debug_dump_resolution(&config->capt_pp_in_res, + "capt_pp_in_res"); + ia_css_debug_dump_resolution(&config->vf_pp_in_res, "vf_pp_in_res"); + + if (IS_ISP2401) { + ia_css_debug_dump_resolution(&config->output_system_in_res, + "output_system_in_res"); + } + ia_css_debug_dump_resolution(&config->dvs_crop_out_res, + "dvs_crop_out_res"); + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + ia_css_debug_dump_frame_info(&config->output_info[i], "output_info"); + ia_css_debug_dump_frame_info(&config->vf_output_info[i], + "vf_output_info"); + } + ia_css_debug_dump_capture_config(&config->default_capture_config); + ia_css_debug_dump_resolution(&config->dvs_envelope, "dvs_envelope"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "dvs_frame_delay: %d\n", + config->dvs_frame_delay); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_dz: %d\n", + config->enable_dz); + IA_CSS_LEAVE_PRIVATE(""); +} + +void +ia_css_debug_dump_stream_config_source( + const struct ia_css_stream_config *config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + switch (config->mode) { + case IA_CSS_INPUT_MODE_SENSOR: + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.port\n"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "port: %d\n", + config->source.port.port); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_lanes: %d\n", + config->source.port.num_lanes); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "timeout: %d\n", + config->source.port.timeout); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "compression: %d\n", + config->source.port.compression.type); + break; + case IA_CSS_INPUT_MODE_TPG: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.tpg\n"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n", + config->source.tpg.id); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", + config->source.tpg.mode); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_mask: 0x%x\n", + config->source.tpg.x_mask); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_delta: %d\n", + config->source.tpg.x_delta); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_mask: 0x%x\n", + config->source.tpg.y_mask); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_delta: %d\n", + config->source.tpg.y_delta); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "xy_mask: 0x%x\n", + config->source.tpg.xy_mask); + break; + case IA_CSS_INPUT_MODE_PRBS: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.prbs\n"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n", + config->source.prbs.id); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "h_blank: %d\n", + config->source.prbs.h_blank); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "v_blank: %d\n", + config->source.prbs.v_blank); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed: 0x%x\n", + config->source.prbs.seed); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed1: 0x%x\n", + config->source.prbs.seed1); + break; + default: + case IA_CSS_INPUT_MODE_FIFO: + case IA_CSS_INPUT_MODE_MEMORY: + break; + } +} + +void +ia_css_debug_dump_mipi_buffer_config( + const struct ia_css_mipi_buffer_config *config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "size_mem_words: %d\n", + config->size_mem_words); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "nof_mipi_buffers: %d\n", + config->nof_mipi_buffers); +} + +void +ia_css_debug_dump_metadata_config( + const struct ia_css_metadata_config *config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "data_type: %d\n", + config->data_type); + ia_css_debug_dump_resolution(&config->resolution, "resolution"); +} + +void +ia_css_debug_dump_stream_config( + const struct ia_css_stream_config *config, + int num_pipes) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_pipes: %d\n", num_pipes); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); + ia_css_debug_dump_stream_config_source(config); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "channel_id: %d\n", + config->channel_id); + ia_css_debug_dump_resolution(&config->input_config.input_res, "input_res"); + ia_css_debug_dump_resolution(&config->input_config.effective_res, + "effective_res"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", + config->input_config.format); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "bayer_order: %d\n", + config->input_config.bayer_order); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sensor_binning_factor: %d\n", + config->sensor_binning_factor); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pixels_per_clock: %d\n", + config->pixels_per_clock); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "online: %d\n", + config->online); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "init_num_cont_raw_buf: %d\n", + config->init_num_cont_raw_buf); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "target_num_cont_raw_buf: %d\n", + config->target_num_cont_raw_buf); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pack_raw_pixels: %d\n", + config->pack_raw_pixels); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "continuous: %d\n", + config->continuous); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "flash_gpio_pin: %d\n", + config->flash_gpio_pin); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "left_padding: %d\n", + config->left_padding); + ia_css_debug_dump_mipi_buffer_config(&config->mipi_buffer_config); + ia_css_debug_dump_metadata_config(&config->metadata_config); +} + +/* + Trace support. + + This tracer is using a buffer to trace the flow of the FW and dump misc values (see below for details). + Currently, support is only for SKC. + To enable support for other platforms: + - Allocate a buffer for tracing in DMEM. The longer the better. + - Use the DBG_init routine in sp.hive.c to initiatilize the tracer with the address and size selected. + - Add trace points in the SP code wherever needed. + - Enable the dump below with the required address and required adjustments. + Dump is called at the end of ia_css_debug_dump_sp_state(). +*/ + +/* + dump_trace() : dump the trace points from DMEM2. + for every trace point, the following are printed: index, major:minor and the 16-bit attached value. + The routine looks for the first 0, and then prints from it cyclically. + Data forma in DMEM2: + first 4 DWORDS: header + DWORD 0: data description + byte 0: version + byte 1: number of threads (for future use) + byte 2+3: number ot TPs + DWORD 1: command byte + data (for future use) + byte 0: command + byte 1-3: command signature + DWORD 2-3: additional data (for future use) + Following data is 4-byte oriented: + byte 0: major + byte 1: minor + byte 2-3: data +*/ +#if TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP +static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id) +{ +#if defined(HAS_TRACER_V2) + u32 start_addr; + u32 start_addr_data; + u32 item_size; + u32 tmp; + u8 tid_val; + enum TRACE_DUMP_FORMAT dump_format; + + int i, j, max_trace_points, point_num, limit = -1; + /* using a static buffer here as the driver has issues allocating memory */ + static u32 trace_read_buf[TRACE_BUFF_SIZE] = {0}; + static struct trace_header_t header; + u8 *header_arr; + + /* read the header and parse it */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "~~~ Tracer "); + switch (proc_id) { + case TRACE_SP0_ID: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP0"); + start_addr = TRACE_SP0_ADDR; + start_addr_data = TRACE_SP0_DATA_ADDR; + item_size = TRACE_SP0_ITEM_SIZE; + max_trace_points = TRACE_SP0_MAX_POINTS; + break; + case TRACE_SP1_ID: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP1"); + start_addr = TRACE_SP1_ADDR; + start_addr_data = TRACE_SP1_DATA_ADDR; + item_size = TRACE_SP1_ITEM_SIZE; + max_trace_points = TRACE_SP1_MAX_POINTS; + break; + case TRACE_ISP_ID: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ISP"); + start_addr = TRACE_ISP_ADDR; + start_addr_data = TRACE_ISP_DATA_ADDR; + item_size = TRACE_ISP_ITEM_SIZE; + max_trace_points = TRACE_ISP_MAX_POINTS; + break; + default: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "\t\ttraces are not supported for this processor ID - exiting\n"); + return; + } + + if (!IS_ISP2401) { + tmp = ia_css_device_load_uint32(start_addr); + point_num = (tmp >> 16) & 0xFFFF; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", tmp & 0xFF, + point_num); + } else { + /* Loading byte-by-byte as using the master routine had issues */ + header_arr = (uint8_t *)&header; + for (i = 0; i < (int)sizeof(struct trace_header_t); i++) + header_arr[i] = ia_css_device_load_uint8(start_addr + (i)); + + point_num = header.max_tracer_points; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", header.version, + point_num); + + tmp = header.version; + } + if ((tmp & 0xFF) != TRACER_VER) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tUnknown version - exiting\n"); + return; + } + if (point_num > max_trace_points) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tToo many points - exiting\n"); + return; + } + /* copy the TPs and find the first 0 */ + for (i = 0; i < point_num; i++) { + trace_read_buf[i] = ia_css_device_load_uint32(start_addr_data + + (i * item_size)); + if ((limit == (-1)) && (trace_read_buf[i] == 0)) + limit = i; + } + if (IS_ISP2401) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Status:\n"); + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "\tT%d: %3d (%02x) %6d (%04x) %10d (%08x)\n", i, + header.thr_status_byte[i], header.thr_status_byte[i], + header.thr_status_word[i], header.thr_status_word[i], + header.thr_status_dword[i], header.thr_status_dword[i]); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Scratch:\n"); + for (i = 0; i < MAX_SCRATCH_DATA; i++) + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%10d (%08x) ", + header.scratch_debug[i], header.scratch_debug[i]); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\n"); + } + /* two 0s in the beginning: empty buffer */ + if ((trace_read_buf[0] == 0) && (trace_read_buf[1] == 0)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tEmpty tracer - exiting\n"); + return; + } + /* no overrun: start from 0 */ + if ((limit == point_num - 1) || + /* first 0 is at the end - border case */ + (trace_read_buf[limit + 1] == + 0)) /* did not make a full cycle after the memset */ + limit = 0; + /* overrun: limit is the first non-zero after the first zero */ + else + limit++; + + /* print the TPs */ + for (i = 0; i < point_num; i++) { + j = (limit + i) % point_num; + if (trace_read_buf[j]) { + if (!IS_ISP2401) { + TRACE_DUMP_FORMAT dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]); + } else { + tid_val = FIELD_TID_UNPACK(trace_read_buf[j]); + dump_format = TRACE_DUMP_FORMAT_POINT; + + /* + * When tid value is 111b, the data will be interpreted differently: + * tid val is ignored, major field contains 2 bits (msb) for format type + */ + if (tid_val == FIELD_TID_SEL_FORMAT_PAT) { + dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]); + } + } + switch (dump_format) { + case TRACE_DUMP_FORMAT_POINT: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %d\n", + j, FIELD_MAJOR_UNPACK(trace_read_buf[j]), + FIELD_MINOR_UNPACK(trace_read_buf[j]), + FIELD_VALUE_UNPACK(trace_read_buf[j])); + break; + /* ISP2400 */ + case TRACE_DUMP_FORMAT_VALUE24_HEX: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x H\n", + j, + FIELD_MAJOR_UNPACK(trace_read_buf[j]), + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); + break; + /* ISP2400 */ + case TRACE_DUMP_FORMAT_VALUE24_DEC: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %d D\n", + j, + FIELD_MAJOR_UNPACK(trace_read_buf[j]), + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); + break; + /* ISP2401 */ + case TRACE_DUMP_FORMAT_POINT_NO_TID: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %x (%d)\n", + j, + FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), + FIELD_MINOR_UNPACK(trace_read_buf[j]), + FIELD_VALUE_UNPACK(trace_read_buf[j]), + FIELD_VALUE_UNPACK(trace_read_buf[j])); + break; + /* ISP2401 */ + case TRACE_DUMP_FORMAT_VALUE24: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x (%d)\n", + j, + FIELD_MAJOR_UNPACK(trace_read_buf[j]), + FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), + FIELD_VALUE_24_UNPACK(trace_read_buf[j]), + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); + break; + case TRACE_DUMP_FORMAT_VALUE24_TIMING: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing %x\n", + j, + FIELD_MAJOR_UNPACK(trace_read_buf[j]), + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); + break; + case TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing delta %x\n", + j, + FIELD_MAJOR_UNPACK(trace_read_buf[j]), + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); + break; + default: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, + "no such trace dump format %d", + dump_format); + break; + } + } + } +#else + (void)proc_id; +#endif /* HAS_TRACER_V2 */ +} +#endif /* TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP */ + +void ia_css_debug_dump_trace(void) +{ +#if TRACE_ENABLE_SP0 + debug_dump_one_trace(TRACE_SP0_ID); +#endif +#if TRACE_ENABLE_SP1 + debug_dump_one_trace(TRACE_SP1_ID); +#endif +#if TRACE_ENABLE_ISP + debug_dump_one_trace(TRACE_ISP_ID); +#endif +} + +/* Tagger state dump function. The tagger is only available when the CSS + * contains an input system (2400 or 2401). */ +void ia_css_debug_tagger_state(void) +{ + unsigned int i; + unsigned int HIVE_ADDR_tagger_frames; + ia_css_tagger_buf_sp_elem_t tbuf_frames[MAX_CB_ELEMS_FOR_TAGGER]; + + HIVE_ADDR_tagger_frames = sh_css_sp_fw.info.sp.tagger_frames_addr; + + /* This variable is not used in crun */ + (void)HIVE_ADDR_tagger_frames; + + /* 2400 and 2401 only have 1 SP, so the tagger lives on SP0 */ + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(tagger_frames), + tbuf_frames, + sizeof(tbuf_frames)); + + ia_css_debug_dtrace(2, "Tagger Info:\n"); + for (i = 0; i < MAX_CB_ELEMS_FOR_TAGGER; i++) { + ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n", + i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock); + } +} + +/* ISP2401 */ +void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps) +{ + unsigned int pc; + unsigned int i; + hrt_data sc = sp_ctrl_load(id, SP_SC_REG); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Status reg: 0x%X\n", id, sc); + sc = sp_ctrl_load(id, SP_CTRL_SINK_REG); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Stall reg: 0x%X\n", id, sc); + for (i = 0; i < num_of_dumps; i++) { + pc = sp_ctrl_load(id, SP_PC_REG); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d PC: 0x%X\n", id, pc); + } +} diff --git a/drivers/staging/media/atomisp/pci/runtime/event/interface/ia_css_event.h b/drivers/staging/media/atomisp/pci/runtime/event/interface/ia_css_event.h new file mode 100644 index 000000000..ebbd90b14 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/event/interface/ia_css_event.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_EVENT_H +#define _IA_CSS_EVENT_H + +#include +#include "sw_event_global.h" /*event macros.TODO : Change File Name..???*/ + +bool ia_css_event_encode( + u8 *in, + u8 nr, + uint32_t *out); + +void ia_css_event_decode( + u32 event, + uint8_t *payload); + +#endif /*_IA_CSS_EVENT_H*/ diff --git a/drivers/staging/media/atomisp/pci/runtime/event/src/event.c b/drivers/staging/media/atomisp/pci/runtime/event/src/event.c new file mode 100644 index 000000000..e702297b0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/event/src/event.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "sh_css_sp.h" + +#include "dma.h" /* N_DMA_CHANNEL_ID */ + +#include +#include "ia_css_binary.h" +#include "sh_css_hrt.h" +#include "sh_css_defs.h" +#include "sh_css_internal.h" +#include "ia_css_debug.h" +#include "ia_css_debug_internal.h" +#include "sh_css_legacy.h" + +#include "gdc_device.h" /* HRT_GDC_N */ + +/*#include "sp.h"*/ /* host2sp_enqueue_frame_data() */ + +#include "assert_support.h" + +#include "ia_css_queue.h" /* host_sp_enqueue_XXX */ +#include "ia_css_event.h" /* ia_css_event_encode */ +/* + * @brief Encode the information into the software-event. + * Refer to "sw_event_public.h" for details. + */ +bool ia_css_event_encode( + u8 *in, + u8 nr, + uint32_t *out) +{ + bool ret; + u32 nr_of_bits; + u32 i; + + assert(in); + assert(out); + OP___assert(nr > 0 && nr <= MAX_NR_OF_PAYLOADS_PER_SW_EVENT); + + /* initialize the output */ + *out = 0; + + /* get the number of bits per information */ + nr_of_bits = sizeof(uint32_t) * 8 / nr; + + /* compress the all inputs into a signle output */ + for (i = 0; i < nr; i++) { + *out <<= nr_of_bits; + *out |= in[i]; + } + + /* get the return value */ + ret = (nr > 0 && nr <= MAX_NR_OF_PAYLOADS_PER_SW_EVENT); + + return ret; +} + +void ia_css_event_decode( + u32 event, + uint8_t *payload) +{ + assert(payload[1] == 0); + assert(payload[2] == 0); + assert(payload[3] == 0); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_event_decode() enter:\n"); + + /* First decode according to the common case + * In case of a PORT_EOF event we overwrite with + * the specific values + * This is somewhat ugly but probably somewhat efficient + * (and it avoids some code duplication) + */ + payload[0] = event & 0xff; /*event_code */ + payload[1] = (event >> 8) & 0xff; + payload[2] = (event >> 16) & 0xff; + payload[3] = 0; + + switch (payload[0]) { + case SH_CSS_SP_EVENT_PORT_EOF: + payload[2] = 0; + payload[3] = (event >> 24) & 0xff; + break; + + case SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE: + case SH_CSS_SP_EVENT_TIMER: + case SH_CSS_SP_EVENT_FRAME_TAGGED: + case SH_CSS_SP_EVENT_FW_WARNING: + case SH_CSS_SP_EVENT_FW_ASSERT: + payload[3] = (event >> 24) & 0xff; + break; + default: + break; + } +} diff --git a/drivers/staging/media/atomisp/pci/runtime/eventq/interface/ia_css_eventq.h b/drivers/staging/media/atomisp/pci/runtime/eventq/interface/ia_css_eventq.h new file mode 100644 index 000000000..fd001ae35 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/eventq/interface/ia_css_eventq.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_EVENTQ_H +#define _IA_CSS_EVENTQ_H + +#include "ia_css_queue.h" /* queue APIs */ + +/** + * @brief HOST receives event from SP. + * + * @param[in] eventq_handle eventq_handle. + * @param[in] payload The event payload. + * @return 0 - Successfully dequeue. + * @return -EINVAL - Invalid argument. + * @return -ENODATA - Queue is empty. + */ +int ia_css_eventq_recv( + ia_css_queue_t *eventq_handle, + uint8_t *payload); + +/** + * @brief The Host sends the event to SP. + * The caller of this API will be blocked until the event + * is sent. + * + * @param[in] eventq_handle eventq_handle. + * @param[in] evt_id The event ID. + * @param[in] evt_payload_0 The event payload. + * @param[in] evt_payload_1 The event payload. + * @param[in] evt_payload_2 The event payload. + * @return 0 - Successfully enqueue. + * @return -EINVAL - Invalid argument. + * @return -ENOBUFS - Queue is full. + */ +int ia_css_eventq_send( + ia_css_queue_t *eventq_handle, + u8 evt_id, + u8 evt_payload_0, + u8 evt_payload_1, + uint8_t evt_payload_2); +#endif /* _IA_CSS_EVENTQ_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/eventq/src/eventq.c b/drivers/staging/media/atomisp/pci/runtime/eventq/src/eventq.c new file mode 100644 index 000000000..df75cef46 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/eventq/src/eventq.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "assert_support.h" +#include "ia_css_queue.h" /* sp2host_dequeue_irq_event() */ +#include "ia_css_eventq.h" +#include "ia_css_event.h" /* ia_css_event_encode() + ia_css_event_decode() + */ +int ia_css_eventq_recv( + ia_css_queue_t *eventq_handle, + uint8_t *payload) +{ + u32 sp_event; + int error; + + /* dequeue the IRQ event */ + error = ia_css_queue_dequeue(eventq_handle, &sp_event); + + /* check whether the IRQ event is available or not */ + if (!error) + ia_css_event_decode(sp_event, payload); + return error; +} + +/* + * @brief The Host sends the event to the SP. + * Refer to "sh_css_sp.h" for details. + */ +int ia_css_eventq_send( + ia_css_queue_t *eventq_handle, + u8 evt_id, + u8 evt_payload_0, + u8 evt_payload_1, + uint8_t evt_payload_2) +{ + u8 tmp[4]; + u32 sw_event; + int error = -ENOSYS; + + /* + * Encode the queue type, the thread ID and + * the queue ID into the event. + */ + tmp[0] = evt_id; + tmp[1] = evt_payload_0; + tmp[2] = evt_payload_1; + tmp[3] = evt_payload_2; + ia_css_event_encode(tmp, 4, &sw_event); + + /* queue the software event (busy-waiting) */ + for ( ; ; ) { + error = ia_css_queue_enqueue(eventq_handle, sw_event); + if (error != -ENOBUFS) { + /* We were able to successfully send the event + or had a real failure. return the status*/ + break; + } + /* Wait for the queue to be not full and try again*/ + udelay(1); + } + return error; +} diff --git a/drivers/staging/media/atomisp/pci/runtime/frame/interface/ia_css_frame.h b/drivers/staging/media/atomisp/pci/runtime/frame/interface/ia_css_frame.h new file mode 100644 index 000000000..700070c58 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/frame/interface/ia_css_frame.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FRAME_H__ +#define __IA_CSS_FRAME_H__ + +/* ISP2401 */ +#include + +#include +#include +#include "dma.h" + +/********************************************************************* +**** Frame INFO APIs +**********************************************************************/ +/* @brief Sets the given width and alignment to the frame info + * + * @param + * @param[in] info The info to which parameters would set + * @param[in] width The width to be set to info + * @param[in] aligned The aligned to be set to info + * @return + */ +void ia_css_frame_info_set_width(struct ia_css_frame_info *info, + unsigned int width, + unsigned int min_padded_width); + +/* @brief Sets the given format to the frame info + * + * @param + * @param[in] info The info to which parameters would set + * @param[in] format The format to be set to info + * @return + */ +void ia_css_frame_info_set_format(struct ia_css_frame_info *info, + enum ia_css_frame_format format); + +/* @brief Sets the frame info with the given parameters + * + * @param + * @param[in] info The info to which parameters would set + * @param[in] width The width to be set to info + * @param[in] height The height to be set to info + * @param[in] format The format to be set to info + * @param[in] aligned The aligned to be set to info + * @return + */ +void ia_css_frame_info_init(struct ia_css_frame_info *info, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int aligned); + +/* @brief Checks whether 2 frame infos has the same resolution + * + * @param + * @param[in] frame_a The first frame to be compared + * @param[in] frame_b The second frame to be compared + * @return Returns true if the frames are equal + */ +bool ia_css_frame_info_is_same_resolution( + const struct ia_css_frame_info *info_a, + const struct ia_css_frame_info *info_b); + +/* @brief Check the frame info is valid + * + * @param + * @param[in] info The frame attributes to be initialized + * @return The error code. + */ +int ia_css_frame_check_info(const struct ia_css_frame_info *info); + +/********************************************************************* +**** Frame APIs +**********************************************************************/ + +/* @brief Initialize the plane depending on the frame type + * + * @param + * @param[in] frame The frame attributes to be initialized + * @return The error code. + */ +int ia_css_frame_init_planes(struct ia_css_frame *frame); + +/* @brief Free an array of frames + * + * @param + * @param[in] num_frames The number of frames to be freed in the array + * @param[in] **frames_array The array of frames to be removed + * @return + */ +void ia_css_frame_free_multiple(unsigned int num_frames, + struct ia_css_frame **frames_array); + +/* @brief Allocate a CSS frame structure of given size in bytes.. + * + * @param frame The allocated frame. + * @param[in] size_bytes The frame size in bytes. + * @return The error code. + * + * Allocate a frame using the given size in bytes. + * The frame structure is partially null initialized. + */ +int ia_css_frame_allocate_with_buffer_size(struct ia_css_frame **frame, + const unsigned int size_bytes); + +/* @brief Check whether 2 frames are same type + * + * @param + * @param[in] frame_a The first frame to be compared + * @param[in] frame_b The second frame to be compared + * @return Returns true if the frames are equal + */ +bool ia_css_frame_is_same_type( + const struct ia_css_frame *frame_a, + const struct ia_css_frame *frame_b); + +/* @brief Configure a dma port from frame info + * + * @param + * @param[in] config The DAM port configuration + * @param[in] info The frame info + * @return + */ +int ia_css_dma_configure_from_info(struct dma_port_config *config, + const struct ia_css_frame_info *info); + +#endif /* __IA_CSS_FRAME_H__ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/frame/interface/ia_css_frame_comm.h b/drivers/staging/media/atomisp/pci/runtime/frame/interface/ia_css_frame_comm.h new file mode 100644 index 000000000..ce6110efb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/frame/interface/ia_css_frame_comm.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FRAME_COMM_H__ +#define __IA_CSS_FRAME_COMM_H__ + +#include "type_support.h" +#include "platform_support.h" +#include "runtime/bufq/interface/ia_css_bufq_comm.h" +#include /* ia_css_ptr */ + +/* + * These structs are derived from structs defined in ia_css_types.h + * (just take out the "_sp" from the struct name to get the "original") + * All the fields that are not needed by the SP are removed. + */ +struct ia_css_frame_sp_plane { + unsigned int offset; /* offset in bytes to start of frame data */ + /* offset is wrt data in sh_css_sp_sp_frame */ +}; + +struct ia_css_frame_sp_binary_plane { + unsigned int size; + struct ia_css_frame_sp_plane data; +}; + +struct ia_css_frame_sp_yuv_planes { + struct ia_css_frame_sp_plane y; + struct ia_css_frame_sp_plane u; + struct ia_css_frame_sp_plane v; +}; + +struct ia_css_frame_sp_nv_planes { + struct ia_css_frame_sp_plane y; + struct ia_css_frame_sp_plane uv; +}; + +struct ia_css_frame_sp_rgb_planes { + struct ia_css_frame_sp_plane r; + struct ia_css_frame_sp_plane g; + struct ia_css_frame_sp_plane b; +}; + +struct ia_css_frame_sp_plane6 { + struct ia_css_frame_sp_plane r; + struct ia_css_frame_sp_plane r_at_b; + struct ia_css_frame_sp_plane gr; + struct ia_css_frame_sp_plane gb; + struct ia_css_frame_sp_plane b; + struct ia_css_frame_sp_plane b_at_r; +}; + +struct ia_css_sp_resolution { + u16 width; /* width of valid data in pixels */ + u16 height; /* Height of valid data in lines */ +}; + +/* + * Frame info struct. This describes the contents of an image frame buffer. + */ +struct ia_css_frame_sp_info { + struct ia_css_sp_resolution res; + u16 padded_width; /* stride of line in memory + (in pixels) */ + unsigned char format; /* format of the frame data */ + unsigned char raw_bit_depth; /* number of valid bits per pixel, + only valid for RAW bayer frames */ + unsigned char raw_bayer_order; /* bayer order, only valid + for RAW bayer frames */ + unsigned char padding[3]; /* Extend to 32 bit multiple */ +}; + +struct ia_css_buffer_sp { + union { + ia_css_ptr xmem_addr; + enum sh_css_queue_id queue_id; + } buf_src; + enum ia_css_buffer_type buf_type; +}; + +struct ia_css_frame_sp { + struct ia_css_frame_sp_info info; + struct ia_css_buffer_sp buf_attr; + union { + struct ia_css_frame_sp_plane raw; + struct ia_css_frame_sp_plane rgb; + struct ia_css_frame_sp_rgb_planes planar_rgb; + struct ia_css_frame_sp_plane yuyv; + struct ia_css_frame_sp_yuv_planes yuv; + struct ia_css_frame_sp_nv_planes nv; + struct ia_css_frame_sp_plane6 plane6; + struct ia_css_frame_sp_binary_plane binary; + } planes; +}; + +void ia_css_frame_info_to_frame_sp_info( + struct ia_css_frame_sp_info *sp_info, + const struct ia_css_frame_info *info); + +void ia_css_resolution_to_sp_resolution( + struct ia_css_sp_resolution *sp_info, + const struct ia_css_resolution *info); + +#endif /*__IA_CSS_FRAME_COMM_H__*/ diff --git a/drivers/staging/media/atomisp/pci/runtime/frame/src/frame.c b/drivers/staging/media/atomisp/pci/runtime/frame/src/frame.c new file mode 100644 index 000000000..83bb42e05 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/frame/src/frame.c @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include "ia_css_frame.h" +#include +#include "assert_support.h" +#include "ia_css_debug.h" +#include "isp.h" +#include "sh_css_internal.h" +#include "atomisp_internal.h" + +#define NV12_TILEY_TILE_WIDTH 128 +#define NV12_TILEY_TILE_HEIGHT 32 + +/************************************************************************** +** Static functions declarations +**************************************************************************/ +static void frame_init_plane(struct ia_css_frame_plane *plane, + unsigned int width, + unsigned int stride, + unsigned int height, + unsigned int offset); + +static void frame_init_single_plane(struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bytes_per_pixel); + +static void frame_init_raw_single_plane( + struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bits_per_pixel); + +static void frame_init_nv_planes(struct ia_css_frame *frame, + unsigned int horizontal_decimation, + unsigned int vertical_decimation, + unsigned int bytes_per_element); + +static void frame_init_yuv_planes(struct ia_css_frame *frame, + unsigned int horizontal_decimation, + unsigned int vertical_decimation, + bool swap_uv, + unsigned int bytes_per_element); + +static void frame_init_rgb_planes(struct ia_css_frame *frame, + unsigned int bytes_per_element); + +static void frame_init_qplane6_planes(struct ia_css_frame *frame); + +static int frame_allocate_buffer_data(struct ia_css_frame *frame); + +static int frame_allocate_with_data(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth); + +static struct ia_css_frame *frame_create(unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth, + bool valid); + +static unsigned +ia_css_elems_bytes_from_info( + const struct ia_css_frame_info *info); + +/************************************************************************** +** CSS API functions, exposed by ia_css.h +**************************************************************************/ + +int ia_css_frame_allocate_from_info(struct ia_css_frame **frame, + const struct ia_css_frame_info *info) +{ + int err = 0; + + if (!frame || !info) + return -EINVAL; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate_from_info() enter:\n"); + err = + ia_css_frame_allocate(frame, info->res.width, info->res.height, + info->format, info->padded_width, + info->raw_bit_depth); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate_from_info() leave:\n"); + return err; +} + +int ia_css_frame_allocate(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth) +{ + int err = 0; + + if (!frame || width == 0 || height == 0) + return -EINVAL; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate() enter: width=%d, height=%d, format=%d, padded_width=%d, raw_bit_depth=%d\n", + width, height, format, padded_width, raw_bit_depth); + + err = frame_allocate_with_data(frame, width, height, format, + padded_width, raw_bit_depth); + + if ((*frame) && err == 0) + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate() leave: frame=%p, data(DDR address)=0x%x\n", *frame, + (*frame)->data); + else + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate() leave: frame=%p, data(DDR address)=0x%x\n", + (void *)-1, (unsigned int)-1); + + return err; +} + +void ia_css_frame_free(struct ia_css_frame *frame) +{ + IA_CSS_ENTER_PRIVATE("frame = %p", frame); + + if (frame) { + hmm_free(frame->data); + kvfree(frame); + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +/************************************************************************** +** Module public functions +**************************************************************************/ + +int ia_css_frame_check_info(const struct ia_css_frame_info *info) +{ + assert(info); + if (info->res.width == 0 || info->res.height == 0) + return -EINVAL; + return 0; +} + +int ia_css_frame_init_planes(struct ia_css_frame *frame) +{ + assert(frame); + + switch (frame->frame_info.format) { + case IA_CSS_FRAME_FORMAT_MIPI: + dev_err(atomisp_dev, + "%s: unexpected use of IA_CSS_FRAME_FORMAT_MIPI\n", __func__); + return -EINVAL; + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + frame_init_raw_single_plane(frame, &frame->planes.raw, + frame->frame_info.res.height, + frame->frame_info.padded_width, + frame->frame_info.raw_bit_depth); + break; + case IA_CSS_FRAME_FORMAT_RAW: + frame_init_single_plane(frame, &frame->planes.raw, + frame->frame_info.res.height, + frame->frame_info.padded_width, + frame->frame_info.raw_bit_depth <= 8 ? 1 : 2); + break; + case IA_CSS_FRAME_FORMAT_RGB565: + frame_init_single_plane(frame, &frame->planes.rgb, + frame->frame_info.res.height, + frame->frame_info.padded_width, 2); + break; + case IA_CSS_FRAME_FORMAT_RGBA888: + frame_init_single_plane(frame, &frame->planes.rgb, + frame->frame_info.res.height, + frame->frame_info.padded_width * 4, 1); + break; + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + frame_init_rgb_planes(frame, 1); + break; + /* yuyv and uyvu have the same frame layout, only the data + * positioning differs. + */ + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + frame_init_single_plane(frame, &frame->planes.yuyv, + frame->frame_info.res.height, + frame->frame_info.padded_width * 2, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV_LINE: + /* Needs 3 extra lines to allow vf_pp prefetching */ + frame_init_single_plane(frame, &frame->planes.yuyv, + frame->frame_info.res.height * 3 / 2 + 3, + frame->frame_info.padded_width, 1); + break; + case IA_CSS_FRAME_FORMAT_NV11: + frame_init_nv_planes(frame, 4, 1, 1); + break; + /* nv12 and nv21 have the same frame layout, only the data + * positioning differs. + */ + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + frame_init_nv_planes(frame, 2, 2, 1); + break; + case IA_CSS_FRAME_FORMAT_NV12_16: + frame_init_nv_planes(frame, 2, 2, 2); + break; + /* nv16 and nv61 have the same frame layout, only the data + * positioning differs. + */ + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV61: + frame_init_nv_planes(frame, 2, 1, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV420: + frame_init_yuv_planes(frame, 2, 2, false, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV422: + frame_init_yuv_planes(frame, 2, 1, false, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV444: + frame_init_yuv_planes(frame, 1, 1, false, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV420_16: + frame_init_yuv_planes(frame, 2, 2, false, 2); + break; + case IA_CSS_FRAME_FORMAT_YUV422_16: + frame_init_yuv_planes(frame, 2, 1, false, 2); + break; + case IA_CSS_FRAME_FORMAT_YV12: + frame_init_yuv_planes(frame, 2, 2, true, 1); + break; + case IA_CSS_FRAME_FORMAT_YV16: + frame_init_yuv_planes(frame, 2, 1, true, 1); + break; + case IA_CSS_FRAME_FORMAT_QPLANE6: + frame_init_qplane6_planes(frame); + break; + case IA_CSS_FRAME_FORMAT_BINARY_8: + frame_init_single_plane(frame, &frame->planes.binary.data, + frame->frame_info.res.height, + frame->frame_info.padded_width, 1); + frame->planes.binary.size = 0; + break; + default: + return -EINVAL; + } + return 0; +} + +void ia_css_frame_info_set_width(struct ia_css_frame_info *info, + unsigned int width, + unsigned int min_padded_width) +{ + unsigned int align; + + IA_CSS_ENTER_PRIVATE("info = %p,width = %d, minimum padded width = %d", + info, width, min_padded_width); + if (!info) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE(""); + return; + } + align = max(min_padded_width, width); + + info->res.width = width; + /* frames with a U and V plane of 8 bits per pixel need to have + all planes aligned, this means double the alignment for the + Y plane if the horizontal decimation is 2. */ + if (info->format == IA_CSS_FRAME_FORMAT_YUV420 || + info->format == IA_CSS_FRAME_FORMAT_YV12 || + info->format == IA_CSS_FRAME_FORMAT_NV12 || + info->format == IA_CSS_FRAME_FORMAT_NV21 || + info->format == IA_CSS_FRAME_FORMAT_BINARY_8 || + info->format == IA_CSS_FRAME_FORMAT_YUV_LINE) + info->padded_width = + CEIL_MUL(align, 2 * HIVE_ISP_DDR_WORD_BYTES); + else if (info->format == IA_CSS_FRAME_FORMAT_NV12_TILEY) + info->padded_width = CEIL_MUL(align, NV12_TILEY_TILE_WIDTH); + else if (info->format == IA_CSS_FRAME_FORMAT_RAW || + info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED) + info->padded_width = CEIL_MUL(align, 2 * ISP_VEC_NELEMS); + else { + info->padded_width = CEIL_MUL(align, HIVE_ISP_DDR_WORD_BYTES); + } + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_frame_info_set_format(struct ia_css_frame_info *info, + enum ia_css_frame_format format) +{ + assert(info); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_info_set_format() enter:\n"); + info->format = format; +} + +void ia_css_frame_info_init(struct ia_css_frame_info *info, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int aligned) +{ + IA_CSS_ENTER_PRIVATE("info = %p, width = %d, height = %d, format = %d, aligned = %d", + info, width, height, format, aligned); + if (!info) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE(""); + return; + } + info->res.height = height; + info->format = format; + ia_css_frame_info_set_width(info, width, aligned); + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_frame_free_multiple(unsigned int num_frames, + struct ia_css_frame **frames_array) +{ + unsigned int i; + + for (i = 0; i < num_frames; i++) { + if (frames_array[i]) { + ia_css_frame_free(frames_array[i]); + frames_array[i] = NULL; + } + } +} + +int ia_css_frame_allocate_with_buffer_size(struct ia_css_frame **frame, + const unsigned int buffer_size_bytes) +{ + /* AM: Body coppied from frame_allocate_with_data(). */ + int err; + struct ia_css_frame *me = frame_create(0, 0, + IA_CSS_FRAME_FORMAT_NUM,/* Not valid format yet */ + 0, 0, false); + + if (!me) + return -ENOMEM; + + /* Get the data size */ + me->data_bytes = buffer_size_bytes; + + err = frame_allocate_buffer_data(me); + + if (err) { + kvfree(me); + me = NULL; + } + + *frame = me; + + return err; +} + +bool ia_css_frame_info_is_same_resolution( + const struct ia_css_frame_info *info_a, + const struct ia_css_frame_info *info_b) +{ + if (!info_a || !info_b) + return false; + return (info_a->res.width == info_b->res.width) && + (info_a->res.height == info_b->res.height); +} + +bool ia_css_frame_is_same_type(const struct ia_css_frame *frame_a, + const struct ia_css_frame *frame_b) +{ + bool is_equal = false; + const struct ia_css_frame_info *info_a = &frame_a->frame_info; + const struct ia_css_frame_info *info_b = &frame_b->frame_info; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_is_same_type() enter:\n"); + + if (!info_a || !info_b) + return false; + if (info_a->format != info_b->format) + return false; + if (info_a->padded_width != info_b->padded_width) + return false; + is_equal = ia_css_frame_info_is_same_resolution(info_a, info_b); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_is_same_type() leave:\n"); + + return is_equal; +} + +int ia_css_dma_configure_from_info(struct dma_port_config *config, + const struct ia_css_frame_info *info) +{ + unsigned int is_raw_packed = info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED; + unsigned int bits_per_pixel = is_raw_packed ? info->raw_bit_depth : + ia_css_elems_bytes_from_info(info) * 8; + unsigned int pix_per_ddrword = HIVE_ISP_DDR_WORD_BITS / bits_per_pixel; + unsigned int words_per_line = CEIL_DIV(info->padded_width, pix_per_ddrword); + unsigned int elems_b = pix_per_ddrword; + + config->stride = HIVE_ISP_DDR_WORD_BYTES * words_per_line; + config->elems = (uint8_t)elems_b; + config->width = (uint16_t)info->res.width; + config->crop = 0; + + if (config->width > info->padded_width) { + dev_err(atomisp_dev, "internal error: padded_width is too small!\n"); + return -EINVAL; + } + + return 0; +} + +/************************************************************************** +** Static functions +**************************************************************************/ + +static void frame_init_plane(struct ia_css_frame_plane *plane, + unsigned int width, + unsigned int stride, + unsigned int height, + unsigned int offset) +{ + plane->height = height; + plane->width = width; + plane->stride = stride; + plane->offset = offset; +} + +static void frame_init_single_plane(struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bytes_per_pixel) +{ + unsigned int stride; + + stride = subpixels_per_line * bytes_per_pixel; + /* Frame height needs to be even number - needed by hw ISYS2401 + In case of odd number, round up to even. + Images won't be impacted by this round up, + only needed by jpeg/embedded data. + As long as buffer allocation and release are using data_bytes, + there won't be memory leak. */ + frame->data_bytes = stride * CEIL_MUL2(height, 2); + frame_init_plane(plane, subpixels_per_line, stride, height, 0); + return; +} + +static void frame_init_raw_single_plane( + struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bits_per_pixel) +{ + unsigned int stride; + + assert(frame); + + stride = HIVE_ISP_DDR_WORD_BYTES * + CEIL_DIV(subpixels_per_line, + HIVE_ISP_DDR_WORD_BITS / bits_per_pixel); + frame->data_bytes = stride * height; + frame_init_plane(plane, subpixels_per_line, stride, height, 0); + return; +} + +static void frame_init_nv_planes(struct ia_css_frame *frame, + unsigned int horizontal_decimation, + unsigned int vertical_decimation, + unsigned int bytes_per_element) +{ + unsigned int y_width = frame->frame_info.padded_width; + unsigned int y_height = frame->frame_info.res.height; + unsigned int uv_width; + unsigned int uv_height; + unsigned int y_bytes; + unsigned int uv_bytes; + unsigned int y_stride; + unsigned int uv_stride; + + assert(horizontal_decimation != 0 && vertical_decimation != 0); + + uv_width = 2 * (y_width / horizontal_decimation); + uv_height = y_height / vertical_decimation; + + if (frame->frame_info.format == IA_CSS_FRAME_FORMAT_NV12_TILEY) { + y_width = CEIL_MUL(y_width, NV12_TILEY_TILE_WIDTH); + uv_width = CEIL_MUL(uv_width, NV12_TILEY_TILE_WIDTH); + y_height = CEIL_MUL(y_height, NV12_TILEY_TILE_HEIGHT); + uv_height = CEIL_MUL(uv_height, NV12_TILEY_TILE_HEIGHT); + } + + y_stride = y_width * bytes_per_element; + uv_stride = uv_width * bytes_per_element; + y_bytes = y_stride * y_height; + uv_bytes = uv_stride * uv_height; + + frame->data_bytes = y_bytes + uv_bytes; + frame_init_plane(&frame->planes.nv.y, y_width, y_stride, y_height, 0); + frame_init_plane(&frame->planes.nv.uv, uv_width, + uv_stride, uv_height, y_bytes); + return; +} + +static void frame_init_yuv_planes(struct ia_css_frame *frame, + unsigned int horizontal_decimation, + unsigned int vertical_decimation, + bool swap_uv, + unsigned int bytes_per_element) +{ + unsigned int y_width = frame->frame_info.padded_width, + y_height = frame->frame_info.res.height, + uv_width = y_width / horizontal_decimation, + uv_height = y_height / vertical_decimation, + y_stride, y_bytes, uv_bytes, uv_stride; + + y_stride = y_width * bytes_per_element; + uv_stride = uv_width * bytes_per_element; + y_bytes = y_stride * y_height; + uv_bytes = uv_stride * uv_height; + + frame->data_bytes = y_bytes + 2 * uv_bytes; + frame_init_plane(&frame->planes.yuv.y, y_width, y_stride, y_height, 0); + if (swap_uv) { + frame_init_plane(&frame->planes.yuv.v, uv_width, uv_stride, + uv_height, y_bytes); + frame_init_plane(&frame->planes.yuv.u, uv_width, uv_stride, + uv_height, y_bytes + uv_bytes); + } else { + frame_init_plane(&frame->planes.yuv.u, uv_width, uv_stride, + uv_height, y_bytes); + frame_init_plane(&frame->planes.yuv.v, uv_width, uv_stride, + uv_height, y_bytes + uv_bytes); + } + return; +} + +static void frame_init_rgb_planes(struct ia_css_frame *frame, + unsigned int bytes_per_element) +{ + unsigned int width = frame->frame_info.res.width, + height = frame->frame_info.res.height, stride, bytes; + + stride = width * bytes_per_element; + bytes = stride * height; + frame->data_bytes = 3 * bytes; + frame_init_plane(&frame->planes.planar_rgb.r, width, stride, height, 0); + frame_init_plane(&frame->planes.planar_rgb.g, + width, stride, height, 1 * bytes); + frame_init_plane(&frame->planes.planar_rgb.b, + width, stride, height, 2 * bytes); + return; +} + +static void frame_init_qplane6_planes(struct ia_css_frame *frame) +{ + unsigned int width = frame->frame_info.padded_width / 2, + height = frame->frame_info.res.height / 2, bytes, stride; + + stride = width * 2; + bytes = stride * height; + + frame->data_bytes = 6 * bytes; + frame_init_plane(&frame->planes.plane6.r, + width, stride, height, 0 * bytes); + frame_init_plane(&frame->planes.plane6.r_at_b, + width, stride, height, 1 * bytes); + frame_init_plane(&frame->planes.plane6.gr, + width, stride, height, 2 * bytes); + frame_init_plane(&frame->planes.plane6.gb, + width, stride, height, 3 * bytes); + frame_init_plane(&frame->planes.plane6.b, + width, stride, height, 4 * bytes); + frame_init_plane(&frame->planes.plane6.b_at_r, + width, stride, height, 5 * bytes); + return; +} + +static int frame_allocate_buffer_data(struct ia_css_frame *frame) +{ +#ifdef ISP2401 + IA_CSS_ENTER_LEAVE_PRIVATE("frame->data_bytes=%d\n", frame->data_bytes); +#endif + frame->data = hmm_alloc(frame->data_bytes); + if (frame->data == mmgr_NULL) + return -ENOMEM; + return 0; +} + +static int frame_allocate_with_data(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth) +{ + int err; + struct ia_css_frame *me = frame_create(width, + height, + format, + padded_width, + raw_bit_depth, + true); + + if (!me) + return -ENOMEM; + + err = ia_css_frame_init_planes(me); + + if (!err) + err = frame_allocate_buffer_data(me); + + if (err) { + kvfree(me); +#ifndef ISP2401 + return err; +#else + me = NULL; +#endif + } + + *frame = me; + + return err; +} + +static struct ia_css_frame *frame_create(unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth, + bool valid) +{ + struct ia_css_frame *me = kvmalloc(sizeof(*me), GFP_KERNEL); + + if (!me) + return NULL; + + memset(me, 0, sizeof(*me)); + me->frame_info.res.width = width; + me->frame_info.res.height = height; + me->frame_info.format = format; + me->frame_info.padded_width = padded_width; + me->frame_info.raw_bit_depth = raw_bit_depth; + me->valid = valid; + me->data_bytes = 0; + me->data = mmgr_NULL; + /* To indicate it is not valid frame. */ + me->dynamic_queue_id = (int)SH_CSS_INVALID_QUEUE_ID; + me->buf_type = IA_CSS_BUFFER_TYPE_INVALID; + + return me; +} + +static unsigned +ia_css_elems_bytes_from_info(const struct ia_css_frame_info *info) +{ + if (info->format == IA_CSS_FRAME_FORMAT_RGB565) + return 2; /* bytes per pixel */ + if (info->format == IA_CSS_FRAME_FORMAT_YUV420_16) + return 2; /* bytes per pixel */ + if (info->format == IA_CSS_FRAME_FORMAT_YUV422_16) + return 2; /* bytes per pixel */ + /* Note: Essentially NV12_16 is a 2 bytes per pixel format, this return value is used + * to configure DMA for the output buffer, + * At least in SKC this data is overwritten by isp_output_init.sp.c except for elements(elems), + * which is configured from this return value, + * NV12_16 is implemented by a double buffer of 8 bit elements hence elems should be configured as 8 */ + if (info->format == IA_CSS_FRAME_FORMAT_NV12_16) + return 1; /* bytes per pixel */ + + if (info->format == IA_CSS_FRAME_FORMAT_RAW + || (info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED)) { + if (info->raw_bit_depth) + return CEIL_DIV(info->raw_bit_depth, 8); + else + return 2; /* bytes per pixel */ + } + if (info->format == IA_CSS_FRAME_FORMAT_PLANAR_RGB888) + return 3; /* bytes per pixel */ + if (info->format == IA_CSS_FRAME_FORMAT_RGBA888) + return 4; /* bytes per pixel */ + if (info->format == IA_CSS_FRAME_FORMAT_QPLANE6) + return 2; /* bytes per pixel */ + return 1; /* Default is 1 byte per pixel */ +} + +void ia_css_frame_info_to_frame_sp_info( + struct ia_css_frame_sp_info *to, + const struct ia_css_frame_info *from) +{ + ia_css_resolution_to_sp_resolution(&to->res, &from->res); + to->padded_width = (uint16_t)from->padded_width; + to->format = (uint8_t)from->format; + to->raw_bit_depth = (uint8_t)from->raw_bit_depth; + to->raw_bayer_order = from->raw_bayer_order; +} + +void ia_css_resolution_to_sp_resolution( + struct ia_css_sp_resolution *to, + const struct ia_css_resolution *from) +{ + to->width = (uint16_t)from->width; + to->height = (uint16_t)from->height; +} + +int ia_css_frame_init_from_info(struct ia_css_frame *frame, + const struct ia_css_frame_info *frame_info) +{ + frame->frame_info.res.width = frame_info->res.width; + frame->frame_info.res.height = frame_info->res.height; + frame->frame_info.format = frame_info->format; + frame->frame_info.padded_width = frame_info->padded_width; + frame->frame_info.raw_bit_depth = frame_info->raw_bit_depth; + frame->valid = true; + /* To indicate it is not valid frame. */ + frame->dynamic_queue_id = SH_CSS_INVALID_QUEUE_ID; + frame->buf_type = IA_CSS_BUFFER_TYPE_INVALID; + + return ia_css_frame_init_planes(frame); +} diff --git a/drivers/staging/media/atomisp/pci/runtime/ifmtr/interface/ia_css_ifmtr.h b/drivers/staging/media/atomisp/pci/runtime/ifmtr/interface/ia_css_ifmtr.h new file mode 100644 index 000000000..2c440feec --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/ifmtr/interface/ia_css_ifmtr.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_IFMTR_H__ +#define __IA_CSS_IFMTR_H__ + +#include +#include +#include + +extern bool ifmtr_set_if_blocking_mode_reset; + +unsigned int ia_css_ifmtr_lines_needed_for_bayer_order( + const struct ia_css_stream_config *config); + +unsigned int ia_css_ifmtr_columns_needed_for_bayer_order( + const struct ia_css_stream_config *config); + +int ia_css_ifmtr_configure(struct ia_css_stream_config *config, + struct ia_css_binary *binary); + +#endif /* __IA_CSS_IFMTR_H__ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/ifmtr/src/ifmtr.c b/drivers/staging/media/atomisp/pci/runtime/ifmtr/src/ifmtr.c new file mode 100644 index 000000000..6d9f47629 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/ifmtr/src/ifmtr.c @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" +#include + +#ifndef ISP2401 + +#include "ia_css_ifmtr.h" +#include +#include "sh_css_internal.h" +#include "input_formatter.h" +#include "assert_support.h" +#include "sh_css_sp.h" +#include "isp/modes/interface/input_buf.isp.h" + +/************************************************************ + * Static functions declarations + ************************************************************/ +static int ifmtr_start_column( + const struct ia_css_stream_config *config, + unsigned int bin_in, + unsigned int *start_column); + +static int ifmtr_input_start_line( + const struct ia_css_stream_config *config, + unsigned int bin_in, + unsigned int *start_line); + +static void ifmtr_set_if_blocking_mode( + const input_formatter_cfg_t *const config_a, + const input_formatter_cfg_t *const config_b); + +/************************************************************ + * Public functions + ************************************************************/ + +/* ISP expects GRBG bayer order, we skip one line and/or one row + * to correct in case the input bayer order is different. + */ +unsigned int ia_css_ifmtr_lines_needed_for_bayer_order( + const struct ia_css_stream_config *config) +{ + assert(config); + if ((config->input_config.bayer_order == IA_CSS_BAYER_ORDER_BGGR) + || (config->input_config.bayer_order == IA_CSS_BAYER_ORDER_GBRG)) + return 1; + + return 0; +} + +unsigned int ia_css_ifmtr_columns_needed_for_bayer_order( + const struct ia_css_stream_config *config) +{ + assert(config); + if ((config->input_config.bayer_order == IA_CSS_BAYER_ORDER_RGGB) + || (config->input_config.bayer_order == IA_CSS_BAYER_ORDER_GBRG)) + return 1; + + return 0; +} + +int ia_css_ifmtr_configure(struct ia_css_stream_config *config, + struct ia_css_binary *binary) +{ + unsigned int start_line, start_column = 0, + cropped_height, + cropped_width, + num_vectors, + buffer_height = 2, + buffer_width, + two_ppc, + vmem_increment = 0, + deinterleaving = 0, + deinterleaving_b = 0, + width_a = 0, + width_b = 0, + bits_per_pixel, + vectors_per_buffer, + vectors_per_line = 0, + buffers_per_line = 0, + buf_offset_a = 0, + buf_offset_b = 0, + line_width = 0, + width_b_factor = 1, start_column_b, + left_padding = 0; + input_formatter_cfg_t if_a_config, if_b_config; + enum atomisp_input_format input_format; + int err = 0; + u8 if_config_index; + + /* Determine which input formatter config set is targeted. */ + /* Index is equal to the CSI-2 port used. */ + enum mipi_port_id port; + + if (binary) { + cropped_height = binary->in_frame_info.res.height; + cropped_width = binary->in_frame_info.res.width; + /* This should correspond to the input buffer definition for + ISP binaries in input_buf.isp.h */ + if (binary->info->sp.enable.continuous && + binary->info->sp.pipeline.mode != IA_CSS_BINARY_MODE_COPY) + buffer_width = MAX_VECTORS_PER_INPUT_LINE_CONT * ISP_VEC_NELEMS; + else + buffer_width = binary->info->sp.input.max_width; + input_format = binary->input_format; + } else { + /* sp raw copy pipe (IA_CSS_PIPE_MODE_COPY): binary is NULL */ + cropped_height = config->input_config.input_res.height; + cropped_width = config->input_config.input_res.width; + buffer_width = MAX_VECTORS_PER_INPUT_LINE_CONT * ISP_VEC_NELEMS; + input_format = config->input_config.format; + } + two_ppc = config->pixels_per_clock == 2; + if (config->mode == IA_CSS_INPUT_MODE_SENSOR + || config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + port = config->source.port.port; + if_config_index = (uint8_t)(port - MIPI_PORT0_ID); + } else if (config->mode == IA_CSS_INPUT_MODE_MEMORY) { + if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED; + } else { + if_config_index = 0; + } + + assert(if_config_index <= SH_CSS_MAX_IF_CONFIGS + || if_config_index == SH_CSS_IF_CONFIG_NOT_NEEDED); + + /* TODO: check to see if input is RAW and if current mode interprets + * RAW data in any particular bayer order. copy binary with output + * format other than raw should not result in dropping lines and/or + * columns. + */ + err = ifmtr_input_start_line(config, cropped_height, &start_line); + if (err) + return err; + err = ifmtr_start_column(config, cropped_width, &start_column); + if (err) + return err; + + if (config->left_padding == -1) + if (!binary) + /* sp raw copy pipe: set left_padding value */ + left_padding = 0; + else + left_padding = binary->left_padding; + else + left_padding = 2 * ISP_VEC_NELEMS - config->left_padding; + + if (left_padding) { + num_vectors = CEIL_DIV(cropped_width + left_padding, + ISP_VEC_NELEMS); + } else { + num_vectors = CEIL_DIV(cropped_width, ISP_VEC_NELEMS); + num_vectors *= buffer_height; + /* todo: in case of left padding, + num_vectors is vectors per line, + otherwise vectors per line * buffer_height. */ + } + + start_column_b = start_column; + + bits_per_pixel = input_formatter_get_alignment(INPUT_FORMATTER0_ID) + * 8 / ISP_VEC_NELEMS; + switch (input_format) { + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: + if (two_ppc) { + vmem_increment = 1; + deinterleaving = 1; + deinterleaving_b = 1; + /* half lines */ + width_a = cropped_width * deinterleaving / 2; + width_b_factor = 2; + /* full lines */ + width_b = width_a * width_b_factor; + buffer_width *= deinterleaving * 2; + /* Patch from bayer to yuv */ + num_vectors *= deinterleaving; + buf_offset_b = buffer_width / 2 / ISP_VEC_NELEMS; + vectors_per_line = num_vectors / buffer_height; + /* Even lines are half size */ + line_width = vectors_per_line * + input_formatter_get_alignment(INPUT_FORMATTER0_ID) / + 2; + start_column /= 2; + } else { + vmem_increment = 1; + deinterleaving = 3; + width_a = cropped_width * deinterleaving / 2; + buffer_width = buffer_width * deinterleaving / 2; + /* Patch from bayer to yuv */ + num_vectors = num_vectors / 2 * deinterleaving; + start_column = start_column * deinterleaving / 2; + } + break; + case ATOMISP_INPUT_FORMAT_YUV420_8: + case ATOMISP_INPUT_FORMAT_YUV420_10: + case ATOMISP_INPUT_FORMAT_YUV420_16: + if (two_ppc) { + vmem_increment = 1; + deinterleaving = 1; + width_a = width_b = cropped_width * deinterleaving / 2; + buffer_width *= deinterleaving * 2; + num_vectors *= deinterleaving; + buf_offset_b = buffer_width / 2 / ISP_VEC_NELEMS; + vectors_per_line = num_vectors / buffer_height; + /* Even lines are half size */ + line_width = vectors_per_line * + input_formatter_get_alignment(INPUT_FORMATTER0_ID) / + 2; + start_column *= deinterleaving; + start_column /= 2; + start_column_b = start_column; + } else { + vmem_increment = 1; + deinterleaving = 1; + width_a = cropped_width * deinterleaving; + buffer_width *= deinterleaving * 2; + num_vectors *= deinterleaving; + start_column *= deinterleaving; + } + break; + case ATOMISP_INPUT_FORMAT_YUV422_8: + case ATOMISP_INPUT_FORMAT_YUV422_10: + case ATOMISP_INPUT_FORMAT_YUV422_16: + if (two_ppc) { + vmem_increment = 1; + deinterleaving = 1; + width_a = width_b = cropped_width * deinterleaving; + buffer_width *= deinterleaving * 2; + num_vectors *= deinterleaving; + start_column *= deinterleaving; + buf_offset_b = buffer_width / 2 / ISP_VEC_NELEMS; + start_column_b = start_column; + } else { + vmem_increment = 1; + deinterleaving = 2; + width_a = cropped_width * deinterleaving; + buffer_width *= deinterleaving; + num_vectors *= deinterleaving; + start_column *= deinterleaving; + } + break; + case ATOMISP_INPUT_FORMAT_RGB_444: + case ATOMISP_INPUT_FORMAT_RGB_555: + case ATOMISP_INPUT_FORMAT_RGB_565: + case ATOMISP_INPUT_FORMAT_RGB_666: + case ATOMISP_INPUT_FORMAT_RGB_888: + num_vectors *= 2; + if (two_ppc) { + deinterleaving = 2; /* BR in if_a, G in if_b */ + deinterleaving_b = 1; /* BR in if_a, G in if_b */ + buffers_per_line = 4; + start_column_b = start_column; + start_column *= deinterleaving; + start_column_b *= deinterleaving_b; + } else { + deinterleaving = 3; /* BGR */ + buffers_per_line = 3; + start_column *= deinterleaving; + } + vmem_increment = 1; + width_a = cropped_width * deinterleaving; + width_b = cropped_width * deinterleaving_b; + buffer_width *= buffers_per_line; + /* Patch from bayer to rgb */ + num_vectors = num_vectors / 2 * deinterleaving; + buf_offset_b = buffer_width / 2 / ISP_VEC_NELEMS; + break; + case ATOMISP_INPUT_FORMAT_RAW_6: + case ATOMISP_INPUT_FORMAT_RAW_7: + case ATOMISP_INPUT_FORMAT_RAW_8: + case ATOMISP_INPUT_FORMAT_RAW_10: + case ATOMISP_INPUT_FORMAT_RAW_12: + if (two_ppc) { + int crop_col = (start_column % 2) == 1; + + vmem_increment = 2; + deinterleaving = 1; + width_a = width_b = cropped_width / 2; + + /* When two_ppc is enabled AND we need to crop one extra + * column, if_a crops by one extra and we swap the + * output offsets to interleave the bayer pattern in + * the correct order. + */ + buf_offset_a = crop_col ? 1 : 0; + buf_offset_b = crop_col ? 0 : 1; + start_column_b = start_column / 2; + start_column = start_column / 2 + crop_col; + } else { + vmem_increment = 1; + deinterleaving = 2; + if ((!binary) || (config->continuous && binary + && binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY)) { + /* !binary -> sp raw copy pipe, no deinterleaving */ + deinterleaving = 1; + } + width_a = cropped_width; + /* Must be multiple of deinterleaving */ + num_vectors = CEIL_MUL(num_vectors, deinterleaving); + } + buffer_height *= 2; + if ((!binary) || config->continuous) + /* !binary -> sp raw copy pipe */ + buffer_height *= 2; + vectors_per_line = CEIL_DIV(cropped_width, ISP_VEC_NELEMS); + vectors_per_line = CEIL_MUL(vectors_per_line, deinterleaving); + break; + case ATOMISP_INPUT_FORMAT_RAW_14: + case ATOMISP_INPUT_FORMAT_RAW_16: + if (two_ppc) { + num_vectors *= 2; + vmem_increment = 1; + deinterleaving = 2; + width_a = width_b = cropped_width; + /* B buffer is one line further */ + buf_offset_b = buffer_width / ISP_VEC_NELEMS; + bits_per_pixel *= 2; + } else { + vmem_increment = 1; + deinterleaving = 2; + width_a = cropped_width; + start_column /= deinterleaving; + } + buffer_height *= 2; + break; + case ATOMISP_INPUT_FORMAT_BINARY_8: + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT1: + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT2: + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT3: + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT4: + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT5: + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT6: + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT7: + case ATOMISP_INPUT_FORMAT_GENERIC_SHORT8: + case ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT: + case ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT: + case ATOMISP_INPUT_FORMAT_EMBEDDED: + case ATOMISP_INPUT_FORMAT_USER_DEF1: + case ATOMISP_INPUT_FORMAT_USER_DEF2: + case ATOMISP_INPUT_FORMAT_USER_DEF3: + case ATOMISP_INPUT_FORMAT_USER_DEF4: + case ATOMISP_INPUT_FORMAT_USER_DEF5: + case ATOMISP_INPUT_FORMAT_USER_DEF6: + case ATOMISP_INPUT_FORMAT_USER_DEF7: + case ATOMISP_INPUT_FORMAT_USER_DEF8: + break; + } + if (width_a == 0) + return -EINVAL; + + if (two_ppc) + left_padding /= 2; + + /* Default values */ + if (left_padding) + vectors_per_line = num_vectors; + if (!vectors_per_line) { + vectors_per_line = CEIL_MUL(num_vectors / buffer_height, + deinterleaving); + line_width = 0; + } + if (!line_width) + line_width = vectors_per_line * + input_formatter_get_alignment(INPUT_FORMATTER0_ID); + if (!buffers_per_line) + buffers_per_line = deinterleaving; + line_width = CEIL_MUL(line_width, + input_formatter_get_alignment(INPUT_FORMATTER0_ID) + * vmem_increment); + + vectors_per_buffer = buffer_height * buffer_width / ISP_VEC_NELEMS; + + if (config->mode == IA_CSS_INPUT_MODE_TPG && + ((binary && binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_VIDEO) || + (!binary))) { + /* !binary -> sp raw copy pipe */ + /* workaround for TPG in video mode */ + start_line = 0; + start_column = 0; + cropped_height -= start_line; + width_a -= start_column; + } + + if_a_config.start_line = start_line; + if_a_config.start_column = start_column; + if_a_config.left_padding = left_padding / deinterleaving; + if_a_config.cropped_height = cropped_height; + if_a_config.cropped_width = width_a; + if_a_config.deinterleaving = deinterleaving; + if_a_config.buf_vecs = vectors_per_buffer; + if_a_config.buf_start_index = buf_offset_a; + if_a_config.buf_increment = vmem_increment; + if_a_config.buf_eol_offset = + buffer_width * bits_per_pixel / 8 - line_width; + if_a_config.is_yuv420_format = + (input_format == ATOMISP_INPUT_FORMAT_YUV420_8) + || (input_format == ATOMISP_INPUT_FORMAT_YUV420_10) + || (input_format == ATOMISP_INPUT_FORMAT_YUV420_16); + if_a_config.block_no_reqs = (config->mode != IA_CSS_INPUT_MODE_SENSOR); + + if (two_ppc) { + if (deinterleaving_b) { + deinterleaving = deinterleaving_b; + width_b = cropped_width * deinterleaving; + buffer_width *= deinterleaving; + /* Patch from bayer to rgb */ + num_vectors = num_vectors / 2 * + deinterleaving * width_b_factor; + vectors_per_line = num_vectors / buffer_height; + line_width = vectors_per_line * + input_formatter_get_alignment(INPUT_FORMATTER0_ID); + } + if_b_config.start_line = start_line; + if_b_config.start_column = start_column_b; + if_b_config.left_padding = left_padding / deinterleaving; + if_b_config.cropped_height = cropped_height; + if_b_config.cropped_width = width_b; + if_b_config.deinterleaving = deinterleaving; + if_b_config.buf_vecs = vectors_per_buffer; + if_b_config.buf_start_index = buf_offset_b; + if_b_config.buf_increment = vmem_increment; + if_b_config.buf_eol_offset = + buffer_width * bits_per_pixel / 8 - line_width; + if_b_config.is_yuv420_format = + input_format == ATOMISP_INPUT_FORMAT_YUV420_8 + || input_format == ATOMISP_INPUT_FORMAT_YUV420_10 + || input_format == ATOMISP_INPUT_FORMAT_YUV420_16; + if_b_config.block_no_reqs = + (config->mode != IA_CSS_INPUT_MODE_SENSOR); + + if (if_config_index != SH_CSS_IF_CONFIG_NOT_NEEDED) { + assert(if_config_index <= SH_CSS_MAX_IF_CONFIGS); + + ifmtr_set_if_blocking_mode(&if_a_config, &if_b_config); + /* Set the ifconfigs to SP group */ + sh_css_sp_set_if_configs(&if_a_config, &if_b_config, + if_config_index); + } + } else { + if (if_config_index != SH_CSS_IF_CONFIG_NOT_NEEDED) { + assert(if_config_index <= SH_CSS_MAX_IF_CONFIGS); + + ifmtr_set_if_blocking_mode(&if_a_config, NULL); + /* Set the ifconfigs to SP group */ + sh_css_sp_set_if_configs(&if_a_config, NULL, + if_config_index); + } + } + + return 0; +} + +bool ifmtr_set_if_blocking_mode_reset = true; + +/************************************************************ + * Static functions + ************************************************************/ +static void ifmtr_set_if_blocking_mode( + const input_formatter_cfg_t *const config_a, + const input_formatter_cfg_t *const config_b) +{ + int i; + bool block[] = { false, false, false, false }; + + assert(N_INPUT_FORMATTER_ID <= (ARRAY_SIZE(block))); + + block[INPUT_FORMATTER0_ID] = (bool)config_a->block_no_reqs; + if (config_b) + block[INPUT_FORMATTER1_ID] = (bool)config_b->block_no_reqs; + + /* TODO: next could cause issues when streams are started after + * eachother. */ + /*IF should not be reconfigured/reset from host */ + if (ifmtr_set_if_blocking_mode_reset) { + ifmtr_set_if_blocking_mode_reset = false; + for (i = 0; i < N_INPUT_FORMATTER_ID; i++) { + input_formatter_ID_t id = (input_formatter_ID_t)i; + + input_formatter_rst(id); + input_formatter_set_fifo_blocking_mode(id, block[id]); + } + } + + return; +} + +static int ifmtr_start_column( + const struct ia_css_stream_config *config, + unsigned int bin_in, + unsigned int *start_column) +{ + unsigned int in = config->input_config.input_res.width, start, + for_bayer = ia_css_ifmtr_columns_needed_for_bayer_order(config); + + if (bin_in + 2 * for_bayer > in) + return -EINVAL; + + /* On the hardware, we want to use the middle of the input, so we + * divide the start column by 2. */ + start = (in - bin_in) / 2; + /* in case the number of extra columns is 2 or odd, we round the start + * column down */ + start &= ~0x1; + + /* now we add the one column (if needed) to correct for the bayer + * order). + */ + start += for_bayer; + *start_column = start; + return 0; +} + +static int ifmtr_input_start_line( + const struct ia_css_stream_config *config, + unsigned int bin_in, + unsigned int *start_line) +{ + unsigned int in = config->input_config.input_res.height, start, + for_bayer = ia_css_ifmtr_lines_needed_for_bayer_order(config); + + if (bin_in + 2 * for_bayer > in) + return -EINVAL; + + /* On the hardware, we want to use the middle of the input, so we + * divide the start line by 2. On the simulator, we cannot handle extra + * lines at the end of the frame. + */ + start = (in - bin_in) / 2; + /* in case the number of extra lines is 2 or odd, we round the start + * line down. + */ + start &= ~0x1; + + /* now we add the one line (if needed) to correct for the bayer order */ + start += for_bayer; + *start_line = start; + return 0; +} + +#endif diff --git a/drivers/staging/media/atomisp/pci/runtime/inputfifo/interface/ia_css_inputfifo.h b/drivers/staging/media/atomisp/pci/runtime/inputfifo/interface/ia_css_inputfifo.h new file mode 100644 index 000000000..7950c5c36 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/inputfifo/interface/ia_css_inputfifo.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_INPUTFIFO_H +#define _IA_CSS_INPUTFIFO_H + +#include +#include + +#include "ia_css_stream_format.h" + +/* SP access */ +void ia_css_inputfifo_send_input_frame( + const unsigned short *data, + unsigned int width, + unsigned int height, + unsigned int ch_id, + enum atomisp_input_format input_format, + bool two_ppc); + +void ia_css_inputfifo_start_frame( + unsigned int ch_id, + enum atomisp_input_format input_format, + bool two_ppc); + +void ia_css_inputfifo_send_line( + unsigned int ch_id, + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2); + +void ia_css_inputfifo_send_embedded_line( + unsigned int ch_id, + enum atomisp_input_format data_type, + const unsigned short *data, + unsigned int width); + +void ia_css_inputfifo_end_frame( + unsigned int ch_id); + +#endif /* _IA_CSS_INPUTFIFO_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/inputfifo/src/inputfifo.c b/drivers/staging/media/atomisp/pci/runtime/inputfifo/src/inputfifo.c new file mode 100644 index 000000000..2d06e1240 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/inputfifo/src/inputfifo.c @@ -0,0 +1,529 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "platform_support.h" + +#include "ia_css_inputfifo.h" + +#include "device_access.h" + +#define __INLINE_SP__ +#include "sp.h" +#define __INLINE_ISP__ +#include "isp.h" +#define __INLINE_IRQ__ +#include "irq.h" +#define __INLINE_FIFO_MONITOR__ +#include "fifo_monitor.h" + +#define __INLINE_EVENT__ +#include "event_fifo.h" +#define __INLINE_SP__ + +#include "input_system.h" /* MIPI_PREDICTOR_NONE,... */ + +#include "assert_support.h" + +/* System independent */ +#include "sh_css_internal.h" +#include "ia_css_isys.h" + +#define HBLANK_CYCLES (187) +#define MARKER_CYCLES (6) + +#include + +/* The data type is used to send special cases: + * yuv420: odd lines (1, 3 etc) are twice as wide as even + * lines (0, 2, 4 etc). + * rgb: for two pixels per clock, the R and B values are sent + * to output_0 while only G is sent to output_1. This means + * that output_1 only gets half the number of values of output_0. + * WARNING: This type should also be used for Legacy YUV420. + * regular: used for all other data types (RAW, YUV422, etc) + */ +enum inputfifo_mipi_data_type { + inputfifo_mipi_data_type_regular, + inputfifo_mipi_data_type_yuv420, + inputfifo_mipi_data_type_yuv420_legacy, + inputfifo_mipi_data_type_rgb, +}; + +static unsigned int inputfifo_curr_ch_id, inputfifo_curr_fmt_type; +struct inputfifo_instance { + unsigned int ch_id; + enum atomisp_input_format input_format; + bool two_ppc; + bool streaming; + unsigned int hblank_cycles; + unsigned int marker_cycles; + unsigned int fmt_type; + enum inputfifo_mipi_data_type type; +}; + +/* + * Maintain a basic streaming to Mipi administration with ch_id as index + * ch_id maps on the "Mipi virtual channel ID" and can have value 0..3 + */ +#define INPUTFIFO_NR_OF_S2M_CHANNELS (4) +static struct inputfifo_instance + inputfifo_inst_admin[INPUTFIFO_NR_OF_S2M_CHANNELS]; + +/* Streaming to MIPI */ +static unsigned int inputfifo_wrap_marker( + /* static inline unsigned inputfifo_wrap_marker( */ + unsigned int marker) +{ + return marker | + (inputfifo_curr_ch_id << HIVE_STR_TO_MIPI_CH_ID_LSB) | + (inputfifo_curr_fmt_type << _HIVE_STR_TO_MIPI_FMT_TYPE_LSB); +} + +static inline void +_sh_css_fifo_snd(unsigned int token) +{ + while (!can_event_send_token(STR2MIPI_EVENT_ID)) + udelay(1); + event_send_token(STR2MIPI_EVENT_ID, token); + return; +} + +static void inputfifo_send_data_a( + /* static inline void inputfifo_send_data_a( */ + unsigned int data) +{ + unsigned int token = (1 << HIVE_STR_TO_MIPI_VALID_A_BIT) | + (data << HIVE_STR_TO_MIPI_DATA_A_LSB); + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_data_b( + /* static inline void inputfifo_send_data_b( */ + unsigned int data) +{ + unsigned int token = (1 << HIVE_STR_TO_MIPI_VALID_B_BIT) | + (data << _HIVE_STR_TO_MIPI_DATA_B_LSB); + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_data( + /* static inline void inputfifo_send_data( */ + unsigned int a, + unsigned int b) +{ + unsigned int token = ((1 << HIVE_STR_TO_MIPI_VALID_A_BIT) | + (1 << HIVE_STR_TO_MIPI_VALID_B_BIT) | + (a << HIVE_STR_TO_MIPI_DATA_A_LSB) | + (b << _HIVE_STR_TO_MIPI_DATA_B_LSB)); + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_sol(void) +/* static inline void inputfifo_send_sol(void) */ +{ + hrt_data token = inputfifo_wrap_marker( + 1 << HIVE_STR_TO_MIPI_SOL_BIT); + + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_eol(void) +/* static inline void inputfifo_send_eol(void) */ +{ + hrt_data token = inputfifo_wrap_marker( + 1 << HIVE_STR_TO_MIPI_EOL_BIT); + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_sof(void) +/* static inline void inputfifo_send_sof(void) */ +{ + hrt_data token = inputfifo_wrap_marker( + 1 << HIVE_STR_TO_MIPI_SOF_BIT); + + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_eof(void) +/* static inline void inputfifo_send_eof(void) */ +{ + hrt_data token = inputfifo_wrap_marker( + 1 << HIVE_STR_TO_MIPI_EOF_BIT); + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_ch_id_and_fmt_type( + /* static inline + void inputfifo_send_ch_id_and_fmt_type( */ + unsigned int ch_id, + unsigned int fmt_type) +{ + hrt_data token; + + inputfifo_curr_ch_id = ch_id & _HIVE_ISP_CH_ID_MASK; + inputfifo_curr_fmt_type = fmt_type & _HIVE_ISP_FMT_TYPE_MASK; + /* we send an zero marker, this will wrap the ch_id and + * fmt_type automatically. + */ + token = inputfifo_wrap_marker(0); + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_empty_token(void) +/* static inline void inputfifo_send_empty_token(void) */ +{ + hrt_data token = inputfifo_wrap_marker(0); + + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_start_frame( + /* static inline void inputfifo_start_frame( */ + unsigned int ch_id, + unsigned int fmt_type) +{ + inputfifo_send_ch_id_and_fmt_type(ch_id, fmt_type); + inputfifo_send_sof(); + return; +} + +static void inputfifo_end_frame( + unsigned int marker_cycles) +{ + unsigned int i; + + for (i = 0; i < marker_cycles; i++) + inputfifo_send_empty_token(); + inputfifo_send_eof(); + return; +} + +static void inputfifo_send_line2( + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2, + unsigned int hblank_cycles, + unsigned int marker_cycles, + unsigned int two_ppc, + enum inputfifo_mipi_data_type type) +{ + unsigned int i, is_rgb = 0, is_legacy = 0; + + assert(data); + assert((data2) || (width2 == 0)); + if (type == inputfifo_mipi_data_type_rgb) + is_rgb = 1; + + if (type == inputfifo_mipi_data_type_yuv420_legacy) + is_legacy = 1; + + for (i = 0; i < hblank_cycles; i++) + inputfifo_send_empty_token(); + inputfifo_send_sol(); + for (i = 0; i < marker_cycles; i++) + inputfifo_send_empty_token(); + for (i = 0; i < width; i++, data++) { + /* for RGB in two_ppc, we only actually send 2 pixels per + * clock in the even pixels (0, 2 etc). In the other cycles, + * we only send 1 pixel, to data[0]. + */ + unsigned int send_two_pixels = two_ppc; + + if ((is_rgb || is_legacy) && (i % 3 == 2)) + send_two_pixels = 0; + if (send_two_pixels) { + if (i + 1 == width) { + /* for jpg (binary) copy, this can occur + * if the file contains an odd number of bytes. + */ + inputfifo_send_data( + data[0], 0); + } else { + inputfifo_send_data( + data[0], data[1]); + } + /* Additional increment because we send 2 pixels */ + data++; + i++; + } else if (two_ppc && is_legacy) { + inputfifo_send_data_b(data[0]); + } else { + inputfifo_send_data_a(data[0]); + } + } + + for (i = 0; i < width2; i++, data2++) { + /* for RGB in two_ppc, we only actually send 2 pixels per + * clock in the even pixels (0, 2 etc). In the other cycles, + * we only send 1 pixel, to data2[0]. + */ + unsigned int send_two_pixels = two_ppc; + + if ((is_rgb || is_legacy) && (i % 3 == 2)) + send_two_pixels = 0; + if (send_two_pixels) { + if (i + 1 == width2) { + /* for jpg (binary) copy, this can occur + * if the file contains an odd number of bytes. + */ + inputfifo_send_data( + data2[0], 0); + } else { + inputfifo_send_data( + data2[0], data2[1]); + } + /* Additional increment because we send 2 pixels */ + data2++; + i++; + } else if (two_ppc && is_legacy) { + inputfifo_send_data_b(data2[0]); + } else { + inputfifo_send_data_a(data2[0]); + } + } + for (i = 0; i < hblank_cycles; i++) + inputfifo_send_empty_token(); + inputfifo_send_eol(); + return; +} + +static void +inputfifo_send_line(const unsigned short *data, + unsigned int width, + unsigned int hblank_cycles, + unsigned int marker_cycles, + unsigned int two_ppc, + enum inputfifo_mipi_data_type type) +{ + assert(data); + inputfifo_send_line2(data, width, NULL, 0, + hblank_cycles, + marker_cycles, + two_ppc, + type); +} + +/* Send a frame of data into the input network via the GP FIFO. + * Parameters: + * - data: array of 16 bit values that contains all data for the frame. + * - width: width of a line in number of subpixels, for yuv420 it is the + * number of Y components per line. + * - height: height of the frame in number of lines. + * - ch_id: channel ID. + * - fmt_type: format type. + * - hblank_cycles: length of horizontal blanking in cycles. + * - marker_cycles: number of empty cycles after start-of-line and before + * end-of-frame. + * - two_ppc: boolean, describes whether to send one or two pixels per clock + * cycle. In this mode, we sent pixels N and N+1 in the same cycle, + * to IF_PRIM_A and IF_PRIM_B respectively. The caller must make + * sure the input data has been formatted correctly for this. + * For example, for RGB formats this means that unused values + * must be inserted. + * - yuv420: boolean, describes whether (non-legacy) yuv420 data is used. In + * this mode, the odd lines (1,3,5 etc) are half as long as the + * even lines (2,4,6 etc). + * Note that the first line is odd (1) and the second line is even + * (2). + * + * This function does not do any reordering of pixels, the caller must make + * sure the data is in the righ format. Please refer to the CSS receiver + * documentation for details on the data formats. + */ + +static void inputfifo_send_frame( + const unsigned short *data, + unsigned int width, + unsigned int height, + unsigned int ch_id, + unsigned int fmt_type, + unsigned int hblank_cycles, + unsigned int marker_cycles, + unsigned int two_ppc, + enum inputfifo_mipi_data_type type) +{ + unsigned int i; + + assert(data); + inputfifo_start_frame(ch_id, fmt_type); + + for (i = 0; i < height; i++) { + if ((type == inputfifo_mipi_data_type_yuv420) && + (i & 1) == 1) { + inputfifo_send_line(data, 2 * width, + hblank_cycles, + marker_cycles, + two_ppc, type); + data += 2 * width; + } else { + inputfifo_send_line(data, width, + hblank_cycles, + marker_cycles, + two_ppc, type); + data += width; + } + } + inputfifo_end_frame(marker_cycles); + return; +} + +static enum inputfifo_mipi_data_type inputfifo_determine_type( + enum atomisp_input_format input_format) +{ + enum inputfifo_mipi_data_type type; + + type = inputfifo_mipi_data_type_regular; + if (input_format == ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY) { + type = + inputfifo_mipi_data_type_yuv420_legacy; + } else if (input_format == ATOMISP_INPUT_FORMAT_YUV420_8 || + input_format == ATOMISP_INPUT_FORMAT_YUV420_10 || + input_format == ATOMISP_INPUT_FORMAT_YUV420_16) { + type = + inputfifo_mipi_data_type_yuv420; + } else if (input_format >= ATOMISP_INPUT_FORMAT_RGB_444 && + input_format <= ATOMISP_INPUT_FORMAT_RGB_888) { + type = + inputfifo_mipi_data_type_rgb; + } + return type; +} + +static struct inputfifo_instance *inputfifo_get_inst( + unsigned int ch_id) +{ + return &inputfifo_inst_admin[ch_id]; +} + +void ia_css_inputfifo_send_input_frame( + const unsigned short *data, + unsigned int width, + unsigned int height, + unsigned int ch_id, + enum atomisp_input_format input_format, + bool two_ppc) +{ + unsigned int fmt_type, hblank_cycles, marker_cycles; + enum inputfifo_mipi_data_type type; + + assert(data); + hblank_cycles = HBLANK_CYCLES; + marker_cycles = MARKER_CYCLES; + ia_css_isys_convert_stream_format_to_mipi_format(input_format, + MIPI_PREDICTOR_NONE, + &fmt_type); + + type = inputfifo_determine_type(input_format); + + inputfifo_send_frame(data, width, height, + ch_id, fmt_type, hblank_cycles, marker_cycles, + two_ppc, type); +} + +void ia_css_inputfifo_start_frame( + unsigned int ch_id, + enum atomisp_input_format input_format, + bool two_ppc) +{ + struct inputfifo_instance *s2mi; + + s2mi = inputfifo_get_inst(ch_id); + + s2mi->ch_id = ch_id; + ia_css_isys_convert_stream_format_to_mipi_format(input_format, + MIPI_PREDICTOR_NONE, + &s2mi->fmt_type); + s2mi->two_ppc = two_ppc; + s2mi->type = inputfifo_determine_type(input_format); + s2mi->hblank_cycles = HBLANK_CYCLES; + s2mi->marker_cycles = MARKER_CYCLES; + s2mi->streaming = true; + + inputfifo_start_frame(ch_id, s2mi->fmt_type); + return; +} + +void ia_css_inputfifo_send_line( + unsigned int ch_id, + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2) +{ + struct inputfifo_instance *s2mi; + + assert(data); + assert((data2) || (width2 == 0)); + s2mi = inputfifo_get_inst(ch_id); + + /* Set global variables that indicate channel_id and format_type */ + inputfifo_curr_ch_id = (s2mi->ch_id) & _HIVE_ISP_CH_ID_MASK; + inputfifo_curr_fmt_type = (s2mi->fmt_type) & _HIVE_ISP_FMT_TYPE_MASK; + + inputfifo_send_line2(data, width, data2, width2, + s2mi->hblank_cycles, + s2mi->marker_cycles, + s2mi->two_ppc, + s2mi->type); +} + +void ia_css_inputfifo_send_embedded_line( + unsigned int ch_id, + enum atomisp_input_format data_type, + const unsigned short *data, + unsigned int width) +{ + struct inputfifo_instance *s2mi; + unsigned int fmt_type; + + assert(data); + s2mi = inputfifo_get_inst(ch_id); + ia_css_isys_convert_stream_format_to_mipi_format(data_type, + MIPI_PREDICTOR_NONE, &fmt_type); + + /* Set format_type for metadata line. */ + inputfifo_curr_fmt_type = fmt_type & _HIVE_ISP_FMT_TYPE_MASK; + + inputfifo_send_line(data, width, s2mi->hblank_cycles, s2mi->marker_cycles, + s2mi->two_ppc, inputfifo_mipi_data_type_regular); +} + +void ia_css_inputfifo_end_frame( + unsigned int ch_id) +{ + struct inputfifo_instance *s2mi; + + s2mi = inputfifo_get_inst(ch_id); + + /* Set global variables that indicate channel_id and format_type */ + inputfifo_curr_ch_id = (s2mi->ch_id) & _HIVE_ISP_CH_ID_MASK; + inputfifo_curr_fmt_type = (s2mi->fmt_type) & _HIVE_ISP_FMT_TYPE_MASK; + + /* Call existing HRT function */ + inputfifo_end_frame(s2mi->marker_cycles); + + s2mi->streaming = false; + return; +} diff --git a/drivers/staging/media/atomisp/pci/runtime/isp_param/interface/ia_css_isp_param.h b/drivers/staging/media/atomisp/pci/runtime/isp_param/interface/ia_css_isp_param.h new file mode 100644 index 000000000..0ea5d6fdc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isp_param/interface/ia_css_isp_param.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_ISP_PARAM_H_ +#define _IA_CSS_ISP_PARAM_H_ + +#include +#include "ia_css_isp_param_types.h" + +/* Set functions for parameter memory descriptors */ +void +ia_css_isp_param_set_mem_init( + struct ia_css_isp_param_host_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + char *address, size_t size); + +void +ia_css_isp_param_set_css_mem_init( + struct ia_css_isp_param_css_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + ia_css_ptr address, size_t size); + +void +ia_css_isp_param_set_isp_mem_init( + struct ia_css_isp_param_isp_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + u32 address, size_t size); + +/* Get functions for parameter memory descriptors */ +const struct ia_css_host_data * +ia_css_isp_param_get_mem_init( + const struct ia_css_isp_param_host_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem); + +const struct ia_css_data * +ia_css_isp_param_get_css_mem_init( + const struct ia_css_isp_param_css_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem); + +const struct ia_css_isp_data * +ia_css_isp_param_get_isp_mem_init( + const struct ia_css_isp_param_isp_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem); + +/* Initialize the memory interface sizes and addresses */ +void +ia_css_init_memory_interface( + struct ia_css_isp_param_css_segments *isp_mem_if, + const struct ia_css_isp_param_host_segments *mem_params, + const struct ia_css_isp_param_css_segments *css_params); + +/* Allocate memory parameters */ +int +ia_css_isp_param_allocate_isp_parameters( + struct ia_css_isp_param_host_segments *mem_params, + struct ia_css_isp_param_css_segments *css_params, + const struct ia_css_isp_param_isp_segments *mem_initializers); + +/* Destroy memory parameters */ +void +ia_css_isp_param_destroy_isp_parameters( + struct ia_css_isp_param_host_segments *mem_params, + struct ia_css_isp_param_css_segments *css_params); + +/* Load fw parameters */ +void +ia_css_isp_param_load_fw_params( + const char *fw, + union ia_css_all_memory_offsets *mem_offsets, + const struct ia_css_isp_param_memory_offsets *memory_offsets, + bool init); + +/* Copy host parameter images to ddr */ +int +ia_css_isp_param_copy_isp_mem_if_to_ddr( + struct ia_css_isp_param_css_segments *ddr, + const struct ia_css_isp_param_host_segments *host, + enum ia_css_param_class pclass); + +/* Enable a pipeline by setting the control field in the isp dmem parameters */ +void +ia_css_isp_param_enable_pipeline( + const struct ia_css_isp_param_host_segments *mem_params); + +#endif /* _IA_CSS_ISP_PARAM_H_ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isp_param/interface/ia_css_isp_param_types.h b/drivers/staging/media/atomisp/pci/runtime/isp_param/interface/ia_css_isp_param_types.h new file mode 100644 index 000000000..8cdeae98b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isp_param/interface/ia_css_isp_param_types.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef _IA_CSS_ISP_PARAM_TYPES_H_ +#define _IA_CSS_ISP_PARAM_TYPES_H_ + +#include "ia_css_types.h" +#include +#include + +/* Short hands */ +#define IA_CSS_ISP_DMEM IA_CSS_ISP_DMEM0 +#define IA_CSS_ISP_VMEM IA_CSS_ISP_VMEM0 + +/* The driver depends on this, to be removed later. */ +#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES + +/* Explicit member numbering to avoid fish type checker bug */ +enum ia_css_param_class { + IA_CSS_PARAM_CLASS_PARAM = 0, /* Late binding parameters, like 3A */ + IA_CSS_PARAM_CLASS_CONFIG = 1, /* Pipe config time parameters, like resolution */ + IA_CSS_PARAM_CLASS_STATE = 2, /* State parameters, like tnr buffer index */ +#if 0 /* Not yet implemented */ + IA_CSS_PARAM_CLASS_FRAME = 3, /* Frame time parameters, like output buffer */ +#endif +}; + +#define IA_CSS_NUM_PARAM_CLASSES (IA_CSS_PARAM_CLASS_STATE + 1) + +/* ISP parameter descriptor */ +struct ia_css_isp_parameter { + u32 offset; /* Offset in isp_)parameters, etc. */ + u32 size; /* Disabled if 0 */ +}; + +/* Address/size of each parameter class in each isp memory, host memory pointers */ +struct ia_css_isp_param_host_segments { + struct ia_css_host_data params[IA_CSS_NUM_PARAM_CLASSES][IA_CSS_NUM_MEMORIES]; +}; + +/* Address/size of each parameter class in each isp memory, css memory pointers */ +struct ia_css_isp_param_css_segments { + struct ia_css_data params[IA_CSS_NUM_PARAM_CLASSES][IA_CSS_NUM_MEMORIES]; +}; + +/* Address/size of each parameter class in each isp memory, isp memory pointers */ +struct ia_css_isp_param_isp_segments { + struct ia_css_isp_data params[IA_CSS_NUM_PARAM_CLASSES][IA_CSS_NUM_MEMORIES]; +}; + +/* Memory offsets in binary info */ +struct ia_css_isp_param_memory_offsets { + u32 offsets[IA_CSS_NUM_PARAM_CLASSES]; /** offset wrt hdr in bytes */ +}; + +/* Offsets for ISP kernel parameters per isp memory. + * Only relevant for standard ISP binaries, not ACC or SP. + */ +union ia_css_all_memory_offsets { + struct { + CSS_ALIGN(struct ia_css_memory_offsets *param, 8); + CSS_ALIGN(struct ia_css_config_memory_offsets *config, 8); + CSS_ALIGN(struct ia_css_state_memory_offsets *state, 8); + } offsets; + struct { + CSS_ALIGN(void *ptr, 8); + } array[IA_CSS_NUM_PARAM_CLASSES]; +}; + +#endif /* _IA_CSS_ISP_PARAM_TYPES_H_ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isp_param/src/isp_param.c b/drivers/staging/media/atomisp/pci/runtime/isp_param/src/isp_param.c new file mode 100644 index 000000000..99c2f3a53 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isp_param/src/isp_param.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include "ia_css_pipeline.h" +#include "ia_css_isp_param.h" + +/* Set functions for parameter memory descriptors */ + +void +ia_css_isp_param_set_mem_init( + struct ia_css_isp_param_host_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + char *address, size_t size) +{ + mem_init->params[pclass][mem].address = address; + mem_init->params[pclass][mem].size = (uint32_t)size; +} + +void +ia_css_isp_param_set_css_mem_init( + struct ia_css_isp_param_css_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + ia_css_ptr address, size_t size) +{ + mem_init->params[pclass][mem].address = address; + mem_init->params[pclass][mem].size = (uint32_t)size; +} + +void +ia_css_isp_param_set_isp_mem_init( + struct ia_css_isp_param_isp_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + u32 address, size_t size) +{ + mem_init->params[pclass][mem].address = address; + mem_init->params[pclass][mem].size = (uint32_t)size; +} + +/* Get functions for parameter memory descriptors */ +const struct ia_css_host_data * +ia_css_isp_param_get_mem_init( + const struct ia_css_isp_param_host_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem) +{ + return &mem_init->params[pclass][mem]; +} + +const struct ia_css_data * +ia_css_isp_param_get_css_mem_init( + const struct ia_css_isp_param_css_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem) +{ + return &mem_init->params[pclass][mem]; +} + +const struct ia_css_isp_data * +ia_css_isp_param_get_isp_mem_init( + const struct ia_css_isp_param_isp_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem) +{ + return &mem_init->params[pclass][mem]; +} + +void +ia_css_init_memory_interface( + struct ia_css_isp_param_css_segments *isp_mem_if, + const struct ia_css_isp_param_host_segments *mem_params, + const struct ia_css_isp_param_css_segments *css_params) +{ + unsigned int pclass, mem; + + for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) { + memset(isp_mem_if->params[pclass], 0, sizeof(isp_mem_if->params[pclass])); + for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) { + if (!mem_params->params[pclass][mem].address) + continue; + isp_mem_if->params[pclass][mem].size = mem_params->params[pclass][mem].size; + if (pclass != IA_CSS_PARAM_CLASS_PARAM) + isp_mem_if->params[pclass][mem].address = + css_params->params[pclass][mem].address; + } + } +} + +int +ia_css_isp_param_allocate_isp_parameters( + struct ia_css_isp_param_host_segments *mem_params, + struct ia_css_isp_param_css_segments *css_params, + const struct ia_css_isp_param_isp_segments *mem_initializers) { + int err = 0; + unsigned int mem, pclass; + + pclass = IA_CSS_PARAM_CLASS_PARAM; + for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) + { + for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) { + u32 size = 0; + + if (mem_initializers) + size = mem_initializers->params[pclass][mem].size; + mem_params->params[pclass][mem].size = size; + mem_params->params[pclass][mem].address = NULL; + css_params->params[pclass][mem].size = size; + css_params->params[pclass][mem].address = 0x0; + if (size) { + mem_params->params[pclass][mem].address = kvcalloc(1, + size, + GFP_KERNEL); + if (!mem_params->params[pclass][mem].address) { + err = -ENOMEM; + goto cleanup; + } + if (pclass != IA_CSS_PARAM_CLASS_PARAM) { + css_params->params[pclass][mem].address = hmm_alloc(size); + if (!css_params->params[pclass][mem].address) { + err = -ENOMEM; + goto cleanup; + } + } + } + } + } + return err; +cleanup: + ia_css_isp_param_destroy_isp_parameters(mem_params, css_params); + return err; +} + +void +ia_css_isp_param_destroy_isp_parameters( + struct ia_css_isp_param_host_segments *mem_params, + struct ia_css_isp_param_css_segments *css_params) +{ + unsigned int mem, pclass; + + for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) { + for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) { + kvfree(mem_params->params[pclass][mem].address); + if (css_params->params[pclass][mem].address) + hmm_free(css_params->params[pclass][mem].address); + mem_params->params[pclass][mem].address = NULL; + css_params->params[pclass][mem].address = 0x0; + } + } +} + +void +ia_css_isp_param_load_fw_params( + const char *fw, + union ia_css_all_memory_offsets *mem_offsets, + const struct ia_css_isp_param_memory_offsets *memory_offsets, + bool init) +{ + unsigned int pclass; + + for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) { + mem_offsets->array[pclass].ptr = NULL; + if (init) + mem_offsets->array[pclass].ptr = (void *)(fw + memory_offsets->offsets[pclass]); + } +} + +int +ia_css_isp_param_copy_isp_mem_if_to_ddr( + struct ia_css_isp_param_css_segments *ddr, + const struct ia_css_isp_param_host_segments *host, + enum ia_css_param_class pclass) { + unsigned int mem; + + for (mem = 0; mem < N_IA_CSS_ISP_MEMORIES; mem++) + { + size_t size = host->params[pclass][mem].size; + ia_css_ptr ddr_mem_ptr = ddr->params[pclass][mem].address; + char *host_mem_ptr = host->params[pclass][mem].address; + + if (size != ddr->params[pclass][mem].size) + return -EINVAL; + if (!size) + continue; + hmm_store(ddr_mem_ptr, host_mem_ptr, size); + } + return 0; +} + +void +ia_css_isp_param_enable_pipeline( + const struct ia_css_isp_param_host_segments *mem_params) +{ + /* By protocol b0 of the mandatory uint32_t first field of the + input parameter is a disable bit*/ + short dmem_offset = 0; + + if (mem_params->params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM0].size == 0) + return; + + *(uint32_t *) + &mem_params->params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM0].address[dmem_offset] + = 0x0; +} diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/interface/ia_css_isys.h b/drivers/staging/media/atomisp/pci/runtime/isys/interface/ia_css_isys.h new file mode 100644 index 000000000..711a321e9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/interface/ia_css_isys.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ISYS_H__ +#define __IA_CSS_ISYS_H__ + +#include +#include +#include +#include +#include +#include +#include "ia_css_isys_comm.h" + +#ifdef ISP2401 +/** + * Virtual Input System. (Input System 2401) + */ +typedef isp2401_input_system_cfg_t ia_css_isys_descr_t; +/* end of Virtual Input System */ +#endif + +input_system_err_t ia_css_isys_init(void); +void ia_css_isys_uninit(void); +enum mipi_port_id ia_css_isys_port_to_mipi_port( + enum mipi_port_id api_port); + +#if defined(ISP2401) + +/** + * @brief Register one (virtual) stream. This is used to track when all + * virtual streams are configured inside the input system. The CSI RX is + * only started when all registered streams are configured. + * + * @param[in] port CSI port + * @param[in] isys_stream_id Stream handle generated with ia_css_isys_generate_stream_id() + * Must be lower than SH_CSS_MAX_ISYS_CHANNEL_NODES + * @return 0 if successful, -EINVAL if + * there is already a stream registered with the same handle + */ +int ia_css_isys_csi_rx_register_stream( + enum mipi_port_id port, + uint32_t isys_stream_id); + +/** + * @brief Unregister one (virtual) stream. This is used to track when all + * virtual streams are configured inside the input system. The CSI RX is + * only started when all registered streams are configured. + * + * @param[in] port CSI port + * @param[in] isys_stream_id Stream handle generated with ia_css_isys_generate_stream_id() + * Must be lower than SH_CSS_MAX_ISYS_CHANNEL_NODES + * @return 0 if successful, -EINVAL if + * there is no stream registered with that handle + */ +int ia_css_isys_csi_rx_unregister_stream( + enum mipi_port_id port, + uint32_t isys_stream_id); + +int ia_css_isys_convert_compressed_format( + struct ia_css_csi2_compression *comp, + struct isp2401_input_system_cfg_s *cfg); +unsigned int ia_css_csi2_calculate_input_system_alignment( + enum atomisp_input_format fmt_type); +#endif + +#if !defined(ISP2401) +/* CSS Receiver */ +void ia_css_isys_rx_configure( + const rx_cfg_t *config, + const enum ia_css_input_mode input_mode); + +void ia_css_isys_rx_disable(void); + +void ia_css_isys_rx_enable_all_interrupts(enum mipi_port_id port); + +unsigned int ia_css_isys_rx_get_interrupt_reg(enum mipi_port_id port); +void ia_css_isys_rx_get_irq_info(enum mipi_port_id port, + unsigned int *irq_infos); +void ia_css_isys_rx_clear_irq_info(enum mipi_port_id port, + unsigned int irq_infos); +unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits); + +#endif /* #if !defined(ISP2401) */ + +/* @brief Translate format and compression to format type. + * + * @param[in] input_format The input format. + * @param[in] compression The compression scheme. + * @param[out] fmt_type Pointer to the resulting format type. + * @return Error code. + * + * Translate an input format and mipi compression pair to the fmt_type. + * This is normally done by the sensor, but when using the input fifo, this + * format type must be sumitted correctly by the application. + */ +int ia_css_isys_convert_stream_format_to_mipi_format( + enum atomisp_input_format input_format, + mipi_predictor_t compression, + unsigned int *fmt_type); + +#ifdef ISP2401 +/** + * Virtual Input System. (Input System 2401) + */ +ia_css_isys_error_t ia_css_isys_stream_create( + ia_css_isys_descr_t *isys_stream_descr, + ia_css_isys_stream_h isys_stream, + uint32_t isys_stream_id); + +void ia_css_isys_stream_destroy( + ia_css_isys_stream_h isys_stream); + +ia_css_isys_error_t ia_css_isys_stream_calculate_cfg( + ia_css_isys_stream_h isys_stream, + ia_css_isys_descr_t *isys_stream_descr, + ia_css_isys_stream_cfg_t *isys_stream_cfg); + +void ia_css_isys_csi_rx_lut_rmgr_init(void); + +void ia_css_isys_csi_rx_lut_rmgr_uninit(void); + +bool ia_css_isys_csi_rx_lut_rmgr_acquire( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry); + +void ia_css_isys_csi_rx_lut_rmgr_release( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry); + +void ia_css_isys_ibuf_rmgr_init(void); + +void ia_css_isys_ibuf_rmgr_uninit(void); + +bool ia_css_isys_ibuf_rmgr_acquire( + u32 size, + uint32_t *start_addr); + +void ia_css_isys_ibuf_rmgr_release( + uint32_t *start_addr); + +void ia_css_isys_dma_channel_rmgr_init(void); + +void ia_css_isys_dma_channel_rmgr_uninit(void); + +bool ia_css_isys_dma_channel_rmgr_acquire( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel); + +void ia_css_isys_dma_channel_rmgr_release( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel); + +void ia_css_isys_stream2mmio_sid_rmgr_init(void); + +void ia_css_isys_stream2mmio_sid_rmgr_uninit(void); + +bool ia_css_isys_stream2mmio_sid_rmgr_acquire( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid); + +void ia_css_isys_stream2mmio_sid_rmgr_release( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid); + +/* end of Virtual Input System */ +#endif + +#endif /* __IA_CSS_ISYS_H__ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/interface/ia_css_isys_comm.h b/drivers/staging/media/atomisp/pci/runtime/isys/interface/ia_css_isys_comm.h new file mode 100644 index 000000000..d80ef42c7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/interface/ia_css_isys_comm.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ISYS_COMM_H +#define __IA_CSS_ISYS_COMM_H + +#include +#include + +#ifdef ISP2401 +#include /* inline */ +#include +#include /* IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH */ + +#define SH_CSS_NODES_PER_THREAD 2 +#define SH_CSS_MAX_ISYS_CHANNEL_NODES (SH_CSS_MAX_SP_THREADS * SH_CSS_NODES_PER_THREAD) + +/* + * a) ia_css_isys_stream_h & ia_css_isys_stream_cfg_t come from host. + * + * b) Here it is better to use actual structures for stream handle + * instead of opaque handles. Otherwise, we need to have another + * communication channel to interpret that opaque handle(this handle is + * maintained by host and needs to be populated to sp for every stream open) + * */ +typedef virtual_input_system_stream_t *ia_css_isys_stream_h; +typedef virtual_input_system_stream_cfg_t ia_css_isys_stream_cfg_t; + +/* + * error check for ISYS APIs. + * */ +typedef bool ia_css_isys_error_t; + +static inline uint32_t ia_css_isys_generate_stream_id( + u32 sp_thread_id, + uint32_t stream_id) +{ + return sp_thread_id * IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH + stream_id; +} + +#endif /* ISP2401*/ +#endif /*_IA_CSS_ISYS_COMM_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/csi_rx_rmgr.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/csi_rx_rmgr.c new file mode 100644 index 000000000..3fc9fed1e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/csi_rx_rmgr.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" + +#ifdef ISP2401 + +#include "assert_support.h" +#include "platform_support.h" +#include "ia_css_isys.h" +#include "bitop_support.h" +#include "ia_css_pipeline.h" /* ia_css_pipeline_get_pipe_io_status() */ +#include "sh_css_internal.h" /* sh_css_sp_pipeline_io_status + * SH_CSS_MAX_SP_THREADS + */ +#include "csi_rx_rmgr.h" + +static isys_csi_rx_rsrc_t isys_csi_rx_rsrc[N_CSI_RX_BACKEND_ID]; + +void ia_css_isys_csi_rx_lut_rmgr_init(void) +{ + memset(isys_csi_rx_rsrc, 0, sizeof(isys_csi_rx_rsrc)); +} + +void ia_css_isys_csi_rx_lut_rmgr_uninit(void) +{ + memset(isys_csi_rx_rsrc, 0, sizeof(isys_csi_rx_rsrc)); +} + +bool ia_css_isys_csi_rx_lut_rmgr_acquire( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry) +{ + bool retval = false; + u32 max_num_packets_of_type; + u32 num_active_of_type; + isys_csi_rx_rsrc_t *cur_rsrc = NULL; + u16 i; + + assert(backend < N_CSI_RX_BACKEND_ID); + assert((packet_type == CSI_MIPI_PACKET_TYPE_LONG) || + (packet_type == CSI_MIPI_PACKET_TYPE_SHORT)); + assert(entry); + + if ((backend < N_CSI_RX_BACKEND_ID) && (entry)) { + cur_rsrc = &isys_csi_rx_rsrc[backend]; + if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) { + max_num_packets_of_type = N_LONG_PACKET_LUT_ENTRIES[backend]; + num_active_of_type = cur_rsrc->num_long_packets; + } else { + max_num_packets_of_type = N_SHORT_PACKET_LUT_ENTRIES[backend]; + num_active_of_type = cur_rsrc->num_short_packets; + } + + if (num_active_of_type < max_num_packets_of_type) { + for (i = 0; i < max_num_packets_of_type; i++) { + if (bitop_getbit(cur_rsrc->active_table, i) == 0) { + bitop_setbit(cur_rsrc->active_table, i); + + if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) { + entry->long_packet_entry = i; + entry->short_packet_entry = 0; + cur_rsrc->num_long_packets++; + } else { + entry->long_packet_entry = 0; + entry->short_packet_entry = i; + cur_rsrc->num_short_packets++; + } + cur_rsrc->num_active++; + retval = true; + break; + } + } + } + } + return retval; +} + +void ia_css_isys_csi_rx_lut_rmgr_release( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry) +{ + u32 max_num_packets; + isys_csi_rx_rsrc_t *cur_rsrc = NULL; + u32 packet_entry = 0; + + assert(backend < N_CSI_RX_BACKEND_ID); + assert(entry); + assert((packet_type >= CSI_MIPI_PACKET_TYPE_LONG) || + (packet_type <= CSI_MIPI_PACKET_TYPE_SHORT)); + + if ((backend < N_CSI_RX_BACKEND_ID) && (entry)) { + if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) { + max_num_packets = N_LONG_PACKET_LUT_ENTRIES[backend]; + packet_entry = entry->long_packet_entry; + } else { + max_num_packets = N_SHORT_PACKET_LUT_ENTRIES[backend]; + packet_entry = entry->short_packet_entry; + } + + cur_rsrc = &isys_csi_rx_rsrc[backend]; + if ((packet_entry < max_num_packets) && (cur_rsrc->num_active > 0)) { + if (bitop_getbit(cur_rsrc->active_table, packet_entry) == 1) { + bitop_clearbit(cur_rsrc->active_table, packet_entry); + + if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) + cur_rsrc->num_long_packets--; + else + cur_rsrc->num_short_packets--; + cur_rsrc->num_active--; + } + } + } +} + +int ia_css_isys_csi_rx_register_stream( + enum mipi_port_id port, + uint32_t isys_stream_id) +{ + int retval = -EINVAL; + + if ((port < N_INPUT_SYSTEM_CSI_PORT) && + (isys_stream_id < SH_CSS_MAX_ISYS_CHANNEL_NODES)) { + struct sh_css_sp_pipeline_io_status *pipe_io_status; + + pipe_io_status = ia_css_pipeline_get_pipe_io_status(); + if (bitop_getbit(pipe_io_status->active[port], isys_stream_id) == 0) { + bitop_setbit(pipe_io_status->active[port], isys_stream_id); + pipe_io_status->running[port] = 0; + retval = 0; + } + } + return retval; +} + +int ia_css_isys_csi_rx_unregister_stream( + enum mipi_port_id port, + uint32_t isys_stream_id) +{ + int retval = -EINVAL; + + if ((port < N_INPUT_SYSTEM_CSI_PORT) && + (isys_stream_id < SH_CSS_MAX_ISYS_CHANNEL_NODES)) { + struct sh_css_sp_pipeline_io_status *pipe_io_status; + + pipe_io_status = ia_css_pipeline_get_pipe_io_status(); + if (bitop_getbit(pipe_io_status->active[port], isys_stream_id) == 1) { + bitop_clearbit(pipe_io_status->active[port], isys_stream_id); + retval = 0; + } + } + return retval; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/csi_rx_rmgr.h b/drivers/staging/media/atomisp/pci/runtime/isys/src/csi_rx_rmgr.h new file mode 100644 index 000000000..11f730dc1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/csi_rx_rmgr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_RMGR_H_INCLUDED__ +#define __CSI_RX_RMGR_H_INCLUDED__ + +typedef struct isys_csi_rx_rsrc_s isys_csi_rx_rsrc_t; +struct isys_csi_rx_rsrc_s { + u32 active_table; + u32 num_active; + u16 num_long_packets; + u16 num_short_packets; +}; + +#endif /* __CSI_RX_RMGR_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/ibuf_ctrl_rmgr.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/ibuf_ctrl_rmgr.c new file mode 100644 index 000000000..9710493c4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/ibuf_ctrl_rmgr.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" + +#include "assert_support.h" +#include "platform_support.h" +#include "ia_css_isys.h" +#include "ibuf_ctrl_rmgr.h" + +static ibuf_rsrc_t ibuf_rsrc; + +static ibuf_handle_t *getHandle(uint16_t index) +{ + ibuf_handle_t *handle = NULL; + + if (index < MAX_IBUF_HANDLES) + handle = &ibuf_rsrc.handles[index]; + return handle; +} + +void ia_css_isys_ibuf_rmgr_init(void) +{ + memset(&ibuf_rsrc, 0, sizeof(ibuf_rsrc)); + ibuf_rsrc.free_size = MAX_INPUT_BUFFER_SIZE; +} + +void ia_css_isys_ibuf_rmgr_uninit(void) +{ + memset(&ibuf_rsrc, 0, sizeof(ibuf_rsrc)); + ibuf_rsrc.free_size = MAX_INPUT_BUFFER_SIZE; +} + +bool ia_css_isys_ibuf_rmgr_acquire( + u32 size, + uint32_t *start_addr) +{ + bool retval = false; + bool input_buffer_found = false; + u32 aligned_size; + ibuf_handle_t *handle = NULL; + u16 i; + + assert(start_addr); + assert(size > 0); + + aligned_size = (size + (IBUF_ALIGN - 1)) & ~(IBUF_ALIGN - 1); + + /* Check if there is an available un-used handle with the size + * that will fulfill the request. + */ + if (ibuf_rsrc.num_active < ibuf_rsrc.num_allocated) { + for (i = 0; i < ibuf_rsrc.num_allocated; i++) { + handle = getHandle(i); + if (!handle->active) { + if (handle->size >= aligned_size) { + handle->active = true; + input_buffer_found = true; + ibuf_rsrc.num_active++; + break; + } + } + } + } + + if (!input_buffer_found) { + /* There were no available handles that fulfilled the + * request. Allocate a new handle with the requested size. + */ + if ((ibuf_rsrc.num_allocated < MAX_IBUF_HANDLES) && + (ibuf_rsrc.free_size >= aligned_size)) { + handle = getHandle(ibuf_rsrc.num_allocated); + handle->start_addr = ibuf_rsrc.free_start_addr; + handle->size = aligned_size; + handle->active = true; + + ibuf_rsrc.free_start_addr += aligned_size; + ibuf_rsrc.free_size -= aligned_size; + ibuf_rsrc.num_active++; + ibuf_rsrc.num_allocated++; + + input_buffer_found = true; + } + } + + if (input_buffer_found && handle) { + *start_addr = handle->start_addr; + retval = true; + } + + return retval; +} + +void ia_css_isys_ibuf_rmgr_release( + uint32_t *start_addr) +{ + u16 i; + ibuf_handle_t *handle = NULL; + + assert(start_addr); + + for (i = 0; i < ibuf_rsrc.num_allocated; i++) { + handle = getHandle(i); + if (handle->active && handle->start_addr == *start_addr) { + handle->active = false; + ibuf_rsrc.num_active--; + break; + } + } +} diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/ibuf_ctrl_rmgr.h b/drivers/staging/media/atomisp/pci/runtime/isys/src/ibuf_ctrl_rmgr.h new file mode 100644 index 000000000..7c754ec72 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/ibuf_ctrl_rmgr.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_RMGR_H_INCLUDED__ +#define __IBUF_CTRL_RMGR_H_INCLUDED__ + +#define MAX_IBUF_HANDLES 24 +#define MAX_INPUT_BUFFER_SIZE (64 * 1024) +#define IBUF_ALIGN 8 + +typedef struct ibuf_handle_s ibuf_handle_t; +struct ibuf_handle_s { + u32 start_addr; + u32 size; + bool active; +}; + +typedef struct ibuf_rsrc_s ibuf_rsrc_t; +struct ibuf_rsrc_s { + u32 free_start_addr; + u32 free_size; + u16 num_active; + u16 num_allocated; + ibuf_handle_t handles[MAX_IBUF_HANDLES]; +}; + +#endif /* __IBUF_CTRL_RMGR_H_INCLUDED */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_dma_rmgr.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_dma_rmgr.c new file mode 100644 index 000000000..261c6460e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_dma_rmgr.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" + +#ifdef ISP2401 + +#include "assert_support.h" +#include "platform_support.h" +#include "ia_css_isys.h" +#include "bitop_support.h" +#include "isys_dma_rmgr.h" + +static isys_dma_rsrc_t isys_dma_rsrc[N_ISYS2401_DMA_ID]; + +void ia_css_isys_dma_channel_rmgr_init(void) +{ + memset(&isys_dma_rsrc, 0, sizeof(isys_dma_rsrc_t)); +} + +void ia_css_isys_dma_channel_rmgr_uninit(void) +{ + memset(&isys_dma_rsrc, 0, sizeof(isys_dma_rsrc_t)); +} + +bool ia_css_isys_dma_channel_rmgr_acquire( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel) +{ + bool retval = false; + isys2401_dma_channel i; + isys2401_dma_channel max_dma_channel; + isys_dma_rsrc_t *cur_rsrc = NULL; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(channel); + + max_dma_channel = N_ISYS2401_DMA_CHANNEL_PROCS[dma_id]; + cur_rsrc = &isys_dma_rsrc[dma_id]; + + if (cur_rsrc->num_active < max_dma_channel) { + for (i = ISYS2401_DMA_CHANNEL_0; i < N_ISYS2401_DMA_CHANNEL; i++) { + if (bitop_getbit(cur_rsrc->active_table, i) == 0) { + bitop_setbit(cur_rsrc->active_table, i); + *channel = i; + cur_rsrc->num_active++; + retval = true; + break; + } + } + } + + return retval; +} + +void ia_css_isys_dma_channel_rmgr_release( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel) +{ + isys2401_dma_channel max_dma_channel; + isys_dma_rsrc_t *cur_rsrc = NULL; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(channel); + + max_dma_channel = N_ISYS2401_DMA_CHANNEL_PROCS[dma_id]; + cur_rsrc = &isys_dma_rsrc[dma_id]; + + if ((*channel < max_dma_channel) && (cur_rsrc->num_active > 0)) { + if (bitop_getbit(cur_rsrc->active_table, *channel) == 1) { + bitop_clearbit(cur_rsrc->active_table, *channel); + cur_rsrc->num_active--; + } + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_dma_rmgr.h b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_dma_rmgr.h new file mode 100644 index 000000000..88c3d5581 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_dma_rmgr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_RMGR_H_INCLUDED__ +#define __ISYS_DMA_RMGR_H_INCLUDED__ + +typedef struct isys_dma_rsrc_s isys_dma_rsrc_t; +struct isys_dma_rsrc_s { + u32 active_table; + u16 num_active; +}; + +#endif /* __ISYS_DMA_RMGR_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_init.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_init.c new file mode 100644 index 000000000..d0a43c449 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_init.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "input_system.h" + +#include "ia_css_isys.h" +#include "platform_support.h" + +#ifdef ISP2401 +#include "isys_dma_public.h" /* isys2401_dma_set_max_burst_size() */ +#include "isys_irq.h" +#endif + +#if !defined(ISP2401) +input_system_err_t ia_css_isys_init(void) +{ + backend_channel_cfg_t backend_ch0; + backend_channel_cfg_t backend_ch1; + target_cfg2400_t targetB; + target_cfg2400_t targetC; + u32 acq_mem_region_size = 24; + u32 acq_nof_mem_regions = 2; + input_system_err_t error = INPUT_SYSTEM_ERR_NO_ERROR; + + memset(&backend_ch0, 0, sizeof(backend_channel_cfg_t)); + memset(&backend_ch1, 0, sizeof(backend_channel_cfg_t)); + memset(&targetB, 0, sizeof(targetB)); + memset(&targetC, 0, sizeof(targetC)); + + error = input_system_configuration_reset(); + if (error != INPUT_SYSTEM_ERR_NO_ERROR) + return error; + + error = input_system_csi_xmem_channel_cfg( + 0, /*ch_id */ + INPUT_SYSTEM_PORT_A, /*port */ + backend_ch0, /*backend_ch */ + 32, /*mem_region_size */ + 6, /*nof_mem_regions */ + acq_mem_region_size, /*acq_mem_region_size */ + acq_nof_mem_regions, /*acq_nof_mem_regions */ + targetB, /*target */ + 3); /*nof_xmem_buffers */ + if (error != INPUT_SYSTEM_ERR_NO_ERROR) + return error; + + error = input_system_csi_xmem_channel_cfg( + 1, /*ch_id */ + INPUT_SYSTEM_PORT_B, /*port */ + backend_ch0, /*backend_ch */ + 16, /*mem_region_size */ + 3, /*nof_mem_regions */ + acq_mem_region_size, /*acq_mem_region_size */ + acq_nof_mem_regions, /*acq_nof_mem_regions */ + targetB, /*target */ + 3); /*nof_xmem_buffers */ + if (error != INPUT_SYSTEM_ERR_NO_ERROR) + return error; + + error = input_system_csi_xmem_channel_cfg( + 2, /*ch_id */ + INPUT_SYSTEM_PORT_C, /*port */ + backend_ch1, /*backend_ch */ + 32, /*mem_region_size */ + 3, /*nof_mem_regions */ + acq_mem_region_size, /*acq_mem_region_size */ + acq_nof_mem_regions, /*acq_nof_mem_regions */ + targetC, /*target */ + 2); /*nof_xmem_buffers */ + if (error != INPUT_SYSTEM_ERR_NO_ERROR) + return error; + + error = input_system_configuration_commit(); + + return error; +} +#elif defined(ISP2401) +input_system_err_t ia_css_isys_init(void) +{ + ia_css_isys_csi_rx_lut_rmgr_init(); + ia_css_isys_ibuf_rmgr_init(); + ia_css_isys_dma_channel_rmgr_init(); + ia_css_isys_stream2mmio_sid_rmgr_init(); + + isys2401_dma_set_max_burst_size(ISYS2401_DMA0_ID, + 1 /* Non Burst DMA transactions */); + + /* Enable 2401 input system IRQ status for driver to retrieve */ + isys_irqc_status_enable(ISYS_IRQ0_ID); + isys_irqc_status_enable(ISYS_IRQ1_ID); + isys_irqc_status_enable(ISYS_IRQ2_ID); + + return INPUT_SYSTEM_ERR_NO_ERROR; +} +#endif + +#if !defined(ISP2401) +void ia_css_isys_uninit(void) +{ +} +#elif defined(ISP2401) +void ia_css_isys_uninit(void) +{ + ia_css_isys_csi_rx_lut_rmgr_uninit(); + ia_css_isys_ibuf_rmgr_uninit(); + ia_css_isys_dma_channel_rmgr_uninit(); + ia_css_isys_stream2mmio_sid_rmgr_uninit(); +} +#endif + diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_stream2mmio_rmgr.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_stream2mmio_rmgr.c new file mode 100644 index 000000000..fb0cb183f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_stream2mmio_rmgr.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" + +#ifdef ISP2401 + +#include "assert_support.h" +#include "platform_support.h" +#include "ia_css_isys.h" +#include "bitop_support.h" +#include "isys_stream2mmio_rmgr.h" + +static isys_stream2mmio_rsrc_t isys_stream2mmio_rsrc[N_STREAM2MMIO_ID]; + +void ia_css_isys_stream2mmio_sid_rmgr_init(void) +{ + memset(isys_stream2mmio_rsrc, 0, sizeof(isys_stream2mmio_rsrc)); +} + +void ia_css_isys_stream2mmio_sid_rmgr_uninit(void) +{ + memset(isys_stream2mmio_rsrc, 0, sizeof(isys_stream2mmio_rsrc)); +} + +bool ia_css_isys_stream2mmio_sid_rmgr_acquire( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid) +{ + bool retval = false; + stream2mmio_sid_ID_t max_sid; + isys_stream2mmio_rsrc_t *cur_rsrc = NULL; + stream2mmio_sid_ID_t i; + + assert(stream2mmio < N_STREAM2MMIO_ID); + assert(sid); + + if ((stream2mmio < N_STREAM2MMIO_ID) && (sid)) { + max_sid = N_STREAM2MMIO_SID_PROCS[stream2mmio]; + cur_rsrc = &isys_stream2mmio_rsrc[stream2mmio]; + + if (cur_rsrc->num_active < max_sid) { + for (i = STREAM2MMIO_SID0_ID; i < max_sid; i++) { + if (bitop_getbit(cur_rsrc->active_table, i) == 0) { + bitop_setbit(cur_rsrc->active_table, i); + *sid = i; + cur_rsrc->num_active++; + retval = true; + break; + } + } + } + } + return retval; +} + +void ia_css_isys_stream2mmio_sid_rmgr_release( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid) +{ + stream2mmio_sid_ID_t max_sid; + isys_stream2mmio_rsrc_t *cur_rsrc = NULL; + + assert(stream2mmio < N_STREAM2MMIO_ID); + assert(sid); + + if ((stream2mmio < N_STREAM2MMIO_ID) && (sid)) { + max_sid = N_STREAM2MMIO_SID_PROCS[stream2mmio]; + cur_rsrc = &isys_stream2mmio_rsrc[stream2mmio]; + if ((*sid < max_sid) && (cur_rsrc->num_active > 0)) { + if (bitop_getbit(cur_rsrc->active_table, *sid) == 1) { + bitop_clearbit(cur_rsrc->active_table, *sid); + cur_rsrc->num_active--; + } + } + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_stream2mmio_rmgr.h b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_stream2mmio_rmgr.h new file mode 100644 index 000000000..78a4c867f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/isys_stream2mmio_rmgr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_RMGR_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_RMGR_H_INCLUDED__ + +typedef struct isys_stream2mmio_rsrc_s isys_stream2mmio_rsrc_t; +struct isys_stream2mmio_rsrc_s { + u32 active_table; + u16 num_active; +}; + +#endif /* __ISYS_STREAM2MMIO_RMGR_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c new file mode 100644 index 000000000..af153c3fb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define __INLINE_INPUT_SYSTEM__ +#include "input_system.h" +#include "assert_support.h" +#include "ia_css_isys.h" +#include "ia_css_irq.h" +#include "sh_css_internal.h" + +#if !defined(ISP2401) +void ia_css_isys_rx_enable_all_interrupts(enum mipi_port_id port) +{ + hrt_data bits = receiver_port_reg_load(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX); + + bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT) | + /*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT) | */ + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT); + /*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT); */ + + receiver_port_reg_store(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits); + + /* + * The CSI is nested into the Iunit IRQ's + */ + ia_css_irq_enable(IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR, true); + + return; +} + +/* This function converts between the enum used on the CSS API and the + * internal DLI enum type. + * We do not use an array for this since we cannot use named array + * initializers in Windows. Without that there is no easy way to guarantee + * that the array values would be in the correct order. + * */ +enum mipi_port_id ia_css_isys_port_to_mipi_port(enum mipi_port_id api_port) +{ + /* In this module the validity of the inptu variable should + * have been checked already, so we do not check for erroneous + * values. */ + enum mipi_port_id port = MIPI_PORT0_ID; + + if (api_port == MIPI_PORT1_ID) + port = MIPI_PORT1_ID; + else if (api_port == MIPI_PORT2_ID) + port = MIPI_PORT2_ID; + + return port; +} + +unsigned int ia_css_isys_rx_get_interrupt_reg(enum mipi_port_id port) +{ + return receiver_port_reg_load(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX); +} + +void ia_css_rx_get_irq_info(unsigned int *irq_infos) +{ + ia_css_rx_port_get_irq_info(MIPI_PORT1_ID, irq_infos); +} + +void ia_css_rx_port_get_irq_info(enum mipi_port_id api_port, + unsigned int *irq_infos) +{ + enum mipi_port_id port = ia_css_isys_port_to_mipi_port(api_port); + + ia_css_isys_rx_get_irq_info(port, irq_infos); +} + +void ia_css_isys_rx_get_irq_info(enum mipi_port_id port, + unsigned int *irq_infos) +{ + unsigned int bits; + + assert(irq_infos); + bits = ia_css_isys_rx_get_interrupt_reg(port); + *irq_infos = ia_css_isys_rx_translate_irq_infos(bits); +} + +/* Translate register bits to CSS API enum mask */ +unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits) +{ + unsigned int infos = 0; + + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ECC_CORRECTED; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_CONTROL; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_CRC; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC; + + return infos; +} + +void ia_css_rx_clear_irq_info(unsigned int irq_infos) +{ + ia_css_rx_port_clear_irq_info(MIPI_PORT1_ID, irq_infos); +} + +void ia_css_rx_port_clear_irq_info(enum mipi_port_id api_port, + unsigned int irq_infos) +{ + enum mipi_port_id port = ia_css_isys_port_to_mipi_port(api_port); + + ia_css_isys_rx_clear_irq_info(port, irq_infos); +} + +void ia_css_isys_rx_clear_irq_info(enum mipi_port_id port, + unsigned int irq_infos) +{ + hrt_data bits = receiver_port_reg_load(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX); + + /* MW: Why do we remap the receiver bitmap */ + if (irq_infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ECC_CORRECTED) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CRC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT; + + receiver_port_reg_store(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits); + + return; +} +#endif /* #if !defined(ISP2401) */ + +int ia_css_isys_convert_stream_format_to_mipi_format( + enum atomisp_input_format input_format, + mipi_predictor_t compression, + unsigned int *fmt_type) +{ + assert(fmt_type); + /* + * Custom (user defined) modes. Used for compressed + * MIPI transfers + * + * Checkpatch thinks the indent before "if" is suspect + * I think the only suspect part is the missing "else" + * because of the return. + */ + if (compression != MIPI_PREDICTOR_NONE) { + switch (input_format) { + case ATOMISP_INPUT_FORMAT_RAW_6: + *fmt_type = 6; + break; + case ATOMISP_INPUT_FORMAT_RAW_7: + *fmt_type = 7; + break; + case ATOMISP_INPUT_FORMAT_RAW_8: + *fmt_type = 8; + break; + case ATOMISP_INPUT_FORMAT_RAW_10: + *fmt_type = 10; + break; + case ATOMISP_INPUT_FORMAT_RAW_12: + *fmt_type = 12; + break; + case ATOMISP_INPUT_FORMAT_RAW_14: + *fmt_type = 14; + break; + case ATOMISP_INPUT_FORMAT_RAW_16: + *fmt_type = 16; + break; + default: + return -EINVAL; + } + return 0; + } + /* + * This mapping comes from the Arasan CSS function spec + * (CSS_func_spec1.08_ahb_sep29_08.pdf). + * + * MW: For some reason the mapping is not 1-to-1 + */ + switch (input_format) { + case ATOMISP_INPUT_FORMAT_RGB_888: + *fmt_type = MIPI_FORMAT_RGB888; + break; + case ATOMISP_INPUT_FORMAT_RGB_555: + *fmt_type = MIPI_FORMAT_RGB555; + break; + case ATOMISP_INPUT_FORMAT_RGB_444: + *fmt_type = MIPI_FORMAT_RGB444; + break; + case ATOMISP_INPUT_FORMAT_RGB_565: + *fmt_type = MIPI_FORMAT_RGB565; + break; + case ATOMISP_INPUT_FORMAT_RGB_666: + *fmt_type = MIPI_FORMAT_RGB666; + break; + case ATOMISP_INPUT_FORMAT_RAW_8: + *fmt_type = MIPI_FORMAT_RAW8; + break; + case ATOMISP_INPUT_FORMAT_RAW_10: + *fmt_type = MIPI_FORMAT_RAW10; + break; + case ATOMISP_INPUT_FORMAT_RAW_6: + *fmt_type = MIPI_FORMAT_RAW6; + break; + case ATOMISP_INPUT_FORMAT_RAW_7: + *fmt_type = MIPI_FORMAT_RAW7; + break; + case ATOMISP_INPUT_FORMAT_RAW_12: + *fmt_type = MIPI_FORMAT_RAW12; + break; + case ATOMISP_INPUT_FORMAT_RAW_14: + *fmt_type = MIPI_FORMAT_RAW14; + break; + case ATOMISP_INPUT_FORMAT_YUV420_8: + *fmt_type = MIPI_FORMAT_YUV420_8; + break; + case ATOMISP_INPUT_FORMAT_YUV420_10: + *fmt_type = MIPI_FORMAT_YUV420_10; + break; + case ATOMISP_INPUT_FORMAT_YUV422_8: + *fmt_type = MIPI_FORMAT_YUV422_8; + break; + case ATOMISP_INPUT_FORMAT_YUV422_10: + *fmt_type = MIPI_FORMAT_YUV422_10; + break; + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: + *fmt_type = MIPI_FORMAT_YUV420_8_LEGACY; + break; + case ATOMISP_INPUT_FORMAT_EMBEDDED: + *fmt_type = MIPI_FORMAT_EMBEDDED; + break; +#ifndef ISP2401 + case ATOMISP_INPUT_FORMAT_RAW_16: + /* This is not specified by Arasan, so we use + * 17 for now. + */ + *fmt_type = MIPI_FORMAT_RAW16; + break; + case ATOMISP_INPUT_FORMAT_BINARY_8: + *fmt_type = MIPI_FORMAT_BINARY_8; + break; +#else + case ATOMISP_INPUT_FORMAT_USER_DEF1: + *fmt_type = MIPI_FORMAT_CUSTOM0; + break; + case ATOMISP_INPUT_FORMAT_USER_DEF2: + *fmt_type = MIPI_FORMAT_CUSTOM1; + break; + case ATOMISP_INPUT_FORMAT_USER_DEF3: + *fmt_type = MIPI_FORMAT_CUSTOM2; + break; + case ATOMISP_INPUT_FORMAT_USER_DEF4: + *fmt_type = MIPI_FORMAT_CUSTOM3; + break; + case ATOMISP_INPUT_FORMAT_USER_DEF5: + *fmt_type = MIPI_FORMAT_CUSTOM4; + break; + case ATOMISP_INPUT_FORMAT_USER_DEF6: + *fmt_type = MIPI_FORMAT_CUSTOM5; + break; + case ATOMISP_INPUT_FORMAT_USER_DEF7: + *fmt_type = MIPI_FORMAT_CUSTOM6; + break; + case ATOMISP_INPUT_FORMAT_USER_DEF8: + *fmt_type = MIPI_FORMAT_CUSTOM7; + break; +#endif + + case ATOMISP_INPUT_FORMAT_YUV420_16: + case ATOMISP_INPUT_FORMAT_YUV422_16: + default: + return -EINVAL; + } + return 0; +} + +#if defined(ISP2401) +static mipi_predictor_t sh_css_csi2_compression_type_2_mipi_predictor( + enum ia_css_csi2_compression_type type) +{ + mipi_predictor_t predictor = MIPI_PREDICTOR_NONE; + + switch (type) { + case IA_CSS_CSI2_COMPRESSION_TYPE_1: + predictor = MIPI_PREDICTOR_TYPE1 - 1; + break; + case IA_CSS_CSI2_COMPRESSION_TYPE_2: + predictor = MIPI_PREDICTOR_TYPE2 - 1; + break; + default: + break; + } + return predictor; +} + +int ia_css_isys_convert_compressed_format( + struct ia_css_csi2_compression *comp, + struct isp2401_input_system_cfg_s *cfg) +{ + int err = 0; + + assert(comp); + assert(cfg); + + if (comp->type != IA_CSS_CSI2_COMPRESSION_TYPE_NONE) { + /* compression register bit slicing + 4 bit for each user defined data type + 3 bit indicate compression scheme + 000 No compression + 001 10-6-10 + 010 10-7-10 + 011 10-8-10 + 100 12-6-12 + 101 12-6-12 + 100 12-7-12 + 110 12-8-12 + 1 bit indicate predictor + */ + if (comp->uncompressed_bits_per_pixel == UNCOMPRESSED_BITS_PER_PIXEL_10) { + switch (comp->compressed_bits_per_pixel) { + case COMPRESSED_BITS_PER_PIXEL_6: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_6_10; + break; + case COMPRESSED_BITS_PER_PIXEL_7: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_7_10; + break; + case COMPRESSED_BITS_PER_PIXEL_8: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_8_10; + break; + default: + err = -EINVAL; + } + } else if (comp->uncompressed_bits_per_pixel == + UNCOMPRESSED_BITS_PER_PIXEL_12) { + switch (comp->compressed_bits_per_pixel) { + case COMPRESSED_BITS_PER_PIXEL_6: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_6_12; + break; + case COMPRESSED_BITS_PER_PIXEL_7: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_7_12; + break; + case COMPRESSED_BITS_PER_PIXEL_8: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_8_12; + break; + default: + err = -EINVAL; + } + } else + err = -EINVAL; + cfg->csi_port_attr.comp_predictor = + sh_css_csi2_compression_type_2_mipi_predictor(comp->type); + cfg->csi_port_attr.comp_enable = true; + } else /* No compression */ + cfg->csi_port_attr.comp_enable = false; + return err; +} + +unsigned int ia_css_csi2_calculate_input_system_alignment( + enum atomisp_input_format fmt_type) +{ + unsigned int memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES; + + switch (fmt_type) { + case ATOMISP_INPUT_FORMAT_RAW_6: + case ATOMISP_INPUT_FORMAT_RAW_7: + case ATOMISP_INPUT_FORMAT_RAW_8: + case ATOMISP_INPUT_FORMAT_RAW_10: + case ATOMISP_INPUT_FORMAT_RAW_12: + case ATOMISP_INPUT_FORMAT_RAW_14: + memory_alignment_in_bytes = 2 * ISP_VEC_NELEMS; + break; + case ATOMISP_INPUT_FORMAT_YUV420_8: + case ATOMISP_INPUT_FORMAT_YUV422_8: + case ATOMISP_INPUT_FORMAT_USER_DEF1: + case ATOMISP_INPUT_FORMAT_USER_DEF2: + case ATOMISP_INPUT_FORMAT_USER_DEF3: + case ATOMISP_INPUT_FORMAT_USER_DEF4: + case ATOMISP_INPUT_FORMAT_USER_DEF5: + case ATOMISP_INPUT_FORMAT_USER_DEF6: + case ATOMISP_INPUT_FORMAT_USER_DEF7: + case ATOMISP_INPUT_FORMAT_USER_DEF8: + /* Planar YUV formats need to have all planes aligned, this means + * double the alignment for the Y plane if the horizontal decimation is 2. */ + memory_alignment_in_bytes = 2 * HIVE_ISP_DDR_WORD_BYTES; + break; + case ATOMISP_INPUT_FORMAT_EMBEDDED: + default: + memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES; + break; + } + return memory_alignment_in_bytes; +} + +#endif + +#if !defined(ISP2401) +static const mipi_lane_cfg_t MIPI_PORT_LANES[N_RX_MODE][N_MIPI_PORT_ID] = { + {MIPI_4LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_2LANE_CFG}, + {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, + {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG} +}; + +void ia_css_isys_rx_configure(const rx_cfg_t *config, + const enum ia_css_input_mode input_mode) +{ + bool any_port_enabled = false; + enum mipi_port_id port; + + if ((!config) + || (config->mode >= N_RX_MODE) + || (config->port >= N_MIPI_PORT_ID)) { + assert(0); + return; + } + for (port = (enum mipi_port_id)0; port < N_MIPI_PORT_ID; port++) { + if (is_receiver_port_enabled(RX0_ID, port)) + any_port_enabled = true; + } + /* AM: Check whether this is a problem with multiple + * streams. MS: This is the case. */ + + port = config->port; + receiver_port_enable(RX0_ID, port, false); + + port = config->port; + + /* AM: Check whether this is a problem with multiple streams. */ + if (MIPI_PORT_LANES[config->mode][port] != MIPI_0LANE_CFG) { + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX, + config->timeout); + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX, + config->initcount); + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX, + config->synccount); + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX, + config->rxcount); + + if (input_mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + /* MW: A bit of a hack, straight wiring of the capture + * units,assuming they are linearly enumerated. */ + input_system_sub_system_reg_store(INPUT_SYSTEM0_ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX + + (unsigned int)port, + INPUT_SYSTEM_CSI_BACKEND); + /* MW: Like the integration test example we overwite, + * the GPREG_MUX register */ + input_system_sub_system_reg_store(INPUT_SYSTEM0_ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX, + (input_system_multiplex_t)port); + } else { + /* + * AM: A bit of a hack, wiring the input system. + */ + input_system_sub_system_reg_store(INPUT_SYSTEM0_ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX + + (unsigned int)port, + INPUT_SYSTEM_INPUT_BUFFER); + input_system_sub_system_reg_store(INPUT_SYSTEM0_ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX, + INPUT_SYSTEM_ACQUISITION_UNIT); + } + } + /* + * The 2ppc is shared for all ports, so we cannot + * disable->configure->enable individual ports + */ + /* AM: Check whether this is a problem with multiple streams. */ + /* MS: 2ppc should be a property per binary and should be + * enabled/disabled per binary. + * Currently it is implemented as a system wide setting due + * to effort and risks. */ + if (!any_port_enabled) { + receiver_reg_store(RX0_ID, + _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX, + config->is_two_ppc); + receiver_reg_store(RX0_ID, _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX, + config->is_two_ppc); + } + receiver_port_enable(RX0_ID, port, true); + /* TODO: JB: need to add the beneath used define to mizuchi */ + /* sh_css_sw_hive_isp_css_2400_system_20121224_0125\css + * \hrt\input_system_defs.h + * #define INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG 0X207 + */ + /* TODO: need better name for define + * input_system_reg_store(INPUT_SYSTEM0_ID, + * INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG, 1); + */ + input_system_reg_store(INPUT_SYSTEM0_ID, 0x207, 1); + + return; +} + +void ia_css_isys_rx_disable(void) +{ + enum mipi_port_id port; + + for (port = (enum mipi_port_id)0; port < N_MIPI_PORT_ID; port++) { + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, + false); + } + return; +} +#endif /* if !defined(ISP2401) */ diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/virtual_isys.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/virtual_isys.c new file mode 100644 index 000000000..8fc7746f8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/virtual_isys.c @@ -0,0 +1,869 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for memcpy() */ + +#include "system_global.h" + +#ifdef ISP2401 + +#include "ia_css_isys.h" +#include "ia_css_debug.h" +#include "math_support.h" +#include "virtual_isys.h" +#include "isp.h" +#include "sh_css_defs.h" + +/************************************************* + * + * Forwarded Declaration + * + *************************************************/ + +static bool create_input_system_channel( + isp2401_input_system_cfg_t *cfg, + bool metadata, + input_system_channel_t *channel); + +static void destroy_input_system_channel( + input_system_channel_t *channel); + +static bool create_input_system_input_port( + isp2401_input_system_cfg_t *cfg, + input_system_input_port_t *input_port); + +static void destroy_input_system_input_port( + input_system_input_port_t *input_port); + +static bool calculate_input_system_channel_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + isp2401_input_system_cfg_t *isys_cfg, + input_system_channel_cfg_t *channel_cfg, + bool metadata); + +static bool calculate_input_system_input_port_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + isp2401_input_system_cfg_t *isys_cfg, + input_system_input_port_cfg_t *input_port_cfg); + +static bool acquire_sid( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid); + +static void release_sid( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid); + +static bool acquire_ib_buffer( + s32 bits_per_pixel, + s32 pixels_per_line, + s32 lines_per_frame, + s32 align_in_bytes, + bool online, + isp2401_ib_buffer_t *buf); + +static void release_ib_buffer( + isp2401_ib_buffer_t *buf); + +static bool acquire_dma_channel( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel); + +static void release_dma_channel( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel); + +static bool acquire_be_lut_entry( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry); + +static void release_be_lut_entry( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry); + +static bool calculate_tpg_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + isp2401_input_system_cfg_t *isys_cfg, + pixelgen_tpg_cfg_t *cfg); + +static bool calculate_prbs_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + isp2401_input_system_cfg_t *isys_cfg, + pixelgen_prbs_cfg_t *cfg); + +static bool calculate_fe_cfg( + const isp2401_input_system_cfg_t *isys_cfg, + csi_rx_frontend_cfg_t *cfg); + +static bool calculate_be_cfg( + const input_system_input_port_t *input_port, + const isp2401_input_system_cfg_t *isys_cfg, + bool metadata, + csi_rx_backend_cfg_t *cfg); + +static bool calculate_stream2mmio_cfg( + const isp2401_input_system_cfg_t *isys_cfg, + bool metadata, + stream2mmio_cfg_t *cfg); + +static bool calculate_ibuf_ctrl_cfg( + const input_system_channel_t *channel, + const input_system_input_port_t *input_port, + const isp2401_input_system_cfg_t *isys_cfg, + ibuf_ctrl_cfg_t *cfg); + +static bool calculate_isys2401_dma_cfg( + const input_system_channel_t *channel, + const isp2401_input_system_cfg_t *isys_cfg, + isys2401_dma_cfg_t *cfg); + +static bool calculate_isys2401_dma_port_cfg( + const isp2401_input_system_cfg_t *isys_cfg, + bool raw_packed, + bool metadata, + isys2401_dma_port_cfg_t *cfg); + +static csi_mipi_packet_type_t get_csi_mipi_packet_type( + int32_t data_type); + +static int32_t calculate_stride( + s32 bits_per_pixel, + s32 pixels_per_line, + bool raw_packed, + int32_t align_in_bytes); + +/* end of Forwarded Declaration */ + +/************************************************** + * + * Public Methods + * + **************************************************/ +ia_css_isys_error_t ia_css_isys_stream_create( + ia_css_isys_descr_t *isys_stream_descr, + ia_css_isys_stream_h isys_stream, + uint32_t isys_stream_id) +{ + ia_css_isys_error_t rc; + + if (!isys_stream_descr || !isys_stream || + isys_stream_id >= SH_CSS_MAX_ISYS_CHANNEL_NODES) + return false; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_isys_stream_create() enter:\n"); + + /*Reset isys_stream to 0*/ + memset(isys_stream, 0, sizeof(*isys_stream)); + isys_stream->enable_metadata = isys_stream_descr->metadata.enable; + isys_stream->id = isys_stream_id; + + isys_stream->linked_isys_stream_id = isys_stream_descr->linked_isys_stream_id; + rc = create_input_system_input_port(isys_stream_descr, + &isys_stream->input_port); + if (!rc) + return false; + + rc = create_input_system_channel(isys_stream_descr, false, + &isys_stream->channel); + if (!rc) { + destroy_input_system_input_port(&isys_stream->input_port); + return false; + } + + /* create metadata channel */ + if (isys_stream_descr->metadata.enable) { + rc = create_input_system_channel(isys_stream_descr, true, + &isys_stream->md_channel); + if (!rc) { + destroy_input_system_input_port(&isys_stream->input_port); + destroy_input_system_channel(&isys_stream->channel); + return false; + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_isys_stream_create() leave:\n"); + + return true; +} + +void ia_css_isys_stream_destroy( + ia_css_isys_stream_h isys_stream) +{ + destroy_input_system_input_port(&isys_stream->input_port); + destroy_input_system_channel(&isys_stream->channel); + if (isys_stream->enable_metadata) { + /* Destroy metadata channel only if its allocated*/ + destroy_input_system_channel(&isys_stream->md_channel); + } +} + +ia_css_isys_error_t ia_css_isys_stream_calculate_cfg( + ia_css_isys_stream_h isys_stream, + ia_css_isys_descr_t *isys_stream_descr, + ia_css_isys_stream_cfg_t *isys_stream_cfg) +{ + ia_css_isys_error_t rc; + + if (!isys_stream_cfg || + !isys_stream_descr || + !isys_stream) + return false; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_isys_stream_calculate_cfg() enter:\n"); + + rc = calculate_input_system_channel_cfg( + &isys_stream->channel, + &isys_stream->input_port, + isys_stream_descr, + &isys_stream_cfg->channel_cfg, + false); + if (!rc) + return false; + + /* configure metadata channel */ + if (isys_stream_descr->metadata.enable) { + isys_stream_cfg->enable_metadata = true; + rc = calculate_input_system_channel_cfg( + &isys_stream->md_channel, + &isys_stream->input_port, + isys_stream_descr, + &isys_stream_cfg->md_channel_cfg, + true); + if (!rc) + return false; + } + + rc = calculate_input_system_input_port_cfg( + &isys_stream->channel, + &isys_stream->input_port, + isys_stream_descr, + &isys_stream_cfg->input_port_cfg); + if (!rc) + return false; + + isys_stream->valid = 1; + isys_stream_cfg->valid = 1; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_isys_stream_calculate_cfg() leave:\n"); + return rc; +} + +/* end of Public Methods */ + +/************************************************** + * + * Private Methods + * + **************************************************/ +static bool create_input_system_channel( + isp2401_input_system_cfg_t *cfg, + bool metadata, + input_system_channel_t *me) +{ + bool rc = true; + + me->dma_id = ISYS2401_DMA0_ID; + + switch (cfg->input_port_id) { + case INPUT_SYSTEM_CSI_PORT0_ID: + case INPUT_SYSTEM_PIXELGEN_PORT0_ID: + me->stream2mmio_id = STREAM2MMIO0_ID; + me->ibuf_ctrl_id = IBUF_CTRL0_ID; + break; + + case INPUT_SYSTEM_CSI_PORT1_ID: + case INPUT_SYSTEM_PIXELGEN_PORT1_ID: + me->stream2mmio_id = STREAM2MMIO1_ID; + me->ibuf_ctrl_id = IBUF_CTRL1_ID; + break; + + case INPUT_SYSTEM_CSI_PORT2_ID: + case INPUT_SYSTEM_PIXELGEN_PORT2_ID: + me->stream2mmio_id = STREAM2MMIO2_ID; + me->ibuf_ctrl_id = IBUF_CTRL2_ID; + break; + default: + rc = false; + break; + } + + if (!rc) + return false; + + if (!acquire_sid(me->stream2mmio_id, &me->stream2mmio_sid_id)) { + return false; + } + + if (!acquire_ib_buffer( + metadata ? cfg->metadata.bits_per_pixel : + cfg->input_port_resolution.bits_per_pixel, + metadata ? cfg->metadata.pixels_per_line : + cfg->input_port_resolution.pixels_per_line, + metadata ? cfg->metadata.lines_per_frame : + cfg->input_port_resolution.lines_per_frame, + metadata ? cfg->metadata.align_req_in_bytes : + cfg->input_port_resolution.align_req_in_bytes, + cfg->online, + &me->ib_buffer)) { + release_sid(me->stream2mmio_id, &me->stream2mmio_sid_id); + return false; + } + + if (!acquire_dma_channel(me->dma_id, &me->dma_channel)) { + release_sid(me->stream2mmio_id, &me->stream2mmio_sid_id); + release_ib_buffer(&me->ib_buffer); + return false; + } + + return true; +} + +static void destroy_input_system_channel( + input_system_channel_t *me) +{ + release_sid(me->stream2mmio_id, + &me->stream2mmio_sid_id); + + release_ib_buffer(&me->ib_buffer); + + release_dma_channel(me->dma_id, &me->dma_channel); +} + +static bool create_input_system_input_port( + isp2401_input_system_cfg_t *cfg, + input_system_input_port_t *me) +{ + csi_mipi_packet_type_t packet_type; + bool rc = true; + + switch (cfg->input_port_id) { + case INPUT_SYSTEM_CSI_PORT0_ID: + me->csi_rx.frontend_id = CSI_RX_FRONTEND0_ID; + me->csi_rx.backend_id = CSI_RX_BACKEND0_ID; + + packet_type = get_csi_mipi_packet_type(cfg->csi_port_attr.fmt_type); + me->csi_rx.packet_type = packet_type; + + rc = acquire_be_lut_entry( + me->csi_rx.backend_id, + packet_type, + &me->csi_rx.backend_lut_entry); + break; + case INPUT_SYSTEM_PIXELGEN_PORT0_ID: + me->pixelgen.pixelgen_id = PIXELGEN0_ID; + break; + case INPUT_SYSTEM_CSI_PORT1_ID: + me->csi_rx.frontend_id = CSI_RX_FRONTEND1_ID; + me->csi_rx.backend_id = CSI_RX_BACKEND1_ID; + + packet_type = get_csi_mipi_packet_type(cfg->csi_port_attr.fmt_type); + me->csi_rx.packet_type = packet_type; + + rc = acquire_be_lut_entry( + me->csi_rx.backend_id, + packet_type, + &me->csi_rx.backend_lut_entry); + break; + case INPUT_SYSTEM_PIXELGEN_PORT1_ID: + me->pixelgen.pixelgen_id = PIXELGEN1_ID; + + break; + case INPUT_SYSTEM_CSI_PORT2_ID: + me->csi_rx.frontend_id = CSI_RX_FRONTEND2_ID; + me->csi_rx.backend_id = CSI_RX_BACKEND2_ID; + + packet_type = get_csi_mipi_packet_type(cfg->csi_port_attr.fmt_type); + me->csi_rx.packet_type = packet_type; + + rc = acquire_be_lut_entry( + me->csi_rx.backend_id, + packet_type, + &me->csi_rx.backend_lut_entry); + break; + case INPUT_SYSTEM_PIXELGEN_PORT2_ID: + me->pixelgen.pixelgen_id = PIXELGEN2_ID; + break; + default: + rc = false; + break; + } + + me->source_type = cfg->mode; + + /* for metadata */ + me->metadata.packet_type = CSI_MIPI_PACKET_TYPE_UNDEFINED; + if (rc && cfg->metadata.enable) { + me->metadata.packet_type = get_csi_mipi_packet_type( + cfg->metadata.fmt_type); + rc = acquire_be_lut_entry( + me->csi_rx.backend_id, + me->metadata.packet_type, + &me->metadata.backend_lut_entry); + } + + return rc; +} + +static void destroy_input_system_input_port( + input_system_input_port_t *me) +{ + if (me->source_type == INPUT_SYSTEM_SOURCE_TYPE_SENSOR) { + release_be_lut_entry( + me->csi_rx.backend_id, + me->csi_rx.packet_type, + &me->csi_rx.backend_lut_entry); + } + + if (me->metadata.packet_type != CSI_MIPI_PACKET_TYPE_UNDEFINED) { + /*Free the backend lut allocated for metadata*/ + release_be_lut_entry( + me->csi_rx.backend_id, + me->metadata.packet_type, + &me->metadata.backend_lut_entry); + } +} + +static bool calculate_input_system_channel_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + isp2401_input_system_cfg_t *isys_cfg, + input_system_channel_cfg_t *channel_cfg, + bool metadata) +{ + bool rc; + + rc = calculate_stream2mmio_cfg(isys_cfg, metadata, + &channel_cfg->stream2mmio_cfg); + if (!rc) + return false; + + rc = calculate_ibuf_ctrl_cfg( + channel, + input_port, + isys_cfg, + &channel_cfg->ibuf_ctrl_cfg); + if (!rc) + return false; + if (metadata) + channel_cfg->ibuf_ctrl_cfg.stores_per_frame = + isys_cfg->metadata.lines_per_frame; + + rc = calculate_isys2401_dma_cfg( + channel, + isys_cfg, + &channel_cfg->dma_cfg); + if (!rc) + return false; + + rc = calculate_isys2401_dma_port_cfg( + isys_cfg, + false, + metadata, + &channel_cfg->dma_src_port_cfg); + if (!rc) + return false; + + rc = calculate_isys2401_dma_port_cfg( + isys_cfg, + isys_cfg->raw_packed, + metadata, + &channel_cfg->dma_dest_port_cfg); + if (!rc) + return false; + + return true; +} + +static bool calculate_input_system_input_port_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + isp2401_input_system_cfg_t *isys_cfg, + input_system_input_port_cfg_t *input_port_cfg) +{ + bool rc; + + switch (input_port->source_type) { + case INPUT_SYSTEM_SOURCE_TYPE_SENSOR: + rc = calculate_fe_cfg( + isys_cfg, + &input_port_cfg->csi_rx_cfg.frontend_cfg); + + rc &= calculate_be_cfg( + input_port, + isys_cfg, + false, + &input_port_cfg->csi_rx_cfg.backend_cfg); + + if (rc && isys_cfg->metadata.enable) + rc &= calculate_be_cfg(input_port, isys_cfg, true, + &input_port_cfg->csi_rx_cfg.md_backend_cfg); + break; + case INPUT_SYSTEM_SOURCE_TYPE_TPG: + rc = calculate_tpg_cfg( + channel, + input_port, + isys_cfg, + &input_port_cfg->pixelgen_cfg.tpg_cfg); + break; + case INPUT_SYSTEM_SOURCE_TYPE_PRBS: + rc = calculate_prbs_cfg( + channel, + input_port, + isys_cfg, + &input_port_cfg->pixelgen_cfg.prbs_cfg); + break; + default: + rc = false; + break; + } + + return rc; +} + +static bool acquire_sid( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid) +{ + return ia_css_isys_stream2mmio_sid_rmgr_acquire(stream2mmio, sid); +} + +static void release_sid( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid) +{ + ia_css_isys_stream2mmio_sid_rmgr_release(stream2mmio, sid); +} + +/* See also: ia_css_dma_configure_from_info() */ +static int32_t calculate_stride( + s32 bits_per_pixel, + s32 pixels_per_line, + bool raw_packed, + int32_t align_in_bytes) +{ + s32 bytes_per_line; + s32 pixels_per_word; + s32 words_per_line; + s32 pixels_per_line_padded; + + pixels_per_line_padded = CEIL_MUL(pixels_per_line, align_in_bytes); + + if (!raw_packed) + bits_per_pixel = CEIL_MUL(bits_per_pixel, 8); + + pixels_per_word = HIVE_ISP_DDR_WORD_BITS / bits_per_pixel; + words_per_line = ceil_div(pixels_per_line_padded, pixels_per_word); + bytes_per_line = HIVE_ISP_DDR_WORD_BYTES * words_per_line; + + return bytes_per_line; +} + +static bool acquire_ib_buffer( + s32 bits_per_pixel, + s32 pixels_per_line, + s32 lines_per_frame, + s32 align_in_bytes, + bool online, + isp2401_ib_buffer_t *buf) +{ + buf->stride = calculate_stride(bits_per_pixel, pixels_per_line, false, + align_in_bytes); + if (online) + buf->lines = 4; /* use double buffering for online usecases */ + else + buf->lines = 2; + + (void)(lines_per_frame); + return ia_css_isys_ibuf_rmgr_acquire(buf->stride * buf->lines, + &buf->start_addr); +} + +static void release_ib_buffer( + isp2401_ib_buffer_t *buf) +{ + ia_css_isys_ibuf_rmgr_release(&buf->start_addr); +} + +static bool acquire_dma_channel( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel) +{ + return ia_css_isys_dma_channel_rmgr_acquire(dma_id, channel); +} + +static void release_dma_channel( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel) +{ + ia_css_isys_dma_channel_rmgr_release(dma_id, channel); +} + +static bool acquire_be_lut_entry( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry) +{ + return ia_css_isys_csi_rx_lut_rmgr_acquire(backend, packet_type, entry); +} + +static void release_be_lut_entry( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry) +{ + ia_css_isys_csi_rx_lut_rmgr_release(backend, packet_type, entry); +} + +static bool calculate_tpg_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + isp2401_input_system_cfg_t *isys_cfg, + pixelgen_tpg_cfg_t *cfg) +{ + memcpy(cfg, &isys_cfg->tpg_port_attr, sizeof(pixelgen_tpg_cfg_t)); + + return true; +} + +static bool calculate_prbs_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + isp2401_input_system_cfg_t *isys_cfg, + pixelgen_prbs_cfg_t *cfg) +{ + memcpy(cfg, &isys_cfg->prbs_port_attr, sizeof(pixelgen_prbs_cfg_t)); + + return true; +} + +static bool calculate_fe_cfg( + const isp2401_input_system_cfg_t *isys_cfg, + csi_rx_frontend_cfg_t *cfg) +{ + cfg->active_lanes = isys_cfg->csi_port_attr.active_lanes; + return true; +} + +static bool calculate_be_cfg( + const input_system_input_port_t *input_port, + const isp2401_input_system_cfg_t *isys_cfg, + bool metadata, + csi_rx_backend_cfg_t *cfg) +{ + memcpy(&cfg->lut_entry, + metadata ? &input_port->metadata.backend_lut_entry : + &input_port->csi_rx.backend_lut_entry, + sizeof(csi_rx_backend_lut_entry_t)); + + cfg->csi_mipi_cfg.virtual_channel = isys_cfg->csi_port_attr.ch_id; + if (metadata) { + cfg->csi_mipi_packet_type = get_csi_mipi_packet_type( + isys_cfg->metadata.fmt_type); + cfg->csi_mipi_cfg.comp_enable = false; + cfg->csi_mipi_cfg.data_type = isys_cfg->metadata.fmt_type; + } else { + cfg->csi_mipi_packet_type = get_csi_mipi_packet_type( + isys_cfg->csi_port_attr.fmt_type); + cfg->csi_mipi_cfg.data_type = isys_cfg->csi_port_attr.fmt_type; + cfg->csi_mipi_cfg.comp_enable = isys_cfg->csi_port_attr.comp_enable; + cfg->csi_mipi_cfg.comp_scheme = isys_cfg->csi_port_attr.comp_scheme; + cfg->csi_mipi_cfg.comp_predictor = isys_cfg->csi_port_attr.comp_predictor; + cfg->csi_mipi_cfg.comp_bit_idx = cfg->csi_mipi_cfg.data_type - + MIPI_FORMAT_CUSTOM0; + } + + return true; +} + +static bool calculate_stream2mmio_cfg( + const isp2401_input_system_cfg_t *isys_cfg, + bool metadata, + stream2mmio_cfg_t *cfg +) +{ + cfg->bits_per_pixel = metadata ? isys_cfg->metadata.bits_per_pixel : + isys_cfg->input_port_resolution.bits_per_pixel; + + cfg->enable_blocking = + ((isys_cfg->mode == INPUT_SYSTEM_SOURCE_TYPE_TPG) || + (isys_cfg->mode == INPUT_SYSTEM_SOURCE_TYPE_PRBS)); + + return true; +} + +static bool calculate_ibuf_ctrl_cfg( + const input_system_channel_t *channel, + const input_system_input_port_t *input_port, + const isp2401_input_system_cfg_t *isys_cfg, + ibuf_ctrl_cfg_t *cfg) +{ + const s32 bits_per_byte = 8; + s32 bits_per_pixel; + s32 bytes_per_pixel; + s32 left_padding; + + (void)input_port; + + bits_per_pixel = isys_cfg->input_port_resolution.bits_per_pixel; + bytes_per_pixel = ceil_div(bits_per_pixel, bits_per_byte); + + left_padding = CEIL_MUL(isys_cfg->output_port_attr.left_padding, ISP_VEC_NELEMS) + * bytes_per_pixel; + + cfg->online = isys_cfg->online; + + cfg->dma_cfg.channel = channel->dma_channel; + cfg->dma_cfg.cmd = _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND; + + cfg->dma_cfg.shift_returned_items = 0; + cfg->dma_cfg.elems_per_word_in_ibuf = 0; + cfg->dma_cfg.elems_per_word_in_dest = 0; + + cfg->ib_buffer.start_addr = channel->ib_buffer.start_addr; + cfg->ib_buffer.stride = channel->ib_buffer.stride; + cfg->ib_buffer.lines = channel->ib_buffer.lines; + + /* + #ifndef ISP2401 + * zhengjie.lu@intel.com: + #endif + * "dest_buf_cfg" should be part of the input system output + * port configuration. + * + * TODO: move "dest_buf_cfg" to the input system output + * port configuration. + */ + + /* input_buf addr only available in sched mode; + this buffer is allocated in isp, crun mode addr + can be passed by after ISP allocation */ + if (cfg->online) { + cfg->dest_buf_cfg.start_addr = ISP_INPUT_BUF_START_ADDR + left_padding; + cfg->dest_buf_cfg.stride = bytes_per_pixel + * isys_cfg->output_port_attr.max_isp_input_width; + cfg->dest_buf_cfg.lines = LINES_OF_ISP_INPUT_BUF; + } else if (isys_cfg->raw_packed) { + cfg->dest_buf_cfg.stride = calculate_stride(bits_per_pixel, + isys_cfg->input_port_resolution.pixels_per_line, + isys_cfg->raw_packed, + isys_cfg->input_port_resolution.align_req_in_bytes); + } else { + cfg->dest_buf_cfg.stride = channel->ib_buffer.stride; + } + + /* + #ifndef ISP2401 + * zhengjie.lu@intel.com: + #endif + * "items_per_store" is hard coded as "1", which is ONLY valid + * when the CSI-MIPI long packet is transferred. + * + * TODO: After the 1st stage of MERR+, make the proper solution to + * configure "items_per_store" so that it can also handle the CSI-MIPI + * short packet. + */ + cfg->items_per_store = 1; + + cfg->stores_per_frame = isys_cfg->input_port_resolution.lines_per_frame; + + cfg->stream2mmio_cfg.sync_cmd = _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME; + + /* TODO: Define conditions as when to use store words vs store packets */ + cfg->stream2mmio_cfg.store_cmd = _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS; + + return true; +} + +static bool calculate_isys2401_dma_cfg( + const input_system_channel_t *channel, + const isp2401_input_system_cfg_t *isys_cfg, + isys2401_dma_cfg_t *cfg) +{ + cfg->channel = channel->dma_channel; + + /* only online/sensor mode goto vmem + offline/buffered_sensor, tpg and prbs will go to ddr */ + if (isys_cfg->online) + cfg->connection = isys2401_dma_ibuf_to_vmem_connection; + else + cfg->connection = isys2401_dma_ibuf_to_ddr_connection; + + cfg->extension = isys2401_dma_zero_extension; + cfg->height = 1; + + return true; +} + +/* See also: ia_css_dma_configure_from_info() */ +static bool calculate_isys2401_dma_port_cfg( + const isp2401_input_system_cfg_t *isys_cfg, + bool raw_packed, + bool metadata, + isys2401_dma_port_cfg_t *cfg) +{ + s32 bits_per_pixel; + s32 pixels_per_line; + s32 align_req_in_bytes; + + /* TODO: Move metadata away from isys_cfg to application layer */ + if (metadata) { + bits_per_pixel = isys_cfg->metadata.bits_per_pixel; + pixels_per_line = isys_cfg->metadata.pixels_per_line; + align_req_in_bytes = isys_cfg->metadata.align_req_in_bytes; + } else { + bits_per_pixel = isys_cfg->input_port_resolution.bits_per_pixel; + pixels_per_line = isys_cfg->input_port_resolution.pixels_per_line; + align_req_in_bytes = isys_cfg->input_port_resolution.align_req_in_bytes; + } + + cfg->stride = calculate_stride(bits_per_pixel, pixels_per_line, raw_packed, + align_req_in_bytes); + + if (!raw_packed) + bits_per_pixel = CEIL_MUL(bits_per_pixel, 8); + + cfg->elements = HIVE_ISP_DDR_WORD_BITS / bits_per_pixel; + cfg->cropping = 0; + cfg->width = CEIL_DIV(cfg->stride, HIVE_ISP_DDR_WORD_BYTES); + + return true; +} + +static csi_mipi_packet_type_t get_csi_mipi_packet_type( + int32_t data_type) +{ + csi_mipi_packet_type_t packet_type; + + packet_type = CSI_MIPI_PACKET_TYPE_RESERVED; + + if (data_type >= 0 && data_type <= MIPI_FORMAT_SHORT8) + packet_type = CSI_MIPI_PACKET_TYPE_SHORT; + + if (data_type > MIPI_FORMAT_SHORT8 && data_type <= N_MIPI_FORMAT) + packet_type = CSI_MIPI_PACKET_TYPE_LONG; + + return packet_type; +} + +/* end of Private Methods */ +#endif diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/virtual_isys.h b/drivers/staging/media/atomisp/pci/runtime/isys/src/virtual_isys.h new file mode 100644 index 000000000..fbdbca0cf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/virtual_isys.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VIRTUAL_ISYS_H_INCLUDED__ +#define __VIRTUAL_ISYS_H_INCLUDED__ + +/* cmd for storing a number of packets indicated by reg _STREAM2MMIO_NUM_ITEMS*/ +#define _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS 1 + +/* command for waiting for a frame start */ +#define _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME 2 + +#endif /* __VIRTUAL_ISYS_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/ia_css_pipeline.h b/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/ia_css_pipeline.h new file mode 100644 index 000000000..222c381ff --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/ia_css_pipeline.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPELINE_H__ +#define __IA_CSS_PIPELINE_H__ + +#include "sh_css_internal.h" +#include "ia_css_pipe_public.h" +#include "ia_css_pipeline_common.h" + +#define IA_CSS_PIPELINE_NUM_MAX (20) + +/* Pipeline stage to be executed on SP/ISP */ +struct ia_css_pipeline_stage { + unsigned int stage_num; + struct ia_css_binary *binary; /* built-in binary */ + struct ia_css_binary_info *binary_info; + const struct ia_css_fw_info *firmware; /* acceleration binary */ + /* SP function for SP stage */ + enum ia_css_pipeline_stage_sp_func sp_func; + unsigned int max_input_width; /* For SP raw copy */ + struct sh_css_binary_args args; + int mode; + bool out_frame_allocated[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + bool vf_frame_allocated; + struct ia_css_pipeline_stage *next; + bool enable_zoom; +}; + +/* Pipeline of n stages to be executed on SP/ISP per stage */ +struct ia_css_pipeline { + enum ia_css_pipe_id pipe_id; + u8 pipe_num; + bool stop_requested; + struct ia_css_pipeline_stage *stages; + struct ia_css_pipeline_stage *current_stage; + unsigned int num_stages; + struct ia_css_frame in_frame; + struct ia_css_frame out_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame vf_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + unsigned int dvs_frame_delay; + unsigned int inout_port_config; + int num_execs; + bool acquire_isp_each_stage; +}; + +#define DEFAULT_PIPELINE { \ + .pipe_id = IA_CSS_PIPE_ID_PREVIEW, \ + .in_frame = DEFAULT_FRAME, \ + .out_frame = {DEFAULT_FRAME}, \ + .vf_frame = {DEFAULT_FRAME}, \ + .dvs_frame_delay = IA_CSS_FRAME_DELAY_1, \ + .num_execs = -1, \ + .acquire_isp_each_stage = true, \ +} + +/* Stage descriptor used to create a new stage in the pipeline */ +struct ia_css_pipeline_stage_desc { + struct ia_css_binary *binary; + const struct ia_css_fw_info *firmware; + enum ia_css_pipeline_stage_sp_func sp_func; + unsigned int max_input_width; + unsigned int mode; + struct ia_css_frame *in_frame; + struct ia_css_frame *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame *vf_frame; +}; + +/* @brief initialize the pipeline module + * + * @return None + * + * Initializes the pipeline module. This API has to be called + * before any operation on the pipeline module is done + */ +void ia_css_pipeline_init(void); + +/* @brief initialize the pipeline structure with default values + * + * @param[out] pipeline structure to be initialized with defaults + * @param[in] pipe_id + * @param[in] pipe_num Number that uniquely identifies a pipeline. + * @return 0 or error code upon error. + * + * Initializes the pipeline structure with a set of default values. + * This API is expected to be used when a pipeline structure is allocated + * externally and needs sane defaults + */ +int ia_css_pipeline_create( + struct ia_css_pipeline *pipeline, + enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + unsigned int dvs_frame_delay); + +/* @brief destroy a pipeline + * + * @param[in] pipeline + * @return None + * + */ +void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline); + +/* @brief Starts a pipeline + * + * @param[in] pipe_id + * @param[in] pipeline + * @return None + * + */ +void ia_css_pipeline_start(enum ia_css_pipe_id pipe_id, + struct ia_css_pipeline *pipeline); + +/* @brief Request to stop a pipeline + * + * @param[in] pipeline + * @return 0 or error code upon error. + * + */ +int ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline); + +/* @brief Check whether pipeline has stopped + * + * @param[in] pipeline + * @return true if the pipeline has stopped + * + */ +bool ia_css_pipeline_has_stopped(struct ia_css_pipeline *pipe); + +/* @brief clean all the stages pipeline and make it as new + * + * @param[in] pipeline + * @return None + * + */ +void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline); + +/* @brief Add a stage to pipeline. + * + * @param pipeline Pointer to the pipeline to be added to. + * @param[in] stage_desc The description of the stage + * @param[out] stage The successor of the stage. + * @return 0 or error code upon error. + * + * Add a new stage to a non-NULL pipeline. + * The stage consists of an ISP binary or firmware and input and output + * arguments. +*/ +int ia_css_pipeline_create_and_add_stage( + struct ia_css_pipeline *pipeline, + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_pipeline_stage **stage); + +/* @brief Finalize the stages in a pipeline + * + * @param pipeline Pointer to the pipeline to be added to. + * @return None + * + * This API is expected to be called after adding all stages +*/ +void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline, + bool continuous); + +/* @brief gets a stage from the pipeline + * + * @param[in] pipeline + * @return 0 or error code upon error. + * + */ +int ia_css_pipeline_get_stage(struct ia_css_pipeline *pipeline, + int mode, + struct ia_css_pipeline_stage **stage); + +/* @brief Gets a pipeline stage corresponding Firmware handle from the pipeline + * + * @param[in] pipeline + * @param[in] fw_handle + * @param[out] stage Pointer to Stage + * + * @return 0 or error code upon error. + * + */ +int ia_css_pipeline_get_stage_from_fw(struct ia_css_pipeline + *pipeline, + u32 fw_handle, + struct ia_css_pipeline_stage **stage); + +/* @brief Gets the Firmware handle corresponding the stage num from the pipeline + * + * @param[in] pipeline + * @param[in] stage_num + * @param[out] fw_handle + * + * @return 0 or error code upon error. + * + */ +int ia_css_pipeline_get_fw_from_stage(struct ia_css_pipeline + *pipeline, + u32 stage_num, + uint32_t *fw_handle); + +/* @brief gets the output stage from the pipeline + * + * @param[in] pipeline + * @return 0 or error code upon error. + * + */ +int ia_css_pipeline_get_output_stage( + struct ia_css_pipeline *pipeline, + int mode, + struct ia_css_pipeline_stage **stage); + +/* @brief Checks whether the pipeline uses params + * + * @param[in] pipeline + * @return true if the pipeline uses params + * + */ +bool ia_css_pipeline_uses_params(struct ia_css_pipeline *pipeline); + +/** + * @brief get the SP thread ID. + * + * @param[in] key The query key, typical use is pipe_num. + * @param[out] val The query value. + * + * @return + * true, if the query succeeds; + * false, if the query fails. + */ +bool ia_css_pipeline_get_sp_thread_id(unsigned int key, unsigned int *val); + +#if defined(ISP2401) +/** + * @brief Get the pipeline io status + * + * @param[in] None + * @return + * Pointer to pipe_io_status + */ +struct sh_css_sp_pipeline_io_status *ia_css_pipeline_get_pipe_io_status(void); +#endif + +/** + * @brief Map an SP thread to this pipeline + * + * @param[in] pipe_num + * @param[in] map true for mapping and false for unmapping sp threads. + * + */ +void ia_css_pipeline_map(unsigned int pipe_num, bool map); + +/** + * @brief Checks whether the pipeline is mapped to SP threads + * + * @param[in] Query key, typical use is pipe_num + * + * return + * true, pipeline is mapped to SP threads + * false, pipeline is not mapped to SP threads + */ +bool ia_css_pipeline_is_mapped(unsigned int key); + +/** + * @brief Print pipeline thread mapping + * + * @param[in] none + * + * return none + */ +void ia_css_pipeline_dump_thread_map_info(void); + +#endif /*__IA_CSS_PIPELINE_H__*/ diff --git a/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/ia_css_pipeline_common.h b/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/ia_css_pipeline_common.h new file mode 100644 index 000000000..cc44f03c3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/ia_css_pipeline_common.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPELINE_COMMON_H__ +#define __IA_CSS_PIPELINE_COMMON_H__ + +enum ia_css_pipeline_stage_sp_func { + IA_CSS_PIPELINE_RAW_COPY = 0, + IA_CSS_PIPELINE_BIN_COPY = 1, + IA_CSS_PIPELINE_ISYS_COPY = 2, + IA_CSS_PIPELINE_NO_FUNC = 3, +}; + +#define IA_CSS_PIPELINE_NUM_STAGE_FUNCS 3 + +#endif /*__IA_CSS_PIPELINE_COMMON_H__*/ diff --git a/drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c b/drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c new file mode 100644 index 000000000..e9e187649 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c @@ -0,0 +1,783 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include "ia_css_debug.h" +#include "sw_event_global.h" /* encode_sw_event */ +#include "sp.h" /* cnd_sp_irq_enable() */ +#include "assert_support.h" +#include "sh_css_sp.h" +#include "ia_css_pipeline.h" +#include "ia_css_isp_param.h" +#include "ia_css_bufq.h" + +#define PIPELINE_NUM_UNMAPPED (~0U) +#define PIPELINE_SP_THREAD_EMPTY_TOKEN (0x0) +#define PIPELINE_SP_THREAD_RESERVED_TOKEN (0x1) + +/******************************************************* +*** Static variables +********************************************************/ +static unsigned int pipeline_num_to_sp_thread_map[IA_CSS_PIPELINE_NUM_MAX]; +static unsigned int pipeline_sp_thread_list[SH_CSS_MAX_SP_THREADS]; + +/******************************************************* +*** Static functions +********************************************************/ +static void pipeline_init_sp_thread_map(void); +static void pipeline_map_num_to_sp_thread(unsigned int pipe_num); +static void pipeline_unmap_num_to_sp_thread(unsigned int pipe_num); +static void pipeline_init_defaults( + struct ia_css_pipeline *pipeline, + enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + unsigned int dvs_frame_delay); + +static void pipeline_stage_destroy(struct ia_css_pipeline_stage *stage); +static int pipeline_stage_create( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_pipeline_stage **new_stage); +static void ia_css_pipeline_set_zoom_stage(struct ia_css_pipeline *pipeline); +static void ia_css_pipeline_configure_inout_port(struct ia_css_pipeline *me, + bool continuous); + +/******************************************************* +*** Public functions +********************************************************/ +void ia_css_pipeline_init(void) +{ + pipeline_init_sp_thread_map(); +} + +int ia_css_pipeline_create( + struct ia_css_pipeline *pipeline, + enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + unsigned int dvs_frame_delay) +{ + assert(pipeline); + IA_CSS_ENTER_PRIVATE("pipeline = %p, pipe_id = %d, pipe_num = %d, dvs_frame_delay = %d", + pipeline, pipe_id, pipe_num, dvs_frame_delay); + if (!pipeline) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + pipeline_init_defaults(pipeline, pipe_id, pipe_num, dvs_frame_delay); + + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +void ia_css_pipeline_map(unsigned int pipe_num, bool map) +{ + assert(pipe_num < IA_CSS_PIPELINE_NUM_MAX); + IA_CSS_ENTER_PRIVATE("pipe_num = %d, map = %d", pipe_num, map); + + if (pipe_num >= IA_CSS_PIPELINE_NUM_MAX) { + IA_CSS_ERROR("Invalid pipe number"); + IA_CSS_LEAVE_PRIVATE("void"); + return; + } + if (map) + pipeline_map_num_to_sp_thread(pipe_num); + else + pipeline_unmap_num_to_sp_thread(pipe_num); + IA_CSS_LEAVE_PRIVATE("void"); +} + +/* @brief destroy a pipeline + * + * @param[in] pipeline + * @return None + * + */ +void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline) +{ + assert(pipeline); + IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline); + + if (!pipeline) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE("void"); + return; + } + + IA_CSS_LOG("pipe_num = %d", pipeline->pipe_num); + + /* Free the pipeline number */ + ia_css_pipeline_clean(pipeline); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +/* Run a pipeline and wait till it completes. */ +void ia_css_pipeline_start(enum ia_css_pipe_id pipe_id, + struct ia_css_pipeline *pipeline) +{ + u8 pipe_num = 0; + unsigned int thread_id; + + assert(pipeline); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_start() enter: pipe_id=%d, pipeline=%p\n", + pipe_id, pipeline); + pipeline->pipe_id = pipe_id; + sh_css_sp_init_pipeline(pipeline, pipe_id, pipe_num, + false, false, false, true, SH_CSS_BDS_FACTOR_1_00, + SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD, + IA_CSS_INPUT_MODE_MEMORY, NULL, NULL, + (enum mipi_port_id)0); + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + if (!sh_css_sp_is_running()) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_start() error,leaving\n"); + /* queues are invalid*/ + return; + } + ia_css_bufq_enqueue_psys_event(IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, + 0, + 0); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_start() leave: return_void\n"); +} + +/* + * @brief Query the SP thread ID. + * Refer to "sh_css_internal.h" for details. + */ +bool ia_css_pipeline_get_sp_thread_id(unsigned int key, unsigned int *val) +{ + IA_CSS_ENTER("key=%d, val=%p", key, val); + + if ((!val) || (key >= IA_CSS_PIPELINE_NUM_MAX) || (key >= IA_CSS_PIPE_ID_NUM)) { + IA_CSS_LEAVE("return value = false"); + return false; + } + + *val = pipeline_num_to_sp_thread_map[key]; + + if (*val == (unsigned int)PIPELINE_NUM_UNMAPPED) { + IA_CSS_LOG("unmapped pipeline number"); + IA_CSS_LEAVE("return value = false"); + return false; + } + IA_CSS_LEAVE("return value = true"); + return true; +} + +void ia_css_pipeline_dump_thread_map_info(void) +{ + unsigned int i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "pipeline_num_to_sp_thread_map:\n"); + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "pipe_num: %u, tid: 0x%x\n", i, pipeline_num_to_sp_thread_map[i]); + } +} + +int ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline) +{ + int err = 0; + unsigned int thread_id; + + assert(pipeline); + + if (!pipeline) + return -EINVAL; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_request_stop() enter: pipeline=%p\n", + pipeline); + pipeline->stop_requested = true; + + /* Send stop event to the sp*/ + /* This needs improvement, stop on all the pipes available + * in the stream*/ + ia_css_pipeline_get_sp_thread_id(pipeline->pipe_num, &thread_id); + if (!sh_css_sp_is_running()) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_request_stop() leaving\n"); + /* queues are invalid */ + return -EBUSY; + } + ia_css_bufq_enqueue_psys_event(IA_CSS_PSYS_SW_EVENT_STOP_STREAM, + (uint8_t)thread_id, + 0, + 0); + sh_css_sp_uninit_pipeline(pipeline->pipe_num); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_request_stop() leave: return_err=%d\n", + err); + return err; +} + +void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline) +{ + struct ia_css_pipeline_stage *s; + + assert(pipeline); + IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline); + + if (!pipeline) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE("void"); + return; + } + s = pipeline->stages; + + while (s) { + struct ia_css_pipeline_stage *next = s->next; + + pipeline_stage_destroy(s); + s = next; + } + pipeline_init_defaults(pipeline, pipeline->pipe_id, pipeline->pipe_num, + pipeline->dvs_frame_delay); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +/* @brief Add a stage to pipeline. + * + * @param pipeline Pointer to the pipeline to be added to. + * @param[in] stage_desc The description of the stage + * @param[out] stage The successor of the stage. + * @return 0 or error code upon error. + * + * Add a new stage to a non-NULL pipeline. + * The stage consists of an ISP binary or firmware and input and + * output arguments. +*/ +int ia_css_pipeline_create_and_add_stage( + struct ia_css_pipeline *pipeline, + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_pipeline_stage **stage) +{ + struct ia_css_pipeline_stage *last, *new_stage = NULL; + int err; + + /* other arguments can be NULL */ + assert(pipeline); + assert(stage_desc); + last = pipeline->stages; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_create_and_add_stage() enter:\n"); + if (!stage_desc->binary && !stage_desc->firmware + && (stage_desc->sp_func == IA_CSS_PIPELINE_NO_FUNC)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_create_and_add_stage() done: Invalid args\n"); + + return -EINVAL; + } + + /* Find the last stage */ + while (last && last->next) + last = last->next; + + /* if in_frame is not set, we use the out_frame from the previous + * stage, if no previous stage, it's an error. + */ + if ((stage_desc->sp_func == IA_CSS_PIPELINE_NO_FUNC) + && (!stage_desc->in_frame) + && (!stage_desc->firmware) + && (!stage_desc->binary->online)) { + /* Do this only for ISP stages*/ + if (last && last->args.out_frame[0]) + stage_desc->in_frame = last->args.out_frame[0]; + + if (!stage_desc->in_frame) + return -EINVAL; + } + + /* Create the new stage */ + err = pipeline_stage_create(stage_desc, &new_stage); + if (err) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_create_and_add_stage() done: stage_create_failed\n"); + return err; + } + + if (last) + last->next = new_stage; + else + pipeline->stages = new_stage; + + /* Output the new stage */ + if (stage) + *stage = new_stage; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_create_and_add_stage() done:\n"); + return 0; +} + +void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline, + bool continuous) +{ + unsigned int i = 0; + struct ia_css_pipeline_stage *stage; + + assert(pipeline); + for (stage = pipeline->stages; stage; stage = stage->next) { + stage->stage_num = i; + i++; + } + pipeline->num_stages = i; + + ia_css_pipeline_set_zoom_stage(pipeline); + ia_css_pipeline_configure_inout_port(pipeline, continuous); +} + +int ia_css_pipeline_get_stage(struct ia_css_pipeline *pipeline, + int mode, + struct ia_css_pipeline_stage **stage) +{ + struct ia_css_pipeline_stage *s; + + assert(pipeline); + assert(stage); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_get_stage() enter:\n"); + for (s = pipeline->stages; s; s = s->next) { + if (s->mode == mode) { + *stage = s; + return 0; + } + } + return -EINVAL; +} + +int ia_css_pipeline_get_stage_from_fw(struct ia_css_pipeline + *pipeline, + u32 fw_handle, + struct ia_css_pipeline_stage **stage) +{ + struct ia_css_pipeline_stage *s; + + assert(pipeline); + assert(stage); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + for (s = pipeline->stages; s; s = s->next) { + if ((s->firmware) && (s->firmware->handle == fw_handle)) { + *stage = s; + return 0; + } + } + return -EINVAL; +} + +int ia_css_pipeline_get_fw_from_stage(struct ia_css_pipeline + *pipeline, + u32 stage_num, + uint32_t *fw_handle) +{ + struct ia_css_pipeline_stage *s; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + if ((!pipeline) || (!fw_handle)) + return -EINVAL; + + for (s = pipeline->stages; s; s = s->next) { + if ((s->stage_num == stage_num) && (s->firmware)) { + *fw_handle = s->firmware->handle; + return 0; + } + } + return -EINVAL; +} + +int ia_css_pipeline_get_output_stage( + struct ia_css_pipeline *pipeline, + int mode, + struct ia_css_pipeline_stage **stage) +{ + struct ia_css_pipeline_stage *s; + + assert(pipeline); + assert(stage); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_get_output_stage() enter:\n"); + + *stage = NULL; + /* First find acceleration firmware at end of pipe */ + for (s = pipeline->stages; s; s = s->next) { + if (s->firmware && s->mode == mode && + s->firmware->info.isp.sp.enable.output) + *stage = s; + } + if (*stage) + return 0; + /* If no firmware, find binary in pipe */ + return ia_css_pipeline_get_stage(pipeline, mode, stage); +} + +bool ia_css_pipeline_has_stopped(struct ia_css_pipeline *pipeline) +{ + /* Android compilation files if made an local variable + stack size on android is limited to 2k and this structure + is around 2.5K, in place of static malloc can be done but + if this call is made too often it will lead to fragment memory + versus a fixed allocation */ + static struct sh_css_sp_group sp_group; + unsigned int thread_id; + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_group; + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_group = fw->info.sp.group; + + ia_css_pipeline_get_sp_thread_id(pipeline->pipe_num, &thread_id); + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_group), + &sp_group, sizeof(struct sh_css_sp_group)); + return sp_group.pipe[thread_id].num_stages == 0; +} + +#if defined(ISP2401) +struct sh_css_sp_pipeline_io_status *ia_css_pipeline_get_pipe_io_status(void) +{ + return(&sh_css_sp_group.pipe_io_status); +} +#endif + +bool ia_css_pipeline_is_mapped(unsigned int key) +{ + bool ret = false; + + IA_CSS_ENTER_PRIVATE("key = %d", key); + + if ((key >= IA_CSS_PIPELINE_NUM_MAX) || (key >= IA_CSS_PIPE_ID_NUM)) { + IA_CSS_ERROR("Invalid key!!"); + IA_CSS_LEAVE_PRIVATE("return = %d", false); + return false; + } + + ret = (bool)(pipeline_num_to_sp_thread_map[key] != (unsigned int) + PIPELINE_NUM_UNMAPPED); + + IA_CSS_LEAVE_PRIVATE("return = %d", ret); + return ret; +} + +/******************************************************* +*** Static functions +********************************************************/ + +/* Pipeline: + * To organize the several different binaries for each type of mode, + * we use a pipeline. A pipeline contains a number of stages, each with + * their own binary and frame pointers. + * When stages are added to a pipeline, output frames that are not passed + * from outside are automatically allocated. + * When input frames are not passed from outside, each stage will use the + * output frame of the previous stage as input (the full resolution output, + * not the viewfinder output). + * Pipelines must be cleaned and re-created when settings of the binaries + * change. + */ +static void pipeline_stage_destroy(struct ia_css_pipeline_stage *stage) +{ + unsigned int i; + + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (stage->out_frame_allocated[i]) { + ia_css_frame_free(stage->args.out_frame[i]); + stage->args.out_frame[i] = NULL; + } + } + if (stage->vf_frame_allocated) { + ia_css_frame_free(stage->args.out_vf_frame); + stage->args.out_vf_frame = NULL; + } + kvfree(stage); +} + +static void pipeline_init_sp_thread_map(void) +{ + unsigned int i; + + for (i = 1; i < SH_CSS_MAX_SP_THREADS; i++) + pipeline_sp_thread_list[i] = PIPELINE_SP_THREAD_EMPTY_TOKEN; + + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) + pipeline_num_to_sp_thread_map[i] = PIPELINE_NUM_UNMAPPED; +} + +static void pipeline_map_num_to_sp_thread(unsigned int pipe_num) +{ + unsigned int i; + bool found_sp_thread = false; + + /* pipe is not mapped to any thread */ + assert(pipeline_num_to_sp_thread_map[pipe_num] + == (unsigned int)PIPELINE_NUM_UNMAPPED); + + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) { + if (pipeline_sp_thread_list[i] == + PIPELINE_SP_THREAD_EMPTY_TOKEN) { + pipeline_sp_thread_list[i] = + PIPELINE_SP_THREAD_RESERVED_TOKEN; + pipeline_num_to_sp_thread_map[pipe_num] = i; + found_sp_thread = true; + break; + } + } + + /* Make sure a mapping is found */ + /* I could do: + assert(i < SH_CSS_MAX_SP_THREADS); + + But the below is more descriptive. + */ + assert(found_sp_thread); +} + +static void pipeline_unmap_num_to_sp_thread(unsigned int pipe_num) +{ + unsigned int thread_id; + + assert(pipeline_num_to_sp_thread_map[pipe_num] + != (unsigned int)PIPELINE_NUM_UNMAPPED); + + thread_id = pipeline_num_to_sp_thread_map[pipe_num]; + pipeline_num_to_sp_thread_map[pipe_num] = PIPELINE_NUM_UNMAPPED; + pipeline_sp_thread_list[thread_id] = PIPELINE_SP_THREAD_EMPTY_TOKEN; +} + +static int pipeline_stage_create( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_pipeline_stage **new_stage) +{ + int err = 0; + struct ia_css_pipeline_stage *stage = NULL; + struct ia_css_binary *binary; + struct ia_css_frame *vf_frame; + struct ia_css_frame *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + const struct ia_css_fw_info *firmware; + unsigned int i; + + /* Verify input parameters*/ + if (!(stage_desc->in_frame) && !(stage_desc->firmware) + && (stage_desc->binary) && !(stage_desc->binary->online)) { + err = -EINVAL; + goto ERR; + } + + binary = stage_desc->binary; + firmware = stage_desc->firmware; + vf_frame = stage_desc->vf_frame; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + out_frame[i] = stage_desc->out_frame[i]; + } + + stage = kvzalloc(sizeof(*stage), GFP_KERNEL); + if (!stage) { + err = -ENOMEM; + goto ERR; + } + + if (firmware) { + stage->binary = NULL; + stage->binary_info = + (struct ia_css_binary_info *)&firmware->info.isp; + } else { + stage->binary = binary; + if (binary) + stage->binary_info = + (struct ia_css_binary_info *)binary->info; + else + stage->binary_info = NULL; + } + + stage->firmware = firmware; + stage->sp_func = stage_desc->sp_func; + stage->max_input_width = stage_desc->max_input_width; + stage->mode = stage_desc->mode; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + stage->out_frame_allocated[i] = false; + stage->vf_frame_allocated = false; + stage->next = NULL; + sh_css_binary_args_reset(&stage->args); + + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (!(out_frame[i]) && (binary) + && (binary->out_frame_info[i].res.width)) { + err = ia_css_frame_allocate_from_info(&out_frame[i], + &binary->out_frame_info[i]); + if (err) + goto ERR; + stage->out_frame_allocated[i] = true; + } + } + /* VF frame is not needed in case of need_pp + However, the capture binary needs a vf frame to write to. + */ + if (!vf_frame) { + if ((binary && binary->vf_frame_info.res.width) || + (firmware && firmware->info.isp.sp.enable.vf_veceven) + ) { + err = ia_css_frame_allocate_from_info(&vf_frame, + &binary->vf_frame_info); + if (err) + goto ERR; + stage->vf_frame_allocated = true; + } + } else if (vf_frame && binary && binary->vf_frame_info.res.width + && !firmware) { + /* only mark as allocated if buffer pointer available */ + if (vf_frame->data != mmgr_NULL) + stage->vf_frame_allocated = true; + } + + stage->args.in_frame = stage_desc->in_frame; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + stage->args.out_frame[i] = out_frame[i]; + stage->args.out_vf_frame = vf_frame; + *new_stage = stage; + return err; +ERR: + if (stage) + pipeline_stage_destroy(stage); + return err; +} + +static const struct ia_css_frame ia_css_default_frame = DEFAULT_FRAME; + +static void pipeline_init_defaults( + struct ia_css_pipeline *pipeline, + enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + unsigned int dvs_frame_delay) +{ + unsigned int i; + + pipeline->pipe_id = pipe_id; + pipeline->stages = NULL; + pipeline->stop_requested = false; + pipeline->current_stage = NULL; + + memcpy(&pipeline->in_frame, &ia_css_default_frame, + sizeof(ia_css_default_frame)); + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + memcpy(&pipeline->out_frame[i], &ia_css_default_frame, + sizeof(ia_css_default_frame)); + memcpy(&pipeline->vf_frame[i], &ia_css_default_frame, + sizeof(ia_css_default_frame)); + } + pipeline->num_execs = -1; + pipeline->acquire_isp_each_stage = true; + pipeline->pipe_num = (uint8_t)pipe_num; + pipeline->dvs_frame_delay = dvs_frame_delay; +} + +static void ia_css_pipeline_set_zoom_stage(struct ia_css_pipeline *pipeline) +{ + struct ia_css_pipeline_stage *stage = NULL; + int err = 0; + + assert(pipeline); + if (pipeline->pipe_id == IA_CSS_PIPE_ID_PREVIEW) { + /* in preview pipeline, vf_pp stage should do zoom */ + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_VF_PP, &stage); + if (!err) + stage->enable_zoom = true; + } else if (pipeline->pipe_id == IA_CSS_PIPE_ID_CAPTURE) { + /* in capture pipeline, capture_pp stage should do zoom */ + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_CAPTURE_PP, + &stage); + if (!err) + stage->enable_zoom = true; + } else if (pipeline->pipe_id == IA_CSS_PIPE_ID_VIDEO) { + /* in video pipeline, video stage should do zoom */ + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_VIDEO, &stage); + if (!err) + stage->enable_zoom = true; + } else if (pipeline->pipe_id == IA_CSS_PIPE_ID_YUVPP) { + /* in yuvpp pipeline, first yuv_scaler stage should do zoom */ + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_CAPTURE_PP, + &stage); + if (!err) + stage->enable_zoom = true; + } +} + +static void +ia_css_pipeline_configure_inout_port(struct ia_css_pipeline *me, + bool continuous) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipeline_configure_inout_port() enter: pipe_id(%d) continuous(%d)\n", + me->pipe_id, continuous); + switch (me->pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + case IA_CSS_PIPE_ID_VIDEO: + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)(continuous ? SH_CSS_COPYSINK_TYPE : SH_CSS_HOST_TYPE), 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + break; + case IA_CSS_PIPE_ID_COPY: /*Copy pipe ports configured to "offline" mode*/ + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + if (continuous) { + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_COPYSINK_TYPE, 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_TAGGERSINK_TYPE, 1); + } else { + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + } + break; + case IA_CSS_PIPE_ID_CAPTURE: + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)(continuous ? SH_CSS_TAGGERSINK_TYPE : SH_CSS_HOST_TYPE), + 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + break; + case IA_CSS_PIPE_ID_YUVPP: + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)(SH_CSS_HOST_TYPE), 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + break; + default: + break; + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipeline_configure_inout_port() leave: inout_port_config(%x)\n", + me->inout_port_config); +} diff --git a/drivers/staging/media/atomisp/pci/runtime/queue/interface/ia_css_queue.h b/drivers/staging/media/atomisp/pci/runtime/queue/interface/ia_css_queue.h new file mode 100644 index 000000000..08112be46 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/queue/interface/ia_css_queue.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_QUEUE_H +#define __IA_CSS_QUEUE_H + +#include +#include + +#include "ia_css_queue_comm.h" +#include "../src/queue_access.h" + +/* Local Queue object descriptor */ +struct ia_css_queue_local { + ia_css_circbuf_desc_t *cb_desc; /*Circbuf desc for local queues*/ + ia_css_circbuf_elem_t *cb_elems; /*Circbuf elements*/ +}; + +typedef struct ia_css_queue_local ia_css_queue_local_t; + +/* Handle for queue object*/ +typedef struct ia_css_queue ia_css_queue_t; + +/***************************************************************************** + * Queue Public APIs + *****************************************************************************/ +/* @brief Initialize a local queue instance. + * + * @param[out] qhandle. Handle to queue instance for use with API + * @param[in] desc. Descriptor with queue properties filled-in + * @return 0 - Successful init of local queue instance. + * @return -EINVAL - Invalid argument. + * + */ +int ia_css_queue_local_init( + ia_css_queue_t *qhandle, + ia_css_queue_local_t *desc); + +/* @brief Initialize a remote queue instance + * + * @param[out] qhandle. Handle to queue instance for use with API + * @param[in] desc. Descriptor with queue properties filled-in + * @return 0 - Successful init of remote queue instance. + * @return -EINVAL - Invalid argument. + */ +int ia_css_queue_remote_init( + ia_css_queue_t *qhandle, + ia_css_queue_remote_t *desc); + +/* @brief Uninitialize a queue instance + * + * @param[in] qhandle. Handle to queue instance + * @return 0 - Successful uninit. + * + */ +int ia_css_queue_uninit( + ia_css_queue_t *qhandle); + +/* @brief Enqueue an item in the queue instance + * + * @param[in] qhandle. Handle to queue instance + * @param[in] item. Object to be enqueued. + * @return 0 - Successful enqueue. + * @return -EINVAL - Invalid argument. + * @return -ENOBUFS - Queue is full. + * + */ +int ia_css_queue_enqueue( + ia_css_queue_t *qhandle, + uint32_t item); + +/* @brief Dequeue an item from the queue instance + * + * @param[in] qhandle. Handle to queue instance + * @param[out] item. Object to be dequeued into this item. + + * @return 0 - Successful dequeue. + * @return -EINVAL - Invalid argument. + * @return -ENODATA - Queue is empty. + * + */ +int ia_css_queue_dequeue( + ia_css_queue_t *qhandle, + uint32_t *item); + +/* @brief Check if the queue is empty + * + * @param[in] qhandle. Handle to queue instance + * @param[in] is_empty True if empty, False if not. + * @return 0 - Successful access state. + * @return -EINVAL - Invalid argument. + * @return -ENOSYS - Function not implemented. + * + */ +int ia_css_queue_is_empty( + ia_css_queue_t *qhandle, + bool *is_empty); + +/* @brief Check if the queue is full + * + * @param[in] qhandle. Handle to queue instance + * @param[in] is_full True if Full, False if not. + * @return 0 - Successfully access state. + * @return -EINVAL - Invalid argument. + * @return -ENOSYS - Function not implemented. + * + */ +int ia_css_queue_is_full( + ia_css_queue_t *qhandle, + bool *is_full); + +/* @brief Get used space in the queue + * + * @param[in] qhandle. Handle to queue instance + * @param[in] size Number of available elements in the queue + * @return 0 - Successfully access state. + * @return -EINVAL - Invalid argument. + * + */ +int ia_css_queue_get_used_space( + ia_css_queue_t *qhandle, + uint32_t *size); + +/* @brief Get free space in the queue + * + * @param[in] qhandle. Handle to queue instance + * @param[in] size Number of free elements in the queue + * @return 0 - Successfully access state. + * @return -EINVAL - Invalid argument. + * + */ +int ia_css_queue_get_free_space( + ia_css_queue_t *qhandle, + uint32_t *size); + +/* @brief Peek at an element in the queue + * + * @param[in] qhandle. Handle to queue instance + * @param[in] offset Offset of element to peek, + * starting from head of queue + * @param[in] element Value of element returned + * @return 0 - Successfully access state. + * @return -EINVAL - Invalid argument. + * + */ +int ia_css_queue_peek( + ia_css_queue_t *qhandle, + u32 offset, + uint32_t *element); + +/* @brief Get the usable size for the queue + * + * @param[in] qhandle. Handle to queue instance + * @param[out] size Size value to be returned here. + * @return 0 - Successful get size. + * @return -EINVAL - Invalid argument. + * @return -ENOSYS - Function not implemented. + * + */ +int ia_css_queue_get_size( + ia_css_queue_t *qhandle, + uint32_t *size); + +#endif /* __IA_CSS_QUEUE_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/queue/interface/ia_css_queue_comm.h b/drivers/staging/media/atomisp/pci/runtime/queue/interface/ia_css_queue_comm.h new file mode 100644 index 000000000..1379ae8f8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/queue/interface/ia_css_queue_comm.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_QUEUE_COMM_H +#define __IA_CSS_QUEUE_COMM_H + +#include "type_support.h" +#include "ia_css_circbuf.h" +/***************************************************************************** + * Queue Public Data Structures + *****************************************************************************/ + +/* Queue location specifier */ +/* Avoiding enums to save space */ +#define IA_CSS_QUEUE_LOC_HOST 0 +#define IA_CSS_QUEUE_LOC_SP 1 +#define IA_CSS_QUEUE_LOC_ISP 2 + +/* Queue type specifier */ +/* Avoiding enums to save space */ +#define IA_CSS_QUEUE_TYPE_LOCAL 0 +#define IA_CSS_QUEUE_TYPE_REMOTE 1 + +/* for DDR Allocated queues, +allocate minimum these many elements. +DDR->SP' DMEM DMA transfer needs 32byte aligned address. +Since each element size is 4 bytes, 8 elements need to be +DMAed to access single element.*/ +#define IA_CSS_MIN_ELEM_COUNT 8 +#define IA_CSS_DMA_XFER_MASK (IA_CSS_MIN_ELEM_COUNT - 1) + +/* Remote Queue object descriptor */ +struct ia_css_queue_remote { + u32 cb_desc_addr; /*Circbuf desc address for remote queues*/ + u32 cb_elems_addr; /*Circbuf elements addr for remote queue*/ + u8 location; /* Cell location for queue */ + u8 proc_id; /* Processor id for queue access */ +}; + +typedef struct ia_css_queue_remote ia_css_queue_remote_t; + +#endif /* __IA_CSS_QUEUE_COMM_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/queue/src/queue.c b/drivers/staging/media/atomisp/pci/runtime/queue/src/queue.c new file mode 100644 index 000000000..2f1c2df59 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/queue/src/queue.c @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_queue.h" +#include +#include +#include +#include "queue_access.h" + +/***************************************************************************** + * Queue Public APIs + *****************************************************************************/ +int ia_css_queue_local_init(ia_css_queue_t *qhandle, ia_css_queue_local_t *desc) +{ + if (NULL == qhandle || NULL == desc + || NULL == desc->cb_elems || NULL == desc->cb_desc) { + /* Invalid parameters, return error*/ + return -EINVAL; + } + + /* Mark the queue as Local */ + qhandle->type = IA_CSS_QUEUE_TYPE_LOCAL; + + /* Create a local circular buffer queue*/ + ia_css_circbuf_create(&qhandle->desc.cb_local, + desc->cb_elems, + desc->cb_desc); + + return 0; +} + +int ia_css_queue_remote_init(ia_css_queue_t *qhandle, ia_css_queue_remote_t *desc) +{ + if (NULL == qhandle || NULL == desc) { + /* Invalid parameters, return error*/ + return -EINVAL; + } + + /* Mark the queue as remote*/ + qhandle->type = IA_CSS_QUEUE_TYPE_REMOTE; + + /* Copy over the local queue descriptor*/ + qhandle->location = desc->location; + qhandle->proc_id = desc->proc_id; + qhandle->desc.remote.cb_desc_addr = desc->cb_desc_addr; + qhandle->desc.remote.cb_elems_addr = desc->cb_elems_addr; + + /* If queue is remote, we let the local processor + * do its init, before using it. This is just to get us + * started, we can remove this restriction as we go ahead + */ + + return 0; +} + +int ia_css_queue_uninit(ia_css_queue_t *qhandle) +{ + if (!qhandle) + return -EINVAL; + + /* Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Local queues are created. Destroy it*/ + ia_css_circbuf_destroy(&qhandle->desc.cb_local); + } + + return 0; +} + +int ia_css_queue_enqueue(ia_css_queue_t *qhandle, uint32_t item) +{ + int error = 0; + + if (!qhandle) + return -EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + if (ia_css_circbuf_is_full(&qhandle->desc.cb_local)) { + /* Cannot push the element. Return*/ + return -ENOBUFS; + } + + /* Push the element*/ + ia_css_circbuf_push(&qhandle->desc.cb_local, item); + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + ia_css_circbuf_desc_t cb_desc; + ia_css_circbuf_elem_t cb_elem; + u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + /* a. Load the queue cb_desc from remote */ + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + if (ia_css_circbuf_desc_is_full(&cb_desc)) + return -ENOBUFS; + + cb_elem.val = item; + + error = ia_css_queue_item_store(qhandle, cb_desc.end, &cb_elem); + if (error != 0) + return error; + + cb_desc.end = (cb_desc.end + 1) % cb_desc.size; + + /* c. Store the queue object */ + /* Set only fields requiring update with + * valid value. Avoids uncessary calls + * to load/store functions + */ + ignore_desc_flags = QUEUE_IGNORE_SIZE_START_STEP_FLAGS; + + error = ia_css_queue_store(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + } + + return 0; +} + +int ia_css_queue_dequeue(ia_css_queue_t *qhandle, uint32_t *item) +{ + int error = 0; + + if (!qhandle || NULL == item) + return -EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + if (ia_css_circbuf_is_empty(&qhandle->desc.cb_local)) { + /* Nothing to pop. Return empty queue*/ + return -ENODATA; + } + + *item = ia_css_circbuf_pop(&qhandle->desc.cb_local); + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + ia_css_circbuf_elem_t cb_elem; + u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + if (ia_css_circbuf_desc_is_empty(&cb_desc)) + return -ENODATA; + + error = ia_css_queue_item_load(qhandle, cb_desc.start, &cb_elem); + if (error != 0) + return error; + + *item = cb_elem.val; + + cb_desc.start = OP_std_modadd(cb_desc.start, 1, cb_desc.size); + + /* c. Store the queue object */ + /* Set only fields requiring update with + * valid value. Avoids uncessary calls + * to load/store functions + */ + ignore_desc_flags = QUEUE_IGNORE_SIZE_END_STEP_FLAGS; + error = ia_css_queue_store(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + } + return 0; +} + +int ia_css_queue_is_full(ia_css_queue_t *qhandle, bool *is_full) +{ + int error = 0; + + if ((!qhandle) || (!is_full)) + return -EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + *is_full = ia_css_circbuf_is_full(&qhandle->desc.cb_local); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + *is_full = ia_css_circbuf_desc_is_full(&cb_desc); + return 0; + } + + return -EINVAL; +} + +int ia_css_queue_get_free_space(ia_css_queue_t *qhandle, uint32_t *size) +{ + int error = 0; + + if ((!qhandle) || (!size)) + return -EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + *size = ia_css_circbuf_get_free_elems(&qhandle->desc.cb_local); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + *size = ia_css_circbuf_desc_get_free_elems(&cb_desc); + return 0; + } + + return -EINVAL; +} + +int ia_css_queue_get_used_space(ia_css_queue_t *qhandle, uint32_t *size) +{ + int error = 0; + + if ((!qhandle) || (!size)) + return -EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + *size = ia_css_circbuf_get_num_elems(&qhandle->desc.cb_local); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + *size = ia_css_circbuf_desc_get_num_elems(&cb_desc); + return 0; + } + + return -EINVAL; +} + +int ia_css_queue_peek(ia_css_queue_t *qhandle, u32 offset, uint32_t *element) +{ + u32 num_elems = 0; + int error = 0; + + if ((!qhandle) || (!element)) + return -EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + /* Check if offset is valid */ + num_elems = ia_css_circbuf_get_num_elems(&qhandle->desc.cb_local); + if (offset > num_elems) + return -EINVAL; + + *element = ia_css_circbuf_peek_from_start(&qhandle->desc.cb_local, (int)offset); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + ia_css_circbuf_elem_t cb_elem; + u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* Check if offset is valid */ + num_elems = ia_css_circbuf_desc_get_num_elems(&cb_desc); + if (offset > num_elems) + return -EINVAL; + + offset = OP_std_modadd(cb_desc.start, offset, cb_desc.size); + error = ia_css_queue_item_load(qhandle, (uint8_t)offset, &cb_elem); + if (error != 0) + return error; + + *element = cb_elem.val; + return 0; + } + + return -EINVAL; +} + +int ia_css_queue_is_empty(ia_css_queue_t *qhandle, bool *is_empty) +{ + int error = 0; + + if ((!qhandle) || (!is_empty)) + return -EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + *is_empty = ia_css_circbuf_is_empty(&qhandle->desc.cb_local); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + u32 ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + *is_empty = ia_css_circbuf_desc_is_empty(&cb_desc); + return 0; + } + + return -EINVAL; +} + +int ia_css_queue_get_size(ia_css_queue_t *qhandle, uint32_t *size) +{ + int error = 0; + + if ((!qhandle) || (!size)) + return -EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + /* Return maximum usable capacity */ + *size = ia_css_circbuf_get_size(&qhandle->desc.cb_local); + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + u32 ignore_desc_flags = QUEUE_IGNORE_START_END_STEP_FLAGS; + + QUEUE_CB_DESC_INIT(&cb_desc); + + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* Return maximum usable capacity */ + *size = cb_desc.size; + } + + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/runtime/queue/src/queue_access.c b/drivers/staging/media/atomisp/pci/runtime/queue/src/queue_access.c new file mode 100644 index 000000000..424e7a15a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/queue/src/queue_access.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include "type_support.h" +#include "queue_access.h" +#include "ia_css_circbuf.h" +#include "sp.h" +#include "assert_support.h" + +int ia_css_queue_load( + struct ia_css_queue *rdesc, + ia_css_circbuf_desc_t *cb_desc, + uint32_t ignore_desc_flags) +{ + if (!rdesc || !cb_desc) + return -EINVAL; + + if (rdesc->location == IA_CSS_QUEUE_LOC_SP) { + assert(ignore_desc_flags <= QUEUE_IGNORE_DESC_FLAGS_MAX); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_SIZE_FLAG)) { + cb_desc->size = sp_dmem_load_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, size)); + + if (cb_desc->size == 0) { + /* Adding back the workaround which was removed + while refactoring queues. When reading size + through sp_dmem_load_*, sometimes we get back + the value as zero. This causes division by 0 + exception as the size is used in a modular + division operation. */ + return -EDOM; + } + } + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_START_FLAG)) + cb_desc->start = sp_dmem_load_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, start)); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_END_FLAG)) + cb_desc->end = sp_dmem_load_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, end)); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_STEP_FLAG)) + cb_desc->step = sp_dmem_load_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, step)); + + } else if (rdesc->location == IA_CSS_QUEUE_LOC_HOST) { + /* doing DMA transfer of entire structure */ + hmm_load(rdesc->desc.remote.cb_desc_addr, + (void *)cb_desc, + sizeof(ia_css_circbuf_desc_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_ISP) { + /* Not supported yet */ + return -ENOTSUPP; + } + + return 0; +} + +int ia_css_queue_store( + struct ia_css_queue *rdesc, + ia_css_circbuf_desc_t *cb_desc, + uint32_t ignore_desc_flags) +{ + if (!rdesc || !cb_desc) + return -EINVAL; + + if (rdesc->location == IA_CSS_QUEUE_LOC_SP) { + assert(ignore_desc_flags <= QUEUE_IGNORE_DESC_FLAGS_MAX); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_SIZE_FLAG)) + sp_dmem_store_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, size), + cb_desc->size); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_START_FLAG)) + sp_dmem_store_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, start), + cb_desc->start); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_END_FLAG)) + sp_dmem_store_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, end), + cb_desc->end); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_STEP_FLAG)) + sp_dmem_store_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, step), + cb_desc->step); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_HOST) { + /* doing DMA transfer of entire structure */ + hmm_store(rdesc->desc.remote.cb_desc_addr, + (void *)cb_desc, + sizeof(ia_css_circbuf_desc_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_ISP) { + /* Not supported yet */ + return -ENOTSUPP; + } + + return 0; +} + +int ia_css_queue_item_load( + struct ia_css_queue *rdesc, + u8 position, + ia_css_circbuf_elem_t *item) +{ + if (!rdesc || !item) + return -EINVAL; + + if (rdesc->location == IA_CSS_QUEUE_LOC_SP) { + sp_dmem_load(rdesc->proc_id, + rdesc->desc.remote.cb_elems_addr + + position * sizeof(ia_css_circbuf_elem_t), + item, + sizeof(ia_css_circbuf_elem_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_HOST) { + hmm_load(rdesc->desc.remote.cb_elems_addr + + position * sizeof(ia_css_circbuf_elem_t), + (void *)item, + sizeof(ia_css_circbuf_elem_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_ISP) { + /* Not supported yet */ + return -ENOTSUPP; + } + + return 0; +} + +int ia_css_queue_item_store( + struct ia_css_queue *rdesc, + u8 position, + ia_css_circbuf_elem_t *item) +{ + if (!rdesc || !item) + return -EINVAL; + + if (rdesc->location == IA_CSS_QUEUE_LOC_SP) { + sp_dmem_store(rdesc->proc_id, + rdesc->desc.remote.cb_elems_addr + + position * sizeof(ia_css_circbuf_elem_t), + item, + sizeof(ia_css_circbuf_elem_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_HOST) { + hmm_store(rdesc->desc.remote.cb_elems_addr + + position * sizeof(ia_css_circbuf_elem_t), + (void *)item, + sizeof(ia_css_circbuf_elem_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_ISP) { + /* Not supported yet */ + return -ENOTSUPP; + } + + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/runtime/queue/src/queue_access.h b/drivers/staging/media/atomisp/pci/runtime/queue/src/queue_access.h new file mode 100644 index 000000000..d5107adcc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/queue/src/queue_access.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_ACCESS_H +#define __QUEUE_ACCESS_H + +#include + +#include +#include +#include + +#define QUEUE_IGNORE_START_FLAG 0x0001 +#define QUEUE_IGNORE_END_FLAG 0x0002 +#define QUEUE_IGNORE_SIZE_FLAG 0x0004 +#define QUEUE_IGNORE_STEP_FLAG 0x0008 +#define QUEUE_IGNORE_DESC_FLAGS_MAX 0x000f + +#define QUEUE_IGNORE_SIZE_START_STEP_FLAGS \ + (QUEUE_IGNORE_SIZE_FLAG | \ + QUEUE_IGNORE_START_FLAG | \ + QUEUE_IGNORE_STEP_FLAG) + +#define QUEUE_IGNORE_SIZE_END_STEP_FLAGS \ + (QUEUE_IGNORE_SIZE_FLAG | \ + QUEUE_IGNORE_END_FLAG | \ + QUEUE_IGNORE_STEP_FLAG) + +#define QUEUE_IGNORE_START_END_STEP_FLAGS \ + (QUEUE_IGNORE_START_FLAG | \ + QUEUE_IGNORE_END_FLAG | \ + QUEUE_IGNORE_STEP_FLAG) + +#define QUEUE_CB_DESC_INIT(cb_desc) \ + do { \ + (cb_desc)->size = 0; \ + (cb_desc)->step = 0; \ + (cb_desc)->start = 0; \ + (cb_desc)->end = 0; \ + } while (0) + +struct ia_css_queue { + u8 type; /* Specify remote/local type of access */ + u8 location; /* Cell location for queue */ + u8 proc_id; /* Processor id for queue access */ + union { + ia_css_circbuf_t cb_local; + struct { + u32 cb_desc_addr; /*Circbuf desc address for remote queues*/ + u32 cb_elems_addr; /*Circbuf elements addr for remote queue*/ + } remote; + } desc; +}; + +int ia_css_queue_load( + struct ia_css_queue *rdesc, + ia_css_circbuf_desc_t *cb_desc, + uint32_t ignore_desc_flags); + +int ia_css_queue_store( + struct ia_css_queue *rdesc, + ia_css_circbuf_desc_t *cb_desc, + uint32_t ignore_desc_flags); + +int ia_css_queue_item_load( + struct ia_css_queue *rdesc, + u8 position, + ia_css_circbuf_elem_t *item); + +int ia_css_queue_item_store( + struct ia_css_queue *rdesc, + u8 position, + ia_css_circbuf_elem_t *item); + +#endif /* __QUEUE_ACCESS_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/rmgr/interface/ia_css_rmgr.h b/drivers/staging/media/atomisp/pci/runtime/rmgr/interface/ia_css_rmgr.h new file mode 100644 index 000000000..9cd3d92b3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/rmgr/interface/ia_css_rmgr.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_RMGR_H +#define _IA_CSS_RMGR_H + +#include + +#ifndef __INLINE_RMGR__ +#define STORAGE_CLASS_RMGR_H extern +#define STORAGE_CLASS_RMGR_C +#else /* __INLINE_RMGR__ */ +#define STORAGE_CLASS_RMGR_H static inline +#define STORAGE_CLASS_RMGR_C static inline +#endif /* __INLINE_RMGR__ */ + +/** + * @brief Initialize resource manager (host/common) + */ +int ia_css_rmgr_init(void); + +/** + * @brief Uninitialize resource manager (host/common) + */ +void ia_css_rmgr_uninit(void); + +/***************************************************************** + * Interface definition - resource type (host/common) + ***************************************************************** + * + * struct ia_css_rmgr__pool; + * struct ia_css_rmgr__handle; + * + * STORAGE_CLASS_RMGR_H void ia_css_rmgr_init_( + * struct ia_css_rmgr__pool *pool); + * + * STORAGE_CLASS_RMGR_H void ia_css_rmgr_uninit_( + * struct ia_css_rmgr__pool *pool); + * + * STORAGE_CLASS_RMGR_H void ia_css_rmgr_acq_( + * struct ia_css_rmgr__pool *pool, + * struct ia_css_rmgr__handle **handle); + * + * STORAGE_CLASS_RMGR_H void ia_css_rmgr_rel_( + * struct ia_css_rmgr__pool *pool, + * struct ia_css_rmgr__handle **handle); + * + ***************************************************************** + * Interface definition - refcounting (host/common) + ***************************************************************** + * + * void ia_css_rmgr_refcount_retain_( + * struct ia_css_rmgr__handle **handle); + * + * void ia_css_rmgr_refcount_release_( + * struct ia_css_rmgr__handle **handle); + */ + +#include "ia_css_rmgr_vbuf.h" + +#endif /* _IA_CSS_RMGR_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/rmgr/interface/ia_css_rmgr_vbuf.h b/drivers/staging/media/atomisp/pci/runtime/rmgr/interface/ia_css_rmgr_vbuf.h new file mode 100644 index 000000000..ac969afc8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/rmgr/interface/ia_css_rmgr_vbuf.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_RMGR_VBUF_H +#define _IA_CSS_RMGR_VBUF_H + +#include "ia_css_rmgr.h" +#include +#include +#include + +/** + * @brief Data structure for the resource handle (host, vbuf) + */ +struct ia_css_rmgr_vbuf_handle { + ia_css_ptr vptr; + u8 count; + u32 size; +}; + +/** + * @brief Data structure for the resource pool (host, vbuf) + */ +struct ia_css_rmgr_vbuf_pool { + u8 copy_on_write; + u8 recycle; + u32 size; + u32 index; + struct ia_css_rmgr_vbuf_handle **handles; +}; + +/** + * @brief VBUF resource pools + */ +extern struct ia_css_rmgr_vbuf_pool *vbuf_ref; +extern struct ia_css_rmgr_vbuf_pool *vbuf_write; +extern struct ia_css_rmgr_vbuf_pool *hmm_buffer_pool; + +/** + * @brief Initialize the resource pool (host, vbuf) + * + * @param pool The pointer to the pool + */ +STORAGE_CLASS_RMGR_H int ia_css_rmgr_init_vbuf( + struct ia_css_rmgr_vbuf_pool *pool); + +/** + * @brief Uninitialize the resource pool (host, vbuf) + * + * @param pool The pointer to the pool + */ +STORAGE_CLASS_RMGR_H void ia_css_rmgr_uninit_vbuf( + struct ia_css_rmgr_vbuf_pool *pool); + +/** + * @brief Acquire a handle from the pool (host, vbuf) + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +STORAGE_CLASS_RMGR_H void ia_css_rmgr_acq_vbuf( + struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle); + +/** + * @brief Release a handle to the pool (host, vbuf) + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +STORAGE_CLASS_RMGR_H void ia_css_rmgr_rel_vbuf( + struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle); + +/** + * @brief Retain the reference count for a handle (host, vbuf) + * + * @param handle The pointer to the handle + */ +void ia_css_rmgr_refcount_retain_vbuf(struct ia_css_rmgr_vbuf_handle **handle); + +/** + * @brief Release the reference count for a handle (host, vbuf) + * + * @param handle The pointer to the handle + */ +void ia_css_rmgr_refcount_release_vbuf(struct ia_css_rmgr_vbuf_handle **handle); + +#endif /* _IA_CSS_RMGR_VBUF_H */ diff --git a/drivers/staging/media/atomisp/pci/runtime/rmgr/src/rmgr.c b/drivers/staging/media/atomisp/pci/runtime/rmgr/src/rmgr.c new file mode 100644 index 000000000..c94a428aa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/rmgr/src/rmgr.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_rmgr.h" + +int ia_css_rmgr_init(void) +{ + int err = 0; + + err = ia_css_rmgr_init_vbuf(vbuf_ref); + if (!err) + err = ia_css_rmgr_init_vbuf(vbuf_write); + if (!err) + err = ia_css_rmgr_init_vbuf(hmm_buffer_pool); + if (err) + ia_css_rmgr_uninit(); + return err; +} + +/* + * @brief Uninitialize resource pool (host) + */ +void ia_css_rmgr_uninit(void) +{ + ia_css_rmgr_uninit_vbuf(hmm_buffer_pool); + ia_css_rmgr_uninit_vbuf(vbuf_write); + ia_css_rmgr_uninit_vbuf(vbuf_ref); +} diff --git a/drivers/staging/media/atomisp/pci/runtime/rmgr/src/rmgr_vbuf.c b/drivers/staging/media/atomisp/pci/runtime/rmgr/src/rmgr_vbuf.c new file mode 100644 index 000000000..2e07dab8b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/rmgr/src/rmgr_vbuf.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" +#include "ia_css_rmgr.h" + +#include +#include +#include /* memset */ +#include + +/* + * @brief VBUF resource handles + */ +#define NUM_HANDLES 1000 +static struct ia_css_rmgr_vbuf_handle handle_table[NUM_HANDLES]; + +/* + * @brief VBUF resource pool - refpool + */ +static struct ia_css_rmgr_vbuf_pool refpool; + +/* + * @brief VBUF resource pool - writepool + */ +static struct ia_css_rmgr_vbuf_pool writepool = { + .copy_on_write = true, +}; + +/* + * @brief VBUF resource pool - hmmbufferpool + */ +static struct ia_css_rmgr_vbuf_pool hmmbufferpool = { + .copy_on_write = true, + .recycle = true, + .size = 32, +}; + +struct ia_css_rmgr_vbuf_pool *vbuf_ref = &refpool; +struct ia_css_rmgr_vbuf_pool *vbuf_write = &writepool; +struct ia_css_rmgr_vbuf_pool *hmm_buffer_pool = &hmmbufferpool; + +/* + * @brief Initialize the reference count (host, vbuf) + */ +static void rmgr_refcount_init_vbuf(void) +{ + /* initialize the refcount table */ + memset(&handle_table, 0, sizeof(handle_table)); +} + +/* + * @brief Retain the reference count for a handle (host, vbuf) + * + * @param handle The pointer to the handle + */ +void ia_css_rmgr_refcount_retain_vbuf(struct ia_css_rmgr_vbuf_handle **handle) +{ + int i; + struct ia_css_rmgr_vbuf_handle *h; + + if ((!handle) || (!*handle)) { + IA_CSS_LOG("Invalid inputs"); + return; + } + /* new vbuf to count on */ + if ((*handle)->count == 0) { + h = *handle; + *handle = NULL; + for (i = 0; i < NUM_HANDLES; i++) { + if (handle_table[i].count == 0) { + *handle = &handle_table[i]; + break; + } + } + /* if the loop dus not break and *handle == NULL + * this is an error handle and report it. + */ + if (!*handle) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_i_host_refcount_retain_vbuf() failed to find empty slot!\n"); + return; + } + (*handle)->vptr = h->vptr; + (*handle)->size = h->size; + } + (*handle)->count++; +} + +/* + * @brief Release the reference count for a handle (host, vbuf) + * + * @param handle The pointer to the handle + */ +void ia_css_rmgr_refcount_release_vbuf(struct ia_css_rmgr_vbuf_handle **handle) +{ + if ((!handle) || ((*handle) == NULL) || (((*handle)->count) == 0)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, "%s invalid arguments!\n", __func__); + return; + } + /* decrease reference count */ + (*handle)->count--; + /* remove from admin */ + if ((*handle)->count == 0) { + (*handle)->vptr = 0x0; + (*handle)->size = 0; + *handle = NULL; + } +} + +/* + * @brief Initialize the resource pool (host, vbuf) + * + * @param pool The pointer to the pool + */ +int ia_css_rmgr_init_vbuf(struct ia_css_rmgr_vbuf_pool *pool) +{ + int err = 0; + size_t bytes_needed; + + rmgr_refcount_init_vbuf(); + assert(pool); + if (!pool) + return -EINVAL; + /* initialize the recycle pool if used */ + if (pool->recycle && pool->size) { + /* allocate memory for storing the handles */ + bytes_needed = + sizeof(void *) * + pool->size; + pool->handles = kvmalloc(bytes_needed, GFP_KERNEL); + if (pool->handles) + memset(pool->handles, 0, bytes_needed); + else + err = -ENOMEM; + } else { + /* just in case, set the size to 0 */ + pool->size = 0; + pool->handles = NULL; + } + return err; +} + +/* + * @brief Uninitialize the resource pool (host, vbuf) + * + * @param pool The pointer to the pool + */ +void ia_css_rmgr_uninit_vbuf(struct ia_css_rmgr_vbuf_pool *pool) +{ + u32 i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); + if (!pool) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, "%s NULL argument\n", __func__); + return; + } + if (pool->handles) { + /* free the hmm buffers */ + for (i = 0; i < pool->size; i++) { + if (pool->handles[i]) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + " freeing/releasing %x (count=%d)\n", + pool->handles[i]->vptr, + pool->handles[i]->count); + /* free memory */ + hmm_free(pool->handles[i]->vptr); + /* remove from refcount admin */ + ia_css_rmgr_refcount_release_vbuf(&pool->handles[i]); + } + } + /* now free the pool handles list */ + kvfree(pool->handles); + pool->handles = NULL; + } +} + +/* + * @brief Push a handle to the pool + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +static +void rmgr_push_handle(struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle) +{ + u32 i; + bool succes = false; + + assert(pool); + assert(pool->recycle); + assert(pool->handles); + assert(handle); + for (i = 0; i < pool->size; i++) { + if (!pool->handles[i]) { + ia_css_rmgr_refcount_retain_vbuf(handle); + pool->handles[i] = *handle; + succes = true; + break; + } + } + assert(succes); +} + +/* + * @brief Pop a handle from the pool + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +static +void rmgr_pop_handle(struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle) +{ + u32 i; + + assert(pool); + assert(pool->recycle); + assert(pool->handles); + assert(handle); + assert(*handle); + for (i = 0; i < pool->size; i++) { + if ((pool->handles[i]) && + (pool->handles[i]->size == (*handle)->size)) { + *handle = pool->handles[i]; + pool->handles[i] = NULL; + /* dont release, we are returning it... + * ia_css_rmgr_refcount_release_vbuf(handle); + */ + return; + } + } +} + +/* + * @brief Acquire a handle from the pool (host, vbuf) + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +void ia_css_rmgr_acq_vbuf(struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle) +{ + if ((!pool) || (!handle) || (!*handle)) { + IA_CSS_LOG("Invalid inputs"); + return; + } + + if (pool->copy_on_write) { + struct ia_css_rmgr_vbuf_handle *new_handle; + struct ia_css_rmgr_vbuf_handle h = { 0 }; + + /* only one reference, reuse (no new retain) */ + if ((*handle)->count == 1) + return; + /* more than one reference, release current buffer */ + if ((*handle)->count > 1) { + /* store current values */ + h.vptr = 0x0; + h.size = (*handle)->size; + /* release ref to current buffer */ + ia_css_rmgr_refcount_release_vbuf(handle); + new_handle = &h; + } else { + new_handle = *handle; + } + /* get new buffer for needed size */ + if (new_handle->vptr == 0x0) { + if (pool->recycle) { + /* try and pop from pool */ + rmgr_pop_handle(pool, &new_handle); + } + if (new_handle->vptr == 0x0) { + /* we need to allocate */ + new_handle->vptr = hmm_alloc(new_handle->size); + } else { + /* we popped a buffer */ + *handle = new_handle; + return; + } + } + /* Note that new_handle will change to an internally maintained one */ + ia_css_rmgr_refcount_retain_vbuf(&new_handle); + *handle = new_handle; + return; + } + /* Note that handle will change to an internally maintained one */ + ia_css_rmgr_refcount_retain_vbuf(handle); +} + +/* + * @brief Release a handle to the pool (host, vbuf) + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +void ia_css_rmgr_rel_vbuf(struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle) +{ + if ((!pool) || (!handle) || (!*handle)) { + IA_CSS_LOG("Invalid inputs"); + return; + } + /* release the handle */ + if ((*handle)->count == 1) { + if (!pool->recycle) { + /* non recycling pool, free mem */ + hmm_free((*handle)->vptr); + } else { + /* recycle to pool */ + rmgr_push_handle(pool, handle); + } + } + ia_css_rmgr_refcount_release_vbuf(handle); + *handle = NULL; +} diff --git a/drivers/staging/media/atomisp/pci/runtime/spctrl/interface/ia_css_spctrl.h b/drivers/staging/media/atomisp/pci/runtime/spctrl/interface/ia_css_spctrl.h new file mode 100644 index 000000000..efe6c4a82 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/spctrl/interface/ia_css_spctrl.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SPCTRL_H__ +#define __IA_CSS_SPCTRL_H__ + +#include +#include +#include "ia_css_spctrl_comm.h" + +typedef struct { + u32 ddr_data_offset; /** posistion of data in DDR */ + u32 dmem_data_addr; /** data segment address in dmem */ + u32 dmem_bss_addr; /** bss segment address in dmem */ + u32 data_size; /** data segment size */ + u32 bss_size; /** bss segment size */ + u32 spctrl_config_dmem_addr; /* + +/* state of SP */ +typedef enum { + IA_CSS_SP_SW_TERMINATED = 0, + IA_CSS_SP_SW_INITIALIZED, + IA_CSS_SP_SW_CONNECTED, + IA_CSS_SP_SW_RUNNING +} ia_css_spctrl_sp_sw_state; + +/* Structure to encapsulate required arguments for + * initialization of SP DMEM using the SP itself + */ +struct ia_css_sp_init_dmem_cfg { + ia_css_ptr ddr_data_addr; /** data segment address in ddr */ + u32 dmem_data_addr; /** data segment address in dmem */ + u32 dmem_bss_addr; /** bss segment address in dmem */ + u32 data_size; /** data segment size */ + u32 bss_size; /** bss segment size */ + sp_ID_t sp_id; /* = N_SP_ID) || (!spctrl_cfg)) + return -EINVAL; + + spctrl_cofig_info[sp_id].code_addr = mmgr_NULL; + + init_dmem_cfg = &spctrl_cofig_info[sp_id].dmem_config; + init_dmem_cfg->dmem_data_addr = spctrl_cfg->dmem_data_addr; + init_dmem_cfg->dmem_bss_addr = spctrl_cfg->dmem_bss_addr; + init_dmem_cfg->data_size = spctrl_cfg->data_size; + init_dmem_cfg->bss_size = spctrl_cfg->bss_size; + init_dmem_cfg->sp_id = sp_id; + + spctrl_cofig_info[sp_id].spctrl_config_dmem_addr = + spctrl_cfg->spctrl_config_dmem_addr; + spctrl_cofig_info[sp_id].spctrl_state_dmem_addr = + spctrl_cfg->spctrl_state_dmem_addr; + + /* store code (text + icache) and data to DDR + * + * Data used to be stored separately, because of access alignment constraints, + * fix the FW generation instead + */ + code_addr = hmm_alloc(spctrl_cfg->code_size); + if (code_addr == mmgr_NULL) + return -ENOMEM; + hmm_store(code_addr, spctrl_cfg->code, spctrl_cfg->code_size); + + if (sizeof(ia_css_ptr) > sizeof(hrt_data)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "size of ia_css_ptr can not be greater than hrt_data\n"); + hmm_free(code_addr); + code_addr = mmgr_NULL; + return -EINVAL; + } + + init_dmem_cfg->ddr_data_addr = code_addr + spctrl_cfg->ddr_data_offset; + if ((init_dmem_cfg->ddr_data_addr % HIVE_ISP_DDR_WORD_BYTES) != 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "DDR address pointer is not properly aligned for DMA transfer\n"); + hmm_free(code_addr); + code_addr = mmgr_NULL; + return -EINVAL; + } + + spctrl_cofig_info[sp_id].sp_entry = spctrl_cfg->sp_entry; + spctrl_cofig_info[sp_id].code_addr = code_addr; + spctrl_cofig_info[sp_id].program_name = spctrl_cfg->program_name; + + /* now we program the base address into the icache and + * invalidate the cache. + */ + sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG, + (hrt_data)spctrl_cofig_info[sp_id].code_addr); + sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT); + spctrl_loaded[sp_id] = true; + return 0; +} + +/* ISP2401 */ +/* reload pre-loaded FW */ +void sh_css_spctrl_reload_fw(sp_ID_t sp_id) +{ + /* now we program the base address into the icache and + * invalidate the cache. + */ + sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG, + (hrt_data)spctrl_cofig_info[sp_id].code_addr); + sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT); + spctrl_loaded[sp_id] = true; +} + +ia_css_ptr get_sp_code_addr(sp_ID_t sp_id) +{ + return spctrl_cofig_info[sp_id].code_addr; +} + +int ia_css_spctrl_unload_fw(sp_ID_t sp_id) +{ + if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id]))) + return -EINVAL; + + /* freeup the resource */ + if (spctrl_cofig_info[sp_id].code_addr) { + hmm_free(spctrl_cofig_info[sp_id].code_addr); + spctrl_cofig_info[sp_id].code_addr = mmgr_NULL; + } + spctrl_loaded[sp_id] = false; + return 0; +} + +/* Initialize dmem_cfg in SP dmem and start SP program*/ +int ia_css_spctrl_start(sp_ID_t sp_id) +{ + if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id]))) + return -EINVAL; + + /* Set descr in the SP to initialize the SP DMEM */ + /* + * The FW stores user-space pointers to the FW, the ISP pointer + * is only available here + * + */ + assert(sizeof(unsigned int) <= sizeof(hrt_data)); + + sp_dmem_store(sp_id, + spctrl_cofig_info[sp_id].spctrl_config_dmem_addr, + &spctrl_cofig_info[sp_id].dmem_config, + sizeof(spctrl_cofig_info[sp_id].dmem_config)); + /* set the start address */ + sp_ctrl_store(sp_id, SP_START_ADDR_REG, + (hrt_data)spctrl_cofig_info[sp_id].sp_entry); + sp_ctrl_setbit(sp_id, SP_SC_REG, SP_RUN_BIT); + sp_ctrl_setbit(sp_id, SP_SC_REG, SP_START_BIT); + return 0; +} + +/* Query the state of SP1 */ +ia_css_spctrl_sp_sw_state ia_css_spctrl_get_state(sp_ID_t sp_id) +{ + ia_css_spctrl_sp_sw_state state = 0; + unsigned int HIVE_ADDR_sp_sw_state; + + if (sp_id >= N_SP_ID) + return IA_CSS_SP_SW_TERMINATED; + + HIVE_ADDR_sp_sw_state = spctrl_cofig_info[sp_id].spctrl_state_dmem_addr; + (void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */ + if (sp_id == SP0_ID) + state = sp_dmem_load_uint32(sp_id, (unsigned int)sp_address_of(sp_sw_state)); + return state; +} + +int ia_css_spctrl_is_idle(sp_ID_t sp_id) +{ + int state = 0; + + assert(sp_id < N_SP_ID); + + state = sp_ctrl_getbit(sp_id, SP_SC_REG, SP_IDLE_BIT); + return state; +} diff --git a/drivers/staging/media/atomisp/pci/runtime/tagger/interface/ia_css_tagger_common.h b/drivers/staging/media/atomisp/pci/runtime/tagger/interface/ia_css_tagger_common.h new file mode 100644 index 000000000..49801fbc1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/tagger/interface/ia_css_tagger_common.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TAGGER_COMMON_H__ +#define __IA_CSS_TAGGER_COMMON_H__ + +#include +#include + +/** + * @brief The tagger's circular buffer. + * + * Should be one less than NUM_CONTINUOUS_FRAMES in sh_css_internal.h + */ +#define MAX_CB_ELEMS_FOR_TAGGER 14 + +/** + * @brief Data structure for the tagger buffer element. + */ +typedef struct { + u32 frame; /* the frame value stored in the element */ + u32 param; /* the param value stored in the element */ + u8 mark; /* the mark on the element */ + u8 lock; /* the lock on the element */ + u8 exp_id; /* exp_id of frame, for debugging only */ +} ia_css_tagger_buf_sp_elem_t; + +#endif /* __IA_CSS_TAGGER_COMMON_H__ */ diff --git a/drivers/staging/media/atomisp/pci/runtime/timer/src/timer.c b/drivers/staging/media/atomisp/pci/runtime/timer/src/timer.c new file mode 100644 index 000000000..08f5c3ea6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/runtime/timer/src/timer.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for uint32_t */ +#include "ia_css_timer.h" /*struct ia_css_clock_tick */ +#include "sh_css_legacy.h" /* IA_CSS_PIPE_ID_NUM*/ +#include "gp_timer.h" /*gp_timer_read()*/ +#include "assert_support.h" + +int ia_css_timer_get_current_tick(struct ia_css_clock_tick *curr_ts) +{ + assert(curr_ts); + if (!curr_ts) + return -EINVAL; + curr_ts->ticks = (clock_value_t)gp_timer_read(GP_TIMER_SEL); + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/scalar_processor_2400_params.h b/drivers/staging/media/atomisp/pci/scalar_processor_2400_params.h new file mode 100644 index 000000000..7e7188797 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/scalar_processor_2400_params.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _scalar_processor_2400_params_h +#define _scalar_processor_2400_params_h + +#include "cell_params.h" + +#endif /* _scalar_processor_2400_params_h */ diff --git a/drivers/staging/media/atomisp/pci/sh_css.c b/drivers/staging/media/atomisp/pci/sh_css.c new file mode 100644 index 000000000..726cb7aa4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css.c @@ -0,0 +1,9372 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/*! \file */ +#include +#include +#include + +#include "hmm.h" + +#include "atomisp_internal.h" + +#include "ia_css.h" +#include "sh_css_hrt.h" /* only for file 2 MIPI */ +#include "ia_css_buffer.h" +#include "ia_css_binary.h" +#include "sh_css_internal.h" +#include "sh_css_mipi.h" +#include "sh_css_sp.h" /* sh_css_sp_group */ +#include "ia_css_isys.h" +#include "ia_css_frame.h" +#include "sh_css_defs.h" +#include "sh_css_firmware.h" +#include "sh_css_params.h" +#include "sh_css_params_internal.h" +#include "sh_css_param_shading.h" +#include "ia_css_refcount.h" +#include "ia_css_rmgr.h" +#include "ia_css_debug.h" +#include "ia_css_debug_pipe.h" +#include "ia_css_device_access.h" +#include "device_access.h" +#include "sh_css_legacy.h" +#include "ia_css_pipeline.h" +#include "ia_css_stream.h" +#include "sh_css_stream_format.h" +#include "ia_css_pipe.h" +#include "ia_css_util.h" +#include "ia_css_pipe_util.h" +#include "ia_css_pipe_binarydesc.h" +#include "ia_css_pipe_stagedesc.h" + +#include "tag.h" +#include "assert_support.h" +#include "math_support.h" +#include "sw_event_global.h" /* Event IDs.*/ +#if !defined(ISP2401) +#include "ia_css_ifmtr.h" +#endif +#include "input_system.h" +#include "mmu_device.h" /* mmu_set_page_table_base_index(), ... */ +#include "ia_css_mmu_private.h" /* sh_css_mmu_set_page_table_base_index() */ +#include "gdc_device.h" /* HRT_GDC_N */ +#include "dma.h" /* dma_set_max_burst_size() */ +#include "irq.h" /* virq */ +#include "sp.h" /* cnd_sp_irq_enable() */ +#include "isp.h" /* cnd_isp_irq_enable, ISP_VEC_NELEMS */ +#include "gp_device.h" /* gp_device_reg_store() */ +#define __INLINE_GPIO__ +#include "gpio.h" +#include "timed_ctrl.h" +#include "ia_css_inputfifo.h" +#define WITH_PC_MONITORING 0 + +#define SH_CSS_VIDEO_BUFFER_ALIGNMENT 0 + + +#include "ia_css_spctrl.h" +#include "ia_css_version_data.h" +#include "sh_css_struct.h" +#include "ia_css_bufq.h" +#include "ia_css_timer.h" /* clock_value_t */ + +#include "isp/modes/interface/input_buf.isp.h" + +/* Name of the sp program: should not be built-in */ +#define SP_PROG_NAME "sp" +/* Size of Refcount List */ +#define REFCOUNT_SIZE 1000 + +/* + * for JPEG, we don't know the length of the image upfront, + * but since we support sensor up to 16MP, we take this as + * upper limit. + */ +#define JPEG_BYTES (16 * 1024 * 1024) + +#define STATS_ENABLED(stage) (stage && stage->binary && stage->binary->info && \ + (stage->binary->info->sp.enable.s3a || stage->binary->info->sp.enable.dis)) + +struct sh_css my_css; + +int __printf(1, 0) (*sh_css_printf)(const char *fmt, va_list args) = NULL; + +/* + * modes of work: stream_create and stream_destroy will update the save/restore + * data only when in working mode, not suspend/resume + */ +enum ia_sh_css_modes { + sh_css_mode_none = 0, + sh_css_mode_working, + sh_css_mode_suspend, + sh_css_mode_resume +}; + +/** + * struct sh_css_stream_seed - a stream seed, to save and restore the + * stream data. + * + * @orig_stream: pointer to restore the original handle + * @stream: handle, used as ID too. + * @stream_config: stream config struct + * @num_pipes: number of pipes + * @pipes: pipe handles + * @orig_pipes: pointer to restore original handle + * @pipe_config: pipe config structs + * + * the stream seed contains all the data required to "grow" the seed again + * after it was closed. +*/ +struct sh_css_stream_seed { + struct ia_css_stream **orig_stream; + struct ia_css_stream *stream; + struct ia_css_stream_config stream_config; + int num_pipes; + struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM]; + struct ia_css_pipe **orig_pipes[IA_CSS_PIPE_ID_NUM]; + struct ia_css_pipe_config pipe_config[IA_CSS_PIPE_ID_NUM]; +}; + +#define MAX_ACTIVE_STREAMS 5 +/* + * A global struct for save/restore to hold all the data that should + * sustain power-down: MMU base, IRQ type, env for routines, binary loaded FW + * and the stream seeds. + */ +struct sh_css_save { + enum ia_sh_css_modes mode; + u32 mmu_base; /* the last mmu_base */ + enum ia_css_irq_type irq_type; + struct sh_css_stream_seed stream_seeds[MAX_ACTIVE_STREAMS]; + struct ia_css_fw *loaded_fw; /* fw struct previously loaded */ + struct ia_css_env driver_env; /* driver-supplied env copy */ +}; + +static bool my_css_save_initialized; /* if my_css_save was initialized */ +static struct sh_css_save my_css_save; + +/* + * pqiao NOTICE: this is for css internal buffer recycling when stopping + * pipeline, + * this array is temporary and will be replaced by resource manager + */ + +/* Taking the biggest Size for number of Elements */ +#define MAX_HMM_BUFFER_NUM \ + (SH_CSS_MAX_NUM_QUEUES * (IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE + 2)) + +struct sh_css_hmm_buffer_record { + bool in_use; + enum ia_css_buffer_type type; + struct ia_css_rmgr_vbuf_handle *h_vbuf; + hrt_address kernel_ptr; +}; + +static struct sh_css_hmm_buffer_record hmm_buffer_record[MAX_HMM_BUFFER_NUM]; + +#define GPIO_FLASH_PIN_MASK BIT(HIVE_GPIO_STROBE_TRIGGER_PIN) + +static bool fw_explicitly_loaded; + +/* + * Local prototypes + */ + +static int +allocate_delay_frames(struct ia_css_pipe *pipe); + +static int +sh_css_pipe_start(struct ia_css_stream *stream); + +/* + * @brief Check if all "ia_css_pipe" instances in the target + * "ia_css_stream" instance have stopped. + * + * @param[in] stream Point to the target "ia_css_stream" instance. + * + * @return + * - true, if all "ia_css_pipe" instances in the target "ia_css_stream" + * instance have ben stopped. + * - false, otherwise. + */ + +/* ISP 2401 */ +static int +ia_css_pipe_check_format(struct ia_css_pipe *pipe, + enum ia_css_frame_format format); + +/* ISP 2401 */ +static void +ia_css_reset_defaults(struct sh_css *css); + +static void +sh_css_init_host_sp_control_vars(void); + +static int +set_num_primary_stages(unsigned int *num, enum ia_css_pipe_version version); + +static bool +need_capture_pp(const struct ia_css_pipe *pipe); + +static bool +need_yuv_scaler_stage(const struct ia_css_pipe *pipe); + +static int ia_css_pipe_create_cas_scaler_desc_single_output( + struct ia_css_frame_info *cas_scaler_in_info, + struct ia_css_frame_info *cas_scaler_out_info, + struct ia_css_frame_info *cas_scaler_vf_info, + struct ia_css_cas_binary_descr *descr); + +static void ia_css_pipe_destroy_cas_scaler_desc(struct ia_css_cas_binary_descr + *descr); + +static bool +need_downscaling(const struct ia_css_resolution in_res, + const struct ia_css_resolution out_res); + +static bool need_capt_ldc(const struct ia_css_pipe *pipe); + +static int +sh_css_pipe_load_binaries(struct ia_css_pipe *pipe); + +static +int sh_css_pipe_get_viewfinder_frame_info( + struct ia_css_pipe *pipe, + struct ia_css_frame_info *info, + unsigned int idx); + +static int +sh_css_pipe_get_output_frame_info(struct ia_css_pipe *pipe, + struct ia_css_frame_info *info, + unsigned int idx); + +static int +capture_start(struct ia_css_pipe *pipe); + +static int +video_start(struct ia_css_pipe *pipe); + +static int +preview_start(struct ia_css_pipe *pipe); + +static int +yuvpp_start(struct ia_css_pipe *pipe); + +static bool copy_on_sp(struct ia_css_pipe *pipe); + +static int +init_vf_frameinfo_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *vf_frame, unsigned int idx); + +static int +init_in_frameinfo_memory_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *frame, enum ia_css_frame_format format); + +static int +init_out_frameinfo_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *out_frame, unsigned int idx); + +static int +alloc_continuous_frames(struct ia_css_pipe *pipe, bool init_time); + +static void +pipe_global_init(void); + +static int +pipe_generate_pipe_num(const struct ia_css_pipe *pipe, + unsigned int *pipe_number); + +static void +pipe_release_pipe_num(unsigned int pipe_num); + +static int +create_host_pipeline_structure(struct ia_css_stream *stream); + +static int +create_host_pipeline(struct ia_css_stream *stream); + +static int +create_host_preview_pipeline(struct ia_css_pipe *pipe); + +static int +create_host_video_pipeline(struct ia_css_pipe *pipe); + +static int +create_host_copy_pipeline(struct ia_css_pipe *pipe, + unsigned int max_input_width, + struct ia_css_frame *out_frame); + +static int +create_host_isyscopy_capture_pipeline(struct ia_css_pipe *pipe); + +static int +create_host_capture_pipeline(struct ia_css_pipe *pipe); + +static int +create_host_yuvpp_pipeline(struct ia_css_pipe *pipe); + +static unsigned int +sh_css_get_sw_interrupt_value(unsigned int irq); + +static struct ia_css_binary *ia_css_pipe_get_shading_correction_binary( + const struct ia_css_pipe *pipe); + +static struct ia_css_binary * +ia_css_pipe_get_s3a_binary(const struct ia_css_pipe *pipe); + +static struct ia_css_binary * +ia_css_pipe_get_sdis_binary(const struct ia_css_pipe *pipe); + +static void +sh_css_hmm_buffer_record_init(void); + +static void +sh_css_hmm_buffer_record_uninit(void); + +static void +sh_css_hmm_buffer_record_reset(struct sh_css_hmm_buffer_record *buffer_record); + +static struct sh_css_hmm_buffer_record +*sh_css_hmm_buffer_record_acquire(struct ia_css_rmgr_vbuf_handle *h_vbuf, + enum ia_css_buffer_type type, + hrt_address kernel_ptr); + +static struct sh_css_hmm_buffer_record +*sh_css_hmm_buffer_record_validate(ia_css_ptr ddr_buffer_addr, + enum ia_css_buffer_type type); + +#ifdef ISP2401 +static unsigned int get_crop_lines_for_bayer_order(const struct + ia_css_stream_config *config); +static unsigned int get_crop_columns_for_bayer_order(const struct + ia_css_stream_config *config); +static void get_pipe_extra_pixel(struct ia_css_pipe *pipe, + unsigned int *extra_row, unsigned int *extra_column); + +#endif + +static void +sh_css_pipe_free_shading_table(struct ia_css_pipe *pipe) +{ + if (!pipe) { + IA_CSS_ERROR("NULL input parameter"); + return; + } + + if (pipe->shading_table) + ia_css_shading_table_free(pipe->shading_table); + pipe->shading_table = NULL; +} + +static enum ia_css_frame_format yuv420_copy_formats[] = { + IA_CSS_FRAME_FORMAT_NV12, + IA_CSS_FRAME_FORMAT_NV21, + IA_CSS_FRAME_FORMAT_YV12, + IA_CSS_FRAME_FORMAT_YUV420, + IA_CSS_FRAME_FORMAT_YUV420_16, + IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8, + IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8 +}; + +static enum ia_css_frame_format yuv422_copy_formats[] = { + IA_CSS_FRAME_FORMAT_NV12, + IA_CSS_FRAME_FORMAT_NV16, + IA_CSS_FRAME_FORMAT_NV21, + IA_CSS_FRAME_FORMAT_NV61, + IA_CSS_FRAME_FORMAT_YV12, + IA_CSS_FRAME_FORMAT_YV16, + IA_CSS_FRAME_FORMAT_YUV420, + IA_CSS_FRAME_FORMAT_YUV420_16, + IA_CSS_FRAME_FORMAT_YUV422, + IA_CSS_FRAME_FORMAT_YUV422_16, + IA_CSS_FRAME_FORMAT_UYVY, + IA_CSS_FRAME_FORMAT_YUYV +}; + +/* + * Verify whether the selected output format is can be produced + * by the copy binary given the stream format. + */ +static int +verify_copy_out_frame_format(struct ia_css_pipe *pipe) +{ + enum ia_css_frame_format out_fmt = pipe->output_info[0].format; + unsigned int i, found = 0; + + assert(pipe); + assert(pipe->stream); + + switch (pipe->stream->config.input_config.format) { + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: + case ATOMISP_INPUT_FORMAT_YUV420_8: + for (i = 0; i < ARRAY_SIZE(yuv420_copy_formats) && !found; i++) + found = (out_fmt == yuv420_copy_formats[i]); + break; + case ATOMISP_INPUT_FORMAT_YUV420_10: + case ATOMISP_INPUT_FORMAT_YUV420_16: + found = (out_fmt == IA_CSS_FRAME_FORMAT_YUV420_16); + break; + case ATOMISP_INPUT_FORMAT_YUV422_8: + for (i = 0; i < ARRAY_SIZE(yuv422_copy_formats) && !found; i++) + found = (out_fmt == yuv422_copy_formats[i]); + break; + case ATOMISP_INPUT_FORMAT_YUV422_10: + case ATOMISP_INPUT_FORMAT_YUV422_16: + found = (out_fmt == IA_CSS_FRAME_FORMAT_YUV422_16 || + out_fmt == IA_CSS_FRAME_FORMAT_YUV420_16); + break; + case ATOMISP_INPUT_FORMAT_RGB_444: + case ATOMISP_INPUT_FORMAT_RGB_555: + case ATOMISP_INPUT_FORMAT_RGB_565: + found = (out_fmt == IA_CSS_FRAME_FORMAT_RGBA888 || + out_fmt == IA_CSS_FRAME_FORMAT_RGB565); + break; + case ATOMISP_INPUT_FORMAT_RGB_666: + case ATOMISP_INPUT_FORMAT_RGB_888: + found = (out_fmt == IA_CSS_FRAME_FORMAT_RGBA888 || + out_fmt == IA_CSS_FRAME_FORMAT_YUV420); + break; + case ATOMISP_INPUT_FORMAT_RAW_6: + case ATOMISP_INPUT_FORMAT_RAW_7: + case ATOMISP_INPUT_FORMAT_RAW_8: + case ATOMISP_INPUT_FORMAT_RAW_10: + case ATOMISP_INPUT_FORMAT_RAW_12: + case ATOMISP_INPUT_FORMAT_RAW_14: + case ATOMISP_INPUT_FORMAT_RAW_16: + found = (out_fmt == IA_CSS_FRAME_FORMAT_RAW) || + (out_fmt == IA_CSS_FRAME_FORMAT_RAW_PACKED); + break; + case ATOMISP_INPUT_FORMAT_BINARY_8: + found = (out_fmt == IA_CSS_FRAME_FORMAT_BINARY_8); + break; + default: + break; + } + if (!found) + return -EINVAL; + return 0; +} + +unsigned int +ia_css_stream_input_format_bits_per_pixel(struct ia_css_stream *stream) +{ + int bpp = 0; + + if (stream) + bpp = ia_css_util_input_format_bpp(stream->config.input_config.format, + stream->config.pixels_per_clock == 2); + + return bpp; +} + +/* TODO: move define to proper file in tools */ +#define GP_ISEL_TPG_MODE 0x90058 + +#if !defined(ISP2401) +static int +sh_css_config_input_network(struct ia_css_stream *stream) +{ + unsigned int fmt_type; + struct ia_css_pipe *pipe = stream->last_pipe; + struct ia_css_binary *binary = NULL; + int err = 0; + + assert(stream); + assert(pipe); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_config_input_network() enter:\n"); + + if (pipe->pipeline.stages) + binary = pipe->pipeline.stages->binary; + + err = ia_css_isys_convert_stream_format_to_mipi_format( + stream->config.input_config.format, + stream->csi_rx_config.comp, + &fmt_type); + if (err) + return err; + sh_css_sp_program_input_circuit(fmt_type, + stream->config.channel_id, + stream->config.mode); + + if ((binary && (binary->online || stream->config.continuous)) || + pipe->config.mode == IA_CSS_PIPE_MODE_COPY) { + err = ia_css_ifmtr_configure(&stream->config, + binary); + if (err) + return err; + } + + if (stream->config.mode == IA_CSS_INPUT_MODE_TPG || + stream->config.mode == IA_CSS_INPUT_MODE_PRBS) { + unsigned int hblank_cycles = 100, + vblank_lines = 6, + width, + height, + vblank_cycles; + width = (stream->config.input_config.input_res.width) / (1 + + (stream->config.pixels_per_clock == 2)); + height = stream->config.input_config.input_res.height; + vblank_cycles = vblank_lines * (width + hblank_cycles); + sh_css_sp_configure_sync_gen(width, height, hblank_cycles, + vblank_cycles); + if (pipe->stream->config.mode == IA_CSS_INPUT_MODE_TPG) + ia_css_device_store_uint32(GP_ISEL_TPG_MODE, 0); + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_config_input_network() leave:\n"); + return 0; +} +#elif defined(ISP2401) +static unsigned int csi2_protocol_calculate_max_subpixels_per_line( + enum atomisp_input_format format, + unsigned int pixels_per_line) +{ + unsigned int rval; + + switch (format) { + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: + /* + * The frame format layout is shown below. + * + * Line 0: UYY0 UYY0 ... UYY0 + * Line 1: VYY0 VYY0 ... VYY0 + * Line 2: UYY0 UYY0 ... UYY0 + * Line 3: VYY0 VYY0 ... VYY0 + * ... + * Line (n-2): UYY0 UYY0 ... UYY0 + * Line (n-1): VYY0 VYY0 ... VYY0 + * + * In this frame format, the even-line is + * as wide as the odd-line. + * The 0 is introduced by the input system + * (mipi backend). + */ + rval = pixels_per_line * 2; + break; + case ATOMISP_INPUT_FORMAT_YUV420_8: + case ATOMISP_INPUT_FORMAT_YUV420_10: + case ATOMISP_INPUT_FORMAT_YUV420_16: + /* + * The frame format layout is shown below. + * + * Line 0: YYYY YYYY ... YYYY + * Line 1: UYVY UYVY ... UYVY UYVY + * Line 2: YYYY YYYY ... YYYY + * Line 3: UYVY UYVY ... UYVY UYVY + * ... + * Line (n-2): YYYY YYYY ... YYYY + * Line (n-1): UYVY UYVY ... UYVY UYVY + * + * In this frame format, the odd-line is twice + * wider than the even-line. + */ + rval = pixels_per_line * 2; + break; + case ATOMISP_INPUT_FORMAT_YUV422_8: + case ATOMISP_INPUT_FORMAT_YUV422_10: + case ATOMISP_INPUT_FORMAT_YUV422_16: + /* + * The frame format layout is shown below. + * + * Line 0: UYVY UYVY ... UYVY + * Line 1: UYVY UYVY ... UYVY + * Line 2: UYVY UYVY ... UYVY + * Line 3: UYVY UYVY ... UYVY + * ... + * Line (n-2): UYVY UYVY ... UYVY + * Line (n-1): UYVY UYVY ... UYVY + * + * In this frame format, the even-line is + * as wide as the odd-line. + */ + rval = pixels_per_line * 2; + break; + case ATOMISP_INPUT_FORMAT_RGB_444: + case ATOMISP_INPUT_FORMAT_RGB_555: + case ATOMISP_INPUT_FORMAT_RGB_565: + case ATOMISP_INPUT_FORMAT_RGB_666: + case ATOMISP_INPUT_FORMAT_RGB_888: + /* + * The frame format layout is shown below. + * + * Line 0: ABGR ABGR ... ABGR + * Line 1: ABGR ABGR ... ABGR + * Line 2: ABGR ABGR ... ABGR + * Line 3: ABGR ABGR ... ABGR + * ... + * Line (n-2): ABGR ABGR ... ABGR + * Line (n-1): ABGR ABGR ... ABGR + * + * In this frame format, the even-line is + * as wide as the odd-line. + */ + rval = pixels_per_line * 4; + break; + case ATOMISP_INPUT_FORMAT_RAW_6: + case ATOMISP_INPUT_FORMAT_RAW_7: + case ATOMISP_INPUT_FORMAT_RAW_8: + case ATOMISP_INPUT_FORMAT_RAW_10: + case ATOMISP_INPUT_FORMAT_RAW_12: + case ATOMISP_INPUT_FORMAT_RAW_14: + case ATOMISP_INPUT_FORMAT_RAW_16: + case ATOMISP_INPUT_FORMAT_BINARY_8: + case ATOMISP_INPUT_FORMAT_USER_DEF1: + case ATOMISP_INPUT_FORMAT_USER_DEF2: + case ATOMISP_INPUT_FORMAT_USER_DEF3: + case ATOMISP_INPUT_FORMAT_USER_DEF4: + case ATOMISP_INPUT_FORMAT_USER_DEF5: + case ATOMISP_INPUT_FORMAT_USER_DEF6: + case ATOMISP_INPUT_FORMAT_USER_DEF7: + case ATOMISP_INPUT_FORMAT_USER_DEF8: + /* + * The frame format layout is shown below. + * + * Line 0: Pixel ... Pixel + * Line 1: Pixel ... Pixel + * Line 2: Pixel ... Pixel + * Line 3: Pixel ... Pixel + * ... + * Line (n-2): Pixel ... Pixel + * Line (n-1): Pixel ... Pixel + * + * In this frame format, the even-line is + * as wide as the odd-line. + */ + rval = pixels_per_line; + break; + default: + rval = 0; + break; + } + + return rval; +} + +static bool sh_css_translate_stream_cfg_to_input_system_input_port_id( + struct ia_css_stream_config *stream_cfg, + ia_css_isys_descr_t *isys_stream_descr) +{ + bool rc; + + rc = true; + switch (stream_cfg->mode) { + case IA_CSS_INPUT_MODE_TPG: + + if (stream_cfg->source.tpg.id == IA_CSS_TPG_ID0) + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT0_ID; + else if (stream_cfg->source.tpg.id == IA_CSS_TPG_ID1) + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT1_ID; + else if (stream_cfg->source.tpg.id == IA_CSS_TPG_ID2) + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT2_ID; + + break; + case IA_CSS_INPUT_MODE_PRBS: + + if (stream_cfg->source.prbs.id == IA_CSS_PRBS_ID0) + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT0_ID; + else if (stream_cfg->source.prbs.id == IA_CSS_PRBS_ID1) + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT1_ID; + else if (stream_cfg->source.prbs.id == IA_CSS_PRBS_ID2) + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT2_ID; + + break; + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: + + if (stream_cfg->source.port.port == MIPI_PORT0_ID) + isys_stream_descr->input_port_id = INPUT_SYSTEM_CSI_PORT0_ID; + else if (stream_cfg->source.port.port == MIPI_PORT1_ID) + isys_stream_descr->input_port_id = INPUT_SYSTEM_CSI_PORT1_ID; + else if (stream_cfg->source.port.port == MIPI_PORT2_ID) + isys_stream_descr->input_port_id = INPUT_SYSTEM_CSI_PORT2_ID; + + break; + default: + rc = false; + break; + } + + return rc; +} + +static bool sh_css_translate_stream_cfg_to_input_system_input_port_type( + struct ia_css_stream_config *stream_cfg, + ia_css_isys_descr_t *isys_stream_descr) +{ + bool rc; + + rc = true; + switch (stream_cfg->mode) { + case IA_CSS_INPUT_MODE_TPG: + + isys_stream_descr->mode = INPUT_SYSTEM_SOURCE_TYPE_TPG; + + break; + case IA_CSS_INPUT_MODE_PRBS: + + isys_stream_descr->mode = INPUT_SYSTEM_SOURCE_TYPE_PRBS; + + break; + case IA_CSS_INPUT_MODE_SENSOR: + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: + + isys_stream_descr->mode = INPUT_SYSTEM_SOURCE_TYPE_SENSOR; + break; + + default: + rc = false; + break; + } + + return rc; +} + +static bool sh_css_translate_stream_cfg_to_input_system_input_port_attr( + struct ia_css_stream_config *stream_cfg, + ia_css_isys_descr_t *isys_stream_descr, + int isys_stream_idx) +{ + bool rc; + + rc = true; + switch (stream_cfg->mode) { + case IA_CSS_INPUT_MODE_TPG: + if (stream_cfg->source.tpg.mode == IA_CSS_TPG_MODE_RAMP) + isys_stream_descr->tpg_port_attr.mode = PIXELGEN_TPG_MODE_RAMP; + else if (stream_cfg->source.tpg.mode == IA_CSS_TPG_MODE_CHECKERBOARD) + isys_stream_descr->tpg_port_attr.mode = PIXELGEN_TPG_MODE_CHBO; + else if (stream_cfg->source.tpg.mode == IA_CSS_TPG_MODE_MONO) + isys_stream_descr->tpg_port_attr.mode = PIXELGEN_TPG_MODE_MONO; + else + rc = false; + + /* + * TODO + * - Make "color_cfg" as part of "ia_css_tpg_config". + */ + isys_stream_descr->tpg_port_attr.color_cfg.R1 = 51; + isys_stream_descr->tpg_port_attr.color_cfg.G1 = 102; + isys_stream_descr->tpg_port_attr.color_cfg.B1 = 255; + isys_stream_descr->tpg_port_attr.color_cfg.R2 = 0; + isys_stream_descr->tpg_port_attr.color_cfg.G2 = 100; + isys_stream_descr->tpg_port_attr.color_cfg.B2 = 160; + + isys_stream_descr->tpg_port_attr.mask_cfg.h_mask = + stream_cfg->source.tpg.x_mask; + isys_stream_descr->tpg_port_attr.mask_cfg.v_mask = + stream_cfg->source.tpg.y_mask; + isys_stream_descr->tpg_port_attr.mask_cfg.hv_mask = + stream_cfg->source.tpg.xy_mask; + + isys_stream_descr->tpg_port_attr.delta_cfg.h_delta = + stream_cfg->source.tpg.x_delta; + isys_stream_descr->tpg_port_attr.delta_cfg.v_delta = + stream_cfg->source.tpg.y_delta; + + /* + * TODO + * - Make "sync_gen_cfg" as part of "ia_css_tpg_config". + */ + isys_stream_descr->tpg_port_attr.sync_gen_cfg.hblank_cycles = 100; + isys_stream_descr->tpg_port_attr.sync_gen_cfg.vblank_cycles = 100; + isys_stream_descr->tpg_port_attr.sync_gen_cfg.pixels_per_clock = + stream_cfg->pixels_per_clock; + isys_stream_descr->tpg_port_attr.sync_gen_cfg.nr_of_frames = (uint32_t)~(0x0); + isys_stream_descr->tpg_port_attr.sync_gen_cfg.pixels_per_line = + stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.width; + isys_stream_descr->tpg_port_attr.sync_gen_cfg.lines_per_frame = + stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.height; + + break; + case IA_CSS_INPUT_MODE_PRBS: + + isys_stream_descr->prbs_port_attr.seed0 = stream_cfg->source.prbs.seed; + isys_stream_descr->prbs_port_attr.seed1 = stream_cfg->source.prbs.seed1; + + /* + * TODO + * - Make "sync_gen_cfg" as part of "ia_css_prbs_config". + */ + isys_stream_descr->prbs_port_attr.sync_gen_cfg.hblank_cycles = 100; + isys_stream_descr->prbs_port_attr.sync_gen_cfg.vblank_cycles = 100; + isys_stream_descr->prbs_port_attr.sync_gen_cfg.pixels_per_clock = + stream_cfg->pixels_per_clock; + isys_stream_descr->prbs_port_attr.sync_gen_cfg.nr_of_frames = (uint32_t)~(0x0); + isys_stream_descr->prbs_port_attr.sync_gen_cfg.pixels_per_line = + stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.width; + isys_stream_descr->prbs_port_attr.sync_gen_cfg.lines_per_frame = + stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.height; + + break; + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: { + int err; + unsigned int fmt_type; + + err = ia_css_isys_convert_stream_format_to_mipi_format( + stream_cfg->isys_config[isys_stream_idx].format, + MIPI_PREDICTOR_NONE, + &fmt_type); + if (err) + rc = false; + + isys_stream_descr->csi_port_attr.active_lanes = + stream_cfg->source.port.num_lanes; + isys_stream_descr->csi_port_attr.fmt_type = fmt_type; + isys_stream_descr->csi_port_attr.ch_id = stream_cfg->channel_id; +#ifdef ISP2401 + isys_stream_descr->online = stream_cfg->online; +#endif + err |= ia_css_isys_convert_compressed_format( + &stream_cfg->source.port.compression, + isys_stream_descr); + if (err) + rc = false; + + /* metadata */ + isys_stream_descr->metadata.enable = false; + if (stream_cfg->metadata_config.resolution.height > 0) { + err = ia_css_isys_convert_stream_format_to_mipi_format( + stream_cfg->metadata_config.data_type, + MIPI_PREDICTOR_NONE, + &fmt_type); + if (err) + rc = false; + isys_stream_descr->metadata.fmt_type = fmt_type; + isys_stream_descr->metadata.bits_per_pixel = + ia_css_util_input_format_bpp(stream_cfg->metadata_config.data_type, true); + isys_stream_descr->metadata.pixels_per_line = + stream_cfg->metadata_config.resolution.width; + isys_stream_descr->metadata.lines_per_frame = + stream_cfg->metadata_config.resolution.height; +#ifdef ISP2401 + /* + * For new input system, number of str2mmio requests must be even. + * So we round up number of metadata lines to be even. + */ + if (isys_stream_descr->metadata.lines_per_frame > 0) + isys_stream_descr->metadata.lines_per_frame += + (isys_stream_descr->metadata.lines_per_frame & 1); +#endif + isys_stream_descr->metadata.align_req_in_bytes = + ia_css_csi2_calculate_input_system_alignment( + stream_cfg->metadata_config.data_type); + isys_stream_descr->metadata.enable = true; + } + + break; + } + default: + rc = false; + break; + } + + return rc; +} + +static bool sh_css_translate_stream_cfg_to_input_system_input_port_resolution( + struct ia_css_stream_config *stream_cfg, + ia_css_isys_descr_t *isys_stream_descr, + int isys_stream_idx) +{ + unsigned int bits_per_subpixel; + unsigned int max_subpixels_per_line; + unsigned int lines_per_frame; + unsigned int align_req_in_bytes; + enum atomisp_input_format fmt_type; + + fmt_type = stream_cfg->isys_config[isys_stream_idx].format; + if ((stream_cfg->mode == IA_CSS_INPUT_MODE_SENSOR || + stream_cfg->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) && + stream_cfg->source.port.compression.type != IA_CSS_CSI2_COMPRESSION_TYPE_NONE) { + if (stream_cfg->source.port.compression.uncompressed_bits_per_pixel == + UNCOMPRESSED_BITS_PER_PIXEL_10) + fmt_type = ATOMISP_INPUT_FORMAT_RAW_10; + else if (stream_cfg->source.port.compression.uncompressed_bits_per_pixel == + UNCOMPRESSED_BITS_PER_PIXEL_12) + fmt_type = ATOMISP_INPUT_FORMAT_RAW_12; + else + return false; + } + + bits_per_subpixel = + sh_css_stream_format_2_bits_per_subpixel(fmt_type); + if (bits_per_subpixel == 0) + return false; + + max_subpixels_per_line = + csi2_protocol_calculate_max_subpixels_per_line(fmt_type, + stream_cfg->isys_config[isys_stream_idx].input_res.width); + if (max_subpixels_per_line == 0) + return false; + + lines_per_frame = stream_cfg->isys_config[isys_stream_idx].input_res.height; + if (lines_per_frame == 0) + return false; + + align_req_in_bytes = ia_css_csi2_calculate_input_system_alignment(fmt_type); + + /* HW needs subpixel info for their settings */ + isys_stream_descr->input_port_resolution.bits_per_pixel = bits_per_subpixel; + isys_stream_descr->input_port_resolution.pixels_per_line = + max_subpixels_per_line; + isys_stream_descr->input_port_resolution.lines_per_frame = lines_per_frame; + isys_stream_descr->input_port_resolution.align_req_in_bytes = + align_req_in_bytes; + + return true; +} + +static bool sh_css_translate_stream_cfg_to_isys_stream_descr( + struct ia_css_stream_config *stream_cfg, + bool early_polling, + ia_css_isys_descr_t *isys_stream_descr, + int isys_stream_idx) +{ + bool rc; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_translate_stream_cfg_to_isys_stream_descr() enter:\n"); + rc = sh_css_translate_stream_cfg_to_input_system_input_port_id(stream_cfg, + isys_stream_descr); + rc &= sh_css_translate_stream_cfg_to_input_system_input_port_type(stream_cfg, + isys_stream_descr); + rc &= sh_css_translate_stream_cfg_to_input_system_input_port_attr(stream_cfg, + isys_stream_descr, isys_stream_idx); + rc &= sh_css_translate_stream_cfg_to_input_system_input_port_resolution( + stream_cfg, isys_stream_descr, isys_stream_idx); + + isys_stream_descr->raw_packed = stream_cfg->pack_raw_pixels; + isys_stream_descr->linked_isys_stream_id = (int8_t) + stream_cfg->isys_config[isys_stream_idx].linked_isys_stream_id; + + if (IS_ISP2401) + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_translate_stream_cfg_to_isys_stream_descr() leave:\n"); + + return rc; +} + +static bool sh_css_translate_binary_info_to_input_system_output_port_attr( + struct ia_css_binary *binary, + ia_css_isys_descr_t *isys_stream_descr) +{ + if (!binary) + return false; + + isys_stream_descr->output_port_attr.left_padding = binary->left_padding; + isys_stream_descr->output_port_attr.max_isp_input_width = + binary->info->sp.input.max_width; + + return true; +} + +static int +sh_css_config_input_network(struct ia_css_stream *stream) +{ + bool rc; + ia_css_isys_descr_t isys_stream_descr; + unsigned int sp_thread_id; + struct sh_css_sp_pipeline_terminal *sp_pipeline_input_terminal; + struct ia_css_pipe *pipe = NULL; + struct ia_css_binary *binary = NULL; + int i; + u32 isys_stream_id; + bool early_polling = false; + + assert(stream); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_config_input_network() enter 0x%p:\n", stream); + + if (stream->config.continuous) { + if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_CAPTURE) + pipe = stream->last_pipe; + else if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_YUVPP) + pipe = stream->last_pipe; + else if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_PREVIEW) + pipe = stream->last_pipe->pipe_settings.preview.copy_pipe; + else if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_VIDEO) + pipe = stream->last_pipe->pipe_settings.video.copy_pipe; + } else { + pipe = stream->last_pipe; + } + + if (!pipe) + return -EINVAL; + + if (pipe->pipeline.stages) + if (pipe->pipeline.stages->binary) + binary = pipe->pipeline.stages->binary; + + if (binary) { + /* + * this was being done in ifmtr in 2400. + * online and cont bypass the init_in_frameinfo_memory_defaults + * so need to do it here + */ + ia_css_get_crop_offsets(pipe, &binary->in_frame_info); + } + + /* get the SP thread id */ + rc = ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &sp_thread_id); + if (!rc) + return -EINVAL; + /* get the target input terminal */ + sp_pipeline_input_terminal = &sh_css_sp_group.pipe_io[sp_thread_id].input; + + for (i = 0; i < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; i++) { + /* initialization */ + memset((void *)(&isys_stream_descr), 0, sizeof(ia_css_isys_descr_t)); + sp_pipeline_input_terminal->context.virtual_input_system_stream[i].valid = 0; + sp_pipeline_input_terminal->ctrl.virtual_input_system_stream_cfg[i].valid = 0; + + if (!stream->config.isys_config[i].valid) + continue; + + /* translate the stream configuration to the Input System (2401) configuration */ + rc = sh_css_translate_stream_cfg_to_isys_stream_descr( + &stream->config, + early_polling, + &(isys_stream_descr), i); + + if (stream->config.online) { + rc &= sh_css_translate_binary_info_to_input_system_output_port_attr( + binary, + &(isys_stream_descr)); + } + + if (!rc) + return -EINVAL; + + isys_stream_id = ia_css_isys_generate_stream_id(sp_thread_id, i); + + /* create the virtual Input System (2401) */ + rc = ia_css_isys_stream_create( + &(isys_stream_descr), + &sp_pipeline_input_terminal->context.virtual_input_system_stream[i], + isys_stream_id); + if (!rc) + return -EINVAL; + + /* calculate the configuration of the virtual Input System (2401) */ + rc = ia_css_isys_stream_calculate_cfg( + &sp_pipeline_input_terminal->context.virtual_input_system_stream[i], + &(isys_stream_descr), + &sp_pipeline_input_terminal->ctrl.virtual_input_system_stream_cfg[i]); + if (!rc) { + ia_css_isys_stream_destroy( + &sp_pipeline_input_terminal->context.virtual_input_system_stream[i]); + return -EINVAL; + } + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_config_input_network() leave:\n"); + + return 0; +} + +static inline struct ia_css_pipe *stream_get_last_pipe( + struct ia_css_stream *stream) +{ + struct ia_css_pipe *last_pipe = NULL; + + if (stream) + last_pipe = stream->last_pipe; + + return last_pipe; +} + +static inline struct ia_css_pipe *stream_get_copy_pipe( + struct ia_css_stream *stream) +{ + struct ia_css_pipe *copy_pipe = NULL; + struct ia_css_pipe *last_pipe = NULL; + enum ia_css_pipe_id pipe_id; + + last_pipe = stream_get_last_pipe(stream); + + if ((stream) && + (last_pipe) && + (stream->config.continuous)) { + pipe_id = last_pipe->mode; + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + copy_pipe = last_pipe->pipe_settings.preview.copy_pipe; + break; + case IA_CSS_PIPE_ID_VIDEO: + copy_pipe = last_pipe->pipe_settings.video.copy_pipe; + break; + default: + copy_pipe = NULL; + break; + } + } + + return copy_pipe; +} + +static inline struct ia_css_pipe *stream_get_target_pipe( + struct ia_css_stream *stream) +{ + struct ia_css_pipe *target_pipe; + + /* get the pipe that consumes the stream */ + if (stream->config.continuous) + target_pipe = stream_get_copy_pipe(stream); + else + target_pipe = stream_get_last_pipe(stream); + + return target_pipe; +} + +static int stream_csi_rx_helper( + struct ia_css_stream *stream, + int (*func)(enum mipi_port_id, uint32_t)) +{ + int retval = -EINVAL; + u32 sp_thread_id, stream_id; + bool rc; + struct ia_css_pipe *target_pipe = NULL; + + if ((!stream) || (stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR)) + goto exit; + + target_pipe = stream_get_target_pipe(stream); + + if (!target_pipe) + goto exit; + + rc = ia_css_pipeline_get_sp_thread_id( + ia_css_pipe_get_pipe_num(target_pipe), + &sp_thread_id); + + if (!rc) + goto exit; + + /* (un)register all valid "virtual isys streams" within the ia_css_stream */ + stream_id = 0; + do { + if (stream->config.isys_config[stream_id].valid) { + u32 isys_stream_id = ia_css_isys_generate_stream_id(sp_thread_id, stream_id); + + retval = func(stream->config.source.port.port, isys_stream_id); + } + stream_id++; + } while ((retval == 0) && + (stream_id < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH)); + +exit: + return retval; +} + +static inline int stream_register_with_csi_rx( + struct ia_css_stream *stream) +{ + return stream_csi_rx_helper(stream, ia_css_isys_csi_rx_register_stream); +} + +static inline int stream_unregister_with_csi_rx( + struct ia_css_stream *stream) +{ + return stream_csi_rx_helper(stream, ia_css_isys_csi_rx_unregister_stream); +} +#endif + + +static void +start_binary(struct ia_css_pipe *pipe, + struct ia_css_binary *binary) +{ + assert(pipe); + /* Acceleration uses firmware, the binary thus can be NULL */ + + if (binary) + sh_css_metrics_start_binary(&binary->metrics); + + +#if !defined(ISP2401) + if (pipe->stream->reconfigure_css_rx) { + ia_css_isys_rx_configure(&pipe->stream->csi_rx_config, + pipe->stream->config.mode); + pipe->stream->reconfigure_css_rx = false; + } +#endif +} + +/* start the copy function on the SP */ +static int +start_copy_on_sp(struct ia_css_pipe *pipe, + struct ia_css_frame *out_frame) +{ + (void)out_frame; + + if ((!pipe) || (!pipe->stream)) + return -EINVAL; + +#if !defined(ISP2401) + if (pipe->stream->reconfigure_css_rx) + ia_css_isys_rx_disable(); +#endif + + if (pipe->stream->config.input_config.format != ATOMISP_INPUT_FORMAT_BINARY_8) + return -EINVAL; + sh_css_sp_start_binary_copy(ia_css_pipe_get_pipe_num(pipe), out_frame, pipe->stream->config.pixels_per_clock == 2); + +#if !defined(ISP2401) + if (pipe->stream->reconfigure_css_rx) { + ia_css_isys_rx_configure(&pipe->stream->csi_rx_config, + pipe->stream->config.mode); + pipe->stream->reconfigure_css_rx = false; + } +#endif + + return 0; +} + +void sh_css_binary_args_reset(struct sh_css_binary_args *args) +{ + unsigned int i; + + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) + args->tnr_frames[i] = NULL; + for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) + args->delay_frames[i] = NULL; + args->in_frame = NULL; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + args->out_frame[i] = NULL; + args->out_vf_frame = NULL; + args->copy_vf = false; + args->copy_output = true; + args->vf_downscale_log2 = 0; +} + +static void start_pipe( + struct ia_css_pipe *me, + enum sh_css_pipe_config_override copy_ovrd, + enum ia_css_input_mode input_mode) +{ + IA_CSS_ENTER_PRIVATE("me = %p, copy_ovrd = %d, input_mode = %d", + me, copy_ovrd, input_mode); + + assert(me); /* all callers are in this file and call with non null argument */ + + sh_css_sp_init_pipeline(&me->pipeline, + me->mode, + (uint8_t)ia_css_pipe_get_pipe_num(me), + me->config.default_capture_config.enable_xnr != 0, + me->stream->config.pixels_per_clock == 2, + me->stream->config.continuous, + false, + me->required_bds_factor, + copy_ovrd, + input_mode, + &me->stream->config.metadata_config, + &me->stream->info.metadata_info + , (input_mode == IA_CSS_INPUT_MODE_MEMORY) ? + (enum mipi_port_id)0 : + me->stream->config.source.port.port); + + if (me->config.mode != IA_CSS_PIPE_MODE_COPY) { + struct ia_css_pipeline_stage *stage; + + stage = me->pipeline.stages; + if (stage) { + me->pipeline.current_stage = stage; + start_binary(me, stage->binary); + } + } + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +sh_css_invalidate_shading_tables(struct ia_css_stream *stream) +{ + int i; + + assert(stream); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_invalidate_shading_tables() enter:\n"); + + for (i = 0; i < stream->num_pipes; i++) { + assert(stream->pipes[i]); + sh_css_pipe_free_shading_table(stream->pipes[i]); + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_invalidate_shading_tables() leave: return_void\n"); +} + +static void +enable_interrupts(enum ia_css_irq_type irq_type) +{ +#ifndef ISP2401 + enum mipi_port_id port; +#endif + bool enable_pulse = irq_type != IA_CSS_IRQ_TYPE_EDGE; + + IA_CSS_ENTER_PRIVATE(""); + /* Enable IRQ on the SP which signals that SP goes to idle + * (aka ready state) */ + cnd_sp_irq_enable(SP0_ID, true); + /* Set the IRQ device 0 to either level or pulse */ + irq_enable_pulse(IRQ0_ID, enable_pulse); + + cnd_virq_enable_channel(virq_sp, true); + + /* Enable SW interrupt 0, this is used to signal ISYS events */ + cnd_virq_enable_channel( + (enum virq_id)(IRQ_SW_CHANNEL0_ID + IRQ_SW_CHANNEL_OFFSET), + true); + /* Enable SW interrupt 1, this is used to signal PSYS events */ + cnd_virq_enable_channel( + (enum virq_id)(IRQ_SW_CHANNEL1_ID + IRQ_SW_CHANNEL_OFFSET), + true); + +#ifndef ISP2401 + for (port = 0; port < N_MIPI_PORT_ID; port++) + ia_css_isys_rx_enable_all_interrupts(port); +#endif + + IA_CSS_LEAVE_PRIVATE(""); +} + +static bool sh_css_setup_spctrl_config(const struct ia_css_fw_info *fw, + const char *program, + ia_css_spctrl_cfg *spctrl_cfg) +{ + if ((!fw) || (!spctrl_cfg)) + return false; + spctrl_cfg->sp_entry = 0; + spctrl_cfg->program_name = (char *)(program); + + spctrl_cfg->ddr_data_offset = fw->blob.data_source; + spctrl_cfg->dmem_data_addr = fw->blob.data_target; + spctrl_cfg->dmem_bss_addr = fw->blob.bss_target; + spctrl_cfg->data_size = fw->blob.data_size; + spctrl_cfg->bss_size = fw->blob.bss_size; + + spctrl_cfg->spctrl_config_dmem_addr = fw->info.sp.init_dmem_data; + spctrl_cfg->spctrl_state_dmem_addr = fw->info.sp.sw_state; + + spctrl_cfg->code_size = fw->blob.size; + spctrl_cfg->code = fw->blob.code; + spctrl_cfg->sp_entry = fw->info.sp.sp_entry; /* entry function ptr on SP */ + + return true; +} + +void +ia_css_unload_firmware(void) +{ + if (sh_css_num_binaries) { + /* we have already loaded before so get rid of the old stuff */ + ia_css_binary_uninit(); + sh_css_unload_firmware(); + } + fw_explicitly_loaded = false; +} + +static void +ia_css_reset_defaults(struct sh_css *css) +{ + struct sh_css default_css; + + /* Reset everything to zero */ + memset(&default_css, 0, sizeof(default_css)); + + /* Initialize the non zero values */ + default_css.check_system_idle = true; + default_css.num_cont_raw_frames = NUM_CONTINUOUS_FRAMES; + + /* + * All should be 0: but memset does it already. + * default_css.num_mipi_frames[N_CSI_PORTS] = 0; + */ + + default_css.irq_type = IA_CSS_IRQ_TYPE_EDGE; + + /* Set the defaults to the output */ + *css = default_css; +} + +int +ia_css_load_firmware(struct device *dev, const struct ia_css_env *env, + const struct ia_css_fw *fw) +{ + int err; + + if (!env) + return -EINVAL; + if (!fw) + return -EINVAL; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_load_firmware() enter\n"); + + /* make sure we initialize my_css */ + if (my_css.flush != env->cpu_mem_env.flush) { + ia_css_reset_defaults(&my_css); + my_css.flush = env->cpu_mem_env.flush; + } + + ia_css_unload_firmware(); /* in case we are called twice */ + err = sh_css_load_firmware(dev, fw->data, fw->bytes); + if (!err) { + err = ia_css_binary_init_infos(); + if (!err) + fw_explicitly_loaded = true; + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_load_firmware() leave\n"); + return err; +} + +int +ia_css_init(struct device *dev, const struct ia_css_env *env, + const struct ia_css_fw *fw, + u32 mmu_l1_base, + enum ia_css_irq_type irq_type) +{ + int err; + ia_css_spctrl_cfg spctrl_cfg; + + void (*flush_func)(struct ia_css_acc_fw *fw); + hrt_data select, enable; + + /* + * The C99 standard does not specify the exact object representation of structs; + * the representation is compiler dependent. + * + * The structs that are communicated between host and SP/ISP should have the + * exact same object representation. The compiler that is used to compile the + * firmware is hivecc. + * + * To check if a different compiler, used to compile a host application, uses + * another object representation, macros are defined specifying the size of + * the structs as expected by the firmware. + * + * A host application shall verify that a sizeof( ) of the struct is equal to + * the SIZE_OF_XXX macro of the corresponding struct. If they are not + * equal, functionality will break. + */ + + /* Check struct sh_css_ddr_address_map */ + COMPILATION_ERROR_IF(sizeof(struct sh_css_ddr_address_map) != SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT); + /* Check struct host_sp_queues */ + COMPILATION_ERROR_IF(sizeof(struct host_sp_queues) != SIZE_OF_HOST_SP_QUEUES_STRUCT); + COMPILATION_ERROR_IF(sizeof(struct ia_css_circbuf_desc_s) != SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT); + COMPILATION_ERROR_IF(sizeof(struct ia_css_circbuf_elem_s) != SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT); + + /* Check struct host_sp_communication */ + COMPILATION_ERROR_IF(sizeof(struct host_sp_communication) != SIZE_OF_HOST_SP_COMMUNICATION_STRUCT); + COMPILATION_ERROR_IF(sizeof(struct sh_css_event_irq_mask) != SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT); + + /* Check struct sh_css_hmm_buffer */ + COMPILATION_ERROR_IF(sizeof(struct sh_css_hmm_buffer) != SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT); + COMPILATION_ERROR_IF(sizeof(struct ia_css_isp_3a_statistics) != SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT); + COMPILATION_ERROR_IF(sizeof(struct ia_css_isp_dvs_statistics) != SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT); + COMPILATION_ERROR_IF(sizeof(struct ia_css_metadata) != SIZE_OF_IA_CSS_METADATA_STRUCT); + + /* Check struct ia_css_init_dmem_cfg */ + COMPILATION_ERROR_IF(sizeof(struct ia_css_sp_init_dmem_cfg) != SIZE_OF_IA_CSS_SP_INIT_DMEM_CFG_STRUCT); + + if (!fw && !fw_explicitly_loaded) + return -EINVAL; + if (!env) + return -EINVAL; + + sh_css_printf = env->print_env.debug_print; + + IA_CSS_ENTER("void"); + + flush_func = env->cpu_mem_env.flush; + + pipe_global_init(); + ia_css_pipeline_init(); + ia_css_queue_map_init(); + + ia_css_device_access_init(&env->hw_access_env); + + select = gpio_reg_load(GPIO0_ID, _gpio_block_reg_do_select) + & (~GPIO_FLASH_PIN_MASK); + enable = gpio_reg_load(GPIO0_ID, _gpio_block_reg_do_e) + | GPIO_FLASH_PIN_MASK; + sh_css_mmu_set_page_table_base_index(mmu_l1_base); + + my_css_save.mmu_base = mmu_l1_base; + + ia_css_reset_defaults(&my_css); + + my_css_save.driver_env = *env; + my_css.flush = flush_func; + + err = ia_css_rmgr_init(); + if (err) { + IA_CSS_LEAVE_ERR(err); + return err; + } + + IA_CSS_LOG("init: %d", my_css_save_initialized); + + if (!my_css_save_initialized) { + my_css_save_initialized = true; + my_css_save.mode = sh_css_mode_working; + memset(my_css_save.stream_seeds, 0, + sizeof(struct sh_css_stream_seed) * MAX_ACTIVE_STREAMS); + IA_CSS_LOG("init: %d mode=%d", my_css_save_initialized, my_css_save.mode); + } + + mipi_init(); + +#ifndef ISP2401 + /* + * In case this has been programmed already, update internal + * data structure ... + * DEPRECATED + */ + my_css.page_table_base_index = mmu_get_page_table_base_index(MMU0_ID); + +#endif + my_css.irq_type = irq_type; + + my_css_save.irq_type = irq_type; + + enable_interrupts(my_css.irq_type); + + /* configure GPIO to output mode */ + gpio_reg_store(GPIO0_ID, _gpio_block_reg_do_select, select); + gpio_reg_store(GPIO0_ID, _gpio_block_reg_do_e, enable); + gpio_reg_store(GPIO0_ID, _gpio_block_reg_do_0, 0); + + err = ia_css_refcount_init(REFCOUNT_SIZE); + if (err) { + IA_CSS_LEAVE_ERR(err); + return err; + } + err = sh_css_params_init(); + if (err) { + IA_CSS_LEAVE_ERR(err); + return err; + } + if (fw) { + ia_css_unload_firmware(); /* in case we already had firmware loaded */ + err = sh_css_load_firmware(dev, fw->data, fw->bytes); + if (err) { + IA_CSS_LEAVE_ERR(err); + return err; + } + err = ia_css_binary_init_infos(); + if (err) { + IA_CSS_LEAVE_ERR(err); + return err; + } + fw_explicitly_loaded = false; + + my_css_save.loaded_fw = (struct ia_css_fw *)fw; + } + if (!sh_css_setup_spctrl_config(&sh_css_sp_fw, SP_PROG_NAME, &spctrl_cfg)) + return -EINVAL; + + err = ia_css_spctrl_load_fw(SP0_ID, &spctrl_cfg); + if (err) { + IA_CSS_LEAVE_ERR(err); + return err; + } + + if (!sh_css_hrt_system_is_idle()) { + IA_CSS_LEAVE_ERR(-EBUSY); + return -EBUSY; + } + /* + * can be called here, queuing works, but: + * - when sp is started later, it will wipe queued items + * so for now we leave it for later and make sure + * updates are not called to frequently. + * sh_css_init_buffer_queues(); + */ + +#if defined(ISP2401) + gp_device_reg_store(GP_DEVICE0_ID, _REG_GP_SWITCH_ISYS2401_ADDR, 1); +#endif + + + if (!IS_ISP2401) + dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN, + ISP2400_DMA_MAX_BURST_LENGTH); + else + dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN, + ISP2401_DMA_MAX_BURST_LENGTH); + + if (ia_css_isys_init() != INPUT_SYSTEM_ERR_NO_ERROR) + err = -EINVAL; + + sh_css_params_map_and_store_default_gdc_lut(); + + IA_CSS_LEAVE_ERR(err); + return err; +} + +int +ia_css_enable_isys_event_queue(bool enable) +{ + if (sh_css_sp_is_running()) + return -EBUSY; + sh_css_sp_enable_isys_event_queue(enable); + return 0; +} + +/* + * Mapping sp threads. Currently, this is done when a stream is created and + * pipelines are ready to be converted to sp pipelines. Be careful if you are + * doing it from stream_create since we could run out of sp threads due to + * allocation on inactive pipelines. + */ +static int +map_sp_threads(struct ia_css_stream *stream, bool map) +{ + struct ia_css_pipe *main_pipe = NULL; + struct ia_css_pipe *copy_pipe = NULL; + struct ia_css_pipe *capture_pipe = NULL; + int err = 0; + enum ia_css_pipe_id pipe_id; + + IA_CSS_ENTER_PRIVATE("stream = %p, map = %s", + stream, map ? "true" : "false"); + + if (!stream) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + main_pipe = stream->last_pipe; + pipe_id = main_pipe->mode; + + ia_css_pipeline_map(main_pipe->pipe_num, map); + + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + copy_pipe = main_pipe->pipe_settings.preview.copy_pipe; + capture_pipe = main_pipe->pipe_settings.preview.capture_pipe; + break; + + case IA_CSS_PIPE_ID_VIDEO: + copy_pipe = main_pipe->pipe_settings.video.copy_pipe; + capture_pipe = main_pipe->pipe_settings.video.capture_pipe; + break; + + case IA_CSS_PIPE_ID_CAPTURE: + default: + break; + } + + if (capture_pipe) + ia_css_pipeline_map(capture_pipe->pipe_num, map); + + /* Firmware expects copy pipe to be the last pipe mapped. (if needed) */ + if (copy_pipe) + ia_css_pipeline_map(copy_pipe->pipe_num, map); + + /* DH regular multi pipe - not continuous mode: map the next pipes too */ + if (!stream->config.continuous) { + int i; + + for (i = 1; i < stream->num_pipes; i++) + ia_css_pipeline_map(stream->pipes[i]->pipe_num, map); + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* + * creates a host pipeline skeleton for all pipes in a stream. Called during + * stream_create. + */ +static int +create_host_pipeline_structure(struct ia_css_stream *stream) +{ + struct ia_css_pipe *copy_pipe = NULL, *capture_pipe = NULL; + enum ia_css_pipe_id pipe_id; + struct ia_css_pipe *main_pipe = NULL; + int err = 0; + unsigned int copy_pipe_delay = 0, + capture_pipe_delay = 0; + + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + + if (!stream) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + main_pipe = stream->last_pipe; + if (!main_pipe) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + pipe_id = main_pipe->mode; + + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + copy_pipe = main_pipe->pipe_settings.preview.copy_pipe; + copy_pipe_delay = main_pipe->dvs_frame_delay; + capture_pipe = main_pipe->pipe_settings.preview.capture_pipe; + capture_pipe_delay = IA_CSS_FRAME_DELAY_0; + err = ia_css_pipeline_create(&main_pipe->pipeline, main_pipe->mode, + main_pipe->pipe_num, main_pipe->dvs_frame_delay); + break; + + case IA_CSS_PIPE_ID_VIDEO: + copy_pipe = main_pipe->pipe_settings.video.copy_pipe; + copy_pipe_delay = main_pipe->dvs_frame_delay; + capture_pipe = main_pipe->pipe_settings.video.capture_pipe; + capture_pipe_delay = IA_CSS_FRAME_DELAY_0; + err = ia_css_pipeline_create(&main_pipe->pipeline, main_pipe->mode, + main_pipe->pipe_num, main_pipe->dvs_frame_delay); + break; + + case IA_CSS_PIPE_ID_CAPTURE: + capture_pipe = main_pipe; + capture_pipe_delay = main_pipe->dvs_frame_delay; + break; + + case IA_CSS_PIPE_ID_YUVPP: + err = ia_css_pipeline_create(&main_pipe->pipeline, main_pipe->mode, + main_pipe->pipe_num, main_pipe->dvs_frame_delay); + break; + + default: + err = -EINVAL; + } + + if (!(err) && copy_pipe) + err = ia_css_pipeline_create(©_pipe->pipeline, + copy_pipe->mode, + copy_pipe->pipe_num, + copy_pipe_delay); + + if (!(err) && capture_pipe) + err = ia_css_pipeline_create(&capture_pipe->pipeline, + capture_pipe->mode, + capture_pipe->pipe_num, + capture_pipe_delay); + + /* DH regular multi pipe - not continuous mode: create the next pipelines too */ + if (!stream->config.continuous) { + int i; + + for (i = 1; i < stream->num_pipes && 0 == err; i++) { + main_pipe = stream->pipes[i]; + err = ia_css_pipeline_create(&main_pipe->pipeline, + main_pipe->mode, + main_pipe->pipe_num, + main_pipe->dvs_frame_delay); + } + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* + * creates a host pipeline for all pipes in a stream. Called during + * stream_start. + */ +static int +create_host_pipeline(struct ia_css_stream *stream) +{ + struct ia_css_pipe *copy_pipe = NULL, *capture_pipe = NULL; + enum ia_css_pipe_id pipe_id; + struct ia_css_pipe *main_pipe = NULL; + int err = 0; + unsigned int max_input_width = 0; + + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + if (!stream) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + main_pipe = stream->last_pipe; + pipe_id = main_pipe->mode; + + /* + * No continuous frame allocation for capture pipe. It uses the + * "main" pipe's frames. + */ + if ((pipe_id == IA_CSS_PIPE_ID_PREVIEW) || + (pipe_id == IA_CSS_PIPE_ID_VIDEO)) { + /* + * About + * pipe_id == IA_CSS_PIPE_ID_PREVIEW && + * stream->config.mode != IA_CSS_INPUT_MODE_MEMORY: + * + * The original condition pipe_id == IA_CSS_PIPE_ID_PREVIEW is + * too strong. E.g. in SkyCam (with memory based input frames) + * there is no continuous mode and thus no need for allocated + * continuous frames. + * This is not only for SkyCam but for all preview cases that + * use DDR based input frames. For this reason the + * stream->config.mode != IA_CSS_INPUT_MODE_MEMORY has beed + * added. + */ + if (stream->config.continuous || + (pipe_id == IA_CSS_PIPE_ID_PREVIEW && + stream->config.mode != IA_CSS_INPUT_MODE_MEMORY)) { + err = alloc_continuous_frames(main_pipe, true); + if (err) + goto ERR; + } + } + + /* old isys: need to allocate_mipi_frames() even in IA_CSS_PIPE_MODE_COPY */ + if (!IS_ISP2401 || main_pipe->config.mode != IA_CSS_PIPE_MODE_COPY) { + err = allocate_mipi_frames(main_pipe, &stream->info); + if (err) + goto ERR; + } + + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + copy_pipe = main_pipe->pipe_settings.preview.copy_pipe; + capture_pipe = main_pipe->pipe_settings.preview.capture_pipe; + max_input_width = + main_pipe->pipe_settings.preview.preview_binary.info->sp.input.max_width; + + err = create_host_preview_pipeline(main_pipe); + if (err) + goto ERR; + + break; + + case IA_CSS_PIPE_ID_VIDEO: + copy_pipe = main_pipe->pipe_settings.video.copy_pipe; + capture_pipe = main_pipe->pipe_settings.video.capture_pipe; + max_input_width = + main_pipe->pipe_settings.video.video_binary.info->sp.input.max_width; + + err = create_host_video_pipeline(main_pipe); + if (err) + goto ERR; + + break; + + case IA_CSS_PIPE_ID_CAPTURE: + capture_pipe = main_pipe; + + break; + + case IA_CSS_PIPE_ID_YUVPP: + err = create_host_yuvpp_pipeline(main_pipe); + if (err) + goto ERR; + + break; + + default: + err = -EINVAL; + } + if (err) + goto ERR; + + if (copy_pipe) { + err = create_host_copy_pipeline(copy_pipe, max_input_width, + main_pipe->continuous_frames[0]); + if (err) + goto ERR; + } + + if (capture_pipe) { + err = create_host_capture_pipeline(capture_pipe); + if (err) + goto ERR; + } + + /* DH regular multi pipe - not continuous mode: create the next pipelines too */ + if (!stream->config.continuous) { + int i; + + for (i = 1; i < stream->num_pipes && 0 == err; i++) { + switch (stream->pipes[i]->mode) { + case IA_CSS_PIPE_ID_PREVIEW: + err = create_host_preview_pipeline(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_VIDEO: + err = create_host_video_pipeline(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_CAPTURE: + err = create_host_capture_pipeline(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_YUVPP: + err = create_host_yuvpp_pipeline(stream->pipes[i]); + break; + default: + err = -EINVAL; + } + if (err) + goto ERR; + } + } + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static const struct ia_css_pipe default_pipe = IA_CSS_DEFAULT_PIPE; +static const struct ia_css_preview_settings preview = IA_CSS_DEFAULT_PREVIEW_SETTINGS; +static const struct ia_css_capture_settings capture = IA_CSS_DEFAULT_CAPTURE_SETTINGS; +static const struct ia_css_video_settings video = IA_CSS_DEFAULT_VIDEO_SETTINGS; +static const struct ia_css_yuvpp_settings yuvpp = IA_CSS_DEFAULT_YUVPP_SETTINGS; + +static int +init_pipe_defaults(enum ia_css_pipe_mode mode, + struct ia_css_pipe *pipe, + bool copy_pipe) +{ + if (!pipe) { + IA_CSS_ERROR("NULL pipe parameter"); + return -EINVAL; + } + + /* Initialize pipe to pre-defined defaults */ + memcpy(pipe, &default_pipe, sizeof(default_pipe)); + + /* TODO: JB should not be needed, but temporary backward reference */ + switch (mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + pipe->mode = IA_CSS_PIPE_ID_PREVIEW; + memcpy(&pipe->pipe_settings.preview, &preview, sizeof(preview)); + break; + case IA_CSS_PIPE_MODE_CAPTURE: + if (copy_pipe) + pipe->mode = IA_CSS_PIPE_ID_COPY; + else + pipe->mode = IA_CSS_PIPE_ID_CAPTURE; + + memcpy(&pipe->pipe_settings.capture, &capture, sizeof(capture)); + break; + case IA_CSS_PIPE_MODE_VIDEO: + pipe->mode = IA_CSS_PIPE_ID_VIDEO; + memcpy(&pipe->pipe_settings.video, &video, sizeof(video)); + break; + case IA_CSS_PIPE_MODE_COPY: + pipe->mode = IA_CSS_PIPE_ID_CAPTURE; + break; + case IA_CSS_PIPE_MODE_YUVPP: + pipe->mode = IA_CSS_PIPE_ID_YUVPP; + memcpy(&pipe->pipe_settings.yuvpp, &yuvpp, sizeof(yuvpp)); + break; + default: + return -EINVAL; + } + + return 0; +} + +static void +pipe_global_init(void) +{ + u8 i; + + my_css.pipe_counter = 0; + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) + my_css.all_pipes[i] = NULL; +} + +static int +pipe_generate_pipe_num(const struct ia_css_pipe *pipe, + unsigned int *pipe_number) +{ + const u8 INVALID_PIPE_NUM = (uint8_t)~(0); + u8 pipe_num = INVALID_PIPE_NUM; + u8 i; + + if (!pipe) { + IA_CSS_ERROR("NULL pipe parameter"); + return -EINVAL; + } + + /* Assign a new pipe_num .... search for empty place */ + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) { + if (!my_css.all_pipes[i]) { + /* position is reserved */ + my_css.all_pipes[i] = (struct ia_css_pipe *)pipe; + pipe_num = i; + break; + } + } + if (pipe_num == INVALID_PIPE_NUM) { + /* Max number of pipes already allocated */ + IA_CSS_ERROR("Max number of pipes already created"); + return -ENOSPC; + } + + my_css.pipe_counter++; + + IA_CSS_LOG("pipe_num (%d)", pipe_num); + + *pipe_number = pipe_num; + return 0; +} + +static void +pipe_release_pipe_num(unsigned int pipe_num) +{ + my_css.all_pipes[pipe_num] = NULL; + my_css.pipe_counter--; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "pipe_release_pipe_num (%d)\n", pipe_num); +} + +static int +create_pipe(enum ia_css_pipe_mode mode, + struct ia_css_pipe **pipe, + bool copy_pipe) +{ + int err = 0; + struct ia_css_pipe *me; + + if (!pipe) { + IA_CSS_ERROR("NULL pipe parameter"); + return -EINVAL; + } + + me = kmalloc(sizeof(*me), GFP_KERNEL); + if (!me) + return -ENOMEM; + + err = init_pipe_defaults(mode, me, copy_pipe); + if (err) { + kfree(me); + return err; + } + + err = pipe_generate_pipe_num(me, &me->pipe_num); + if (err) { + kfree(me); + return err; + } + + *pipe = me; + return 0; +} + +struct ia_css_pipe * +find_pipe_by_num(uint32_t pipe_num) +{ + unsigned int i; + + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) { + if (my_css.all_pipes[i] && + ia_css_pipe_get_pipe_num(my_css.all_pipes[i]) == pipe_num) { + return my_css.all_pipes[i]; + } + } + return NULL; +} + +int +ia_css_pipe_destroy(struct ia_css_pipe *pipe) +{ + int err = 0; + + IA_CSS_ENTER("pipe = %p", pipe); + + if (!pipe) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + if (pipe->stream) { + IA_CSS_LOG("ia_css_stream_destroy not called!"); + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + switch (pipe->config.mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + /* + * need to take into account that this function is also called + * on the internal copy pipe + */ + if (pipe->mode == IA_CSS_PIPE_ID_PREVIEW) { + ia_css_frame_free_multiple(NUM_CONTINUOUS_FRAMES, + pipe->continuous_frames); + ia_css_metadata_free_multiple(NUM_CONTINUOUS_FRAMES, + pipe->cont_md_buffers); + if (pipe->pipe_settings.preview.copy_pipe) { + err = ia_css_pipe_destroy(pipe->pipe_settings.preview.copy_pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipe_destroy(): destroyed internal copy pipe err=%d\n", + err); + } + } + break; + case IA_CSS_PIPE_MODE_VIDEO: + if (pipe->mode == IA_CSS_PIPE_ID_VIDEO) { + ia_css_frame_free_multiple(NUM_CONTINUOUS_FRAMES, + pipe->continuous_frames); + ia_css_metadata_free_multiple(NUM_CONTINUOUS_FRAMES, + pipe->cont_md_buffers); + if (pipe->pipe_settings.video.copy_pipe) { + err = ia_css_pipe_destroy(pipe->pipe_settings.video.copy_pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipe_destroy(): destroyed internal copy pipe err=%d\n", + err); + } + } +#ifndef ISP2401 + ia_css_frame_free_multiple(NUM_VIDEO_TNR_FRAMES, + pipe->pipe_settings.video.tnr_frames); +#else + ia_css_frame_free_multiple(NUM_VIDEO_TNR_FRAMES, + pipe->pipe_settings.video.tnr_frames); +#endif + ia_css_frame_free_multiple(MAX_NUM_VIDEO_DELAY_FRAMES, + pipe->pipe_settings.video.delay_frames); + break; + case IA_CSS_PIPE_MODE_CAPTURE: + ia_css_frame_free_multiple(MAX_NUM_VIDEO_DELAY_FRAMES, + pipe->pipe_settings.capture.delay_frames); + break; + case IA_CSS_PIPE_MODE_COPY: + break; + case IA_CSS_PIPE_MODE_YUVPP: + break; + } + + if (pipe->scaler_pp_lut != mmgr_NULL) { + hmm_free(pipe->scaler_pp_lut); + pipe->scaler_pp_lut = mmgr_NULL; + } + + my_css.active_pipes[ia_css_pipe_get_pipe_num(pipe)] = NULL; + sh_css_pipe_free_shading_table(pipe); + + ia_css_pipeline_destroy(&pipe->pipeline); + pipe_release_pipe_num(ia_css_pipe_get_pipe_num(pipe)); + + kfree(pipe); + IA_CSS_LEAVE("err = %d", err); + return err; +} + +void +ia_css_uninit(void) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_uninit() enter: void\n"); + + sh_css_params_free_default_gdc_lut(); + + /* TODO: JB: implement decent check and handling of freeing mipi frames */ + if (!mipi_is_free()) + dev_warn(atomisp_dev, "mipi frames are not freed.\n"); + + /* cleanup generic data */ + sh_css_params_uninit(); + ia_css_refcount_uninit(); + + ia_css_rmgr_uninit(); + +#if !defined(ISP2401) + /* needed for reprogramming the inputformatter after power cycle of css */ + ifmtr_set_if_blocking_mode_reset = true; +#endif + + if (!fw_explicitly_loaded) + ia_css_unload_firmware(); + + ia_css_spctrl_unload_fw(SP0_ID); + sh_css_sp_set_sp_running(false); + /* check and free any remaining mipi frames */ + free_mipi_frames(NULL); + + sh_css_sp_reset_global_vars(); + + ia_css_isys_uninit(); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_uninit() leave: return_void\n"); +} + +int ia_css_irq_translate( + unsigned int *irq_infos) +{ + enum virq_id irq; + enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_more_irqs; + unsigned int infos = 0; + + /* irq_infos can be NULL, but that would make the function useless */ + /* assert(irq_infos != NULL); */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_irq_translate() enter: irq_infos=%p\n", irq_infos); + + while (status == hrt_isp_css_irq_status_more_irqs) { + status = virq_get_channel_id(&irq); + if (status == hrt_isp_css_irq_status_error) + return -EINVAL; + + + switch (irq) { + case virq_sp: + /* + * When SP goes to idle, info is available in the + * event queue. + */ + infos |= IA_CSS_IRQ_INFO_EVENTS_READY; + break; + case virq_isp: + break; + case virq_isys_sof: + infos |= IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF; + break; + case virq_isys_eof: + infos |= IA_CSS_IRQ_INFO_CSS_RECEIVER_EOF; + break; + case virq_isys_csi: + infos |= IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR; + break; +#if !defined(ISP2401) + case virq_ifmt0_id: + infos |= IA_CSS_IRQ_INFO_IF_ERROR; + break; +#endif + case virq_dma: + infos |= IA_CSS_IRQ_INFO_DMA_ERROR; + break; + case virq_sw_pin_0: + infos |= sh_css_get_sw_interrupt_value(0); + break; + case virq_sw_pin_1: + infos |= sh_css_get_sw_interrupt_value(1); + /* pqiao TODO: also assumption here */ + break; + default: + break; + } + } + + if (irq_infos) + *irq_infos = infos; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_irq_translate() leave: irq_infos=%u\n", + infos); + + return 0; +} + +int ia_css_irq_enable( + enum ia_css_irq_info info, + bool enable) +{ + enum virq_id irq = N_virq_id; + + IA_CSS_ENTER("info=%d, enable=%d", info, enable); + + switch (info) { +#if !defined(ISP2401) + case IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF: + irq = virq_isys_sof; + break; + case IA_CSS_IRQ_INFO_CSS_RECEIVER_EOF: + irq = virq_isys_eof; + break; + case IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR: + irq = virq_isys_csi; + break; + case IA_CSS_IRQ_INFO_IF_ERROR: + irq = virq_ifmt0_id; + break; +#else + case IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF: + case IA_CSS_IRQ_INFO_CSS_RECEIVER_EOF: + case IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR: + case IA_CSS_IRQ_INFO_IF_ERROR: + /* Just ignore those unused IRQs without printing errors */ + return 0; +#endif + case IA_CSS_IRQ_INFO_DMA_ERROR: + irq = virq_dma; + break; + case IA_CSS_IRQ_INFO_SW_0: + irq = virq_sw_pin_0; + break; + case IA_CSS_IRQ_INFO_SW_1: + irq = virq_sw_pin_1; + break; + default: + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + cnd_virq_enable_channel(irq, enable); + + IA_CSS_LEAVE_ERR(0); + return 0; +} + + +static unsigned int +sh_css_get_sw_interrupt_value(unsigned int irq) +{ + unsigned int irq_value; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_get_sw_interrupt_value() enter: irq=%d\n", irq); + irq_value = sh_css_sp_get_sw_interrupt_value(irq); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_get_sw_interrupt_value() leave: irq_value=%d\n", irq_value); + return irq_value; +} + +/* + * configure and load the copy binary, the next binary is used to + * determine whether the copy binary needs to do left padding. + */ +static int load_copy_binary( + struct ia_css_pipe *pipe, + struct ia_css_binary *copy_binary, + struct ia_css_binary *next_binary) +{ + struct ia_css_frame_info copy_out_info, copy_in_info, copy_vf_info; + unsigned int left_padding; + int err; + struct ia_css_binary_descr copy_descr; + + /* next_binary can be NULL */ + assert(pipe); + assert(copy_binary); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "load_copy_binary() enter:\n"); + + if (next_binary) { + copy_out_info = next_binary->in_frame_info; + left_padding = next_binary->left_padding; + } else { + copy_out_info = pipe->output_info[0]; + copy_vf_info = pipe->vf_output_info[0]; + ia_css_frame_info_set_format(©_vf_info, IA_CSS_FRAME_FORMAT_YUV_LINE); + left_padding = 0; + } + + ia_css_pipe_get_copy_binarydesc(pipe, ©_descr, + ©_in_info, ©_out_info, + (next_binary) ? NULL : NULL/*TODO: ©_vf_info*/); + err = ia_css_binary_find(©_descr, copy_binary); + if (err) + return err; + copy_binary->left_padding = left_padding; + return 0; +} + +static int +alloc_continuous_frames(struct ia_css_pipe *pipe, bool init_time) +{ + int err = 0; + struct ia_css_frame_info ref_info; + enum ia_css_pipe_id pipe_id; + bool continuous; + unsigned int i, idx; + unsigned int num_frames; + + IA_CSS_ENTER_PRIVATE("pipe = %p, init_time = %d", pipe, init_time); + + if ((!pipe) || (!pipe->stream)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + pipe_id = pipe->mode; + continuous = pipe->stream->config.continuous; + + if (continuous) { + if (init_time) { + num_frames = pipe->stream->config.init_num_cont_raw_buf; + pipe->stream->continuous_pipe = pipe; + } else { + num_frames = pipe->stream->config.target_num_cont_raw_buf; + } + } else { + num_frames = NUM_ONLINE_INIT_CONTINUOUS_FRAMES; + } + + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) { + ref_info = pipe->pipe_settings.preview.preview_binary.in_frame_info; + } else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) { + ref_info = pipe->pipe_settings.video.video_binary.in_frame_info; + } else { + /* should not happen */ + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + +#if defined(ISP2401) + /* For CSI2+, the continuous frame will hold the full input frame */ + ref_info.res.width = pipe->stream->config.input_config.input_res.width; + ref_info.res.height = pipe->stream->config.input_config.input_res.height; + + /* Ensure padded width is aligned for 2401 */ + ref_info.padded_width = CEIL_MUL(ref_info.res.width, 2 * ISP_VEC_NELEMS); +#endif + + if (pipe->stream->config.pack_raw_pixels) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "alloc_continuous_frames() IA_CSS_FRAME_FORMAT_RAW_PACKED\n"); + ref_info.format = IA_CSS_FRAME_FORMAT_RAW_PACKED; + } else + { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "alloc_continuous_frames() IA_CSS_FRAME_FORMAT_RAW\n"); + ref_info.format = IA_CSS_FRAME_FORMAT_RAW; + } + + /* Write format back to binary */ + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) { + pipe->pipe_settings.preview.preview_binary.in_frame_info.format = + ref_info.format; + } else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) { + pipe->pipe_settings.video.video_binary.in_frame_info.format = ref_info.format; + } else { + /* should not happen */ + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + if (init_time) + idx = 0; + else + idx = pipe->stream->config.init_num_cont_raw_buf; + + for (i = idx; i < NUM_CONTINUOUS_FRAMES; i++) { + /* free previous frame */ + if (pipe->continuous_frames[i]) { + ia_css_frame_free(pipe->continuous_frames[i]); + pipe->continuous_frames[i] = NULL; + } + /* free previous metadata buffer */ + ia_css_metadata_free(pipe->cont_md_buffers[i]); + pipe->cont_md_buffers[i] = NULL; + + /* check if new frame needed */ + if (i < num_frames) { + /* allocate new frame */ + err = ia_css_frame_allocate_from_info( + &pipe->continuous_frames[i], + &ref_info); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* allocate metadata buffer */ + pipe->cont_md_buffers[i] = ia_css_metadata_allocate( + &pipe->stream->info.metadata_info); + } + } + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +int +ia_css_alloc_continuous_frame_remain(struct ia_css_stream *stream) +{ + if (!stream) + return -EINVAL; + return alloc_continuous_frames(stream->continuous_pipe, false); +} + +static int +load_preview_binaries(struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info prev_in_info, + prev_bds_out_info, + prev_out_info, + prev_vf_info; + struct ia_css_binary_descr preview_descr; + bool online; + int err = 0; + bool need_vf_pp = false; + bool need_isp_copy_binary = false; +#ifdef ISP2401 + bool sensor = false; +#else + bool continuous; +#endif + /* preview only have 1 output pin now */ + struct ia_css_frame_info *pipe_out_info = &pipe->output_info[0]; + struct ia_css_preview_settings *mycs = &pipe->pipe_settings.preview; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->stream); + assert(pipe->mode == IA_CSS_PIPE_ID_PREVIEW); + + online = pipe->stream->config.online; +#ifdef ISP2401 + sensor = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR; +#else + continuous = pipe->stream->config.continuous; +#endif + + if (mycs->preview_binary.info) + return 0; + + err = ia_css_util_check_input(&pipe->stream->config, false, false); + if (err) + return err; + err = ia_css_frame_check_info(pipe_out_info); + if (err) + return err; + + /* + * Note: the current selection of vf_pp binary and + * parameterization of the preview binary contains a few pieces + * of hardcoded knowledge. This needs to be cleaned up such that + * the binary selection becomes more generic. + * The vf_pp binary is needed if one or more of the following features + * are required: + * 1. YUV downscaling. + * 2. Digital zoom. + * 3. An output format that is not supported by the preview binary. + * In practice this means something other than yuv_line or nv12. + * The decision if the vf_pp binary is needed for YUV downscaling is + * made after the preview binary selection, since some preview binaries + * can perform the requested YUV downscaling. + */ + need_vf_pp = pipe->config.enable_dz; + need_vf_pp |= pipe_out_info->format != IA_CSS_FRAME_FORMAT_YUV_LINE && + !(pipe_out_info->format == IA_CSS_FRAME_FORMAT_NV12 || + pipe_out_info->format == IA_CSS_FRAME_FORMAT_NV12_16 || + pipe_out_info->format == IA_CSS_FRAME_FORMAT_NV12_TILEY); + + /* Preview step 1 */ + if (pipe->vf_yuv_ds_input_info.res.width) + prev_vf_info = pipe->vf_yuv_ds_input_info; + else + prev_vf_info = *pipe_out_info; + /* + * If vf_pp is needed, then preview must output yuv_line. + * The exception is when vf_pp is manually disabled, that is only + * used in combination with a pipeline extension that requires + * yuv_line as input. + */ + if (need_vf_pp) + ia_css_frame_info_set_format(&prev_vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + err = ia_css_pipe_get_preview_binarydesc( + pipe, + &preview_descr, + &prev_in_info, + &prev_bds_out_info, + &prev_out_info, + &prev_vf_info); + if (err) + return err; + err = ia_css_binary_find(&preview_descr, &mycs->preview_binary); + if (err) + return err; + + /* The vf_pp binary is needed when (further) YUV downscaling is required */ + need_vf_pp |= mycs->preview_binary.out_frame_info[0].res.width != pipe_out_info->res.width; + need_vf_pp |= mycs->preview_binary.out_frame_info[0].res.height != pipe_out_info->res.height; + + /* + * When vf_pp is needed, then the output format of the selected + * preview binary must be yuv_line. If this is not the case, + * then the preview binary selection is done again. + */ + if (need_vf_pp && + (mycs->preview_binary.out_frame_info[0].format != IA_CSS_FRAME_FORMAT_YUV_LINE)) { + /* Preview step 2 */ + if (pipe->vf_yuv_ds_input_info.res.width) + prev_vf_info = pipe->vf_yuv_ds_input_info; + else + prev_vf_info = *pipe_out_info; + + ia_css_frame_info_set_format(&prev_vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + err = ia_css_pipe_get_preview_binarydesc( + pipe, + &preview_descr, + &prev_in_info, + &prev_bds_out_info, + &prev_out_info, + &prev_vf_info); + if (err) + return err; + err = ia_css_binary_find(&preview_descr, + &mycs->preview_binary); + if (err) + return err; + } + + if (need_vf_pp) { + struct ia_css_binary_descr vf_pp_descr; + + /* Viewfinder post-processing */ + ia_css_pipe_get_vfpp_binarydesc(pipe, &vf_pp_descr, + &mycs->preview_binary.out_frame_info[0], + pipe_out_info); + err = ia_css_binary_find(&vf_pp_descr, + &mycs->vf_pp_binary); + if (err) + return err; + } + +#ifdef ISP2401 + /* + * When the input system is 2401, only the Direct Sensor Mode + * Offline Preview uses the ISP copy binary. + */ + need_isp_copy_binary = !online && sensor; +#else + /* + * About pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY: + * This is typical the case with SkyCam (which has no input system) but it also applies to all cases + * where the driver chooses for memory based input frames. In these cases, a copy binary (which typical + * copies sensor data to DDR) does not have much use. + */ + if (!IS_ISP2401) + need_isp_copy_binary = !online && !continuous; + else + need_isp_copy_binary = !online && !continuous && !(pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY); +#endif + + /* Copy */ + if (need_isp_copy_binary) { + err = load_copy_binary(pipe, + &mycs->copy_binary, + &mycs->preview_binary); + if (err) + return err; + } + + if (pipe->shading_table) { + ia_css_shading_table_free(pipe->shading_table); + pipe->shading_table = NULL; + } + + return 0; +} + +static void +ia_css_binary_unload(struct ia_css_binary *binary) +{ + ia_css_binary_destroy_isp_parameters(binary); +} + +static int +unload_preview_binaries(struct ia_css_pipe *pipe) +{ + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + ia_css_binary_unload(&pipe->pipe_settings.preview.copy_binary); + ia_css_binary_unload(&pipe->pipe_settings.preview.preview_binary); + ia_css_binary_unload(&pipe->pipe_settings.preview.vf_pp_binary); + + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +static const struct ia_css_fw_info *last_output_firmware( + const struct ia_css_fw_info *fw) +{ + const struct ia_css_fw_info *last_fw = NULL; + /* fw can be NULL */ + IA_CSS_ENTER_LEAVE_PRIVATE(""); + + for (; fw; fw = fw->next) { + const struct ia_css_fw_info *info = fw; + + if (info->info.isp.sp.enable.output) + last_fw = fw; + } + return last_fw; +} + +static int add_firmwares( + struct ia_css_pipeline *me, + struct ia_css_binary *binary, + const struct ia_css_fw_info *fw, + const struct ia_css_fw_info *last_fw, + unsigned int binary_mode, + struct ia_css_frame *in_frame, + struct ia_css_frame *out_frame, + struct ia_css_frame *vf_frame, + struct ia_css_pipeline_stage **my_stage, + struct ia_css_pipeline_stage **vf_stage) +{ + int err = 0; + struct ia_css_pipeline_stage *extra_stage = NULL; + struct ia_css_pipeline_stage_desc stage_desc; + + /* all args can be NULL ??? */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_firmwares() enter:\n"); + + for (; fw; fw = fw->next) { + struct ia_css_frame *out[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL}; + struct ia_css_frame *in = NULL; + struct ia_css_frame *vf = NULL; + + if ((fw == last_fw) && (fw->info.isp.sp.enable.out_frame != 0)) + out[0] = out_frame; + + if (fw->info.isp.sp.enable.in_frame != 0) + in = in_frame; + + if (fw->info.isp.sp.enable.out_frame != 0) + vf = vf_frame; + + ia_css_pipe_get_firmwares_stage_desc(&stage_desc, binary, + out, in, vf, fw, binary_mode); + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + &extra_stage); + if (err) + return err; + if (fw->info.isp.sp.enable.output != 0) + in_frame = extra_stage->args.out_frame[0]; + if (my_stage && !*my_stage && extra_stage) + *my_stage = extra_stage; + if (vf_stage && !*vf_stage && extra_stage && + fw->info.isp.sp.enable.vf_veceven) + *vf_stage = extra_stage; + } + return err; +} + +static int add_vf_pp_stage( + struct ia_css_pipe *pipe, + struct ia_css_frame *in_frame, + struct ia_css_frame *out_frame, + struct ia_css_binary *vf_pp_binary, + struct ia_css_pipeline_stage **vf_pp_stage) +{ + struct ia_css_pipeline *me = NULL; + const struct ia_css_fw_info *last_fw = NULL; + int err = 0; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_pipeline_stage_desc stage_desc; + + /* out_frame can be NULL ??? */ + + if (!pipe) + return -EINVAL; + if (!in_frame) + return -EINVAL; + if (!vf_pp_binary) + return -EINVAL; + if (!vf_pp_stage) + return -EINVAL; + + ia_css_pipe_util_create_output_frames(out_frames); + me = &pipe->pipeline; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_vf_pp_stage() enter:\n"); + + *vf_pp_stage = NULL; + + last_fw = last_output_firmware(pipe->vf_stage); + if (!pipe->extra_config.disable_vf_pp) { + if (last_fw) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, vf_pp_binary, + out_frames, in_frame, NULL); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, vf_pp_binary, + out_frames, in_frame, NULL); + } + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, vf_pp_stage); + if (err) + return err; + in_frame = (*vf_pp_stage)->args.out_frame[0]; + } + err = add_firmwares(me, vf_pp_binary, pipe->vf_stage, last_fw, + IA_CSS_BINARY_MODE_VF_PP, + in_frame, out_frame, NULL, + vf_pp_stage, NULL); + return err; +} + +static int add_yuv_scaler_stage( + struct ia_css_pipe *pipe, + struct ia_css_pipeline *me, + struct ia_css_frame *in_frame, + struct ia_css_frame *out_frame, + struct ia_css_frame *internal_out_frame, + struct ia_css_binary *yuv_scaler_binary, + struct ia_css_pipeline_stage **pre_vf_pp_stage) +{ + const struct ia_css_fw_info *last_fw; + int err = 0; + struct ia_css_frame *vf_frame = NULL; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_pipeline_stage_desc stage_desc; + + /* out_frame can be NULL ??? */ + assert(in_frame); + assert(pipe); + assert(me); + assert(yuv_scaler_binary); + assert(pre_vf_pp_stage); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_yuv_scaler_stage() enter:\n"); + + *pre_vf_pp_stage = NULL; + ia_css_pipe_util_create_output_frames(out_frames); + + last_fw = last_output_firmware(pipe->output_stage); + + if (last_fw) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + yuv_scaler_binary, out_frames, in_frame, vf_frame); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_util_set_output_frames(out_frames, 1, internal_out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + yuv_scaler_binary, out_frames, in_frame, vf_frame); + } + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + pre_vf_pp_stage); + if (err) + return err; + in_frame = (*pre_vf_pp_stage)->args.out_frame[0]; + + err = add_firmwares(me, yuv_scaler_binary, pipe->output_stage, last_fw, + IA_CSS_BINARY_MODE_CAPTURE_PP, + in_frame, out_frame, vf_frame, + NULL, pre_vf_pp_stage); + /* If a firmware produce vf_pp output, we set that as vf_pp input */ + (*pre_vf_pp_stage)->args.vf_downscale_log2 = + yuv_scaler_binary->vf_downscale_log2; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_yuv_scaler_stage() leave:\n"); + return err; +} + +static int add_capture_pp_stage( + struct ia_css_pipe *pipe, + struct ia_css_pipeline *me, + struct ia_css_frame *in_frame, + struct ia_css_frame *out_frame, + struct ia_css_binary *capture_pp_binary, + struct ia_css_pipeline_stage **capture_pp_stage) +{ + const struct ia_css_fw_info *last_fw = NULL; + int err = 0; + struct ia_css_frame *vf_frame = NULL; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_pipeline_stage_desc stage_desc; + + /* out_frame can be NULL ??? */ + assert(in_frame); + assert(pipe); + assert(me); + assert(capture_pp_binary); + assert(capture_pp_stage); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_capture_pp_stage() enter:\n"); + + *capture_pp_stage = NULL; + ia_css_pipe_util_create_output_frames(out_frames); + + last_fw = last_output_firmware(pipe->output_stage); + err = ia_css_frame_allocate_from_info(&vf_frame, + &capture_pp_binary->vf_frame_info); + if (err) + return err; + if (last_fw) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + capture_pp_binary, out_frames, NULL, vf_frame); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + capture_pp_binary, out_frames, NULL, vf_frame); + } + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + capture_pp_stage); + if (err) + return err; + err = add_firmwares(me, capture_pp_binary, pipe->output_stage, last_fw, + IA_CSS_BINARY_MODE_CAPTURE_PP, + in_frame, out_frame, vf_frame, + NULL, capture_pp_stage); + /* If a firmware produce vf_pp output, we set that as vf_pp input */ + if (*capture_pp_stage) { + (*capture_pp_stage)->args.vf_downscale_log2 = + capture_pp_binary->vf_downscale_log2; + } + return err; +} + +static void sh_css_setup_queues(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_host_sp_queues_initialized; + + sh_css_hmm_buffer_record_init(); + + sh_css_event_init_irq_mask(); + + fw = &sh_css_sp_fw; + HIVE_ADDR_host_sp_queues_initialized = + fw->info.sp.host_sp_queues_initialized; + + ia_css_bufq_init(); + + /* set "host_sp_queues_initialized" to "true" */ + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(host_sp_queues_initialized), + (uint32_t)(1)); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_setup_queues() leave:\n"); +} + +static int +init_vf_frameinfo_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *vf_frame, unsigned int idx) +{ + int err = 0; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + + assert(vf_frame); + + sh_css_pipe_get_viewfinder_frame_info(pipe, &vf_frame->frame_info, idx); + vf_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME + idx, thread_id, &queue_id); + vf_frame->dynamic_queue_id = queue_id; + vf_frame->buf_type = IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME + idx; + + err = ia_css_frame_init_planes(vf_frame); + return err; +} + +#ifdef ISP2401 +static unsigned int +get_crop_lines_for_bayer_order(const struct ia_css_stream_config *config) +{ + assert(config); + if ((config->input_config.bayer_order == IA_CSS_BAYER_ORDER_BGGR) || + (config->input_config.bayer_order == IA_CSS_BAYER_ORDER_GBRG)) + return 1; + + return 0; +} + +static unsigned int +get_crop_columns_for_bayer_order(const struct ia_css_stream_config *config) +{ + assert(config); + if ((config->input_config.bayer_order == IA_CSS_BAYER_ORDER_RGGB) || + (config->input_config.bayer_order == IA_CSS_BAYER_ORDER_GBRG)) + return 1; + + return 0; +} + +/* + * This function is to get the sum of all extra pixels in addition to the effective + * input, it includes dvs envelop and filter run-in + */ +static void get_pipe_extra_pixel(struct ia_css_pipe *pipe, + unsigned int *extra_row, unsigned int *extra_column) +{ + enum ia_css_pipe_id pipe_id = pipe->mode; + unsigned int left_cropping = 0, top_cropping = 0; + unsigned int i; + struct ia_css_resolution dvs_env = pipe->config.dvs_envelope; + + /* + * The dvs envelope info may not be correctly sent down via pipe config + * The check is made and the correct value is populated in the binary info + * Use this value when computing crop, else excess lines may get trimmed + */ + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + if (pipe->pipe_settings.preview.preview_binary.info) { + left_cropping = + pipe->pipe_settings.preview.preview_binary.info->sp.pipeline.left_cropping; + top_cropping = + pipe->pipe_settings.preview.preview_binary.info->sp.pipeline.top_cropping; + } + dvs_env = pipe->pipe_settings.preview.preview_binary.dvs_envelope; + break; + case IA_CSS_PIPE_ID_VIDEO: + if (pipe->pipe_settings.video.video_binary.info) { + left_cropping = + pipe->pipe_settings.video.video_binary.info->sp.pipeline.left_cropping; + top_cropping = + pipe->pipe_settings.video.video_binary.info->sp.pipeline.top_cropping; + } + dvs_env = pipe->pipe_settings.video.video_binary.dvs_envelope; + break; + case IA_CSS_PIPE_ID_CAPTURE: + for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) { + if (pipe->pipe_settings.capture.primary_binary[i].info) { + left_cropping += + pipe->pipe_settings.capture.primary_binary[i].info->sp.pipeline.left_cropping; + top_cropping += + pipe->pipe_settings.capture.primary_binary[i].info->sp.pipeline.top_cropping; + } + dvs_env.width += + pipe->pipe_settings.capture.primary_binary[i].dvs_envelope.width; + dvs_env.height += + pipe->pipe_settings.capture.primary_binary[i].dvs_envelope.height; + } + break; + default: + break; + } + + *extra_row = top_cropping + dvs_env.height; + *extra_column = left_cropping + dvs_env.width; +} + +void +ia_css_get_crop_offsets( + struct ia_css_pipe *pipe, + struct ia_css_frame_info *in_frame) +{ + unsigned int row = 0; + unsigned int column = 0; + struct ia_css_resolution *input_res; + struct ia_css_resolution *effective_res; + unsigned int extra_row = 0, extra_col = 0; + unsigned int min_reqd_height, min_reqd_width; + + assert(pipe); + assert(pipe->stream); + assert(in_frame); + + IA_CSS_ENTER_PRIVATE("pipe = %p effective_wd = %u effective_ht = %u", + pipe, pipe->config.input_effective_res.width, + pipe->config.input_effective_res.height); + + input_res = &pipe->stream->config.input_config.input_res; +#ifndef ISP2401 + effective_res = &pipe->stream->config.input_config.effective_res; +#else + effective_res = &pipe->config.input_effective_res; +#endif + + get_pipe_extra_pixel(pipe, &extra_row, &extra_col); + + in_frame->raw_bayer_order = pipe->stream->config.input_config.bayer_order; + + min_reqd_height = effective_res->height + extra_row; + min_reqd_width = effective_res->width + extra_col; + + if (input_res->height > min_reqd_height) { + row = (input_res->height - min_reqd_height) / 2; + row &= ~0x1; + } + if (input_res->width > min_reqd_width) { + column = (input_res->width - min_reqd_width) / 2; + column &= ~0x1; + } + + /* + * TODO: + * 1. Require the special support for RAW10 packed mode. + * 2. Require the special support for the online use cases. + */ + + /* + * ISP expects GRBG bayer order, we skip one line and/or one row + * to correct in case the input bayer order is different. + */ + column += get_crop_columns_for_bayer_order(&pipe->stream->config); + row += get_crop_lines_for_bayer_order(&pipe->stream->config); + + in_frame->crop_info.start_column = column; + in_frame->crop_info.start_line = row; + + IA_CSS_LEAVE_PRIVATE("void start_col: %u start_row: %u", column, row); + + return; +} +#endif + +static int +init_in_frameinfo_memory_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *frame, enum ia_css_frame_format format) +{ + struct ia_css_frame *in_frame; + int err = 0; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + + assert(frame); + in_frame = frame; + + in_frame->frame_info.format = format; + +#ifdef ISP2401 + if (format == IA_CSS_FRAME_FORMAT_RAW) + in_frame->frame_info.format = (pipe->stream->config.pack_raw_pixels) ? + IA_CSS_FRAME_FORMAT_RAW_PACKED : IA_CSS_FRAME_FORMAT_RAW; +#endif + + in_frame->frame_info.res.width = pipe->stream->config.input_config.input_res.width; + in_frame->frame_info.res.height = pipe->stream->config.input_config.input_res.height; + in_frame->frame_info.raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + ia_css_frame_info_set_width(&in_frame->frame_info, + pipe->stream->config.input_config.input_res.width, 0); + in_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_INPUT_FRAME, thread_id, &queue_id); + in_frame->dynamic_queue_id = queue_id; + in_frame->buf_type = IA_CSS_BUFFER_TYPE_INPUT_FRAME; +#ifdef ISP2401 + ia_css_get_crop_offsets(pipe, &in_frame->frame_info); +#endif + err = ia_css_frame_init_planes(in_frame); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "%s() bayer_order = %d\n", + __func__, in_frame->frame_info.raw_bayer_order); + + return err; +} + +static int +init_out_frameinfo_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *out_frame, unsigned int idx) +{ + int err = 0; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + + assert(out_frame); + + sh_css_pipe_get_output_frame_info(pipe, &out_frame->frame_info, idx); + out_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_OUTPUT_FRAME + idx, thread_id, &queue_id); + out_frame->dynamic_queue_id = queue_id; + out_frame->buf_type = IA_CSS_BUFFER_TYPE_OUTPUT_FRAME + idx; + err = ia_css_frame_init_planes(out_frame); + + return err; +} + +/* Create stages for video pipe */ +static int create_host_video_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline_stage_desc stage_desc; + struct ia_css_binary *copy_binary, *video_binary, + *yuv_scaler_binary, *vf_pp_binary; + struct ia_css_pipeline_stage *copy_stage = NULL; + struct ia_css_pipeline_stage *video_stage = NULL; + struct ia_css_pipeline_stage *yuv_scaler_stage = NULL; + struct ia_css_pipeline_stage *vf_pp_stage = NULL; + struct ia_css_pipeline *me; + struct ia_css_frame *in_frame = NULL; + struct ia_css_frame *out_frame; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame *vf_frame = NULL; + int err = 0; + bool need_copy = false; + bool need_vf_pp = false; + bool need_yuv_pp = false; + bool need_in_frameinfo_memory = false; + + unsigned int i, num_yuv_scaler; + bool *is_output_stage = NULL; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + ia_css_pipe_util_create_output_frames(out_frames); + out_frame = &pipe->out_frame_struct; + + /* pipeline already created as part of create_host_pipeline_structure */ + me = &pipe->pipeline; + ia_css_pipeline_clean(me); + + me->dvs_frame_delay = pipe->dvs_frame_delay; + +#ifdef ISP2401 + /* + * When the input system is 2401, always enable 'in_frameinfo_memory' + * except for the following: online or continuous + */ + need_in_frameinfo_memory = !(pipe->stream->config.online || + pipe->stream->config.continuous); +#else + /* Construct in_frame info (only in case we have dynamic input */ + need_in_frameinfo_memory = pipe->stream->config.mode == + IA_CSS_INPUT_MODE_MEMORY; +#endif + + /* Construct in_frame info (only in case we have dynamic input */ + if (need_in_frameinfo_memory) { + in_frame = &pipe->in_frame_struct; + err = init_in_frameinfo_memory_defaults(pipe, in_frame, + IA_CSS_FRAME_FORMAT_RAW); + if (err) + goto ERR; + } + + out_frame->data = 0; + err = init_out_frameinfo_defaults(pipe, out_frame, 0); + if (err) + goto ERR; + + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + vf_frame = &pipe->vf_frame_struct; + vf_frame->data = 0; + err = init_vf_frameinfo_defaults(pipe, vf_frame, 0); + if (err) + goto ERR; + } + + copy_binary = &pipe->pipe_settings.video.copy_binary; + video_binary = &pipe->pipe_settings.video.video_binary; + vf_pp_binary = &pipe->pipe_settings.video.vf_pp_binary; + + yuv_scaler_binary = pipe->pipe_settings.video.yuv_scaler_binary; + num_yuv_scaler = pipe->pipe_settings.video.num_yuv_scaler; + is_output_stage = pipe->pipe_settings.video.is_output_stage; + + need_copy = (copy_binary && copy_binary->info); + need_vf_pp = (vf_pp_binary && vf_pp_binary->info); + need_yuv_pp = (yuv_scaler_binary && yuv_scaler_binary->info); + + if (need_copy) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + out_frames, NULL, NULL); + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + ©_stage); + if (err) + goto ERR; + in_frame = me->stages->args.out_frame[0]; + } else if (pipe->stream->config.continuous) { +#ifdef ISP2401 + /* + * When continuous is enabled, configure in_frame with the + * last pipe, which is the copy pipe. + */ + in_frame = pipe->stream->last_pipe->continuous_frames[0]; +#else + in_frame = pipe->continuous_frames[0]; +#endif + } + + ia_css_pipe_util_set_output_frames(out_frames, 0, + need_yuv_pp ? NULL : out_frame); + + /* + * when the video binary supports a second output pin, + * it can directly produce the vf_frame. + */ + if (need_vf_pp) { + ia_css_pipe_get_generic_stage_desc(&stage_desc, video_binary, + out_frames, in_frame, NULL); + } else { + ia_css_pipe_get_generic_stage_desc(&stage_desc, video_binary, + out_frames, in_frame, vf_frame); + } + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + &video_stage); + if (err) + goto ERR; + + /* If we use copy iso video, the input must be yuv iso raw */ + if (video_stage) { + video_stage->args.copy_vf = + video_binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY; + video_stage->args.copy_output = video_stage->args.copy_vf; + } + + /* when the video binary supports only 1 output pin, vf_pp is needed to + produce the vf_frame.*/ + if (need_vf_pp && video_stage) { + in_frame = video_stage->args.out_vf_frame; + err = add_vf_pp_stage(pipe, in_frame, vf_frame, vf_pp_binary, + &vf_pp_stage); + if (err) + goto ERR; + } + if (video_stage) { + int frm; + + for (frm = 0; frm < NUM_VIDEO_TNR_FRAMES; frm++) { + video_stage->args.tnr_frames[frm] = + pipe->pipe_settings.video.tnr_frames[frm]; + } + for (frm = 0; frm < MAX_NUM_VIDEO_DELAY_FRAMES; frm++) { + video_stage->args.delay_frames[frm] = + pipe->pipe_settings.video.delay_frames[frm]; + } + } + + if (need_yuv_pp && video_stage) { + struct ia_css_frame *tmp_in_frame = video_stage->args.out_frame[0]; + struct ia_css_frame *tmp_out_frame = NULL; + + for (i = 0; i < num_yuv_scaler; i++) { + tmp_out_frame = is_output_stage[i] ? out_frame : NULL; + + err = add_yuv_scaler_stage(pipe, me, tmp_in_frame, + tmp_out_frame, NULL, + &yuv_scaler_binary[i], + &yuv_scaler_stage); + + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* we use output port 1 as internal output port */ + if (yuv_scaler_stage) + tmp_in_frame = yuv_scaler_stage->args.out_frame[1]; + } + } + + pipe->pipeline.acquire_isp_each_stage = false; + ia_css_pipeline_finalize_stages(&pipe->pipeline, + pipe->stream->config.continuous); + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* Create stages for preview */ +static int +create_host_preview_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline_stage *copy_stage = NULL; + struct ia_css_pipeline_stage *preview_stage = NULL; + struct ia_css_pipeline_stage *vf_pp_stage = NULL; + struct ia_css_pipeline_stage_desc stage_desc; + struct ia_css_pipeline *me = NULL; + struct ia_css_binary *copy_binary, *preview_binary, *vf_pp_binary = NULL; + struct ia_css_frame *in_frame = NULL; + int err = 0; + struct ia_css_frame *out_frame; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + bool need_in_frameinfo_memory = false; +#ifdef ISP2401 + bool sensor = false; + bool buffered_sensor = false; + bool online = false; + bool continuous = false; +#endif + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + ia_css_pipe_util_create_output_frames(out_frames); + /* pipeline already created as part of create_host_pipeline_structure */ + me = &pipe->pipeline; + ia_css_pipeline_clean(me); + +#ifdef ISP2401 + /* + * When the input system is 2401, always enable 'in_frameinfo_memory' + * except for the following: + * - Direct Sensor Mode Online Preview + * - Buffered Sensor Mode Online Preview + * - Direct Sensor Mode Continuous Preview + * - Buffered Sensor Mode Continuous Preview + */ + sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR); + buffered_sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR); + online = pipe->stream->config.online; + continuous = pipe->stream->config.continuous; + need_in_frameinfo_memory = + !((sensor && (online || continuous)) || (buffered_sensor && (online || continuous))); +#else + /* Construct in_frame info (only in case we have dynamic input */ + need_in_frameinfo_memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + if (need_in_frameinfo_memory) { + err = init_in_frameinfo_memory_defaults(pipe, &me->in_frame, + IA_CSS_FRAME_FORMAT_RAW); + if (err) + goto ERR; + + in_frame = &me->in_frame; + } else { + in_frame = NULL; + } + + err = init_out_frameinfo_defaults(pipe, &me->out_frame[0], 0); + if (err) + goto ERR; + out_frame = &me->out_frame[0]; + + copy_binary = &pipe->pipe_settings.preview.copy_binary; + preview_binary = &pipe->pipe_settings.preview.preview_binary; + if (pipe->pipe_settings.preview.vf_pp_binary.info) + vf_pp_binary = &pipe->pipe_settings.preview.vf_pp_binary; + + if (pipe->pipe_settings.preview.copy_binary.info) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + out_frames, NULL, NULL); + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + ©_stage); + if (err) + goto ERR; + in_frame = me->stages->args.out_frame[0]; + } else if (pipe->stream->config.continuous) { +#ifdef ISP2401 + /* + * When continuous is enabled, configure in_frame with the + * last pipe, which is the copy pipe. + */ + if (continuous || !online) + in_frame = pipe->stream->last_pipe->continuous_frames[0]; + +#else + in_frame = pipe->continuous_frames[0]; +#endif + } + + if (vf_pp_binary) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, preview_binary, + out_frames, in_frame, NULL); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, preview_binary, + out_frames, in_frame, NULL); + } + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + &preview_stage); + if (err) + goto ERR; + /* If we use copy iso preview, the input must be yuv iso raw */ + preview_stage->args.copy_vf = + preview_binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY; + preview_stage->args.copy_output = !preview_stage->args.copy_vf; + if (preview_stage->args.copy_vf && !preview_stage->args.out_vf_frame) { + /* in case of copy, use the vf frame as output frame */ + preview_stage->args.out_vf_frame = + preview_stage->args.out_frame[0]; + } + if (vf_pp_binary) { + if (preview_binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY) + in_frame = preview_stage->args.out_vf_frame; + else + in_frame = preview_stage->args.out_frame[0]; + err = add_vf_pp_stage(pipe, in_frame, out_frame, vf_pp_binary, + &vf_pp_stage); + if (err) + goto ERR; + } + + pipe->pipeline.acquire_isp_each_stage = false; + ia_css_pipeline_finalize_stages(&pipe->pipeline, pipe->stream->config.continuous); + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static void send_raw_frames(struct ia_css_pipe *pipe) +{ + if (pipe->stream->config.continuous) { + unsigned int i; + + sh_css_update_host2sp_cont_num_raw_frames + (pipe->stream->config.init_num_cont_raw_buf, true); + sh_css_update_host2sp_cont_num_raw_frames + (pipe->stream->config.target_num_cont_raw_buf, false); + + /* Hand-over all the SP-internal buffers */ + for (i = 0; i < pipe->stream->config.init_num_cont_raw_buf; i++) { + sh_css_update_host2sp_offline_frame(i, + pipe->continuous_frames[i], pipe->cont_md_buffers[i]); + } + } + + return; +} + +static int +preview_start(struct ia_css_pipe *pipe) +{ + int err = 0; + struct ia_css_pipe *copy_pipe, *capture_pipe; + enum sh_css_pipe_config_override copy_ovrd; + enum ia_css_input_mode preview_pipe_input_mode; + unsigned int thread_id; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + preview_pipe_input_mode = pipe->stream->config.mode; + + copy_pipe = pipe->pipe_settings.preview.copy_pipe; + capture_pipe = pipe->pipe_settings.preview.capture_pipe; + + sh_css_metrics_start_frame(); + + /* multi stream video needs mipi buffers */ + err = send_mipi_frames(pipe); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + send_raw_frames(pipe); + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + copy_ovrd = 1 << thread_id; + + if (pipe->stream->cont_capt) { + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(capture_pipe), + &thread_id); + copy_ovrd |= 1 << thread_id; + } + + /* Construct and load the copy pipe */ + if (pipe->stream->config.continuous) { + sh_css_sp_init_pipeline(©_pipe->pipeline, + IA_CSS_PIPE_ID_COPY, + (uint8_t)ia_css_pipe_get_pipe_num(copy_pipe), + false, + pipe->stream->config.pixels_per_clock == 2, false, + false, pipe->required_bds_factor, + copy_ovrd, + pipe->stream->config.mode, + &pipe->stream->config.metadata_config, + &pipe->stream->info.metadata_info, + pipe->stream->config.source.port.port); + + /* + * make the preview pipe start with mem mode input, copy handles + * the actual mode + */ + preview_pipe_input_mode = IA_CSS_INPUT_MODE_MEMORY; + } + + /* Construct and load the capture pipe */ + if (pipe->stream->cont_capt) { + sh_css_sp_init_pipeline(&capture_pipe->pipeline, + IA_CSS_PIPE_ID_CAPTURE, + (uint8_t)ia_css_pipe_get_pipe_num(capture_pipe), + capture_pipe->config.default_capture_config.enable_xnr != 0, + capture_pipe->stream->config.pixels_per_clock == 2, + true, /* continuous */ + false, /* offline */ + capture_pipe->required_bds_factor, + 0, + IA_CSS_INPUT_MODE_MEMORY, + &pipe->stream->config.metadata_config, + &pipe->stream->info.metadata_info, + (enum mipi_port_id)0); + } + + start_pipe(pipe, copy_ovrd, preview_pipe_input_mode); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +int +ia_css_pipe_enqueue_buffer(struct ia_css_pipe *pipe, + const struct ia_css_buffer *buffer) +{ + int return_err = 0; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + struct ia_css_pipeline *pipeline; + struct ia_css_pipeline_stage *stage; + struct ia_css_rmgr_vbuf_handle p_vbuf; + struct ia_css_rmgr_vbuf_handle *h_vbuf; + struct sh_css_hmm_buffer ddr_buffer; + enum ia_css_buffer_type buf_type; + enum ia_css_pipe_id pipe_id; + bool ret_err; + + IA_CSS_ENTER("pipe=%p, buffer=%p", pipe, buffer); + + if ((!pipe) || (!buffer)) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + buf_type = buffer->type; + + pipe_id = pipe->mode; + + IA_CSS_LOG("pipe_id=%d, buf_type=%d", pipe_id, buf_type); + + assert(pipe_id < IA_CSS_PIPE_ID_NUM); + assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE); + if (buf_type == IA_CSS_BUFFER_TYPE_INVALID || + buf_type >= IA_CSS_NUM_DYNAMIC_BUFFER_TYPE || + pipe_id >= IA_CSS_PIPE_ID_NUM) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + ret_err = ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + if (!ret_err) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + ret_err = ia_css_query_internal_queue_id(buf_type, thread_id, &queue_id); + if (!ret_err) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + if ((queue_id <= SH_CSS_INVALID_QUEUE_ID) || (queue_id >= SH_CSS_MAX_NUM_QUEUES)) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + if (!sh_css_sp_is_running()) { + IA_CSS_LOG("SP is not running!"); + IA_CSS_LEAVE_ERR(-EBUSY); + /* SP is not running. The queues are not valid */ + return -EBUSY; + } + + pipeline = &pipe->pipeline; + + assert(pipeline || pipe_id == IA_CSS_PIPE_ID_COPY); + + assert(sizeof(NULL) <= sizeof(ddr_buffer.kernel_ptr)); + ddr_buffer.kernel_ptr = HOST_ADDRESS(NULL); + ddr_buffer.cookie_ptr = buffer->driver_cookie; + ddr_buffer.timing_data = buffer->timing_data; + + if (buf_type == IA_CSS_BUFFER_TYPE_3A_STATISTICS) { + if (!buffer->data.stats_3a) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.stats_3a); + ddr_buffer.payload.s3a = *buffer->data.stats_3a; + } else if (buf_type == IA_CSS_BUFFER_TYPE_DIS_STATISTICS) { + if (!buffer->data.stats_dvs) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.stats_dvs); + ddr_buffer.payload.dis = *buffer->data.stats_dvs; + } else if (buf_type == IA_CSS_BUFFER_TYPE_METADATA) { + if (!buffer->data.metadata) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.metadata); + ddr_buffer.payload.metadata = *buffer->data.metadata; + } else if (buf_type == IA_CSS_BUFFER_TYPE_INPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME) { + if (!buffer->data.frame) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.frame); + ddr_buffer.payload.frame.frame_data = buffer->data.frame->data; + ddr_buffer.payload.frame.flashed = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipe_enqueue_buffer() buf_type=%d, data(DDR address)=0x%x\n", + buf_type, buffer->data.frame->data); + + } + + /* start of test for using rmgr for acq/rel memory */ + p_vbuf.vptr = 0; + p_vbuf.count = 0; + p_vbuf.size = sizeof(struct sh_css_hmm_buffer); + h_vbuf = &p_vbuf; + /* TODO: change next to correct pool for optimization */ + ia_css_rmgr_acq_vbuf(hmm_buffer_pool, &h_vbuf); + + if ((!h_vbuf) || (h_vbuf->vptr == 0x0)) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + hmm_store(h_vbuf->vptr, + (void *)(&ddr_buffer), + sizeof(struct sh_css_hmm_buffer)); + if (buf_type == IA_CSS_BUFFER_TYPE_3A_STATISTICS || + buf_type == IA_CSS_BUFFER_TYPE_DIS_STATISTICS || + buf_type == IA_CSS_BUFFER_TYPE_LACE_STATISTICS) { + if (!pipeline) { + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &h_vbuf); + IA_CSS_LOG("pipeline is empty!"); + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + for (stage = pipeline->stages; stage; stage = stage->next) { + /* + * The SP will read the params after it got + * empty 3a and dis + */ + if (STATS_ENABLED(stage)) { + /* there is a stage that needs it */ + return_err = ia_css_bufq_enqueue_buffer(thread_id, + queue_id, + (uint32_t)h_vbuf->vptr); + } + } + } else if (buf_type == IA_CSS_BUFFER_TYPE_INPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_METADATA) { + return_err = ia_css_bufq_enqueue_buffer(thread_id, + queue_id, + (uint32_t)h_vbuf->vptr); + if (!return_err && + buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) { + IA_CSS_LOG("pfp: enqueued OF %d to q %d thread %d", + ddr_buffer.payload.frame.frame_data, + queue_id, thread_id); + } + } + + if (!return_err) { + if (sh_css_hmm_buffer_record_acquire( + h_vbuf, buf_type, + HOST_ADDRESS(ddr_buffer.kernel_ptr))) { + IA_CSS_LOG("send vbuf=%p", h_vbuf); + } else { + return_err = -EINVAL; + IA_CSS_ERROR("hmm_buffer_record[]: no available slots\n"); + } + } + + /* + * Tell the SP which queues are not empty, + * by sending the software event. + */ + if (!return_err) { + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + IA_CSS_LOG("SP is not running!"); + IA_CSS_LEAVE_ERR(-EBUSY); + return -EBUSY; + } + return_err = ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_BUFFER_ENQUEUED, + (uint8_t)thread_id, + queue_id, + 0); + } else { + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &h_vbuf); + IA_CSS_ERROR("buffer not enqueued"); + } + + IA_CSS_LEAVE("return value = %d", return_err); + + return return_err; +} + +/* + * TODO: Free up the hmm memory space. + */ +int +ia_css_pipe_dequeue_buffer(struct ia_css_pipe *pipe, + struct ia_css_buffer *buffer) +{ + int return_err; + enum sh_css_queue_id queue_id; + ia_css_ptr ddr_buffer_addr = (ia_css_ptr)0; + struct sh_css_hmm_buffer ddr_buffer; + enum ia_css_buffer_type buf_type; + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + hrt_address kernel_ptr = 0; + bool ret_err; + + IA_CSS_ENTER("pipe=%p, buffer=%p", pipe, buffer); + + if ((!pipe) || (!buffer)) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + pipe_id = pipe->mode; + + buf_type = buffer->type; + + IA_CSS_LOG("pipe_id=%d, buf_type=%d", pipe_id, buf_type); + + ddr_buffer.kernel_ptr = 0; + + ret_err = ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + if (!ret_err) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + ret_err = ia_css_query_internal_queue_id(buf_type, thread_id, &queue_id); + if (!ret_err) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + if ((queue_id <= SH_CSS_INVALID_QUEUE_ID) || (queue_id >= SH_CSS_MAX_NUM_QUEUES)) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + if (!sh_css_sp_is_running()) { + IA_CSS_LOG("SP is not running!"); + IA_CSS_LEAVE_ERR(-EBUSY); + /* SP is not running. The queues are not valid */ + return -EBUSY; + } + + return_err = ia_css_bufq_dequeue_buffer(queue_id, + (uint32_t *)&ddr_buffer_addr); + + if (!return_err) { + struct ia_css_frame *frame; + struct sh_css_hmm_buffer_record *hmm_buffer_record = NULL; + + IA_CSS_LOG("receive vbuf=%x", (int)ddr_buffer_addr); + + /* Validate the ddr_buffer_addr and buf_type */ + hmm_buffer_record = sh_css_hmm_buffer_record_validate( + ddr_buffer_addr, buf_type); + if (hmm_buffer_record) { + /* + * valid hmm_buffer_record found. Save the kernel_ptr + * for validation after performing hmm_load. The + * vbuf handle and buffer_record can be released. + */ + kernel_ptr = hmm_buffer_record->kernel_ptr; + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &hmm_buffer_record->h_vbuf); + sh_css_hmm_buffer_record_reset(hmm_buffer_record); + } else { + IA_CSS_ERROR("hmm_buffer_record not found (0x%x) buf_type(%d)", + ddr_buffer_addr, buf_type); + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + hmm_load(ddr_buffer_addr, + &ddr_buffer, + sizeof(struct sh_css_hmm_buffer)); + + /* + * if the kernel_ptr is 0 or an invalid, return an error. + * do not access the buffer via the kernal_ptr. + */ + if ((ddr_buffer.kernel_ptr == 0) || + (kernel_ptr != HOST_ADDRESS(ddr_buffer.kernel_ptr))) { + IA_CSS_ERROR("kernel_ptr invalid"); + IA_CSS_ERROR("expected: (0x%llx)", (u64)kernel_ptr); + IA_CSS_ERROR("actual: (0x%llx)", (u64)HOST_ADDRESS(ddr_buffer.kernel_ptr)); + IA_CSS_ERROR("buf_type: %d\n", buf_type); + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + if (ddr_buffer.kernel_ptr != 0) { + /* + * buffer->exp_id : all instances to be removed later + * once the driver change is completed. See patch #5758 + * for reference + */ + buffer->exp_id = 0; + buffer->driver_cookie = ddr_buffer.cookie_ptr; + buffer->timing_data = ddr_buffer.timing_data; + + if (buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME || + buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) { + buffer->isys_eof_clock_tick.ticks = ddr_buffer.isys_eof_clock_tick; + } + + switch (buf_type) { + case IA_CSS_BUFFER_TYPE_INPUT_FRAME: + case IA_CSS_BUFFER_TYPE_OUTPUT_FRAME: + case IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME: + if (pipe && pipe->stop_requested) { +#if !defined(ISP2401) + /* + * free mipi frames only for old input + * system for 2401 it is done in + * ia_css_stream_destroy call + */ + return_err = free_mipi_frames(pipe); + if (return_err) { + IA_CSS_LOG("free_mipi_frames() failed"); + IA_CSS_LEAVE_ERR(return_err); + return return_err; + } +#endif + pipe->stop_requested = false; + } + fallthrough; + case IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME: + case IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME: + frame = (struct ia_css_frame *)HOST_ADDRESS(ddr_buffer.kernel_ptr); + buffer->data.frame = frame; + buffer->exp_id = ddr_buffer.payload.frame.exp_id; + frame->exp_id = ddr_buffer.payload.frame.exp_id; + frame->isp_config_id = ddr_buffer.payload.frame.isp_parameters_id; + if (ddr_buffer.payload.frame.flashed == 1) + frame->flash_state = + IA_CSS_FRAME_FLASH_STATE_PARTIAL; + if (ddr_buffer.payload.frame.flashed == 2) + frame->flash_state = + IA_CSS_FRAME_FLASH_STATE_FULL; + frame->valid = pipe->num_invalid_frames == 0; + if (!frame->valid) + pipe->num_invalid_frames--; + + if (frame->frame_info.format == IA_CSS_FRAME_FORMAT_BINARY_8) { +#ifdef ISP2401 + frame->planes.binary.size = frame->data_bytes; +#else + frame->planes.binary.size = + sh_css_sp_get_binary_copy_size(); +#endif + } + if (buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) { + IA_CSS_LOG("pfp: dequeued OF %d with config id %d thread %d", + frame->data, frame->isp_config_id, thread_id); + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipe_dequeue_buffer() buf_type=%d, data(DDR address)=0x%x\n", + buf_type, buffer->data.frame->data); + + break; + case IA_CSS_BUFFER_TYPE_3A_STATISTICS: + buffer->data.stats_3a = + (struct ia_css_isp_3a_statistics *)HOST_ADDRESS(ddr_buffer.kernel_ptr); + buffer->exp_id = ddr_buffer.payload.s3a.exp_id; + buffer->data.stats_3a->exp_id = ddr_buffer.payload.s3a.exp_id; + buffer->data.stats_3a->isp_config_id = ddr_buffer.payload.s3a.isp_config_id; + break; + case IA_CSS_BUFFER_TYPE_DIS_STATISTICS: + buffer->data.stats_dvs = + (struct ia_css_isp_dvs_statistics *) + HOST_ADDRESS(ddr_buffer.kernel_ptr); + buffer->exp_id = ddr_buffer.payload.dis.exp_id; + buffer->data.stats_dvs->exp_id = ddr_buffer.payload.dis.exp_id; + break; + case IA_CSS_BUFFER_TYPE_LACE_STATISTICS: + break; + case IA_CSS_BUFFER_TYPE_METADATA: + buffer->data.metadata = + (struct ia_css_metadata *)HOST_ADDRESS(ddr_buffer.kernel_ptr); + buffer->exp_id = ddr_buffer.payload.metadata.exp_id; + buffer->data.metadata->exp_id = ddr_buffer.payload.metadata.exp_id; + break; + default: + return_err = -EINVAL; + break; + } + } + } + + /* + * Tell the SP which queues are not full, + * by sending the software event. + */ + if (!return_err) { + if (!sh_css_sp_is_running()) { + IA_CSS_LOG("SP is not running!"); + IA_CSS_LEAVE_ERR(-EBUSY); + /* SP is not running. The queues are not valid */ + return -EBUSY; + } + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_BUFFER_DEQUEUED, + 0, + queue_id, + 0); + } + IA_CSS_LEAVE("buffer=%p", buffer); + + return return_err; +} + +/* + * Cannot Move this to event module as it is of ia_css_event_type which is declared in ia_css.h + * TODO: modify and move it if possible. + * + * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: + * 1) "enum ia_css_event_type" (ia_css_event_public.h) + * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) + * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) + * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) + */ +static enum ia_css_event_type convert_event_sp_to_host_domain[] = { + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE, /* Output frame ready. */ + IA_CSS_EVENT_TYPE_SECOND_OUTPUT_FRAME_DONE, /* Second output frame ready. */ + IA_CSS_EVENT_TYPE_VF_OUTPUT_FRAME_DONE, /* Viewfinder Output frame ready. */ + IA_CSS_EVENT_TYPE_SECOND_VF_OUTPUT_FRAME_DONE, /* Second viewfinder Output frame ready. */ + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE, /* Indication that 3A statistics are available. */ + IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE, /* Indication that DIS statistics are available. */ + IA_CSS_EVENT_TYPE_PIPELINE_DONE, /* Pipeline Done event, sent after last pipeline stage. */ + IA_CSS_EVENT_TYPE_FRAME_TAGGED, /* Frame tagged. */ + IA_CSS_EVENT_TYPE_INPUT_FRAME_DONE, /* Input frame ready. */ + IA_CSS_EVENT_TYPE_METADATA_DONE, /* Metadata ready. */ + IA_CSS_EVENT_TYPE_LACE_STATISTICS_DONE, /* Indication that LACE statistics are available. */ + IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE, /* Extension stage executed. */ + IA_CSS_EVENT_TYPE_TIMER, /* Timing measurement data. */ + IA_CSS_EVENT_TYPE_PORT_EOF, /* End Of Frame event, sent when in buffered sensor mode. */ + IA_CSS_EVENT_TYPE_FW_WARNING, /* Performance warning encountered by FW */ + IA_CSS_EVENT_TYPE_FW_ASSERT, /* Assertion hit by FW */ + 0, /* error if sp passes SH_CSS_SP_EVENT_NR_OF_TYPES as a valid event. */ +}; + +int +ia_css_dequeue_psys_event(struct ia_css_event *event) +{ + enum ia_css_pipe_id pipe_id = 0; + u8 payload[4] = {0, 0, 0, 0}; + int ret_err; + + /* + * TODO: + * a) use generic decoding function , same as the one used by sp. + * b) group decode and dequeue into eventQueue module + * + * We skip the IA_CSS_ENTER logging call + * to avoid flooding the logs when the host application + * uses polling. + */ + if (!event) + return -EINVAL; + + /* SP is not running. The queues are not valid */ + if (!sh_css_sp_is_running()) + return -EBUSY; + + /* dequeue the event (if any) from the psys event queue */ + ret_err = ia_css_bufq_dequeue_psys_event(payload); + if (ret_err) + return ret_err; + + IA_CSS_LOG("event dequeued from psys event queue"); + + /* Tell the SP that we dequeued an event from the event queue. */ + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_EVENT_DEQUEUED, 0, 0, 0); + + /* + * Events are decoded into 4 bytes of payload, the first byte + * contains the sp event type. This is converted to a host enum. + * TODO: can this enum conversion be eliminated + */ + event->type = convert_event_sp_to_host_domain[payload[0]]; + /* Some sane default values since not all events use all fields. */ + event->pipe = NULL; + event->port = MIPI_PORT0_ID; + event->exp_id = 0; + event->fw_warning = IA_CSS_FW_WARNING_NONE; + event->fw_handle = 0; + event->timer_data = 0; + event->timer_code = 0; + event->timer_subcode = 0; + + if (event->type == IA_CSS_EVENT_TYPE_TIMER) { + /* + * timer event ??? get the 2nd event and decode the data + * into the event struct + */ + u32 tmp_data; + /* 1st event: LSB 16-bit timer data and code */ + event->timer_data = ((payload[1] & 0xFF) | ((payload[3] & 0xFF) << 8)); + event->timer_code = payload[2]; + payload[0] = payload[1] = payload[2] = payload[3] = 0; + ret_err = ia_css_bufq_dequeue_psys_event(payload); + if (ret_err) { + /* no 2nd event ??? an error */ + /* + * Putting IA_CSS_ERROR is resulting in failures in + * Merrifield smoke testing + */ + IA_CSS_WARNING("Timer: Error de-queuing the 2nd TIMER event!!!\n"); + return ret_err; + } + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_EVENT_DEQUEUED, 0, 0, 0); + event->type = convert_event_sp_to_host_domain[payload[0]]; + /* It's a timer */ + if (event->type == IA_CSS_EVENT_TYPE_TIMER) { + /* 2nd event data: MSB 16-bit timer and subcode */ + tmp_data = ((payload[1] & 0xFF) | ((payload[3] & 0xFF) << 8)); + event->timer_data |= (tmp_data << 16); + event->timer_subcode = payload[2]; + } else { + /* + * It's a non timer event. So clear first half of the + * timer event data. + * If the second part of the TIMER event is not + * received, we discard the first half of the timer + * data and process the non timer event without + * affecting the flow. So the non timer event falls + * through the code. + */ + event->timer_data = 0; + event->timer_code = 0; + event->timer_subcode = 0; + IA_CSS_ERROR("Missing 2nd timer event. Timer event discarded"); + } + } + if (event->type == IA_CSS_EVENT_TYPE_PORT_EOF) { + event->port = (enum mipi_port_id)payload[1]; + event->exp_id = payload[3]; + } else if (event->type == IA_CSS_EVENT_TYPE_FW_WARNING) { + event->fw_warning = (enum ia_css_fw_warning)payload[1]; + /* exp_id is only available in these warning types */ + if (event->fw_warning == IA_CSS_FW_WARNING_EXP_ID_LOCKED || + event->fw_warning == IA_CSS_FW_WARNING_TAG_EXP_ID_FAILED) + event->exp_id = payload[3]; + } else if (event->type == IA_CSS_EVENT_TYPE_FW_ASSERT) { + event->fw_assert_module_id = payload[1]; /* module */ + event->fw_assert_line_no = (payload[2] << 8) + payload[3]; + /* payload[2] is line_no>>8, payload[3] is line_no&0xff */ + } else if (event->type != IA_CSS_EVENT_TYPE_TIMER) { + /* + * pipe related events. + * payload[1] contains the pipe_num, + * payload[2] contains the pipe_id. These are different. + */ + event->pipe = find_pipe_by_num(payload[1]); + pipe_id = (enum ia_css_pipe_id)payload[2]; + /* Check to see if pipe still exists */ + if (!event->pipe) + return -EBUSY; + + if (event->type == IA_CSS_EVENT_TYPE_FRAME_TAGGED) { + /* find the capture pipe that goes with this */ + int i, n; + + n = event->pipe->stream->num_pipes; + for (i = 0; i < n; i++) { + struct ia_css_pipe *p = + event->pipe->stream->pipes[i]; + if (p->config.mode == IA_CSS_PIPE_MODE_CAPTURE) { + event->pipe = p; + break; + } + } + event->exp_id = payload[3]; + } + if (event->type == IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE) { + /* payload[3] contains the acc fw handle. */ + u32 stage_num = (uint32_t)payload[3]; + + ret_err = ia_css_pipeline_get_fw_from_stage( + &event->pipe->pipeline, + stage_num, + &event->fw_handle); + if (ret_err) { + IA_CSS_ERROR("Invalid stage num received for ACC event. stage_num:%u", + stage_num); + return ret_err; + } + } + } + + if (event->pipe) + IA_CSS_LEAVE("event_id=%d, pipe_id=%d", event->type, pipe_id); + else + IA_CSS_LEAVE("event_id=%d", event->type); + + return 0; +} + +int +ia_css_dequeue_isys_event(struct ia_css_event *event) +{ + u8 payload[4] = {0, 0, 0, 0}; + int err = 0; + + /* + * We skip the IA_CSS_ENTER logging call + * to avoid flooding the logs when the host application + * uses polling. + */ + if (!event) + return -EINVAL; + + /* SP is not running. The queues are not valid */ + if (!sh_css_sp_is_running()) + return -EBUSY; + + err = ia_css_bufq_dequeue_isys_event(payload); + if (err) + return err; + + IA_CSS_LOG("event dequeued from isys event queue"); + + /* Update SP state to indicate that element was dequeued. */ + ia_css_bufq_enqueue_isys_event(IA_CSS_ISYS_SW_EVENT_EVENT_DEQUEUED); + + /* Fill return struct with appropriate info */ + event->type = IA_CSS_EVENT_TYPE_PORT_EOF; + /* EOF events are associated with a CSI port, not with a pipe */ + event->pipe = NULL; + event->port = payload[1]; + event->exp_id = payload[3]; + + IA_CSS_LEAVE_ERR(err); + return err; +} + +static int +sh_css_pipe_start(struct ia_css_stream *stream) +{ + int err = 0; + + struct ia_css_pipe *pipe; + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + + if (!stream) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + pipe = stream->last_pipe; + if (!pipe) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + pipe_id = pipe->mode; + + if (stream->started) { + IA_CSS_WARNING("Cannot start stream that is already started"); + IA_CSS_LEAVE_ERR(err); + return err; + } + + pipe->stop_requested = false; + + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + err = preview_start(pipe); + break; + case IA_CSS_PIPE_ID_VIDEO: + err = video_start(pipe); + break; + case IA_CSS_PIPE_ID_CAPTURE: + err = capture_start(pipe); + break; + case IA_CSS_PIPE_ID_YUVPP: + err = yuvpp_start(pipe); + break; + default: + err = -EINVAL; + } + /* DH regular multi pipe - not continuous mode: start the next pipes too */ + if (!stream->config.continuous) { + int i; + + for (i = 1; i < stream->num_pipes && 0 == err ; i++) { + switch (stream->pipes[i]->mode) { + case IA_CSS_PIPE_ID_PREVIEW: + stream->pipes[i]->stop_requested = false; + err = preview_start(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_VIDEO: + stream->pipes[i]->stop_requested = false; + err = video_start(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_CAPTURE: + stream->pipes[i]->stop_requested = false; + err = capture_start(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_YUVPP: + stream->pipes[i]->stop_requested = false; + err = yuvpp_start(stream->pipes[i]); + break; + default: + err = -EINVAL; + } + } + } + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + /* + * Force ISP parameter calculation after a mode change + * Acceleration API examples pass NULL for stream but they + * don't use ISP parameters anyway. So this should be okay. + * The SP binary (jpeg) copy does not use any parameters. + */ + if (!copy_on_sp(pipe)) { + sh_css_invalidate_params(stream); + err = sh_css_param_update_isp_params(pipe, + stream->isp_params_configs, true, NULL); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + ia_css_debug_pipe_graph_dump_epilogue(); + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + + if (!sh_css_sp_is_running()) { + IA_CSS_LEAVE_ERR_PRIVATE(-EBUSY); + /* SP is not running. The queues are not valid */ + return -EBUSY; + } + ia_css_bufq_enqueue_psys_event(IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, 0, 0); + + /* DH regular multi pipe - not continuous mode: enqueue event to the next pipes too */ + if (!stream->config.continuous) { + int i; + + for (i = 1; i < stream->num_pipes; i++) { + ia_css_pipeline_get_sp_thread_id( + ia_css_pipe_get_pipe_num(stream->pipes[i]), + &thread_id); + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, 0, 0); + } + } + + /* in case of continuous capture mode, we also start capture thread and copy thread*/ + if (pipe->stream->config.continuous) { + struct ia_css_pipe *copy_pipe = NULL; + + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) + copy_pipe = pipe->pipe_settings.preview.copy_pipe; + else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) + copy_pipe = pipe->pipe_settings.video.copy_pipe; + + if (!copy_pipe) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(copy_pipe), + &thread_id); + /* by the time we reach here q is initialized and handle is available.*/ + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, 0, 0); + } + if (pipe->stream->cont_capt) { + struct ia_css_pipe *capture_pipe = NULL; + + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) + capture_pipe = pipe->pipe_settings.preview.capture_pipe; + else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) + capture_pipe = pipe->pipe_settings.video.capture_pipe; + + if (!capture_pipe) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(capture_pipe), + &thread_id); + /* by the time we reach here q is initialized and handle is available.*/ + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, 0, 0); + } + + stream->started = true; + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* ISP2400 */ +void +sh_css_enable_cont_capt(bool enable, bool stop_copy_preview) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_enable_cont_capt() enter: enable=%d\n", enable); +//my_css.cont_capt = enable; + my_css.stop_copy_preview = stop_copy_preview; +} + +bool +sh_css_continuous_is_enabled(uint8_t pipe_num) +{ + struct ia_css_pipe *pipe; + bool continuous; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_continuous_is_enabled() enter: pipe_num=%d\n", pipe_num); + + pipe = find_pipe_by_num(pipe_num); + continuous = pipe && pipe->stream->config.continuous; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_continuous_is_enabled() leave: enable=%d\n", + continuous); + return continuous; +} + +/* ISP2400 */ +int +ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, + int *buffer_depth) +{ + if (!buffer_depth) + return -EINVAL; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_max_buffer_depth() enter: void\n"); + (void)stream; + *buffer_depth = NUM_CONTINUOUS_FRAMES; + return 0; +} + +int +ia_css_stream_set_buffer_depth(struct ia_css_stream *stream, int buffer_depth) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_set_buffer_depth() enter: num_frames=%d\n", buffer_depth); + (void)stream; + if (buffer_depth > NUM_CONTINUOUS_FRAMES || buffer_depth < 1) + return -EINVAL; + /* ok, value allowed */ + stream->config.target_num_cont_raw_buf = buffer_depth; + /* TODO: check what to regarding initialization */ + return 0; +} + +/* ISP2401 */ +int +ia_css_stream_get_buffer_depth(struct ia_css_stream *stream, + int *buffer_depth) +{ + if (!buffer_depth) + return -EINVAL; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_buffer_depth() enter: void\n"); + (void)stream; + *buffer_depth = stream->config.target_num_cont_raw_buf; + return 0; +} + +#if !defined(ISP2401) +unsigned int +sh_css_get_mipi_sizes_for_check(const unsigned int port, const unsigned int idx) +{ + OP___assert(port < N_CSI_PORTS); + OP___assert(idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_get_mipi_sizes_for_check(port %d, idx %d): %d\n", + port, idx, my_css.mipi_sizes_for_check[port][idx]); + return my_css.mipi_sizes_for_check[port][idx]; +} +#endif + +static int sh_css_pipe_configure_output( + struct ia_css_pipe *pipe, + unsigned int width, + unsigned int height, + unsigned int padded_width, + enum ia_css_frame_format format, + unsigned int idx) +{ + int err = 0; + + IA_CSS_ENTER_PRIVATE("pipe = %p, width = %d, height = %d, padded width = %d, format = %d, idx = %d", + pipe, width, height, padded_width, format, idx); + if (!pipe) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + err = ia_css_util_check_res(width, height); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (pipe->output_info[idx].res.width != width || + pipe->output_info[idx].res.height != height || + pipe->output_info[idx].format != format) { + ia_css_frame_info_init( + &pipe->output_info[idx], + width, + height, + format, + padded_width); + } + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +static int +sh_css_pipe_get_shading_info(struct ia_css_pipe *pipe, + struct ia_css_shading_info *shading_info, + struct ia_css_pipe_config *pipe_config) +{ + int err = 0; + struct ia_css_binary *binary = NULL; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_shading_info() enter:\n"); + + binary = ia_css_pipe_get_shading_correction_binary(pipe); + + if (binary) { + err = ia_css_binary_get_shading_info(binary, + IA_CSS_SHADING_CORRECTION_TYPE_1, + pipe->required_bds_factor, + (const struct ia_css_stream_config *)&pipe->stream->config, + shading_info, pipe_config); + + /* + * Other function calls can be added here when other shading + * correction types will be added in the future. + */ + } else { + /* + * When the pipe does not have a binary which has the shading + * correction, this function does not need to fill the shading + * information. It is not a error case, and then + * this function should return 0. + */ + memset(shading_info, 0, sizeof(*shading_info)); + } + return err; +} + +static int +sh_css_pipe_get_grid_info(struct ia_css_pipe *pipe, + struct ia_css_grid_info *info) +{ + int err = 0; + struct ia_css_binary *binary = NULL; + + assert(pipe); + assert(info); + + IA_CSS_ENTER_PRIVATE(""); + + binary = ia_css_pipe_get_s3a_binary(pipe); + + if (binary) { + err = ia_css_binary_3a_grid_info(binary, info, pipe); + if (err) + goto err; + } else { + memset(&info->s3a_grid, 0, sizeof(info->s3a_grid)); + } + + binary = ia_css_pipe_get_sdis_binary(pipe); + + if (binary) { + ia_css_binary_dvs_grid_info(binary, info, pipe); + ia_css_binary_dvs_stat_grid_info(binary, info, pipe); + } else { + memset(&info->dvs_grid, 0, sizeof(info->dvs_grid)); + memset(&info->dvs_grid.dvs_stat_grid_info, 0, + sizeof(info->dvs_grid.dvs_stat_grid_info)); + } + + if (binary) { + /* copy pipe does not have ISP binary*/ + info->isp_in_width = binary->internal_frame_info.res.width; + info->isp_in_height = binary->internal_frame_info.res.height; + } + + info->vamem_type = IA_CSS_VAMEM_TYPE_2; + +err: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* ISP2401 */ +/* + * @brief Check if a format is supported by the pipe. + * + */ +static int +ia_css_pipe_check_format(struct ia_css_pipe *pipe, + enum ia_css_frame_format format) +{ + const enum ia_css_frame_format *supported_formats; + int number_of_formats; + int found = 0; + int i; + + IA_CSS_ENTER_PRIVATE(""); + + if (NULL == pipe || NULL == pipe->pipe_settings.video.video_binary.info) { + IA_CSS_ERROR("Pipe or binary info is not set"); + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + supported_formats = pipe->pipe_settings.video.video_binary.info->output_formats; + number_of_formats = sizeof(pipe->pipe_settings.video.video_binary.info->output_formats) / sizeof(enum ia_css_frame_format); + + for (i = 0; i < number_of_formats && !found; i++) { + if (supported_formats[i] == format) { + found = 1; + break; + } + } + if (!found) { + IA_CSS_ERROR("Requested format is not supported by binary"); + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +static int load_video_binaries(struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info video_in_info, tnr_info, + *video_vf_info, video_bds_out_info, *pipe_out_info, *pipe_vf_out_info; + bool online; + int err = 0; + bool continuous = pipe->stream->config.continuous; + unsigned int i; + unsigned int num_output_pins; + struct ia_css_frame_info video_bin_out_info; + bool need_scaler = false; + bool vf_res_different_than_output = false; + bool need_vf_pp = false; + int vf_ds_log2; + struct ia_css_video_settings *mycs = &pipe->pipe_settings.video; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->mode == IA_CSS_PIPE_ID_VIDEO); + /* + * we only test the video_binary because offline video doesn't need a + * vf_pp binary and online does not (always use) the copy_binary. + * All are always reset at the same time anyway. + */ + if (mycs->video_binary.info) + return 0; + + online = pipe->stream->config.online; + pipe_out_info = &pipe->output_info[0]; + pipe_vf_out_info = &pipe->vf_output_info[0]; + + assert(pipe_out_info); + + /* + * There is no explicit input format requirement for raw or yuv + * What matters is that there is a binary that supports the stream format. + * This is checked in the binary_find(), so no need to check it here + */ + err = ia_css_util_check_input(&pipe->stream->config, false, false); + if (err) + return err; + /* cannot have online video and input_mode memory */ + if (online && pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY) + return -EINVAL; + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + err = ia_css_util_check_vf_out_info(pipe_out_info, + pipe_vf_out_info); + if (err) + return err; + } else { + err = ia_css_frame_check_info(pipe_out_info); + if (err) + return err; + } + + if (pipe->out_yuv_ds_input_info.res.width) + video_bin_out_info = pipe->out_yuv_ds_input_info; + else + video_bin_out_info = *pipe_out_info; + + /* Video */ + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + video_vf_info = pipe_vf_out_info; + vf_res_different_than_output = (video_vf_info->res.width != + video_bin_out_info.res.width) || + (video_vf_info->res.height != video_bin_out_info.res.height); + } else { + video_vf_info = NULL; + } + + need_scaler = need_downscaling(video_bin_out_info.res, pipe_out_info->res); + + /* we build up the pipeline starting at the end */ + /* YUV post-processing if needed */ + if (need_scaler) { + struct ia_css_cas_binary_descr cas_scaler_descr = { }; + + /* NV12 is the common format that is supported by both */ + /* yuv_scaler and the video_xx_isp2_min binaries. */ + video_bin_out_info.format = IA_CSS_FRAME_FORMAT_NV12; + + err = ia_css_pipe_create_cas_scaler_desc_single_output( + &video_bin_out_info, + pipe_out_info, + NULL, + &cas_scaler_descr); + if (err) + return err; + mycs->num_yuv_scaler = cas_scaler_descr.num_stage; + mycs->yuv_scaler_binary = kcalloc(cas_scaler_descr.num_stage, + sizeof(struct ia_css_binary), + GFP_KERNEL); + if (!mycs->yuv_scaler_binary) { + err = -ENOMEM; + return err; + } + mycs->is_output_stage = kcalloc(cas_scaler_descr.num_stage, + sizeof(bool), GFP_KERNEL); + if (!mycs->is_output_stage) { + err = -ENOMEM; + return err; + } + for (i = 0; i < cas_scaler_descr.num_stage; i++) { + struct ia_css_binary_descr yuv_scaler_descr; + + mycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i]; + ia_css_pipe_get_yuvscaler_binarydesc(pipe, + &yuv_scaler_descr, &cas_scaler_descr.in_info[i], + &cas_scaler_descr.out_info[i], + &cas_scaler_descr.internal_out_info[i], + &cas_scaler_descr.vf_info[i]); + err = ia_css_binary_find(&yuv_scaler_descr, + &mycs->yuv_scaler_binary[i]); + if (err) { + kfree(mycs->is_output_stage); + mycs->is_output_stage = NULL; + return err; + } + } + ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr); + } + + { + struct ia_css_binary_descr video_descr; + enum ia_css_frame_format vf_info_format; + + err = ia_css_pipe_get_video_binarydesc(pipe, + &video_descr, &video_in_info, &video_bds_out_info, &video_bin_out_info, + video_vf_info, + pipe->stream->config.left_padding); + if (err) + return err; + + /* + * In the case where video_vf_info is not NULL, this allows + * us to find a potential video library with desired vf format. + * If success, no vf_pp binary is needed. + * If failed, we will look up video binary with YUV_LINE vf format + */ + err = ia_css_binary_find(&video_descr, + &mycs->video_binary); + + if (err) { + /* This will do another video binary lookup later for YUV_LINE format*/ + if (video_vf_info) + need_vf_pp = true; + else + return err; + } else if (video_vf_info) { + /* + * The first video binary lookup is successful, but we + * may still need vf_pp binary based on additional check + */ + num_output_pins = mycs->video_binary.info->num_output_pins; + vf_ds_log2 = mycs->video_binary.vf_downscale_log2; + + /* + * If the binary has dual output pins, we need vf_pp + * if the resolution is different. + */ + need_vf_pp |= ((num_output_pins == 2) && vf_res_different_than_output); + + /* + * If the binary has single output pin, we need vf_pp + * if additional scaling is needed for vf + */ + need_vf_pp |= ((num_output_pins == 1) && + ((video_vf_info->res.width << vf_ds_log2 != pipe_out_info->res.width) || + (video_vf_info->res.height << vf_ds_log2 != pipe_out_info->res.height))); + } + + if (need_vf_pp) { + /* save the current vf_info format for restoration later */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "load_video_binaries() need_vf_pp; find video binary with YUV_LINE again\n"); + + vf_info_format = video_vf_info->format; + + if (!pipe->config.enable_vfpp_bci) + ia_css_frame_info_set_format(video_vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + ia_css_binary_destroy_isp_parameters(&mycs->video_binary); + + err = ia_css_binary_find(&video_descr, + &mycs->video_binary); + + /* restore original vf_info format */ + ia_css_frame_info_set_format(video_vf_info, + vf_info_format); + if (err) + return err; + } + } + + /* + * If a video binary does not use a ref_frame, we set the frame delay + * to 0. This is the case for the 1-stage low-power video binary. + */ + if (!mycs->video_binary.info->sp.enable.ref_frame) + pipe->dvs_frame_delay = 0; + + /* + * The delay latency determines the number of invalid frames after + * a stream is started. + */ + pipe->num_invalid_frames = pipe->dvs_frame_delay; + pipe->info.num_invalid_frames = pipe->num_invalid_frames; + + /* + * Viewfinder frames also decrement num_invalid_frames. If the pipe + * outputs a viewfinder output, then we need double the number of + * invalid frames + */ + if (video_vf_info) + pipe->num_invalid_frames *= 2; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "load_video_binaries() num_invalid_frames=%d dvs_frame_delay=%d\n", + pipe->num_invalid_frames, pipe->dvs_frame_delay); + + /* pqiao TODO: temp hack for PO, should be removed after offline YUVPP is enabled */ +#if !defined(ISP2401) + /* Copy */ + if (!online && !continuous) { + /* + * TODO: what exactly needs doing, prepend the copy binary to + * video base this only on !online? + */ + err = load_copy_binary(pipe, + &mycs->copy_binary, + &mycs->video_binary); + if (err) + return err; + } +#else + (void)continuous; +#endif + + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0] && need_vf_pp) { + struct ia_css_binary_descr vf_pp_descr; + + if (mycs->video_binary.vf_frame_info.format + == IA_CSS_FRAME_FORMAT_YUV_LINE) { + ia_css_pipe_get_vfpp_binarydesc(pipe, &vf_pp_descr, + &mycs->video_binary.vf_frame_info, + pipe_vf_out_info); + } else { + /* + * output from main binary is not yuv line. currently + * this is possible only when bci is enabled on vfpp + * output + */ + assert(pipe->config.enable_vfpp_bci); + ia_css_pipe_get_yuvscaler_binarydesc(pipe, &vf_pp_descr, + &mycs->video_binary.vf_frame_info, + pipe_vf_out_info, NULL, NULL); + } + + err = ia_css_binary_find(&vf_pp_descr, + &mycs->vf_pp_binary); + if (err) + return err; + } + + err = allocate_delay_frames(pipe); + + if (err) + return err; + + if (mycs->video_binary.info->sp.enable.block_output) { + tnr_info = mycs->video_binary.out_frame_info[0]; + + /* Make tnr reference buffers output block height align */ + tnr_info.res.height = CEIL_MUL(tnr_info.res.height, + mycs->video_binary.info->sp.block.output_block_height); + } else { + tnr_info = mycs->video_binary.internal_frame_info; + } + tnr_info.format = IA_CSS_FRAME_FORMAT_YUV_LINE; + tnr_info.raw_bit_depth = SH_CSS_TNR_BIT_DEPTH; + + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) { + if (mycs->tnr_frames[i]) { + ia_css_frame_free(mycs->tnr_frames[i]); + mycs->tnr_frames[i] = NULL; + } + err = ia_css_frame_allocate_from_info( + &mycs->tnr_frames[i], + &tnr_info); + if (err) + return err; + } + IA_CSS_LEAVE_PRIVATE(""); + return 0; +} + +static int +unload_video_binaries(struct ia_css_pipe *pipe) +{ + unsigned int i; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + ia_css_binary_unload(&pipe->pipe_settings.video.copy_binary); + ia_css_binary_unload(&pipe->pipe_settings.video.video_binary); + ia_css_binary_unload(&pipe->pipe_settings.video.vf_pp_binary); + + for (i = 0; i < pipe->pipe_settings.video.num_yuv_scaler; i++) + ia_css_binary_unload(&pipe->pipe_settings.video.yuv_scaler_binary[i]); + + kfree(pipe->pipe_settings.video.is_output_stage); + pipe->pipe_settings.video.is_output_stage = NULL; + kfree(pipe->pipe_settings.video.yuv_scaler_binary); + pipe->pipe_settings.video.yuv_scaler_binary = NULL; + + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +static int video_start(struct ia_css_pipe *pipe) +{ + int err = 0; + struct ia_css_pipe *copy_pipe, *capture_pipe; + enum sh_css_pipe_config_override copy_ovrd; + enum ia_css_input_mode video_pipe_input_mode; + unsigned int thread_id; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + video_pipe_input_mode = pipe->stream->config.mode; + + copy_pipe = pipe->pipe_settings.video.copy_pipe; + capture_pipe = pipe->pipe_settings.video.capture_pipe; + + sh_css_metrics_start_frame(); + + /* multi stream video needs mipi buffers */ + + err = send_mipi_frames(pipe); + if (err) + return err; + + send_raw_frames(pipe); + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + copy_ovrd = 1 << thread_id; + + if (pipe->stream->cont_capt) { + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(capture_pipe), + &thread_id); + copy_ovrd |= 1 << thread_id; + } + + /* Construct and load the copy pipe */ + if (pipe->stream->config.continuous) { + sh_css_sp_init_pipeline(©_pipe->pipeline, + IA_CSS_PIPE_ID_COPY, + (uint8_t)ia_css_pipe_get_pipe_num(copy_pipe), + false, + pipe->stream->config.pixels_per_clock == 2, false, + false, pipe->required_bds_factor, + copy_ovrd, + pipe->stream->config.mode, + &pipe->stream->config.metadata_config, + &pipe->stream->info.metadata_info, + pipe->stream->config.source.port.port); + + /* + * make the video pipe start with mem mode input, copy handles + * the actual mode + */ + video_pipe_input_mode = IA_CSS_INPUT_MODE_MEMORY; + } + + /* Construct and load the capture pipe */ + if (pipe->stream->cont_capt) { + sh_css_sp_init_pipeline(&capture_pipe->pipeline, + IA_CSS_PIPE_ID_CAPTURE, + (uint8_t)ia_css_pipe_get_pipe_num(capture_pipe), + capture_pipe->config.default_capture_config.enable_xnr != 0, + capture_pipe->stream->config.pixels_per_clock == 2, + true, /* continuous */ + false, /* offline */ + capture_pipe->required_bds_factor, + 0, + IA_CSS_INPUT_MODE_MEMORY, + &pipe->stream->config.metadata_config, + &pipe->stream->info.metadata_info, + (enum mipi_port_id)0); + } + + start_pipe(pipe, copy_ovrd, video_pipe_input_mode); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static +int sh_css_pipe_get_viewfinder_frame_info( + struct ia_css_pipe *pipe, + struct ia_css_frame_info *info, + unsigned int idx) +{ + assert(pipe); + assert(info); + + /* We could print the pointer as input arg, and the values as output */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_viewfinder_frame_info() enter: void\n"); + + if (pipe->mode == IA_CSS_PIPE_ID_CAPTURE && + (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER)) + return -EINVAL; + /* offline video does not generate viewfinder output */ + *info = pipe->vf_output_info[idx]; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_viewfinder_frame_info() leave: \ + info.res.width=%d, info.res.height=%d, \ + info.padded_width=%d, info.format=%d, \ + info.raw_bit_depth=%d, info.raw_bayer_order=%d\n", + info->res.width, info->res.height, + info->padded_width, info->format, + info->raw_bit_depth, info->raw_bayer_order); + + return 0; +} + +static int +sh_css_pipe_configure_viewfinder(struct ia_css_pipe *pipe, unsigned int width, + unsigned int height, unsigned int min_width, + enum ia_css_frame_format format, + unsigned int idx) +{ + int err = 0; + + IA_CSS_ENTER_PRIVATE("pipe = %p, width = %d, height = %d, min_width = %d, format = %d, idx = %d\n", + pipe, width, height, min_width, format, idx); + + if (!pipe) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + err = ia_css_util_check_res(width, height); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (pipe->vf_output_info[idx].res.width != width || + pipe->vf_output_info[idx].res.height != height || + pipe->vf_output_info[idx].format != format) + ia_css_frame_info_init(&pipe->vf_output_info[idx], width, height, + format, min_width); + + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +static int load_copy_binaries(struct ia_css_pipe *pipe) +{ + int err = 0; + + assert(pipe); + IA_CSS_ENTER_PRIVATE(""); + + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || + pipe->mode == IA_CSS_PIPE_ID_COPY); + if (pipe->pipe_settings.capture.copy_binary.info) + return 0; + + err = ia_css_frame_check_info(&pipe->output_info[0]); + if (err) + goto ERR; + + err = verify_copy_out_frame_format(pipe); + if (err) + goto ERR; + + err = load_copy_binary(pipe, + &pipe->pipe_settings.capture.copy_binary, + NULL); + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static bool need_capture_pp( + const struct ia_css_pipe *pipe) +{ + const struct ia_css_frame_info *out_info = &pipe->output_info[0]; + + IA_CSS_ENTER_LEAVE_PRIVATE(""); + assert(pipe); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE); + + /* determine whether we need to use the capture_pp binary. + * This is needed for: + * 1. XNR or + * 2. Digital Zoom or + * 3. YUV downscaling + */ + if (pipe->out_yuv_ds_input_info.res.width && + ((pipe->out_yuv_ds_input_info.res.width != out_info->res.width) || + (pipe->out_yuv_ds_input_info.res.height != out_info->res.height))) + return true; + + if (pipe->config.default_capture_config.enable_xnr != 0) + return true; + + if ((pipe->stream->isp_params_configs->dz_config.dx < HRT_GDC_N) || + (pipe->stream->isp_params_configs->dz_config.dy < HRT_GDC_N) || + pipe->config.enable_dz) + return true; + + return false; +} + +static bool need_capt_ldc( + const struct ia_css_pipe *pipe) +{ + IA_CSS_ENTER_LEAVE_PRIVATE(""); + assert(pipe); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE); + return (pipe->extra_config.enable_dvs_6axis) ? true : false; +} + +static int set_num_primary_stages(unsigned int *num, + enum ia_css_pipe_version version) +{ + int err = 0; + + if (!num) + return -EINVAL; + + switch (version) { + case IA_CSS_PIPE_VERSION_2_6_1: + *num = NUM_PRIMARY_HQ_STAGES; + break; + case IA_CSS_PIPE_VERSION_2_2: + case IA_CSS_PIPE_VERSION_1: + *num = NUM_PRIMARY_STAGES; + break; + default: + err = -EINVAL; + break; + } + + return err; +} + +static int load_primary_binaries( + struct ia_css_pipe *pipe) +{ + bool online = false; + bool need_pp = false; + bool need_isp_copy_binary = false; + bool need_ldc = false; +#ifdef ISP2401 + bool sensor = false; +#else + bool memory, continuous; +#endif + struct ia_css_frame_info prim_in_info, + prim_out_info, + capt_pp_out_info, vf_info, + *vf_pp_in_info, *pipe_out_info, + *pipe_vf_out_info, *capt_pp_in_info, + capt_ldc_out_info; + int err = 0; + struct ia_css_capture_settings *mycs; + unsigned int i; + bool need_extra_yuv_scaler = false; + struct ia_css_binary_descr prim_descr[MAX_NUM_PRIMARY_STAGES]; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->stream); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || + pipe->mode == IA_CSS_PIPE_ID_COPY); + + online = pipe->stream->config.online; +#ifdef ISP2401 + sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR); +#else + memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; + continuous = pipe->stream->config.continuous; +#endif + + mycs = &pipe->pipe_settings.capture; + pipe_out_info = &pipe->output_info[0]; + pipe_vf_out_info = &pipe->vf_output_info[0]; + + if (mycs->primary_binary[0].info) + return 0; + + err = set_num_primary_stages(&mycs->num_primary_stage, + pipe->config.isp_pipe_version); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + err = ia_css_util_check_vf_out_info(pipe_out_info, pipe_vf_out_info); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } else { + err = ia_css_frame_check_info(pipe_out_info); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + need_pp = need_capture_pp(pipe); + + /* + * we use the vf output info to get the primary/capture_pp binary + * configured for vf_veceven. It will select the closest downscaling + * factor. + */ + vf_info = *pipe_vf_out_info; + + /* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The + * vf-pp stage has been removed for Skycam in the solution + * provided. The vf-pp stage should be re-introduced when + * required. This should not be considered as a clean solution. + * Proper investigation should be done to come up with the clean + * solution. + */ + ia_css_frame_info_set_format(&vf_info, IA_CSS_FRAME_FORMAT_YUV_LINE); + + /* + * TODO: All this yuv_scaler and capturepp calculation logic + * can be shared later. Capture_pp is also a yuv_scale binary + * with extra XNR funcionality. Therefore, it can be made as the + * first step of the cascade. + */ + capt_pp_out_info = pipe->out_yuv_ds_input_info; + capt_pp_out_info.format = IA_CSS_FRAME_FORMAT_YUV420; + capt_pp_out_info.res.width /= MAX_PREFERRED_YUV_DS_PER_STEP; + capt_pp_out_info.res.height /= MAX_PREFERRED_YUV_DS_PER_STEP; + ia_css_frame_info_set_width(&capt_pp_out_info, capt_pp_out_info.res.width, 0); + + need_extra_yuv_scaler = need_downscaling(capt_pp_out_info.res, + pipe_out_info->res); + + if (need_extra_yuv_scaler) { + struct ia_css_cas_binary_descr cas_scaler_descr = { }; + + err = ia_css_pipe_create_cas_scaler_desc_single_output( + &capt_pp_out_info, + pipe_out_info, + NULL, + &cas_scaler_descr); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + mycs->num_yuv_scaler = cas_scaler_descr.num_stage; + mycs->yuv_scaler_binary = kcalloc(cas_scaler_descr.num_stage, + sizeof(struct ia_css_binary), + GFP_KERNEL); + if (!mycs->yuv_scaler_binary) { + err = -ENOMEM; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + mycs->is_output_stage = kcalloc(cas_scaler_descr.num_stage, + sizeof(bool), GFP_KERNEL); + if (!mycs->is_output_stage) { + err = -ENOMEM; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + for (i = 0; i < cas_scaler_descr.num_stage; i++) { + struct ia_css_binary_descr yuv_scaler_descr; + + mycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i]; + ia_css_pipe_get_yuvscaler_binarydesc(pipe, + &yuv_scaler_descr, &cas_scaler_descr.in_info[i], + &cas_scaler_descr.out_info[i], + &cas_scaler_descr.internal_out_info[i], + &cas_scaler_descr.vf_info[i]); + err = ia_css_binary_find(&yuv_scaler_descr, + &mycs->yuv_scaler_binary[i]); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr); + + } else { + capt_pp_out_info = pipe->output_info[0]; + } + + /* TODO Do we disable ldc for skycam */ + need_ldc = need_capt_ldc(pipe); + + /* we build up the pipeline starting at the end */ + /* Capture post-processing */ + if (need_pp) { + struct ia_css_binary_descr capture_pp_descr; + + capt_pp_in_info = need_ldc ? &capt_ldc_out_info : &prim_out_info; + + ia_css_pipe_get_capturepp_binarydesc(pipe, + &capture_pp_descr, + capt_pp_in_info, + &capt_pp_out_info, + &vf_info); + + err = ia_css_binary_find(&capture_pp_descr, + &mycs->capture_pp_binary); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (need_ldc) { + struct ia_css_binary_descr capt_ldc_descr; + + ia_css_pipe_get_ldc_binarydesc(pipe, + &capt_ldc_descr, + &prim_out_info, + &capt_ldc_out_info); + + err = ia_css_binary_find(&capt_ldc_descr, + &mycs->capture_ldc_binary); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + } else { + prim_out_info = *pipe_out_info; + } + + /* Primary */ + for (i = 0; i < mycs->num_primary_stage; i++) { + struct ia_css_frame_info *local_vf_info = NULL; + + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0] && + (i == mycs->num_primary_stage - 1)) + local_vf_info = &vf_info; + ia_css_pipe_get_primary_binarydesc(pipe, &prim_descr[i], + &prim_in_info, &prim_out_info, + local_vf_info, i); + err = ia_css_binary_find(&prim_descr[i], &mycs->primary_binary[i]); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + /* Viewfinder post-processing */ + if (need_pp) + vf_pp_in_info = &mycs->capture_pp_binary.vf_frame_info; + else + vf_pp_in_info = &mycs->primary_binary[mycs->num_primary_stage - 1].vf_frame_info; + + /* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The + * vf-pp stage has been removed for Skycam in the solution + * provided. The vf-pp stage should be re-introduced when + * required. Thisshould not be considered as a clean solution. + * Proper * investigation should be done to come up with the clean + * solution. + */ + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + struct ia_css_binary_descr vf_pp_descr; + + ia_css_pipe_get_vfpp_binarydesc(pipe, + &vf_pp_descr, vf_pp_in_info, pipe_vf_out_info); + err = ia_css_binary_find(&vf_pp_descr, &mycs->vf_pp_binary); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + err = allocate_delay_frames(pipe); + + if (err) + return err; + +#ifdef ISP2401 + /* + * When the input system is 2401, only the Direct Sensor Mode + * Offline Capture uses the ISP copy binary. + */ + need_isp_copy_binary = !online && sensor; +#else + need_isp_copy_binary = !online && !continuous && !memory; +#endif + + /* ISP Copy */ + if (need_isp_copy_binary) { + err = load_copy_binary(pipe, + &mycs->copy_binary, + &mycs->primary_binary[0]); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + return 0; +} + +static int +allocate_delay_frames(struct ia_css_pipe *pipe) +{ + unsigned int num_delay_frames = 0, i = 0; + unsigned int dvs_frame_delay = 0; + struct ia_css_frame_info ref_info; + int err = 0; + enum ia_css_pipe_id mode = IA_CSS_PIPE_ID_VIDEO; + struct ia_css_frame **delay_frames = NULL; + + IA_CSS_ENTER_PRIVATE(""); + + if (!pipe) { + IA_CSS_ERROR("Invalid args - pipe %p", pipe); + return -EINVAL; + } + + mode = pipe->mode; + dvs_frame_delay = pipe->dvs_frame_delay; + + if (dvs_frame_delay > 0) + num_delay_frames = dvs_frame_delay + 1; + + switch (mode) { + case IA_CSS_PIPE_ID_CAPTURE: { + struct ia_css_capture_settings *mycs_capture = &pipe->pipe_settings.capture; + (void)mycs_capture; + return err; + } + break; + case IA_CSS_PIPE_ID_VIDEO: { + struct ia_css_video_settings *mycs_video = &pipe->pipe_settings.video; + + ref_info = mycs_video->video_binary.internal_frame_info; + + /* + * The ref frame expects + * 1. Y plane + * 2. UV plane with line interleaving, like below + * UUUUUU(width/2 times) VVVVVVVV..(width/2 times) + * + * This format is not YUV420(which has Y, U and V planes). + * Its closer to NV12, except that the UV plane has UV + * interleaving, like UVUVUVUVUVUVUVUVU... + * + * TODO: make this ref_frame format as a separate frame format + */ + ref_info.format = IA_CSS_FRAME_FORMAT_NV12; + delay_frames = mycs_video->delay_frames; + } + break; + case IA_CSS_PIPE_ID_PREVIEW: { + struct ia_css_preview_settings *mycs_preview = &pipe->pipe_settings.preview; + + ref_info = mycs_preview->preview_binary.internal_frame_info; + + /* + * The ref frame expects + * 1. Y plane + * 2. UV plane with line interleaving, like below + * UUUUUU(width/2 times) VVVVVVVV..(width/2 times) + * + * This format is not YUV420(which has Y, U and V planes). + * Its closer to NV12, except that the UV plane has UV + * interleaving, like UVUVUVUVUVUVUVUVU... + * + * TODO: make this ref_frame format as a separate frame format + */ + ref_info.format = IA_CSS_FRAME_FORMAT_NV12; + delay_frames = mycs_preview->delay_frames; + } + break; + default: + return -EINVAL; + } + + ref_info.raw_bit_depth = SH_CSS_REF_BIT_DEPTH; + + assert(num_delay_frames <= MAX_NUM_VIDEO_DELAY_FRAMES); + for (i = 0; i < num_delay_frames; i++) { + err = ia_css_frame_allocate_from_info(&delay_frames[i], &ref_info); + if (err) + return err; + } + IA_CSS_LEAVE_PRIVATE(""); + return 0; +} + +static int load_advanced_binaries(struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info pre_in_info, gdc_in_info, + post_in_info, post_out_info, + vf_info, *vf_pp_in_info, *pipe_out_info, + *pipe_vf_out_info; + bool need_pp; + bool need_isp_copy = true; + int err = 0; + + IA_CSS_ENTER_PRIVATE(""); + + assert(pipe); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || + pipe->mode == IA_CSS_PIPE_ID_COPY); + if (pipe->pipe_settings.capture.pre_isp_binary.info) + return 0; + pipe_out_info = &pipe->output_info[0]; + pipe_vf_out_info = &pipe->vf_output_info[0]; + + vf_info = *pipe_vf_out_info; + err = ia_css_util_check_vf_out_info(pipe_out_info, &vf_info); + if (err) + return err; + need_pp = need_capture_pp(pipe); + + ia_css_frame_info_set_format(&vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + /* we build up the pipeline starting at the end */ + /* Capture post-processing */ + if (need_pp) { + struct ia_css_binary_descr capture_pp_descr; + + ia_css_pipe_get_capturepp_binarydesc(pipe, &capture_pp_descr, + &post_out_info, + pipe_out_info, &vf_info); + err = ia_css_binary_find(&capture_pp_descr, + &pipe->pipe_settings.capture.capture_pp_binary); + if (err) + return err; + } else { + post_out_info = *pipe_out_info; + } + + /* Post-gdc */ + { + struct ia_css_binary_descr post_gdc_descr; + + ia_css_pipe_get_post_gdc_binarydesc(pipe, &post_gdc_descr, + &post_in_info, + &post_out_info, &vf_info); + err = ia_css_binary_find(&post_gdc_descr, + &pipe->pipe_settings.capture.post_isp_binary); + if (err) + return err; + } + + /* Gdc */ + { + struct ia_css_binary_descr gdc_descr; + + ia_css_pipe_get_gdc_binarydesc(pipe, &gdc_descr, &gdc_in_info, + &pipe->pipe_settings.capture.post_isp_binary.in_frame_info); + err = ia_css_binary_find(&gdc_descr, + &pipe->pipe_settings.capture.anr_gdc_binary); + if (err) + return err; + } + pipe->pipe_settings.capture.anr_gdc_binary.left_padding = + pipe->pipe_settings.capture.post_isp_binary.left_padding; + + /* Pre-gdc */ + { + struct ia_css_binary_descr pre_gdc_descr; + + ia_css_pipe_get_pre_gdc_binarydesc(pipe, &pre_gdc_descr, &pre_in_info, + &pipe->pipe_settings.capture.anr_gdc_binary.in_frame_info); + err = ia_css_binary_find(&pre_gdc_descr, + &pipe->pipe_settings.capture.pre_isp_binary); + if (err) + return err; + } + pipe->pipe_settings.capture.pre_isp_binary.left_padding = + pipe->pipe_settings.capture.anr_gdc_binary.left_padding; + + /* Viewfinder post-processing */ + if (need_pp) { + vf_pp_in_info = + &pipe->pipe_settings.capture.capture_pp_binary.vf_frame_info; + } else { + vf_pp_in_info = + &pipe->pipe_settings.capture.post_isp_binary.vf_frame_info; + } + + { + struct ia_css_binary_descr vf_pp_descr; + + ia_css_pipe_get_vfpp_binarydesc(pipe, + &vf_pp_descr, vf_pp_in_info, pipe_vf_out_info); + err = ia_css_binary_find(&vf_pp_descr, + &pipe->pipe_settings.capture.vf_pp_binary); + if (err) + return err; + } + + /* Copy */ +#ifdef ISP2401 + /* For CSI2+, only the direct sensor mode/online requires ISP copy */ + need_isp_copy = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR; +#endif + if (need_isp_copy) + load_copy_binary(pipe, + &pipe->pipe_settings.capture.copy_binary, + &pipe->pipe_settings.capture.pre_isp_binary); + + return err; +} + +static int load_bayer_isp_binaries(struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info pre_isp_in_info, *pipe_out_info; + int err = 0; + struct ia_css_binary_descr pre_de_descr; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || + pipe->mode == IA_CSS_PIPE_ID_COPY); + pipe_out_info = &pipe->output_info[0]; + + if (pipe->pipe_settings.capture.pre_isp_binary.info) + return 0; + + err = ia_css_frame_check_info(pipe_out_info); + if (err) + return err; + + ia_css_pipe_get_pre_de_binarydesc(pipe, &pre_de_descr, + &pre_isp_in_info, + pipe_out_info); + + err = ia_css_binary_find(&pre_de_descr, + &pipe->pipe_settings.capture.pre_isp_binary); + + return err; +} + +static int load_low_light_binaries(struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info pre_in_info, anr_in_info, + post_in_info, post_out_info, + vf_info, *pipe_vf_out_info, *pipe_out_info, + *vf_pp_in_info; + bool need_pp; + bool need_isp_copy = true; + int err = 0; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || + pipe->mode == IA_CSS_PIPE_ID_COPY); + + if (pipe->pipe_settings.capture.pre_isp_binary.info) + return 0; + pipe_vf_out_info = &pipe->vf_output_info[0]; + pipe_out_info = &pipe->output_info[0]; + + vf_info = *pipe_vf_out_info; + err = ia_css_util_check_vf_out_info(pipe_out_info, + &vf_info); + if (err) + return err; + need_pp = need_capture_pp(pipe); + + ia_css_frame_info_set_format(&vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + /* we build up the pipeline starting at the end */ + /* Capture post-processing */ + if (need_pp) { + struct ia_css_binary_descr capture_pp_descr; + + ia_css_pipe_get_capturepp_binarydesc(pipe, &capture_pp_descr, + &post_out_info, + pipe_out_info, &vf_info); + err = ia_css_binary_find(&capture_pp_descr, + &pipe->pipe_settings.capture.capture_pp_binary); + if (err) + return err; + } else { + post_out_info = *pipe_out_info; + } + + /* Post-anr */ + { + struct ia_css_binary_descr post_anr_descr; + + ia_css_pipe_get_post_anr_binarydesc(pipe, + &post_anr_descr, &post_in_info, &post_out_info, &vf_info); + err = ia_css_binary_find(&post_anr_descr, + &pipe->pipe_settings.capture.post_isp_binary); + if (err) + return err; + } + + /* Anr */ + { + struct ia_css_binary_descr anr_descr; + + ia_css_pipe_get_anr_binarydesc(pipe, &anr_descr, &anr_in_info, + &pipe->pipe_settings.capture.post_isp_binary.in_frame_info); + err = ia_css_binary_find(&anr_descr, + &pipe->pipe_settings.capture.anr_gdc_binary); + if (err) + return err; + } + pipe->pipe_settings.capture.anr_gdc_binary.left_padding = + pipe->pipe_settings.capture.post_isp_binary.left_padding; + + /* Pre-anr */ + { + struct ia_css_binary_descr pre_anr_descr; + + ia_css_pipe_get_pre_anr_binarydesc(pipe, &pre_anr_descr, &pre_in_info, + &pipe->pipe_settings.capture.anr_gdc_binary.in_frame_info); + err = ia_css_binary_find(&pre_anr_descr, + &pipe->pipe_settings.capture.pre_isp_binary); + if (err) + return err; + } + pipe->pipe_settings.capture.pre_isp_binary.left_padding = + pipe->pipe_settings.capture.anr_gdc_binary.left_padding; + + /* Viewfinder post-processing */ + if (need_pp) { + vf_pp_in_info = + &pipe->pipe_settings.capture.capture_pp_binary.vf_frame_info; + } else { + vf_pp_in_info = + &pipe->pipe_settings.capture.post_isp_binary.vf_frame_info; + } + + { + struct ia_css_binary_descr vf_pp_descr; + + ia_css_pipe_get_vfpp_binarydesc(pipe, &vf_pp_descr, + vf_pp_in_info, pipe_vf_out_info); + err = ia_css_binary_find(&vf_pp_descr, + &pipe->pipe_settings.capture.vf_pp_binary); + if (err) + return err; + } + + /* Copy */ +#ifdef ISP2401 + /* For CSI2+, only the direct sensor mode/online requires ISP copy */ + need_isp_copy = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR; +#endif + if (need_isp_copy) + err = load_copy_binary(pipe, + &pipe->pipe_settings.capture.copy_binary, + &pipe->pipe_settings.capture.pre_isp_binary); + + return err; +} + +static bool copy_on_sp(struct ia_css_pipe *pipe) +{ + bool rval; + + assert(pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "copy_on_sp() enter:\n"); + + rval = true; + + rval &= (pipe->mode == IA_CSS_PIPE_ID_CAPTURE); + + rval &= (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW); + + rval &= ((pipe->stream->config.input_config.format == + ATOMISP_INPUT_FORMAT_BINARY_8) || + (pipe->config.mode == IA_CSS_PIPE_MODE_COPY)); + + return rval; +} + +static int load_capture_binaries(struct ia_css_pipe *pipe) +{ + int err = 0; + bool must_be_raw; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || + pipe->mode == IA_CSS_PIPE_ID_COPY); + + if (pipe->pipe_settings.capture.primary_binary[0].info) { + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; + } + + /* in primary, advanced,low light or bayer, + the input format must be raw */ + must_be_raw = + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_ADVANCED || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT; + err = ia_css_util_check_input(&pipe->stream->config, must_be_raw, false); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (copy_on_sp(pipe) && + pipe->stream->config.input_config.format == ATOMISP_INPUT_FORMAT_BINARY_8) { + ia_css_frame_info_init( + &pipe->output_info[0], + JPEG_BYTES, + 1, + IA_CSS_FRAME_FORMAT_BINARY_8, + 0); + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; + } + + switch (pipe->config.default_capture_config.mode) { + case IA_CSS_CAPTURE_MODE_RAW: + err = load_copy_binaries(pipe); +#if defined(ISP2401) + if (!err) + pipe->pipe_settings.capture.copy_binary.online = pipe->stream->config.online; +#endif + break; + case IA_CSS_CAPTURE_MODE_BAYER: + err = load_bayer_isp_binaries(pipe); + break; + case IA_CSS_CAPTURE_MODE_PRIMARY: + err = load_primary_binaries(pipe); + break; + case IA_CSS_CAPTURE_MODE_ADVANCED: + err = load_advanced_binaries(pipe); + break; + case IA_CSS_CAPTURE_MODE_LOW_LIGHT: + err = load_low_light_binaries(pipe); + break; + } + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int +unload_capture_binaries(struct ia_css_pipe *pipe) +{ + unsigned int i; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if (!pipe || (pipe->mode != IA_CSS_PIPE_ID_CAPTURE && + pipe->mode != IA_CSS_PIPE_ID_COPY)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + ia_css_binary_unload(&pipe->pipe_settings.capture.copy_binary); + for (i = 0; i < MAX_NUM_PRIMARY_STAGES; i++) + ia_css_binary_unload(&pipe->pipe_settings.capture.primary_binary[i]); + ia_css_binary_unload(&pipe->pipe_settings.capture.pre_isp_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.anr_gdc_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.post_isp_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.capture_pp_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.capture_ldc_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.vf_pp_binary); + + for (i = 0; i < pipe->pipe_settings.capture.num_yuv_scaler; i++) + ia_css_binary_unload(&pipe->pipe_settings.capture.yuv_scaler_binary[i]); + + kfree(pipe->pipe_settings.capture.is_output_stage); + pipe->pipe_settings.capture.is_output_stage = NULL; + kfree(pipe->pipe_settings.capture.yuv_scaler_binary); + pipe->pipe_settings.capture.yuv_scaler_binary = NULL; + + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +static bool +need_downscaling(const struct ia_css_resolution in_res, + const struct ia_css_resolution out_res) +{ + if (in_res.width > out_res.width || in_res.height > out_res.height) + return true; + + return false; +} + +static bool +need_yuv_scaler_stage(const struct ia_css_pipe *pipe) +{ + unsigned int i; + struct ia_css_resolution in_res, out_res; + + bool need_format_conversion = false; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->mode == IA_CSS_PIPE_ID_YUVPP); + + /* TODO: make generic function */ + need_format_conversion = + ((pipe->stream->config.input_config.format == + ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY) && + (pipe->output_info[0].format != IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8)); + + in_res = pipe->config.input_effective_res; + + if (pipe->config.enable_dz) + return true; + + if ((pipe->output_info[0].res.width != 0) && need_format_conversion) + return true; + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + out_res = pipe->output_info[i].res; + + /* A non-zero width means it is a valid output port */ + if ((out_res.width != 0) && need_downscaling(in_res, out_res)) + return true; + } + + return false; +} + +/* + * TODO: it is temporarily created from ia_css_pipe_create_cas_scaler_desc + * which has some hard-coded knowledge which prevents reuse of the function. + * Later, merge this with ia_css_pipe_create_cas_scaler_desc + */ +static int ia_css_pipe_create_cas_scaler_desc_single_output( + struct ia_css_frame_info *cas_scaler_in_info, + struct ia_css_frame_info *cas_scaler_out_info, + struct ia_css_frame_info *cas_scaler_vf_info, + struct ia_css_cas_binary_descr *descr) +{ + unsigned int i; + unsigned int hor_ds_factor = 0, ver_ds_factor = 0; + int err = 0; + struct ia_css_frame_info tmp_in_info; + + unsigned int max_scale_factor_per_stage = MAX_PREFERRED_YUV_DS_PER_STEP; + + assert(cas_scaler_in_info); + assert(cas_scaler_out_info); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipe_create_cas_scaler_desc() enter:\n"); + + /* We assume that this function is used only for single output port case. */ + descr->num_output_stage = 1; + + hor_ds_factor = CEIL_DIV(cas_scaler_in_info->res.width, + cas_scaler_out_info->res.width); + ver_ds_factor = CEIL_DIV(cas_scaler_in_info->res.height, + cas_scaler_out_info->res.height); + /* use the same horizontal and vertical downscaling factor for simplicity */ + assert(hor_ds_factor == ver_ds_factor); + + i = 1; + while (i < hor_ds_factor) { + descr->num_stage++; + i *= max_scale_factor_per_stage; + } + + descr->in_info = kmalloc(descr->num_stage * + sizeof(struct ia_css_frame_info), + GFP_KERNEL); + if (!descr->in_info) { + err = -ENOMEM; + goto ERR; + } + descr->internal_out_info = kmalloc(descr->num_stage * + sizeof(struct ia_css_frame_info), + GFP_KERNEL); + if (!descr->internal_out_info) { + err = -ENOMEM; + goto ERR; + } + descr->out_info = kmalloc(descr->num_stage * + sizeof(struct ia_css_frame_info), + GFP_KERNEL); + if (!descr->out_info) { + err = -ENOMEM; + goto ERR; + } + descr->vf_info = kmalloc(descr->num_stage * + sizeof(struct ia_css_frame_info), + GFP_KERNEL); + if (!descr->vf_info) { + err = -ENOMEM; + goto ERR; + } + descr->is_output_stage = kmalloc(descr->num_stage * sizeof(bool), + GFP_KERNEL); + if (!descr->is_output_stage) { + err = -ENOMEM; + goto ERR; + } + + tmp_in_info = *cas_scaler_in_info; + for (i = 0; i < descr->num_stage; i++) { + descr->in_info[i] = tmp_in_info; + if ((tmp_in_info.res.width / max_scale_factor_per_stage) <= + cas_scaler_out_info->res.width) { + descr->is_output_stage[i] = true; + if ((descr->num_output_stage > 1) && (i != (descr->num_stage - 1))) { + descr->internal_out_info[i].res.width = cas_scaler_out_info->res.width; + descr->internal_out_info[i].res.height = cas_scaler_out_info->res.height; + descr->internal_out_info[i].padded_width = cas_scaler_out_info->padded_width; + descr->internal_out_info[i].format = IA_CSS_FRAME_FORMAT_YUV420; + } else { + assert(i == (descr->num_stage - 1)); + descr->internal_out_info[i].res.width = 0; + descr->internal_out_info[i].res.height = 0; + } + descr->out_info[i].res.width = cas_scaler_out_info->res.width; + descr->out_info[i].res.height = cas_scaler_out_info->res.height; + descr->out_info[i].padded_width = cas_scaler_out_info->padded_width; + descr->out_info[i].format = cas_scaler_out_info->format; + if (cas_scaler_vf_info) { + descr->vf_info[i].res.width = cas_scaler_vf_info->res.width; + descr->vf_info[i].res.height = cas_scaler_vf_info->res.height; + descr->vf_info[i].padded_width = cas_scaler_vf_info->padded_width; + ia_css_frame_info_set_format(&descr->vf_info[i], IA_CSS_FRAME_FORMAT_YUV_LINE); + } else { + descr->vf_info[i].res.width = 0; + descr->vf_info[i].res.height = 0; + descr->vf_info[i].padded_width = 0; + } + } else { + descr->is_output_stage[i] = false; + descr->internal_out_info[i].res.width = tmp_in_info.res.width / + max_scale_factor_per_stage; + descr->internal_out_info[i].res.height = tmp_in_info.res.height / + max_scale_factor_per_stage; + descr->internal_out_info[i].format = IA_CSS_FRAME_FORMAT_YUV420; + ia_css_frame_info_init(&descr->internal_out_info[i], + tmp_in_info.res.width / max_scale_factor_per_stage, + tmp_in_info.res.height / max_scale_factor_per_stage, + IA_CSS_FRAME_FORMAT_YUV420, 0); + descr->out_info[i].res.width = 0; + descr->out_info[i].res.height = 0; + descr->vf_info[i].res.width = 0; + descr->vf_info[i].res.height = 0; + } + tmp_in_info = descr->internal_out_info[i]; + } +ERR: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipe_create_cas_scaler_desc() leave, err=%d\n", + err); + return err; +} + +/* FIXME: merge most of this and single output version */ +static int +ia_css_pipe_create_cas_scaler_desc(struct ia_css_pipe *pipe, + struct ia_css_cas_binary_descr *descr) +{ + struct ia_css_frame_info in_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + struct ia_css_frame_info *out_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame_info *vf_out_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame_info tmp_in_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + unsigned int i, j; + unsigned int hor_scale_factor[IA_CSS_PIPE_MAX_OUTPUT_STAGE], + ver_scale_factor[IA_CSS_PIPE_MAX_OUTPUT_STAGE], + scale_factor = 0; + unsigned int num_stages = 0; + int err = 0; + + unsigned int max_scale_factor_per_stage = MAX_PREFERRED_YUV_DS_PER_STEP; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipe_create_cas_scaler_desc() enter:\n"); + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + out_info[i] = NULL; + vf_out_info[i] = NULL; + hor_scale_factor[i] = 0; + ver_scale_factor[i] = 0; + } + + in_info.res = pipe->config.input_effective_res; + in_info.padded_width = in_info.res.width; + descr->num_output_stage = 0; + /* Find out how much scaling we need for each output */ + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if (pipe->output_info[i].res.width != 0) { + out_info[i] = &pipe->output_info[i]; + if (pipe->vf_output_info[i].res.width != 0) + vf_out_info[i] = &pipe->vf_output_info[i]; + descr->num_output_stage += 1; + } + + if (out_info[i]) { + hor_scale_factor[i] = CEIL_DIV(in_info.res.width, out_info[i]->res.width); + ver_scale_factor[i] = CEIL_DIV(in_info.res.height, out_info[i]->res.height); + /* use the same horizontal and vertical scaling factor for simplicity */ + assert(hor_scale_factor[i] == ver_scale_factor[i]); + scale_factor = 1; + do { + num_stages++; + scale_factor *= max_scale_factor_per_stage; + } while (scale_factor < hor_scale_factor[i]); + + in_info.res = out_info[i]->res; + } + } + + if (need_yuv_scaler_stage(pipe) && (num_stages == 0)) + num_stages = 1; + + descr->num_stage = num_stages; + + descr->in_info = kmalloc_array(descr->num_stage, + sizeof(struct ia_css_frame_info), + GFP_KERNEL); + if (!descr->in_info) { + err = -ENOMEM; + goto ERR; + } + descr->internal_out_info = kmalloc(descr->num_stage * + sizeof(struct ia_css_frame_info), + GFP_KERNEL); + if (!descr->internal_out_info) { + err = -ENOMEM; + goto ERR; + } + descr->out_info = kmalloc(descr->num_stage * + sizeof(struct ia_css_frame_info), + GFP_KERNEL); + if (!descr->out_info) { + err = -ENOMEM; + goto ERR; + } + descr->vf_info = kmalloc(descr->num_stage * + sizeof(struct ia_css_frame_info), + GFP_KERNEL); + if (!descr->vf_info) { + err = -ENOMEM; + goto ERR; + } + descr->is_output_stage = kmalloc(descr->num_stage * sizeof(bool), + GFP_KERNEL); + if (!descr->is_output_stage) { + err = -ENOMEM; + goto ERR; + } + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if (out_info[i]) { + if (i > 0) { + assert((out_info[i - 1]->res.width >= out_info[i]->res.width) && + (out_info[i - 1]->res.height >= out_info[i]->res.height)); + } + } + } + + tmp_in_info.res = pipe->config.input_effective_res; + tmp_in_info.format = IA_CSS_FRAME_FORMAT_YUV420; + for (i = 0, j = 0; i < descr->num_stage; i++) { + assert(j < 2); + assert(out_info[j]); + + descr->in_info[i] = tmp_in_info; + if ((tmp_in_info.res.width / max_scale_factor_per_stage) <= + out_info[j]->res.width) { + descr->is_output_stage[i] = true; + if ((descr->num_output_stage > 1) && (i != (descr->num_stage - 1))) { + descr->internal_out_info[i].res.width = out_info[j]->res.width; + descr->internal_out_info[i].res.height = out_info[j]->res.height; + descr->internal_out_info[i].padded_width = out_info[j]->padded_width; + descr->internal_out_info[i].format = IA_CSS_FRAME_FORMAT_YUV420; + } else { + assert(i == (descr->num_stage - 1)); + descr->internal_out_info[i].res.width = 0; + descr->internal_out_info[i].res.height = 0; + } + descr->out_info[i].res.width = out_info[j]->res.width; + descr->out_info[i].res.height = out_info[j]->res.height; + descr->out_info[i].padded_width = out_info[j]->padded_width; + descr->out_info[i].format = out_info[j]->format; + if (vf_out_info[j]) { + descr->vf_info[i].res.width = vf_out_info[j]->res.width; + descr->vf_info[i].res.height = vf_out_info[j]->res.height; + descr->vf_info[i].padded_width = vf_out_info[j]->padded_width; + ia_css_frame_info_set_format(&descr->vf_info[i], IA_CSS_FRAME_FORMAT_YUV_LINE); + } else { + descr->vf_info[i].res.width = 0; + descr->vf_info[i].res.height = 0; + descr->vf_info[i].padded_width = 0; + } + j++; + } else { + descr->is_output_stage[i] = false; + descr->internal_out_info[i].res.width = tmp_in_info.res.width / + max_scale_factor_per_stage; + descr->internal_out_info[i].res.height = tmp_in_info.res.height / + max_scale_factor_per_stage; + descr->internal_out_info[i].format = IA_CSS_FRAME_FORMAT_YUV420; + ia_css_frame_info_init(&descr->internal_out_info[i], + tmp_in_info.res.width / max_scale_factor_per_stage, + tmp_in_info.res.height / max_scale_factor_per_stage, + IA_CSS_FRAME_FORMAT_YUV420, 0); + descr->out_info[i].res.width = 0; + descr->out_info[i].res.height = 0; + descr->vf_info[i].res.width = 0; + descr->vf_info[i].res.height = 0; + } + tmp_in_info = descr->internal_out_info[i]; + } +ERR: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipe_create_cas_scaler_desc() leave, err=%d\n", + err); + return err; +} + +static void ia_css_pipe_destroy_cas_scaler_desc(struct ia_css_cas_binary_descr + *descr) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipe_destroy_cas_scaler_desc() enter:\n"); + kfree(descr->in_info); + descr->in_info = NULL; + kfree(descr->internal_out_info); + descr->internal_out_info = NULL; + kfree(descr->out_info); + descr->out_info = NULL; + kfree(descr->vf_info); + descr->vf_info = NULL; + kfree(descr->is_output_stage); + descr->is_output_stage = NULL; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipe_destroy_cas_scaler_desc() leave\n"); +} + +static int +load_yuvpp_binaries(struct ia_css_pipe *pipe) +{ + int err = 0; + bool need_scaler = false; + struct ia_css_frame_info *vf_pp_in_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_yuvpp_settings *mycs; + struct ia_css_binary *next_binary; + struct ia_css_cas_binary_descr cas_scaler_descr = { }; + unsigned int i, j; + bool need_isp_copy_binary = false; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->stream); + assert(pipe->mode == IA_CSS_PIPE_ID_YUVPP); + + if (pipe->pipe_settings.yuvpp.copy_binary.info) + goto ERR; + + /* Set both must_be_raw and must_be_yuv to false then yuvpp can take rgb inputs */ + err = ia_css_util_check_input(&pipe->stream->config, false, false); + if (err) + goto ERR; + + mycs = &pipe->pipe_settings.yuvpp; + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if (pipe->vf_output_info[i].res.width != 0) { + err = ia_css_util_check_vf_out_info(&pipe->output_info[i], + &pipe->vf_output_info[i]); + if (err) + goto ERR; + } + vf_pp_in_info[i] = NULL; + } + + need_scaler = need_yuv_scaler_stage(pipe); + + /* we build up the pipeline starting at the end */ + /* Capture post-processing */ + if (need_scaler) { + struct ia_css_binary_descr yuv_scaler_descr; + + err = ia_css_pipe_create_cas_scaler_desc(pipe, + &cas_scaler_descr); + if (err) + goto ERR; + mycs->num_output = cas_scaler_descr.num_output_stage; + mycs->num_yuv_scaler = cas_scaler_descr.num_stage; + mycs->yuv_scaler_binary = kcalloc(cas_scaler_descr.num_stage, + sizeof(struct ia_css_binary), + GFP_KERNEL); + if (!mycs->yuv_scaler_binary) { + err = -ENOMEM; + goto ERR; + } + mycs->is_output_stage = kcalloc(cas_scaler_descr.num_stage, + sizeof(bool), GFP_KERNEL); + if (!mycs->is_output_stage) { + err = -ENOMEM; + goto ERR; + } + for (i = 0; i < cas_scaler_descr.num_stage; i++) { + mycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i]; + ia_css_pipe_get_yuvscaler_binarydesc(pipe, + &yuv_scaler_descr, + &cas_scaler_descr.in_info[i], + &cas_scaler_descr.out_info[i], + &cas_scaler_descr.internal_out_info[i], + &cas_scaler_descr.vf_info[i]); + err = ia_css_binary_find(&yuv_scaler_descr, + &mycs->yuv_scaler_binary[i]); + if (err) + goto ERR; + } + ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr); + } else { + mycs->num_output = 1; + } + + if (need_scaler) + next_binary = &mycs->yuv_scaler_binary[0]; + else + next_binary = NULL; + +#if defined(ISP2401) + /* + * NOTES + * - Why does the "yuvpp" pipe needs "isp_copy_binary" (i.e. ISP Copy) when + * its input is "ATOMISP_INPUT_FORMAT_YUV422_8"? + * + * In most use cases, the first stage in the "yuvpp" pipe is the "yuv_scale_ + * binary". However, the "yuv_scale_binary" does NOT support the input-frame + * format as "IA_CSS_STREAM _FORMAT_YUV422_8". + * + * Hence, the "isp_copy_binary" is required to be present in front of the "yuv + * _scale_binary". It would translate the input-frame to the frame formats that + * are supported by the "yuv_scale_binary". + * + * Please refer to "FrameWork/css/isp/pipes/capture_pp/capture_pp_1.0/capture_ + * pp_defs.h" for the list of input-frame formats that are supported by the + * "yuv_scale_binary". + */ + need_isp_copy_binary = + (pipe->stream->config.input_config.format == ATOMISP_INPUT_FORMAT_YUV422_8); +#else /* !ISP2401 */ + need_isp_copy_binary = true; +#endif /* ISP2401 */ + + if (need_isp_copy_binary) { + err = load_copy_binary(pipe, + &mycs->copy_binary, + next_binary); + + if (err) + goto ERR; + + /* + * NOTES + * - Why is "pipe->pipe_settings.capture.copy_binary.online" specified? + * + * In some use cases, the first stage in the "yuvpp" pipe is the + * "isp_copy_binary". The "isp_copy_binary" is designed to process + * the input from either the system DDR or from the IPU internal VMEM. + * So it provides the flag "online" to specify where its input is from, + * i.e.: + * + * (1) "online <= true", the input is from the IPU internal VMEM. + * (2) "online <= false", the input is from the system DDR. + * + * In other use cases, the first stage in the "yuvpp" pipe is the + * "yuv_scale_binary". "The "yuv_scale_binary" is designed to process the + * input ONLY from the system DDR. So it does not provide the flag "online" + * to specify where its input is from. + */ + pipe->pipe_settings.capture.copy_binary.online = pipe->stream->config.online; + } + + /* Viewfinder post-processing */ + if (need_scaler) { + for (i = 0, j = 0; i < mycs->num_yuv_scaler; i++) { + if (mycs->is_output_stage[i]) { + assert(j < 2); + vf_pp_in_info[j] = + &mycs->yuv_scaler_binary[i].vf_frame_info; + j++; + } + } + mycs->num_vf_pp = j; + } else { + vf_pp_in_info[0] = + &mycs->copy_binary.vf_frame_info; + for (i = 1; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) + vf_pp_in_info[i] = NULL; + + mycs->num_vf_pp = 1; + } + mycs->vf_pp_binary = kcalloc(mycs->num_vf_pp, + sizeof(struct ia_css_binary), + GFP_KERNEL); + if (!mycs->vf_pp_binary) { + err = -ENOMEM; + goto ERR; + } + + { + struct ia_css_binary_descr vf_pp_descr; + + for (i = 0; i < mycs->num_vf_pp; i++) { + if (pipe->vf_output_info[i].res.width != 0) { + ia_css_pipe_get_vfpp_binarydesc(pipe, + &vf_pp_descr, vf_pp_in_info[i], &pipe->vf_output_info[i]); + err = ia_css_binary_find(&vf_pp_descr, &mycs->vf_pp_binary[i]); + if (err) + goto ERR; + } + } + } + + if (err) + goto ERR; + +ERR: + if (need_scaler) + ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "load_yuvpp_binaries() leave, err=%d\n", + err); + return err; +} + +static int +unload_yuvpp_binaries(struct ia_css_pipe *pipe) +{ + unsigned int i; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + ia_css_binary_unload(&pipe->pipe_settings.yuvpp.copy_binary); + for (i = 0; i < pipe->pipe_settings.yuvpp.num_yuv_scaler; i++) + ia_css_binary_unload(&pipe->pipe_settings.yuvpp.yuv_scaler_binary[i]); + + for (i = 0; i < pipe->pipe_settings.yuvpp.num_vf_pp; i++) + ia_css_binary_unload(&pipe->pipe_settings.yuvpp.vf_pp_binary[i]); + + kfree(pipe->pipe_settings.yuvpp.is_output_stage); + pipe->pipe_settings.yuvpp.is_output_stage = NULL; + kfree(pipe->pipe_settings.yuvpp.yuv_scaler_binary); + pipe->pipe_settings.yuvpp.yuv_scaler_binary = NULL; + kfree(pipe->pipe_settings.yuvpp.vf_pp_binary); + pipe->pipe_settings.yuvpp.vf_pp_binary = NULL; + + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +static int yuvpp_start(struct ia_css_pipe *pipe) +{ + int err = 0; + enum sh_css_pipe_config_override copy_ovrd; + enum ia_css_input_mode yuvpp_pipe_input_mode; + unsigned int thread_id; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + yuvpp_pipe_input_mode = pipe->stream->config.mode; + + sh_css_metrics_start_frame(); + + /* multi stream video needs mipi buffers */ + + err = send_mipi_frames(pipe); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + copy_ovrd = 1 << thread_id; + + start_pipe(pipe, copy_ovrd, yuvpp_pipe_input_mode); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int +sh_css_pipe_unload_binaries(struct ia_css_pipe *pipe) +{ + int err = 0; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if (!pipe) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + /* PIPE_MODE_COPY has no binaries, but has output frames to outside*/ + if (pipe->config.mode == IA_CSS_PIPE_MODE_COPY) { + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; + } + + switch (pipe->mode) { + case IA_CSS_PIPE_ID_PREVIEW: + err = unload_preview_binaries(pipe); + break; + case IA_CSS_PIPE_ID_VIDEO: + err = unload_video_binaries(pipe); + break; + case IA_CSS_PIPE_ID_CAPTURE: + err = unload_capture_binaries(pipe); + break; + case IA_CSS_PIPE_ID_YUVPP: + err = unload_yuvpp_binaries(pipe); + break; + default: + break; + } + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int +sh_css_pipe_load_binaries(struct ia_css_pipe *pipe) +{ + int err = 0; + + assert(pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "sh_css_pipe_load_binaries() enter:\n"); + + /* PIPE_MODE_COPY has no binaries, but has output frames to outside*/ + if (pipe->config.mode == IA_CSS_PIPE_MODE_COPY) + return err; + + switch (pipe->mode) { + case IA_CSS_PIPE_ID_PREVIEW: + err = load_preview_binaries(pipe); + break; + case IA_CSS_PIPE_ID_VIDEO: + err = load_video_binaries(pipe); + break; + case IA_CSS_PIPE_ID_CAPTURE: + err = load_capture_binaries(pipe); + break; + case IA_CSS_PIPE_ID_YUVPP: + err = load_yuvpp_binaries(pipe); + break; + default: + err = -EINVAL; + break; + } + if (err) { + if (sh_css_pipe_unload_binaries(pipe)) { + /* + * currently css does not support multiple error + * returns in a single function, using -EINVAL in + * this case + */ + err = -EINVAL; + } + } + return err; +} + +static int +create_host_yuvpp_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me; + int err = 0; + struct ia_css_pipeline_stage *vf_pp_stage = NULL, + *copy_stage = NULL, + *yuv_scaler_stage = NULL; + struct ia_css_binary *copy_binary, + *vf_pp_binary, + *yuv_scaler_binary; + bool need_scaler = false; + unsigned int num_stage, num_output_stage; + unsigned int i, j; + + struct ia_css_frame *in_frame = NULL; + struct ia_css_frame *out_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame *bin_out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame *vf_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_pipeline_stage_desc stage_desc; + bool need_in_frameinfo_memory = false; +#ifdef ISP2401 + bool sensor = false; + bool buffered_sensor = false; + bool online = false; + bool continuous = false; +#endif + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + me = &pipe->pipeline; + ia_css_pipeline_clean(me); + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + out_frame[i] = NULL; + vf_frame[i] = NULL; + } + ia_css_pipe_util_create_output_frames(bin_out_frame); + num_stage = pipe->pipe_settings.yuvpp.num_yuv_scaler; + num_output_stage = pipe->pipe_settings.yuvpp.num_output; + +#ifdef ISP2401 + /* + * When the input system is 2401, always enable 'in_frameinfo_memory' + * except for the following: + * - Direct Sensor Mode Online Capture + * - Direct Sensor Mode Continuous Capture + * - Buffered Sensor Mode Continuous Capture + */ + sensor = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR; + buffered_sensor = pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR; + online = pipe->stream->config.online; + continuous = pipe->stream->config.continuous; + need_in_frameinfo_memory = + !((sensor && (online || continuous)) || (buffered_sensor && continuous)); +#else + /* Construct in_frame info (only in case we have dynamic input */ + need_in_frameinfo_memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + /* + * the input frame can come from: + * + * a) memory: connect yuvscaler to me->in_frame + * b) sensor, via copy binary: connect yuvscaler to copy binary later + * on + */ + if (need_in_frameinfo_memory) { + /* TODO: improve for different input formats. */ + + /* + * "pipe->stream->config.input_config.format" represents the sensor output + * frame format, e.g. YUV422 8-bit. + * + * "in_frame_format" represents the imaging pipe's input frame format, e.g. + * Bayer-Quad RAW. + */ + int in_frame_format; + + if (pipe->stream->config.input_config.format == + ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY) { + in_frame_format = IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8; + } else if (pipe->stream->config.input_config.format == + ATOMISP_INPUT_FORMAT_YUV422_8) { + /* + * When the sensor output frame format is "ATOMISP_INPUT_FORMAT_YUV422_8", + * the "isp_copy_var" binary is selected as the first stage in the yuvpp + * pipe. + * + * For the "isp_copy_var" binary, it reads the YUV422-8 pixels from + * the frame buffer (at DDR) to the frame-line buffer (at VMEM). + * + * By now, the "isp_copy_var" binary does NOT provide a separated + * frame-line buffer to store the YUV422-8 pixels. Instead, it stores + * the YUV422-8 pixels in the frame-line buffer which is designed to + * store the Bayer-Quad RAW pixels. + * + * To direct the "isp_copy_var" binary reading from the RAW frame-line + * buffer, its input frame format must be specified as "IA_CSS_FRAME_ + * FORMAT_RAW". + */ + in_frame_format = IA_CSS_FRAME_FORMAT_RAW; + } else { + in_frame_format = IA_CSS_FRAME_FORMAT_NV12; + } + + err = init_in_frameinfo_memory_defaults(pipe, + &me->in_frame, + in_frame_format); + + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + in_frame = &me->in_frame; + } else { + in_frame = NULL; + } + + for (i = 0; i < num_output_stage; i++) { + assert(i < IA_CSS_PIPE_MAX_OUTPUT_STAGE); + if (pipe->output_info[i].res.width != 0) { + err = init_out_frameinfo_defaults(pipe, &me->out_frame[i], i); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + out_frame[i] = &me->out_frame[i]; + } + + /* Construct vf_frame info (only in case we have VF) */ + if (pipe->vf_output_info[i].res.width != 0) { + err = init_vf_frameinfo_defaults(pipe, &me->vf_frame[i], i); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + vf_frame[i] = &me->vf_frame[i]; + } + } + + copy_binary = &pipe->pipe_settings.yuvpp.copy_binary; + vf_pp_binary = pipe->pipe_settings.yuvpp.vf_pp_binary; + yuv_scaler_binary = pipe->pipe_settings.yuvpp.yuv_scaler_binary; + need_scaler = need_yuv_scaler_stage(pipe); + + if (pipe->pipe_settings.yuvpp.copy_binary.info) { + struct ia_css_frame *in_frame_local = NULL; + +#ifdef ISP2401 + /* After isp copy is enabled in_frame needs to be passed. */ + if (!online) + in_frame_local = in_frame; +#endif + + if (need_scaler) { + ia_css_pipe_util_set_output_frames(bin_out_frame, + 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + copy_binary, + bin_out_frame, + in_frame_local, + NULL); + } else { + ia_css_pipe_util_set_output_frames(bin_out_frame, + 0, out_frame[0]); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + copy_binary, + bin_out_frame, + in_frame_local, + NULL); + } + + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ©_stage); + + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (copy_stage) { + /* if we use yuv scaler binary, vf output should be from there */ + copy_stage->args.copy_vf = !need_scaler; + /* for yuvpp pipe, it should always be enabled */ + copy_stage->args.copy_output = true; + /* connect output of copy binary to input of yuv scaler */ + in_frame = copy_stage->args.out_frame[0]; + } + } + + if (need_scaler) { + struct ia_css_frame *tmp_out_frame = NULL; + struct ia_css_frame *tmp_vf_frame = NULL; + struct ia_css_frame *tmp_in_frame = in_frame; + + for (i = 0, j = 0; i < num_stage; i++) { + assert(j < num_output_stage); + if (pipe->pipe_settings.yuvpp.is_output_stage[i]) { + tmp_out_frame = out_frame[j]; + tmp_vf_frame = vf_frame[j]; + } else { + tmp_out_frame = NULL; + tmp_vf_frame = NULL; + } + + err = add_yuv_scaler_stage(pipe, me, tmp_in_frame, + tmp_out_frame, + NULL, + &yuv_scaler_binary[i], + &yuv_scaler_stage); + + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* we use output port 1 as internal output port */ + tmp_in_frame = yuv_scaler_stage->args.out_frame[1]; + if (pipe->pipe_settings.yuvpp.is_output_stage[i]) { + if (tmp_vf_frame && (tmp_vf_frame->frame_info.res.width != 0)) { + in_frame = yuv_scaler_stage->args.out_vf_frame; + err = add_vf_pp_stage(pipe, in_frame, + tmp_vf_frame, + &vf_pp_binary[j], + &vf_pp_stage); + + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + j++; + } + } + } else if (copy_stage) { + if (vf_frame[0] && vf_frame[0]->frame_info.res.width != 0) { + in_frame = copy_stage->args.out_vf_frame; + err = add_vf_pp_stage(pipe, in_frame, vf_frame[0], + &vf_pp_binary[0], &vf_pp_stage); + } + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + ia_css_pipeline_finalize_stages(&pipe->pipeline, + pipe->stream->config.continuous); + + IA_CSS_LEAVE_ERR_PRIVATE(0); + + return 0; +} + +static int +create_host_copy_pipeline(struct ia_css_pipe *pipe, + unsigned int max_input_width, + struct ia_css_frame *out_frame) +{ + struct ia_css_pipeline *me; + int err = 0; + struct ia_css_pipeline_stage_desc stage_desc; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_copy_pipeline() enter:\n"); + + /* pipeline already created as part of create_host_pipeline_structure */ + me = &pipe->pipeline; + ia_css_pipeline_clean(me); + + /* Construct out_frame info */ + out_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + + if (copy_on_sp(pipe) && + pipe->stream->config.input_config.format == ATOMISP_INPUT_FORMAT_BINARY_8) { + ia_css_frame_info_init(&out_frame->frame_info, JPEG_BYTES, 1, + IA_CSS_FRAME_FORMAT_BINARY_8, 0); + } else if (out_frame->frame_info.format == IA_CSS_FRAME_FORMAT_RAW) { + out_frame->frame_info.raw_bit_depth = + ia_css_pipe_util_pipe_input_format_bpp(pipe); + } + + me->num_stages = 1; + me->pipe_id = IA_CSS_PIPE_ID_COPY; + pipe->mode = IA_CSS_PIPE_ID_COPY; + + ia_css_pipe_get_sp_func_stage_desc(&stage_desc, out_frame, + IA_CSS_PIPELINE_RAW_COPY, + max_input_width); + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, NULL); + + ia_css_pipeline_finalize_stages(&pipe->pipeline, + pipe->stream->config.continuous); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_copy_pipeline() leave:\n"); + + return err; +} + +static int +create_host_isyscopy_capture_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me = &pipe->pipeline; + int err = 0; + struct ia_css_pipeline_stage_desc stage_desc; + struct ia_css_frame *out_frame = &me->out_frame[0]; + struct ia_css_pipeline_stage *out_stage = NULL; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + unsigned int max_input_width = MAX_VECTORS_PER_INPUT_LINE_CONT * ISP_VEC_NELEMS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_isyscopy_capture_pipeline() enter:\n"); + ia_css_pipeline_clean(me); + + /* Construct out_frame info */ + err = sh_css_pipe_get_output_frame_info(pipe, &out_frame->frame_info, 0); + if (err) + return err; + out_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, thread_id, &queue_id); + out_frame->dynamic_queue_id = queue_id; + out_frame->buf_type = IA_CSS_BUFFER_TYPE_OUTPUT_FRAME; + + me->num_stages = 1; + me->pipe_id = IA_CSS_PIPE_ID_CAPTURE; + pipe->mode = IA_CSS_PIPE_ID_CAPTURE; + ia_css_pipe_get_sp_func_stage_desc(&stage_desc, out_frame, + IA_CSS_PIPELINE_ISYS_COPY, + max_input_width); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, &out_stage); + if (err) + return err; + + ia_css_pipeline_finalize_stages(me, pipe->stream->config.continuous); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_isyscopy_capture_pipeline() leave:\n"); + + return err; +} + +static int +create_host_regular_capture_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me; + int err = 0; + enum ia_css_capture_mode mode; + struct ia_css_pipeline_stage *current_stage = NULL; + struct ia_css_pipeline_stage *yuv_scaler_stage = NULL; + struct ia_css_binary *copy_binary, + *primary_binary[MAX_NUM_PRIMARY_STAGES], + *vf_pp_binary, + *pre_isp_binary, + *anr_gdc_binary, + *post_isp_binary, + *yuv_scaler_binary, + *capture_pp_binary, + *capture_ldc_binary; + bool need_pp = false; + bool raw; + + struct ia_css_frame *in_frame; + struct ia_css_frame *out_frame; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame *vf_frame; + struct ia_css_pipeline_stage_desc stage_desc; + bool need_in_frameinfo_memory = false; +#ifdef ISP2401 + bool sensor = false; + bool buffered_sensor = false; + bool online = false; + bool continuous = false; +#endif + unsigned int i, num_yuv_scaler, num_primary_stage; + bool need_yuv_pp = false; + bool *is_output_stage = NULL; + bool need_ldc = false; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe); + assert(pipe->stream); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || + pipe->mode == IA_CSS_PIPE_ID_COPY); + + me = &pipe->pipeline; + mode = pipe->config.default_capture_config.mode; + raw = (mode == IA_CSS_CAPTURE_MODE_RAW); + ia_css_pipeline_clean(me); + ia_css_pipe_util_create_output_frames(out_frames); + +#ifdef ISP2401 + /* + * When the input system is 2401, always enable 'in_frameinfo_memory' + * except for the following: + * - Direct Sensor Mode Online Capture + * - Direct Sensor Mode Online Capture + * - Direct Sensor Mode Continuous Capture + * - Buffered Sensor Mode Continuous Capture + */ + sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR); + buffered_sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR); + online = pipe->stream->config.online; + continuous = pipe->stream->config.continuous; + need_in_frameinfo_memory = + !((sensor && (online || continuous)) || (buffered_sensor && (online || continuous))); +#else + /* Construct in_frame info (only in case we have dynamic input */ + need_in_frameinfo_memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + if (need_in_frameinfo_memory) { + err = init_in_frameinfo_memory_defaults(pipe, &me->in_frame, + IA_CSS_FRAME_FORMAT_RAW); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + in_frame = &me->in_frame; + } else { + in_frame = NULL; + } + + err = init_out_frameinfo_defaults(pipe, &me->out_frame[0], 0); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + out_frame = &me->out_frame[0]; + + /* Construct vf_frame info (only in case we have VF) */ + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + if (mode == IA_CSS_CAPTURE_MODE_RAW || mode == IA_CSS_CAPTURE_MODE_BAYER) { + /* These modes don't support viewfinder output */ + vf_frame = NULL; + } else { + init_vf_frameinfo_defaults(pipe, &me->vf_frame[0], 0); + vf_frame = &me->vf_frame[0]; + } + } else { + vf_frame = NULL; + } + + copy_binary = &pipe->pipe_settings.capture.copy_binary; + num_primary_stage = pipe->pipe_settings.capture.num_primary_stage; + if ((num_primary_stage == 0) && (mode == IA_CSS_CAPTURE_MODE_PRIMARY)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + for (i = 0; i < num_primary_stage; i++) + primary_binary[i] = &pipe->pipe_settings.capture.primary_binary[i]; + + vf_pp_binary = &pipe->pipe_settings.capture.vf_pp_binary; + pre_isp_binary = &pipe->pipe_settings.capture.pre_isp_binary; + anr_gdc_binary = &pipe->pipe_settings.capture.anr_gdc_binary; + post_isp_binary = &pipe->pipe_settings.capture.post_isp_binary; + capture_pp_binary = &pipe->pipe_settings.capture.capture_pp_binary; + yuv_scaler_binary = pipe->pipe_settings.capture.yuv_scaler_binary; + num_yuv_scaler = pipe->pipe_settings.capture.num_yuv_scaler; + is_output_stage = pipe->pipe_settings.capture.is_output_stage; + capture_ldc_binary = &pipe->pipe_settings.capture.capture_ldc_binary; + + need_pp = (need_capture_pp(pipe) || pipe->output_stage) && + mode != IA_CSS_CAPTURE_MODE_RAW && + mode != IA_CSS_CAPTURE_MODE_BAYER; + need_yuv_pp = (yuv_scaler_binary && yuv_scaler_binary->info); + need_ldc = (capture_ldc_binary && capture_ldc_binary->info); + + if (pipe->pipe_settings.capture.copy_binary.info) { + if (raw) { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); +#if defined(ISP2401) + if (!continuous) { + ia_css_pipe_get_generic_stage_desc(&stage_desc, + copy_binary, + out_frames, + in_frame, + NULL); + } else { + in_frame = pipe->stream->last_pipe->continuous_frames[0]; + ia_css_pipe_get_generic_stage_desc(&stage_desc, + copy_binary, + out_frames, + in_frame, + NULL); + } +#else + ia_css_pipe_get_generic_stage_desc(&stage_desc, + copy_binary, + out_frames, + NULL, NULL); +#endif + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, + in_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + copy_binary, + out_frames, + NULL, NULL); + } + + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ¤t_stage); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } else if (pipe->stream->config.continuous) { + in_frame = pipe->stream->last_pipe->continuous_frames[0]; + } + + if (mode == IA_CSS_CAPTURE_MODE_PRIMARY) { + struct ia_css_frame *local_in_frame = NULL; + struct ia_css_frame *local_out_frame = NULL; + + for (i = 0; i < num_primary_stage; i++) { + if (i == 0) + local_in_frame = in_frame; + else + local_in_frame = NULL; +#ifndef ISP2401 + if (!need_pp && (i == num_primary_stage - 1)) +#else + if (!need_pp && (i == num_primary_stage - 1) && !need_ldc) +#endif + local_out_frame = out_frame; + else + local_out_frame = NULL; + ia_css_pipe_util_set_output_frames(out_frames, 0, local_out_frame); + /* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The + * vf-pp stage has been removed from Skycam in the solution + * provided. The vf-pp stage should be re-introduced when + * required. This * should not be considered as a clean solution. + * Proper investigation should be done to come up with the clean + * solution. + */ + ia_css_pipe_get_generic_stage_desc(&stage_desc, + primary_binary[i], + out_frames, + local_in_frame, + NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ¤t_stage); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + /* If we use copy iso primary, the input must be yuv iso raw */ + current_stage->args.copy_vf = + primary_binary[0]->info->sp.pipeline.mode == + IA_CSS_BINARY_MODE_COPY; + current_stage->args.copy_output = current_stage->args.copy_vf; + } else if (mode == IA_CSS_CAPTURE_MODE_ADVANCED || + mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, pre_isp_binary, + out_frames, in_frame, NULL); + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + NULL); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, anr_gdc_binary, + out_frames, NULL, NULL); + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + NULL); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (need_pp) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + post_isp_binary, + out_frames, + NULL, NULL); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, + out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + post_isp_binary, + out_frames, + NULL, NULL); + } + + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + ¤t_stage); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } else if (mode == IA_CSS_CAPTURE_MODE_BAYER) { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, pre_isp_binary, + out_frames, in_frame, NULL); + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, + NULL); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + if (need_pp && current_stage) { + struct ia_css_frame *local_in_frame = NULL; + + local_in_frame = current_stage->args.out_frame[0]; + + if (need_ldc) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + capture_ldc_binary, + out_frames, + local_in_frame, + NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ¤t_stage); + local_in_frame = current_stage->args.out_frame[0]; + } + err = add_capture_pp_stage(pipe, me, local_in_frame, + need_yuv_pp ? NULL : out_frame, + capture_pp_binary, + ¤t_stage); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + if (need_yuv_pp && current_stage) { + struct ia_css_frame *tmp_in_frame = current_stage->args.out_frame[0]; + struct ia_css_frame *tmp_out_frame = NULL; + + for (i = 0; i < num_yuv_scaler; i++) { + if (is_output_stage[i]) + tmp_out_frame = out_frame; + else + tmp_out_frame = NULL; + + err = add_yuv_scaler_stage(pipe, me, tmp_in_frame, + tmp_out_frame, NULL, + &yuv_scaler_binary[i], + &yuv_scaler_stage); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* we use output port 1 as internal output port */ + tmp_in_frame = yuv_scaler_stage->args.out_frame[1]; + } + } + + /* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The vf-pp + * stage has been removed from Skycam in the solution provided. + * The vf-pp stage should be re-introduced when required. This + * should not be considered as a clean solution. Proper + * investigation should be done to come up with the clean solution. + */ + if (mode != IA_CSS_CAPTURE_MODE_RAW && + mode != IA_CSS_CAPTURE_MODE_BAYER && + current_stage && vf_frame) { + in_frame = current_stage->args.out_vf_frame; + err = add_vf_pp_stage(pipe, in_frame, vf_frame, vf_pp_binary, + ¤t_stage); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + ia_css_pipeline_finalize_stages(&pipe->pipeline, pipe->stream->config.continuous); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_regular_capture_pipeline() leave:\n"); + + return 0; +} + +static int +create_host_capture_pipeline(struct ia_css_pipe *pipe) +{ + int err = 0; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if (pipe->config.mode == IA_CSS_PIPE_MODE_COPY) + err = create_host_isyscopy_capture_pipeline(pipe); + else + err = create_host_regular_capture_pipeline(pipe); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + + return err; +} + +static int capture_start(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me; + unsigned int thread_id; + + int err = 0; + enum sh_css_pipe_config_override copy_ovrd; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if (!pipe) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + me = &pipe->pipeline; + + if ((pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER) && + (pipe->config.mode != IA_CSS_PIPE_MODE_COPY)) { + if (copy_on_sp(pipe)) { + err = start_copy_on_sp(pipe, &me->out_frame[0]); + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + +#if !defined(ISP2401) + /* old isys: need to send_mipi_frames() in all pipe modes */ + err = send_mipi_frames(pipe); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } +#else + if (pipe->config.mode != IA_CSS_PIPE_MODE_COPY) { + err = send_mipi_frames(pipe); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } +#endif + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + copy_ovrd = 1 << thread_id; + + start_pipe(pipe, copy_ovrd, pipe->stream->config.mode); + +#if !defined(ISP2401) + /* + * old isys: for IA_CSS_PIPE_MODE_COPY pipe, isys rx has to be configured, + * which is currently done in start_binary(); but COPY pipe contains no binary, + * and does not call start_binary(); so we need to configure the rx here. + */ + if (pipe->config.mode == IA_CSS_PIPE_MODE_COPY && + pipe->stream->reconfigure_css_rx) { + ia_css_isys_rx_configure(&pipe->stream->csi_rx_config, + pipe->stream->config.mode); + pipe->stream->reconfigure_css_rx = false; + } +#endif + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int +sh_css_pipe_get_output_frame_info(struct ia_css_pipe *pipe, + struct ia_css_frame_info *info, + unsigned int idx) +{ + assert(pipe); + assert(info); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_output_frame_info() enter:\n"); + + *info = pipe->output_info[idx]; + if (copy_on_sp(pipe) && + pipe->stream->config.input_config.format == ATOMISP_INPUT_FORMAT_BINARY_8) { + ia_css_frame_info_init( + info, + JPEG_BYTES, + 1, + IA_CSS_FRAME_FORMAT_BINARY_8, + 0); + } else if (info->format == IA_CSS_FRAME_FORMAT_RAW || + info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED) { + info->raw_bit_depth = + ia_css_pipe_util_pipe_input_format_bpp(pipe); + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_output_frame_info() leave:\n"); + return 0; +} + +void +ia_css_stream_send_input_frame(const struct ia_css_stream *stream, + const unsigned short *data, + unsigned int width, + unsigned int height) +{ + assert(stream); + + ia_css_inputfifo_send_input_frame( + data, width, height, + stream->config.channel_id, + stream->config.input_config.format, + stream->config.pixels_per_clock == 2); +} + +void +ia_css_stream_start_input_frame(const struct ia_css_stream *stream) +{ + assert(stream); + + ia_css_inputfifo_start_frame( + stream->config.channel_id, + stream->config.input_config.format, + stream->config.pixels_per_clock == 2); +} + +void +ia_css_stream_send_input_line(const struct ia_css_stream *stream, + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2) +{ + assert(stream); + + ia_css_inputfifo_send_line(stream->config.channel_id, + data, width, data2, width2); +} + +void +ia_css_stream_send_input_embedded_line(const struct ia_css_stream *stream, + enum atomisp_input_format format, + const unsigned short *data, + unsigned int width) +{ + assert(stream); + if (!data || width == 0) + return; + ia_css_inputfifo_send_embedded_line(stream->config.channel_id, + format, data, width); +} + +void +ia_css_stream_end_input_frame(const struct ia_css_stream *stream) +{ + assert(stream); + + ia_css_inputfifo_end_frame(stream->config.channel_id); +} + +bool +ia_css_pipeline_uses_params(struct ia_css_pipeline *me) +{ + struct ia_css_pipeline_stage *stage; + + assert(me); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_uses_params() enter: me=%p\n", me); + + for (stage = me->stages; stage; stage = stage->next) + if (stage->binary_info && stage->binary_info->enable.params) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_uses_params() leave: return_bool=true\n"); + return true; + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_uses_params() leave: return_bool=false\n"); + return false; +} + +/* + * @brief Tag a specific frame in continuous capture. + * Refer to "sh_css_internal.h" for details. + */ +int ia_css_stream_capture_frame(struct ia_css_stream *stream, + unsigned int exp_id) +{ + struct sh_css_tag_descr tag_descr; + u32 encoded_tag_descr; + int err; + + assert(stream); + IA_CSS_ENTER("exp_id=%d", exp_id); + + /* Only continuous streams have a tagger */ + if (exp_id == 0 || !stream->config.continuous) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + IA_CSS_LEAVE_ERR(-EBUSY); + return -EBUSY; + } + + /* Create the tag descriptor from the parameters */ + sh_css_create_tag_descr(0, 0, 0, exp_id, &tag_descr); + /* Encode the tag descriptor into a 32-bit value */ + encoded_tag_descr = sh_css_encode_tag_descr(&tag_descr); + /* + * Enqueue the encoded tag to the host2sp queue. + * Note: The pipe and stage IDs for tag_cmd queue are hard-coded to 0 + * on both host and the SP side. + * It is mainly because it is enough to have only one tag_cmd queue + */ + err = ia_css_bufq_enqueue_tag_cmd(encoded_tag_descr); + + IA_CSS_LEAVE_ERR(err); + return err; +} + +/* + * @brief Configure the continuous capture. + * Refer to "sh_css_internal.h" for details. + */ +int ia_css_stream_capture(struct ia_css_stream *stream, int num_captures, + unsigned int skip, int offset) +{ + struct sh_css_tag_descr tag_descr; + unsigned int encoded_tag_descr; + int return_err; + + if (!stream) + return -EINVAL; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_capture() enter: num_captures=%d, skip=%d, offset=%d\n", + num_captures, skip, offset); + + /* Check if the tag descriptor is valid */ + if (num_captures < SH_CSS_MINIMUM_TAG_ID) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_capture() leave: return_err=%d\n", + -EINVAL); + return -EINVAL; + } + + /* Create the tag descriptor from the parameters */ + sh_css_create_tag_descr(num_captures, skip, offset, 0, &tag_descr); + + /* Encode the tag descriptor into a 32-bit value */ + encoded_tag_descr = sh_css_encode_tag_descr(&tag_descr); + + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_capture() leaving:queues unavailable\n"); + return -EBUSY; + } + + /* + * Enqueue the encoded tag to the host2sp queue. + * Note: The pipe and stage IDs for tag_cmd queue are hard-coded to 0 + * on both host and the SP side. + * It is mainly because it is enough to have only one tag_cmd queue + */ + return_err = ia_css_bufq_enqueue_tag_cmd((uint32_t)encoded_tag_descr); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_capture() leave: return_err=%d\n", + return_err); + + return return_err; +} + +void ia_css_stream_request_flash(struct ia_css_stream *stream) +{ + (void)stream; + + assert(stream); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_request_flash() enter: void\n"); + +#ifndef ISP2401 + sh_css_write_host2sp_command(host2sp_cmd_start_flash); +#else + if (sh_css_sp_is_running()) { + if (!sh_css_write_host2sp_command(host2sp_cmd_start_flash)) { + IA_CSS_ERROR("Call to 'sh-css_write_host2sp_command()' failed"); + ia_css_debug_dump_sp_sw_debug_info(); + ia_css_debug_dump_debug_info(NULL); + } + } else { + IA_CSS_LOG("SP is not running!"); + } + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_request_flash() leave: return_void\n"); +} + +static void +sh_css_init_host_sp_control_vars(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_ia_css_ispctrl_sp_isp_started; + + unsigned int HIVE_ADDR_host_sp_queues_initialized; + unsigned int HIVE_ADDR_sp_sleep_mode; + unsigned int HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb; + unsigned int HIVE_ADDR_sp_stop_copy_preview; + unsigned int HIVE_ADDR_host_sp_com; + unsigned int o = offsetof(struct host_sp_communication, host2sp_command) + / sizeof(int); + + unsigned int i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_init_host_sp_control_vars() enter: void\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_ia_css_ispctrl_sp_isp_started = fw->info.sp.isp_started; + + HIVE_ADDR_host_sp_queues_initialized = + fw->info.sp.host_sp_queues_initialized; + HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode; + HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb = fw->info.sp.invalidate_tlb; + HIVE_ADDR_sp_stop_copy_preview = fw->info.sp.stop_copy_preview; + HIVE_ADDR_host_sp_com = fw->info.sp.host_sp_com; + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(ia_css_ispctrl_sp_isp_started), + (uint32_t)(0)); + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(host_sp_queues_initialized), + (uint32_t)(0)); + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(sp_sleep_mode), + (uint32_t)(0)); + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(ia_css_dmaproxy_sp_invalidate_tlb), + (uint32_t)(false)); + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(sp_stop_copy_preview), + my_css.stop_copy_preview ? (uint32_t)(1) : (uint32_t)(0)); + store_sp_array_uint(host_sp_com, o, host2sp_cmd_ready); + + for (i = 0; i < N_CSI_PORTS; i++) { + sh_css_update_host2sp_num_mipi_frames + (my_css.num_mipi_frames[i]); + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_init_host_sp_control_vars() leave: return_void\n"); +} + +/* + * create the internal structures and fill in the configuration data + */ + +static const struct +ia_css_pipe_config ia_css_pipe_default_config = DEFAULT_PIPE_CONFIG; + +void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_config_defaults()\n"); + memcpy(pipe_config, &ia_css_pipe_default_config, sizeof(*pipe_config)); +} + +void +ia_css_pipe_extra_config_defaults(struct ia_css_pipe_extra_config *extra_config) +{ + if (!extra_config) { + IA_CSS_ERROR("NULL input parameter"); + return; + } + + extra_config->enable_raw_binning = false; + extra_config->enable_yuv_ds = false; + extra_config->enable_high_speed = false; + extra_config->enable_dvs_6axis = false; + extra_config->enable_reduced_pipe = false; + extra_config->disable_vf_pp = false; + extra_config->enable_fractional_ds = false; +} + +void ia_css_stream_config_defaults(struct ia_css_stream_config *stream_config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_config_defaults()\n"); + assert(stream_config); + memset(stream_config, 0, sizeof(*stream_config)); + stream_config->online = true; + stream_config->left_padding = -1; + stream_config->pixels_per_clock = 1; + /* + * temporary default value for backwards compatibility. + * This field used to be hardcoded within CSS but this has now + * been moved to the stream_config struct. + */ + stream_config->source.port.rxcount = 0x04040404; +} + +int ia_css_pipe_create(const struct ia_css_pipe_config *config, + struct ia_css_pipe **pipe) +{ + int err = 0; + + IA_CSS_ENTER_PRIVATE("config = %p, pipe = %p", config, pipe); + + if (!config || !pipe) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + err = ia_css_pipe_create_extra(config, NULL, pipe); + + if (err == 0) + IA_CSS_LOG("pipe created successfully = %p", *pipe); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + + return err; +} + +int +ia_css_pipe_create_extra(const struct ia_css_pipe_config *config, + const struct ia_css_pipe_extra_config *extra_config, + struct ia_css_pipe **pipe) +{ + int err = -EINVAL; + struct ia_css_pipe *internal_pipe = NULL; + unsigned int i; + + IA_CSS_ENTER_PRIVATE("config = %p, extra_config = %p and pipe = %p", config, extra_config, pipe); + + /* do not allow to create more than the maximum limit */ + if (my_css.pipe_counter >= IA_CSS_PIPELINE_NUM_MAX) { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOSPC); + return -EINVAL; + } + + if ((!pipe) || (!config)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + + ia_css_debug_dump_pipe_config(config); + ia_css_debug_dump_pipe_extra_config(extra_config); + + err = create_pipe(config->mode, &internal_pipe, false); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + /* now we have a pipe structure to fill */ + internal_pipe->config = *config; + if (extra_config) + internal_pipe->extra_config = *extra_config; + else + ia_css_pipe_extra_config_defaults(&internal_pipe->extra_config); + + /* + * Use config value when dvs_frame_delay setting equal to 2, + * otherwise always 1 by default + */ + if (internal_pipe->config.dvs_frame_delay == IA_CSS_FRAME_DELAY_2) + internal_pipe->dvs_frame_delay = 2; + else + internal_pipe->dvs_frame_delay = 1; + + /* + * we still keep enable_raw_binning for backward compatibility, + * for any new fractional bayer downscaling, we should use + * bayer_ds_out_res. if both are specified, bayer_ds_out_res will + * take precedence.if none is specified, we set bayer_ds_out_res + * equal to IF output resolution(IF may do cropping on sensor output) + * or use default decimation factor 1. + */ + + /* YUV downscaling */ + if ((internal_pipe->config.vf_pp_in_res.width || + internal_pipe->config.capt_pp_in_res.width)) { + enum ia_css_frame_format format; + + if (internal_pipe->config.vf_pp_in_res.width) { + format = IA_CSS_FRAME_FORMAT_YUV_LINE; + ia_css_frame_info_init( + &internal_pipe->vf_yuv_ds_input_info, + internal_pipe->config.vf_pp_in_res.width, + internal_pipe->config.vf_pp_in_res.height, + format, 0); + } + if (internal_pipe->config.capt_pp_in_res.width) { + format = IA_CSS_FRAME_FORMAT_YUV420; + ia_css_frame_info_init( + &internal_pipe->out_yuv_ds_input_info, + internal_pipe->config.capt_pp_in_res.width, + internal_pipe->config.capt_pp_in_res.height, + format, 0); + } + } + if (internal_pipe->config.vf_pp_in_res.width && + internal_pipe->config.mode == IA_CSS_PIPE_MODE_PREVIEW) { + ia_css_frame_info_init( + &internal_pipe->vf_yuv_ds_input_info, + internal_pipe->config.vf_pp_in_res.width, + internal_pipe->config.vf_pp_in_res.height, + IA_CSS_FRAME_FORMAT_YUV_LINE, 0); + } + /* handle bayer downscaling output info */ + if (internal_pipe->config.bayer_ds_out_res.width) { + ia_css_frame_info_init( + &internal_pipe->bds_output_info, + internal_pipe->config.bayer_ds_out_res.width, + internal_pipe->config.bayer_ds_out_res.height, + IA_CSS_FRAME_FORMAT_RAW, 0); + } + + /* handle output info, assume always needed */ + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if (internal_pipe->config.output_info[i].res.width) { + err = sh_css_pipe_configure_output( + internal_pipe, + internal_pipe->config.output_info[i].res.width, + internal_pipe->config.output_info[i].res.height, + internal_pipe->config.output_info[i].padded_width, + internal_pipe->config.output_info[i].format, + i); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + kvfree(internal_pipe); + internal_pipe = NULL; + return err; + } + } + + /* handle vf output info, when configured */ + internal_pipe->enable_viewfinder[i] = + (internal_pipe->config.vf_output_info[i].res.width != 0); + if (internal_pipe->config.vf_output_info[i].res.width) { + err = sh_css_pipe_configure_viewfinder( + internal_pipe, + internal_pipe->config.vf_output_info[i].res.width, + internal_pipe->config.vf_output_info[i].res.height, + internal_pipe->config.vf_output_info[i].padded_width, + internal_pipe->config.vf_output_info[i].format, + i); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + kvfree(internal_pipe); + internal_pipe = NULL; + return err; + } + } + } + /* set all info to zeroes first */ + memset(&internal_pipe->info, 0, sizeof(internal_pipe->info)); + + /* all went well, return the pipe */ + *pipe = internal_pipe; + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +int +ia_css_pipe_get_info(const struct ia_css_pipe *pipe, + struct ia_css_pipe_info *pipe_info) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipe_get_info()\n"); + if (!pipe_info) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_pipe_get_info: pipe_info cannot be NULL\n"); + return -EINVAL; + } + if (!pipe || !pipe->stream) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_pipe_get_info: ia_css_stream_create needs to be called before ia_css_[stream/pipe]_get_info\n"); + return -EINVAL; + } + /* we succeeded return the info */ + *pipe_info = pipe->info; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_get_info() leave\n"); + return 0; +} + +bool ia_css_pipe_has_dvs_stats(struct ia_css_pipe_info *pipe_info) +{ + unsigned int i; + + if (pipe_info) { + for (i = 0; i < IA_CSS_DVS_STAT_NUM_OF_LEVELS; i++) { + if (pipe_info->grid_info.dvs_grid.dvs_stat_grid_info.grd_cfg[i].grd_start.enable) + return true; + } + } + + return false; +} + +int +ia_css_pipe_override_frame_format(struct ia_css_pipe *pipe, + int pin_index, + enum ia_css_frame_format new_format) +{ + int err = 0; + + IA_CSS_ENTER_PRIVATE("pipe = %p, pin_index = %d, new_formats = %d", pipe, pin_index, new_format); + + if (!pipe) { + IA_CSS_ERROR("pipe is not set"); + err = -EINVAL; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (0 != pin_index && 1 != pin_index) { + IA_CSS_ERROR("pin index is not valid"); + err = -EINVAL; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (new_format != IA_CSS_FRAME_FORMAT_NV12_TILEY) { + IA_CSS_ERROR("new format is not valid"); + err = -EINVAL; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } else { + err = ia_css_pipe_check_format(pipe, new_format); + if (!err) { + if (pin_index == 0) + pipe->output_info[0].format = new_format; + else + pipe->vf_output_info[0].format = new_format; + } + } + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +#if !defined(ISP2401) +/* Configuration of INPUT_SYSTEM_VERSION_2401 is done on SP */ +static int +ia_css_stream_configure_rx(struct ia_css_stream *stream) +{ + struct ia_css_input_port *config; + + assert(stream); + + config = &stream->config.source.port; + /* AM: this code is not reliable, especially for 2400 */ + if (config->num_lanes == 1) + stream->csi_rx_config.mode = MONO_1L_1L_0L; + else if (config->num_lanes == 2) + stream->csi_rx_config.mode = MONO_2L_1L_0L; + else if (config->num_lanes == 3) + stream->csi_rx_config.mode = MONO_3L_1L_0L; + else if (config->num_lanes == 4) + stream->csi_rx_config.mode = MONO_4L_1L_0L; + else if (config->num_lanes != 0) + return -EINVAL; + + if (config->port > MIPI_PORT2_ID) + return -EINVAL; + stream->csi_rx_config.port = + ia_css_isys_port_to_mipi_port(config->port); + stream->csi_rx_config.timeout = config->timeout; + stream->csi_rx_config.initcount = 0; + stream->csi_rx_config.synccount = 0x28282828; + stream->csi_rx_config.rxcount = config->rxcount; + if (config->compression.type == IA_CSS_CSI2_COMPRESSION_TYPE_NONE) + stream->csi_rx_config.comp = MIPI_PREDICTOR_NONE; + else + /* + * not implemented yet, requires extension of the rx_cfg_t + * struct + */ + return -EINVAL; + + stream->csi_rx_config.is_two_ppc = (stream->config.pixels_per_clock == 2); + stream->reconfigure_css_rx = true; + return 0; +} +#endif + +static struct ia_css_pipe * +find_pipe(struct ia_css_pipe *pipes[], unsigned int num_pipes, + enum ia_css_pipe_mode mode, bool copy_pipe) +{ + unsigned int i; + + assert(pipes); + for (i = 0; i < num_pipes; i++) { + assert(pipes[i]); + if (pipes[i]->config.mode != mode) + continue; + if (copy_pipe && pipes[i]->mode != IA_CSS_PIPE_ID_COPY) + continue; + return pipes[i]; + } + return NULL; +} + +static int +metadata_info_init(const struct ia_css_metadata_config *mdc, + struct ia_css_metadata_info *md) +{ + /* Either both width and height should be set or neither */ + if ((mdc->resolution.height > 0) ^ (mdc->resolution.width > 0)) + return -EINVAL; + + md->resolution = mdc->resolution; + /* + * We round up the stride to a multiple of the width + * of the port going to DDR, this is a HW requirements (DMA). + */ + md->stride = CEIL_MUL(mdc->resolution.width, HIVE_ISP_DDR_WORD_BYTES); + md->size = mdc->resolution.height * md->stride; + return 0; +} + +int +ia_css_stream_create(const struct ia_css_stream_config *stream_config, + int num_pipes, + struct ia_css_pipe *pipes[], + struct ia_css_stream **stream) +{ + struct ia_css_pipe *curr_pipe; + struct ia_css_stream *curr_stream = NULL; + bool spcopyonly; + bool sensor_binning_changed; + int i, j; + int err = -EINVAL; + struct ia_css_metadata_info md_info; + struct ia_css_resolution effective_res; + + IA_CSS_ENTER("num_pipes=%d", num_pipes); + ia_css_debug_dump_stream_config(stream_config, num_pipes); + + /* some checks */ + if (num_pipes == 0 || + !stream || + !pipes) { + err = -EINVAL; + IA_CSS_LEAVE_ERR(err); + return err; + } + +#if !defined(ISP2401) + /* We don't support metadata for JPEG stream, since they both use str2mem */ + if (stream_config->input_config.format == ATOMISP_INPUT_FORMAT_BINARY_8 && + stream_config->metadata_config.resolution.height > 0) { + err = -EINVAL; + IA_CSS_LEAVE_ERR(err); + return err; + } +#endif + +#ifdef ISP2401 + if (stream_config->online && stream_config->pack_raw_pixels) { + IA_CSS_LOG("online and pack raw is invalid on input system 2401"); + err = -EINVAL; + IA_CSS_LEAVE_ERR(err); + return err; + } +#endif + + ia_css_debug_pipe_graph_dump_stream_config(stream_config); + + /* check if mipi size specified */ + if (stream_config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) +#ifdef ISP2401 + if (!stream_config->online) +#endif + { + unsigned int port = (unsigned int)stream_config->source.port.port; + + if (port >= N_MIPI_PORT_ID) { + err = -EINVAL; + IA_CSS_LEAVE_ERR(err); + return err; + } + + if (my_css.size_mem_words != 0) { + my_css.mipi_frame_size[port] = my_css.size_mem_words; + } else if (stream_config->mipi_buffer_config.size_mem_words != 0) { + my_css.mipi_frame_size[port] = stream_config->mipi_buffer_config.size_mem_words; + } else { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_create() exit: error, need to set mipi frame size.\n"); + assert(stream_config->mipi_buffer_config.size_mem_words != 0); + err = -EINVAL; + IA_CSS_LEAVE_ERR(err); + return err; + } + + if (my_css.size_mem_words != 0) { + my_css.num_mipi_frames[port] = + 2; /* Temp change: Default for backwards compatibility. */ + } else if (stream_config->mipi_buffer_config.nof_mipi_buffers != 0) { + my_css.num_mipi_frames[port] = + stream_config->mipi_buffer_config.nof_mipi_buffers; + } else { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_create() exit: error, need to set number of mipi frames.\n"); + assert(stream_config->mipi_buffer_config.nof_mipi_buffers != 0); + err = -EINVAL; + IA_CSS_LEAVE_ERR(err); + return err; + } + } + + /* Currently we only supported metadata up to a certain size. */ + err = metadata_info_init(&stream_config->metadata_config, &md_info); + if (err) { + IA_CSS_LEAVE_ERR(err); + return err; + } + + /* allocate the stream instance */ + curr_stream = kzalloc(sizeof(struct ia_css_stream), GFP_KERNEL); + if (!curr_stream) { + err = -ENOMEM; + IA_CSS_LEAVE_ERR(err); + return err; + } + /* default all to 0 */ + curr_stream->info.metadata_info = md_info; + + /* allocate pipes */ + curr_stream->num_pipes = num_pipes; + curr_stream->pipes = kcalloc(num_pipes, sizeof(struct ia_css_pipe *), GFP_KERNEL); + if (!curr_stream->pipes) { + curr_stream->num_pipes = 0; + kfree(curr_stream); + curr_stream = NULL; + err = -ENOMEM; + IA_CSS_LEAVE_ERR(err); + return err; + } + /* store pipes */ + spcopyonly = (num_pipes == 1) && (pipes[0]->config.mode == IA_CSS_PIPE_MODE_COPY); + for (i = 0; i < num_pipes; i++) + curr_stream->pipes[i] = pipes[i]; + curr_stream->last_pipe = curr_stream->pipes[0]; + /* take over stream config */ + curr_stream->config = *stream_config; + +#if defined(ISP2401) + if (stream_config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR && + stream_config->online) + curr_stream->config.online = false; +#endif + +#ifdef ISP2401 + if (curr_stream->config.online) { + curr_stream->config.source.port.num_lanes = + stream_config->source.port.num_lanes; + curr_stream->config.mode = IA_CSS_INPUT_MODE_BUFFERED_SENSOR; + } +#endif + /* in case driver doesn't configure init number of raw buffers, configure it here */ + if (curr_stream->config.target_num_cont_raw_buf == 0) + curr_stream->config.target_num_cont_raw_buf = NUM_CONTINUOUS_FRAMES; + if (curr_stream->config.init_num_cont_raw_buf == 0) + curr_stream->config.init_num_cont_raw_buf = curr_stream->config.target_num_cont_raw_buf; + + /* Enable locking & unlocking of buffers in RAW buffer pool */ + if (curr_stream->config.ia_css_enable_raw_buffer_locking) + sh_css_sp_configure_enable_raw_pool_locking( + curr_stream->config.lock_all); + + /* copy mode specific stuff */ + switch (curr_stream->config.mode) { + case IA_CSS_INPUT_MODE_SENSOR: + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: +#if !defined(ISP2401) + ia_css_stream_configure_rx(curr_stream); +#endif + break; + case IA_CSS_INPUT_MODE_TPG: +#if !defined(ISP2401) + IA_CSS_LOG("tpg_configuration: x_mask=%d, y_mask=%d, x_delta=%d, y_delta=%d, xy_mask=%d", + curr_stream->config.source.tpg.x_mask, + curr_stream->config.source.tpg.y_mask, + curr_stream->config.source.tpg.x_delta, + curr_stream->config.source.tpg.y_delta, + curr_stream->config.source.tpg.xy_mask); + + sh_css_sp_configure_tpg( + curr_stream->config.source.tpg.x_mask, + curr_stream->config.source.tpg.y_mask, + curr_stream->config.source.tpg.x_delta, + curr_stream->config.source.tpg.y_delta, + curr_stream->config.source.tpg.xy_mask); +#endif + break; + case IA_CSS_INPUT_MODE_PRBS: +#if !defined(ISP2401) + IA_CSS_LOG("mode prbs"); + sh_css_sp_configure_prbs(curr_stream->config.source.prbs.seed); +#endif + break; + case IA_CSS_INPUT_MODE_MEMORY: + IA_CSS_LOG("mode memory"); + curr_stream->reconfigure_css_rx = false; + break; + default: + IA_CSS_LOG("mode sensor/default"); + } + + for (i = 0; i < num_pipes; i++) { + struct ia_css_resolution effective_res; + + curr_pipe = pipes[i]; + /* set current stream */ + curr_pipe->stream = curr_stream; + /* take over effective info */ + + effective_res = curr_pipe->config.input_effective_res; + if (effective_res.height == 0 || effective_res.width == 0) { + effective_res = curr_pipe->stream->config.input_config.effective_res; + + curr_pipe->config.input_effective_res = effective_res; + } + IA_CSS_LOG("effective_res=%dx%d", + effective_res.width, + effective_res.height); + } + + err = ia_css_stream_isp_parameters_init(curr_stream); + if (err) + goto ERR; + IA_CSS_LOG("isp_params_configs: %p", curr_stream->isp_params_configs); + + /* sensor binning */ + if (!spcopyonly) { + sensor_binning_changed = + sh_css_params_set_binning_factor(curr_stream, + curr_stream->config.sensor_binning_factor); + } else { + sensor_binning_changed = false; + } + + IA_CSS_LOG("sensor_binning=%d, changed=%d", + curr_stream->config.sensor_binning_factor, sensor_binning_changed); + /* loop over pipes */ + IA_CSS_LOG("num_pipes=%d", num_pipes); + curr_stream->cont_capt = false; + /* Temporary hack: we give the preview pipe a reference to the capture + * pipe in continuous capture mode. */ + if (curr_stream->config.continuous) { + /* Search for the preview pipe and create the copy pipe */ + struct ia_css_pipe *preview_pipe; + struct ia_css_pipe *video_pipe; + struct ia_css_pipe *capture_pipe = NULL; + struct ia_css_pipe *copy_pipe = NULL; + + if (num_pipes >= 2) { + curr_stream->cont_capt = true; + curr_stream->disable_cont_vf = curr_stream->config.disable_cont_viewfinder; + curr_stream->stop_copy_preview = my_css.stop_copy_preview; + } + + /* Create copy pipe here, since it may not be exposed to the driver */ + preview_pipe = find_pipe(pipes, num_pipes, + IA_CSS_PIPE_MODE_PREVIEW, false); + video_pipe = find_pipe(pipes, num_pipes, + IA_CSS_PIPE_MODE_VIDEO, false); + + if (curr_stream->cont_capt) { + capture_pipe = find_pipe(pipes, num_pipes, + IA_CSS_PIPE_MODE_CAPTURE, + false); + if (!capture_pipe) { + err = -EINVAL; + goto ERR; + } + } + /* We do not support preview and video pipe at the same time */ + if (preview_pipe && video_pipe) { + err = -EINVAL; + goto ERR; + } + + if (preview_pipe && !preview_pipe->pipe_settings.preview.copy_pipe) { + err = create_pipe(IA_CSS_PIPE_MODE_CAPTURE, ©_pipe, true); + if (err) + goto ERR; + ia_css_pipe_config_defaults(©_pipe->config); + preview_pipe->pipe_settings.preview.copy_pipe = copy_pipe; + copy_pipe->stream = curr_stream; + } + if (preview_pipe && curr_stream->cont_capt) + preview_pipe->pipe_settings.preview.capture_pipe = capture_pipe; + + if (video_pipe && !video_pipe->pipe_settings.video.copy_pipe) { + err = create_pipe(IA_CSS_PIPE_MODE_CAPTURE, ©_pipe, true); + if (err) + goto ERR; + ia_css_pipe_config_defaults(©_pipe->config); + video_pipe->pipe_settings.video.copy_pipe = copy_pipe; + copy_pipe->stream = curr_stream; + } + if (video_pipe && curr_stream->cont_capt) + video_pipe->pipe_settings.video.capture_pipe = capture_pipe; + } + for (i = 0; i < num_pipes; i++) { + curr_pipe = pipes[i]; + /* set current stream */ + curr_pipe->stream = curr_stream; + + /* take over effective info */ + + effective_res = curr_pipe->config.input_effective_res; + err = ia_css_util_check_res( + effective_res.width, + effective_res.height); + if (err) + goto ERR; + + /* sensor binning per pipe */ + if (sensor_binning_changed) + sh_css_pipe_free_shading_table(curr_pipe); + } + + /* now pipes have been configured, info should be available */ + for (i = 0; i < num_pipes; i++) { + struct ia_css_pipe_info *pipe_info = NULL; + + curr_pipe = pipes[i]; + + err = sh_css_pipe_load_binaries(curr_pipe); + if (err) + goto ERR; + + /* handle each pipe */ + pipe_info = &curr_pipe->info; + for (j = 0; j < IA_CSS_PIPE_MAX_OUTPUT_STAGE; j++) { + err = sh_css_pipe_get_output_frame_info(curr_pipe, + &pipe_info->output_info[j], j); + if (err) + goto ERR; + } + + if (!spcopyonly) { + if (!IS_ISP2401) + err = sh_css_pipe_get_shading_info(curr_pipe, + &pipe_info->shading_info, + NULL); + else + err = sh_css_pipe_get_shading_info(curr_pipe, + &pipe_info->shading_info, + &curr_pipe->config); + + if (err) + goto ERR; + err = sh_css_pipe_get_grid_info(curr_pipe, + &pipe_info->grid_info); + if (err) + goto ERR; + for (j = 0; j < IA_CSS_PIPE_MAX_OUTPUT_STAGE; j++) { + sh_css_pipe_get_viewfinder_frame_info(curr_pipe, + &pipe_info->vf_output_info[j], + j); + if (err) + goto ERR; + } + } + + my_css.active_pipes[ia_css_pipe_get_pipe_num(curr_pipe)] = curr_pipe; + } + + curr_stream->started = false; + + /* Map SP threads before doing anything. */ + err = map_sp_threads(curr_stream, true); + if (err) { + IA_CSS_LOG("map_sp_threads: return_err=%d", err); + goto ERR; + } + + for (i = 0; i < num_pipes; i++) { + curr_pipe = pipes[i]; + ia_css_pipe_map_queue(curr_pipe, true); + } + + /* Create host side pipeline objects without stages */ + err = create_host_pipeline_structure(curr_stream); + if (err) { + IA_CSS_LOG("create_host_pipeline_structure: return_err=%d", err); + goto ERR; + } + + /* assign curr_stream */ + *stream = curr_stream; + +ERR: + if (!err) { + /* working mode: enter into the seed list */ + if (my_css_save.mode == sh_css_mode_working) { + for (i = 0; i < MAX_ACTIVE_STREAMS; i++) { + if (!my_css_save.stream_seeds[i].stream) { + IA_CSS_LOG("entered stream into loc=%d", i); + my_css_save.stream_seeds[i].orig_stream = stream; + my_css_save.stream_seeds[i].stream = curr_stream; + my_css_save.stream_seeds[i].num_pipes = num_pipes; + my_css_save.stream_seeds[i].stream_config = *stream_config; + for (j = 0; j < num_pipes; j++) { + my_css_save.stream_seeds[i].pipe_config[j] = pipes[j]->config; + my_css_save.stream_seeds[i].pipes[j] = pipes[j]; + my_css_save.stream_seeds[i].orig_pipes[j] = &pipes[j]; + } + break; + } + } + } else { + ia_css_stream_destroy(curr_stream); + } + } else { + ia_css_stream_destroy(curr_stream); + } + IA_CSS_LEAVE("return_err=%d mode=%d", err, my_css_save.mode); + return err; +} + +int +ia_css_stream_destroy(struct ia_css_stream *stream) +{ + int i; + int err = 0; + + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + if (!stream) { + err = -EINVAL; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + ia_css_stream_isp_parameters_uninit(stream); + + if ((stream->last_pipe) && + ia_css_pipeline_is_mapped(stream->last_pipe->pipe_num)) { +#if defined(ISP2401) + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *entry = stream->pipes[i]; + unsigned int sp_thread_id; + struct sh_css_sp_pipeline_terminal *sp_pipeline_input_terminal; + + assert(entry); + if (entry) { + /* get the SP thread id */ + if (!ia_css_pipeline_get_sp_thread_id( + ia_css_pipe_get_pipe_num(entry), &sp_thread_id)) + return -EINVAL; + /* get the target input terminal */ + sp_pipeline_input_terminal = + &sh_css_sp_group.pipe_io[sp_thread_id].input; + + for (i = 0; i < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; i++) { + ia_css_isys_stream_h isys_stream = + &sp_pipeline_input_terminal->context.virtual_input_system_stream[i]; + if (stream->config.isys_config[i].valid && isys_stream->valid) + ia_css_isys_stream_destroy(isys_stream); + } + } + } + if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *entry = stream->pipes[i]; + /* + * free any mipi frames that are remaining: + * some test stream create-destroy cycles do + * not generate output frames + * and the mipi buffer is not freed in the + * deque function + */ + if (entry) + free_mipi_frames(entry); + } + } + stream_unregister_with_csi_rx(stream); +#endif + + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *curr_pipe = stream->pipes[i]; + + assert(curr_pipe); + ia_css_pipe_map_queue(curr_pipe, false); + } + + err = map_sp_threads(stream, false); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + /* remove references from pipes to stream */ + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *entry = stream->pipes[i]; + + assert(entry); + if (entry) { + /* clear reference to stream */ + entry->stream = NULL; + /* check internal copy pipe */ + if (entry->mode == IA_CSS_PIPE_ID_PREVIEW && + entry->pipe_settings.preview.copy_pipe) { + IA_CSS_LOG("clearing stream on internal preview copy pipe"); + entry->pipe_settings.preview.copy_pipe->stream = NULL; + } + if (entry->mode == IA_CSS_PIPE_ID_VIDEO && + entry->pipe_settings.video.copy_pipe) { + IA_CSS_LOG("clearing stream on internal video copy pipe"); + entry->pipe_settings.video.copy_pipe->stream = NULL; + } + err = sh_css_pipe_unload_binaries(entry); + } + } + /* free associated memory of stream struct */ + kfree(stream->pipes); + stream->pipes = NULL; + stream->num_pipes = 0; + + /* working mode: take out of the seed list */ + if (my_css_save.mode == sh_css_mode_working) { + for (i = 0; i < MAX_ACTIVE_STREAMS; i++) { + if (my_css_save.stream_seeds[i].stream == stream) { + IA_CSS_LOG("took out stream %d", i); + my_css_save.stream_seeds[i].stream = NULL; + break; + } + } + } + + kfree(stream); + IA_CSS_LEAVE_ERR(err); + + return err; +} + +int +ia_css_stream_get_info(const struct ia_css_stream *stream, + struct ia_css_stream_info *stream_info) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_info: enter/exit\n"); + assert(stream); + assert(stream_info); + + *stream_info = stream->info; + return 0; +} + +int +ia_css_stream_start(struct ia_css_stream *stream) +{ + int err = 0; + + IA_CSS_ENTER("stream = %p", stream); + if ((!stream) || (!stream->last_pipe)) { + IA_CSS_LEAVE_ERR(-EINVAL); + return -EINVAL; + } + IA_CSS_LOG("starting %d", stream->last_pipe->mode); + + sh_css_sp_set_disable_continuous_viewfinder(stream->disable_cont_vf); + + /* Create host side pipeline. */ + err = create_host_pipeline(stream); + if (err) { + IA_CSS_LEAVE_ERR(err); + return err; + } + +#if defined(ISP2401) + if ((stream->config.mode == IA_CSS_INPUT_MODE_SENSOR) || + (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR)) + stream_register_with_csi_rx(stream); +#endif + +#if !defined(ISP2401) + /* Initialize mipi size checks */ + if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + unsigned int idx; + unsigned int port = (unsigned int)(stream->config.source.port.port); + + for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT; idx++) { + sh_css_sp_group.config.mipi_sizes_for_check[port][idx] = + sh_css_get_mipi_sizes_for_check(port, idx); + } + } +#endif + + if (stream->config.mode != IA_CSS_INPUT_MODE_MEMORY) { + err = sh_css_config_input_network(stream); + if (err) + return err; + } + + err = sh_css_pipe_start(stream); + IA_CSS_LEAVE_ERR(err); + return err; +} + +int +ia_css_stream_stop(struct ia_css_stream *stream) +{ + int err = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_stop() enter/exit\n"); + assert(stream); + assert(stream->last_pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_stop: stopping %d\n", + stream->last_pipe->mode); + +#if !defined(ISP2401) + /* De-initialize mipi size checks */ + if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + unsigned int idx; + unsigned int port = (unsigned int)(stream->config.source.port.port); + + for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT; idx++) + sh_css_sp_group.config.mipi_sizes_for_check[port][idx] = 0; + } +#endif + + err = ia_css_pipeline_request_stop(&stream->last_pipe->pipeline); + if (err) + return err; + + /* + * Ideally, unmapping should happen after pipeline_stop, but current + * semantics do not allow that. + */ + /* err = map_sp_threads(stream, false); */ + + return err; +} + +bool +ia_css_stream_has_stopped(struct ia_css_stream *stream) +{ + bool stopped; + + assert(stream); + + stopped = ia_css_pipeline_has_stopped(&stream->last_pipe->pipeline); + + return stopped; +} + +/* ISP2400 */ +/* + * Destroy the stream and all the pipes related to it. + * The stream handle is used to identify the correct entry in the css_save struct + */ +int +ia_css_stream_unload(struct ia_css_stream *stream) +{ + int i; + + assert(stream); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload() enter,\n"); + /* some checks */ + assert(stream); + for (i = 0; i < MAX_ACTIVE_STREAMS; i++) + if (my_css_save.stream_seeds[i].stream == stream) { + int j; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_unload(): unloading %d (%p)\n", i, + my_css_save.stream_seeds[i].stream); + ia_css_stream_destroy(stream); + for (j = 0; j < my_css_save.stream_seeds[i].num_pipes; j++) + ia_css_pipe_destroy(my_css_save.stream_seeds[i].pipes[j]); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_unload(): after unloading %d (%p)\n", i, + my_css_save.stream_seeds[i].stream); + break; + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload() exit,\n"); + return 0; +} + +int +ia_css_temp_pipe_to_pipe_id(const struct ia_css_pipe *pipe, + enum ia_css_pipe_id *pipe_id) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_temp_pipe_to_pipe_id() enter/exit\n"); + if (pipe) + *pipe_id = pipe->mode; + else + *pipe_id = IA_CSS_PIPE_ID_COPY; + + return 0; +} + +enum atomisp_input_format +ia_css_stream_get_format(const struct ia_css_stream *stream) +{ + return stream->config.input_config.format; +} + +bool +ia_css_stream_get_two_pixels_per_clock(const struct ia_css_stream *stream) +{ + return (stream->config.pixels_per_clock == 2); +} + +struct ia_css_binary * +ia_css_stream_get_shading_correction_binary(const struct ia_css_stream + *stream) +{ + struct ia_css_pipe *pipe; + + assert(stream); + + pipe = stream->pipes[0]; + + if (stream->num_pipes == 2) { + assert(stream->pipes[1]); + if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO || + stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW) + pipe = stream->pipes[1]; + } + + return ia_css_pipe_get_shading_correction_binary(pipe); +} + +struct ia_css_binary * +ia_css_stream_get_dvs_binary(const struct ia_css_stream *stream) +{ + int i; + struct ia_css_pipe *video_pipe = NULL; + + /* First we find the video pipe */ + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *pipe = stream->pipes[i]; + + if (pipe->config.mode == IA_CSS_PIPE_MODE_VIDEO) { + video_pipe = pipe; + break; + } + } + if (video_pipe) + return &video_pipe->pipe_settings.video.video_binary; + return NULL; +} + +struct ia_css_binary * +ia_css_stream_get_3a_binary(const struct ia_css_stream *stream) +{ + struct ia_css_pipe *pipe; + struct ia_css_binary *s3a_binary = NULL; + + assert(stream); + + pipe = stream->pipes[0]; + + if (stream->num_pipes == 2) { + assert(stream->pipes[1]); + if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO || + stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW) + pipe = stream->pipes[1]; + } + + s3a_binary = ia_css_pipe_get_s3a_binary(pipe); + + return s3a_binary; +} + +int +ia_css_stream_set_output_padded_width(struct ia_css_stream *stream, + unsigned int output_padded_width) +{ + struct ia_css_pipe *pipe; + + assert(stream); + + pipe = stream->last_pipe; + + assert(pipe); + + /* set the config also just in case (redundant info? why do we save config in pipe?) */ + pipe->config.output_info[IA_CSS_PIPE_OUTPUT_STAGE_0].padded_width = output_padded_width; + pipe->output_info[IA_CSS_PIPE_OUTPUT_STAGE_0].padded_width = output_padded_width; + + return 0; +} + +static struct ia_css_binary * +ia_css_pipe_get_shading_correction_binary(const struct ia_css_pipe *pipe) +{ + struct ia_css_binary *binary = NULL; + + assert(pipe); + + switch (pipe->config.mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + binary = (struct ia_css_binary *)&pipe->pipe_settings.preview.preview_binary; + break; + case IA_CSS_PIPE_MODE_VIDEO: + binary = (struct ia_css_binary *)&pipe->pipe_settings.video.video_binary; + break; + case IA_CSS_PIPE_MODE_CAPTURE: + if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_PRIMARY) { + unsigned int i; + + for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) { + if (pipe->pipe_settings.capture.primary_binary[i].info->sp.enable.sc) { + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.primary_binary[i]; + break; + } + } + } else if (pipe->config.default_capture_config.mode == + IA_CSS_CAPTURE_MODE_BAYER) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary; + else if (pipe->config.default_capture_config.mode == + IA_CSS_CAPTURE_MODE_ADVANCED || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) { + if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_1) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary; + else if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_2_2) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.post_isp_binary; + } + break; + default: + break; + } + + if (binary && binary->info->sp.enable.sc) + return binary; + + return NULL; +} + +static struct ia_css_binary * +ia_css_pipe_get_s3a_binary(const struct ia_css_pipe *pipe) +{ + struct ia_css_binary *binary = NULL; + + assert(pipe); + + switch (pipe->config.mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + binary = (struct ia_css_binary *)&pipe->pipe_settings.preview.preview_binary; + break; + case IA_CSS_PIPE_MODE_VIDEO: + binary = (struct ia_css_binary *)&pipe->pipe_settings.video.video_binary; + break; + case IA_CSS_PIPE_MODE_CAPTURE: + if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_PRIMARY) { + unsigned int i; + + for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) { + if (pipe->pipe_settings.capture.primary_binary[i].info->sp.enable.s3a) { + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.primary_binary[i]; + break; + } + } + } else if (pipe->config.default_capture_config.mode == + IA_CSS_CAPTURE_MODE_BAYER) { + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary; + } else if (pipe->config.default_capture_config.mode == + IA_CSS_CAPTURE_MODE_ADVANCED || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) { + if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_1) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary; + else if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_2_2) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.post_isp_binary; + else + assert(0); + } + break; + default: + break; + } + + if (binary && !binary->info->sp.enable.s3a) + binary = NULL; + + return binary; +} + +static struct ia_css_binary * +ia_css_pipe_get_sdis_binary(const struct ia_css_pipe *pipe) +{ + struct ia_css_binary *binary = NULL; + + assert(pipe); + + switch (pipe->config.mode) { + case IA_CSS_PIPE_MODE_VIDEO: + binary = (struct ia_css_binary *)&pipe->pipe_settings.video.video_binary; + break; + default: + break; + } + + if (binary && !binary->info->sp.enable.dis) + binary = NULL; + + return binary; +} + +struct ia_css_pipeline * +ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe) +{ + assert(pipe); + + return (struct ia_css_pipeline *)&pipe->pipeline; +} + +unsigned int +ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe) +{ + assert(pipe); + + /* + * KW was not sure this function was not returning a value + * that was out of range; so added an assert, and, for the + * case when asserts are not enabled, clip to the largest + * value; pipe_num is unsigned so the value cannot be too small + */ + assert(pipe->pipe_num < IA_CSS_PIPELINE_NUM_MAX); + + if (pipe->pipe_num >= IA_CSS_PIPELINE_NUM_MAX) + return (IA_CSS_PIPELINE_NUM_MAX - 1); + + return pipe->pipe_num; +} + +unsigned int +ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe) +{ + assert(pipe); + + return (unsigned int)pipe->config.isp_pipe_version; +} + +#define SP_START_TIMEOUT_US 30000000 + +int +ia_css_start_sp(void) +{ + unsigned long timeout; + int err = 0; + + IA_CSS_ENTER(""); + sh_css_sp_start_isp(); + + /* waiting for the SP is completely started */ + timeout = SP_START_TIMEOUT_US; + while ((ia_css_spctrl_get_state(SP0_ID) != IA_CSS_SP_SW_INITIALIZED) && timeout) { + timeout--; + udelay(1); + } + if (timeout == 0) { + IA_CSS_ERROR("timeout during SP initialization"); + return -EINVAL; + } + + /* Workaround, in order to run two streams in parallel. See TASK 4271*/ + /* TODO: Fix this. */ + + sh_css_init_host_sp_control_vars(); + + /* buffers should be initialized only when sp is started */ + /* AM: At the moment it will be done only when there is no stream active. */ + + sh_css_setup_queues(); + ia_css_bufq_dump_queue_info(); + + IA_CSS_LEAVE_ERR(err); + return err; +} + +/* + * Time to wait SP for termincate. Only condition when this can happen + * is a fatal hw failure, but we must be able to detect this and emit + * a proper error trace. + */ +#define SP_SHUTDOWN_TIMEOUT_US 200000 + +int +ia_css_stop_sp(void) +{ + unsigned long timeout; + int err = 0; + + IA_CSS_ENTER("void"); + + if (!sh_css_sp_is_running()) { + err = -EINVAL; + IA_CSS_LEAVE("SP already stopped : return_err=%d", err); + + /* Return an error - stop SP should not have been called by driver */ + return err; + } + + /* For now, stop whole SP */ + if (!sh_css_write_host2sp_command(host2sp_cmd_terminate)) { + IA_CSS_ERROR("Call to 'sh-css_write_host2sp_command()' failed"); + ia_css_debug_dump_sp_sw_debug_info(); + ia_css_debug_dump_debug_info(NULL); + } + + sh_css_sp_set_sp_running(false); + + timeout = SP_SHUTDOWN_TIMEOUT_US; + while (!ia_css_spctrl_is_idle(SP0_ID) && timeout) { + timeout--; + udelay(1); + } + if (ia_css_spctrl_get_state(SP0_ID) != IA_CSS_SP_SW_TERMINATED) + IA_CSS_WARNING("SP has not terminated (SW)"); + + if (timeout == 0) { + IA_CSS_WARNING("SP is not idle"); + ia_css_debug_dump_sp_sw_debug_info(); + } + timeout = SP_SHUTDOWN_TIMEOUT_US; + while (!isp_ctrl_getbit(ISP0_ID, ISP_SC_REG, ISP_IDLE_BIT) && timeout) { + timeout--; + udelay(1); + } + if (timeout == 0) { + IA_CSS_WARNING("ISP is not idle"); + ia_css_debug_dump_sp_sw_debug_info(); + } + + sh_css_hmm_buffer_record_uninit(); + + /* clear pending param sets from refcount */ + sh_css_param_clear_param_sets(); + + IA_CSS_LEAVE_ERR(err); + return err; +} + +int +ia_css_update_continuous_frames(struct ia_css_stream *stream) +{ + struct ia_css_pipe *pipe; + unsigned int i; + + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, + "sh_css_update_continuous_frames() enter:\n"); + + if (!stream) { + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, + "sh_css_update_continuous_frames() leave: invalid stream, return_void\n"); + return -EINVAL; + } + + pipe = stream->continuous_pipe; + + for (i = stream->config.init_num_cont_raw_buf; + i < stream->config.target_num_cont_raw_buf; i++) + sh_css_update_host2sp_offline_frame(i, + pipe->continuous_frames[i], pipe->cont_md_buffers[i]); + + sh_css_update_host2sp_cont_num_raw_frames + (stream->config.target_num_cont_raw_buf, true); + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, + "sh_css_update_continuous_frames() leave: return_void\n"); + + return 0; +} + +void ia_css_pipe_map_queue(struct ia_css_pipe *pipe, bool map) +{ + unsigned int thread_id; + unsigned int pipe_num; + bool need_input_queue; + + IA_CSS_ENTER(""); + assert(pipe); + + pipe_num = pipe->pipe_num; + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + +#if defined(ISP2401) + need_input_queue = true; +#else + need_input_queue = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + + /* map required buffer queues to resources */ + /* TODO: to be improved */ + if (pipe->mode == IA_CSS_PIPE_ID_PREVIEW) { + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); + if (pipe->pipe_settings.preview.preview_binary.info && + pipe->pipe_settings.preview.preview_binary.info->sp.enable.s3a) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_3A_STATISTICS, map); + } else if (pipe->mode == IA_CSS_PIPE_ID_CAPTURE) { + unsigned int i; + + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); + if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_PRIMARY) { + for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) { + if (pipe->pipe_settings.capture.primary_binary[i].info && + pipe->pipe_settings.capture.primary_binary[i].info->sp.enable.s3a) { + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_3A_STATISTICS, map); + break; + } + } + } else if (pipe->config.default_capture_config.mode == + IA_CSS_CAPTURE_MODE_ADVANCED || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER) { + if (pipe->pipe_settings.capture.pre_isp_binary.info && + pipe->pipe_settings.capture.pre_isp_binary.info->sp.enable.s3a) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_3A_STATISTICS, map); + } + } else if (pipe->mode == IA_CSS_PIPE_ID_VIDEO) { + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); + if (pipe->pipe_settings.video.video_binary.info && + pipe->pipe_settings.video.video_binary.info->sp.enable.s3a) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_3A_STATISTICS, map); + if (pipe->pipe_settings.video.video_binary.info && + (pipe->pipe_settings.video.video_binary.info->sp.enable.dis + )) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_DIS_STATISTICS, map); + } else if (pipe->mode == IA_CSS_PIPE_ID_COPY) { + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + if (!pipe->stream->config.continuous) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); + } else if (pipe->mode == IA_CSS_PIPE_ID_YUVPP) { + unsigned int idx; + + for (idx = 0; idx < IA_CSS_PIPE_MAX_OUTPUT_STAGE; idx++) { + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME + idx, map); + if (pipe->enable_viewfinder[idx]) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME + idx, map); + } + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); + } + IA_CSS_LEAVE(""); +} + + +int +ia_css_unlock_raw_frame(struct ia_css_stream *stream, uint32_t exp_id) +{ + int ret; + + IA_CSS_ENTER(""); + + /* + * Only continuous streams have a tagger to which we can send the + * unlock message. + */ + if (!stream || !stream->config.continuous) { + IA_CSS_ERROR("invalid stream pointer"); + return -EINVAL; + } + + if (exp_id > IA_CSS_ISYS_MAX_EXPOSURE_ID || + exp_id < IA_CSS_ISYS_MIN_EXPOSURE_ID) { + IA_CSS_ERROR("invalid exposure ID: %d\n", exp_id); + return -EINVAL; + } + + /* + * Send the event. Since we verified that the exp_id is valid, + * we can safely assign it to an 8-bit argument here. + */ + ret = ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_UNLOCK_RAW_BUFFER, exp_id, 0, 0); + + IA_CSS_LEAVE_ERR(ret); + return ret; +} + +static void +sh_css_hmm_buffer_record_init(void) +{ + int i; + + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) + sh_css_hmm_buffer_record_reset(&hmm_buffer_record[i]); +} + +static void +sh_css_hmm_buffer_record_uninit(void) +{ + int i; + struct sh_css_hmm_buffer_record *buffer_record = NULL; + + buffer_record = &hmm_buffer_record[0]; + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + if (buffer_record->in_use) { + if (buffer_record->h_vbuf) + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &buffer_record->h_vbuf); + sh_css_hmm_buffer_record_reset(buffer_record); + } + buffer_record++; + } +} + +static void +sh_css_hmm_buffer_record_reset(struct sh_css_hmm_buffer_record *buffer_record) +{ + assert(buffer_record); + buffer_record->in_use = false; + buffer_record->type = IA_CSS_BUFFER_TYPE_INVALID; + buffer_record->h_vbuf = NULL; + buffer_record->kernel_ptr = 0; +} + +static struct sh_css_hmm_buffer_record +*sh_css_hmm_buffer_record_acquire(struct ia_css_rmgr_vbuf_handle *h_vbuf, + enum ia_css_buffer_type type, + hrt_address kernel_ptr) +{ + int i; + struct sh_css_hmm_buffer_record *buffer_record = NULL; + struct sh_css_hmm_buffer_record *out_buffer_record = NULL; + + assert(h_vbuf); + assert((type > IA_CSS_BUFFER_TYPE_INVALID) && + (type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE)); + assert(kernel_ptr != 0); + + buffer_record = &hmm_buffer_record[0]; + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + if (!buffer_record->in_use) { + buffer_record->in_use = true; + buffer_record->type = type; + buffer_record->h_vbuf = h_vbuf; + buffer_record->kernel_ptr = kernel_ptr; + out_buffer_record = buffer_record; + break; + } + buffer_record++; + } + + return out_buffer_record; +} + +static struct sh_css_hmm_buffer_record +*sh_css_hmm_buffer_record_validate(ia_css_ptr ddr_buffer_addr, + enum ia_css_buffer_type type) +{ + int i; + struct sh_css_hmm_buffer_record *buffer_record = NULL; + bool found_record = false; + + buffer_record = &hmm_buffer_record[0]; + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + if ((buffer_record->in_use) && + (buffer_record->type == type) && + (buffer_record->h_vbuf) && + (buffer_record->h_vbuf->vptr == ddr_buffer_addr)) { + found_record = true; + break; + } + buffer_record++; + } + + if (found_record) + return buffer_record; + else + return NULL; +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_defs.h b/drivers/staging/media/atomisp/pci/sh_css_defs.h new file mode 100644 index 000000000..7eb10b226 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_defs.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_DEFS_H_ +#define _SH_CSS_DEFS_H_ + +#include "isp.h" + +/*#include "vamem.h"*/ /* Cannot include for VAMEM properties this file is visible on ISP -> pipeline generator */ + +#include "math_support.h" /* max(), min, etc etc */ + +/* ID's for refcount */ +#define IA_CSS_REFCOUNT_PARAM_SET_POOL 0xCAFE0001 +#define IA_CSS_REFCOUNT_PARAM_BUFFER 0xCAFE0002 + +/* Digital Image Stabilization */ +#define SH_CSS_DIS_DECI_FACTOR_LOG2 6 + +/* UV offset: 1:uv=-128...127, 0:uv=0...255 */ +#define SH_CSS_UV_OFFSET_IS_0 0 + +/* Bits of bayer is adjusted as 13 in ISP */ +#define SH_CSS_BAYER_BITS 13 + +/* Max value of bayer data (unsigned 13bit in ISP) */ +#define SH_CSS_BAYER_MAXVAL ((1U << SH_CSS_BAYER_BITS) - 1) + +/* Bits of yuv in ISP */ +#define SH_CSS_ISP_YUV_BITS 8 + +#define SH_CSS_DP_GAIN_SHIFT 5 +#define SH_CSS_BNR_GAIN_SHIFT 13 +#define SH_CSS_YNR_GAIN_SHIFT 13 +#define SH_CSS_AE_YCOEF_SHIFT 13 +#define SH_CSS_AF_FIR_SHIFT 13 +#define SH_CSS_YEE_DETAIL_GAIN_SHIFT 8 /* [u5.8] */ +#define SH_CSS_YEE_SCALE_SHIFT 8 +#define SH_CSS_TNR_COEF_SHIFT 13 +#define SH_CSS_MACC_COEF_SHIFT 11 /* [s2.11] for ISP1 */ +#define SH_CSS_MACC2_COEF_SHIFT 13 /* [s[exp].[13-exp]] for ISP2 */ +#define SH_CSS_DIS_COEF_SHIFT 13 + +/* enumeration of the bayer downscale factors. When a binary supports multiple + * factors, the OR of these defines is used to build the mask of supported + * factors. The BDS factor is used in pre-processor expressions so we cannot + * use an enum here. */ +#define SH_CSS_BDS_FACTOR_1_00 (0) +#define SH_CSS_BDS_FACTOR_1_25 (1) +#define SH_CSS_BDS_FACTOR_1_50 (2) +#define SH_CSS_BDS_FACTOR_2_00 (3) +#define SH_CSS_BDS_FACTOR_2_25 (4) +#define SH_CSS_BDS_FACTOR_2_50 (5) +#define SH_CSS_BDS_FACTOR_3_00 (6) +#define SH_CSS_BDS_FACTOR_4_00 (7) +#define SH_CSS_BDS_FACTOR_4_50 (8) +#define SH_CSS_BDS_FACTOR_5_00 (9) +#define SH_CSS_BDS_FACTOR_6_00 (10) +#define SH_CSS_BDS_FACTOR_8_00 (11) +#define NUM_BDS_FACTORS (12) + +#define PACK_BDS_FACTOR(factor) (1 << (factor)) + +/* Following macros should match with the type enum ia_css_pipe_version in + * ia_css_pipe_public.h. The reason to add these macros is that enum type + * will be evaluted to 0 in preprocessing time. */ +#define SH_CSS_ISP_PIPE_VERSION_1 1 +#define SH_CSS_ISP_PIPE_VERSION_2_2 2 +#define SH_CSS_ISP_PIPE_VERSION_2_6_1 3 +#define SH_CSS_ISP_PIPE_VERSION_2_7 4 + +/*--------------- sRGB Gamma ----------------- +CCM : YCgCo[0,8191] -> RGB[0,4095] +sRGB Gamma : RGB [0,4095] -> RGB[0,8191] +CSC : RGB [0,8191] -> YUV[0,8191] + +CCM: +Y[0,8191],CgCo[-4096,4095],coef[-8192,8191] -> RGB[0,4095] + +sRGB Gamma: +RGB[0,4095] -(interpolation step16)-> RGB[0,255] -(LUT 12bit)-> RGB[0,4095] -> RGB[0,8191] + +CSC: +RGB[0,8191],coef[-8192,8191] -> RGB[0,8191] +--------------------------------------------*/ +/* Bits of input/output of sRGB Gamma */ +#define SH_CSS_RGB_GAMMA_INPUT_BITS 12 /* [0,4095] */ +#define SH_CSS_RGB_GAMMA_OUTPUT_BITS 13 /* [0,8191] */ + +/* Bits of fractional part of interpolation in vamem, [0,4095]->[0,255] */ +#define SH_CSS_RGB_GAMMA_FRAC_BITS \ + (SH_CSS_RGB_GAMMA_INPUT_BITS - SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE_LOG2) +#define SH_CSS_RGB_GAMMA_ONE BIT(SH_CSS_RGB_GAMMA_FRAC_BITS) + +/* Bits of input of CCM, = 13, Y[0,8191],CgCo[-4096,4095] */ +#define SH_CSS_YUV2RGB_CCM_INPUT_BITS SH_CSS_BAYER_BITS + +/* Bits of output of CCM, = 12, RGB[0,4095] */ +#define SH_CSS_YUV2RGB_CCM_OUTPUT_BITS SH_CSS_RGB_GAMMA_INPUT_BITS + +/* Maximum value of output of CCM */ +#define SH_CSS_YUV2RGB_CCM_MAX_OUTPUT \ + ((1 << SH_CSS_YUV2RGB_CCM_OUTPUT_BITS) - 1) + +#define SH_CSS_NUM_INPUT_BUF_LINES 4 + +/* Left cropping only applicable for sufficiently large nway */ +#define SH_CSS_MAX_LEFT_CROPPING 12 +#define SH_CSS_MAX_TOP_CROPPING 12 + +#define SH_CSS_SP_MAX_WIDTH 1280 + +/* This is the maximum grid we can handle in the ISP binaries. + * The host code makes sure no bigger grid is ever selected. */ +#define SH_CSS_MAX_BQ_GRID_WIDTH 80 +#define SH_CSS_MAX_BQ_GRID_HEIGHT 60 + +/* The minimum dvs envelope is 12x12(for IPU2) to make sure the + * invalid rows/columns that result from filter initialization are skipped. */ +#define SH_CSS_MIN_DVS_ENVELOPE 12U + +/* The FPGA system (vec_nelems == 16) only supports upto 5MP */ +#define SH_CSS_MAX_SENSOR_WIDTH 4608 +#define SH_CSS_MAX_SENSOR_HEIGHT 3450 + +/* Limited to reduce vmem pressure */ +#if ISP_VMEM_DEPTH >= 3072 +#define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH SH_CSS_MAX_SENSOR_WIDTH +#define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT +#else +#define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH 3264 +#define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT 2448 +#endif +/* When using bayer decimation */ +/* +#define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC 4224 +#define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC 3168 +*/ +#define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC SH_CSS_MAX_SENSOR_WIDTH +#define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC SH_CSS_MAX_SENSOR_HEIGHT + +#define SH_CSS_MIN_SENSOR_WIDTH 2 +#define SH_CSS_MIN_SENSOR_HEIGHT 2 + +/* +#define SH_CSS_MAX_VF_WIDTH_DEC 1920 +#define SH_CSS_MAX_VF_HEIGHT_DEC 1080 +*/ +#define SH_CSS_MAX_VF_WIDTH_DEC SH_CSS_MAX_VF_WIDTH +#define SH_CSS_MAX_VF_HEIGHT_DEC SH_CSS_MAX_VF_HEIGHT + +/* We use 16 bits per coordinate component, including integer + and fractional bits */ +#define SH_CSS_MORPH_TABLE_GRID ISP_VEC_NELEMS +#define SH_CSS_MORPH_TABLE_ELEM_BYTES 2 +#define SH_CSS_MORPH_TABLE_ELEMS_PER_DDR_WORD \ + (HIVE_ISP_DDR_WORD_BYTES / SH_CSS_MORPH_TABLE_ELEM_BYTES) + +#define SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR (SH_CSS_MAX_BQ_GRID_WIDTH + 1) +#define SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR (SH_CSS_MAX_BQ_GRID_HEIGHT + 1) + +#define SH_CSS_MAX_SCTBL_ALIGNED_WIDTH_PER_COLOR \ + CEIL_MUL(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) + +/* Each line of this table is aligned to the maximum line width. */ +#define SH_CSS_MAX_S3ATBL_WIDTH SH_CSS_MAX_BQ_GRID_WIDTH + +/* Video mode specific DVS define */ +/* The video binary supports a delay of 1 or 2 frames */ +#define MAX_DVS_FRAME_DELAY 2 +/* +1 because DVS reads the previous and writes the current frame concurrently */ +#define MAX_NUM_VIDEO_DELAY_FRAMES (MAX_DVS_FRAME_DELAY + 1) + +#define NUM_VIDEO_TNR_FRAMES 2 + +/* Note that this is the define used to configure all data structures common for all modes */ +/* It should be equal or bigger to the max number of DVS frames for all possible modes */ +/* Rules: these implement logic shared between the host code and ISP firmware. + The ISP firmware needs these rules to be applied at pre-processor time, + that's why these are macros, not functions. */ +#define _ISP_BQS(num) ((num) / 2) +#define _ISP_VECS(width) CEIL_DIV(width, ISP_VEC_NELEMS) + +#define ISP_BQ_GRID_WIDTH(elements_per_line, deci_factor_log2) \ + CEIL_SHIFT(elements_per_line / 2, deci_factor_log2) +#define ISP_BQ_GRID_HEIGHT(lines_per_frame, deci_factor_log2) \ + CEIL_SHIFT(lines_per_frame / 2, deci_factor_log2) +#define ISP_C_VECTORS_PER_LINE(elements_per_line) \ + _ISP_VECS(elements_per_line / 2) + +/* The morphing table is similar to the shading table in the sense that we + have 1 more value than we have cells in the grid. */ +#define _ISP_MORPH_TABLE_WIDTH(int_width) \ + (CEIL_DIV(int_width, SH_CSS_MORPH_TABLE_GRID) + 1) +#define _ISP_MORPH_TABLE_HEIGHT(int_height) \ + (CEIL_DIV(int_height, SH_CSS_MORPH_TABLE_GRID) + 1) +#define _ISP_MORPH_TABLE_ALIGNED_WIDTH(width) \ + CEIL_MUL(_ISP_MORPH_TABLE_WIDTH(width), \ + SH_CSS_MORPH_TABLE_ELEMS_PER_DDR_WORD) + +#define _ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ + (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + 1) +#define _ISP_SCTBL_HEIGHT(input_height, deci_factor_log2) \ + (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + 1) +#define _ISP_SCTBL_ALIGNED_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ + CEIL_MUL(_ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2), \ + ISP_VEC_NELEMS) + +/* To position the shading center grid point on the center of output image, + * one more grid cell is needed as margin. */ +#define SH_CSS_SCTBL_CENTERING_MARGIN 1 + +/* The shading table width and height are the number of grids, not cells. The last grid should be counted. */ +#define SH_CSS_SCTBL_LAST_GRID_COUNT 1 + +/* Number of horizontal grids per color in the shading table. */ +#define _ISP2401_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ + (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + \ + SH_CSS_SCTBL_CENTERING_MARGIN + SH_CSS_SCTBL_LAST_GRID_COUNT) + +/* Number of vertical grids per color in the shading table. */ +#define _ISP2401_SCTBL_HEIGHT(input_height, deci_factor_log2) \ + (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + \ + SH_CSS_SCTBL_CENTERING_MARGIN + SH_CSS_SCTBL_LAST_GRID_COUNT) + +/* ISP2401: Legacy API: Number of horizontal grids per color in the shading table. */ +#define _ISP_SCTBL_LEGACY_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ + (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + SH_CSS_SCTBL_LAST_GRID_COUNT) + +/* ISP2401: Legacy API: Number of vertical grids per color in the shading table. */ +#define _ISP_SCTBL_LEGACY_HEIGHT(input_height, deci_factor_log2) \ + (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + SH_CSS_SCTBL_LAST_GRID_COUNT) + +/* ***************************************************************** + * Statistics for 3A (Auto Focus, Auto White Balance, Auto Exposure) + * *****************************************************************/ +/* if left cropping is used, 3A statistics are also cropped by 2 vectors. */ +#define _ISP_S3ATBL_WIDTH(in_width, deci_factor_log2) \ + (_ISP_BQS(in_width) >> deci_factor_log2) +#define _ISP_S3ATBL_HEIGHT(in_height, deci_factor_log2) \ + (_ISP_BQS(in_height) >> deci_factor_log2) +#define _ISP_S3A_ELEMS_ISP_WIDTH(width, left_crop) \ + (width - ((left_crop) ? 2 * ISP_VEC_NELEMS : 0)) + +#define _ISP_S3ATBL_ISP_WIDTH(in_width, deci_factor_log2) \ + CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2) +#define _ISP_S3ATBL_ISP_HEIGHT(in_height, deci_factor_log2) \ + CEIL_SHIFT(_ISP_BQS(in_height), deci_factor_log2) +#define ISP_S3ATBL_VECTORS \ + _ISP_VECS(SH_CSS_MAX_S3ATBL_WIDTH * \ + (sizeof(struct ia_css_3a_output) / sizeof(int32_t))) +#define ISP_S3ATBL_HI_LO_STRIDE \ + (ISP_S3ATBL_VECTORS * ISP_VEC_NELEMS) +#define ISP_S3ATBL_HI_LO_STRIDE_BYTES \ + (sizeof(unsigned short) * ISP_S3ATBL_HI_LO_STRIDE) + +/* Viewfinder support */ +#define __ISP_MAX_VF_OUTPUT_WIDTH(width, left_crop) \ + (width - 2 * ISP_VEC_NELEMS + ((left_crop) ? 2 * ISP_VEC_NELEMS : 0)) + +#define __ISP_VF_OUTPUT_WIDTH_VECS(out_width, vf_log_downscale) \ + (_ISP_VECS((out_width) >> (vf_log_downscale))) + +#define _ISP_VF_OUTPUT_WIDTH(vf_out_vecs) ((vf_out_vecs) * ISP_VEC_NELEMS) +#define _ISP_VF_OUTPUT_HEIGHT(out_height, vf_log_ds) \ + ((out_height) >> (vf_log_ds)) + +#define _ISP_LOG_VECTOR_STEP(mode) \ + ((mode) == IA_CSS_BINARY_MODE_CAPTURE_PP ? 2 : 1) + +/* It is preferred to have not more than 2x scaling at one step + * in GDC (assumption is for capture_pp and yuv_scale stages) */ +#define MAX_PREFERRED_YUV_DS_PER_STEP 2 + +/* Rules for computing the internal width. This is extremely complicated + * and definitely needs to be commented and explained. */ +#define _ISP_LEFT_CROP_EXTRA(left_crop) ((left_crop) > 0 ? 2 * ISP_VEC_NELEMS : 0) + +#define __ISP_MIN_INTERNAL_WIDTH(num_chunks, pipelining, mode) \ + ((num_chunks) * (pipelining) * (1 << _ISP_LOG_VECTOR_STEP(mode)) * \ + ISP_VEC_NELEMS) + +#define __ISP_PADDED_OUTPUT_WIDTH(out_width, dvs_env_width, left_crop) \ + ((out_width) + MAX(dvs_env_width, _ISP_LEFT_CROP_EXTRA(left_crop))) + +#define __ISP_CHUNK_STRIDE_ISP(mode) \ + ((1 << _ISP_LOG_VECTOR_STEP(mode)) * ISP_VEC_NELEMS) + +#define __ISP_CHUNK_STRIDE_DDR(c_subsampling, num_chunks) \ + ((c_subsampling) * (num_chunks) * HIVE_ISP_DDR_WORD_BYTES) +#define __ISP_INTERNAL_WIDTH(out_width, \ + dvs_env_width, \ + left_crop, \ + mode, \ + c_subsampling, \ + num_chunks, \ + pipelining) \ + CEIL_MUL2(CEIL_MUL2(MAX(__ISP_PADDED_OUTPUT_WIDTH(out_width, \ + dvs_env_width, \ + left_crop), \ + __ISP_MIN_INTERNAL_WIDTH(num_chunks, \ + pipelining, \ + mode) \ + ), \ + __ISP_CHUNK_STRIDE_ISP(mode) \ + ), \ + __ISP_CHUNK_STRIDE_DDR(c_subsampling, num_chunks) \ + ) + +#define __ISP_INTERNAL_HEIGHT(out_height, dvs_env_height, top_crop) \ + ((out_height) + (dvs_env_height) + top_crop) + +/* @GC: Input can be up to sensor resolution when either bayer downscaling + * or raw binning is enabled. + * Also, during continuous mode, we need to align to 4*NWAY since input + * should support binning */ +#define _ISP_MAX_INPUT_WIDTH(max_internal_width, enable_ds, enable_fixed_bayer_ds, enable_raw_bin, \ + enable_continuous) \ + ((enable_ds) ? \ + SH_CSS_MAX_SENSOR_WIDTH :\ + (enable_fixed_bayer_ds) ? \ + CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC, 4 * ISP_VEC_NELEMS) : \ + (enable_raw_bin) ? \ + CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH, 4 * ISP_VEC_NELEMS) : \ + (enable_continuous) ? \ + SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH \ + : max_internal_width) + +#define _ISP_INPUT_WIDTH(internal_width, ds_input_width, enable_ds) \ + ((enable_ds) ? (ds_input_width) : (internal_width)) + +#define _ISP_MAX_INPUT_HEIGHT(max_internal_height, enable_ds, enable_fixed_bayer_ds, enable_raw_bin, \ + enable_continuous) \ + ((enable_ds) ? \ + SH_CSS_MAX_SENSOR_HEIGHT :\ + (enable_fixed_bayer_ds) ? \ + SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC : \ + (enable_raw_bin || enable_continuous) ? \ + SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT \ + : max_internal_height) + +#define _ISP_INPUT_HEIGHT(internal_height, ds_input_height, enable_ds) \ + ((enable_ds) ? (ds_input_height) : (internal_height)) + +#define SH_CSS_MAX_STAGES 8 /* primary_stage[1-6], capture_pp, vf_pp */ + +/* For CSI2+ input system, it requires extra paddinga from vmem */ +#define _ISP_EXTRA_PADDING_VECS 0 + +#endif /* _SH_CSS_DEFS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_dvs_info.h b/drivers/staging/media/atomisp/pci/sh_css_dvs_info.h new file mode 100644 index 000000000..6f058f132 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_dvs_info.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __SH_CSS_DVS_INFO_H__ +#define __SH_CSS_DVS_INFO_H__ + +#include + +/* horizontal 64x64 blocks round up to DVS_BLOCKDIM_X, make even */ +#define DVS_NUM_BLOCKS_X(X) (CEIL_MUL(CEIL_DIV((X), DVS_BLOCKDIM_X), 2)) + +/* vertical 64x64 blocks round up to DVS_BLOCKDIM_Y */ +#define DVS_NUM_BLOCKS_Y(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_LUMA)) + +/* Bilinear interpolation (HRT_GDC_BLI_MODE) is the supported method currently. + * Bicubic interpolation (HRT_GDC_BCI_MODE) is not supported yet */ +#define DVS_GDC_INTERP_METHOD HRT_GDC_BLI_MODE + +#define DVS_INPUT_BYTES_PER_PIXEL (1) + +#define DVS_NUM_BLOCKS_X_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_X)) + +#define DVS_NUM_BLOCKS_Y_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_CHROMA)) + +#endif /* __SH_CSS_DVS_INFO_H__ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_firmware.c b/drivers/staging/media/atomisp/pci/sh_css_firmware.c new file mode 100644 index 000000000..e7ef578db --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_firmware.c @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for memcpy() */ +#include +#include + +#include "hmm.h" + +#include +#include "platform_support.h" +#include "sh_css_firmware.h" + +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_internal.h" +#include "ia_css_isp_param.h" + +#include "assert_support.h" + +#include "isp.h" /* PMEM_WIDTH_LOG2 */ + +#include "ia_css_isp_params.h" +#include "ia_css_isp_configs.h" +#include "ia_css_isp_states.h" + +#define _STR(x) #x +#define STR(x) _STR(x) + +struct firmware_header { + struct sh_css_fw_bi_file_h file_header; + struct ia_css_fw_info binary_header; +}; + +struct fw_param { + const char *name; + const void *buffer; +}; + +static struct firmware_header *firmware_header; + +/* + * The string STR is a place holder + * which will be replaced with the actual RELEASE_VERSION + * during package generation. Please do not modify + */ +#ifdef ISP2401 +static const char *release_version = STR(irci_stable_candrpv_0415_20150521_0458); +#else +static const char *release_version = STR(irci_stable_candrpv_0415_20150423_1753); +#endif + +#define MAX_FW_REL_VER_NAME 300 +static char FW_rel_ver_name[MAX_FW_REL_VER_NAME] = "---"; + +struct ia_css_fw_info sh_css_sp_fw; +struct ia_css_blob_descr *sh_css_blob_info; /* Only ISP blob info (no SP) */ +unsigned int sh_css_num_binaries; /* This includes 1 SP binary */ + +static struct fw_param *fw_minibuffer; + +char *sh_css_get_fw_version(void) +{ + return FW_rel_ver_name; +} + +/* + * Split the loaded firmware into blobs + */ + +/* Setup sp/sp1 binary */ +static int +setup_binary(struct ia_css_fw_info *fw, const char *fw_data, + struct ia_css_fw_info *sh_css_fw, unsigned int binary_id) +{ + const char *blob_data; + + if ((!fw) || (!fw_data)) + return -EINVAL; + + blob_data = fw_data + fw->blob.offset; + + *sh_css_fw = *fw; + + sh_css_fw->blob.code = vmalloc(fw->blob.size); + if (!sh_css_fw->blob.code) + return -ENOMEM; + + memcpy((void *)sh_css_fw->blob.code, blob_data, fw->blob.size); + sh_css_fw->blob.data = (char *)sh_css_fw->blob.code + fw->blob.data_source; + fw_minibuffer[binary_id].buffer = sh_css_fw->blob.code; + + return 0; +} + +int +sh_css_load_blob_info(const char *fw, const struct ia_css_fw_info *bi, + struct ia_css_blob_descr *bd, + unsigned int index) +{ + const char *name; + const unsigned char *blob; + + if ((!fw) || (!bd)) + return -EINVAL; + + /* Special case: only one binary in fw */ + if (!bi) + bi = (const struct ia_css_fw_info *)fw; + + name = fw + bi->blob.prog_name_offset; + blob = (const unsigned char *)fw + bi->blob.offset; + + /* sanity check */ + if (bi->blob.size != + bi->blob.text_size + bi->blob.icache_size + + bi->blob.data_size + bi->blob.padding_size) { + /* sanity check, note the padding bytes added for section to DDR alignment */ + return -EINVAL; + } + + if ((bi->blob.offset % (1UL << (ISP_PMEM_WIDTH_LOG2 - 3))) != 0) + return -EINVAL; + + bd->blob = blob; + bd->header = *bi; + + if (bi->type == ia_css_isp_firmware || bi->type == ia_css_sp_firmware) { + char *namebuffer; + + namebuffer = kstrdup(name, GFP_KERNEL); + if (!namebuffer) + return -ENOMEM; + bd->name = fw_minibuffer[index].name = namebuffer; + } else { + bd->name = name; + } + + if (bi->type == ia_css_isp_firmware) { + size_t paramstruct_size = sizeof(struct ia_css_memory_offsets); + size_t configstruct_size = sizeof(struct ia_css_config_memory_offsets); + size_t statestruct_size = sizeof(struct ia_css_state_memory_offsets); + + char *parambuf = kmalloc(paramstruct_size + configstruct_size + + statestruct_size, + GFP_KERNEL); + if (!parambuf) + return -ENOMEM; + + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_PARAM].ptr = NULL; + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_CONFIG].ptr = NULL; + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_STATE].ptr = NULL; + + fw_minibuffer[index].buffer = parambuf; + + /* copy ia_css_memory_offsets */ + memcpy(parambuf, (void *)(fw + + bi->blob.memory_offsets.offsets[IA_CSS_PARAM_CLASS_PARAM]), + paramstruct_size); + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_PARAM].ptr = parambuf; + + /* copy ia_css_config_memory_offsets */ + memcpy(parambuf + paramstruct_size, + (void *)(fw + bi->blob.memory_offsets.offsets[IA_CSS_PARAM_CLASS_CONFIG]), + configstruct_size); + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_CONFIG].ptr = parambuf + + paramstruct_size; + + /* copy ia_css_state_memory_offsets */ + memcpy(parambuf + paramstruct_size + configstruct_size, + (void *)(fw + bi->blob.memory_offsets.offsets[IA_CSS_PARAM_CLASS_STATE]), + statestruct_size); + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_STATE].ptr = parambuf + + paramstruct_size + configstruct_size; + } + return 0; +} + +bool +sh_css_check_firmware_version(struct device *dev, const char *fw_data) +{ + struct sh_css_fw_bi_file_h *file_header; + + firmware_header = (struct firmware_header *)fw_data; + file_header = &firmware_header->file_header; + + if (strcmp(file_header->version, release_version) != 0) { + dev_err(dev, "Firmware version may not be compatible with this driver\n"); + dev_err(dev, "Expecting version '%s', but firmware is '%s'.\n", + release_version, file_header->version); + } + + /* For now, let's just accept a wrong version, even if wrong */ + return false; +} + +static const char * const fw_type_name[] = { + [ia_css_sp_firmware] = "SP", + [ia_css_isp_firmware] = "ISP", + [ia_css_bootloader_firmware] = "BootLoader", + [ia_css_acc_firmware] = "accel", +}; + +static const char * const fw_acc_type_name[] = { + [IA_CSS_ACC_NONE] = "Normal", + [IA_CSS_ACC_OUTPUT] = "Accel for output", + [IA_CSS_ACC_VIEWFINDER] = "Accel for viewfinder", + [IA_CSS_ACC_STANDALONE] = "Stand-alone accel", +}; + +int +sh_css_load_firmware(struct device *dev, const char *fw_data, + unsigned int fw_size) +{ + unsigned int i; + struct ia_css_fw_info *binaries; + struct sh_css_fw_bi_file_h *file_header; + int ret; + + firmware_header = (struct firmware_header *)fw_data; + file_header = &firmware_header->file_header; + binaries = &firmware_header->binary_header; + strscpy(FW_rel_ver_name, file_header->version, + min(sizeof(FW_rel_ver_name), sizeof(file_header->version))); + ret = sh_css_check_firmware_version(dev, fw_data); + if (ret) { + IA_CSS_ERROR("CSS code version (%s) and firmware version (%s) mismatch!", + file_header->version, release_version); + return -EINVAL; + } else { + IA_CSS_LOG("successfully load firmware version %s", release_version); + } + + /* some sanity checks */ + if (!fw_data || fw_size < sizeof(struct sh_css_fw_bi_file_h)) + return -EINVAL; + + if (file_header->h_size != sizeof(struct sh_css_fw_bi_file_h)) + return -EINVAL; + + sh_css_num_binaries = file_header->binary_nr; + /* Only allocate memory for ISP blob info */ + if (sh_css_num_binaries > NUM_OF_SPS) { + sh_css_blob_info = kmalloc( + (sh_css_num_binaries - NUM_OF_SPS) * + sizeof(*sh_css_blob_info), GFP_KERNEL); + if (!sh_css_blob_info) + return -ENOMEM; + } else { + sh_css_blob_info = NULL; + } + + fw_minibuffer = kcalloc(sh_css_num_binaries, sizeof(struct fw_param), + GFP_KERNEL); + if (!fw_minibuffer) + return -ENOMEM; + + for (i = 0; i < sh_css_num_binaries; i++) { + struct ia_css_fw_info *bi = &binaries[i]; + /* + * note: the var below is made static as it is quite large; + * if it is not static it ends up on the stack which could + * cause issues for drivers + */ + static struct ia_css_blob_descr bd; + int err; + + err = sh_css_load_blob_info(fw_data, bi, &bd, i); + + if (err) + return -EINVAL; + + if (bi->blob.offset + bi->blob.size > fw_size) + return -EINVAL; + + switch (bd.header.type) { + case ia_css_isp_firmware: + if (bd.header.info.isp.type > IA_CSS_ACC_STANDALONE) { + dev_err(dev, "binary #%2d: invalid SP type\n", + i); + return -EINVAL; + } + + dev_dbg(dev, + "binary #%-2d type %s (%s), binary id is %2d: %s\n", + i, + fw_type_name[bd.header.type], + fw_acc_type_name[bd.header.info.isp.type], + bd.header.info.isp.sp.id, + bd.name); + break; + case ia_css_sp_firmware: + case ia_css_bootloader_firmware: + case ia_css_acc_firmware: + dev_dbg(dev, + "binary #%-2d type %s: %s\n", + i, fw_type_name[bd.header.type], + bd.name); + break; + default: + if (bd.header.info.isp.type > IA_CSS_ACC_STANDALONE) { + dev_err(dev, + "binary #%2d: invalid firmware type\n", + i); + return -EINVAL; + } + break; + } + + if (bi->type == ia_css_sp_firmware) { + if (i != SP_FIRMWARE) + return -EINVAL; + err = setup_binary(bi, fw_data, &sh_css_sp_fw, i); + if (err) + return err; + + } else { + /* + * All subsequent binaries + * (including bootloaders) (i>NUM_OF_SPS) + * are ISP firmware + */ + if (i < NUM_OF_SPS) + return -EINVAL; + + if (bi->type != ia_css_isp_firmware) + return -EINVAL; + if (!sh_css_blob_info) /* cannot happen but KW does not see this */ + return -EINVAL; + sh_css_blob_info[i - NUM_OF_SPS] = bd; + } + } + + return 0; +} + +void sh_css_unload_firmware(void) +{ + /* release firmware minibuffer */ + if (fw_minibuffer) { + unsigned int i = 0; + + for (i = 0; i < sh_css_num_binaries; i++) { + kfree(fw_minibuffer[i].name); + kvfree(fw_minibuffer[i].buffer); + } + kfree(fw_minibuffer); + fw_minibuffer = NULL; + } + + memset(&sh_css_sp_fw, 0, sizeof(sh_css_sp_fw)); + kfree(sh_css_blob_info); + sh_css_blob_info = NULL; + sh_css_num_binaries = 0; +} + +ia_css_ptr +sh_css_load_blob(const unsigned char *blob, unsigned int size) +{ + ia_css_ptr target_addr = hmm_alloc(size); + /* + * this will allocate memory aligned to a DDR word boundary which + * is required for the CSS DMA to read the instructions. + */ + + assert(blob); + if (target_addr) + hmm_store(target_addr, blob, size); + return target_addr; +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_firmware.h b/drivers/staging/media/atomisp/pci/sh_css_firmware.h new file mode 100644 index 000000000..a73ce703a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_firmware.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_FIRMWARE_H_ +#define _SH_CSS_FIRMWARE_H_ + +#include + +#include +#include + +/* This is for the firmware loaded from user space */ +struct sh_css_fw_bi_file_h { + char version[64]; /* branch tag + week day + time */ + int binary_nr; /* Number of binaries */ + unsigned int h_size; /* sizeof(struct sh_css_fw_bi_file_h) */ +}; + +extern struct ia_css_fw_info sh_css_sp_fw; +extern struct ia_css_blob_descr *sh_css_blob_info; +extern unsigned int sh_css_num_binaries; + +char +*sh_css_get_fw_version(void); + +struct device; +bool +sh_css_check_firmware_version(struct device *dev, const char *fw_data); + +int +sh_css_load_firmware(struct device *dev, const char *fw_data, + unsigned int fw_size); + +void sh_css_unload_firmware(void); + +ia_css_ptr sh_css_load_blob(const unsigned char *blob, unsigned int size); + +int +sh_css_load_blob_info(const char *fw, const struct ia_css_fw_info *bi, + struct ia_css_blob_descr *bd, unsigned int i); + +#endif /* _SH_CSS_FIRMWARE_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_frac.h b/drivers/staging/media/atomisp/pci/sh_css_frac.h new file mode 100644 index 000000000..8f08df5c8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_frac.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_FRAC_H +#define __SH_CSS_FRAC_H + +#include + +#define sISP_REG_BIT ISP_VEC_ELEMBITS +#define uISP_REG_BIT ((unsigned int)(sISP_REG_BIT - 1)) +#define sSHIFT (16 - sISP_REG_BIT) +#define uSHIFT ((unsigned int)(16 - uISP_REG_BIT)) +#define sFRACTION_BITS_FITTING(a) (a - sSHIFT) +#define uFRACTION_BITS_FITTING(a) ((unsigned int)(a - uSHIFT)) +#define sISP_VAL_MIN (-(1 << uISP_REG_BIT)) +#define sISP_VAL_MAX ((1 << uISP_REG_BIT) - 1) +#define uISP_VAL_MIN (0U) +#define uISP_VAL_MAX ((unsigned int)((1 << uISP_REG_BIT) - 1)) + +/* a:fraction bits for 16bit precision, b:fraction bits for ISP precision */ +#define sDIGIT_FITTING(v, a, b) \ + min_t(int, max_t(int, (((v) >> sSHIFT) >> max(sFRACTION_BITS_FITTING(a) - (b), 0)), \ + sISP_VAL_MIN), sISP_VAL_MAX) +#define uDIGIT_FITTING(v, a, b) \ + min((unsigned int)max((unsigned)(((v) >> uSHIFT) \ + >> max((int)(uFRACTION_BITS_FITTING(a) - (b)), 0)), \ + uISP_VAL_MIN), uISP_VAL_MAX) + +#endif /* __SH_CSS_FRAC_H */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_host_data.c b/drivers/staging/media/atomisp/pci/sh_css_host_data.c new file mode 100644 index 000000000..39a9b9812 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_host_data.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +struct ia_css_host_data *ia_css_host_data_allocate(size_t size) +{ + struct ia_css_host_data *me; + + me = kmalloc(sizeof(struct ia_css_host_data), GFP_KERNEL); + if (!me) + return NULL; + me->size = (uint32_t)size; + me->address = kvmalloc(size, GFP_KERNEL); + if (!me->address) { + kfree(me); + return NULL; + } + return me; +} + +void ia_css_host_data_free(struct ia_css_host_data *me) +{ + if (me) { + kvfree(me->address); + me->address = NULL; + kfree(me); + } +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_hrt.c b/drivers/staging/media/atomisp/pci/sh_css_hrt.c new file mode 100644 index 000000000..879c85311 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_hrt.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "platform_support.h" + +#include "sh_css_hrt.h" +#include "ia_css_debug.h" + +#include "device_access.h" + +#define __INLINE_EVENT__ +#include "event_fifo.h" +#define __INLINE_SP__ +#include "sp.h" +#define __INLINE_ISP__ +#include "isp.h" +#define __INLINE_IRQ__ +#include "irq.h" +#define __INLINE_FIFO_MONITOR__ +#include "fifo_monitor.h" + +/* System independent */ +#include "sh_css_internal.h" + +bool sh_css_hrt_system_is_idle(void) +{ + bool not_idle = false, idle; + fifo_channel_t ch; + + idle = sp_ctrl_getbit(SP0_ID, SP_SC_REG, SP_IDLE_BIT); + not_idle |= !idle; + if (!idle) + IA_CSS_WARNING("SP not idle"); + + idle = isp_ctrl_getbit(ISP0_ID, ISP_SC_REG, ISP_IDLE_BIT); + not_idle |= !idle; + if (!idle) + IA_CSS_WARNING("ISP not idle"); + + for (ch = 0; ch < N_FIFO_CHANNEL; ch++) { + fifo_channel_state_t state; + + fifo_channel_get_state(FIFO_MONITOR0_ID, ch, &state); + if (state.fifo_valid) { + IA_CSS_WARNING("FIFO channel %d is not empty", ch); + not_idle = true; + } + } + + return !not_idle; +} + +int sh_css_hrt_sp_wait(void) +{ + irq_sw_channel_id_t irq_id = IRQ_SW_CHANNEL0_ID; + /* + * Wait till SP is idle or till there is a SW2 interrupt + * The SW2 interrupt will be used when frameloop runs on SP + * and signals an event with similar meaning as SP idle + * (e.g. frame_done) + */ + while (!sp_ctrl_getbit(SP0_ID, SP_SC_REG, SP_IDLE_BIT) && + ((irq_reg_load(IRQ0_ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX) & + (1U << (irq_id + IRQ_SW_CHANNEL_OFFSET))) == 0)) { + udelay(1); + } + + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_hrt.h b/drivers/staging/media/atomisp/pci/sh_css_hrt.h new file mode 100644 index 000000000..168bbd579 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_hrt.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_HRT_H_ +#define _SH_CSS_HRT_H_ + +#include +#include + +#include + +/* SP access */ +void sh_css_hrt_sp_start_si(void); + +void sh_css_hrt_sp_start_copy_frame(void); + +void sh_css_hrt_sp_start_isp(void); + +int sh_css_hrt_sp_wait(void); + +bool sh_css_hrt_system_is_idle(void); + +#endif /* _SH_CSS_HRT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_internal.h b/drivers/staging/media/atomisp/pci/sh_css_internal.h new file mode 100644 index 000000000..d98f13234 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_internal.h @@ -0,0 +1,981 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_INTERNAL_H_ +#define _SH_CSS_INTERNAL_H_ + +#include +#include +#include +#include +#include + +#if !defined(ISP2401) +#include "input_formatter.h" +#endif +#include "input_system.h" + +#include "ia_css_types.h" +#include "ia_css_acc_types.h" +#include "ia_css_buffer.h" + +#include "ia_css_binary.h" +#include "sh_css_firmware.h" /* not needed/desired on SP/ISP */ +#include "sh_css_legacy.h" +#include "sh_css_defs.h" +#include "sh_css_uds.h" +#include "dma.h" /* N_DMA_CHANNEL_ID */ +#include "ia_css_circbuf_comm.h" /* Circular buffer */ +#include "ia_css_frame_comm.h" +#include "ia_css_3a.h" +#include "ia_css_dvs.h" +#include "ia_css_metadata.h" +#include "runtime/bufq/interface/ia_css_bufq.h" +#include "ia_css_timer.h" + +/* TODO: Move to a more suitable place when sp pipeline design is done. */ +#define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2 +#define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1 +#define IA_CSS_NUM_CBS 2 +#define IA_CSS_CB_MAX_ELEMS 2 + +/* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or + * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively. + * TODO: Enforce the limitation above. +*/ +#define IA_CSS_COPYSINK_SEM_INDEX 0 +#define IA_CSS_TAGGER_SEM_INDEX 1 + +/* Force generation of output event. Used by acceleration pipe. */ +#define IA_CSS_POST_OUT_EVENT_FORCE 2 + +#define SH_CSS_MAX_BINARY_NAME 64 + +#define SP_DEBUG_NONE (0) +#define SP_DEBUG_DUMP (1) +#define SP_DEBUG_COPY (2) +#define SP_DEBUG_TRACE (3) +#define SP_DEBUG_MINIMAL (4) + +#define SP_DEBUG SP_DEBUG_NONE +#define SP_DEBUG_MINIMAL_OVERWRITE 1 + +#define SH_CSS_TNR_BIT_DEPTH 8 +#define SH_CSS_REF_BIT_DEPTH 8 + +/* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */ +#define NUM_CONTINUOUS_FRAMES 15 +#define NUM_MIPI_FRAMES_PER_STREAM 2 + +#define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2 + +#define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */ + +#define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/ +#define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF + +/* + * SH_CSS_MAX_SP_THREADS: + * sp threads visible to host with connected communication queues + * these threads are capable of running an image pipe + * SH_CSS_MAX_SP_INTERNAL_THREADS: + * internal sp service threads, no communication queues to host + * these threads can't be used as image pipe + */ + +#if !defined(ISP2401) +#define SH_CSS_SP_INTERNAL_METADATA_THREAD 1 +#else +#define SH_CSS_SP_INTERNAL_METADATA_THREAD 0 +#endif + +#define SH_CSS_SP_INTERNAL_SERVICE_THREAD 1 + +#define SH_CSS_MAX_SP_THREADS 5 + +#define SH_CSS_MAX_SP_INTERNAL_THREADS (\ + SH_CSS_SP_INTERNAL_SERVICE_THREAD +\ + SH_CSS_SP_INTERNAL_METADATA_THREAD) + +#define SH_CSS_MAX_PIPELINES SH_CSS_MAX_SP_THREADS + +/** + * The C99 standard does not specify the exact object representation of structs; + * the representation is compiler dependent. + * + * The structs that are communicated between host and SP/ISP should have the + * exact same object representation. The compiler that is used to compile the + * firmware is hivecc. + * + * To check if a different compiler, used to compile a host application, uses + * another object representation, macros are defined specifying the size of + * the structs as expected by the firmware. + * + * A host application shall verify that a sizeof( ) of the struct is equal to + * the SIZE_OF_XXX macro of the corresponding struct. If they are not + * equal, functionality will break. + */ +#define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x) +#define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32) +#define SIZE_OF_IA_CSS_PTR sizeof(uint32_t) + +/* Number of SP's */ +#define NUM_OF_SPS 1 + +#define NUM_OF_BLS 0 + +/* Enum for order of Binaries */ +enum sh_css_order_binaries { + SP_FIRMWARE = 0, + ISP_FIRMWARE +}; + +/* +* JB: keep next enum in sync with thread id's +* and pipe id's +*/ +enum sh_css_pipe_config_override { + SH_CSS_PIPE_CONFIG_OVRD_NONE = 0, + SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff +}; + +enum host2sp_commands { + host2sp_cmd_error = 0, + /* + * The host2sp_cmd_ready command is the only command written by the SP + * It acknowledges that is previous command has been received. + * (this does not mean that the command has been executed) + * It also indicates that a new command can be send (it is a queue + * with depth 1). + */ + host2sp_cmd_ready = 1, + /* Command written by the Host */ + host2sp_cmd_dummy, /* No action, can be used as watchdog */ + host2sp_cmd_start_flash, /* Request SP to start the flash */ + host2sp_cmd_terminate, /* SP should terminate itself */ + N_host2sp_cmd +}; + +/* Enumeration used to indicate the events that are produced by + * the SP and consumed by the Host. + * + * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: + * 1) "enum ia_css_event_type" (ia_css_event_public.h) + * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) + * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) + * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) + */ +enum sh_css_sp_event_type { + SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE, + SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE, + SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE, + SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE, + SH_CSS_SP_EVENT_3A_STATISTICS_DONE, + SH_CSS_SP_EVENT_DIS_STATISTICS_DONE, + SH_CSS_SP_EVENT_PIPELINE_DONE, + SH_CSS_SP_EVENT_FRAME_TAGGED, + SH_CSS_SP_EVENT_INPUT_FRAME_DONE, + SH_CSS_SP_EVENT_METADATA_DONE, + SH_CSS_SP_EVENT_LACE_STATISTICS_DONE, + SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE, + SH_CSS_SP_EVENT_TIMER, + SH_CSS_SP_EVENT_PORT_EOF, + SH_CSS_SP_EVENT_FW_WARNING, + SH_CSS_SP_EVENT_FW_ASSERT, + SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */ +}; + +/* xmem address map allocation per pipeline, css pointers */ +/* Note that the struct below should only consist of ia_css_ptr-es + Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map + */ +struct sh_css_ddr_address_map { + ia_css_ptr isp_param; + ia_css_ptr isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; + ia_css_ptr macc_tbl; + ia_css_ptr fpn_tbl; + ia_css_ptr sc_tbl; + ia_css_ptr tetra_r_x; + ia_css_ptr tetra_r_y; + ia_css_ptr tetra_gr_x; + ia_css_ptr tetra_gr_y; + ia_css_ptr tetra_gb_x; + ia_css_ptr tetra_gb_y; + ia_css_ptr tetra_b_x; + ia_css_ptr tetra_b_y; + ia_css_ptr tetra_ratb_x; + ia_css_ptr tetra_ratb_y; + ia_css_ptr tetra_batr_x; + ia_css_ptr tetra_batr_y; + ia_css_ptr dvs_6axis_params_y; +}; + +#define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \ + (SIZE_OF_HRT_VADDRESS + \ + (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \ + (16 * SIZE_OF_HRT_VADDRESS)) + +/* xmem address map allocation per pipeline */ +struct sh_css_ddr_address_map_size { + size_t isp_param; + size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; + size_t macc_tbl; + size_t fpn_tbl; + size_t sc_tbl; + size_t tetra_r_x; + size_t tetra_r_y; + size_t tetra_gr_x; + size_t tetra_gr_y; + size_t tetra_gb_x; + size_t tetra_gb_y; + size_t tetra_b_x; + size_t tetra_b_y; + size_t tetra_ratb_x; + size_t tetra_ratb_y; + size_t tetra_batr_x; + size_t tetra_batr_y; + size_t dvs_6axis_params_y; +}; + +struct sh_css_ddr_address_map_compound { + struct sh_css_ddr_address_map map; + struct sh_css_ddr_address_map_size size; +}; + +struct ia_css_isp_parameter_set_info { + struct sh_css_ddr_address_map + mem_map;/** pointers to Parameters in ISP format IMPT: + This should be first member of this struct */ + u32 + isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */ + ia_css_ptr + output_frame_ptr;/** Output frame to which this config has to be applied (optional) */ +}; + +/* this struct contains all arguments that can be passed to + a binary. It depends on the binary which ones are used. */ +struct sh_css_binary_args { + struct ia_css_frame *in_frame; /* input frame */ + const struct ia_css_frame + *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */ + const struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; /* tnr frames */ + struct ia_css_frame + *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */ + struct ia_css_frame *out_vf_frame; /* viewfinder output frame */ + bool copy_vf; + bool copy_output; + unsigned int vf_downscale_log2; +}; + +#if SP_DEBUG == SP_DEBUG_DUMP + +#define SH_CSS_NUM_SP_DEBUG 48 + +struct sh_css_sp_debug_state { + unsigned int error; + unsigned int debug[SH_CSS_NUM_SP_DEBUG]; +}; + +#elif SP_DEBUG == SP_DEBUG_COPY + +#define SH_CSS_SP_DBG_TRACE_DEPTH (40) + +struct sh_css_sp_debug_trace { + u16 frame; + u16 line; + u16 pixel_distance; + u16 mipi_used_dword; + u16 sp_index; +}; + +struct sh_css_sp_debug_state { + u16 if_start_line; + u16 if_start_column; + u16 if_cropped_height; + u16 if_cropped_width; + unsigned int index; + struct sh_css_sp_debug_trace + trace[SH_CSS_SP_DBG_TRACE_DEPTH]; +}; + +#elif SP_DEBUG == SP_DEBUG_TRACE + +/* Example of just one global trace */ +#define SH_CSS_SP_DBG_NR_OF_TRACES (1) +#define SH_CSS_SP_DBG_TRACE_DEPTH (40) + +#define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13) + +struct sh_css_sp_debug_trace { + u16 time_stamp; + u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */ + u32 data; +}; + +struct sh_css_sp_debug_state { + struct sh_css_sp_debug_trace + trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH]; + u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES]; + u8 index[SH_CSS_SP_DBG_NR_OF_TRACES]; +}; + +#elif SP_DEBUG == SP_DEBUG_MINIMAL + +#define SH_CSS_NUM_SP_DEBUG 128 + +struct sh_css_sp_debug_state { + unsigned int error; + unsigned int debug[SH_CSS_NUM_SP_DEBUG]; +}; + +#endif + +struct sh_css_sp_debug_command { + /* + * The DMA software-mask, + * Bit 31...24: unused. + * Bit 23...16: unused. + * Bit 15...08: reading-request enabling bits for DMA channel 7..0 + * Bit 07...00: writing-request enabling bits for DMA channel 7..0 + * + * For example, "0...0 0...0 11111011 11111101" indicates that the + * writing request through DMA Channel 1 and the reading request + * through DMA channel 2 are both disabled. The others are enabled. + */ + u32 dma_sw_reg; +}; + +#if !defined(ISP2401) +/* SP input formatter configuration.*/ +struct sh_css_sp_input_formatter_set { + u32 stream_format; + input_formatter_cfg_t config_a; + input_formatter_cfg_t config_b; +}; +#endif + +#define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3) + +/* SP configuration information */ +struct sh_css_sp_config { + u8 no_isp_sync; /* Signal host immediately after start */ + u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */ + u8 lock_all; + /** If raw buffer locking is enabled, this flag indicates whether raw + frames are locked when their EOF event is successfully sent to the + host (true) or when they are passed to the preview/video pipe + (false). */ +#if !defined(ISP2401) + struct { + u8 a_changed; + u8 b_changed; + u8 isp_2ppc; + struct sh_css_sp_input_formatter_set + set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */ + } input_formatter; +#endif +#if !defined(ISP2401) + sync_generator_cfg_t sync_gen; + tpg_cfg_t tpg; + prbs_cfg_t prbs; + input_system_cfg_t input_circuit; + u8 input_circuit_cfg_changed; + u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT]; +#endif + u8 enable_isys_event_queue; + u8 disable_cont_vf; +}; + +enum sh_css_stage_type { + SH_CSS_SP_STAGE_TYPE = 0, + SH_CSS_ISP_STAGE_TYPE = 1 +}; + +#define SH_CSS_NUM_STAGE_TYPES 2 + +#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0) +#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \ + ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1) + +#if defined(ISP2401) +struct sh_css_sp_pipeline_terminal { + union { + /* Input System 2401 */ + virtual_input_system_stream_t + virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; + } context; + /* + * TODO + * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready. + */ + union { + /* Input System 2401 */ + virtual_input_system_stream_cfg_t + virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; + } ctrl; +}; + +struct sh_css_sp_pipeline_io { + struct sh_css_sp_pipeline_terminal input; + /* pqiao: comment out temporarily to save dmem */ + /*struct sh_css_sp_pipeline_terminal output;*/ +}; + +/* This struct tracks how many streams are registered per CSI port. + * This is used to track which streams have already been configured. + * Only when all streams are configured, the CSI RX is started for that port. + */ +struct sh_css_sp_pipeline_io_status { + u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */ + u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */ +}; + +#endif +enum sh_css_port_dir { + SH_CSS_PORT_INPUT = 0, + SH_CSS_PORT_OUTPUT = 1 +}; + +enum sh_css_port_type { + SH_CSS_HOST_TYPE = 0, + SH_CSS_COPYSINK_TYPE = 1, + SH_CSS_TAGGERSINK_TYPE = 2 +}; + +/* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */ +#define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4) +#define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt)) +#define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0) +#define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) +#define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) +#define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \ + SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt)) +#define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) +#define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \ + (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \ + SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE))) + +#define IA_CSS_ACQUIRE_ISP_POS 31 + +/* Flags for metadata processing */ +#define SH_CSS_METADATA_ENABLED 0x01 +#define SH_CSS_METADATA_PROCESSED 0x02 +#define SH_CSS_METADATA_OFFLINE_MODE 0x04 +#define SH_CSS_METADATA_WAIT_INPUT 0x08 + +/* @brief Free an array of metadata buffers. + * + * @param[in] num_bufs Number of metadata buffers to be freed. + * @param[in] bufs Pointer of array of metadata buffers. + * + * This function frees an array of metadata buffers. + */ +void +ia_css_metadata_free_multiple(unsigned int num_bufs, + struct ia_css_metadata **bufs); + +/* Macro for handling pipe_qos_config */ +#define QOS_INVALID (~0U) + +/* Information for a pipeline */ +struct sh_css_sp_pipeline { + u32 pipe_id; /* the pipe ID */ + u32 pipe_num; /* the dynamic pipe number */ + u32 thread_id; /* the sp thread ID */ + u32 pipe_config; /* the pipe config */ + u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state. + (0xFFFFFFFF) indicates non QOS pipe.*/ + u32 inout_port_config; + u32 required_bds_factor; + u32 dvs_frame_delay; + u32 input_system_mode; /* enum ia_css_input_mode */ + u32 port_id; /* port_id for input system */ + u32 num_stages; /* the pipe config */ + u32 running; /* needed for pipe termination */ + ia_css_ptr sp_stage_addr[SH_CSS_MAX_STAGES]; + ia_css_ptr scaler_pp_lut; /* Early bound LUT */ + u32 dummy; /* stage ptr is only used on sp but lives in + this struct; needs cleanup */ + s32 num_execs; /* number of times to run if this is + an acceleration pipe. */ + struct { + u32 format; /* Metadata format in hrt format */ + u32 width; /* Width of a line */ + u32 height; /* Number of lines */ + u32 stride; /* Stride (in bytes) per line */ + u32 size; /* Total size (in bytes) */ + ia_css_ptr cont_buf; /* Address of continuous buffer */ + } metadata; + u32 output_frame_queue_id; + union { + struct { + u32 bytes_available; + } bin; + struct { + u32 height; + u32 width; + u32 padded_width; + u32 max_input_width; + u32 raw_bit_depth; + } raw; + } copy; +}; + +/* + * The first frames (with comment Dynamic) can be dynamic or static + * The other frames (ref_in and below) can only be static + * Static means that the data address will not change during the life time + * of the associated pipe. Dynamic means that the data address can + * change with every (frame) iteration of the associated pipe + * + * s3a and dis are now also dynamic but (stil) handled separately + */ +#define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3) + +struct ia_css_frames_sp { + struct ia_css_frame_sp in; + struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_resolution effective_in_res; + struct ia_css_frame_sp out_vf; + struct ia_css_frame_sp_info internal_frame_info; + struct ia_css_buffer_sp s3a_buf; + struct ia_css_buffer_sp dvs_buf; + struct ia_css_buffer_sp metadata_buf; +}; + +/* Information for a single pipeline stage for an ISP */ +struct sh_css_isp_stage { + /* + * For compatibility and portabilty, only types + * from "stdint.h" are allowed + * + * Use of "enum" and "bool" is prohibited + * Multiple boolean flags can be stored in an + * integer + */ + struct ia_css_blob_info blob_info; + struct ia_css_binary_info binary_info; + char binary_name[SH_CSS_MAX_BINARY_NAME]; + struct ia_css_isp_param_css_segments mem_initializers; +}; + +/* Information for a single pipeline stage */ +struct sh_css_sp_stage { + /* + * For compatibility and portabilty, only types + * from "stdint.h" are allowed + * + * Use of "enum" and "bool" is prohibited + * Multiple boolean flags can be stored in an + * integer + */ + u8 num; /* Stage number */ + u8 isp_online; + u8 isp_copy_vf; + u8 isp_copy_output; + u8 sp_enable_xnr; + u8 isp_deci_log_factor; + u8 isp_vf_downscale_bits; + u8 deinterleaved; + /* + * NOTE: Programming the input circuit can only be done at the + * start of a session. It is illegal to program it during execution + * The input circuit defines the connectivity + */ + u8 program_input_circuit; + /* enum ia_css_pipeline_stage_sp_func func; */ + u8 func; + /* The type of the pipe-stage */ + /* enum sh_css_stage_type stage_type; */ + u8 stage_type; + u8 num_stripes; + u8 isp_pipe_version; + struct { + u8 vf_output; + u8 s3a; + u8 sdis; + u8 dvs_stats; + u8 lace_stats; + } enable; + /* Add padding to come to a word boundary */ + /* unsigned char padding[0]; */ + + struct sh_css_crop_pos sp_out_crop_pos; + struct ia_css_frames_sp frames; + struct ia_css_resolution dvs_envelope; + struct sh_css_uds_info uds; + ia_css_ptr isp_stage_addr; + ia_css_ptr xmem_bin_addr; + ia_css_ptr xmem_map_addr; + + u16 top_cropping; + u16 row_stripes_height; + u16 row_stripes_overlap_lines; + u8 if_config_index; /* Which should be applied by this stage. */ +}; + +/* + * Time: 2012-07-19, 17:40. + * Note: Add a new data memeber "debug" in "sh_css_sp_group". This + * data member is used to pass the debugging command from the + * Host to the SP. + * + * Time: Before 2012-07-19. + * Note: + * Group all host initialized SP variables into this struct. + * This is initialized every stage through dma. + * The stage part itself is transferred through sh_css_sp_stage. +*/ +struct sh_css_sp_group { + struct sh_css_sp_config config; + struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS]; +#if defined(ISP2401) + struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS]; + struct sh_css_sp_pipeline_io_status pipe_io_status; +#endif + struct sh_css_sp_debug_command debug; +}; + +/* Data in SP dmem that is set from the host every stage. */ +struct sh_css_sp_per_frame_data { + /* ddr address of sp_group and sp_stage */ + ia_css_ptr sp_group_addr; +}; + +#define SH_CSS_NUM_SDW_IRQS 3 + +/* Output data from SP to css */ +struct sh_css_sp_output { + unsigned int bin_copy_bytes_copied; +#if SP_DEBUG != SP_DEBUG_NONE + struct sh_css_sp_debug_state debug; +#endif + unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS]; +}; + +/** + * @brief Data structure for the circular buffer. + * The circular buffer is empty if "start == end". The + * circular buffer is full if "(end + 1) % size == start". + */ +/* Variable Sized Buffer Queue Elements */ + +#define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6 +#define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3 +#define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6 + +/* sp-to-host queue is expected to be emptied in ISR since + * it is used instead of HW interrupts (due to HW design issue). + * We need one queue element per CSI port. */ +#define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) +/* The host-to-sp queue needs to allow for some delay + * in the emptying of this queue in the SP since there is no + * separate SP thread for this. */ +#define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) + +#define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13 +#define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19 +#define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */ + +struct sh_css_hmm_buffer { + union { + struct ia_css_isp_3a_statistics s3a; + struct ia_css_isp_dvs_statistics dis; + ia_css_ptr skc_dvs_statistics; + ia_css_ptr lace_stat; + struct ia_css_metadata metadata; + struct frame_data_wrapper { + ia_css_ptr frame_data; + u32 flashed; + u32 exp_id; + u32 isp_parameters_id; /** Unique ID to track which config was + actually applied to a particular frame */ + } frame; + ia_css_ptr ddr_ptrs; + } payload; + /* + * kernel_ptr is present for host administration purposes only. + * type is uint64_t in order to be 64-bit host compatible. + * uint64_t does not exist on SP/ISP. + * Size of the struct is checked by sp.hive.c. + */ + CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */ + u64 kernel_ptr; + struct ia_css_time_meas timing_data; + clock_value_t isys_eof_clock_tick; +}; + +#define SIZE_OF_FRAME_STRUCT \ + (SIZE_OF_HRT_VADDRESS + \ + (3 * sizeof(uint32_t))) + +#define SIZE_OF_PAYLOAD_UNION \ + (MAX(MAX(MAX(MAX( \ + SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \ + SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \ + SIZE_OF_IA_CSS_METADATA_STRUCT), \ + SIZE_OF_FRAME_STRUCT), \ + SIZE_OF_HRT_VADDRESS)) + +/* Do not use sizeof(uint64_t) since that does not exist of SP */ +#define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \ + (SIZE_OF_PAYLOAD_UNION + \ + CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \ + 8 + \ + 8 + \ + SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \ + SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \ + CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8)) + +enum sh_css_queue_type { + sh_css_invalid_queue_type = -1, + sh_css_host2sp_buffer_queue, + sh_css_sp2host_buffer_queue, + sh_css_host2sp_psys_event_queue, + sh_css_sp2host_psys_event_queue, + sh_css_sp2host_isys_event_queue, + sh_css_host2sp_isys_event_queue, + sh_css_host2sp_tag_cmd_queue, +}; + +struct sh_css_event_irq_mask { + u16 or_mask; + u16 and_mask; +}; + +#define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \ + (2 * sizeof(uint16_t)) + +struct host_sp_communication { + /* + * Don't use enum host2sp_commands, because the sizeof an enum is + * compiler dependent and thus non-portable + */ + u32 host2sp_command; + + /* + * The frame buffers that are reused by the + * copy pipe in the offline preview mode. + * + * host2sp_offline_frames[0]: the input frame of the preview pipe. + * host2sp_offline_frames[1]: the output frame of the copy pipe. + * + * TODO: + * Remove it when the Host and the SP is decoupled. + */ + ia_css_ptr host2sp_offline_frames[NUM_CONTINUOUS_FRAMES]; + ia_css_ptr host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES]; + + ia_css_ptr host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; + ia_css_ptr host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; + u32 host2sp_num_mipi_frames[N_CSI_PORTS]; + u32 host2sp_cont_avail_num_raw_frames; + u32 host2sp_cont_extra_num_raw_frames; + u32 host2sp_cont_target_num_raw_frames; + struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES]; + +}; + +#define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \ + (sizeof(uint32_t) + \ + (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \ + (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \ + ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \ + (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT)) + +struct host_sp_queues { + /* + * Queues for the dynamic frame information, + * i.e. the "in_frame" buffer, the "out_frame" + * buffer and the "vf_out_frame" buffer. + */ + ia_css_circbuf_desc_t host2sp_buffer_queues_desc + [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; + ia_css_circbuf_elem_t host2sp_buffer_queues_elems + [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES] + [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE]; + ia_css_circbuf_desc_t sp2host_buffer_queues_desc + [SH_CSS_MAX_NUM_QUEUES]; + ia_css_circbuf_elem_t sp2host_buffer_queues_elems + [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE]; + + /* + * The queues for the events. + */ + ia_css_circbuf_desc_t host2sp_psys_event_queue_desc; + + ia_css_circbuf_elem_t host2sp_psys_event_queue_elems + [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE]; + ia_css_circbuf_desc_t sp2host_psys_event_queue_desc; + + ia_css_circbuf_elem_t sp2host_psys_event_queue_elems + [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE]; + + /* + * The queues for the ISYS events. + */ + ia_css_circbuf_desc_t host2sp_isys_event_queue_desc; + + ia_css_circbuf_elem_t host2sp_isys_event_queue_elems + [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE]; + ia_css_circbuf_desc_t sp2host_isys_event_queue_desc; + + ia_css_circbuf_elem_t sp2host_isys_event_queue_elems + [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE]; + /* + * The queue for the tagger commands. + * CHECK: are these last two present on the 2401 ? + */ + ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc; + + ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems + [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE]; +}; + +#define SIZE_OF_QUEUES_ELEMS \ + (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \ + ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \ + (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \ + (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \ + (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \ + (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \ + (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \ + (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE))) + +#define IA_CSS_NUM_CIRCBUF_DESCS 5 + +#define SIZE_OF_QUEUES_DESC \ + ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \ + SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ + (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ + (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT)) + +#define SIZE_OF_HOST_SP_QUEUES_STRUCT \ + (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC) + +extern int __printf(1, 0) (*sh_css_printf)(const char *fmt, va_list args); + +static inline void __printf(1, 2) sh_css_print(const char *fmt, ...) +{ + va_list ap; + + if (sh_css_printf) { + va_start(ap, fmt); + sh_css_printf(fmt, ap); + va_end(ap); + } +} + +static inline void __printf(1, 0) sh_css_vprint(const char *fmt, va_list args) +{ + if (sh_css_printf) + sh_css_printf(fmt, args); +} + +/* The following #if is there because this header file is also included + by SP and ISP code but they do not need this data and HIVECC has alignment + issue with the firmware struct/union's. + More permanent solution will be to refactor this include. +*/ +ia_css_ptr sh_css_params_ddr_address_map(void); + +int +sh_css_params_init(void); + +void +sh_css_params_uninit(void); + +void +sh_css_binary_args_reset(struct sh_css_binary_args *args); + +/* Check two frames for equality (format, resolution, bits per element) */ +bool +sh_css_frame_equal_types(const struct ia_css_frame *frame_a, + const struct ia_css_frame *frame_b); + +bool +sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a, + const struct ia_css_frame_info *info_b); + +void +sh_css_capture_enable_bayer_downscaling(bool enable); + +void +sh_css_binary_print(const struct ia_css_binary *binary); + +/* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement. + When 0, no extra alignment is done. */ +void +sh_css_frame_info_set_width(struct ia_css_frame_info *info, + unsigned int width, + unsigned int aligned); + +#if !defined(ISP2401) + +unsigned int +sh_css_get_mipi_sizes_for_check(const unsigned int port, + const unsigned int idx); + +#endif + +ia_css_ptr +sh_css_store_sp_group_to_ddr(void); + +ia_css_ptr +sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage); + +ia_css_ptr +sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage); + +void +sh_css_update_uds_and_crop_info( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *in_frame_info, + const struct ia_css_frame_info *out_frame_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_dz_config *zoom, + const struct ia_css_vector *motion_vector, + struct sh_css_uds_info *uds, /* out */ + struct sh_css_crop_pos *sp_out_crop_pos, /* out */ + + bool enable_zoom +); + +void +sh_css_invalidate_shading_tables(struct ia_css_stream *stream); + +struct ia_css_pipeline * +ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe); + +unsigned int +ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe); + +unsigned int +ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe); + +bool +sh_css_continuous_is_enabled(uint8_t pipe_num); + +struct ia_css_pipe * +find_pipe_by_num(uint32_t pipe_num); + +#ifdef ISP2401 +void +ia_css_get_crop_offsets( + struct ia_css_pipe *pipe, + struct ia_css_frame_info *in_frame); +#endif + +#endif /* _SH_CSS_INTERNAL_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_legacy.h b/drivers/staging/media/atomisp/pci/sh_css_legacy.h new file mode 100644 index 000000000..cdf239b07 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_legacy.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_LEGACY_H_ +#define _SH_CSS_LEGACY_H_ + +#include +#include +#include +#include +#include +#include + +/* The pipe id type, distinguishes the kind of pipes that + * can be run in parallel. + */ +enum ia_css_pipe_id { + IA_CSS_PIPE_ID_PREVIEW, + IA_CSS_PIPE_ID_COPY, + IA_CSS_PIPE_ID_VIDEO, + IA_CSS_PIPE_ID_CAPTURE, + IA_CSS_PIPE_ID_YUVPP, + IA_CSS_PIPE_ID_NUM +}; + +struct ia_css_pipe_extra_config { + bool enable_raw_binning; + bool enable_yuv_ds; + bool enable_high_speed; + bool enable_dvs_6axis; + bool enable_reduced_pipe; + bool enable_fractional_ds; + bool disable_vf_pp; +}; + +int +ia_css_pipe_create_extra(const struct ia_css_pipe_config *config, + const struct ia_css_pipe_extra_config *extra_config, + struct ia_css_pipe **pipe); + +void +ia_css_pipe_extra_config_defaults(struct ia_css_pipe_extra_config + *extra_config); + +int +ia_css_temp_pipe_to_pipe_id(const struct ia_css_pipe *pipe, + enum ia_css_pipe_id *pipe_id); + +/* DEPRECATED. FPN is not supported. */ +int +sh_css_set_black_frame(struct ia_css_stream *stream, + const struct ia_css_frame *raw_black_frame); + +/* ISP2400 */ +void +sh_css_enable_cont_capt(bool enable, bool stop_copy_preview); + +#endif /* _SH_CSS_LEGACY_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_metrics.c b/drivers/staging/media/atomisp/pci/sh_css_metrics.c new file mode 100644 index 000000000..8ded6cdd1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_metrics.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "assert_support.h" +#include "sh_css_metrics.h" + +#include "sp.h" +#include "isp.h" + +#include "sh_css_internal.h" + +#define MULTIPLE_PCS 0 +#define SUSPEND 0 +#define NOF_PCS 1 +#define RESUME_MASK 0x8 +#define STOP_MASK 0x0 + +static bool pc_histogram_enabled; +static struct sh_css_pc_histogram *isp_histogram; +static struct sh_css_pc_histogram *sp_histogram; + +struct sh_css_metrics sh_css_metrics; + +void +sh_css_metrics_start_frame(void) +{ + sh_css_metrics.frame_metrics.num_frames++; +} + +static void +clear_histogram(struct sh_css_pc_histogram *histogram) +{ + unsigned int i; + + assert(histogram); + + for (i = 0; i < histogram->length; i++) { + histogram->run[i] = 0; + histogram->stall[i] = 0; + histogram->msink[i] = 0xFFFF; + } +} + +void +sh_css_metrics_enable_pc_histogram(bool enable) +{ + pc_histogram_enabled = enable; +} + +static void +make_histogram(struct sh_css_pc_histogram *histogram, unsigned int length) +{ + assert(histogram); + + if (histogram->length) + return; + if (histogram->run) + return; + histogram->run = kvmalloc(length * sizeof(*histogram->run), + GFP_KERNEL); + if (!histogram->run) + return; + histogram->stall = kvmalloc(length * sizeof(*histogram->stall), + GFP_KERNEL); + if (!histogram->stall) + return; + histogram->msink = kvmalloc(length * sizeof(*histogram->msink), + GFP_KERNEL); + if (!histogram->msink) + return; + + histogram->length = length; + clear_histogram(histogram); +} + +static void +insert_binary_metrics(struct sh_css_binary_metrics **l, + struct sh_css_binary_metrics *metrics) +{ + assert(l); + assert(*l); + assert(metrics); + + for (; *l; l = &(*l)->next) + if (*l == metrics) + return; + + *l = metrics; + metrics->next = NULL; +} + +void +sh_css_metrics_start_binary(struct sh_css_binary_metrics *metrics) +{ + assert(metrics); + + if (!pc_histogram_enabled) + return; + + isp_histogram = &metrics->isp_histogram; + sp_histogram = &metrics->sp_histogram; + make_histogram(isp_histogram, ISP_PMEM_DEPTH); + make_histogram(sp_histogram, SP_PMEM_DEPTH); + insert_binary_metrics(&sh_css_metrics.binary_metrics, metrics); +} + +void +sh_css_metrics_sample_pcs(void) +{ + bool stall; + unsigned int pc; + unsigned int msink; + + + + if (!pc_histogram_enabled) + return; + + if (isp_histogram) { + msink = isp_ctrl_load(ISP0_ID, ISP_CTRL_SINK_REG); + pc = isp_ctrl_load(ISP0_ID, ISP_PC_REG); + + isp_histogram->msink[pc] &= msink; + stall = (msink != 0x7FF); + + if (stall) + isp_histogram->stall[pc]++; + else + isp_histogram->run[pc]++; + } + + if (sp_histogram && 0) { + msink = sp_ctrl_load(SP0_ID, SP_CTRL_SINK_REG); + pc = sp_ctrl_load(SP0_ID, SP_PC_REG); + sp_histogram->msink[pc] &= msink; + stall = (msink != 0x7FF); + if (stall) + sp_histogram->stall[pc]++; + else + sp_histogram->run[pc]++; + } +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_metrics.h b/drivers/staging/media/atomisp/pci/sh_css_metrics.h new file mode 100644 index 000000000..f4bcd0838 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_metrics.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_METRICS_H_ +#define _SH_CSS_METRICS_H_ + +#include + +struct sh_css_pc_histogram { + unsigned int length; + unsigned int *run; + unsigned int *stall; + unsigned int *msink; +}; + +struct sh_css_binary_metrics { + unsigned int mode; + unsigned int id; + struct sh_css_pc_histogram isp_histogram; + struct sh_css_pc_histogram sp_histogram; + struct sh_css_binary_metrics *next; +}; + +struct ia_css_frame_metrics { + unsigned int num_frames; +}; + +struct sh_css_metrics { + struct sh_css_binary_metrics *binary_metrics; + struct ia_css_frame_metrics frame_metrics; +}; + +extern struct sh_css_metrics sh_css_metrics; + +/* includes ia_css_binary.h, which depends on sh_css_metrics.h */ +#include "ia_css_types.h" + +/* Sample ISP and SP pc and add to histogram */ +void sh_css_metrics_enable_pc_histogram(bool enable); +void sh_css_metrics_start_frame(void); +void sh_css_metrics_start_binary(struct sh_css_binary_metrics *metrics); +void sh_css_metrics_sample_pcs(void); + +#endif /* _SH_CSS_METRICS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_mipi.c b/drivers/staging/media/atomisp/pci/sh_css_mipi.c new file mode 100644 index 000000000..bc6e8598a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_mipi.c @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_mipi.h" +#include "sh_css_mipi.h" +#include +#include "system_global.h" +#include "ia_css_err.h" +#include "ia_css_pipe.h" +#include "ia_css_stream_format.h" +#include "sh_css_stream_format.h" +#include "ia_css_stream_public.h" +#include "ia_css_frame_public.h" +#include "ia_css_input_port.h" +#include "ia_css_debug.h" +#include "sh_css_struct.h" +#include "sh_css_defs.h" +#include "sh_css_sp.h" /* sh_css_update_host2sp_mipi_frame sh_css_update_host2sp_num_mipi_frames ... */ +#include "sw_event_global.h" /* IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY */ + +static u32 +ref_count_mipi_allocation[N_CSI_PORTS]; /* Initialized in mipi_init */ + +/* Assumptions: + * - A line is multiple of 4 bytes = 1 word. + * - Each frame has SOF and EOF (each 1 word). + * - Each line has format header and optionally SOL and EOL (each 1 word). + * - Odd and even lines of YUV420 format are different in bites per pixel size. + * - Custom size of embedded data. + * -- Interleaved frames are not taken into account. + * -- Lines are multiples of 8B, and not necessary of (custom 3B, or 7B + * etc.). + * Result is given in DDR mem words, 32B or 256 bits + */ +int +ia_css_mipi_frame_calculate_size(const unsigned int width, + const unsigned int height, + const enum atomisp_input_format format, + const bool hasSOLandEOL, + const unsigned int embedded_data_size_words, + unsigned int *size_mem_words) +{ + int err = 0; + + unsigned int bits_per_pixel = 0; + unsigned int even_line_bytes = 0; + unsigned int odd_line_bytes = 0; + unsigned int words_per_odd_line = 0; + unsigned int words_for_first_line = 0; + unsigned int words_per_even_line = 0; + unsigned int mem_words_per_even_line = 0; + unsigned int mem_words_per_odd_line = 0; + unsigned int mem_words_for_first_line = 0; + unsigned int mem_words_for_EOF = 0; + unsigned int mem_words = 0; + unsigned int width_padded = width; + +#if defined(ISP2401) + /* The changes will be reverted as soon as RAW + * Buffers are deployed by the 2401 Input System + * in the non-continuous use scenario. + */ + width_padded += (2 * ISP_VEC_NELEMS); +#endif + + IA_CSS_ENTER("padded_width=%d, height=%d, format=%d, hasSOLandEOL=%d, embedded_data_size_words=%d\n", + width_padded, height, format, hasSOLandEOL, embedded_data_size_words); + + switch (format) { + case ATOMISP_INPUT_FORMAT_RAW_6: /* 4p, 3B, 24bits */ + bits_per_pixel = 6; + break; + case ATOMISP_INPUT_FORMAT_RAW_7: /* 8p, 7B, 56bits */ + bits_per_pixel = 7; + break; + case ATOMISP_INPUT_FORMAT_RAW_8: /* 1p, 1B, 8bits */ + case ATOMISP_INPUT_FORMAT_BINARY_8: /* 8bits, TODO: check. */ + case ATOMISP_INPUT_FORMAT_YUV420_8: /* odd 2p, 2B, 16bits, even 2p, 4B, 32bits */ + bits_per_pixel = 8; + break; + case ATOMISP_INPUT_FORMAT_YUV420_10: /* odd 4p, 5B, 40bits, even 4p, 10B, 80bits */ + case ATOMISP_INPUT_FORMAT_RAW_10: /* 4p, 5B, 40bits */ + /* The changes will be reverted as soon as RAW + * Buffers are deployed by the 2401 Input System + * in the non-continuous use scenario. + */ + bits_per_pixel = 10; + break; + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: /* 2p, 3B, 24bits */ + case ATOMISP_INPUT_FORMAT_RAW_12: /* 2p, 3B, 24bits */ + bits_per_pixel = 12; + break; + case ATOMISP_INPUT_FORMAT_RAW_14: /* 4p, 7B, 56bits */ + bits_per_pixel = 14; + break; + case ATOMISP_INPUT_FORMAT_RGB_444: /* 1p, 2B, 16bits */ + case ATOMISP_INPUT_FORMAT_RGB_555: /* 1p, 2B, 16bits */ + case ATOMISP_INPUT_FORMAT_RGB_565: /* 1p, 2B, 16bits */ + case ATOMISP_INPUT_FORMAT_YUV422_8: /* 2p, 4B, 32bits */ + bits_per_pixel = 16; + break; + case ATOMISP_INPUT_FORMAT_RGB_666: /* 4p, 9B, 72bits */ + bits_per_pixel = 18; + break; + case ATOMISP_INPUT_FORMAT_YUV422_10: /* 2p, 5B, 40bits */ + bits_per_pixel = 20; + break; + case ATOMISP_INPUT_FORMAT_RGB_888: /* 1p, 3B, 24bits */ + bits_per_pixel = 24; + break; + + case ATOMISP_INPUT_FORMAT_YUV420_16: /* Not supported */ + case ATOMISP_INPUT_FORMAT_YUV422_16: /* Not supported */ + case ATOMISP_INPUT_FORMAT_RAW_16: /* TODO: not specified in MIPI SPEC, check */ + default: + return -EINVAL; + } + + odd_line_bytes = (width_padded * bits_per_pixel + 7) >> 3; /* ceil ( bits per line / 8) */ + + /* Even lines for YUV420 formats are double in bits_per_pixel. */ + if (format == ATOMISP_INPUT_FORMAT_YUV420_8 + || format == ATOMISP_INPUT_FORMAT_YUV420_10 + || format == ATOMISP_INPUT_FORMAT_YUV420_16) { + even_line_bytes = (width_padded * 2 * bits_per_pixel + 7) >> + 3; /* ceil ( bits per line / 8) */ + } else { + even_line_bytes = odd_line_bytes; + } + + /* a frame represented in memory: ()- optional; data - payload words. + * addr 0 1 2 3 4 5 6 7: + * first SOF (SOL) PACK_H data data data data data + * data data data data data data data data + * ... + * data data 0 0 0 0 0 0 + * second (EOL) (SOL) PACK_H data data data data data + * data data data data data data data data + * ... + * data data 0 0 0 0 0 0 + * ... + * last (EOL) EOF 0 0 0 0 0 0 + * + * Embedded lines are regular lines stored before the first and after + * payload lines. + */ + + words_per_odd_line = (odd_line_bytes + 3) >> 2; + /* ceil(odd_line_bytes/4); word = 4 bytes */ + words_per_even_line = (even_line_bytes + 3) >> 2; + words_for_first_line = words_per_odd_line + 2 + (hasSOLandEOL ? 1 : 0); + /* + SOF +packet header + optionally (SOL), but (EOL) is not in the first line */ + words_per_odd_line += (1 + (hasSOLandEOL ? 2 : 0)); + /* each non-first line has format header, and optionally (SOL) and (EOL). */ + words_per_even_line += (1 + (hasSOLandEOL ? 2 : 0)); + + mem_words_per_odd_line = (words_per_odd_line + 7) >> 3; + /* ceil(words_per_odd_line/8); mem_word = 32 bytes, 8 words */ + mem_words_for_first_line = (words_for_first_line + 7) >> 3; + mem_words_per_even_line = (words_per_even_line + 7) >> 3; + mem_words_for_EOF = 1; /* last line consisit of the optional (EOL) and EOF */ + + mem_words = ((embedded_data_size_words + 7) >> 3) + + mem_words_for_first_line + + (((height + 1) >> 1) - 1) * mem_words_per_odd_line + + /* ceil (height/2) - 1 (first line is calculated separatelly) */ + (height >> 1) * mem_words_per_even_line + /* floor(height/2) */ + mem_words_for_EOF; + + *size_mem_words = mem_words; /* ceil(words/8); mem word is 32B = 8words. */ + /* Check if the above is still needed. */ + + IA_CSS_LEAVE_ERR(err); + return err; +} + +/* + * Check if a source port or TPG/PRBS ID is valid + */ + +#if !defined(ISP2401) +int +ia_css_mipi_frame_enable_check_on_size(const enum mipi_port_id port, + const unsigned int size_mem_words) +{ + u32 idx; + + int err = -EBUSY; + + OP___assert(port < N_CSI_PORTS); + OP___assert(size_mem_words != 0); + + for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT && + my_css.mipi_sizes_for_check[port][idx] != 0; + idx++) { /* do nothing */ + } + if (idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT) { + my_css.mipi_sizes_for_check[port][idx] = size_mem_words; + err = 0; + } + + return err; +} +#endif + +void +mipi_init(void) +{ + unsigned int i; + + for (i = 0; i < N_CSI_PORTS; i++) + ref_count_mipi_allocation[i] = 0; +} + +bool mipi_is_free(void) +{ + unsigned int i; + + for (i = 0; i < N_CSI_PORTS; i++) + if (ref_count_mipi_allocation[i]) + return false; + + return true; +} + +#if defined(ISP2401) +/* + * @brief Calculate the required MIPI buffer sizes. + * Based on the stream configuration, calculate the + * required MIPI buffer sizes (in DDR words). + * + * @param[in] stream_cfg Point to the target stream configuration + * @param[out] size_mem_words MIPI buffer size in DDR words. + * + * @return + */ +static int calculate_mipi_buff_size(struct ia_css_stream_config *stream_cfg, + unsigned int *size_mem_words) +{ + unsigned int width; + unsigned int height; + enum atomisp_input_format format; + bool pack_raw_pixels; + + unsigned int width_padded; + unsigned int bits_per_pixel = 0; + + unsigned int even_line_bytes = 0; + unsigned int odd_line_bytes = 0; + + unsigned int words_per_odd_line = 0; + unsigned int words_per_even_line = 0; + + unsigned int mem_words_per_even_line = 0; + unsigned int mem_words_per_odd_line = 0; + + unsigned int mem_words_per_buff_line = 0; + unsigned int mem_words_per_buff = 0; + int err = 0; + + /** + * zhengjie.lu@intel.com + * + * NOTE + * - In the struct "ia_css_stream_config", there + * are two members: "input_config" and "isys_config". + * Both of them provide the same information, e.g. + * input_res and format. + * + * Question here is that: which one shall be used? + */ + width = stream_cfg->input_config.input_res.width; + height = stream_cfg->input_config.input_res.height; + format = stream_cfg->input_config.format; + pack_raw_pixels = stream_cfg->pack_raw_pixels; + /* end of NOTE */ + + /** + * zhengjie.lu@intel.com + * + * NOTE + * - The following code is derived from the + * existing code "ia_css_mipi_frame_calculate_size()". + * + * Question here is: why adding "2 * ISP_VEC_NELEMS" + * to "width_padded", but not making "width_padded" + * aligned with "2 * ISP_VEC_NELEMS"? + */ + /* The changes will be reverted as soon as RAW + * Buffers are deployed by the 2401 Input System + * in the non-continuous use scenario. + */ + width_padded = width + (2 * ISP_VEC_NELEMS); + /* end of NOTE */ + + IA_CSS_ENTER("padded_width=%d, height=%d, format=%d\n", + width_padded, height, format); + + bits_per_pixel = sh_css_stream_format_2_bits_per_subpixel(format); + bits_per_pixel = + (format == ATOMISP_INPUT_FORMAT_RAW_10 && pack_raw_pixels) ? bits_per_pixel : 16; + if (bits_per_pixel == 0) + return -EINVAL; + + odd_line_bytes = (width_padded * bits_per_pixel + 7) >> 3; /* ceil ( bits per line / 8) */ + + /* Even lines for YUV420 formats are double in bits_per_pixel. */ + if (format == ATOMISP_INPUT_FORMAT_YUV420_8 + || format == ATOMISP_INPUT_FORMAT_YUV420_10) { + even_line_bytes = (width_padded * 2 * bits_per_pixel + 7) >> + 3; /* ceil ( bits per line / 8) */ + } else { + even_line_bytes = odd_line_bytes; + } + + words_per_odd_line = (odd_line_bytes + 3) >> 2; + /* ceil(odd_line_bytes/4); word = 4 bytes */ + words_per_even_line = (even_line_bytes + 3) >> 2; + + mem_words_per_odd_line = (words_per_odd_line + 7) >> 3; + /* ceil(words_per_odd_line/8); mem_word = 32 bytes, 8 words */ + mem_words_per_even_line = (words_per_even_line + 7) >> 3; + + mem_words_per_buff_line = + (mem_words_per_odd_line > mem_words_per_even_line) ? mem_words_per_odd_line : mem_words_per_even_line; + mem_words_per_buff = mem_words_per_buff_line * height; + + *size_mem_words = mem_words_per_buff; + + IA_CSS_LEAVE_ERR(err); + return err; +} +#endif + +int +allocate_mipi_frames(struct ia_css_pipe *pipe, + struct ia_css_stream_info *info) +{ + int err = -EINVAL; + unsigned int port; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) enter:\n", pipe); + + assert(pipe); + assert(pipe->stream); + if ((!pipe) || (!pipe->stream)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: pipe or stream is null.\n", + pipe); + return -EINVAL; + } + +#ifdef ISP2401 + if (pipe->stream->config.online) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: no buffers needed for 2401 pipe mode.\n", + pipe); + return 0; + } + +#endif + if (pipe->stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: no buffers needed for pipe mode.\n", + pipe); + return 0; /* AM TODO: Check */ + } + + port = (unsigned int)pipe->stream->config.source.port.port; + if (port >= N_CSI_PORTS) { + IA_CSS_ERROR("allocate_mipi_frames(%p) exit: port is not correct (port=%d).", + pipe, port); + return -EINVAL; + } + +#ifdef ISP2401 + err = calculate_mipi_buff_size(&pipe->stream->config, + &my_css.mipi_frame_size[port]); + /* + * 2401 system allows multiple streams to use same physical port. This is not + * true for 2400 system. Currently 2401 uses MIPI buffers as a temporary solution. + * TODO AM: Once that is changed (removed) this code should be removed as well. + * In that case only 2400 related code should remain. + */ + if (ref_count_mipi_allocation[port] != 0) { + ref_count_mipi_allocation[port]++; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) leave: nothing to do, already allocated for this port (port=%d).\n", + pipe, port); + return 0; + } +#else + if (ref_count_mipi_allocation[port] != 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: already allocated for this port (port=%d).\n", + pipe, port); + return 0; + } +#endif + + ref_count_mipi_allocation[port]++; + + /* AM TODO: mipi frames number should come from stream struct. */ + my_css.num_mipi_frames[port] = NUM_MIPI_FRAMES_PER_STREAM; + + /* Incremental allocation (per stream), not for all streams at once. */ + { /* limit the scope of i,j */ + unsigned int i, j; + + for (i = 0; i < my_css.num_mipi_frames[port]; i++) { + /* free previous frame */ + if (my_css.mipi_frames[port][i]) { + ia_css_frame_free(my_css.mipi_frames[port][i]); + my_css.mipi_frames[port][i] = NULL; + } + /* check if new frame is needed */ + if (i < my_css.num_mipi_frames[port]) { + /* allocate new frame */ + err = ia_css_frame_allocate_with_buffer_size( + &my_css.mipi_frames[port][i], + my_css.mipi_frame_size[port] * HIVE_ISP_DDR_WORD_BYTES); + if (err) { + for (j = 0; j < i; j++) { + if (my_css.mipi_frames[port][j]) { + ia_css_frame_free(my_css.mipi_frames[port][j]); + my_css.mipi_frames[port][j] = NULL; + } + } + IA_CSS_ERROR("allocate_mipi_frames(%p, %d) exit: allocation failed.", + pipe, port); + return err; + } + } + if (info->metadata_info.size > 0) { + /* free previous metadata buffer */ + if (my_css.mipi_metadata[port][i]) { + ia_css_metadata_free(my_css.mipi_metadata[port][i]); + my_css.mipi_metadata[port][i] = NULL; + } + /* check if need to allocate a new metadata buffer */ + if (i < my_css.num_mipi_frames[port]) { + /* allocate new metadata buffer */ + my_css.mipi_metadata[port][i] = ia_css_metadata_allocate(&info->metadata_info); + if (!my_css.mipi_metadata[port][i]) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_metadata(%p, %d) failed.\n", + pipe, port); + return err; + } + } + } + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit:\n", pipe); + + return err; +} + +int +free_mipi_frames(struct ia_css_pipe *pipe) +{ + int err = -EINVAL; + unsigned int port; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) enter:\n", pipe); + + /* assert(pipe != NULL); TEMP: TODO: Should be assert only. */ + if (pipe) { + assert(pipe->stream); + if ((!pipe) || (!pipe->stream)) { + IA_CSS_ERROR("free_mipi_frames(%p) exit: pipe or stream is null.", + pipe); + return -EINVAL; + } + + if (pipe->stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + IA_CSS_ERROR("free_mipi_frames(%p) exit: wrong mode.", + pipe); + return err; + } + + port = (unsigned int)pipe->stream->config.source.port.port; + + if (port >= N_CSI_PORTS) { + IA_CSS_ERROR("free_mipi_frames(%p, %d) exit: pipe port is not correct.", + pipe, port); + return err; + } + + if (ref_count_mipi_allocation[port] > 0) { +#if !defined(ISP2401) + assert(ref_count_mipi_allocation[port] == 1); + if (ref_count_mipi_allocation[port] != 1) { + IA_CSS_ERROR("free_mipi_frames(%p) exit: wrong ref_count (ref_count=%d).", + pipe, ref_count_mipi_allocation[port]); + return err; + } +#endif + + ref_count_mipi_allocation[port]--; + + if (ref_count_mipi_allocation[port] == 0) { + /* no streams are using this buffer, so free it */ + unsigned int i; + + for (i = 0; i < my_css.num_mipi_frames[port]; i++) { + if (my_css.mipi_frames[port][i]) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(port=%d, num=%d).\n", port, i); + ia_css_frame_free(my_css.mipi_frames[port][i]); + my_css.mipi_frames[port][i] = NULL; + } + if (my_css.mipi_metadata[port][i]) { + ia_css_metadata_free(my_css.mipi_metadata[port][i]); + my_css.mipi_metadata[port][i] = NULL; + } + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) exit (deallocated).\n", pipe); + } +#if defined(ISP2401) + else { + /* 2401 system allows multiple streams to use same physical port. This is not + * true for 2400 system. Currently 2401 uses MIPI buffers as a temporary solution. + * TODO AM: Once that is changed (removed) this code should be removed as well. + * In that case only 2400 related code should remain. + */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) leave: nothing to do, other streams still use this port (port=%d).\n", + pipe, port); + } +#endif + } + } else { /* pipe ==NULL */ + /* AM TEMP: free-ing all mipi buffers just like a legacy code. */ + for (port = CSI_PORT0_ID; port < N_CSI_PORTS; port++) { + unsigned int i; + + for (i = 0; i < my_css.num_mipi_frames[port]; i++) { + if (my_css.mipi_frames[port][i]) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(port=%d, num=%d).\n", port, i); + ia_css_frame_free(my_css.mipi_frames[port][i]); + my_css.mipi_frames[port][i] = NULL; + } + if (my_css.mipi_metadata[port][i]) { + ia_css_metadata_free(my_css.mipi_metadata[port][i]); + my_css.mipi_metadata[port][i] = NULL; + } + } + ref_count_mipi_allocation[port] = 0; + } + } + return 0; +} + +int +send_mipi_frames(struct ia_css_pipe *pipe) +{ + int err = -EINVAL; + unsigned int i; + unsigned int port; + + IA_CSS_ENTER_PRIVATE("pipe=%p", pipe); + + assert(pipe); + assert(pipe->stream); + if (!pipe || !pipe->stream) { + IA_CSS_ERROR("pipe or stream is null"); + return -EINVAL; + } + + /* multi stream video needs mipi buffers */ + /* nothing to be done in other cases. */ + if (pipe->stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + IA_CSS_LOG("nothing to be done for this mode"); + return 0; + /* TODO: AM: maybe this should be returning an error. */ + } + + port = (unsigned int)pipe->stream->config.source.port.port; + + if (port >= N_CSI_PORTS) { + IA_CSS_ERROR("send_mipi_frames(%p) exit: invalid port specified (port=%d).", + pipe, port); + return err; + } + + /* Hand-over the SP-internal mipi buffers */ + for (i = 0; i < my_css.num_mipi_frames[port]; i++) { + /* Need to include the ofset for port. */ + sh_css_update_host2sp_mipi_frame(port * NUM_MIPI_FRAMES_PER_STREAM + i, + my_css.mipi_frames[port][i]); + sh_css_update_host2sp_mipi_metadata(port * NUM_MIPI_FRAMES_PER_STREAM + i, + my_css.mipi_metadata[port][i]); + } + sh_css_update_host2sp_num_mipi_frames(my_css.num_mipi_frames[port]); + + /********************************** + * Send an event to inform the SP + * that all MIPI frames are passed. + **********************************/ + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + IA_CSS_ERROR("sp is not running"); + return err; + } + + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY, + (uint8_t)port, + (uint8_t)my_css.num_mipi_frames[port], + 0 /* not used */); + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_mipi.h b/drivers/staging/media/atomisp/pci/sh_css_mipi.h new file mode 100644 index 000000000..e6c86d0ac --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_mipi.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_MIPI_H +#define __SH_CSS_MIPI_H + +#include /* ia_css_err */ +#include /* ia_css_pipe */ +#include /* ia_css_stream_config */ + +void +mipi_init(void); + +bool mipi_is_free(void); + +int +allocate_mipi_frames(struct ia_css_pipe *pipe, struct ia_css_stream_info *info); + +int +free_mipi_frames(struct ia_css_pipe *pipe); + +int +send_mipi_frames(struct ia_css_pipe *pipe); + +#endif /* __SH_CSS_MIPI_H */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_mmu.c b/drivers/staging/media/atomisp/pci/sh_css_mmu.c new file mode 100644 index 000000000..1da7459ea --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_mmu.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_mmu.h" +#include "ia_css_mmu_private.h" +#include +#include "sh_css_sp.h" +#include "sh_css_firmware.h" +#include "sp.h" +#include "mmu_device.h" + +void +ia_css_mmu_invalidate_cache(void) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_mmu_invalidate_cache() enter\n"); + + /* if the SP is not running we should not access its dmem */ + if (sh_css_sp_is_running()) { + HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb = fw->info.sp.invalidate_tlb; + + (void)HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb; /* Suppres warnings in CRUN */ + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(ia_css_dmaproxy_sp_invalidate_tlb), + true); + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_mmu_invalidate_cache() leave\n"); +} + +void +sh_css_mmu_set_page_table_base_index(hrt_data base_index) +{ + int i; + + IA_CSS_ENTER_PRIVATE("base_index=0x%08x\n", base_index); + for (i = 0; i < N_MMU_ID; i++) { + mmu_ID_t mmu_id = i; + + mmu_set_page_table_base_index(mmu_id, base_index); + mmu_invalidate_cache(mmu_id); + } + IA_CSS_LEAVE_PRIVATE(""); +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_param_dvs.c b/drivers/staging/media/atomisp/pci/sh_css_param_dvs.c new file mode 100644 index 000000000..ff0082d02 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_param_dvs.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "sh_css_param_dvs.h" +#include +#include +#include +#include +#include "ia_css_debug.h" + +static struct ia_css_dvs_6axis_config * +alloc_dvs_6axis_table(const struct ia_css_resolution *frame_res, + struct ia_css_dvs_6axis_config *dvs_config_src) +{ + unsigned int width_y = 0; + unsigned int height_y = 0; + unsigned int width_uv = 0; + unsigned int height_uv = 0; + int err = 0; + struct ia_css_dvs_6axis_config *dvs_config = NULL; + + dvs_config = kvmalloc(sizeof(struct ia_css_dvs_6axis_config), + GFP_KERNEL); + if (!dvs_config) { + IA_CSS_ERROR("out of memory"); + err = -ENOMEM; + } else { + /*Initialize new struct with latest config settings*/ + if (dvs_config_src) { + dvs_config->width_y = width_y = dvs_config_src->width_y; + dvs_config->height_y = height_y = dvs_config_src->height_y; + dvs_config->width_uv = width_uv = dvs_config_src->width_uv; + dvs_config->height_uv = height_uv = dvs_config_src->height_uv; + IA_CSS_LOG("alloc_dvs_6axis_table Y: W %d H %d", width_y, height_y); + } else if (frame_res) { + dvs_config->width_y = width_y = DVS_TABLE_IN_BLOCKDIM_X_LUMA(frame_res->width); + dvs_config->height_y = height_y = DVS_TABLE_IN_BLOCKDIM_Y_LUMA( + frame_res->height); + dvs_config->width_uv = width_uv = DVS_TABLE_IN_BLOCKDIM_X_CHROMA( + frame_res->width / + 2); /* UV = Y/2, depens on colour format YUV 4.2.0*/ + dvs_config->height_uv = height_uv = DVS_TABLE_IN_BLOCKDIM_Y_CHROMA( + frame_res->height / + 2);/* UV = Y/2, depens on colour format YUV 4.2.0*/ + IA_CSS_LOG("alloc_dvs_6axis_table Y: W %d H %d", width_y, height_y); + } + + /* Generate Y buffers */ + dvs_config->xcoords_y = kvmalloc(width_y * height_y * sizeof(uint32_t), + GFP_KERNEL); + if (!dvs_config->xcoords_y) { + IA_CSS_ERROR("out of memory"); + err = -ENOMEM; + goto exit; + } + + dvs_config->ycoords_y = kvmalloc(width_y * height_y * sizeof(uint32_t), + GFP_KERNEL); + if (!dvs_config->ycoords_y) { + IA_CSS_ERROR("out of memory"); + err = -ENOMEM; + goto exit; + } + + /* Generate UV buffers */ + IA_CSS_LOG("UV W %d H %d", width_uv, height_uv); + + dvs_config->xcoords_uv = kvmalloc(width_uv * height_uv * sizeof(uint32_t), + GFP_KERNEL); + if (!dvs_config->xcoords_uv) { + IA_CSS_ERROR("out of memory"); + err = -ENOMEM; + goto exit; + } + + dvs_config->ycoords_uv = kvmalloc(width_uv * height_uv * sizeof(uint32_t), + GFP_KERNEL); + if (!dvs_config->ycoords_uv) { + IA_CSS_ERROR("out of memory"); + err = -ENOMEM; + } +exit: + if (err) { + free_dvs_6axis_table( + &dvs_config); /* we might have allocated some memory, release this */ + dvs_config = NULL; + } + } + + IA_CSS_LEAVE("dvs_config=%p", dvs_config); + return dvs_config; +} + +static void +init_dvs_6axis_table_from_default(struct ia_css_dvs_6axis_config *dvs_config, + const struct ia_css_resolution *dvs_offset) +{ + unsigned int x, y; + unsigned int width_y = dvs_config->width_y; + unsigned int height_y = dvs_config->height_y; + unsigned int width_uv = dvs_config->width_uv; + unsigned int height_uv = dvs_config->height_uv; + + IA_CSS_LOG("Env_X=%d, Env_Y=%d, width_y=%d, height_y=%d", + dvs_offset->width, dvs_offset->height, width_y, height_y); + for (y = 0; y < height_y; y++) { + for (x = 0; x < width_y; x++) { + dvs_config->xcoords_y[y * width_y + x] = (dvs_offset->width + x * + DVS_BLOCKDIM_X) << DVS_COORD_FRAC_BITS; + } + } + + for (y = 0; y < height_y; y++) { + for (x = 0; x < width_y; x++) { + dvs_config->ycoords_y[y * width_y + x] = (dvs_offset->height + y * + DVS_BLOCKDIM_Y_LUMA) << DVS_COORD_FRAC_BITS; + } + } + + for (y = 0; y < height_uv; y++) { + for (x = 0; x < width_uv; + x++) { /* Envelope dimensions set in Ypixels hence offset UV = offset Y/2 */ + dvs_config->xcoords_uv[y * width_uv + x] = ((dvs_offset->width / 2) + x * + DVS_BLOCKDIM_X) << DVS_COORD_FRAC_BITS; + } + } + + for (y = 0; y < height_uv; y++) { + for (x = 0; x < width_uv; + x++) { /* Envelope dimensions set in Ypixels hence offset UV = offset Y/2 */ + dvs_config->ycoords_uv[y * width_uv + x] = ((dvs_offset->height / 2) + y * + DVS_BLOCKDIM_Y_CHROMA) << + DVS_COORD_FRAC_BITS; + } + } +} + +static void +init_dvs_6axis_table_from_config(struct ia_css_dvs_6axis_config *dvs_config, + struct ia_css_dvs_6axis_config *dvs_config_src) +{ + unsigned int width_y = dvs_config->width_y; + unsigned int height_y = dvs_config->height_y; + unsigned int width_uv = dvs_config->width_uv; + unsigned int height_uv = dvs_config->height_uv; + + memcpy(dvs_config->xcoords_y, dvs_config_src->xcoords_y, + (width_y * height_y * sizeof(uint32_t))); + memcpy(dvs_config->ycoords_y, dvs_config_src->ycoords_y, + (width_y * height_y * sizeof(uint32_t))); + memcpy(dvs_config->xcoords_uv, dvs_config_src->xcoords_uv, + (width_uv * height_uv * sizeof(uint32_t))); + memcpy(dvs_config->ycoords_uv, dvs_config_src->ycoords_uv, + (width_uv * height_uv * sizeof(uint32_t))); +} + +struct ia_css_dvs_6axis_config * +generate_dvs_6axis_table(const struct ia_css_resolution *frame_res, + const struct ia_css_resolution *dvs_offset) +{ + struct ia_css_dvs_6axis_config *dvs_6axis_table; + + assert(frame_res); + assert(dvs_offset); + + dvs_6axis_table = alloc_dvs_6axis_table(frame_res, NULL); + if (dvs_6axis_table) { + init_dvs_6axis_table_from_default(dvs_6axis_table, dvs_offset); + return dvs_6axis_table; + } + return NULL; +} + +struct ia_css_dvs_6axis_config * +generate_dvs_6axis_table_from_config(struct ia_css_dvs_6axis_config + *dvs_config_src) +{ + struct ia_css_dvs_6axis_config *dvs_6axis_table; + + assert(dvs_config_src); + + dvs_6axis_table = alloc_dvs_6axis_table(NULL, dvs_config_src); + if (dvs_6axis_table) { + init_dvs_6axis_table_from_config(dvs_6axis_table, dvs_config_src); + return dvs_6axis_table; + } + return NULL; +} + +void +free_dvs_6axis_table(struct ia_css_dvs_6axis_config **dvs_6axis_config) +{ + assert(dvs_6axis_config); + assert(*dvs_6axis_config); + + if ((dvs_6axis_config) && (*dvs_6axis_config)) { + IA_CSS_ENTER_PRIVATE("dvs_6axis_config %p", (*dvs_6axis_config)); + if ((*dvs_6axis_config)->xcoords_y) { + kvfree((*dvs_6axis_config)->xcoords_y); + (*dvs_6axis_config)->xcoords_y = NULL; + } + + if ((*dvs_6axis_config)->ycoords_y) { + kvfree((*dvs_6axis_config)->ycoords_y); + (*dvs_6axis_config)->ycoords_y = NULL; + } + + /* Free up UV buffers */ + if ((*dvs_6axis_config)->xcoords_uv) { + kvfree((*dvs_6axis_config)->xcoords_uv); + (*dvs_6axis_config)->xcoords_uv = NULL; + } + + if ((*dvs_6axis_config)->ycoords_uv) { + kvfree((*dvs_6axis_config)->ycoords_uv); + (*dvs_6axis_config)->ycoords_uv = NULL; + } + + IA_CSS_LEAVE_PRIVATE("dvs_6axis_config %p", (*dvs_6axis_config)); + kvfree(*dvs_6axis_config); + *dvs_6axis_config = NULL; + } +} + +void copy_dvs_6axis_table(struct ia_css_dvs_6axis_config *dvs_config_dst, + const struct ia_css_dvs_6axis_config *dvs_config_src) +{ + unsigned int width_y; + unsigned int height_y; + unsigned int width_uv; + unsigned int height_uv; + + assert(dvs_config_src); + assert(dvs_config_dst); + assert(dvs_config_src->xcoords_y); + assert(dvs_config_src->xcoords_uv); + assert(dvs_config_src->ycoords_y); + assert(dvs_config_src->ycoords_uv); + assert(dvs_config_src->width_y == dvs_config_dst->width_y); + assert(dvs_config_src->width_uv == dvs_config_dst->width_uv); + assert(dvs_config_src->height_y == dvs_config_dst->height_y); + assert(dvs_config_src->height_uv == dvs_config_dst->height_uv); + + width_y = dvs_config_src->width_y; + height_y = dvs_config_src->height_y; + width_uv = + dvs_config_src->width_uv; /* = Y/2, depens on colour format YUV 4.2.0*/ + height_uv = dvs_config_src->height_uv; + + memcpy(dvs_config_dst->xcoords_y, dvs_config_src->xcoords_y, + (width_y * height_y * sizeof(uint32_t))); + memcpy(dvs_config_dst->ycoords_y, dvs_config_src->ycoords_y, + (width_y * height_y * sizeof(uint32_t))); + + memcpy(dvs_config_dst->xcoords_uv, dvs_config_src->xcoords_uv, + (width_uv * height_uv * sizeof(uint32_t))); + memcpy(dvs_config_dst->ycoords_uv, dvs_config_src->ycoords_uv, + (width_uv * height_uv * sizeof(uint32_t))); +} + +void +ia_css_dvs_statistics_get(enum dvs_statistics_type type, + union ia_css_dvs_statistics_host *host_stats, + const union ia_css_dvs_statistics_isp *isp_stats) +{ + if (type == DVS_STATISTICS) { + ia_css_get_dvs_statistics(host_stats->p_dvs_statistics_host, + isp_stats->p_dvs_statistics_isp); + } else if (type == DVS2_STATISTICS) { + ia_css_get_dvs2_statistics(host_stats->p_dvs2_statistics_host, + isp_stats->p_dvs_statistics_isp); + } + return; +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_param_dvs.h b/drivers/staging/media/atomisp/pci/sh_css_param_dvs.h new file mode 100644 index 000000000..7782f76b9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_param_dvs.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_PARAMS_DVS_H_ +#define _SH_CSS_PARAMS_DVS_H_ + +#include +#include +#include +#include "gdc_global.h" /* gdc_warp_param_mem_t */ + +#define DVS_ENV_MIN_X (12) +#define DVS_ENV_MIN_Y (12) + +#define DVS_BLOCKDIM_X (64) /* X block height*/ +#define DVS_BLOCKDIM_Y_LUMA (64) /* Y block height*/ +#define DVS_BLOCKDIM_Y_CHROMA (32) /* UV height block size is half the Y block height*/ + +/* ISP2400 */ +/* horizontal 64x64 blocks round up to DVS_BLOCKDIM_X, make even */ +#define DVS_NUM_BLOCKS_X(X) (CEIL_MUL(CEIL_DIV((X), DVS_BLOCKDIM_X), 2)) + +/* ISP2400 */ +/* vertical 64x64 blocks round up to DVS_BLOCKDIM_Y */ +#define DVS_NUM_BLOCKS_Y(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_LUMA)) +#define DVS_NUM_BLOCKS_X_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_X)) +#define DVS_NUM_BLOCKS_Y_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_CHROMA)) + +#define DVS_TABLE_IN_BLOCKDIM_X_LUMA(X) (DVS_NUM_BLOCKS_X(X) + 1) /* N blocks have N + 1 set of coords */ +#define DVS_TABLE_IN_BLOCKDIM_X_CHROMA(X) (DVS_NUM_BLOCKS_X_CHROMA(X) + 1) +#define DVS_TABLE_IN_BLOCKDIM_Y_LUMA(X) (DVS_NUM_BLOCKS_Y(X) + 1) +#define DVS_TABLE_IN_BLOCKDIM_Y_CHROMA(X) (DVS_NUM_BLOCKS_Y_CHROMA(X) + 1) + +#define DVS_ENVELOPE_X(X) (((X) == 0) ? (DVS_ENV_MIN_X) : (X)) +#define DVS_ENVELOPE_Y(X) (((X) == 0) ? (DVS_ENV_MIN_Y) : (X)) + +#define DVS_COORD_FRAC_BITS (10) + +/* ISP2400 */ +#define DVS_INPUT_BYTES_PER_PIXEL (1) + +#define XMEM_ALIGN_LOG2 (5) + +#define DVS_6AXIS_COORDS_ELEMS CEIL_MUL(sizeof(gdc_warp_param_mem_t) \ + , HIVE_ISP_DDR_WORD_BYTES) + +/* currently we only support two output with the same resolution, output 0 is th default one. */ +#define DVS_6AXIS_BYTES(binary) \ + (DVS_6AXIS_COORDS_ELEMS \ + * DVS_NUM_BLOCKS_X((binary)->out_frame_info[0].res.width) \ + * DVS_NUM_BLOCKS_Y((binary)->out_frame_info[0].res.height)) + +/* + * ISP2400: + * Bilinear interpolation (HRT_GDC_BLI_MODE) is the supported method currently. + * Bicubic interpolation (HRT_GDC_BCI_MODE) is not supported yet */ +#define DVS_GDC_INTERP_METHOD HRT_GDC_BLI_MODE + +struct ia_css_dvs_6axis_config * +generate_dvs_6axis_table(const struct ia_css_resolution *frame_res, + const struct ia_css_resolution *dvs_offset); + +struct ia_css_dvs_6axis_config * +generate_dvs_6axis_table_from_config(struct ia_css_dvs_6axis_config + *dvs_config_src); + +void +free_dvs_6axis_table(struct ia_css_dvs_6axis_config **dvs_6axis_config); + +void +copy_dvs_6axis_table(struct ia_css_dvs_6axis_config *dvs_config_dst, + const struct ia_css_dvs_6axis_config *dvs_config_src); + +#endif diff --git a/drivers/staging/media/atomisp/pci/sh_css_param_shading.c b/drivers/staging/media/atomisp/pci/sh_css_param_shading.c new file mode 100644 index 000000000..5b43cc656 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_param_shading.c @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include +#include "sh_css_param_shading.h" +#include "ia_css_shading.h" +#include "assert_support.h" +#include "sh_css_defs.h" +#include "sh_css_internal.h" +#include "ia_css_debug.h" +#include "ia_css_pipe_binarydesc.h" + +#include "sh_css_hrt.h" + +#include "platform_support.h" + +/* Bilinear interpolation on shading tables: + * For each target point T, we calculate the 4 surrounding source points: + * ul (upper left), ur (upper right), ll (lower left) and lr (lower right). + * We then calculate the distances from the T to the source points: x0, x1, + * y0 and y1. + * We then calculate the value of T: + * dx0*dy0*Slr + dx0*dy1*Sur + dx1*dy0*Sll + dx1*dy1*Sul. + * We choose a grid size of 1x1 which means: + * dx1 = 1-dx0 + * dy1 = 1-dy0 + * + * Sul dx0 dx1 Sur + * .<----->|<------------->. + * ^ + * dy0| + * v T + * - . + * ^ + * | + * dy1| + * v + * . . + * Sll Slr + * + * Padding: + * The area that the ISP operates on can include padding both on the left + * and the right. We need to padd the shading table such that the shading + * values end up on the correct pixel values. This means we must padd the + * shading table to match the ISP padding. + * We can have 5 cases: + * 1. All 4 points fall in the left padding. + * 2. The left 2 points fall in the left padding. + * 3. All 4 points fall in the cropped (target) region. + * 4. The right 2 points fall in the right padding. + * 5. All 4 points fall in the right padding. + * Cases 1 and 5 are easy to handle: we simply use the + * value 1 in the shading table. + * Cases 2 and 4 require interpolation that takes into + * account how far into the padding area the pixels + * fall. We extrapolate the shading table into the + * padded area and then interpolate. + */ +static void +crop_and_interpolate(unsigned int cropped_width, + unsigned int cropped_height, + unsigned int left_padding, + int right_padding, + int top_padding, + const struct ia_css_shading_table *in_table, + struct ia_css_shading_table *out_table, + enum ia_css_sc_color color) +{ + unsigned int i, j, + sensor_width, + sensor_height, + table_width, + table_height, + table_cell_h, + out_cell_size, + in_cell_size, + out_start_row, + padded_width; + int out_start_col, /* can be negative to indicate padded space */ + table_cell_w; + unsigned short *in_ptr, + *out_ptr; + + assert(in_table); + assert(out_table); + + sensor_width = in_table->sensor_width; + sensor_height = in_table->sensor_height; + table_width = in_table->width; + table_height = in_table->height; + in_ptr = in_table->data[color]; + out_ptr = out_table->data[color]; + + padded_width = cropped_width + left_padding + right_padding; + out_cell_size = CEIL_DIV(padded_width, out_table->width - 1); + in_cell_size = CEIL_DIV(sensor_width, table_width - 1); + + out_start_col = ((int)sensor_width - (int)cropped_width) / 2 - left_padding; + out_start_row = ((int)sensor_height - (int)cropped_height) / 2 - top_padding; + table_cell_w = (int)((table_width - 1) * in_cell_size); + table_cell_h = (table_height - 1) * in_cell_size; + + for (i = 0; i < out_table->height; i++) { + int ty, src_y0, src_y1; + unsigned int sy0, sy1, dy0, dy1, divy; + + /* + * calculate target point and make sure it falls within + * the table + */ + ty = out_start_row + i * out_cell_size; + + /* calculate closest source points in shading table and + make sure they fall within the table */ + src_y0 = ty / (int)in_cell_size; + if (in_cell_size < out_cell_size) + src_y1 = (ty + out_cell_size) / in_cell_size; + else + src_y1 = src_y0 + 1; + src_y0 = clamp(src_y0, 0, (int)table_height - 1); + src_y1 = clamp(src_y1, 0, (int)table_height - 1); + ty = min(clamp(ty, 0, (int)sensor_height - 1), + (int)table_cell_h); + + /* calculate closest source points for distance computation */ + sy0 = min(src_y0 * in_cell_size, sensor_height - 1); + sy1 = min(src_y1 * in_cell_size, sensor_height - 1); + /* calculate distance between source and target pixels */ + dy0 = ty - sy0; + dy1 = sy1 - ty; + divy = sy1 - sy0; + if (divy == 0) { + dy0 = 1; + divy = 1; + } + + for (j = 0; j < out_table->width; j++, out_ptr++) { + int tx, src_x0, src_x1; + unsigned int sx0, sx1, dx0, dx1, divx; + unsigned short s_ul, s_ur, s_ll, s_lr; + + /* calculate target point */ + tx = out_start_col + j * out_cell_size; + /* calculate closest source points. */ + src_x0 = tx / (int)in_cell_size; + if (in_cell_size < out_cell_size) { + src_x1 = (tx + out_cell_size) / + (int)in_cell_size; + } else { + src_x1 = src_x0 + 1; + } + /* if src points fall in padding, select closest ones.*/ + src_x0 = clamp(src_x0, 0, (int)table_width - 1); + src_x1 = clamp(src_x1, 0, (int)table_width - 1); + tx = min(clamp(tx, 0, (int)sensor_width - 1), + (int)table_cell_w); + /* + * calculate closest source points for distance + * computation + */ + sx0 = min(src_x0 * in_cell_size, sensor_width - 1); + sx1 = min(src_x1 * in_cell_size, sensor_width - 1); + /* + * calculate distances between source and target + * pixels + */ + dx0 = tx - sx0; + dx1 = sx1 - tx; + divx = sx1 - sx0; + /* if we're at the edge, we just use the closest + * point still in the grid. We make up for the divider + * in this case by setting the distance to + * out_cell_size, since it's actually 0. + */ + if (divx == 0) { + dx0 = 1; + divx = 1; + } + + /* get source pixel values */ + s_ul = in_ptr[(table_width * src_y0) + src_x0]; + s_ur = in_ptr[(table_width * src_y0) + src_x1]; + s_ll = in_ptr[(table_width * src_y1) + src_x0]; + s_lr = in_ptr[(table_width * src_y1) + src_x1]; + + *out_ptr = (unsigned short)((dx0 * dy0 * s_lr + dx0 * dy1 * s_ur + dx1 * dy0 * + s_ll + dx1 * dy1 * s_ul) / + (divx * divy)); + } + } +} + +void +sh_css_params_shading_id_table_generate( + struct ia_css_shading_table **target_table, + unsigned int table_width, + unsigned int table_height) +{ + /* initialize table with ones, shift becomes zero */ + unsigned int i, j; + struct ia_css_shading_table *result; + + assert(target_table); + + result = ia_css_shading_table_alloc(table_width, table_height); + if (!result) { + *target_table = NULL; + return; + } + + for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) { + for (j = 0; j < table_height * table_width; j++) + result->data[i][j] = 1; + } + result->fraction_bits = 0; + *target_table = result; +} + +void +prepare_shading_table(const struct ia_css_shading_table *in_table, + unsigned int sensor_binning, + struct ia_css_shading_table **target_table, + const struct ia_css_binary *binary, + unsigned int bds_factor) +{ + unsigned int input_width, input_height, table_width, table_height, i; + unsigned int left_padding, top_padding, left_cropping; + struct ia_css_shading_table *result; + struct u32_fract bds; + int right_padding; + + assert(target_table); + assert(binary); + + if (!in_table) { + sh_css_params_shading_id_table_generate(target_table, + binary->sctbl_width_per_color, + binary->sctbl_height); + return; + } + + /* + * We use the ISP input resolution for the shading table because + * shading correction is performed in the bayer domain (before bayer + * down scaling). + */ + input_height = binary->in_frame_info.res.height; + input_width = binary->in_frame_info.res.width; + left_padding = binary->left_padding; + left_cropping = (binary->info->sp.pipeline.left_cropping == 0) ? + binary->dvs_envelope.width : 2 * ISP_VEC_NELEMS; + + sh_css_bds_factor_get_fract(bds_factor, &bds); + + left_padding = (left_padding + binary->info->sp.pipeline.left_cropping) * + bds.numerator / bds.denominator - + binary->info->sp.pipeline.left_cropping; + right_padding = (binary->internal_frame_info.res.width - + binary->effective_in_frame_res.width * bds.denominator / + bds.numerator - left_cropping) * bds.numerator / bds.denominator; + top_padding = binary->info->sp.pipeline.top_cropping * bds.numerator / + bds.denominator - + binary->info->sp.pipeline.top_cropping; + + /* + * We take into account the binning done by the sensor. We do this + * by cropping the non-binned part of the shading table and then + * increasing the size of a grid cell with this same binning factor. + */ + input_width <<= sensor_binning; + input_height <<= sensor_binning; + /* + * We also scale the padding by the same binning factor. This will + * make it much easier later on to calculate the padding of the + * shading table. + */ + left_padding <<= sensor_binning; + right_padding <<= sensor_binning; + top_padding <<= sensor_binning; + + /* + * during simulation, the used resolution can exceed the sensor + * resolution, so we clip it. + */ + input_width = min(input_width, in_table->sensor_width); + input_height = min(input_height, in_table->sensor_height); + + /* This prepare_shading_table() function is called only in legacy API (not in new API). + Then, the legacy shading table width and height should be used. */ + table_width = binary->sctbl_width_per_color; + table_height = binary->sctbl_height; + + result = ia_css_shading_table_alloc(table_width, table_height); + if (!result) { + *target_table = NULL; + return; + } + result->sensor_width = in_table->sensor_width; + result->sensor_height = in_table->sensor_height; + result->fraction_bits = in_table->fraction_bits; + + /* + * now we crop the original shading table and then interpolate to the + * requested resolution and decimation factor. + */ + for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) { + crop_and_interpolate(input_width, input_height, + left_padding, right_padding, top_padding, + in_table, + result, i); + } + *target_table = result; +} + +struct ia_css_shading_table * +ia_css_shading_table_alloc( + unsigned int width, + unsigned int height) +{ + unsigned int i; + struct ia_css_shading_table *me; + + IA_CSS_ENTER(""); + + me = kmalloc(sizeof(*me), GFP_KERNEL); + if (!me) + return me; + + me->width = width; + me->height = height; + me->sensor_width = 0; + me->sensor_height = 0; + me->fraction_bits = 0; + for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) { + me->data[i] = + kvmalloc(width * height * sizeof(*me->data[0]), + GFP_KERNEL); + if (!me->data[i]) { + unsigned int j; + + for (j = 0; j < i; j++) { + kvfree(me->data[j]); + me->data[j] = NULL; + } + kfree(me); + return NULL; + } + } + + IA_CSS_LEAVE(""); + return me; +} + +void +ia_css_shading_table_free(struct ia_css_shading_table *table) +{ + unsigned int i; + + if (!table) + return; + + /* + * We only output logging when the table is not NULL, otherwise + * logs will give the impression that a table was freed. + */ + IA_CSS_ENTER(""); + + for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) { + if (table->data[i]) { + kvfree(table->data[i]); + table->data[i] = NULL; + } + } + kfree(table); + + IA_CSS_LEAVE(""); +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_param_shading.h b/drivers/staging/media/atomisp/pci/sh_css_param_shading.h new file mode 100644 index 000000000..7cdfaaec0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_param_shading.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_PARAMS_SHADING_H +#define __SH_CSS_PARAMS_SHADING_H + +#include +#include + +void +sh_css_params_shading_id_table_generate( + struct ia_css_shading_table **target_table, + unsigned int table_width, + unsigned int table_height); + +void +prepare_shading_table(const struct ia_css_shading_table *in_table, + unsigned int sensor_binning, + struct ia_css_shading_table **target_table, + const struct ia_css_binary *binary, + unsigned int bds_factor); + +#endif /* __SH_CSS_PARAMS_SHADING_H */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_params.c b/drivers/staging/media/atomisp/pci/sh_css_params.c new file mode 100644 index 000000000..f08564f58 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_params.c @@ -0,0 +1,4510 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gdc_device.h" /* gdc_lut_store(), ... */ +#include "isp.h" /* ISP_VEC_ELEMBITS */ +#include "vamem.h" +#ifndef __INLINE_HMEM__ +#define __INLINE_HMEM__ +#endif +#include "hmem.h" +#define IA_CSS_INCLUDE_PARAMETERS +#define IA_CSS_INCLUDE_ACC_PARAMETERS + +#include "hmm.h" +#include "sh_css_params.h" +#include "ia_css_queue.h" +#include "sw_event_global.h" /* Event IDs */ + +#include "platform_support.h" +#include "assert_support.h" +#include "misc_support.h" /* NOT_USED */ +#include "math_support.h" /* max(), min() EVEN_FLOOR()*/ + +#include "ia_css_stream.h" +#include "sh_css_params_internal.h" +#include "sh_css_param_shading.h" +#include "sh_css_param_dvs.h" +#include "ia_css_refcount.h" +#include "sh_css_internal.h" +#include "ia_css_control.h" +#include "ia_css_shading.h" +#include "sh_css_defs.h" +#include "sh_css_sp.h" +#include "ia_css_pipeline.h" +#include "ia_css_debug.h" + +#include "ia_css_isp_param.h" +#include "ia_css_isp_params.h" +#include "ia_css_mipi.h" +#include "ia_css_morph.h" +#include "ia_css_host_data.h" +#include "ia_css_pipe.h" +#include "ia_css_pipe_binarydesc.h" + +/* Include all kernel host interfaces for ISP1 */ + +#include "anr/anr_1.0/ia_css_anr.host.h" +#include "cnr/cnr_1.0/ia_css_cnr.host.h" +#include "csc/csc_1.0/ia_css_csc.host.h" +#include "de/de_1.0/ia_css_de.host.h" +#include "dp/dp_1.0/ia_css_dp.host.h" +#include "bnr/bnr_1.0/ia_css_bnr.host.h" +#include "dvs/dvs_1.0/ia_css_dvs.host.h" +#include "fpn/fpn_1.0/ia_css_fpn.host.h" +#include "gc/gc_1.0/ia_css_gc.host.h" +#include "macc/macc_1.0/ia_css_macc.host.h" +#include "ctc/ctc_1.0/ia_css_ctc.host.h" +#include "ob/ob_1.0/ia_css_ob.host.h" +#include "raw/raw_1.0/ia_css_raw.host.h" +#include "fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h" +#include "s3a/s3a_1.0/ia_css_s3a.host.h" +#include "sc/sc_1.0/ia_css_sc.host.h" +#include "sdis/sdis_1.0/ia_css_sdis.host.h" +#include "tnr/tnr_1.0/ia_css_tnr.host.h" +#include "uds/uds_1.0/ia_css_uds_param.h" +#include "wb/wb_1.0/ia_css_wb.host.h" +#include "ynr/ynr_1.0/ia_css_ynr.host.h" +#include "xnr/xnr_1.0/ia_css_xnr.host.h" + +/* Include additional kernel host interfaces for ISP2 */ + +#include "aa/aa_2/ia_css_aa2.host.h" +#include "anr/anr_2/ia_css_anr2.host.h" +#include "bh/bh_2/ia_css_bh.host.h" +#include "cnr/cnr_2/ia_css_cnr2.host.h" +#include "ctc/ctc1_5/ia_css_ctc1_5.host.h" +#include "de/de_2/ia_css_de2.host.h" +#include "gc/gc_2/ia_css_gc2.host.h" +#include "sdis/sdis_2/ia_css_sdis2.host.h" +#include "ynr/ynr_2/ia_css_ynr2.host.h" +#include "fc/fc_1.0/ia_css_formats.host.h" + +#include "xnr/xnr_3.0/ia_css_xnr3.host.h" + + +#include "sh_css_frac.h" +#include "ia_css_bufq.h" + +#define FPNTBL_BYTES(binary) \ + (sizeof(char) * (binary)->in_frame_info.res.height * \ + (binary)->in_frame_info.padded_width) + +#define SCTBL_BYTES(binary) \ + (sizeof(unsigned short) * (binary)->sctbl_height * \ + (binary)->sctbl_aligned_width_per_color * IA_CSS_SC_NUM_COLORS) + +#define MORPH_PLANE_BYTES(binary) \ + (SH_CSS_MORPH_TABLE_ELEM_BYTES * (binary)->morph_tbl_aligned_width * \ + (binary)->morph_tbl_height) + +/* We keep a second copy of the ptr struct for the SP to access. + Again, this would not be necessary on the chip. */ +static ia_css_ptr sp_ddr_ptrs; + +/* sp group address on DDR */ +static ia_css_ptr xmem_sp_group_ptrs; + +static ia_css_ptr xmem_sp_stage_ptrs[IA_CSS_PIPE_ID_NUM] +[SH_CSS_MAX_STAGES]; +static ia_css_ptr xmem_isp_stage_ptrs[IA_CSS_PIPE_ID_NUM] +[SH_CSS_MAX_STAGES]; + +static ia_css_ptr default_gdc_lut; +static int interleaved_lut_temp[4][HRT_GDC_N]; + +/* END DO NOT MOVE INTO VIMALS_WORLD */ + +/* Digital Zoom lookup table. See documentation for more details about the + * contents of this table. + */ +static const int zoom_table[4][HRT_GDC_N] = { + { + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, + -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, + -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, + -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, -2 << 4, + -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, + -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, + -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, + -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, -3 << 4, + -4 << 4, -4 << 4, -4 << 4, -4 << 4, -4 << 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<< 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, -1 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, + 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, 1 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, + 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4, 0 << 4 + } +}; + +static const struct ia_css_dz_config default_dz_config = { + HRT_GDC_N, + HRT_GDC_N, + { + \ + {0, 0}, \ + {0, 0}, \ + } +}; + +static const struct ia_css_vector default_motion_config = { + 0, + 0 +}; + +/* ------ deprecated(bz675) : from ------ */ +static const struct ia_css_shading_settings default_shading_settings = { + 1 /* enable shading table conversion in the css + (This matches the legacy way.) */ +}; + +/* ------ deprecated(bz675) : to ------ */ + +struct ia_css_isp_skc_dvs_statistics { + ia_css_ptr p_data; +}; + +static int +ref_sh_css_ddr_address_map( + struct sh_css_ddr_address_map *map, + struct sh_css_ddr_address_map *out); + +static int +write_ia_css_isp_parameter_set_info_to_ddr( + struct ia_css_isp_parameter_set_info *me, + ia_css_ptr *out); + +static int +free_ia_css_isp_parameter_set_info(ia_css_ptr ptr); + +static int +sh_css_params_write_to_ddr_internal( + struct ia_css_pipe *pipe, + unsigned int pipe_id, + struct ia_css_isp_parameters *params, + const struct ia_css_pipeline_stage *stage, + struct sh_css_ddr_address_map *ddr_map, + struct sh_css_ddr_address_map_size *ddr_map_size); + +static int +sh_css_create_isp_params(struct ia_css_stream *stream, + struct ia_css_isp_parameters **isp_params_out); + +static bool +sh_css_init_isp_params_from_global(struct ia_css_stream *stream, + struct ia_css_isp_parameters *params, + bool use_default_config, + struct ia_css_pipe *pipe_in); + +static int +sh_css_init_isp_params_from_config(struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe_in); + +static int +sh_css_set_global_isp_config_on_pipe( + struct ia_css_pipe *curr_pipe, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe); + +static int +sh_css_set_per_frame_isp_config_on_pipe( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe); + +static int +sh_css_update_uds_and_crop_info_based_on_zoom_region( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *in_frame_info, + const struct ia_css_frame_info *out_frame_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_dz_config *zoom, + const struct ia_css_vector *motion_vector, + struct sh_css_uds_info *uds, /* out */ + struct sh_css_crop_pos *sp_out_crop_pos, /* out */ + struct ia_css_resolution pipe_in_res, + bool enable_zoom); + +ia_css_ptr +sh_css_params_ddr_address_map(void) +{ + return sp_ddr_ptrs; +} + +/* **************************************************** + * Each coefficient is stored as 7bits to fit 2 of them into one + * ISP vector element, so we will store 4 coefficents on every + * memory word (32bits) + * + * 0: Coefficient 0 used bits + * 1: Coefficient 1 used bits + * 2: Coefficient 2 used bits + * 3: Coefficient 3 used bits + * x: not used + * + * xx33333332222222 | xx11111110000000 + * + * *************************************************** + */ +static struct ia_css_host_data * +convert_allocate_fpntbl(struct ia_css_isp_parameters *params) +{ + unsigned int i, j; + short *data_ptr; + struct ia_css_host_data *me; + unsigned int isp_format_data_size; + u32 *isp_format_data_ptr; + + assert(params); + + data_ptr = params->fpn_config.data; + isp_format_data_size = params->fpn_config.height * params->fpn_config.width * + sizeof(uint32_t); + + me = ia_css_host_data_allocate(isp_format_data_size); + + if (!me) + return NULL; + + isp_format_data_ptr = (uint32_t *)me->address; + + for (i = 0; i < params->fpn_config.height; i++) { + for (j = 0; + j < params->fpn_config.width; + j += 4, data_ptr += 4, isp_format_data_ptr++) { + int data = data_ptr[0] << 0 | + data_ptr[1] << 7 | + data_ptr[2] << 16 | + data_ptr[3] << 23; + *isp_format_data_ptr = data; + } + } + return me; +} + +static int +store_fpntbl(struct ia_css_isp_parameters *params, ia_css_ptr ptr) +{ + struct ia_css_host_data *isp_data; + + assert(params); + assert(ptr != mmgr_NULL); + + isp_data = convert_allocate_fpntbl(params); + if (!isp_data) { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + ia_css_params_store_ia_css_host_data(ptr, isp_data); + + ia_css_host_data_free(isp_data); + return 0; +} + +static void +convert_raw_to_fpn(struct ia_css_isp_parameters *params) +{ + int maxval = 0; + unsigned int i; + + assert(params); + + /* Find the maximum value in the table */ + for (i = 0; i < params->fpn_config.height * params->fpn_config.width; i++) { + int val = params->fpn_config.data[i]; + /* Make sure FPN value can be represented in 13-bit unsigned + * number (ISP precision - 1), but note that actual input range + * depends on precision of input frame data. + */ + if (val < 0) { + /* Checkpatch patch */ + val = 0; + } else if (val >= (1 << 13)) { + /* Checkpatch patch */ + /* MW: BUG, is "13" a system or application property */ + val = (1 << 13) - 1; + } + maxval = max(maxval, val); + } + /* Find the lowest shift value to remap the values in the range + * 0..maxval to 0..2^shiftval*63. + */ + params->fpn_config.shift = 0; + while (maxval > 63) { + /* MW: BUG, is "63" a system or application property */ + maxval >>= 1; + params->fpn_config.shift++; + } + /* Adjust the values in the table for the shift value */ + for (i = 0; i < params->fpn_config.height * params->fpn_config.width; i++) + ((unsigned short *)params->fpn_config.data)[i] >>= params->fpn_config.shift; +} + +static void +ia_css_process_kernel(struct ia_css_stream *stream, + struct ia_css_isp_parameters *params, + void (*process)(unsigned int pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params)) +{ + int i; + + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *pipe = stream->pipes[i]; + struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe); + struct ia_css_pipeline_stage *stage; + + /* update the other buffers to the pipe specific copies */ + for (stage = pipeline->stages; stage; stage = stage->next) { + if (!stage || !stage->binary) continue; + process(pipeline->pipe_id, stage, params); + } + } +} + +static int +sh_css_select_dp_10bpp_config(const struct ia_css_pipe *pipe, + bool *is_dp_10bpp) +{ + int err = 0; + /* Currently we check if 10bpp DPC configuration is required based + * on the use case,i.e. if BDS and DPC is both enabled. The more cleaner + * design choice would be to expose the type of DPC (either 10bpp or 13bpp) + * using the binary info, but the current control flow does not allow this + * implementation. (This is because the configuration is set before a + * binary is selected, and the binary info is not available) + */ + if ((!pipe) || (!is_dp_10bpp)) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + err = -EINVAL; + } else { + *is_dp_10bpp = false; + + /* check if DPC is enabled from the host */ + if (pipe->config.enable_dpc) { + /*check if BDS is enabled*/ + unsigned int required_bds_factor = SH_CSS_BDS_FACTOR_1_00; + + if ((pipe->config.bayer_ds_out_res.width != 0) && + (pipe->config.bayer_ds_out_res.height != 0)) { + if (0 == binarydesc_calculate_bds_factor( + pipe->config.input_effective_res, + pipe->config.bayer_ds_out_res, + &required_bds_factor)) { + if (required_bds_factor != SH_CSS_BDS_FACTOR_1_00) { + /*we use 10bpp BDS configuration*/ + *is_dp_10bpp = true; + } + } + } + } + } + + return err; +} + +int +sh_css_set_black_frame(struct ia_css_stream *stream, + const struct ia_css_frame *raw_black_frame) +{ + struct ia_css_isp_parameters *params; + /* this function desperately needs to be moved to the ISP or SP such + * that it can use the DMA. + */ + unsigned int height, width, y, x, k, data; + ia_css_ptr ptr; + + assert(stream); + assert(raw_black_frame); + + params = stream->isp_params_configs; + height = raw_black_frame->frame_info.res.height; + width = raw_black_frame->frame_info.padded_width; + + ptr = raw_black_frame->data + + raw_black_frame->planes.raw.offset; + + IA_CSS_ENTER_PRIVATE("black_frame=%p", raw_black_frame); + + if (params->fpn_config.data && + (params->fpn_config.width != width || params->fpn_config.height != height)) { + kvfree(params->fpn_config.data); + params->fpn_config.data = NULL; + } + if (!params->fpn_config.data) { + params->fpn_config.data = kvmalloc(array3_size(height, width, sizeof(short)), + GFP_KERNEL); + if (!params->fpn_config.data) { + IA_CSS_ERROR("out of memory"); + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + params->fpn_config.width = width; + params->fpn_config.height = height; + params->fpn_config.shift = 0; + } + + /* store raw to fpntbl */ + for (y = 0; y < height; y++) { + for (x = 0; x < width; x += (ISP_VEC_NELEMS * 2)) { + int ofs = y * width + x; + + for (k = 0; k < ISP_VEC_NELEMS; k += 2) { + hmm_load(ptr, (void *)(&data), sizeof(int)); + params->fpn_config.data[ofs + 2 * k] = + (short)(data & 0xFFFF); + params->fpn_config.data[ofs + 2 * k + 2] = + (short)((data >> 16) & 0xFFFF); + ptr += sizeof(int); /* byte system address */ + } + for (k = 0; k < ISP_VEC_NELEMS; k += 2) { + hmm_load(ptr, (void *)(&data), sizeof(int)); + params->fpn_config.data[ofs + 2 * k + 1] = + (short)(data & 0xFFFF); + params->fpn_config.data[ofs + 2 * k + 3] = + (short)((data >> 16) & 0xFFFF); + ptr += sizeof(int); /* byte system address */ + } + } + } + + /* raw -> fpn */ + convert_raw_to_fpn(params); + + /* overwrite isp parameter */ + ia_css_process_kernel(stream, params, ia_css_kernel_process_param[IA_CSS_FPN_ID]); + + IA_CSS_LEAVE_ERR_PRIVATE(0); + + return 0; +} + +bool +sh_css_params_set_binning_factor(struct ia_css_stream *stream, + unsigned int binning_fact) +{ + struct ia_css_isp_parameters *params; + + IA_CSS_ENTER_PRIVATE("void"); + assert(stream); + + params = stream->isp_params_configs; + + if (params->sensor_binning != binning_fact) { + params->sensor_binning = binning_fact; + params->sc_table_changed = true; + } + + IA_CSS_LEAVE_PRIVATE("void"); + + return params->sc_table_changed; +} + +static void +sh_css_set_shading_table(struct ia_css_stream *stream, + struct ia_css_isp_parameters *params, + const struct ia_css_shading_table *table) +{ + IA_CSS_ENTER_PRIVATE(""); + if (!table) + return; + assert(stream); + + if (!table->enable) + table = NULL; + + if (table != params->sc_table) { + params->sc_table = table; + params->sc_table_changed = true; + /* Not very clean, this goes to sh_css.c to invalidate the + * shading table for all pipes. Should replaced by a loop + * and a pipe-specific call. + */ + if (!params->output_frame) + sh_css_invalidate_shading_tables(stream); + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +ia_css_params_store_ia_css_host_data( + ia_css_ptr ddr_addr, + struct ia_css_host_data *data) +{ + assert(data); + assert(data->address); + assert(ddr_addr != mmgr_NULL); + + IA_CSS_ENTER_PRIVATE(""); + + hmm_store(ddr_addr, + (void *)(data->address), + (size_t)data->size); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +struct ia_css_host_data * +ia_css_params_alloc_convert_sctbl( + const struct ia_css_pipeline_stage *stage, + const struct ia_css_shading_table *shading_table) +{ + const struct ia_css_binary *binary = stage->binary; + struct ia_css_host_data *sctbl; + unsigned int i, j, aligned_width; + unsigned int sctbl_size; + short int *ptr; + + assert(binary); + assert(shading_table); + + IA_CSS_ENTER_PRIVATE(""); + + if (!shading_table) { + IA_CSS_LEAVE_PRIVATE("void"); + return NULL; + } + + aligned_width = binary->sctbl_aligned_width_per_color; + sctbl_size = shading_table->height * IA_CSS_SC_NUM_COLORS * aligned_width * + sizeof(short); + + sctbl = ia_css_host_data_allocate((size_t)sctbl_size); + + if (!sctbl) + return NULL; + ptr = (short int *)sctbl->address; + memset(ptr, + 0, + sctbl_size); + + for (i = 0; i < shading_table->height; i++) { + for (j = 0; j < IA_CSS_SC_NUM_COLORS; j++) { + memcpy(ptr, + &shading_table->data[j] + [i * shading_table->width], + shading_table->width * sizeof(short)); + ptr += aligned_width; + } + } + + IA_CSS_LEAVE_PRIVATE("void"); + return sctbl; +} + +int ia_css_params_store_sctbl( + const struct ia_css_pipeline_stage *stage, + ia_css_ptr sc_tbl, + const struct ia_css_shading_table *sc_config) +{ + struct ia_css_host_data *isp_sc_tbl; + + IA_CSS_ENTER_PRIVATE(""); + + if (!sc_config) { + IA_CSS_LEAVE_PRIVATE("void"); + return 0; + } + + isp_sc_tbl = ia_css_params_alloc_convert_sctbl(stage, sc_config); + if (!isp_sc_tbl) { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + /* store the shading table to ddr */ + ia_css_params_store_ia_css_host_data(sc_tbl, isp_sc_tbl); + ia_css_host_data_free(isp_sc_tbl); + + IA_CSS_LEAVE_PRIVATE("void"); + + return 0; +} + +static void +sh_css_enable_pipeline(const struct ia_css_binary *binary) +{ + if (!binary) + return; + + IA_CSS_ENTER_PRIVATE(""); + + ia_css_isp_param_enable_pipeline(&binary->mem_params); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static int +ia_css_process_zoom_and_motion( + struct ia_css_isp_parameters *params, + const struct ia_css_pipeline_stage *first_stage) +{ + /* first_stage can be NULL */ + const struct ia_css_pipeline_stage *stage; + int err = 0; + struct ia_css_resolution pipe_in_res; + + pipe_in_res.width = 0; + pipe_in_res.height = 0; + + assert(params); + + IA_CSS_ENTER_PRIVATE(""); + + /* Go through all stages to udate uds and cropping */ + for (stage = first_stage; stage; stage = stage->next) { + struct ia_css_binary *binary; + /* note: the var below is made static as it is quite large; + if it is not static it ends up on the stack which could + cause issues for drivers + */ + static struct ia_css_binary tmp_binary; + + const struct ia_css_binary_xinfo *info = NULL; + + binary = stage->binary; + if (binary) { + info = binary->info; + } else { + const struct sh_css_binary_args *args = &stage->args; + const struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL}; + + out_infos[0] = ia_css_frame_get_info(args->out_frame[0]); + + info = &stage->firmware->info.isp; + ia_css_binary_fill_info(info, false, false, + ATOMISP_INPUT_FORMAT_RAW_10, + ia_css_frame_get_info(args->in_frame), + NULL, + out_infos, + ia_css_frame_get_info(args->out_vf_frame), + &tmp_binary, + NULL, + -1, true); + binary = &tmp_binary; + binary->info = info; + } + + if (stage == first_stage) { + /* we will use pipe_in_res to scale the zoom crop region if needed */ + pipe_in_res = binary->effective_in_frame_res; + } + + assert(stage->stage_num < SH_CSS_MAX_STAGES); + if (params->dz_config.zoom_region.resolution.width == 0 && + params->dz_config.zoom_region.resolution.height == 0) { + sh_css_update_uds_and_crop_info( + &info->sp, + &binary->in_frame_info, + &binary->out_frame_info[0], + &binary->dvs_envelope, + ¶ms->dz_config, + ¶ms->motion_config, + ¶ms->uds[stage->stage_num].uds, + ¶ms->uds[stage->stage_num].crop_pos, + stage->enable_zoom); + } else { + err = sh_css_update_uds_and_crop_info_based_on_zoom_region( + &info->sp, + &binary->in_frame_info, + &binary->out_frame_info[0], + &binary->dvs_envelope, + ¶ms->dz_config, + ¶ms->motion_config, + ¶ms->uds[stage->stage_num].uds, + ¶ms->uds[stage->stage_num].crop_pos, + pipe_in_res, + stage->enable_zoom); + if (err) + return err; + } + } + params->isp_params_changed = true; + + IA_CSS_LEAVE_PRIVATE("void"); + return err; +} + +static void +sh_css_set_gamma_table(struct ia_css_isp_parameters *params, + const struct ia_css_gamma_table *table) +{ + if (!table) + return; + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params); + params->gc_table = *table; + params->config_changed[IA_CSS_GC_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_gamma_table(const struct ia_css_isp_parameters *params, + struct ia_css_gamma_table *table) +{ + if (!table) + return; + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params); + *table = params->gc_table; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_ctc_table(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_table *table) +{ + if (!table) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params); + params->ctc_table = *table; + params->config_changed[IA_CSS_CTC_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_ctc_table(const struct ia_css_isp_parameters *params, + struct ia_css_ctc_table *table) +{ + if (!table) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params); + *table = params->ctc_table; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_macc_table(struct ia_css_isp_parameters *params, + const struct ia_css_macc_table *table) +{ + if (!table) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params); + params->macc_table = *table; + params->config_changed[IA_CSS_MACC_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_macc_table(const struct ia_css_isp_parameters *params, + struct ia_css_macc_table *table) +{ + if (!table) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params); + *table = params->macc_table; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void ia_css_morph_table_free( + struct ia_css_morph_table *me) +{ + unsigned int i; + + if (!me) + return; + + IA_CSS_ENTER(""); + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + if (me->coordinates_x[i]) { + kvfree(me->coordinates_x[i]); + me->coordinates_x[i] = NULL; + } + if (me->coordinates_y[i]) { + kvfree(me->coordinates_y[i]); + me->coordinates_y[i] = NULL; + } + } + + kvfree(me); + IA_CSS_LEAVE("void"); +} + +struct ia_css_morph_table *ia_css_morph_table_allocate( + unsigned int width, + unsigned int height) +{ + unsigned int i; + struct ia_css_morph_table *me; + + IA_CSS_ENTER(""); + + me = kvmalloc(sizeof(*me), GFP_KERNEL); + if (!me) { + IA_CSS_ERROR("out of memory"); + return me; + } + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + me->coordinates_x[i] = NULL; + me->coordinates_y[i] = NULL; + } + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + me->coordinates_x[i] = kvmalloc(height * width * + sizeof(*me->coordinates_x[i]), + GFP_KERNEL); + me->coordinates_y[i] = kvmalloc(height * width * + sizeof(*me->coordinates_y[i]), + GFP_KERNEL); + + if ((!me->coordinates_x[i]) || + (!me->coordinates_y[i])) { + ia_css_morph_table_free(me); + me = NULL; + return me; + } + } + me->width = width; + me->height = height; + IA_CSS_LEAVE(""); + return me; +} + +static int sh_css_params_default_morph_table( + struct ia_css_morph_table **table, + const struct ia_css_binary *binary) +{ + /* MW 2400 advanced requires different scaling */ + unsigned int i, j, k, step, width, height; + short start_x[IA_CSS_MORPH_TABLE_NUM_PLANES] = { -8, 0, -8, 0, 0, -8 }, + start_y[IA_CSS_MORPH_TABLE_NUM_PLANES] = { 0, 0, -8, -8, -8, 0 }; + struct ia_css_morph_table *tab; + + assert(table); + assert(binary); + + IA_CSS_ENTER_PRIVATE(""); + + step = (ISP_VEC_NELEMS / 16) * 128; + width = binary->morph_tbl_width; + height = binary->morph_tbl_height; + + tab = ia_css_morph_table_allocate(width, height); + if (!tab) + return -ENOMEM; + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + short val_y = start_y[i]; + + for (j = 0; j < height; j++) { + short val_x = start_x[i]; + unsigned short *x_ptr, *y_ptr; + + x_ptr = &tab->coordinates_x[i][j * width]; + y_ptr = &tab->coordinates_y[i][j * width]; + for (k = 0; k < width; + k++, x_ptr++, y_ptr++, val_x += (short)step) { + if (k == 0) + *x_ptr = 0; + else if (k == width - 1) + *x_ptr = val_x + 2 * start_x[i]; + else + *x_ptr = val_x; + if (j == 0) + *y_ptr = 0; + else + *y_ptr = val_y; + } + val_y += (short)step; + } + } + *table = tab; + + IA_CSS_LEAVE_ERR_PRIVATE(0); + + return 0; +} + +static void +sh_css_set_morph_table(struct ia_css_isp_parameters *params, + const struct ia_css_morph_table *table) +{ + if (!table) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params); + if (table->enable == false) + table = NULL; + params->morph_table = table; + params->morph_table_changed = true; + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +ia_css_translate_3a_statistics( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_isp_3a_statistics_map *isp_stats) +{ + IA_CSS_ENTER(""); + if (host_stats->grid.use_dmem) { + IA_CSS_LOG("3A: DMEM"); + ia_css_s3a_dmem_decode(host_stats, isp_stats->dmem_stats); + } else { + IA_CSS_LOG("3A: VMEM"); + ia_css_s3a_vmem_decode(host_stats, isp_stats->vmem_stats_hi, + isp_stats->vmem_stats_lo); + } + IA_CSS_LOG("3A: HMEM"); + ia_css_s3a_hmem_decode(host_stats, isp_stats->hmem_stats); + + IA_CSS_LEAVE("void"); +} + +void +ia_css_isp_3a_statistics_map_free(struct ia_css_isp_3a_statistics_map *me) +{ + if (me) { + if (me->data_allocated) { + kvfree(me->data_ptr); + me->data_ptr = NULL; + me->data_allocated = false; + } + kvfree(me); + } +} + +struct ia_css_isp_3a_statistics_map * +ia_css_isp_3a_statistics_map_allocate( + const struct ia_css_isp_3a_statistics *isp_stats, + void *data_ptr) +{ + struct ia_css_isp_3a_statistics_map *me; + /* Windows compiler does not like adding sizes to a void * + * so we use a local char * instead. */ + char *base_ptr; + + me = kvmalloc(sizeof(*me), GFP_KERNEL); + if (!me) { + IA_CSS_LEAVE("cannot allocate memory"); + goto err; + } + + me->data_ptr = data_ptr; + me->data_allocated = !data_ptr; + if (!data_ptr) { + me->data_ptr = kvmalloc(isp_stats->size, GFP_KERNEL); + if (!me->data_ptr) { + IA_CSS_LEAVE("cannot allocate memory"); + goto err; + } + } + base_ptr = me->data_ptr; + + me->size = isp_stats->size; + /* GCC complains when we assign a char * to a void *, so these + * casts are necessary unfortunately. */ + me->dmem_stats = (void *)base_ptr; + me->vmem_stats_hi = (void *)(base_ptr + isp_stats->dmem_size); + me->vmem_stats_lo = (void *)(base_ptr + isp_stats->dmem_size + + isp_stats->vmem_size); + me->hmem_stats = (void *)(base_ptr + isp_stats->dmem_size + + 2 * isp_stats->vmem_size); + + IA_CSS_LEAVE("map=%p", me); + return me; + +err: + kvfree(me); + return NULL; +} + +int +ia_css_get_3a_statistics(struct ia_css_3a_statistics *host_stats, + const struct ia_css_isp_3a_statistics *isp_stats) +{ + struct ia_css_isp_3a_statistics_map *map; + int ret = 0; + + IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats); + + assert(host_stats); + assert(isp_stats); + + map = ia_css_isp_3a_statistics_map_allocate(isp_stats, NULL); + if (map) { + hmm_load(isp_stats->data_ptr, map->data_ptr, isp_stats->size); + ia_css_translate_3a_statistics(host_stats, map); + ia_css_isp_3a_statistics_map_free(map); + } else { + IA_CSS_ERROR("out of memory"); + ret = -ENOMEM; + } + + IA_CSS_LEAVE_ERR(ret); + return ret; +} + +/* Parameter encoding is not yet orthogonal. + This function hnadles some of the exceptions. +*/ +static void +ia_css_set_param_exceptions(const struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params) +{ + assert(params); + + /* Copy also to DP. Should be done by the driver. */ + params->dp_config.gr = params->wb_config.gr; + params->dp_config.r = params->wb_config.r; + params->dp_config.b = params->wb_config.b; + params->dp_config.gb = params->wb_config.gb; +} + +static void +sh_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config) +{ + if (!config) + return; + assert(params); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE); + params->nr_config = *config; + params->yee_config.nr = *config; + params->config_changed[IA_CSS_NR_ID] = true; + params->config_changed[IA_CSS_YEE_ID] = true; + params->config_changed[IA_CSS_BNR_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_ee_config(struct ia_css_isp_parameters *params, + const struct ia_css_ee_config *config) +{ + if (!config) + return; + assert(params); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + ia_css_ee_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE); + + params->ee_config = *config; + params->yee_config.ee = *config; + params->config_changed[IA_CSS_YEE_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_ee_config(const struct ia_css_isp_parameters *params, + struct ia_css_ee_config *config) +{ + if (!config) + return; + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + assert(params); + *config = params->ee_config; + + ia_css_ee_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE); + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_pipe_dvs_6axis_config(const struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params, + const struct ia_css_dvs_6axis_config *dvs_config) +{ + if (!dvs_config) + return; + assert(params); + assert(pipe); + assert(dvs_config->height_y == dvs_config->height_uv); + assert((dvs_config->width_y - 1) == 2 * (dvs_config->width_uv - 1)); + assert(pipe->mode < IA_CSS_PIPE_ID_NUM); + + IA_CSS_ENTER_PRIVATE("dvs_config=%p", dvs_config); + + copy_dvs_6axis_table(params->pipe_dvs_6axis_config[pipe->mode], dvs_config); + + params->pipe_dvs_6axis_config_changed[pipe->mode] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_pipe_dvs_6axis_config(const struct ia_css_pipe *pipe, + const struct ia_css_isp_parameters *params, + struct ia_css_dvs_6axis_config *dvs_config) +{ + if (!dvs_config) + return; + assert(params); + assert(pipe); + assert(dvs_config->height_y == dvs_config->height_uv); + assert((dvs_config->width_y - 1) == 2 * dvs_config->width_uv - 1); + + IA_CSS_ENTER_PRIVATE("dvs_config=%p", dvs_config); + + if ((pipe->mode < IA_CSS_PIPE_ID_NUM) && + (dvs_config->width_y == params->pipe_dvs_6axis_config[pipe->mode]->width_y) && + (dvs_config->height_y == params->pipe_dvs_6axis_config[pipe->mode]->height_y) && + (dvs_config->width_uv == params->pipe_dvs_6axis_config[pipe->mode]->width_uv) && + (dvs_config->height_uv == params->pipe_dvs_6axis_config[pipe->mode]->height_uv) + && + dvs_config->xcoords_y && + dvs_config->ycoords_y && + dvs_config->xcoords_uv && + dvs_config->ycoords_uv) { + copy_dvs_6axis_table(dvs_config, params->pipe_dvs_6axis_config[pipe->mode]); + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_baa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config) +{ + if (!config) + return; + assert(params); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + params->bds_config = *config; + params->config_changed[IA_CSS_BDS_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_baa_config(const struct ia_css_isp_parameters *params, + struct ia_css_aa_config *config) +{ + if (!config) + return; + assert(params); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + *config = params->bds_config; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_dz_config(struct ia_css_isp_parameters *params, + const struct ia_css_dz_config *config) +{ + if (!config) + return; + assert(params); + + IA_CSS_ENTER_PRIVATE("dx=%d, dy=%d", config->dx, config->dy); + + assert(config->dx <= HRT_GDC_N); + assert(config->dy <= HRT_GDC_N); + + params->dz_config = *config; + params->dz_config_changed = true; + /* JK: Why isp params changed?? */ + params->isp_params_changed = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_dz_config(const struct ia_css_isp_parameters *params, + struct ia_css_dz_config *config) +{ + if (!config) + return; + assert(params); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + *config = params->dz_config; + + IA_CSS_LEAVE_PRIVATE("dx=%d, dy=%d", config->dx, config->dy); +} + +static void +sh_css_set_motion_vector(struct ia_css_isp_parameters *params, + const struct ia_css_vector *motion) +{ + if (!motion) + return; + assert(params); + + IA_CSS_ENTER_PRIVATE("x=%d, y=%d", motion->x, motion->y); + + params->motion_config = *motion; + /* JK: Why do isp params change? */ + params->motion_config_changed = true; + params->isp_params_changed = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_motion_vector(const struct ia_css_isp_parameters *params, + struct ia_css_vector *motion) +{ + if (!motion) + return; + assert(params); + + IA_CSS_ENTER_PRIVATE("motion=%p", motion); + + *motion = params->motion_config; + + IA_CSS_LEAVE_PRIVATE("x=%d, y=%d", motion->x, motion->y); +} + +struct ia_css_isp_config * +sh_css_pipe_isp_config_get(struct ia_css_pipe *pipe) +{ + if (!pipe) { + IA_CSS_ERROR("pipe=%p", NULL); + return NULL; + } + return pipe->config.p_isp_config; +} + +int +ia_css_stream_set_isp_config( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config) +{ + return ia_css_stream_set_isp_config_on_pipe(stream, config, NULL); +} + +int +ia_css_stream_set_isp_config_on_pipe( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe) +{ + int err = 0; + + if ((!stream) || (!config)) + return -EINVAL; + + IA_CSS_ENTER("stream=%p, config=%p, pipe=%p", stream, config, pipe); + + if (config->output_frame) + err = sh_css_set_per_frame_isp_config_on_pipe(stream, config, pipe); + else + err = sh_css_set_global_isp_config_on_pipe(stream->pipes[0], config, pipe); + + IA_CSS_LEAVE_ERR(err); + return err; +} + +int +ia_css_pipe_set_isp_config(struct ia_css_pipe *pipe, + struct ia_css_isp_config *config) +{ + struct ia_css_pipe *pipe_in = pipe; + int err = 0; + + IA_CSS_ENTER("pipe=%p", pipe); + + if ((!pipe) || (!pipe->stream)) + return -EINVAL; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "config=%p\n", config); + + if (config->output_frame) + err = sh_css_set_per_frame_isp_config_on_pipe(pipe->stream, config, pipe); + else + err = sh_css_set_global_isp_config_on_pipe(pipe, config, pipe_in); + IA_CSS_LEAVE_ERR(err); + return err; +} + +static int +sh_css_set_global_isp_config_on_pipe( + struct ia_css_pipe *curr_pipe, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe) +{ + int err = 0; + int err1 = 0; + int err2 = 0; + + IA_CSS_ENTER_PRIVATE("stream=%p, config=%p, pipe=%p", curr_pipe, config, pipe); + + err1 = sh_css_init_isp_params_from_config(curr_pipe, curr_pipe->stream->isp_params_configs, config, pipe); + + /* Now commit all changes to the SP */ + err2 = sh_css_param_update_isp_params(curr_pipe, curr_pipe->stream->isp_params_configs, sh_css_sp_is_running(), pipe); + + /* The following code is intentional. The sh_css_init_isp_params_from_config interface + * throws an error when both DPC and BDS is enabled. The CSS API must pass this error + * information to the caller, ie. the host. We do not return this error immediately, + * but instead continue with updating the ISP params to enable testing of features + * which are currently in TR phase. */ + + err = (err1 != 0) ? err1 : ((err2 != 0) ? err2 : err); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int +sh_css_set_per_frame_isp_config_on_pipe( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe) +{ + unsigned int i; + bool per_frame_config_created = false; + int err = 0; + int err1 = 0; + int err2 = 0; + int err3 = 0; + + struct sh_css_ddr_address_map *ddr_ptrs; + struct sh_css_ddr_address_map_size *ddr_ptrs_size; + struct ia_css_isp_parameters *params; + + IA_CSS_ENTER_PRIVATE("stream=%p, config=%p, pipe=%p", stream, config, pipe); + + if (!pipe) { + err = -EINVAL; + goto exit; + } + + /* create per-frame ISP params object with default values + * from stream->isp_params_configs if one doesn't already exist + */ + if (!stream->per_frame_isp_params_configs) { + err = sh_css_create_isp_params(stream, + &stream->per_frame_isp_params_configs); + if (err) + goto exit; + per_frame_config_created = true; + } + + params = stream->per_frame_isp_params_configs; + + /* update new ISP params object with the new config */ + if (!sh_css_init_isp_params_from_global(stream, params, false, pipe)) { + err1 = -EINVAL; + } + + err2 = sh_css_init_isp_params_from_config(stream->pipes[0], params, config, pipe); + + if (per_frame_config_created) { + ddr_ptrs = ¶ms->ddr_ptrs; + ddr_ptrs_size = ¶ms->ddr_ptrs_size; + /* create per pipe reference to general ddr_ptrs */ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + ref_sh_css_ddr_address_map(ddr_ptrs, ¶ms->pipe_ddr_ptrs[i]); + params->pipe_ddr_ptrs_size[i] = *ddr_ptrs_size; + } + } + + /* now commit to ddr */ + err3 = sh_css_param_update_isp_params(stream->pipes[0], params, sh_css_sp_is_running(), pipe); + + /* The following code is intentional. The sh_css_init_sp_params_from_config and + * sh_css_init_isp_params_from_config throws an error when both DPC and BDS is enabled. + * The CSS API must pass this error information to the caller, ie. the host. + * We do not return this error immediately, but instead continue with updating the ISP params + * to enable testing of features which are currently in TR phase. */ + err = (err1 != 0) ? err1 : + (err2 != 0) ? err2 : + (err3 != 0) ? err3 : err; +exit: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int +sh_css_init_isp_params_from_config(struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe_in) +{ + int err = 0; + bool is_dp_10bpp = true; + + assert(pipe); + + IA_CSS_ENTER_PRIVATE("pipe=%p, config=%p, params=%p", pipe, config, params); + + ia_css_set_configs(params, config); + + sh_css_set_nr_config(params, config->nr_config); + sh_css_set_ee_config(params, config->ee_config); + sh_css_set_baa_config(params, config->baa_config); + if ((pipe->mode < IA_CSS_PIPE_ID_NUM) && + (params->pipe_dvs_6axis_config[pipe->mode])) + sh_css_set_pipe_dvs_6axis_config(pipe, params, config->dvs_6axis_config); + sh_css_set_dz_config(params, config->dz_config); + sh_css_set_motion_vector(params, config->motion_vector); + sh_css_set_shading_table(pipe->stream, params, config->shading_table); + sh_css_set_morph_table(params, config->morph_table); + sh_css_set_macc_table(params, config->macc_table); + sh_css_set_gamma_table(params, config->gamma_table); + sh_css_set_ctc_table(params, config->ctc_table); + /* ------ deprecated(bz675) : from ------ */ + sh_css_set_shading_settings(params, config->shading_settings); + /* ------ deprecated(bz675) : to ------ */ + + params->dis_coef_table_changed = (config->dvs_coefs); + params->dvs2_coef_table_changed = (config->dvs2_coefs); + + params->output_frame = config->output_frame; + params->isp_parameters_id = config->isp_config_id; + + if (0 == + sh_css_select_dp_10bpp_config(pipe, &is_dp_10bpp)) { + /* return an error when both DPC and BDS is enabled by the + * user. */ + /* we do not exit from this point immediately to allow internal + * firmware feature testing. */ + if (is_dp_10bpp) { + err = -EINVAL; + } + } else { + err = -EINVAL; + goto exit; + } + + ia_css_set_param_exceptions(pipe, params); + +exit: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +void +ia_css_stream_get_isp_config( + const struct ia_css_stream *stream, + struct ia_css_isp_config *config) +{ + IA_CSS_ENTER("void"); + ia_css_pipe_get_isp_config(stream->pipes[0], config); + IA_CSS_LEAVE("void"); +} + +void +ia_css_pipe_get_isp_config(struct ia_css_pipe *pipe, + struct ia_css_isp_config *config) +{ + struct ia_css_isp_parameters *params = NULL; + + assert(config); + + IA_CSS_ENTER("config=%p", config); + + params = pipe->stream->isp_params_configs; + assert(params); + + ia_css_get_configs(params, config); + + sh_css_get_ee_config(params, config->ee_config); + sh_css_get_baa_config(params, config->baa_config); + sh_css_get_pipe_dvs_6axis_config(pipe, params, config->dvs_6axis_config); + sh_css_get_macc_table(params, config->macc_table); + sh_css_get_gamma_table(params, config->gamma_table); + sh_css_get_ctc_table(params, config->ctc_table); + sh_css_get_dz_config(params, config->dz_config); + sh_css_get_motion_vector(params, config->motion_vector); + /* ------ deprecated(bz675) : from ------ */ + sh_css_get_shading_settings(params, config->shading_settings); + /* ------ deprecated(bz675) : to ------ */ + + config->output_frame = params->output_frame; + config->isp_config_id = params->isp_parameters_id; + + IA_CSS_LEAVE("void"); +} + +/* + * coding style says the return of "mmgr_NULL" is the error signal + * + * Deprecated: Implement mmgr_realloc() + */ +static bool realloc_isp_css_mm_buf( + ia_css_ptr *curr_buf, + size_t *curr_size, + size_t needed_size, + bool force, + int *err) +{ + s32 id; + + *err = 0; + /* Possible optimization: add a function sh_css_isp_css_mm_realloc() + * and implement on top of hmm. */ + + IA_CSS_ENTER_PRIVATE("void"); + + if (!force && *curr_size >= needed_size) { + IA_CSS_LEAVE_PRIVATE("false"); + return false; + } + /* don't reallocate if single ref to buffer and same size */ + if (*curr_size == needed_size && ia_css_refcount_is_single(*curr_buf)) { + IA_CSS_LEAVE_PRIVATE("false"); + return false; + } + + id = IA_CSS_REFCOUNT_PARAM_BUFFER; + ia_css_refcount_decrement(id, *curr_buf); + *curr_buf = ia_css_refcount_increment(id, hmm_alloc(needed_size)); + if (!*curr_buf) { + *err = -ENOMEM; + *curr_size = 0; + } else { + *curr_size = needed_size; + } + IA_CSS_LEAVE_PRIVATE("true"); + return true; +} + +static bool reallocate_buffer( + ia_css_ptr *curr_buf, + size_t *curr_size, + size_t needed_size, + bool force, + int *err) +{ + bool ret; + + IA_CSS_ENTER_PRIVATE("void"); + + ret = realloc_isp_css_mm_buf(curr_buf, + curr_size, needed_size, force, err); + + IA_CSS_LEAVE_PRIVATE("ret=%d", ret); + return ret; +} + +struct ia_css_isp_3a_statistics * +ia_css_isp_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid) +{ + struct ia_css_isp_3a_statistics *me; + + IA_CSS_ENTER("grid=%p", grid); + + assert(grid); + + /* MW: Does "grid->enable" also control the histogram output ?? */ + if (!grid->enable) + return NULL; + + me = kvcalloc(1, sizeof(*me), GFP_KERNEL); + if (!me) + goto err; + + if (grid->use_dmem) { + me->dmem_size = sizeof(struct ia_css_3a_output) * + grid->aligned_width * + grid->aligned_height; + } else { + me->vmem_size = ISP_S3ATBL_HI_LO_STRIDE_BYTES * + grid->aligned_height; + } + me->hmem_size = sizeof_hmem(HMEM0_ID); + + /* All subsections need to be aligned to the system bus width */ + me->dmem_size = CEIL_MUL(me->dmem_size, HIVE_ISP_DDR_WORD_BYTES); + me->vmem_size = CEIL_MUL(me->vmem_size, HIVE_ISP_DDR_WORD_BYTES); + me->hmem_size = CEIL_MUL(me->hmem_size, HIVE_ISP_DDR_WORD_BYTES); + + me->size = me->dmem_size + me->vmem_size * 2 + me->hmem_size; + me->data_ptr = hmm_alloc(me->size); + if (me->data_ptr == mmgr_NULL) { + kvfree(me); + me = NULL; + goto err; + } + if (me->dmem_size) + me->data.dmem.s3a_tbl = me->data_ptr; + if (me->vmem_size) { + me->data.vmem.s3a_tbl_hi = me->data_ptr + me->dmem_size; + me->data.vmem.s3a_tbl_lo = me->data_ptr + me->dmem_size + me->vmem_size; + } + if (me->hmem_size) + me->data_hmem.rgby_tbl = me->data_ptr + me->dmem_size + 2 * me->vmem_size; + +err: + IA_CSS_LEAVE("return=%p", me); + return me; +} + +void +ia_css_isp_3a_statistics_free(struct ia_css_isp_3a_statistics *me) +{ + if (me) { + hmm_free(me->data_ptr); + kvfree(me); + } +} + +struct ia_css_isp_skc_dvs_statistics *ia_css_skc_dvs_statistics_allocate(void) +{ + return NULL; +} + +struct ia_css_metadata * +ia_css_metadata_allocate(const struct ia_css_metadata_info *metadata_info) +{ + struct ia_css_metadata *md = NULL; + + IA_CSS_ENTER(""); + + if (metadata_info->size == 0) + return NULL; + + md = kvmalloc(sizeof(*md), GFP_KERNEL); + if (!md) + goto error; + + md->info = *metadata_info; + md->exp_id = 0; + md->address = hmm_alloc(metadata_info->size); + if (md->address == mmgr_NULL) + goto error; + + IA_CSS_LEAVE("return=%p", md); + return md; + +error: + ia_css_metadata_free(md); + IA_CSS_LEAVE("return=%p", NULL); + return NULL; +} + +void +ia_css_metadata_free(struct ia_css_metadata *me) +{ + if (me) { + /* The enter and leave macros are placed inside + * the condition to avoid false logging of metadata + * free events when metadata is disabled. + * We found this to be confusing during development + * and debugging. */ + IA_CSS_ENTER("me=%p", me); + hmm_free(me->address); + kvfree(me); + IA_CSS_LEAVE("void"); + } +} + +void +ia_css_metadata_free_multiple(unsigned int num_bufs, + struct ia_css_metadata **bufs) +{ + unsigned int i; + + if (bufs) { + for (i = 0; i < num_bufs; i++) + ia_css_metadata_free(bufs[i]); + } +} + +static unsigned int g_param_buffer_dequeue_count; +static unsigned int g_param_buffer_enqueue_count; + +int +ia_css_stream_isp_parameters_init(struct ia_css_stream *stream) +{ + int err = 0; + unsigned int i; + struct sh_css_ddr_address_map *ddr_ptrs; + struct sh_css_ddr_address_map_size *ddr_ptrs_size; + struct ia_css_isp_parameters *params; + + assert(stream); + IA_CSS_ENTER_PRIVATE("void"); + + if (!stream) { + IA_CSS_LEAVE_ERR_PRIVATE(-EINVAL); + return -EINVAL; + } + /* TMP: tracking of paramsets */ + g_param_buffer_dequeue_count = 0; + g_param_buffer_enqueue_count = 0; + + stream->per_frame_isp_params_configs = NULL; + err = sh_css_create_isp_params(stream, + &stream->isp_params_configs); + if (err) + goto ERR; + + params = stream->isp_params_configs; + if (!sh_css_init_isp_params_from_global(stream, params, true, NULL)) { + /* we do not return the error immediately to enable internal + * firmware feature testing */ + err = -EINVAL; + } + + ddr_ptrs = ¶ms->ddr_ptrs; + ddr_ptrs_size = ¶ms->ddr_ptrs_size; + + /* create per pipe reference to general ddr_ptrs */ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + ref_sh_css_ddr_address_map(ddr_ptrs, ¶ms->pipe_ddr_ptrs[i]); + params->pipe_ddr_ptrs_size[i] = *ddr_ptrs_size; + } + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static void +ia_css_set_sdis_config( + struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *dvs_coefs) +{ + ia_css_set_sdis_horicoef_config(params, dvs_coefs); + ia_css_set_sdis_vertcoef_config(params, dvs_coefs); + ia_css_set_sdis_horiproj_config(params, dvs_coefs); + ia_css_set_sdis_vertproj_config(params, dvs_coefs); +} + +static void +ia_css_set_sdis2_config( + struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *dvs2_coefs) +{ + ia_css_set_sdis2_horicoef_config(params, dvs2_coefs); + ia_css_set_sdis2_vertcoef_config(params, dvs2_coefs); + ia_css_set_sdis2_horiproj_config(params, dvs2_coefs); + ia_css_set_sdis2_vertproj_config(params, dvs2_coefs); +} + +static int +sh_css_create_isp_params(struct ia_css_stream *stream, + struct ia_css_isp_parameters **isp_params_out) +{ + bool succ = true; + unsigned int i; + struct sh_css_ddr_address_map *ddr_ptrs; + struct sh_css_ddr_address_map_size *ddr_ptrs_size; + int err; + size_t params_size; + struct ia_css_isp_parameters *params = + kvmalloc(sizeof(struct ia_css_isp_parameters), GFP_KERNEL); + + if (!params) { + *isp_params_out = NULL; + err = -ENOMEM; + IA_CSS_ERROR("%s:%d error: cannot allocate memory", __FILE__, __LINE__); + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } else { + memset(params, 0, sizeof(struct ia_css_isp_parameters)); + } + + ddr_ptrs = ¶ms->ddr_ptrs; + ddr_ptrs_size = ¶ms->ddr_ptrs_size; + + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + memset(¶ms->pipe_ddr_ptrs[i], 0, + sizeof(params->pipe_ddr_ptrs[i])); + memset(¶ms->pipe_ddr_ptrs_size[i], 0, + sizeof(params->pipe_ddr_ptrs_size[i])); + } + + memset(ddr_ptrs, 0, sizeof(*ddr_ptrs)); + memset(ddr_ptrs_size, 0, sizeof(*ddr_ptrs_size)); + + params_size = sizeof(params->uds); + ddr_ptrs_size->isp_param = params_size; + ddr_ptrs->isp_param = + ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER, + hmm_alloc(params_size)); + succ &= (ddr_ptrs->isp_param != mmgr_NULL); + + ddr_ptrs_size->macc_tbl = sizeof(struct ia_css_macc_table); + ddr_ptrs->macc_tbl = + ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER, + hmm_alloc(sizeof(struct ia_css_macc_table))); + succ &= (ddr_ptrs->macc_tbl != mmgr_NULL); + + *isp_params_out = params; + + if (!succ) + return -ENOMEM; + + return 0; +} + +static bool +sh_css_init_isp_params_from_global(struct ia_css_stream *stream, + struct ia_css_isp_parameters *params, + bool use_default_config, + struct ia_css_pipe *pipe_in) +{ + bool retval = true; + int i = 0; + bool is_dp_10bpp = true; + unsigned int isp_pipe_version = ia_css_pipe_get_isp_pipe_version( + stream->pipes[0]); + struct ia_css_isp_parameters *stream_params = stream->isp_params_configs; + + if (!use_default_config && !stream_params) { + retval = false; + goto exit; + } + + params->output_frame = NULL; + params->isp_parameters_id = 0; + + if (use_default_config) { + ia_css_set_xnr3_config(params, &default_xnr3_config); + + sh_css_set_nr_config(params, &default_nr_config); + sh_css_set_ee_config(params, &default_ee_config); + if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1) + sh_css_set_macc_table(params, &default_macc_table); + else if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2) + sh_css_set_macc_table(params, &default_macc2_table); + sh_css_set_gamma_table(params, &default_gamma_table); + sh_css_set_ctc_table(params, &default_ctc_table); + sh_css_set_baa_config(params, &default_baa_config); + sh_css_set_dz_config(params, &default_dz_config); + /* ------ deprecated(bz675) : from ------ */ + sh_css_set_shading_settings(params, &default_shading_settings); + /* ------ deprecated(bz675) : to ------ */ + + ia_css_set_s3a_config(params, &default_3a_config); + ia_css_set_wb_config(params, &default_wb_config); + ia_css_set_csc_config(params, &default_cc_config); + ia_css_set_tnr_config(params, &default_tnr_config); + ia_css_set_ob_config(params, &default_ob_config); + ia_css_set_dp_config(params, &default_dp_config); + + ia_css_set_param_exceptions(pipe_in, params); + + ia_css_set_de_config(params, &default_de_config); + ia_css_set_gc_config(params, &default_gc_config); + ia_css_set_anr_config(params, &default_anr_config); + ia_css_set_anr2_config(params, &default_anr_thres); + ia_css_set_ce_config(params, &default_ce_config); + ia_css_set_xnr_table_config(params, &default_xnr_table); + ia_css_set_ecd_config(params, &default_ecd_config); + ia_css_set_ynr_config(params, &default_ynr_config); + ia_css_set_fc_config(params, &default_fc_config); + ia_css_set_cnr_config(params, &default_cnr_config); + ia_css_set_macc_config(params, &default_macc_config); + ia_css_set_ctc_config(params, &default_ctc_config); + ia_css_set_aa_config(params, &default_aa_config); + ia_css_set_r_gamma_config(params, &default_r_gamma_table); + ia_css_set_g_gamma_config(params, &default_g_gamma_table); + ia_css_set_b_gamma_config(params, &default_b_gamma_table); + ia_css_set_yuv2rgb_config(params, &default_yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, &default_rgb2yuv_cc_config); + ia_css_set_xnr_config(params, &default_xnr_config); + ia_css_set_sdis_config(params, &default_sdis_config); + ia_css_set_sdis2_config(params, &default_sdis2_config); + ia_css_set_formats_config(params, &default_formats_config); + + params->fpn_config.data = NULL; + params->config_changed[IA_CSS_FPN_ID] = true; + params->fpn_config.enabled = 0; + + params->motion_config = default_motion_config; + params->motion_config_changed = true; + + params->morph_table = NULL; + params->morph_table_changed = true; + + params->sc_table = NULL; + params->sc_table_changed = true; + + ia_css_sdis2_clear_coefficients(¶ms->dvs2_coefs); + params->dvs2_coef_table_changed = true; + + ia_css_sdis_clear_coefficients(¶ms->dvs_coefs); + params->dis_coef_table_changed = true; + } else { + ia_css_set_xnr3_config(params, &stream_params->xnr3_config); + + sh_css_set_nr_config(params, &stream_params->nr_config); + sh_css_set_ee_config(params, &stream_params->ee_config); + if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1) + sh_css_set_macc_table(params, &stream_params->macc_table); + else if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2) + sh_css_set_macc_table(params, &stream_params->macc_table); + sh_css_set_gamma_table(params, &stream_params->gc_table); + sh_css_set_ctc_table(params, &stream_params->ctc_table); + sh_css_set_baa_config(params, &stream_params->bds_config); + sh_css_set_dz_config(params, &stream_params->dz_config); + /* ------ deprecated(bz675) : from ------ */ + sh_css_set_shading_settings(params, &stream_params->shading_settings); + /* ------ deprecated(bz675) : to ------ */ + + ia_css_set_s3a_config(params, &stream_params->s3a_config); + ia_css_set_wb_config(params, &stream_params->wb_config); + ia_css_set_csc_config(params, &stream_params->cc_config); + ia_css_set_tnr_config(params, &stream_params->tnr_config); + ia_css_set_ob_config(params, &stream_params->ob_config); + ia_css_set_dp_config(params, &stream_params->dp_config); + ia_css_set_de_config(params, &stream_params->de_config); + ia_css_set_gc_config(params, &stream_params->gc_config); + ia_css_set_anr_config(params, &stream_params->anr_config); + ia_css_set_anr2_config(params, &stream_params->anr_thres); + ia_css_set_ce_config(params, &stream_params->ce_config); + ia_css_set_xnr_table_config(params, &stream_params->xnr_table); + ia_css_set_ecd_config(params, &stream_params->ecd_config); + ia_css_set_ynr_config(params, &stream_params->ynr_config); + ia_css_set_fc_config(params, &stream_params->fc_config); + ia_css_set_cnr_config(params, &stream_params->cnr_config); + ia_css_set_macc_config(params, &stream_params->macc_config); + ia_css_set_ctc_config(params, &stream_params->ctc_config); + ia_css_set_aa_config(params, &stream_params->aa_config); + ia_css_set_r_gamma_config(params, &stream_params->r_gamma_table); + ia_css_set_g_gamma_config(params, &stream_params->g_gamma_table); + ia_css_set_b_gamma_config(params, &stream_params->b_gamma_table); + ia_css_set_yuv2rgb_config(params, &stream_params->yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, &stream_params->rgb2yuv_cc_config); + ia_css_set_xnr_config(params, &stream_params->xnr_config); + ia_css_set_formats_config(params, &stream_params->formats_config); + + for (i = 0; i < stream->num_pipes; i++) { + if (0 == + sh_css_select_dp_10bpp_config(stream->pipes[i], &is_dp_10bpp)) { + /* set the return value as false if both DPC and + * BDS is enabled by the user. But we do not return + * the value immediately to enable internal firmware + * feature testing. */ + retval = !is_dp_10bpp; + /* FIXME: should it ignore this error? */ + } else { + retval = false; + goto exit; + } + } + + ia_css_set_param_exceptions(pipe_in, params); + + params->fpn_config.data = stream_params->fpn_config.data; + params->config_changed[IA_CSS_FPN_ID] = + stream_params->config_changed[IA_CSS_FPN_ID]; + params->fpn_config.enabled = stream_params->fpn_config.enabled; + + sh_css_set_motion_vector(params, &stream_params->motion_config); + sh_css_set_morph_table(params, stream_params->morph_table); + + if (stream_params->sc_table) { + sh_css_set_shading_table(stream, params, stream_params->sc_table); + } else { + params->sc_table = NULL; + params->sc_table_changed = true; + } + + /* Only IA_CSS_PIPE_ID_VIDEO & IA_CSS_PIPE_ID_CAPTURE will support dvs_6axis_config*/ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + if (stream_params->pipe_dvs_6axis_config[i]) { + if (params->pipe_dvs_6axis_config[i]) { + copy_dvs_6axis_table(params->pipe_dvs_6axis_config[i], + stream_params->pipe_dvs_6axis_config[i]); + } else { + params->pipe_dvs_6axis_config[i] = + generate_dvs_6axis_table_from_config(stream_params->pipe_dvs_6axis_config[i]); + } + } + } + ia_css_set_sdis_config(params, &stream_params->dvs_coefs); + params->dis_coef_table_changed = stream_params->dis_coef_table_changed; + + ia_css_set_sdis2_config(params, &stream_params->dvs2_coefs); + params->dvs2_coef_table_changed = stream_params->dvs2_coef_table_changed; + params->sensor_binning = stream_params->sensor_binning; + } + +exit: + return retval; +} + +int +sh_css_params_init(void) +{ + int i, p; + + IA_CSS_ENTER_PRIVATE("void"); + + /* TMP: tracking of paramsets */ + g_param_buffer_dequeue_count = 0; + g_param_buffer_enqueue_count = 0; + + for (p = 0; p < IA_CSS_PIPE_ID_NUM; p++) { + for (i = 0; i < SH_CSS_MAX_STAGES; i++) { + xmem_sp_stage_ptrs[p][i] = + ia_css_refcount_increment(-1, + hmm_alloc(sizeof(struct sh_css_sp_stage))); + xmem_isp_stage_ptrs[p][i] = + ia_css_refcount_increment(-1, + hmm_alloc(sizeof(struct sh_css_sp_stage))); + + if ((xmem_sp_stage_ptrs[p][i] == mmgr_NULL) || + (xmem_isp_stage_ptrs[p][i] == mmgr_NULL)) { + sh_css_params_uninit(); + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + + hmm_set(xmem_sp_stage_ptrs[p][i], 0, sizeof(struct sh_css_sp_stage)); + hmm_set(xmem_isp_stage_ptrs[p][i], 0, sizeof(struct sh_css_sp_stage)); + } + } + + ia_css_config_gamma_table(); + ia_css_config_ctc_table(); + ia_css_config_rgb_gamma_tables(); + ia_css_config_xnr_table(); + + sp_ddr_ptrs = ia_css_refcount_increment(-1, + hmm_alloc(CEIL_MUL(sizeof(struct sh_css_ddr_address_map), + HIVE_ISP_DDR_WORD_BYTES))); + xmem_sp_group_ptrs = ia_css_refcount_increment(-1, + hmm_alloc(sizeof(struct sh_css_sp_group))); + + if ((sp_ddr_ptrs == mmgr_NULL) || + (xmem_sp_group_ptrs == mmgr_NULL)) { + ia_css_uninit(); + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + hmm_set(sp_ddr_ptrs, 0, CEIL_MUL(sizeof(struct sh_css_ddr_address_map), + HIVE_ISP_DDR_WORD_BYTES)); + hmm_set(xmem_sp_group_ptrs, 0, sizeof(struct sh_css_sp_group)); + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +static void host_lut_store(const void *lut) +{ + unsigned int i; + + for (i = 0; i < N_GDC_ID; i++) + gdc_lut_store((gdc_ID_t)i, (const int (*)[HRT_GDC_N]) lut); +} + +int ia_css_pipe_set_bci_scaler_lut(struct ia_css_pipe *pipe, + const void *lut) +{ + int err = 0; + bool stream_started = false; + + IA_CSS_ENTER("pipe=%p lut=%p", pipe, lut); + + if (!lut || !pipe) { + err = -EINVAL; + IA_CSS_LEAVE("err=%d", err); + return err; + } + + /* If the pipe belongs to a stream and the stream has started, it is not + * safe to store lut to gdc HW. If pipe->stream is NULL, then no stream is + * created with this pipe, so it is safe to do this operation as long as + * ia_css_init() has been called. */ + if (pipe->stream && pipe->stream->started) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "unable to set scaler lut since stream has started\n"); + stream_started = true; + err = -ENOTSUPP; + } + + /* Free any existing tables. */ + if (pipe->scaler_pp_lut != mmgr_NULL) { + hmm_free(pipe->scaler_pp_lut); + pipe->scaler_pp_lut = mmgr_NULL; + } + + if (!stream_started) { + pipe->scaler_pp_lut = hmm_alloc(sizeof(zoom_table)); + + if (pipe->scaler_pp_lut == mmgr_NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "unable to allocate scaler_pp_lut\n"); + err = -ENOMEM; + } else { + gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])lut, + interleaved_lut_temp); + hmm_store(pipe->scaler_pp_lut, + (int *)interleaved_lut_temp, + sizeof(zoom_table)); + } + } + + IA_CSS_LEAVE("lut(%u) err=%d", pipe->scaler_pp_lut, err); + return err; +} + +/* if pipe is NULL, returns default lut addr. */ +ia_css_ptr sh_css_pipe_get_pp_gdc_lut(const struct ia_css_pipe *pipe) +{ + assert(pipe); + + if (pipe->scaler_pp_lut != mmgr_NULL) + return pipe->scaler_pp_lut; + else + return sh_css_params_get_default_gdc_lut(); +} + +int sh_css_params_map_and_store_default_gdc_lut(void) +{ + int err = 0; + + IA_CSS_ENTER_PRIVATE("void"); + + /* Is table already mapped? Nothing to do if it is mapped. */ + if (default_gdc_lut != mmgr_NULL) + return err; + + host_lut_store((void *)zoom_table); + + default_gdc_lut = hmm_alloc(sizeof(zoom_table)); + + if (default_gdc_lut == mmgr_NULL) + return -ENOMEM; + + gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])zoom_table, + interleaved_lut_temp); + hmm_store(default_gdc_lut, (int *)interleaved_lut_temp, + sizeof(zoom_table)); + + IA_CSS_LEAVE_PRIVATE("lut(%u) err=%d", default_gdc_lut, err); + return err; +} + +void sh_css_params_free_default_gdc_lut(void) +{ + IA_CSS_ENTER_PRIVATE("void"); + + if (default_gdc_lut != mmgr_NULL) { + hmm_free(default_gdc_lut); + default_gdc_lut = mmgr_NULL; + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +ia_css_ptr sh_css_params_get_default_gdc_lut(void) +{ + return default_gdc_lut; +} + +static void free_param_set_callback( + ia_css_ptr ptr) +{ + IA_CSS_ENTER_PRIVATE("void"); + + free_ia_css_isp_parameter_set_info(ptr); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void free_buffer_callback( + ia_css_ptr ptr) +{ + IA_CSS_ENTER_PRIVATE("void"); + + hmm_free(ptr); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +sh_css_param_clear_param_sets(void) +{ + IA_CSS_ENTER_PRIVATE("void"); + + ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_SET_POOL, &free_param_set_callback); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +/* + * MW: we can define hmm_free() to return a NULL + * then you can write ptr = hmm_free(ptr); + */ +#define safe_free(id, x) \ + do { \ + ia_css_refcount_decrement(id, x); \ + (x) = mmgr_NULL; \ + } while (0) + +static void free_map(struct sh_css_ddr_address_map *map) +{ + unsigned int i; + + ia_css_ptr *addrs = (ia_css_ptr *)map; + + IA_CSS_ENTER_PRIVATE("void"); + + /* free buffers */ + for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size) / + sizeof(size_t)); i++) { + if (addrs[i] == mmgr_NULL) + continue; + safe_free(IA_CSS_REFCOUNT_PARAM_BUFFER, addrs[i]); + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +ia_css_stream_isp_parameters_uninit(struct ia_css_stream *stream) +{ + int i; + struct ia_css_isp_parameters *params = stream->isp_params_configs; + struct ia_css_isp_parameters *per_frame_params = + stream->per_frame_isp_params_configs; + + IA_CSS_ENTER_PRIVATE("void"); + if (!params) { + IA_CSS_LEAVE_PRIVATE("isp_param_configs is NULL"); + return; + } + + /* free existing ddr_ptr maps */ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + free_map(¶ms->pipe_ddr_ptrs[i]); + if (per_frame_params) + free_map(&per_frame_params->pipe_ddr_ptrs[i]); + /* Free up theDVS table memory blocks before recomputing new table */ + if (params->pipe_dvs_6axis_config[i]) + free_dvs_6axis_table(¶ms->pipe_dvs_6axis_config[i]); + if (per_frame_params && per_frame_params->pipe_dvs_6axis_config[i]) + free_dvs_6axis_table(&per_frame_params->pipe_dvs_6axis_config[i]); + } + free_map(¶ms->ddr_ptrs); + if (per_frame_params) + free_map(&per_frame_params->ddr_ptrs); + + if (params->fpn_config.data) { + kvfree(params->fpn_config.data); + params->fpn_config.data = NULL; + } + + /* Free up sc_config (temporal shading table) if it is allocated. */ + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + if (per_frame_params) { + if (per_frame_params->sc_config) { + ia_css_shading_table_free(per_frame_params->sc_config); + per_frame_params->sc_config = NULL; + } + } + + kvfree(params); + kvfree(per_frame_params); + stream->isp_params_configs = NULL; + stream->per_frame_isp_params_configs = NULL; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +sh_css_params_uninit(void) +{ + unsigned int p, i; + + IA_CSS_ENTER_PRIVATE("void"); + + ia_css_refcount_decrement(-1, sp_ddr_ptrs); + sp_ddr_ptrs = mmgr_NULL; + ia_css_refcount_decrement(-1, xmem_sp_group_ptrs); + xmem_sp_group_ptrs = mmgr_NULL; + + for (p = 0; p < IA_CSS_PIPE_ID_NUM; p++) + for (i = 0; i < SH_CSS_MAX_STAGES; i++) { + ia_css_refcount_decrement(-1, xmem_sp_stage_ptrs[p][i]); + xmem_sp_stage_ptrs[p][i] = mmgr_NULL; + ia_css_refcount_decrement(-1, xmem_isp_stage_ptrs[p][i]); + xmem_isp_stage_ptrs[p][i] = mmgr_NULL; + } + + /* go through the pools to clear references */ + ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_SET_POOL, &free_param_set_callback); + ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_BUFFER, &free_buffer_callback); + ia_css_refcount_clear(-1, &free_buffer_callback); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static struct ia_css_host_data * +convert_allocate_morph_plane( + unsigned short *data, + unsigned int width, + unsigned int height, + unsigned int aligned_width) +{ + unsigned int i, j, padding, w; + struct ia_css_host_data *me; + unsigned int isp_data_size; + u16 *isp_data_ptr; + + IA_CSS_ENTER_PRIVATE("void"); + + /* currently we don't have morph table interpolation yet, + * so we allow a wider table to be used. This will be removed + * in the future. */ + if (width > aligned_width) { + padding = 0; + w = aligned_width; + } else { + padding = aligned_width - width; + w = width; + } + isp_data_size = height * (w + padding) * sizeof(uint16_t); + + me = ia_css_host_data_allocate((size_t)isp_data_size); + + if (!me) { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return NULL; + } + + isp_data_ptr = (uint16_t *)me->address; + + memset(isp_data_ptr, 0, (size_t)isp_data_size); + + for (i = 0; i < height; i++) { + for (j = 0; j < w; j++) + *isp_data_ptr++ = (uint16_t)data[j]; + isp_data_ptr += padding; + data += width; + } + + IA_CSS_LEAVE_PRIVATE("void"); + return me; +} + +static int +store_morph_plane( + unsigned short *data, + unsigned int width, + unsigned int height, + ia_css_ptr dest, + unsigned int aligned_width) +{ + struct ia_css_host_data *isp_data; + + assert(dest != mmgr_NULL); + + isp_data = convert_allocate_morph_plane(data, width, height, aligned_width); + if (!isp_data) { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + ia_css_params_store_ia_css_host_data(dest, isp_data); + + ia_css_host_data_free(isp_data); + return 0; +} + +static void sh_css_update_isp_params_to_ddr( + struct ia_css_isp_parameters *params, + ia_css_ptr ddr_ptr) +{ + size_t size = sizeof(params->uds); + + IA_CSS_ENTER_PRIVATE("void"); + + assert(params); + + hmm_store(ddr_ptr, ¶ms->uds, size); + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void sh_css_update_isp_mem_params_to_ddr( + const struct ia_css_binary *binary, + ia_css_ptr ddr_mem_ptr, + size_t size, + enum ia_css_isp_memories mem) +{ + const struct ia_css_host_data *params; + + IA_CSS_ENTER_PRIVATE("void"); + + params = ia_css_isp_param_get_mem_init(&binary->mem_params, + IA_CSS_PARAM_CLASS_PARAM, mem); + hmm_store(ddr_mem_ptr, params->address, size); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void ia_css_dequeue_param_buffers(/*unsigned int pipe_num*/ void) +{ + unsigned int i; + ia_css_ptr cpy; + enum sh_css_queue_id param_queue_ids[3] = { IA_CSS_PARAMETER_SET_QUEUE_ID, + IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID, + SH_CSS_INVALID_QUEUE_ID + }; + + IA_CSS_ENTER_PRIVATE("void"); + + if (!sh_css_sp_is_running()) { + IA_CSS_LEAVE_PRIVATE("sp is not running"); + /* SP is not running. The queues are not valid */ + return; + } + + for (i = 0; SH_CSS_INVALID_QUEUE_ID != param_queue_ids[i]; i++) { + cpy = (ia_css_ptr)0; + /* clean-up old copy */ + while (ia_css_bufq_dequeue_buffer(param_queue_ids[i], + (uint32_t *)&cpy) == 0) { + /* TMP: keep track of dequeued param set count + */ + g_param_buffer_dequeue_count++; + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_BUFFER_DEQUEUED, + 0, + param_queue_ids[i], + 0); + + IA_CSS_LOG("dequeued param set %x from %d, release ref", cpy, 0); + free_ia_css_isp_parameter_set_info(cpy); + cpy = (ia_css_ptr)0; + } + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +process_kernel_parameters(unsigned int pipe_id, + struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params, + unsigned int isp_pipe_version, + unsigned int raw_bit_depth) +{ + unsigned int param_id; + + (void)isp_pipe_version; + (void)raw_bit_depth; + + sh_css_enable_pipeline(stage->binary); + + if (params->config_changed[IA_CSS_OB_ID]) { + ia_css_ob_configure(¶ms->stream_configs.ob, + isp_pipe_version, raw_bit_depth); + } + if (params->config_changed[IA_CSS_S3A_ID]) { + ia_css_s3a_configure(raw_bit_depth); + } + /* Copy stage uds parameters to config, since they can differ per stage. + */ + params->crop_config.crop_pos = params->uds[stage->stage_num].crop_pos; + params->uds_config.crop_pos = params->uds[stage->stage_num].crop_pos; + params->uds_config.uds = params->uds[stage->stage_num].uds; + /* Call parameter process functions for all kernels */ + /* Skip SC, since that is called on a temp sc table */ + for (param_id = 0; param_id < IA_CSS_NUM_PARAMETER_IDS; param_id++) { + if (param_id == IA_CSS_SC_ID) continue; + if (params->config_changed[param_id]) + ia_css_kernel_process_param[param_id](pipe_id, stage, params); + } +} + +int +sh_css_param_update_isp_params(struct ia_css_pipe *curr_pipe, + struct ia_css_isp_parameters *params, + bool commit, + struct ia_css_pipe *pipe_in) +{ + int err = 0; + ia_css_ptr cpy; + int i; + unsigned int raw_bit_depth = 10; + unsigned int isp_pipe_version = SH_CSS_ISP_PIPE_VERSION_1; + bool acc_cluster_params_changed = false; + unsigned int thread_id, pipe_num; + + (void)acc_cluster_params_changed; + + assert(curr_pipe); + + IA_CSS_ENTER_PRIVATE("pipe=%p, isp_parameters_id=%d", pipe_in, params->isp_parameters_id); + raw_bit_depth = ia_css_stream_input_format_bits_per_pixel(curr_pipe->stream); + + /* now make the map available to the sp */ + if (!commit) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* enqueue a copies of the mem_map to + the designated pipelines */ + for (i = 0; i < curr_pipe->stream->num_pipes; i++) { + struct ia_css_pipe *pipe; + struct sh_css_ddr_address_map *cur_map; + struct sh_css_ddr_address_map_size *cur_map_size; + struct ia_css_isp_parameter_set_info isp_params_info; + struct ia_css_pipeline *pipeline; + struct ia_css_pipeline_stage *stage; + + enum sh_css_queue_id queue_id; + + pipe = curr_pipe->stream->pipes[i]; + pipeline = ia_css_pipe_get_pipeline(pipe); + pipe_num = ia_css_pipe_get_pipe_num(pipe); + isp_pipe_version = ia_css_pipe_get_isp_pipe_version(pipe); + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + + ia_css_query_internal_queue_id(params->output_frame + ? IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET + : IA_CSS_BUFFER_TYPE_PARAMETER_SET, + thread_id, &queue_id); + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + err = -EBUSY; + break; + } + cur_map = ¶ms->pipe_ddr_ptrs[pipeline->pipe_id]; + cur_map_size = ¶ms->pipe_ddr_ptrs_size[pipeline->pipe_id]; + + /* TODO: Normally, zoom and motion parameters shouldn't + * be part of "isp_params" as it is resolution/pipe dependent + * Therefore, move the zoom config elsewhere (e.g. shading + * table can be taken as an example! @GC + * */ + { + /* we have to do this per pipeline because */ + /* the processing is a.o. resolution dependent */ + err = ia_css_process_zoom_and_motion(params, + pipeline->stages); + if (err) + return err; + } + /* check if to actually update the parameters for this pipe */ + /* When API change is implemented making good distinction between + * stream config and pipe config this skipping code can be moved out of the #ifdef */ + if (pipe_in && (pipe != pipe_in)) { + IA_CSS_LOG("skipping pipe %p", pipe); + continue; + } + + /* BZ 125915, should be moved till after "update other buff" */ + /* update the other buffers to the pipe specific copies */ + for (stage = pipeline->stages; stage; stage = stage->next) { + unsigned int mem; + + if (!stage || !stage->binary) + continue; + + process_kernel_parameters(pipeline->pipe_id, + stage, params, + isp_pipe_version, raw_bit_depth); + + err = sh_css_params_write_to_ddr_internal( + pipe, + pipeline->pipe_id, + params, + stage, + cur_map, + cur_map_size); + + if (err) + break; + for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) { + params->isp_mem_params_changed + [pipeline->pipe_id][stage->stage_num][mem] = false; + } + } /* for */ + if (err) + break; + /* update isp_params to pipe specific copies */ + if (params->isp_params_changed) { + reallocate_buffer(&cur_map->isp_param, + &cur_map_size->isp_param, + cur_map_size->isp_param, + true, + &err); + if (err) + break; + sh_css_update_isp_params_to_ddr(params, cur_map->isp_param); + } + + /* last make referenced copy */ + err = ref_sh_css_ddr_address_map( + cur_map, + &isp_params_info.mem_map); + if (err) + break; + + /* Update Parameters ID */ + isp_params_info.isp_parameters_id = params->isp_parameters_id; + + /* Update output frame pointer */ + isp_params_info.output_frame_ptr = + (params->output_frame) ? params->output_frame->data : mmgr_NULL; + + /* now write the copy to ddr */ + err = write_ia_css_isp_parameter_set_info_to_ddr(&isp_params_info, &cpy); + if (err) + break; + + /* enqueue the set to sp */ + IA_CSS_LOG("queue param set %x to %d", cpy, thread_id); + + err = ia_css_bufq_enqueue_buffer(thread_id, queue_id, (uint32_t)cpy); + if (err) { + free_ia_css_isp_parameter_set_info(cpy); + IA_CSS_LOG("pfp: FAILED to add config id %d for OF %d to q %d on thread %d", + isp_params_info.isp_parameters_id, + isp_params_info.output_frame_ptr, + queue_id, thread_id); + break; + } else { + /* TMP: check discrepancy between nr of enqueued + * parameter sets and dequeued sets + */ + g_param_buffer_enqueue_count++; + assert(g_param_buffer_enqueue_count < g_param_buffer_dequeue_count + 50); + /* + * Tell the SP which queues are not empty, + * by sending the software event. + */ + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + IA_CSS_LEAVE_ERR_PRIVATE(-EBUSY); + return -EBUSY; + } + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_BUFFER_ENQUEUED, + (uint8_t)thread_id, + (uint8_t)queue_id, + 0); + IA_CSS_LOG("pfp: added config id %d for OF %d to q %d on thread %d", + isp_params_info.isp_parameters_id, + isp_params_info.output_frame_ptr, + queue_id, thread_id); + } + /* clean-up old copy */ + ia_css_dequeue_param_buffers(/*pipe_num*/); + params->pipe_dvs_6axis_config_changed[pipeline->pipe_id] = false; + } /* end for each 'active' pipeline */ + /* clear the changed flags after all params + for all pipelines have been updated */ + params->isp_params_changed = false; + params->sc_table_changed = false; + params->dis_coef_table_changed = false; + params->dvs2_coef_table_changed = false; + params->morph_table_changed = false; + params->dz_config_changed = false; + params->motion_config_changed = false; + /* ------ deprecated(bz675) : from ------ */ + params->shading_settings_changed = false; + /* ------ deprecated(bz675) : to ------ */ + + memset(¶ms->config_changed[0], 0, sizeof(params->config_changed)); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int +sh_css_params_write_to_ddr_internal( + struct ia_css_pipe *pipe, + unsigned int pipe_id, + struct ia_css_isp_parameters *params, + const struct ia_css_pipeline_stage *stage, + struct sh_css_ddr_address_map *ddr_map, + struct sh_css_ddr_address_map_size *ddr_map_size) +{ + int err; + const struct ia_css_binary *binary; + + unsigned int stage_num; + unsigned int mem; + bool buff_realloced; + + /* struct is > 128 bytes so it should not be on stack (see checkpatch) */ + static struct ia_css_macc_table converted_macc_table; + + IA_CSS_ENTER_PRIVATE("void"); + assert(params); + assert(ddr_map); + assert(ddr_map_size); + assert(stage); + + binary = stage->binary; + assert(binary); + + stage_num = stage->stage_num; + + if (binary->info->sp.enable.fpnr) { + buff_realloced = reallocate_buffer(&ddr_map->fpn_tbl, + &ddr_map_size->fpn_tbl, + (size_t)(FPNTBL_BYTES(binary)), + params->config_changed[IA_CSS_FPN_ID], + &err); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (params->config_changed[IA_CSS_FPN_ID] || buff_realloced) { + if (params->fpn_config.enabled) { + err = store_fpntbl(params, ddr_map->fpn_tbl); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + } + } + + if (binary->info->sp.enable.sc) { + u32 enable_conv; + + enable_conv = params->shading_settings.enable_shading_table_conversion; + + buff_realloced = reallocate_buffer(&ddr_map->sc_tbl, + &ddr_map_size->sc_tbl, + SCTBL_BYTES(binary), + params->sc_table_changed, + &err); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (params->shading_settings_changed || + params->sc_table_changed || buff_realloced) { + if (enable_conv == 0) { + if (params->sc_table) { + /* store the shading table to ddr */ + err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_table); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* set sc_config to isp */ + params->sc_config = (struct ia_css_shading_table *)params->sc_table; + ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params); + params->sc_config = NULL; + } else { + /* generate the identical shading table */ + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + sh_css_params_shading_id_table_generate(¶ms->sc_config, + binary->sctbl_width_per_color, + binary->sctbl_height); + if (!params->sc_config) { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + + /* store the shading table to ddr */ + err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_config); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + /* set sc_config to isp */ + ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params); + + /* free the shading table */ + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + } else { /* legacy */ + /* ------ deprecated(bz675) : from ------ */ + /* shading table is full resolution, reduce */ + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + prepare_shading_table( + (const struct ia_css_shading_table *)params->sc_table, + params->sensor_binning, + ¶ms->sc_config, + binary, pipe->required_bds_factor); + if (!params->sc_config) { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + + /* store the shading table to ddr */ + err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_config); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + /* set sc_config to isp */ + ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params); + + /* free the shading table */ + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + /* ------ deprecated(bz675) : to ------ */ + } + } + } + + if (params->config_changed[IA_CSS_MACC_ID] && binary->info->sp.enable.macc) { + unsigned int i, j, idx; + static const unsigned int idx_map[] = { + 0, 1, 3, 2, 6, 7, 5, 4, 12, 13, 15, 14, 10, 11, 9, 8 + }; + + for (i = 0; i < IA_CSS_MACC_NUM_AXES; i++) { + idx = 4 * idx_map[i]; + j = 4 * i; + + if (binary->info->sp.pipeline.isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1) { + converted_macc_table.data[idx] = + (int16_t)sDIGIT_FITTING(params->macc_table.data[j], + 13, SH_CSS_MACC_COEF_SHIFT); + converted_macc_table.data[idx + 1] = + (int16_t)sDIGIT_FITTING(params->macc_table.data[j + 1], + 13, SH_CSS_MACC_COEF_SHIFT); + converted_macc_table.data[idx + 2] = + (int16_t)sDIGIT_FITTING(params->macc_table.data[j + 2], + 13, SH_CSS_MACC_COEF_SHIFT); + converted_macc_table.data[idx + 3] = + (int16_t)sDIGIT_FITTING(params->macc_table.data[j + 3], + 13, SH_CSS_MACC_COEF_SHIFT); + } else if (binary->info->sp.pipeline.isp_pipe_version == + SH_CSS_ISP_PIPE_VERSION_2_2) { + converted_macc_table.data[idx] = + params->macc_table.data[j]; + converted_macc_table.data[idx + 1] = + params->macc_table.data[j + 1]; + converted_macc_table.data[idx + 2] = + params->macc_table.data[j + 2]; + converted_macc_table.data[idx + 3] = + params->macc_table.data[j + 3]; + } + } + reallocate_buffer(&ddr_map->macc_tbl, + &ddr_map_size->macc_tbl, + ddr_map_size->macc_tbl, + true, + &err); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + hmm_store(ddr_map->macc_tbl, + converted_macc_table.data, + sizeof(converted_macc_table.data)); + } + + if (binary->info->sp.enable.dvs_6axis) { + /* because UV is packed into the Y plane, calc total + * YYU size = /2 gives size of UV-only, + * total YYU size = UV-only * 3. + */ + buff_realloced = reallocate_buffer( + &ddr_map->dvs_6axis_params_y, + &ddr_map_size->dvs_6axis_params_y, + (size_t)((DVS_6AXIS_BYTES(binary) / 2) * 3), + params->pipe_dvs_6axis_config_changed[pipe_id], + &err); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (params->pipe_dvs_6axis_config_changed[pipe_id] || buff_realloced) { + const struct ia_css_frame_info *dvs_in_frame_info; + + if (stage->args.delay_frames[0]) { + /*When delay frames are present(as in case of video), + they are used for dvs. Configure DVS using those params*/ + dvs_in_frame_info = &stage->args.delay_frames[0]->frame_info; + } else { + /*Otherwise, use input frame to configure DVS*/ + dvs_in_frame_info = &stage->args.in_frame->frame_info; + } + + /* Generate default DVS unity table on start up*/ + if (!params->pipe_dvs_6axis_config[pipe_id]) { + struct ia_css_resolution dvs_offset = {0}; + + dvs_offset.width = (PIX_SHIFT_FILTER_RUN_IN_X + binary->dvs_envelope.width) / 2; + dvs_offset.height = (PIX_SHIFT_FILTER_RUN_IN_Y + binary->dvs_envelope.height) / 2; + + params->pipe_dvs_6axis_config[pipe_id] = + generate_dvs_6axis_table(&binary->out_frame_info[0].res, &dvs_offset); + if (!params->pipe_dvs_6axis_config[pipe_id]) { + IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM); + return -ENOMEM; + } + params->pipe_dvs_6axis_config_changed[pipe_id] = true; + + store_dvs_6axis_config(params->pipe_dvs_6axis_config[pipe_id], + binary, + dvs_in_frame_info, + ddr_map->dvs_6axis_params_y); + params->isp_params_changed = true; + } + } + } + + if (binary->info->sp.enable.ca_gdc) { + unsigned int i; + ia_css_ptr *virt_addr_tetra_x[ + + IA_CSS_MORPH_TABLE_NUM_PLANES]; + size_t *virt_size_tetra_x[ + + IA_CSS_MORPH_TABLE_NUM_PLANES]; + ia_css_ptr *virt_addr_tetra_y[ + + IA_CSS_MORPH_TABLE_NUM_PLANES]; + size_t *virt_size_tetra_y[ + + IA_CSS_MORPH_TABLE_NUM_PLANES]; + + virt_addr_tetra_x[0] = &ddr_map->tetra_r_x; + virt_addr_tetra_x[1] = &ddr_map->tetra_gr_x; + virt_addr_tetra_x[2] = &ddr_map->tetra_gb_x; + virt_addr_tetra_x[3] = &ddr_map->tetra_b_x; + virt_addr_tetra_x[4] = &ddr_map->tetra_ratb_x; + virt_addr_tetra_x[5] = &ddr_map->tetra_batr_x; + + virt_size_tetra_x[0] = &ddr_map_size->tetra_r_x; + virt_size_tetra_x[1] = &ddr_map_size->tetra_gr_x; + virt_size_tetra_x[2] = &ddr_map_size->tetra_gb_x; + virt_size_tetra_x[3] = &ddr_map_size->tetra_b_x; + virt_size_tetra_x[4] = &ddr_map_size->tetra_ratb_x; + virt_size_tetra_x[5] = &ddr_map_size->tetra_batr_x; + + virt_addr_tetra_y[0] = &ddr_map->tetra_r_y; + virt_addr_tetra_y[1] = &ddr_map->tetra_gr_y; + virt_addr_tetra_y[2] = &ddr_map->tetra_gb_y; + virt_addr_tetra_y[3] = &ddr_map->tetra_b_y; + virt_addr_tetra_y[4] = &ddr_map->tetra_ratb_y; + virt_addr_tetra_y[5] = &ddr_map->tetra_batr_y; + + virt_size_tetra_y[0] = &ddr_map_size->tetra_r_y; + virt_size_tetra_y[1] = &ddr_map_size->tetra_gr_y; + virt_size_tetra_y[2] = &ddr_map_size->tetra_gb_y; + virt_size_tetra_y[3] = &ddr_map_size->tetra_b_y; + virt_size_tetra_y[4] = &ddr_map_size->tetra_ratb_y; + virt_size_tetra_y[5] = &ddr_map_size->tetra_batr_y; + + buff_realloced = false; + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + buff_realloced |= + reallocate_buffer(virt_addr_tetra_x[i], + virt_size_tetra_x[i], + (size_t) + (MORPH_PLANE_BYTES(binary)), + params->morph_table_changed, + &err); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + buff_realloced |= + reallocate_buffer(virt_addr_tetra_y[i], + virt_size_tetra_y[i], + (size_t) + (MORPH_PLANE_BYTES(binary)), + params->morph_table_changed, + &err); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + if (params->morph_table_changed || buff_realloced) { + const struct ia_css_morph_table *table = params->morph_table; + struct ia_css_morph_table *id_table = NULL; + + if ((table) && + (table->width < binary->morph_tbl_width || + table->height < binary->morph_tbl_height)) { + table = NULL; + } + if (!table) { + err = sh_css_params_default_morph_table(&id_table, + binary); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + table = id_table; + } + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + store_morph_plane(table->coordinates_x[i], + table->width, + table->height, + *virt_addr_tetra_x[i], + binary->morph_tbl_aligned_width); + store_morph_plane(table->coordinates_y[i], + table->width, + table->height, + *virt_addr_tetra_y[i], + binary->morph_tbl_aligned_width); + } + if (id_table) + ia_css_morph_table_free(id_table); + } + } + + /* After special cases like SC, FPN since they may change parameters */ + for (mem = 0; mem < N_IA_CSS_MEMORIES; mem++) { + const struct ia_css_isp_data *isp_data = + ia_css_isp_param_get_isp_mem_init(&binary->info->sp.mem_initializers, + IA_CSS_PARAM_CLASS_PARAM, mem); + size_t size = isp_data->size; + + if (!size) continue; + buff_realloced = reallocate_buffer(&ddr_map->isp_mem_param[stage_num][mem], + &ddr_map_size->isp_mem_param[stage_num][mem], + size, + params->isp_mem_params_changed[pipe_id][stage_num][mem], + &err); + if (err) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (params->isp_mem_params_changed[pipe_id][stage_num][mem] || buff_realloced) { + sh_css_update_isp_mem_params_to_ddr(binary, + ddr_map->isp_mem_param[stage_num][mem], + ddr_map_size->isp_mem_param[stage_num][mem], mem); + } + } + + IA_CSS_LEAVE_ERR_PRIVATE(0); + return 0; +} + +const struct ia_css_fpn_table *ia_css_get_fpn_table(struct ia_css_stream + *stream) +{ + struct ia_css_isp_parameters *params; + + IA_CSS_ENTER_LEAVE("void"); + assert(stream); + + params = stream->isp_params_configs; + + return ¶ms->fpn_config; +} + +struct ia_css_shading_table *ia_css_get_shading_table(struct ia_css_stream + *stream) +{ + struct ia_css_shading_table *table = NULL; + struct ia_css_isp_parameters *params; + + IA_CSS_ENTER("void"); + + assert(stream); + + params = stream->isp_params_configs; + if (!params) + return NULL; + + if (params->shading_settings.enable_shading_table_conversion == 0) { + if (params->sc_table) { + table = (struct ia_css_shading_table *)params->sc_table; + } else { + const struct ia_css_binary *binary + = ia_css_stream_get_shading_correction_binary(stream); + if (binary) { + /* generate the identical shading table */ + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + sh_css_params_shading_id_table_generate(¶ms->sc_config, + binary->sctbl_width_per_color, + binary->sctbl_height); + table = params->sc_config; + /* The sc_config will be freed in the + * ia_css_stream_isp_parameters_uninit function. */ + } + } + } else { + /* ------ deprecated(bz675) : from ------ */ + const struct ia_css_binary *binary + = ia_css_stream_get_shading_correction_binary(stream); + struct ia_css_pipe *pipe; + + /**********************************************************************/ + /* following code is copied from function ia_css_stream_get_shading_correction_binary() + * to match with the binary */ + pipe = stream->pipes[0]; + + if (stream->num_pipes == 2) { + assert(stream->pipes[1]); + if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO || + stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW) + pipe = stream->pipes[1]; + } + /**********************************************************************/ + if (binary) { + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + prepare_shading_table( + (const struct ia_css_shading_table *)params->sc_table, + params->sensor_binning, + ¶ms->sc_config, + binary, pipe->required_bds_factor); + + table = params->sc_config; + /* The sc_config will be freed in the + * ia_css_stream_isp_parameters_uninit function. */ + } + /* ------ deprecated(bz675) : to ------ */ + } + + IA_CSS_LEAVE("table=%p", table); + + return table; +} + +ia_css_ptr sh_css_store_sp_group_to_ddr(void) +{ + IA_CSS_ENTER_LEAVE_PRIVATE("void"); + hmm_store(xmem_sp_group_ptrs, + &sh_css_sp_group, + sizeof(struct sh_css_sp_group)); + return xmem_sp_group_ptrs; +} + +ia_css_ptr sh_css_store_sp_stage_to_ddr( + unsigned int pipe, + unsigned int stage) +{ + IA_CSS_ENTER_LEAVE_PRIVATE("void"); + hmm_store(xmem_sp_stage_ptrs[pipe][stage], + &sh_css_sp_stage, + sizeof(struct sh_css_sp_stage)); + return xmem_sp_stage_ptrs[pipe][stage]; +} + +ia_css_ptr sh_css_store_isp_stage_to_ddr( + unsigned int pipe, + unsigned int stage) +{ + IA_CSS_ENTER_LEAVE_PRIVATE("void"); + hmm_store(xmem_isp_stage_ptrs[pipe][stage], + &sh_css_isp_stage, + sizeof(struct sh_css_isp_stage)); + return xmem_isp_stage_ptrs[pipe][stage]; +} + +static int ref_sh_css_ddr_address_map( + struct sh_css_ddr_address_map *map, + struct sh_css_ddr_address_map *out) +{ + int err = 0; + unsigned int i; + + /* we will use a union to copy things; overlaying an array + with the struct; that way adding fields in the struct + will keep things working, and we will not get type errors. + */ + union { + struct sh_css_ddr_address_map *map; + ia_css_ptr *addrs; + } in_addrs, to_addrs; + + IA_CSS_ENTER_PRIVATE("void"); + assert(map); + assert(out); + + in_addrs.map = map; + to_addrs.map = out; + + assert(sizeof(struct sh_css_ddr_address_map_size) / sizeof(size_t) == + sizeof(struct sh_css_ddr_address_map) / sizeof(ia_css_ptr)); + + /* copy map using size info */ + for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size) / + sizeof(size_t)); i++) { + if (in_addrs.addrs[i] == mmgr_NULL) + to_addrs.addrs[i] = mmgr_NULL; + else + to_addrs.addrs[i] = ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER, + in_addrs.addrs[i]); + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int write_ia_css_isp_parameter_set_info_to_ddr( + struct ia_css_isp_parameter_set_info *me, + ia_css_ptr *out) +{ + int err = 0; + bool succ; + + IA_CSS_ENTER_PRIVATE("void"); + + assert(me); + assert(out); + + *out = ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_SET_POOL, + hmm_alloc(sizeof(struct ia_css_isp_parameter_set_info))); + succ = (*out != mmgr_NULL); + if (succ) + hmm_store(*out, + me, sizeof(struct ia_css_isp_parameter_set_info)); + else + err = -ENOMEM; + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static int +free_ia_css_isp_parameter_set_info( + ia_css_ptr ptr) +{ + int err = 0; + struct ia_css_isp_parameter_set_info isp_params_info; + unsigned int i; + ia_css_ptr *addrs = (ia_css_ptr *)&isp_params_info.mem_map; + + IA_CSS_ENTER_PRIVATE("ptr = %u", ptr); + + /* sanity check - ptr must be valid */ + if (!ia_css_refcount_is_valid(ptr)) { + IA_CSS_ERROR("%s: IA_CSS_REFCOUNT_PARAM_SET_POOL(0x%x) invalid arg", __func__, + ptr); + err = -EINVAL; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + hmm_load(ptr, &isp_params_info.mem_map, sizeof(struct sh_css_ddr_address_map)); + /* copy map using size info */ + for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size) / + sizeof(size_t)); i++) { + if (addrs[i] == mmgr_NULL) + continue; + + /* sanity check - ptr must be valid */ + if (!ia_css_refcount_is_valid(addrs[i])) { + IA_CSS_ERROR("%s: IA_CSS_REFCOUNT_PARAM_BUFFER(0x%x) invalid arg", __func__, + ptr); + err = -EINVAL; + continue; + } + + ia_css_refcount_decrement(IA_CSS_REFCOUNT_PARAM_BUFFER, addrs[i]); + } + ia_css_refcount_decrement(IA_CSS_REFCOUNT_PARAM_SET_POOL, ptr); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* Mark all parameters as changed to force recomputing the derived ISP parameters */ +void +sh_css_invalidate_params(struct ia_css_stream *stream) +{ + struct ia_css_isp_parameters *params; + unsigned int i, j, mem; + + IA_CSS_ENTER_PRIVATE("void"); + assert(stream); + + params = stream->isp_params_configs; + params->isp_params_changed = true; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + for (j = 0; j < SH_CSS_MAX_STAGES; j++) { + for (mem = 0; mem < N_IA_CSS_MEMORIES; mem++) { + params->isp_mem_params_changed[i][j][mem] = true; + } + } + } + + memset(¶ms->config_changed[0], 1, sizeof(params->config_changed)); + params->dis_coef_table_changed = true; + params->dvs2_coef_table_changed = true; + params->morph_table_changed = true; + params->sc_table_changed = true; + params->dz_config_changed = true; + params->motion_config_changed = true; + + /*Free up theDVS table memory blocks before recomputing new table */ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + if (params->pipe_dvs_6axis_config[i]) { + free_dvs_6axis_table(¶ms->pipe_dvs_6axis_config[i]); + params->pipe_dvs_6axis_config_changed[i] = true; + } + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +sh_css_update_uds_and_crop_info( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *in_frame_info, + const struct ia_css_frame_info *out_frame_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_dz_config *zoom, + const struct ia_css_vector *motion_vector, + struct sh_css_uds_info *uds, /* out */ + struct sh_css_crop_pos *sp_out_crop_pos, /* out */ + + bool enable_zoom) +{ + IA_CSS_ENTER_PRIVATE("void"); + + assert(info); + assert(in_frame_info); + assert(out_frame_info); + assert(dvs_env); + assert(zoom); + assert(motion_vector); + assert(uds); + assert(sp_out_crop_pos); + + uds->curr_dx = enable_zoom ? (uint16_t)zoom->dx : HRT_GDC_N; + uds->curr_dy = enable_zoom ? (uint16_t)zoom->dy : HRT_GDC_N; + + if (info->enable.dvs_envelope) { + unsigned int crop_x = 0, + crop_y = 0, + uds_xc = 0, + uds_yc = 0, + env_width, env_height; + int half_env_x, half_env_y; + int motion_x = motion_vector->x; + int motion_y = motion_vector->y; + bool upscale_x = in_frame_info->res.width < out_frame_info->res.width; + bool upscale_y = in_frame_info->res.height < out_frame_info->res.height; + + if (info->enable.uds && !info->enable.ds) { + /** + * we calculate with the envelope that we can actually + * use, the min dvs envelope is for the filter + * initialization. + */ + env_width = dvs_env->width - + SH_CSS_MIN_DVS_ENVELOPE; + env_height = dvs_env->height - + SH_CSS_MIN_DVS_ENVELOPE; + half_env_x = env_width / 2; + half_env_y = env_height / 2; + /** + * for digital zoom, we use the dvs envelope and make + * sure that we don't include the 8 leftmost pixels or + * 8 topmost rows. + */ + if (upscale_x) { + uds_xc = (in_frame_info->res.width + + env_width + + SH_CSS_MIN_DVS_ENVELOPE) / 2; + } else { + uds_xc = (out_frame_info->res.width + + env_width) / 2 + + SH_CSS_MIN_DVS_ENVELOPE; + } + if (upscale_y) { + uds_yc = (in_frame_info->res.height + + env_height + + SH_CSS_MIN_DVS_ENVELOPE) / 2; + } else { + uds_yc = (out_frame_info->res.height + + env_height) / 2 + + SH_CSS_MIN_DVS_ENVELOPE; + } + /* clip the motion vector to +/- half the envelope */ + motion_x = clamp(motion_x, -half_env_x, half_env_x); + motion_y = clamp(motion_y, -half_env_y, half_env_y); + uds_xc += motion_x; + uds_yc += motion_y; + /* uds can be pipelined, remove top lines */ + crop_y = 2; + } else if (info->enable.ds) { + env_width = dvs_env->width; + env_height = dvs_env->height; + half_env_x = env_width / 2; + half_env_y = env_height / 2; + /* clip the motion vector to +/- half the envelope */ + motion_x = clamp(motion_x, -half_env_x, half_env_x); + motion_y = clamp(motion_y, -half_env_y, half_env_y); + /* for video with downscaling, the envelope is included + in the input resolution. */ + uds_xc = in_frame_info->res.width / 2 + motion_x; + uds_yc = in_frame_info->res.height / 2 + motion_y; + crop_x = info->pipeline.left_cropping; + /* ds == 2 (yuv_ds) can be pipelined, remove top + lines */ + if (info->enable.ds & 1) + crop_y = info->pipeline.top_cropping; + else + crop_y = 2; + } else { + /* video nodz: here we can only crop. We make sure we + crop at least the first 8x8 pixels away. */ + env_width = dvs_env->width - + SH_CSS_MIN_DVS_ENVELOPE; + env_height = dvs_env->height - + SH_CSS_MIN_DVS_ENVELOPE; + half_env_x = env_width / 2; + half_env_y = env_height / 2; + motion_x = clamp(motion_x, -half_env_x, half_env_x); + motion_y = clamp(motion_y, -half_env_y, half_env_y); + crop_x = SH_CSS_MIN_DVS_ENVELOPE + + half_env_x + motion_x; + crop_y = SH_CSS_MIN_DVS_ENVELOPE + + half_env_y + motion_y; + } + + /* Must enforce that the crop position is even */ + crop_x = EVEN_FLOOR(crop_x); + crop_y = EVEN_FLOOR(crop_y); + uds_xc = EVEN_FLOOR(uds_xc); + uds_yc = EVEN_FLOOR(uds_yc); + + uds->xc = (uint16_t)uds_xc; + uds->yc = (uint16_t)uds_yc; + sp_out_crop_pos->x = (uint16_t)crop_x; + sp_out_crop_pos->y = (uint16_t)crop_y; + } else { + /* for down scaling, we always use the center of the image */ + uds->xc = (uint16_t)in_frame_info->res.width / 2; + uds->yc = (uint16_t)in_frame_info->res.height / 2; + sp_out_crop_pos->x = (uint16_t)info->pipeline.left_cropping; + sp_out_crop_pos->y = (uint16_t)info->pipeline.top_cropping; + } + IA_CSS_LEAVE_PRIVATE("void"); +} + +static int +sh_css_update_uds_and_crop_info_based_on_zoom_region( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *in_frame_info, + const struct ia_css_frame_info *out_frame_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_dz_config *zoom, + const struct ia_css_vector *motion_vector, + struct sh_css_uds_info *uds, /* out */ + struct sh_css_crop_pos *sp_out_crop_pos, /* out */ + struct ia_css_resolution pipe_in_res, + bool enable_zoom) +{ + unsigned int x0 = 0, y0 = 0, x1 = 0, y1 = 0; + int err = 0; + /* Note: + * Filter_Envelope = 0 for NND/LUT + * Filter_Envelope = 1 for BCI + * Filter_Envelope = 3 for BLI + * Currently, not considering this filter envelope because, In uds.sp.c is recalculating + * the dx/dy based on filter envelope and other information (ia_css_uds_sp_scale_params) + * Ideally, That should be done on host side not on sp side. + */ + unsigned int filter_envelope = 0; + + IA_CSS_ENTER_PRIVATE("void"); + + assert(info); + assert(in_frame_info); + assert(out_frame_info); + assert(dvs_env); + assert(zoom); + assert(motion_vector); + assert(uds); + assert(sp_out_crop_pos); + x0 = zoom->zoom_region.origin.x; + y0 = zoom->zoom_region.origin.y; + x1 = zoom->zoom_region.resolution.width + x0; + y1 = zoom->zoom_region.resolution.height + y0; + + if ((x0 > x1) || (y0 > y1) || (x1 > pipe_in_res.width) || (y1 > pipe_in_res.height)) + return -EINVAL; + + if (!enable_zoom) { + uds->curr_dx = HRT_GDC_N; + uds->curr_dy = HRT_GDC_N; + } + + if (info->enable.dvs_envelope) { + /* Zoom region is only supported by the UDS module on ISP + * 2 and higher. It is not supported in video mode on ISP 1 */ + return -EINVAL; + } else { + if (enable_zoom) { + /* A. Calculate dx/dy based on crop region using in_frame_info + * Scale the crop region if in_frame_info to the stage is not same as + * actual effective input of the pipeline + */ + if (in_frame_info->res.width != pipe_in_res.width || + in_frame_info->res.height != pipe_in_res.height) { + x0 = (x0 * in_frame_info->res.width) / (pipe_in_res.width); + y0 = (y0 * in_frame_info->res.height) / (pipe_in_res.height); + x1 = (x1 * in_frame_info->res.width) / (pipe_in_res.width); + y1 = (y1 * in_frame_info->res.height) / (pipe_in_res.height); + } + uds->curr_dx = + ((x1 - x0 - filter_envelope) * HRT_GDC_N) / in_frame_info->res.width; + uds->curr_dy = + ((y1 - y0 - filter_envelope) * HRT_GDC_N) / in_frame_info->res.height; + + /* B. Calculate xc/yc based on crop region */ + uds->xc = (uint16_t)x0 + (((x1) - (x0)) / 2); + uds->yc = (uint16_t)y0 + (((y1) - (y0)) / 2); + } else { + uds->xc = (uint16_t)in_frame_info->res.width / 2; + uds->yc = (uint16_t)in_frame_info->res.height / 2; + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "uds->curr_dx=%d, uds->xc=%d, uds->yc=%d\n", + uds->curr_dx, uds->xc, uds->yc); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x0=%d, y0=%d, x1=%d, y1=%d\n", + x0, y0, x1, y1); + sp_out_crop_pos->x = (uint16_t)info->pipeline.left_cropping; + sp_out_crop_pos->y = (uint16_t)info->pipeline.top_cropping; + } + IA_CSS_LEAVE_PRIVATE("void"); + return err; +} + +struct ia_css_3a_statistics * +ia_css_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid) +{ + struct ia_css_3a_statistics *me; + int grid_size; + + IA_CSS_ENTER("grid=%p", grid); + + assert(grid); + + me = kvcalloc(1, sizeof(*me), GFP_KERNEL); + if (!me) + goto err; + + me->grid = *grid; + grid_size = grid->width * grid->height; + me->data = kvmalloc(grid_size * sizeof(*me->data), GFP_KERNEL); + if (!me->data) + goto err; + /* No weighted histogram, no structure, treat the histogram data as a byte dump in a byte array */ + me->rgby_data = kvmalloc(sizeof_hmem(HMEM0_ID), GFP_KERNEL); + + IA_CSS_LEAVE("return=%p", me); + return me; +err: + ia_css_3a_statistics_free(me); + + IA_CSS_LEAVE("return=%p", NULL); + return NULL; +} + +void +ia_css_3a_statistics_free(struct ia_css_3a_statistics *me) +{ + if (me) { + kvfree(me->rgby_data); + kvfree(me->data); + kvfree(me); + } +} + +struct ia_css_dvs_statistics * +ia_css_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_dvs_statistics *me; + + assert(grid); + + me = kvcalloc(1, sizeof(*me), GFP_KERNEL); + if (!me) + goto err; + + me->grid = *grid; + me->hor_proj = kvmalloc(grid->height * IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(*me->hor_proj), GFP_KERNEL); + if (!me->hor_proj) + goto err; + + me->ver_proj = kvmalloc(grid->width * IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(*me->ver_proj), GFP_KERNEL); + if (!me->ver_proj) + goto err; + + return me; +err: + ia_css_dvs_statistics_free(me); + return NULL; +} + +void +ia_css_dvs_statistics_free(struct ia_css_dvs_statistics *me) +{ + if (me) { + kvfree(me->hor_proj); + kvfree(me->ver_proj); + kvfree(me); + } +} + +struct ia_css_dvs_coefficients * +ia_css_dvs_coefficients_allocate(const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_dvs_coefficients *me; + + assert(grid); + + me = kvcalloc(1, sizeof(*me), GFP_KERNEL); + if (!me) + goto err; + + me->grid = *grid; + + me->hor_coefs = kvmalloc(grid->num_hor_coefs * + IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(*me->hor_coefs), GFP_KERNEL); + if (!me->hor_coefs) + goto err; + + me->ver_coefs = kvmalloc(grid->num_ver_coefs * + IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(*me->ver_coefs), GFP_KERNEL); + if (!me->ver_coefs) + goto err; + + return me; +err: + ia_css_dvs_coefficients_free(me); + return NULL; +} + +void +ia_css_dvs_coefficients_free(struct ia_css_dvs_coefficients *me) +{ + if (me) { + kvfree(me->hor_coefs); + kvfree(me->ver_coefs); + kvfree(me); + } +} + +struct ia_css_dvs2_statistics * +ia_css_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_dvs2_statistics *me; + + assert(grid); + + me = kvcalloc(1, sizeof(*me), GFP_KERNEL); + if (!me) + goto err; + + me->grid = *grid; + + me->hor_prod.odd_real = kvmalloc(grid->aligned_width * + grid->aligned_height * + sizeof(*me->hor_prod.odd_real), + GFP_KERNEL); + if (!me->hor_prod.odd_real) + goto err; + + me->hor_prod.odd_imag = kvmalloc(grid->aligned_width * + grid->aligned_height * + sizeof(*me->hor_prod.odd_imag), + GFP_KERNEL); + if (!me->hor_prod.odd_imag) + goto err; + + me->hor_prod.even_real = kvmalloc(grid->aligned_width * + grid->aligned_height * + sizeof(*me->hor_prod.even_real), + GFP_KERNEL); + if (!me->hor_prod.even_real) + goto err; + + me->hor_prod.even_imag = kvmalloc(grid->aligned_width * + grid->aligned_height * + sizeof(*me->hor_prod.even_imag), + GFP_KERNEL); + if (!me->hor_prod.even_imag) + goto err; + + me->ver_prod.odd_real = kvmalloc(grid->aligned_width * + grid->aligned_height * + sizeof(*me->ver_prod.odd_real), + GFP_KERNEL); + if (!me->ver_prod.odd_real) + goto err; + + me->ver_prod.odd_imag = kvmalloc(grid->aligned_width * + grid->aligned_height * + sizeof(*me->ver_prod.odd_imag), + GFP_KERNEL); + if (!me->ver_prod.odd_imag) + goto err; + + me->ver_prod.even_real = kvmalloc(grid->aligned_width * + grid->aligned_height * + sizeof(*me->ver_prod.even_real), + GFP_KERNEL); + if (!me->ver_prod.even_real) + goto err; + + me->ver_prod.even_imag = kvmalloc(grid->aligned_width * + grid->aligned_height * + sizeof(*me->ver_prod.even_imag), + GFP_KERNEL); + if (!me->ver_prod.even_imag) + goto err; + + return me; +err: + ia_css_dvs2_statistics_free(me); + return NULL; +} + +void +ia_css_dvs2_statistics_free(struct ia_css_dvs2_statistics *me) +{ + if (me) { + kvfree(me->hor_prod.odd_real); + kvfree(me->hor_prod.odd_imag); + kvfree(me->hor_prod.even_real); + kvfree(me->hor_prod.even_imag); + kvfree(me->ver_prod.odd_real); + kvfree(me->ver_prod.odd_imag); + kvfree(me->ver_prod.even_real); + kvfree(me->ver_prod.even_imag); + kvfree(me); + } +} + +struct ia_css_dvs2_coefficients * +ia_css_dvs2_coefficients_allocate(const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_dvs2_coefficients *me; + + assert(grid); + + me = kvcalloc(1, sizeof(*me), GFP_KERNEL); + if (!me) + goto err; + + me->grid = *grid; + + me->hor_coefs.odd_real = kvmalloc(grid->num_hor_coefs * + sizeof(*me->hor_coefs.odd_real), + GFP_KERNEL); + if (!me->hor_coefs.odd_real) + goto err; + + me->hor_coefs.odd_imag = kvmalloc(grid->num_hor_coefs * + sizeof(*me->hor_coefs.odd_imag), + GFP_KERNEL); + if (!me->hor_coefs.odd_imag) + goto err; + + me->hor_coefs.even_real = kvmalloc(grid->num_hor_coefs * + sizeof(*me->hor_coefs.even_real), + GFP_KERNEL); + if (!me->hor_coefs.even_real) + goto err; + + me->hor_coefs.even_imag = kvmalloc(grid->num_hor_coefs * + sizeof(*me->hor_coefs.even_imag), + GFP_KERNEL); + if (!me->hor_coefs.even_imag) + goto err; + + me->ver_coefs.odd_real = kvmalloc(grid->num_ver_coefs * + sizeof(*me->ver_coefs.odd_real), + GFP_KERNEL); + if (!me->ver_coefs.odd_real) + goto err; + + me->ver_coefs.odd_imag = kvmalloc(grid->num_ver_coefs * + sizeof(*me->ver_coefs.odd_imag), + GFP_KERNEL); + if (!me->ver_coefs.odd_imag) + goto err; + + me->ver_coefs.even_real = kvmalloc(grid->num_ver_coefs * + sizeof(*me->ver_coefs.even_real), + GFP_KERNEL); + if (!me->ver_coefs.even_real) + goto err; + + me->ver_coefs.even_imag = kvmalloc(grid->num_ver_coefs * + sizeof(*me->ver_coefs.even_imag), + GFP_KERNEL); + if (!me->ver_coefs.even_imag) + goto err; + + return me; +err: + ia_css_dvs2_coefficients_free(me); + return NULL; +} + +void +ia_css_dvs2_coefficients_free(struct ia_css_dvs2_coefficients *me) +{ + if (me) { + kvfree(me->hor_coefs.odd_real); + kvfree(me->hor_coefs.odd_imag); + kvfree(me->hor_coefs.even_real); + kvfree(me->hor_coefs.even_imag); + kvfree(me->ver_coefs.odd_real); + kvfree(me->ver_coefs.odd_imag); + kvfree(me->ver_coefs.even_real); + kvfree(me->ver_coefs.even_imag); + kvfree(me); + } +} + +struct ia_css_dvs_6axis_config * +ia_css_dvs2_6axis_config_allocate(const struct ia_css_stream *stream) +{ + struct ia_css_dvs_6axis_config *dvs_config = NULL; + struct ia_css_isp_parameters *params = NULL; + unsigned int width_y; + unsigned int height_y; + unsigned int width_uv; + unsigned int height_uv; + + assert(stream); + params = stream->isp_params_configs; + + /* Backward compatibility by default consider pipe as Video*/ + if (!params || !params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]) + goto err; + + dvs_config = kvcalloc(1, sizeof(struct ia_css_dvs_6axis_config), + GFP_KERNEL); + if (!dvs_config) + goto err; + + dvs_config->width_y = width_y = + params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->width_y; + dvs_config->height_y = height_y = + params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->height_y; + dvs_config->width_uv = width_uv = + params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->width_uv; + dvs_config->height_uv = height_uv = + params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->height_uv; + IA_CSS_LOG("table Y: W %d H %d", width_y, height_y); + IA_CSS_LOG("table UV: W %d H %d", width_uv, height_uv); + dvs_config->xcoords_y = kvmalloc(width_y * height_y * sizeof(uint32_t), + GFP_KERNEL); + if (!dvs_config->xcoords_y) + goto err; + + dvs_config->ycoords_y = kvmalloc(width_y * height_y * sizeof(uint32_t), + GFP_KERNEL); + if (!dvs_config->ycoords_y) + goto err; + + dvs_config->xcoords_uv = kvmalloc(width_uv * height_uv * + sizeof(uint32_t), + GFP_KERNEL); + if (!dvs_config->xcoords_uv) + goto err; + + dvs_config->ycoords_uv = kvmalloc(width_uv * height_uv * + sizeof(uint32_t), + GFP_KERNEL); + if (!dvs_config->ycoords_uv) + goto err; + + return dvs_config; +err: + ia_css_dvs2_6axis_config_free(dvs_config); + return NULL; +} + +void +ia_css_dvs2_6axis_config_free(struct ia_css_dvs_6axis_config *dvs_6axis_config) +{ + if (dvs_6axis_config) { + kvfree(dvs_6axis_config->xcoords_y); + kvfree(dvs_6axis_config->ycoords_y); + kvfree(dvs_6axis_config->xcoords_uv); + kvfree(dvs_6axis_config->ycoords_uv); + kvfree(dvs_6axis_config); + } +} + +void +ia_css_en_dz_capt_pipe(struct ia_css_stream *stream, bool enable) +{ + struct ia_css_pipe *pipe; + struct ia_css_pipeline *pipeline; + struct ia_css_pipeline_stage *stage; + enum ia_css_pipe_id pipe_id; + int err; + int i; + + if (!stream) + return; + + for (i = 0; i < stream->num_pipes; i++) { + pipe = stream->pipes[i]; + pipeline = ia_css_pipe_get_pipeline(pipe); + pipe_id = pipeline->pipe_id; + + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) { + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_CAPTURE_PP, + &stage); + if (!err) + stage->enable_zoom = enable; + break; + } + } +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_params.h b/drivers/staging/media/atomisp/pci/sh_css_params.h new file mode 100644 index 000000000..bbca19d0e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_params.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_PARAMS_H_ +#define _SH_CSS_PARAMS_H_ + +/*! \file */ + +/* Forward declaration to break mutual dependency */ +struct ia_css_isp_parameters; + +#include +#include "ia_css_types.h" +#include "ia_css_binary.h" +#include "sh_css_legacy.h" + +#include "sh_css_defs.h" /* SH_CSS_MAX_STAGES */ +#include "ia_css_pipeline.h" +#include "ia_css_isp_params.h" +#include "uds/uds_1.0/ia_css_uds_param.h" +#include "crop/crop_1.0/ia_css_crop_types.h" + +#define PIX_SHIFT_FILTER_RUN_IN_X 12 +#define PIX_SHIFT_FILTER_RUN_IN_Y 12 + +#include "ob/ob_1.0/ia_css_ob_param.h" +/* Isp configurations per stream */ +struct sh_css_isp_param_configs { + /* OB (Optical Black) */ + struct sh_css_isp_ob_stream_config ob; +}; + +/* Isp parameters per stream */ +struct ia_css_isp_parameters { + /* UDS */ + struct sh_css_sp_uds_params uds[SH_CSS_MAX_STAGES]; + struct sh_css_isp_param_configs stream_configs; + struct ia_css_fpn_table fpn_config; + struct ia_css_vector motion_config; + const struct ia_css_morph_table *morph_table; + const struct ia_css_shading_table *sc_table; + struct ia_css_shading_table *sc_config; + struct ia_css_macc_table macc_table; + struct ia_css_gamma_table gc_table; + struct ia_css_ctc_table ctc_table; + struct ia_css_xnr_table xnr_table; + + struct ia_css_dz_config dz_config; + struct ia_css_3a_config s3a_config; + struct ia_css_wb_config wb_config; + struct ia_css_cc_config cc_config; + struct ia_css_cc_config yuv2rgb_cc_config; + struct ia_css_cc_config rgb2yuv_cc_config; + struct ia_css_tnr_config tnr_config; + struct ia_css_ob_config ob_config; + /*----- DPC configuration -----*/ + /* The default DPC configuration is retained and currently set + * using the stream configuration. The code generated from genparams + * uses this configuration to set the DPC parameters per stage but this + * will be overwritten by the per pipe configuration */ + struct ia_css_dp_config dp_config; + /* ------ pipe specific DPC configuration ------ */ + /* Please note that this implementation is a temporary solution and + * should be replaced by CSS per pipe configuration when the support + * is ready (HSD 1303967698)*/ + struct ia_css_dp_config pipe_dp_config[IA_CSS_PIPE_ID_NUM]; + struct ia_css_nr_config nr_config; + struct ia_css_ee_config ee_config; + struct ia_css_de_config de_config; + struct ia_css_gc_config gc_config; + struct ia_css_anr_config anr_config; + struct ia_css_ce_config ce_config; + struct ia_css_formats_config formats_config; + /* ---- deprecated: replaced with pipe_dvs_6axis_config---- */ + struct ia_css_dvs_6axis_config *dvs_6axis_config; + struct ia_css_ecd_config ecd_config; + struct ia_css_ynr_config ynr_config; + struct ia_css_yee_config yee_config; + struct ia_css_fc_config fc_config; + struct ia_css_cnr_config cnr_config; + struct ia_css_macc_config macc_config; + struct ia_css_ctc_config ctc_config; + struct ia_css_aa_config aa_config; + struct ia_css_aa_config bds_config; + struct ia_css_aa_config raa_config; + struct ia_css_rgb_gamma_table r_gamma_table; + struct ia_css_rgb_gamma_table g_gamma_table; + struct ia_css_rgb_gamma_table b_gamma_table; + struct ia_css_anr_thres anr_thres; + struct ia_css_xnr_config xnr_config; + struct ia_css_xnr3_config xnr3_config; + struct ia_css_uds_config uds_config; + struct ia_css_crop_config crop_config; + struct ia_css_output_config output_config; + struct ia_css_dvs_6axis_config *pipe_dvs_6axis_config[IA_CSS_PIPE_ID_NUM]; + /* ------ deprecated(bz675) : from ------ */ + struct ia_css_shading_settings shading_settings; + /* ------ deprecated(bz675) : to ------ */ + struct ia_css_dvs_coefficients dvs_coefs; + struct ia_css_dvs2_coefficients dvs2_coefs; + + bool isp_params_changed; + + bool isp_mem_params_changed + [IA_CSS_PIPE_ID_NUM][SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; + bool dz_config_changed; + bool motion_config_changed; + bool dis_coef_table_changed; + bool dvs2_coef_table_changed; + bool morph_table_changed; + bool sc_table_changed; + bool anr_thres_changed; + /* ---- deprecated: replaced with pipe_dvs_6axis_config_changed ---- */ + bool dvs_6axis_config_changed; + /* ------ pipe specific DPC configuration ------ */ + /* Please note that this implementation is a temporary solution and + * should be replaced by CSS per pipe configuration when the support + * is ready (HSD 1303967698) */ + bool pipe_dpc_config_changed[IA_CSS_PIPE_ID_NUM]; + /* ------ deprecated(bz675) : from ------ */ + bool shading_settings_changed; + /* ------ deprecated(bz675) : to ------ */ + bool pipe_dvs_6axis_config_changed[IA_CSS_PIPE_ID_NUM]; + + bool config_changed[IA_CSS_NUM_PARAMETER_IDS]; + + unsigned int sensor_binning; + /* local buffers, used to re-order the 3a statistics in vmem-format */ + struct sh_css_ddr_address_map pipe_ddr_ptrs[IA_CSS_PIPE_ID_NUM]; + struct sh_css_ddr_address_map_size pipe_ddr_ptrs_size[IA_CSS_PIPE_ID_NUM]; + struct sh_css_ddr_address_map ddr_ptrs; + struct sh_css_ddr_address_map_size ddr_ptrs_size; + struct ia_css_frame + *output_frame; /** Output frame the config is to be applied to (optional) */ + u32 isp_parameters_id; /** Unique ID to track which config was actually applied to a particular frame */ +}; + +void +ia_css_params_store_ia_css_host_data( + ia_css_ptr ddr_addr, + struct ia_css_host_data *data); + +int +ia_css_params_store_sctbl( + const struct ia_css_pipeline_stage *stage, + ia_css_ptr ddr_addr, + const struct ia_css_shading_table *shading_table); + +struct ia_css_host_data * +ia_css_params_alloc_convert_sctbl( + const struct ia_css_pipeline_stage *stage, + const struct ia_css_shading_table *shading_table); + +struct ia_css_isp_config * +sh_css_pipe_isp_config_get(struct ia_css_pipe *pipe); + +int +sh_css_params_map_and_store_default_gdc_lut(void); + +void +sh_css_params_free_default_gdc_lut(void); + +ia_css_ptr +sh_css_params_get_default_gdc_lut(void); + +ia_css_ptr +sh_css_pipe_get_pp_gdc_lut(const struct ia_css_pipe *pipe); + +#endif /* _SH_CSS_PARAMS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_params_internal.h b/drivers/staging/media/atomisp/pci/sh_css_params_internal.h new file mode 100644 index 000000000..8e5e6f273 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_params_internal.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_PARAMS_INTERNAL_H_ +#define _SH_CSS_PARAMS_INTERNAL_H_ + +void +sh_css_param_clear_param_sets(void); + +#endif /* _SH_CSS_PARAMS_INTERNAL_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_properties.c b/drivers/staging/media/atomisp/pci/sh_css_properties.c new file mode 100644 index 000000000..8ecd93d65 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_properties.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_properties.h" +#include +#include "ia_css_types.h" +#include "gdc_device.h" + +void +ia_css_get_properties(struct ia_css_properties *properties) +{ + assert(properties); + /* + * MW: We don't want to store the coordinates + * full range in memory: Truncate + */ + properties->gdc_coord_one = gdc_get_unity(GDC0_ID) / HRT_GDC_COORD_SCALE; + + properties->l1_base_is_index = true; + + properties->vamem_type = IA_CSS_VAMEM_TYPE_2; +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_sp.c b/drivers/staging/media/atomisp/pci/sh_css_sp.c new file mode 100644 index 000000000..0dd58a7fe --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_sp.c @@ -0,0 +1,1773 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmm.h" + +#include "sh_css_sp.h" + +#if !defined(ISP2401) +#include "input_formatter.h" +#endif + +#include "dma.h" /* N_DMA_CHANNEL_ID */ + +#include "ia_css_buffer.h" +#include "ia_css_binary.h" +#include "sh_css_hrt.h" +#include "sh_css_defs.h" +#include "sh_css_internal.h" +#include "ia_css_control.h" +#include "ia_css_debug.h" +#include "ia_css_debug_pipe.h" +#include "ia_css_event_public.h" +#include "ia_css_mmu.h" +#include "ia_css_stream.h" +#include "ia_css_isp_param.h" +#include "sh_css_params.h" +#include "sh_css_legacy.h" +#include "ia_css_frame_comm.h" +#include "ia_css_isys.h" + +#include "gdc_device.h" /* HRT_GDC_N */ + +/*#include "sp.h"*/ /* host2sp_enqueue_frame_data() */ + + +#include "assert_support.h" + +#include "sw_event_global.h" /* Event IDs.*/ +#include "ia_css_event.h" +#include "mmu_device.h" +#include "ia_css_spctrl.h" + +#ifndef offsetof +#define offsetof(T, x) ((unsigned int)&(((T *)0)->x)) +#endif + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#define IA_CSS_INCLUDE_STATES +#include "ia_css_isp_states.h" + +#include "isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.h" + +struct sh_css_sp_group sh_css_sp_group; +struct sh_css_sp_stage sh_css_sp_stage; +struct sh_css_isp_stage sh_css_isp_stage; +static struct sh_css_sp_output sh_css_sp_output; +static struct sh_css_sp_per_frame_data per_frame_data; + +/* true if SP supports frame loop and host2sp_commands */ +/* For the moment there is only code that sets this bool to true */ +/* TODO: add code that sets this bool to false */ +static bool sp_running; + +static int +set_output_frame_buffer(const struct ia_css_frame *frame, + unsigned int idx); + +static void +sh_css_copy_buffer_attr_to_spbuffer(struct ia_css_buffer_sp *dest_buf, + const enum sh_css_queue_id queue_id, + const ia_css_ptr xmem_addr, + const enum ia_css_buffer_type buf_type); + +static void +initialize_frame_buffer_attribute(struct ia_css_buffer_sp *buf_attr); + +static void +initialize_stage_frames(struct ia_css_frames_sp *frames); + +/* This data is stored every frame */ +void +store_sp_group_data(void) +{ + per_frame_data.sp_group_addr = sh_css_store_sp_group_to_ddr(); +} + +static void +copy_isp_stage_to_sp_stage(void) +{ + /* [WW07.5]type casting will cause potential issues */ + sh_css_sp_stage.num_stripes = (uint8_t) + sh_css_isp_stage.binary_info.iterator.num_stripes; + sh_css_sp_stage.row_stripes_height = (uint16_t) + sh_css_isp_stage.binary_info.iterator.row_stripes_height; + sh_css_sp_stage.row_stripes_overlap_lines = (uint16_t) + sh_css_isp_stage.binary_info.iterator.row_stripes_overlap_lines; + sh_css_sp_stage.top_cropping = (uint16_t) + sh_css_isp_stage.binary_info.pipeline.top_cropping; + /* moved to sh_css_sp_init_stage + sh_css_sp_stage.enable.vf_output = + sh_css_isp_stage.binary_info.enable.vf_veceven || + sh_css_isp_stage.binary_info.num_output_pins > 1; + */ + sh_css_sp_stage.enable.sdis = sh_css_isp_stage.binary_info.enable.dis; + sh_css_sp_stage.enable.s3a = sh_css_isp_stage.binary_info.enable.s3a; +} + +void +store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num, + unsigned int stage) +{ + unsigned int thread_id; + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + copy_isp_stage_to_sp_stage(); + if (id != IA_CSS_PIPE_ID_COPY) + sh_css_sp_stage.isp_stage_addr = + sh_css_store_isp_stage_to_ddr(pipe_num, stage); + sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = + sh_css_store_sp_stage_to_ddr(pipe_num, stage); + + /* Clear for next frame */ + sh_css_sp_stage.program_input_circuit = false; +} + +static void +store_sp_per_frame_data(const struct ia_css_fw_info *fw) +{ + unsigned int HIVE_ADDR_sp_per_frame_data = 0; + + assert(fw); + + switch (fw->type) { + case ia_css_sp_firmware: + HIVE_ADDR_sp_per_frame_data = fw->info.sp.per_frame_data; + break; + case ia_css_acc_firmware: + HIVE_ADDR_sp_per_frame_data = fw->info.acc.per_frame_data; + break; + case ia_css_isp_firmware: + return; + } + + sp_dmem_store(SP0_ID, + (unsigned int)sp_address_of(sp_per_frame_data), + &per_frame_data, + sizeof(per_frame_data)); +} + +static void +sh_css_store_sp_per_frame_data(enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + const struct ia_css_fw_info *sp_fw) +{ + if (!sp_fw) + sp_fw = &sh_css_sp_fw; + + store_sp_stage_data(pipe_id, pipe_num, 0); + store_sp_group_data(); + store_sp_per_frame_data(sp_fw); +} + +#if SP_DEBUG != SP_DEBUG_NONE + +void +sh_css_sp_get_debug_state(struct sh_css_sp_debug_state *state) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_sp_output = fw->info.sp.output; + unsigned int i; + unsigned int offset = (unsigned int)offsetof(struct sh_css_sp_output, + debug) / sizeof(int); + + assert(state); + + (void)HIVE_ADDR_sp_output; /* To get rid of warning in CRUN */ + for (i = 0; i < sizeof(*state) / sizeof(int); i++) + ((unsigned *)state)[i] = load_sp_array_uint(sp_output, i + offset); +} + +#endif + +void +sh_css_sp_start_binary_copy(unsigned int pipe_num, + struct ia_css_frame *out_frame, + unsigned int two_ppc) +{ + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + struct sh_css_sp_pipeline *pipe; + u8 stage_num = 0; + + assert(out_frame); + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + pipe = &sh_css_sp_group.pipe[thread_id]; + + pipe->copy.bin.bytes_available = out_frame->data_bytes; + pipe->num_stages = 1; + pipe->pipe_id = pipe_id; + pipe->pipe_num = pipe_num; + pipe->thread_id = thread_id; + pipe->pipe_config = 0x0; /* No parameters */ + pipe->pipe_qos_config = QOS_INVALID; + + if (pipe->inout_port_config == 0) { + SH_CSS_PIPE_PORT_CONFIG_SET(pipe->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + SH_CSS_PIPE_PORT_CONFIG_SET(pipe->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + } + IA_CSS_LOG("pipe_id %d port_config %08x", + pipe->pipe_id, pipe->inout_port_config); + +#if !defined(ISP2401) + sh_css_sp_group.config.input_formatter.isp_2ppc = (uint8_t)two_ppc; +#else + (void)two_ppc; +#endif + + sh_css_sp_stage.num = stage_num; + sh_css_sp_stage.stage_type = SH_CSS_SP_STAGE_TYPE; + sh_css_sp_stage.func = + (unsigned int)IA_CSS_PIPELINE_BIN_COPY; + + set_output_frame_buffer(out_frame, 0); + + /* sp_bin_copy_init on the SP does not deal with dynamica/static yet */ + /* For now always update the dynamic data from out frames. */ + sh_css_store_sp_per_frame_data(pipe_id, pipe_num, &sh_css_sp_fw); +} + +static void +sh_css_sp_start_raw_copy(struct ia_css_frame *out_frame, + unsigned int pipe_num, + unsigned int two_ppc, + unsigned int max_input_width, + enum sh_css_pipe_config_override pipe_conf_override, + unsigned int if_config_index) +{ + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + u8 stage_num = 0; + struct sh_css_sp_pipeline *pipe; + + assert(out_frame); + + { + /* + * Clear sh_css_sp_stage for easy debugging. + * program_input_circuit must be saved as it is set outside + * this function. + */ + u8 program_input_circuit; + + program_input_circuit = sh_css_sp_stage.program_input_circuit; + memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage)); + sh_css_sp_stage.program_input_circuit = program_input_circuit; + } + + pipe_id = IA_CSS_PIPE_ID_COPY; + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + pipe = &sh_css_sp_group.pipe[thread_id]; + + pipe->copy.raw.height = out_frame->frame_info.res.height; + pipe->copy.raw.width = out_frame->frame_info.res.width; + pipe->copy.raw.padded_width = out_frame->frame_info.padded_width; + pipe->copy.raw.raw_bit_depth = out_frame->frame_info.raw_bit_depth; + pipe->copy.raw.max_input_width = max_input_width; + pipe->num_stages = 1; + pipe->pipe_id = pipe_id; + /* TODO: next indicates from which queues parameters need to be + sampled, needs checking/improvement */ + if (pipe_conf_override == SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD) + pipe->pipe_config = + (SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << thread_id); + else + pipe->pipe_config = pipe_conf_override; + + pipe->pipe_qos_config = QOS_INVALID; + + if (pipe->inout_port_config == 0) { + SH_CSS_PIPE_PORT_CONFIG_SET(pipe->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + SH_CSS_PIPE_PORT_CONFIG_SET(pipe->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + } + IA_CSS_LOG("pipe_id %d port_config %08x", + pipe->pipe_id, pipe->inout_port_config); + +#if !defined(ISP2401) + sh_css_sp_group.config.input_formatter.isp_2ppc = (uint8_t)two_ppc; +#else + (void)two_ppc; +#endif + + sh_css_sp_stage.num = stage_num; + sh_css_sp_stage.xmem_bin_addr = 0x0; + sh_css_sp_stage.stage_type = SH_CSS_SP_STAGE_TYPE; + sh_css_sp_stage.func = (unsigned int)IA_CSS_PIPELINE_RAW_COPY; + sh_css_sp_stage.if_config_index = (uint8_t)if_config_index; + set_output_frame_buffer(out_frame, 0); + + ia_css_debug_pipe_graph_dump_sp_raw_copy(out_frame); +} + +static void +sh_css_sp_start_isys_copy(struct ia_css_frame *out_frame, + unsigned int pipe_num, unsigned int max_input_width, + unsigned int if_config_index) +{ + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + u8 stage_num = 0; + struct sh_css_sp_pipeline *pipe; + enum sh_css_queue_id queue_id; + + assert(out_frame); + + { + /* + * Clear sh_css_sp_stage for easy debugging. + * program_input_circuit must be saved as it is set outside + * this function. + */ + u8 program_input_circuit; + + program_input_circuit = sh_css_sp_stage.program_input_circuit; + memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage)); + sh_css_sp_stage.program_input_circuit = program_input_circuit; + } + + pipe_id = IA_CSS_PIPE_ID_COPY; + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + pipe = &sh_css_sp_group.pipe[thread_id]; + + pipe->copy.raw.height = out_frame->frame_info.res.height; + pipe->copy.raw.width = out_frame->frame_info.res.width; + pipe->copy.raw.padded_width = out_frame->frame_info.padded_width; + pipe->copy.raw.raw_bit_depth = out_frame->frame_info.raw_bit_depth; + pipe->copy.raw.max_input_width = max_input_width; + pipe->num_stages = 1; + pipe->pipe_id = pipe_id; + pipe->pipe_config = 0x0; /* No parameters */ + pipe->pipe_qos_config = QOS_INVALID; + + initialize_stage_frames(&sh_css_sp_stage.frames); + sh_css_sp_stage.num = stage_num; + sh_css_sp_stage.xmem_bin_addr = 0x0; + sh_css_sp_stage.stage_type = SH_CSS_SP_STAGE_TYPE; + sh_css_sp_stage.func = (unsigned int)IA_CSS_PIPELINE_ISYS_COPY; + sh_css_sp_stage.if_config_index = (uint8_t)if_config_index; + + set_output_frame_buffer(out_frame, 0); + + if (pipe->metadata.height > 0) { + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_METADATA, thread_id, + &queue_id); + sh_css_copy_buffer_attr_to_spbuffer(&sh_css_sp_stage.frames.metadata_buf, + queue_id, mmgr_EXCEPTION, + IA_CSS_BUFFER_TYPE_METADATA); + } + + ia_css_debug_pipe_graph_dump_sp_raw_copy(out_frame); +} + +unsigned int +sh_css_sp_get_binary_copy_size(void) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_sp_output = fw->info.sp.output; + unsigned int offset = (unsigned int)offsetof(struct sh_css_sp_output, + bin_copy_bytes_copied) / sizeof(int); + (void)HIVE_ADDR_sp_output; /* To get rid of warning in CRUN */ + return load_sp_array_uint(sp_output, offset); +} + +unsigned int +sh_css_sp_get_sw_interrupt_value(unsigned int irq) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_sp_output = fw->info.sp.output; + unsigned int offset = (unsigned int)offsetof(struct sh_css_sp_output, + sw_interrupt_value) + / sizeof(int); + (void)HIVE_ADDR_sp_output; /* To get rid of warning in CRUN */ + return load_sp_array_uint(sp_output, offset + irq); +} + +static void +sh_css_copy_buffer_attr_to_spbuffer(struct ia_css_buffer_sp *dest_buf, + const enum sh_css_queue_id queue_id, + const ia_css_ptr xmem_addr, + const enum ia_css_buffer_type buf_type) +{ + assert(buf_type < IA_CSS_NUM_BUFFER_TYPE); + if (queue_id > SH_CSS_INVALID_QUEUE_ID) { + /* + * value >=0 indicates that function init_frame_pointers() + * should use the dynamic data address + */ + assert(queue_id < SH_CSS_MAX_NUM_QUEUES); + + /* Klocwork assumes assert can be disabled; + Since we can get there with any type, and it does not + know that frame_in->dynamic_data_index can only be set + for one of the types in the assert) it has to assume we + can get here for any type. however this could lead to an + out of bounds reference when indexing buf_type about 10 + lines below. In order to satisfy KW an additional if + has been added. This one will always yield true. + */ + if ((queue_id < SH_CSS_MAX_NUM_QUEUES)) { + dest_buf->buf_src.queue_id = queue_id; + } + } else { + assert(xmem_addr != mmgr_EXCEPTION); + dest_buf->buf_src.xmem_addr = xmem_addr; + } + dest_buf->buf_type = buf_type; +} + +static void +sh_css_copy_frame_to_spframe(struct ia_css_frame_sp *sp_frame_out, + const struct ia_css_frame *frame_in) +{ + assert(frame_in); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_copy_frame_to_spframe():\n"); + + sh_css_copy_buffer_attr_to_spbuffer(&sp_frame_out->buf_attr, + frame_in->dynamic_queue_id, + frame_in->data, + frame_in->buf_type); + + ia_css_frame_info_to_frame_sp_info(&sp_frame_out->info, &frame_in->frame_info); + + switch (frame_in->frame_info.format) { + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + case IA_CSS_FRAME_FORMAT_RAW: + sp_frame_out->planes.raw.offset = frame_in->planes.raw.offset; + break; + case IA_CSS_FRAME_FORMAT_RGB565: + case IA_CSS_FRAME_FORMAT_RGBA888: + sp_frame_out->planes.rgb.offset = frame_in->planes.rgb.offset; + break; + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + sp_frame_out->planes.planar_rgb.r.offset = + frame_in->planes.planar_rgb.r.offset; + sp_frame_out->planes.planar_rgb.g.offset = + frame_in->planes.planar_rgb.g.offset; + sp_frame_out->planes.planar_rgb.b.offset = + frame_in->planes.planar_rgb.b.offset; + break; + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + sp_frame_out->planes.yuyv.offset = frame_in->planes.yuyv.offset; + break; + case IA_CSS_FRAME_FORMAT_NV11: + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV12_16: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV61: + sp_frame_out->planes.nv.y.offset = + frame_in->planes.nv.y.offset; + sp_frame_out->planes.nv.uv.offset = + frame_in->planes.nv.uv.offset; + break; + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUV422: + case IA_CSS_FRAME_FORMAT_YUV444: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_YUV422_16: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_YV16: + sp_frame_out->planes.yuv.y.offset = + frame_in->planes.yuv.y.offset; + sp_frame_out->planes.yuv.u.offset = + frame_in->planes.yuv.u.offset; + sp_frame_out->planes.yuv.v.offset = + frame_in->planes.yuv.v.offset; + break; + case IA_CSS_FRAME_FORMAT_QPLANE6: + sp_frame_out->planes.plane6.r.offset = + frame_in->planes.plane6.r.offset; + sp_frame_out->planes.plane6.r_at_b.offset = + frame_in->planes.plane6.r_at_b.offset; + sp_frame_out->planes.plane6.gr.offset = + frame_in->planes.plane6.gr.offset; + sp_frame_out->planes.plane6.gb.offset = + frame_in->planes.plane6.gb.offset; + sp_frame_out->planes.plane6.b.offset = + frame_in->planes.plane6.b.offset; + sp_frame_out->planes.plane6.b_at_r.offset = + frame_in->planes.plane6.b_at_r.offset; + break; + case IA_CSS_FRAME_FORMAT_BINARY_8: + sp_frame_out->planes.binary.data.offset = + frame_in->planes.binary.data.offset; + break; + default: + /* This should not happen, but in case it does, + * nullify the planes + */ + memset(&sp_frame_out->planes, 0, sizeof(sp_frame_out->planes)); + break; + } +} + +static int +set_input_frame_buffer(const struct ia_css_frame *frame) +{ + if (!frame) + return -EINVAL; + + switch (frame->frame_info.format) { + case IA_CSS_FRAME_FORMAT_QPLANE6: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + case IA_CSS_FRAME_FORMAT_RAW: + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV12_16: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10: + break; + default: + return -EINVAL; + } + sh_css_copy_frame_to_spframe(&sh_css_sp_stage.frames.in, frame); + + return 0; +} + +static int +set_output_frame_buffer(const struct ia_css_frame *frame, + unsigned int idx) +{ + if (!frame) + return -EINVAL; + + switch (frame->frame_info.format) { + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUV422: + case IA_CSS_FRAME_FORMAT_YUV444: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_YV16: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_YUV422_16: + case IA_CSS_FRAME_FORMAT_NV11: + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV12_16: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV61: + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + case IA_CSS_FRAME_FORMAT_RGB565: + case IA_CSS_FRAME_FORMAT_RGBA888: + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + case IA_CSS_FRAME_FORMAT_RAW: + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + case IA_CSS_FRAME_FORMAT_QPLANE6: + case IA_CSS_FRAME_FORMAT_BINARY_8: + break; + default: + return -EINVAL; + } + sh_css_copy_frame_to_spframe(&sh_css_sp_stage.frames.out[idx], frame); + return 0; +} + +static int +set_view_finder_buffer(const struct ia_css_frame *frame) +{ + if (!frame) + return -EINVAL; + + switch (frame->frame_info.format) { + /* the dual output pin */ + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV12_16: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + + /* for vf_veceven */ + case IA_CSS_FRAME_FORMAT_YUV_LINE: + break; + default: + return -EINVAL; + } + + sh_css_copy_frame_to_spframe(&sh_css_sp_stage.frames.out_vf, frame); + return 0; +} + +#if !defined(ISP2401) +void sh_css_sp_set_if_configs( + const input_formatter_cfg_t *config_a, + const input_formatter_cfg_t *config_b, + const uint8_t if_config_index +) +{ + assert(if_config_index < SH_CSS_MAX_IF_CONFIGS); + assert(config_a); + + sh_css_sp_group.config.input_formatter.set[if_config_index].config_a = + *config_a; + sh_css_sp_group.config.input_formatter.a_changed = true; + + if (config_b) { + sh_css_sp_group.config.input_formatter.set[if_config_index].config_b = + *config_b; + sh_css_sp_group.config.input_formatter.b_changed = true; + } + + return; +} +#endif + +#if !defined(ISP2401) +void +sh_css_sp_program_input_circuit(int fmt_type, + int ch_id, + enum ia_css_input_mode input_mode) +{ + sh_css_sp_group.config.input_circuit.no_side_band = false; + sh_css_sp_group.config.input_circuit.fmt_type = fmt_type; + sh_css_sp_group.config.input_circuit.ch_id = ch_id; + sh_css_sp_group.config.input_circuit.input_mode = input_mode; + /* + * The SP group is only loaded at SP boot time and is read once + * change flags as "input_circuit_cfg_changed" must be reset on the SP + */ + sh_css_sp_group.config.input_circuit_cfg_changed = true; + sh_css_sp_stage.program_input_circuit = true; +} +#endif + +#if !defined(ISP2401) +void +sh_css_sp_configure_sync_gen(int width, int height, + int hblank_cycles, + int vblank_cycles) +{ + sh_css_sp_group.config.sync_gen.width = width; + sh_css_sp_group.config.sync_gen.height = height; + sh_css_sp_group.config.sync_gen.hblank_cycles = hblank_cycles; + sh_css_sp_group.config.sync_gen.vblank_cycles = vblank_cycles; +} + +void +sh_css_sp_configure_tpg(int x_mask, + int y_mask, + int x_delta, + int y_delta, + int xy_mask) +{ + sh_css_sp_group.config.tpg.x_mask = x_mask; + sh_css_sp_group.config.tpg.y_mask = y_mask; + sh_css_sp_group.config.tpg.x_delta = x_delta; + sh_css_sp_group.config.tpg.y_delta = y_delta; + sh_css_sp_group.config.tpg.xy_mask = xy_mask; +} + +void +sh_css_sp_configure_prbs(int seed) +{ + sh_css_sp_group.config.prbs.seed = seed; +} +#endif + +void +sh_css_sp_configure_enable_raw_pool_locking(bool lock_all) +{ + sh_css_sp_group.config.enable_raw_pool_locking = true; + sh_css_sp_group.config.lock_all = lock_all; +} + +void +sh_css_sp_enable_isys_event_queue(bool enable) +{ + sh_css_sp_group.config.enable_isys_event_queue = enable; +} + +void +sh_css_sp_set_disable_continuous_viewfinder(bool flag) +{ + sh_css_sp_group.config.disable_cont_vf = flag; +} + +static int +sh_css_sp_write_frame_pointers(const struct sh_css_binary_args *args) +{ + int err = 0; + int i; + + assert(args); + + if (args->in_frame) + err = set_input_frame_buffer(args->in_frame); + if (!err && args->out_vf_frame) + err = set_view_finder_buffer(args->out_vf_frame); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (!err && args->out_frame[i]) + err = set_output_frame_buffer(args->out_frame[i], i); + } + + /* we don't pass this error back to the upper layer, so we add a assert here + because we actually hit the error here but it still works by accident... */ + if (err) assert(false); + return err; +} + +static void +sh_css_sp_init_group(bool two_ppc, + enum atomisp_input_format input_format, + bool no_isp_sync, + uint8_t if_config_index) +{ +#if !defined(ISP2401) + sh_css_sp_group.config.input_formatter.isp_2ppc = two_ppc; +#else + (void)two_ppc; +#endif + + sh_css_sp_group.config.no_isp_sync = (uint8_t)no_isp_sync; + /* decide whether the frame is processed online or offline */ + if (if_config_index == SH_CSS_IF_CONFIG_NOT_NEEDED) return; +#if !defined(ISP2401) + assert(if_config_index < SH_CSS_MAX_IF_CONFIGS); + sh_css_sp_group.config.input_formatter.set[if_config_index].stream_format = + input_format; +#else + (void)input_format; +#endif +} + +void +sh_css_stage_write_binary_info(struct ia_css_binary_info *info) +{ + assert(info); + sh_css_isp_stage.binary_info = *info; +} + +static int +copy_isp_mem_if_to_ddr(struct ia_css_binary *binary) +{ + int err; + + err = ia_css_isp_param_copy_isp_mem_if_to_ddr( + &binary->css_params, + &binary->mem_params, + IA_CSS_PARAM_CLASS_CONFIG); + if (err) + return err; + err = ia_css_isp_param_copy_isp_mem_if_to_ddr( + &binary->css_params, + &binary->mem_params, + IA_CSS_PARAM_CLASS_STATE); + if (err) + return err; + return 0; +} + +static bool +is_sp_stage(struct ia_css_pipeline_stage *stage) +{ + assert(stage); + return stage->sp_func != IA_CSS_PIPELINE_NO_FUNC; +} + +static int configure_isp_from_args(const struct sh_css_sp_pipeline *pipeline, + const struct ia_css_binary *binary, + const struct sh_css_binary_args *args, + bool two_ppc, + bool deinterleaved) +{ + int ret; + + ret = ia_css_fpn_configure(binary, &binary->in_frame_info); + if (ret) + return ret; + ret = ia_css_crop_configure(binary, ia_css_frame_get_info(args->delay_frames[0])); + if (ret) + return ret; + ret = ia_css_qplane_configure(pipeline, binary, &binary->in_frame_info); + if (ret) + return ret; + ret = ia_css_output0_configure(binary, ia_css_frame_get_info(args->out_frame[0])); + if (ret) + return ret; + ret = ia_css_output1_configure(binary, ia_css_frame_get_info(args->out_vf_frame)); + if (ret) + return ret; + ret = ia_css_copy_output_configure(binary, args->copy_output); + if (ret) + return ret; + ret = ia_css_output0_configure(binary, ia_css_frame_get_info(args->out_frame[0])); + if (ret) + return ret; + ret = ia_css_iterator_configure(binary, ia_css_frame_get_info(args->in_frame)); + if (ret) + return ret; + ret = ia_css_dvs_configure(binary, ia_css_frame_get_info(args->out_frame[0])); + if (ret) + return ret; + ret = ia_css_output_configure(binary, ia_css_frame_get_info(args->out_frame[0])); + if (ret) + return ret; + ret = ia_css_raw_configure(pipeline, binary, ia_css_frame_get_info(args->in_frame), + &binary->in_frame_info, two_ppc, deinterleaved); + if (ret) + return ret; + + /* + * FIXME: args->delay_frames can be NULL here + * + * Somehow, the driver at the Intel Atom Yocto tree doesn't seem to + * suffer from the same issue. + * + * Anyway, the function below should now handle a NULL delay_frames + * without crashing, but the pipeline should likely be built without + * adding it at the first place (or there are a hidden bug somewhere) + */ + ret = ia_css_ref_configure(binary, args->delay_frames, pipeline->dvs_frame_delay); + if (ret) + return ret; + ret = ia_css_tnr_configure(binary, args->tnr_frames); + if (ret) + return ret; + return ia_css_bayer_io_config(binary, args); +} + +static void +initialize_isp_states(const struct ia_css_binary *binary) +{ + unsigned int i; + + if (!binary->info->mem_offsets.offsets.state) + return; + for (i = 0; i < IA_CSS_NUM_STATE_IDS; i++) { + ia_css_kernel_init_state[i](binary); + } +} + +static void +initialize_frame_buffer_attribute(struct ia_css_buffer_sp *buf_attr) +{ + buf_attr->buf_src.queue_id = SH_CSS_INVALID_QUEUE_ID; + buf_attr->buf_type = IA_CSS_BUFFER_TYPE_INVALID; +} + +static void +initialize_stage_frames(struct ia_css_frames_sp *frames) +{ + unsigned int i; + + initialize_frame_buffer_attribute(&frames->in.buf_attr); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + initialize_frame_buffer_attribute(&frames->out[i].buf_attr); + } + initialize_frame_buffer_attribute(&frames->out_vf.buf_attr); + initialize_frame_buffer_attribute(&frames->s3a_buf); + initialize_frame_buffer_attribute(&frames->dvs_buf); + initialize_frame_buffer_attribute(&frames->metadata_buf); +} + +static int +sh_css_sp_init_stage(struct ia_css_binary *binary, + const char *binary_name, + const struct ia_css_blob_info *blob_info, + const struct sh_css_binary_args *args, + unsigned int pipe_num, + unsigned int stage, + bool xnr, + const struct ia_css_isp_param_css_segments *isp_mem_if, + unsigned int if_config_index, + bool two_ppc) +{ + const struct ia_css_binary_xinfo *xinfo; + const struct ia_css_binary_info *info; + int err = 0; + int i; + struct ia_css_pipe *pipe = NULL; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + bool continuous = sh_css_continuous_is_enabled((uint8_t)pipe_num); + + assert(binary); + assert(blob_info); + assert(args); + assert(isp_mem_if); + + xinfo = binary->info; + info = &xinfo->sp; + { + /* + * Clear sh_css_sp_stage for easy debugging. + * program_input_circuit must be saved as it is set outside + * this function. + */ + u8 program_input_circuit; + + program_input_circuit = sh_css_sp_stage.program_input_circuit; + memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage)); + sh_css_sp_stage.program_input_circuit = (uint8_t)program_input_circuit; + } + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + + if (!info) { + sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = mmgr_NULL; + return 0; + } + +#if defined(ISP2401) + (void)continuous; + sh_css_sp_stage.deinterleaved = 0; +#else + sh_css_sp_stage.deinterleaved = ((stage == 0) && continuous); +#endif + + initialize_stage_frames(&sh_css_sp_stage.frames); + /* + * TODO: Make the Host dynamically determine + * the stage type. + */ + sh_css_sp_stage.stage_type = SH_CSS_ISP_STAGE_TYPE; + sh_css_sp_stage.num = (uint8_t)stage; + sh_css_sp_stage.isp_online = (uint8_t)binary->online; + sh_css_sp_stage.isp_copy_vf = (uint8_t)args->copy_vf; + sh_css_sp_stage.isp_copy_output = (uint8_t)args->copy_output; + sh_css_sp_stage.enable.vf_output = (args->out_vf_frame != NULL); + + /* Copy the frame infos first, to be overwritten by the frames, + if these are present. + */ + sh_css_sp_stage.frames.effective_in_res.width = binary->effective_in_frame_res.width; + sh_css_sp_stage.frames.effective_in_res.height = binary->effective_in_frame_res.height; + + ia_css_frame_info_to_frame_sp_info(&sh_css_sp_stage.frames.in.info, + &binary->in_frame_info); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + ia_css_frame_info_to_frame_sp_info(&sh_css_sp_stage.frames.out[i].info, + &binary->out_frame_info[i]); + } + ia_css_frame_info_to_frame_sp_info(&sh_css_sp_stage.frames.internal_frame_info, + &binary->internal_frame_info); + sh_css_sp_stage.dvs_envelope.width = binary->dvs_envelope.width; + sh_css_sp_stage.dvs_envelope.height = binary->dvs_envelope.height; + sh_css_sp_stage.isp_pipe_version = (uint8_t)info->pipeline.isp_pipe_version; + sh_css_sp_stage.isp_deci_log_factor = (uint8_t)binary->deci_factor_log2; + sh_css_sp_stage.isp_vf_downscale_bits = (uint8_t)binary->vf_downscale_log2; + + sh_css_sp_stage.if_config_index = (uint8_t)if_config_index; + + sh_css_sp_stage.sp_enable_xnr = (uint8_t)xnr; + sh_css_sp_stage.xmem_bin_addr = xinfo->xmem_addr; + sh_css_sp_stage.xmem_map_addr = sh_css_params_ddr_address_map(); + sh_css_isp_stage.blob_info = *blob_info; + sh_css_stage_write_binary_info((struct ia_css_binary_info *)info); + + /* Make sure binary name is smaller than allowed string size */ + assert(strlen(binary_name) < SH_CSS_MAX_BINARY_NAME - 1); + strscpy(sh_css_isp_stage.binary_name, binary_name, SH_CSS_MAX_BINARY_NAME); + sh_css_isp_stage.mem_initializers = *isp_mem_if; + + /* + * Even when a stage does not need uds and does not params, + * ia_css_uds_sp_scale_params() seems to be called (needs + * further investigation). This function can not deal with + * dx, dy = {0, 0} + */ + + err = sh_css_sp_write_frame_pointers(args); + /* TODO: move it to a better place */ + if (binary->info->sp.enable.s3a) { + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_3A_STATISTICS, thread_id, + &queue_id); + sh_css_copy_buffer_attr_to_spbuffer(&sh_css_sp_stage.frames.s3a_buf, queue_id, + mmgr_EXCEPTION, + IA_CSS_BUFFER_TYPE_3A_STATISTICS); + } + if (binary->info->sp.enable.dis) { + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_DIS_STATISTICS, thread_id, + &queue_id); + sh_css_copy_buffer_attr_to_spbuffer(&sh_css_sp_stage.frames.dvs_buf, queue_id, + mmgr_EXCEPTION, + IA_CSS_BUFFER_TYPE_DIS_STATISTICS); + } + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_METADATA, thread_id, &queue_id); + sh_css_copy_buffer_attr_to_spbuffer(&sh_css_sp_stage.frames.metadata_buf, queue_id, mmgr_EXCEPTION, IA_CSS_BUFFER_TYPE_METADATA); + if (err) + return err; + +#ifdef ISP2401 + pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num); + if (!pipe) + return -EINVAL; + + if (args->in_frame) + ia_css_get_crop_offsets(pipe, &args->in_frame->frame_info); + else + ia_css_get_crop_offsets(pipe, &binary->in_frame_info); +#else + (void)pipe; /*avoid build warning*/ +#endif + + err = configure_isp_from_args(&sh_css_sp_group.pipe[thread_id], + binary, args, two_ppc, sh_css_sp_stage.deinterleaved); + if (err) + return err; + + initialize_isp_states(binary); + + /* we do this only for preview pipe because in fill_binary_info function + * we assign vf_out res to out res, but for ISP internal processing, we need + * the original out res. for video pipe, it has two output pins --- out and + * vf_out, so it can keep these two resolutions already. */ + if (binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_PREVIEW && + (binary->vf_downscale_log2 > 0)) { + /* TODO: Remove this after preview output decimation is fixed + * by configuring out&vf info fiels properly */ + sh_css_sp_stage.frames.out[0].info.padded_width + <<= binary->vf_downscale_log2; + sh_css_sp_stage.frames.out[0].info.res.width + <<= binary->vf_downscale_log2; + sh_css_sp_stage.frames.out[0].info.res.height + <<= binary->vf_downscale_log2; + } + err = copy_isp_mem_if_to_ddr(binary); + if (err) + return err; + + return 0; +} + +static int +sp_init_stage(struct ia_css_pipeline_stage *stage, + unsigned int pipe_num, + bool xnr, + unsigned int if_config_index, + bool two_ppc) +{ + struct ia_css_binary *binary; + const struct ia_css_fw_info *firmware; + const struct sh_css_binary_args *args; + unsigned int stage_num; + /* + * Initialiser required because of the "else" path below. + * Is this a valid path ? + */ + const char *binary_name = ""; + const struct ia_css_binary_xinfo *info = NULL; + /* note: the var below is made static as it is quite large; + if it is not static it ends up on the stack which could + cause issues for drivers + */ + static struct ia_css_binary tmp_binary; + const struct ia_css_blob_info *blob_info = NULL; + struct ia_css_isp_param_css_segments isp_mem_if; + /* LA: should be ia_css_data, should not contain host pointer. + However, CSS/DDR pointer is not available yet. + Hack is to store it in params->ddr_ptrs and then copy it late in the SP just before vmem init. + TODO: Call this after CSS/DDR allocation and store that pointer. + Best is to allocate it at stage creation time together with host pointer. + Remove vmem from params. + */ + struct ia_css_isp_param_css_segments *mem_if = &isp_mem_if; + + int err = 0; + + assert(stage); + + binary = stage->binary; + firmware = stage->firmware; + args = &stage->args; + stage_num = stage->stage_num; + + if (binary) { + info = binary->info; + binary_name = (const char *)(info->blob->name); + blob_info = &info->blob->header.blob; + ia_css_init_memory_interface(mem_if, &binary->mem_params, &binary->css_params); + } else if (firmware) { + const struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL}; + + if (args->out_frame[0]) + out_infos[0] = &args->out_frame[0]->frame_info; + info = &firmware->info.isp; + ia_css_binary_fill_info(info, false, false, + ATOMISP_INPUT_FORMAT_RAW_10, + ia_css_frame_get_info(args->in_frame), + NULL, + out_infos, + ia_css_frame_get_info(args->out_vf_frame), + &tmp_binary, + NULL, + -1, true); + binary = &tmp_binary; + binary->info = info; + binary_name = IA_CSS_EXT_ISP_PROG_NAME(firmware); + blob_info = &firmware->blob; + mem_if = (struct ia_css_isp_param_css_segments *)&firmware->mem_initializers; + } else { + /* SP stage */ + assert(stage->sp_func != IA_CSS_PIPELINE_NO_FUNC); + /* binary and blob_info are now NULL. + These will be passed to sh_css_sp_init_stage + and dereferenced there, so passing a NULL + pointer is no good. return an error */ + return -EINVAL; + } + + err = sh_css_sp_init_stage(binary, + (const char *)binary_name, + blob_info, + args, + pipe_num, + stage_num, + xnr, + mem_if, + if_config_index, + two_ppc); + return err; +} + +static void +sp_init_sp_stage(struct ia_css_pipeline_stage *stage, + unsigned int pipe_num, + bool two_ppc, + enum sh_css_pipe_config_override copy_ovrd, + unsigned int if_config_index) +{ + const struct sh_css_binary_args *args = &stage->args; + + assert(stage); + switch (stage->sp_func) { + case IA_CSS_PIPELINE_RAW_COPY: + sh_css_sp_start_raw_copy(args->out_frame[0], + pipe_num, two_ppc, + stage->max_input_width, + copy_ovrd, if_config_index); + break; + case IA_CSS_PIPELINE_BIN_COPY: + assert(false); /* TBI */ + break; + case IA_CSS_PIPELINE_ISYS_COPY: + sh_css_sp_start_isys_copy(args->out_frame[0], + pipe_num, stage->max_input_width, if_config_index); + break; + case IA_CSS_PIPELINE_NO_FUNC: + assert(false); + break; + } +} + +void +sh_css_sp_init_pipeline(struct ia_css_pipeline *me, + enum ia_css_pipe_id id, + u8 pipe_num, + bool xnr, + bool two_ppc, + bool continuous, + bool offline, + unsigned int required_bds_factor, + enum sh_css_pipe_config_override copy_ovrd, + enum ia_css_input_mode input_mode, + const struct ia_css_metadata_config *md_config, + const struct ia_css_metadata_info *md_info, + const enum mipi_port_id port_id) +{ + /* Get first stage */ + struct ia_css_pipeline_stage *stage = NULL; + struct ia_css_binary *first_binary = NULL; + struct ia_css_pipe *pipe = NULL; + unsigned int num; + + enum ia_css_pipe_id pipe_id = id; + unsigned int thread_id; + u8 if_config_index, tmp_if_config_index; + + assert(me); + + assert(me->stages); + + first_binary = me->stages->binary; + + if (input_mode == IA_CSS_INPUT_MODE_SENSOR || + input_mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + assert(port_id < N_MIPI_PORT_ID); + if (port_id >= N_MIPI_PORT_ID) /* should not happen but KW does not know */ + return; /* we should be able to return an error */ + if_config_index = (uint8_t)(port_id - MIPI_PORT0_ID); + } else if (input_mode == IA_CSS_INPUT_MODE_MEMORY) { + if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED; + } else { + if_config_index = 0x0; + } + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + memset(&sh_css_sp_group.pipe[thread_id], 0, sizeof(struct sh_css_sp_pipeline)); + + /* Count stages */ + for (stage = me->stages, num = 0; stage; stage = stage->next, num++) { + stage->stage_num = num; + ia_css_debug_pipe_graph_dump_stage(stage, id); + } + me->num_stages = num; + + if (first_binary) { + /* Init pipeline data */ + sh_css_sp_init_group(two_ppc, first_binary->input_format, + offline, if_config_index); + } /* if (first_binary != NULL) */ + + /* Signal the host immediately after start for SP_ISYS_COPY only */ + if ((me->num_stages == 1) && me->stages && + (me->stages->sp_func == IA_CSS_PIPELINE_ISYS_COPY)) + sh_css_sp_group.config.no_isp_sync = true; + + /* Init stage data */ + sh_css_init_host2sp_frame_data(); + + sh_css_sp_group.pipe[thread_id].num_stages = 0; + sh_css_sp_group.pipe[thread_id].pipe_id = pipe_id; + sh_css_sp_group.pipe[thread_id].thread_id = thread_id; + sh_css_sp_group.pipe[thread_id].pipe_num = pipe_num; + sh_css_sp_group.pipe[thread_id].num_execs = me->num_execs; + sh_css_sp_group.pipe[thread_id].pipe_qos_config = QOS_INVALID; + sh_css_sp_group.pipe[thread_id].required_bds_factor = required_bds_factor; + sh_css_sp_group.pipe[thread_id].input_system_mode + = (uint32_t)input_mode; + sh_css_sp_group.pipe[thread_id].port_id = port_id; + sh_css_sp_group.pipe[thread_id].dvs_frame_delay = (uint32_t)me->dvs_frame_delay; + + /* TODO: next indicates from which queues parameters need to be + sampled, needs checking/improvement */ + if (ia_css_pipeline_uses_params(me)) { + sh_css_sp_group.pipe[thread_id].pipe_config = + SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << thread_id; + } + + /* For continuous use-cases, SP copy is responsible for sampling the + * parameters */ + if (continuous) + sh_css_sp_group.pipe[thread_id].pipe_config = 0; + + sh_css_sp_group.pipe[thread_id].inout_port_config = me->inout_port_config; + + pipe = find_pipe_by_num(pipe_num); + assert(pipe); + if (!pipe) { + return; + } + sh_css_sp_group.pipe[thread_id].scaler_pp_lut = sh_css_pipe_get_pp_gdc_lut(pipe); + + if (md_info && md_info->size > 0) { + sh_css_sp_group.pipe[thread_id].metadata.width = md_info->resolution.width; + sh_css_sp_group.pipe[thread_id].metadata.height = md_info->resolution.height; + sh_css_sp_group.pipe[thread_id].metadata.stride = md_info->stride; + sh_css_sp_group.pipe[thread_id].metadata.size = md_info->size; + ia_css_isys_convert_stream_format_to_mipi_format( + md_config->data_type, MIPI_PREDICTOR_NONE, + &sh_css_sp_group.pipe[thread_id].metadata.format); + } + + sh_css_sp_group.pipe[thread_id].output_frame_queue_id = (uint32_t)SH_CSS_INVALID_QUEUE_ID; + if (pipe_id != IA_CSS_PIPE_ID_COPY) { + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, thread_id, + (enum sh_css_queue_id *)( + &sh_css_sp_group.pipe[thread_id].output_frame_queue_id)); + } + + IA_CSS_LOG("pipe_id %d port_config %08x", + pipe_id, sh_css_sp_group.pipe[thread_id].inout_port_config); + + for (stage = me->stages, num = 0; stage; stage = stage->next, num++) { + sh_css_sp_group.pipe[thread_id].num_stages++; + if (is_sp_stage(stage)) { + sp_init_sp_stage(stage, pipe_num, two_ppc, + copy_ovrd, if_config_index); + } else { + if ((stage->stage_num != 0) || + SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(me->inout_port_config)) + tmp_if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED; + else + tmp_if_config_index = if_config_index; + sp_init_stage(stage, pipe_num, + xnr, tmp_if_config_index, two_ppc); + } + + store_sp_stage_data(pipe_id, pipe_num, num); + } + sh_css_sp_group.pipe[thread_id].pipe_config |= (uint32_t) + (me->acquire_isp_each_stage << IA_CSS_ACQUIRE_ISP_POS); + store_sp_group_data(); +} + +void +sh_css_sp_uninit_pipeline(unsigned int pipe_num) +{ + unsigned int thread_id; + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + /*memset(&sh_css_sp_group.pipe[thread_id], 0, sizeof(struct sh_css_sp_pipeline));*/ + sh_css_sp_group.pipe[thread_id].num_stages = 0; +} + +bool sh_css_write_host2sp_command(enum host2sp_commands host2sp_command) +{ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_command) + / sizeof(int); + enum host2sp_commands last_cmd = host2sp_cmd_error; + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + /* Previous command must be handled by SP (by design) */ + last_cmd = load_sp_array_uint(host_sp_com, offset); + if (last_cmd != host2sp_cmd_ready) + IA_CSS_ERROR("last host command not handled by SP(%d)", last_cmd); + + store_sp_array_uint(host_sp_com, offset, host2sp_command); + + return (last_cmd == host2sp_cmd_ready); +} + +enum host2sp_commands +sh_css_read_host2sp_command(void) +{ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_command) + / sizeof(int); + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + return (enum host2sp_commands)load_sp_array_uint(host_sp_com, offset); +} + +/* + * Frame data is no longer part of the sp_stage structure but part of a + * separate structure. The aim is to make the sp_data struct static + * (it defines a pipeline) and that the dynamic (per frame) data is stored + * separetly. + * + * This function must be called first every where were you start constructing + * a new pipeline by defining one or more stages with use of variable + * sh_css_sp_stage. Even the special cases like accelerator and copy_frame + * These have a pipeline of just 1 stage. + */ +void +sh_css_init_host2sp_frame_data(void) +{ + /* Clean table */ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + /* + * rvanimme: don't clean it to save static frame info line ref_in + * ref_out, and tnr_frames. Once this static data is in a + * separate data struct, this may be enable (but still, there is + * no need for it) + */ +} + +/* + * @brief Update the offline frame information in host_sp_communication. + * Refer to "sh_css_sp.h" for more details. + */ +void +sh_css_update_host2sp_offline_frame( + unsigned int frame_num, + struct ia_css_frame *frame, + struct ia_css_metadata *metadata) +{ + unsigned int HIVE_ADDR_host_sp_com; + unsigned int offset; + + assert(frame_num < NUM_CONTINUOUS_FRAMES); + + /* Write new frame data into SP DMEM */ + HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_offline_frames) + / sizeof(int); + offset += frame_num; + store_sp_array_uint(host_sp_com, offset, frame ? frame->data : 0); + + /* Write metadata buffer into SP DMEM */ + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_offline_metadata) + / sizeof(int); + offset += frame_num; + store_sp_array_uint(host_sp_com, offset, metadata ? metadata->address : 0); +} + +/* + * @brief Update the mipi frame information in host_sp_communication. + * Refer to "sh_css_sp.h" for more details. + */ +void +sh_css_update_host2sp_mipi_frame( + unsigned int frame_num, + struct ia_css_frame *frame) +{ + unsigned int HIVE_ADDR_host_sp_com; + unsigned int offset; + + /* MIPI buffers are dedicated to port, so now there are more of them. */ + assert(frame_num < (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM)); + + /* Write new frame data into SP DMEM */ + HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_mipi_frames) + / sizeof(int); + offset += frame_num; + + store_sp_array_uint(host_sp_com, offset, + frame ? frame->data : 0); +} + +/* + * @brief Update the mipi metadata information in host_sp_communication. + * Refer to "sh_css_sp.h" for more details. + */ +void +sh_css_update_host2sp_mipi_metadata( + unsigned int frame_num, + struct ia_css_metadata *metadata) +{ + unsigned int HIVE_ADDR_host_sp_com; + unsigned int o; + + /* MIPI buffers are dedicated to port, so now there are more of them. */ + assert(frame_num < (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM)); + + /* Write new frame data into SP DMEM */ + HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + o = offsetof(struct host_sp_communication, host2sp_mipi_metadata) + / sizeof(int); + o += frame_num; + store_sp_array_uint(host_sp_com, o, + metadata ? metadata->address : 0); +} + +void +sh_css_update_host2sp_num_mipi_frames(unsigned int num_frames) +{ + unsigned int HIVE_ADDR_host_sp_com; + unsigned int offset; + + /* Write new frame data into SP DMEM */ + HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_num_mipi_frames) + / sizeof(int); + + store_sp_array_uint(host_sp_com, offset, num_frames); +} + +void +sh_css_update_host2sp_cont_num_raw_frames(unsigned int num_frames, + bool set_avail) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_host_sp_com; + unsigned int extra_num_frames, avail_num_frames; + unsigned int offset, offset_extra; + + /* Write new frame data into SP DMEM */ + fw = &sh_css_sp_fw; + HIVE_ADDR_host_sp_com = fw->info.sp.host_sp_com; + if (set_avail) { + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_cont_avail_num_raw_frames) + / sizeof(int); + avail_num_frames = load_sp_array_uint(host_sp_com, offset); + extra_num_frames = num_frames - avail_num_frames; + offset_extra = (unsigned int)offsetof(struct host_sp_communication, + host2sp_cont_extra_num_raw_frames) + / sizeof(int); + store_sp_array_uint(host_sp_com, offset_extra, extra_num_frames); + } else + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_cont_target_num_raw_frames) + / sizeof(int); + + store_sp_array_uint(host_sp_com, offset, num_frames); +} + +void +sh_css_event_init_irq_mask(void) +{ + int i; + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset; + struct sh_css_event_irq_mask event_irq_mask_init; + + event_irq_mask_init.or_mask = IA_CSS_EVENT_TYPE_ALL; + event_irq_mask_init.and_mask = IA_CSS_EVENT_TYPE_NONE; + (void)HIVE_ADDR_host_sp_com; /* Suppress warnings in CRUN */ + + assert(sizeof(event_irq_mask_init) % HRT_BUS_BYTES == 0); + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_event_irq_mask[i]); + assert(offset % HRT_BUS_BYTES == 0); + sp_dmem_store(SP0_ID, + (unsigned int)sp_address_of(host_sp_com) + offset, + &event_irq_mask_init, sizeof(event_irq_mask_init)); + } +} + +int +ia_css_pipe_set_irq_mask(struct ia_css_pipe *pipe, + unsigned int or_mask, + unsigned int and_mask) +{ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset; + struct sh_css_event_irq_mask event_irq_mask; + unsigned int pipe_num; + + assert(pipe); + + assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES); + /* Linux kernel does not have UINT16_MAX + * Therefore decided to comment out these 2 asserts for Linux + * Alternatives that were not chosen: + * - add a conditional #define for UINT16_MAX + * - compare with (uint16_t)~0 or 0xffff + * - different assert for Linux and Windows + */ + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + IA_CSS_LOG("or_mask=%x, and_mask=%x", or_mask, and_mask); + event_irq_mask.or_mask = (uint16_t)or_mask; + event_irq_mask.and_mask = (uint16_t)and_mask; + + pipe_num = ia_css_pipe_get_pipe_num(pipe); + if (pipe_num >= IA_CSS_PIPE_ID_NUM) + return -EINVAL; + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_event_irq_mask[pipe_num]); + assert(offset % HRT_BUS_BYTES == 0); + sp_dmem_store(SP0_ID, + (unsigned int)sp_address_of(host_sp_com) + offset, + &event_irq_mask, sizeof(event_irq_mask)); + + return 0; +} + +int +ia_css_event_get_irq_mask(const struct ia_css_pipe *pipe, + unsigned int *or_mask, + unsigned int *and_mask) +{ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset; + struct sh_css_event_irq_mask event_irq_mask; + unsigned int pipe_num; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + IA_CSS_ENTER_LEAVE(""); + + assert(pipe); + assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES); + + pipe_num = ia_css_pipe_get_pipe_num(pipe); + if (pipe_num >= IA_CSS_PIPE_ID_NUM) + return -EINVAL; + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_event_irq_mask[pipe_num]); + assert(offset % HRT_BUS_BYTES == 0); + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(host_sp_com) + offset, + &event_irq_mask, sizeof(event_irq_mask)); + + if (or_mask) + *or_mask = event_irq_mask.or_mask; + + if (and_mask) + *and_mask = event_irq_mask.and_mask; + + return 0; +} + +void +sh_css_sp_set_sp_running(bool flag) +{ + sp_running = flag; +} + +bool +sh_css_sp_is_running(void) +{ + return sp_running; +} + +void +sh_css_sp_start_isp(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_sw_state; + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_sw_state = fw->info.sp.sw_state; + + if (sp_running) + return; + + (void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */ + + /* no longer here, sp started immediately */ + /*ia_css_debug_pipe_graph_dump_epilogue();*/ + + store_sp_group_data(); + store_sp_per_frame_data(fw); + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(sp_sw_state), + (uint32_t)(IA_CSS_SP_SW_TERMINATED)); + + /* Note 1: The sp_start_isp function contains a wait till + * the input network is configured by the SP. + * Note 2: Not all SP binaries supports host2sp_commands. + * In case a binary does support it, the host2sp_command + * will have status cmd_ready after return of the function + * sh_css_hrt_sp_start_isp. There is no race-condition here + * because only after the process_frame command has been + * received, the SP starts configuring the input network. + */ + + /* we need to set sp_running before we call ia_css_mmu_invalidate_cache + * as ia_css_mmu_invalidate_cache checks on sp_running to + * avoid that it accesses dmem while the SP is not powered + */ + sp_running = true; + ia_css_mmu_invalidate_cache(); + /* Invalidate all MMU caches */ + mmu_invalidate_cache_all(); + + ia_css_spctrl_start(SP0_ID); +} + +bool +ia_css_isp_has_started(void) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_ia_css_ispctrl_sp_isp_started = fw->info.sp.isp_started; + (void)HIVE_ADDR_ia_css_ispctrl_sp_isp_started; /* Suppres warnings in CRUN */ + + return (bool)load_sp_uint(ia_css_ispctrl_sp_isp_started); +} + +/* + * @brief Initialize the DMA software-mask in the debug mode. + * Refer to "sh_css_sp.h" for more details. + */ +bool +sh_css_sp_init_dma_sw_reg(int dma_id) +{ + int i; + + /* enable all the DMA channels */ + for (i = 0; i < N_DMA_CHANNEL_ID; i++) { + /* enable the writing request */ + sh_css_sp_set_dma_sw_reg(dma_id, + i, + 0, + true); + /* enable the reading request */ + sh_css_sp_set_dma_sw_reg(dma_id, + i, + 1, + true); + } + + return true; +} + +/* + * @brief Set the DMA software-mask in the debug mode. + * Refer to "sh_css_sp.h" for more details. + */ +bool +sh_css_sp_set_dma_sw_reg(int dma_id, + int channel_id, + int request_type, + bool enable) +{ + u32 sw_reg; + u32 bit_val; + u32 bit_offset; + u32 bit_mask; + + (void)dma_id; + + assert(channel_id >= 0 && channel_id < N_DMA_CHANNEL_ID); + assert(request_type >= 0); + + /* get the software-mask */ + sw_reg = + sh_css_sp_group.debug.dma_sw_reg; + + /* get the offest of the target bit */ + bit_offset = (8 * request_type) + channel_id; + + /* clear the value of the target bit */ + bit_mask = ~(1 << bit_offset); + sw_reg &= bit_mask; + + /* set the value of the bit for the DMA channel */ + bit_val = enable ? 1 : 0; + bit_val <<= bit_offset; + sw_reg |= bit_val; + + /* update the software status of DMA channels */ + sh_css_sp_group.debug.dma_sw_reg = sw_reg; + + return true; +} + +void +sh_css_sp_reset_global_vars(void) +{ + memset(&sh_css_sp_group, 0, sizeof(struct sh_css_sp_group)); + memset(&sh_css_sp_stage, 0, sizeof(struct sh_css_sp_stage)); + memset(&sh_css_isp_stage, 0, sizeof(struct sh_css_isp_stage)); + memset(&sh_css_sp_output, 0, sizeof(struct sh_css_sp_output)); + memset(&per_frame_data, 0, sizeof(struct sh_css_sp_per_frame_data)); +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_sp.h b/drivers/staging/media/atomisp/pci/sh_css_sp.h new file mode 100644 index 000000000..f69a79b0b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_sp.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_SP_H_ +#define _SH_CSS_SP_H_ + +#include +#include +#if !defined(ISP2401) +#include "input_formatter.h" +#endif + +#include "ia_css_binary.h" +#include "ia_css_types.h" +#include "ia_css_pipeline.h" + +/* Function to initialize the data and bss section descr of the binary */ +void +sh_css_sp_store_init_dmem(const struct ia_css_fw_info *fw); + +void +store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num, + unsigned int stage); + +void +sh_css_stage_write_binary_info(struct ia_css_binary_info *info); + +void +store_sp_group_data(void); + +/* Start binary (jpeg) copy on the SP */ +void +sh_css_sp_start_binary_copy(unsigned int pipe_num, + struct ia_css_frame *out_frame, + unsigned int two_ppc); + +unsigned int +sh_css_sp_get_binary_copy_size(void); + +/* Return the value of a SW interrupt */ +unsigned int +sh_css_sp_get_sw_interrupt_value(unsigned int irq); + +void +sh_css_sp_init_pipeline(struct ia_css_pipeline *me, + enum ia_css_pipe_id id, + u8 pipe_num, + bool xnr, + bool two_ppc, + bool continuous, + bool offline, + unsigned int required_bds_factor, + enum sh_css_pipe_config_override copy_ovrd, + enum ia_css_input_mode input_mode, + const struct ia_css_metadata_config *md_config, + const struct ia_css_metadata_info *md_info, + const enum mipi_port_id port_id); + +void +sh_css_sp_uninit_pipeline(unsigned int pipe_num); + +bool sh_css_write_host2sp_command(enum host2sp_commands host2sp_command); + +enum host2sp_commands +sh_css_read_host2sp_command(void); + +void +sh_css_init_host2sp_frame_data(void); + +/** + * @brief Update the offline frame information in host_sp_communication. + * + * @param[in] frame_num The offline frame number. + * @param[in] frame The pointer to the offline frame. + */ +void +sh_css_update_host2sp_offline_frame( + unsigned int frame_num, + struct ia_css_frame *frame, + struct ia_css_metadata *metadata); + +/** + * @brief Update the mipi frame information in host_sp_communication. + * + * @param[in] frame_num The mipi frame number. + * @param[in] frame The pointer to the mipi frame. + */ +void +sh_css_update_host2sp_mipi_frame( + unsigned int frame_num, + struct ia_css_frame *frame); + +/** + * @brief Update the mipi metadata information in host_sp_communication. + * + * @param[in] frame_num The mipi frame number. + * @param[in] metadata The pointer to the mipi metadata. + */ +void +sh_css_update_host2sp_mipi_metadata( + unsigned int frame_num, + struct ia_css_metadata *metadata); + +/** + * @brief Update the nr of mipi frames to use in host_sp_communication. + * + * @param[in] num_frames The number of mipi frames to use. + */ +void +sh_css_update_host2sp_num_mipi_frames(unsigned int num_frames); + +/** + * @brief Update the nr of offline frames to use in host_sp_communication. + * + * @param[in] num_frames The number of raw frames to use. + */ +void +sh_css_update_host2sp_cont_num_raw_frames(unsigned int num_frames, + bool set_avail); + +void +sh_css_event_init_irq_mask(void); + +void +sh_css_sp_start_isp(void); + +void +sh_css_sp_set_sp_running(bool flag); + +bool +sh_css_sp_is_running(void); + +#if SP_DEBUG != SP_DEBUG_NONE + +void +sh_css_sp_get_debug_state(struct sh_css_sp_debug_state *state); + +#endif + +#if !defined(ISP2401) +void +sh_css_sp_set_if_configs( + const input_formatter_cfg_t *config_a, + const input_formatter_cfg_t *config_b, + const uint8_t if_config_index); +#endif + +void +sh_css_sp_program_input_circuit(int fmt_type, + int ch_id, + enum ia_css_input_mode input_mode); + +void +sh_css_sp_configure_sync_gen(int width, + int height, + int hblank_cycles, + int vblank_cycles); + +void +sh_css_sp_configure_tpg(int x_mask, + int y_mask, + int x_delta, + int y_delta, + int xy_mask); + +void +sh_css_sp_configure_prbs(int seed); + +void +sh_css_sp_configure_enable_raw_pool_locking(bool lock_all); + +void +sh_css_sp_enable_isys_event_queue(bool enable); + +void +sh_css_sp_set_disable_continuous_viewfinder(bool flag); + +void +sh_css_sp_reset_global_vars(void); + +/** + * @brief Initialize the DMA software-mask in the debug mode. + * This API should be ONLY called in the debugging mode. + * And it should be always called before the first call of + * "sh_css_set_dma_sw_reg(...)". + * + * @param[in] dma_id The ID of the target DMA. + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool +sh_css_sp_init_dma_sw_reg(int dma_id); + +/** + * @brief Set the DMA software-mask in the debug mode. + * This API should be ONLYL called in the debugging mode. Must + * call "sh_css_set_dma_sw_reg(...)" before this + * API is called for the first time. + * + * @param[in] dma_id The ID of the target DMA. + * @param[in] channel_id The ID of the target DMA channel. + * @param[in] request_type The type of the DMA request. + * For example: + * - "0" indicates the writing request. + * - "1" indicates the reading request. + * + * @param[in] enable If it is "true", the target DMA + * channel is enabled in the software. + * Otherwise, the target DMA channel + * is disabled in the software. + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool +sh_css_sp_set_dma_sw_reg(int dma_id, + int channel_id, + int request_type, + bool enable); + +extern struct sh_css_sp_group sh_css_sp_group; +extern struct sh_css_sp_stage sh_css_sp_stage; +extern struct sh_css_isp_stage sh_css_isp_stage; + +#endif /* _SH_CSS_SP_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_stream_format.c b/drivers/staging/media/atomisp/pci/sh_css_stream_format.c new file mode 100644 index 000000000..a798f0537 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_stream_format.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "sh_css_stream_format.h" +#include + +unsigned int sh_css_stream_format_2_bits_per_subpixel( + enum atomisp_input_format format) +{ + unsigned int rval; + + switch (format) { + case ATOMISP_INPUT_FORMAT_RGB_444: + rval = 4; + break; + case ATOMISP_INPUT_FORMAT_RGB_555: + rval = 5; + break; + case ATOMISP_INPUT_FORMAT_RGB_565: + case ATOMISP_INPUT_FORMAT_RGB_666: + case ATOMISP_INPUT_FORMAT_RAW_6: + rval = 6; + break; + case ATOMISP_INPUT_FORMAT_RAW_7: + rval = 7; + break; + case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: + case ATOMISP_INPUT_FORMAT_YUV420_8: + case ATOMISP_INPUT_FORMAT_YUV422_8: + case ATOMISP_INPUT_FORMAT_RGB_888: + case ATOMISP_INPUT_FORMAT_RAW_8: + case ATOMISP_INPUT_FORMAT_BINARY_8: + case ATOMISP_INPUT_FORMAT_USER_DEF1: + case ATOMISP_INPUT_FORMAT_USER_DEF2: + case ATOMISP_INPUT_FORMAT_USER_DEF3: + case ATOMISP_INPUT_FORMAT_USER_DEF4: + case ATOMISP_INPUT_FORMAT_USER_DEF5: + case ATOMISP_INPUT_FORMAT_USER_DEF6: + case ATOMISP_INPUT_FORMAT_USER_DEF7: + case ATOMISP_INPUT_FORMAT_USER_DEF8: + rval = 8; + break; + case ATOMISP_INPUT_FORMAT_YUV420_10: + case ATOMISP_INPUT_FORMAT_YUV422_10: + case ATOMISP_INPUT_FORMAT_RAW_10: + rval = 10; + break; + case ATOMISP_INPUT_FORMAT_RAW_12: + rval = 12; + break; + case ATOMISP_INPUT_FORMAT_RAW_14: + rval = 14; + break; + case ATOMISP_INPUT_FORMAT_RAW_16: + case ATOMISP_INPUT_FORMAT_YUV420_16: + case ATOMISP_INPUT_FORMAT_YUV422_16: + rval = 16; + break; + default: + rval = 0; + break; + } + + return rval; +} diff --git a/drivers/staging/media/atomisp/pci/sh_css_stream_format.h b/drivers/staging/media/atomisp/pci/sh_css_stream_format.h new file mode 100644 index 000000000..84b794214 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_stream_format.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_STREAM_FORMAT_H +#define __SH_CSS_STREAM_FORMAT_H + +#include + +unsigned int sh_css_stream_format_2_bits_per_subpixel( + enum atomisp_input_format format); + +#endif /* __SH_CSS_STREAM_FORMAT_H */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_struct.h b/drivers/staging/media/atomisp/pci/sh_css_struct.h new file mode 100644 index 000000000..eb8960eba --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_struct.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_STRUCT_H +#define __SH_CSS_STRUCT_H + +/* This header files contains the definition of the + sh_css struct and friends; locigally the file would + probably be called sh_css.h after the pattern + .h but sh_css.h is the predecesssor of ia_css.h + so this could cause confusion; hence the _struct + in the filename +*/ + +#include +#include +#include "ia_css_pipeline.h" +#include "ia_css_pipe_public.h" +#include "ia_css_frame_public.h" +#include "ia_css_queue.h" +#include "ia_css_irq.h" + +struct sh_css { + struct ia_css_pipe *active_pipes[IA_CSS_PIPELINE_NUM_MAX]; + /* All of the pipes created at any point of time. At this moment there can + * be no more than MAX_SP_THREADS of them because pipe_num is reused as SP + * thread_id to which a pipe's pipeline is associated. At a later point, if + * we support more pipe objects, we should add test code to test that + * possibility. Also, active_pipes[] should be able to hold only + * SH_CSS_MAX_SP_THREADS objects. Anything else is misleading. */ + struct ia_css_pipe *all_pipes[IA_CSS_PIPELINE_NUM_MAX]; + void *(*malloc)(size_t bytes, bool zero_mem); + void (*free)(void *ptr); + void (*flush)(struct ia_css_acc_fw *fw); + +/* ISP2401 */ + void *(*malloc_ex)(size_t bytes, bool zero_mem, const char *caller_func, + int caller_line); + void (*free_ex)(void *ptr, const char *caller_func, int caller_line); + +/* ISP2400 */ + bool stop_copy_preview; + + bool check_system_idle; + unsigned int num_cont_raw_frames; + unsigned int num_mipi_frames[N_CSI_PORTS]; + struct ia_css_frame + *mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; + struct ia_css_metadata + *mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; + unsigned int + mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT]; + unsigned int mipi_frame_size[N_CSI_PORTS]; + ia_css_ptr sp_bin_addr; + hrt_data page_table_base_index; + + unsigned int + size_mem_words; /* \deprecated{Use ia_css_mipi_buffer_config instead.}*/ + enum ia_css_irq_type irq_type; + unsigned int pipe_counter; + + unsigned int type; /* 2400 or 2401 for now */ +}; + +#define IPU_2400 1 +#define IPU_2401 2 + +#define IS_2400() (my_css.type == IPU_2400) +#define IS_2401() (my_css.type == IPU_2401) + +extern struct sh_css my_css; + +#endif /* __SH_CSS_STRUCT_H */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_uds.h b/drivers/staging/media/atomisp/pci/sh_css_uds.h new file mode 100644 index 000000000..8d9c5c92b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_uds.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_UDS_H_ +#define _SH_CSS_UDS_H_ + +#include + +#define SIZE_OF_SH_CSS_UDS_INFO_IN_BITS (4 * 16) +#define SIZE_OF_SH_CSS_CROP_POS_IN_BITS (2 * 16) + +/* Uds types, used in pipeline_global.h and sh_css_internal.h */ + +struct sh_css_uds_info { + u16 curr_dx; + u16 curr_dy; + u16 xc; + u16 yc; +}; + +struct sh_css_crop_pos { + u16 x; + u16 y; +}; + +#endif /* _SH_CSS_UDS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/sh_css_version.c b/drivers/staging/media/atomisp/pci/sh_css_version.c new file mode 100644 index 000000000..f5ff8ca66 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/sh_css_version.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "../../include/linux/atomisp.h" +#include "../../include/linux/atomisp_platform.h" +#include "ia_css_version.h" +#include "ia_css_version_data.h" +#include "ia_css_err.h" +#include "sh_css_firmware.h" + +int +ia_css_get_version(char *version, int max_size) +{ + char *css_version; + + if (!IS_ISP2401) + css_version = ISP2400_CSS_VERSION_STRING; + else + css_version = ISP2401_CSS_VERSION_STRING; + + if (max_size <= (int)strlen(css_version) + (int)strlen(sh_css_get_fw_version()) + 5) + return -EINVAL; + strscpy(version, css_version, max_size); + strcat(version, "FW:"); + strcat(version, sh_css_get_fw_version()); + strcat(version, "; "); + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/str2mem_defs.h b/drivers/staging/media/atomisp/pci/str2mem_defs.h new file mode 100644 index 000000000..e8cb456ac --- /dev/null +++ b/drivers/staging/media/atomisp/pci/str2mem_defs.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ST2MEM_DEFS_H +#define _ST2MEM_DEFS_H + +#define _STR2MEM_CRUN_BIT 0x100000 +#define _STR2MEM_CMD_BITS 0x0F0000 +#define _STR2MEM_COUNT_BITS 0x00FFFF + +#define _STR2MEM_BLOCKS_CMD 0xA0000 +#define _STR2MEM_PACKETS_CMD 0xB0000 +#define _STR2MEM_BYTES_CMD 0xC0000 +#define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000 + +#define _STR2MEM_SOFT_RESET_REG_ID 0 +#define _STR2MEM_INPUT_ENDIANNESS_REG_ID 1 +#define _STR2MEM_OUTPUT_ENDIANNESS_REG_ID 2 +#define _STR2MEM_BIT_SWAPPING_REG_ID 3 +#define _STR2MEM_BLOCK_SYNC_LEVEL_REG_ID 4 +#define _STR2MEM_PACKET_SYNC_LEVEL_REG_ID 5 +#define _STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID 6 +#define _STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID 7 +#define _STR2MEM_EN_STAT_UPDATE_ID 8 + +#define _STR2MEM_REG_ALIGN 4 + +#endif /* _ST2MEM_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/streaming_to_mipi_defs.h b/drivers/staging/media/atomisp/pci/streaming_to_mipi_defs.h new file mode 100644 index 000000000..e0e3a6a66 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/streaming_to_mipi_defs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _streaming_to_mipi_defs_h +#define _streaming_to_mipi_defs_h + +#define HIVE_STR_TO_MIPI_VALID_A_BIT 0 +#define HIVE_STR_TO_MIPI_VALID_B_BIT 1 +#define HIVE_STR_TO_MIPI_SOL_BIT 2 +#define HIVE_STR_TO_MIPI_EOL_BIT 3 +#define HIVE_STR_TO_MIPI_SOF_BIT 4 +#define HIVE_STR_TO_MIPI_EOF_BIT 5 +#define HIVE_STR_TO_MIPI_CH_ID_LSB 6 + +#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1) + +#endif /* _streaming_to_mipi_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/system_global.h b/drivers/staging/media/atomisp/pci/system_global.h new file mode 100644 index 000000000..060b92402 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/system_global.h @@ -0,0 +1,380 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (c) 2020 Mauro Carvalho Chehab + */ + +#ifndef __SYSTEM_GLOBAL_H_INCLUDED__ +#define __SYSTEM_GLOBAL_H_INCLUDED__ + +/* + * Create a list of HAS and IS properties that defines the system + * Those are common for both ISP2400 and ISP2401 + * + * The configuration assumes the following + * - The system is hetereogeneous; Multiple cells and devices classes + * - The cell and device instances are homogeneous, each device type + * belongs to the same class + * - Device instances supporting a subset of the class capabilities are + * allowed + * + * We could manage different device classes through the enumerated + * lists (C) or the use of classes (C++), but that is presently not + * fully supported + * + * N.B. the 3 input formatters are of 2 different classess + */ + +#define DMA_DDR_TO_VAMEM_WORKAROUND +#define DMA_DDR_TO_HMEM_WORKAROUND + +/* + * The longest allowed (uninteruptible) bus transfer, does not + * take stalling into account + */ +#define HIVE_ISP_MAX_BURST_LENGTH 1024 + +/* + * Maximum allowed burst length in words for the ISP DMA + * This value is set to 2 to prevent the ISP DMA from blocking + * the bus for too long; as the input system can only buffer + * 2 lines on Moorefield and Cherrytrail, the input system buffers + * may overflow if blocked for too long (BZ 2726). + */ +#define ISP2400_DMA_MAX_BURST_LENGTH 128 +#define ISP2401_DMA_MAX_BURST_LENGTH 2 + +#include +#include + +/* This interface is deprecated */ +#include "hive_types.h" + +/* + * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply + */ +#define HRT_VADDRESS_WIDTH 32 + +#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3) +#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8) + +/* The main bus connecting all devices */ +#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH +#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES + +typedef u32 hrt_bus_align_t; + +/* + * Enumerate the devices, device access through the API is by ID, + * through the DLI by address. The enumerator terminators are used + * to size the wiring arrays and as an exception value. + */ +typedef enum { + DDR0_ID = 0, + N_DDR_ID +} ddr_ID_t; + +typedef enum { + ISP0_ID = 0, + N_ISP_ID +} isp_ID_t; + +typedef enum { + SP0_ID = 0, + N_SP_ID +} sp_ID_t; + +typedef enum { + MMU0_ID = 0, + MMU1_ID, + N_MMU_ID +} mmu_ID_t; + +typedef enum { + DMA0_ID = 0, + N_DMA_ID +} dma_ID_t; + +typedef enum { + GDC0_ID = 0, + GDC1_ID, + N_GDC_ID +} gdc_ID_t; + +/* this extra define is needed because we want to use it also + in the preprocessor, and that doesn't work with enums. + */ +#define N_GDC_ID_CPP 2 + +typedef enum { + VAMEM0_ID = 0, + VAMEM1_ID, + VAMEM2_ID, + N_VAMEM_ID +} vamem_ID_t; + +typedef enum { + BAMEM0_ID = 0, + N_BAMEM_ID +} bamem_ID_t; + +typedef enum { + HMEM0_ID = 0, + N_HMEM_ID +} hmem_ID_t; + +typedef enum { + IRQ0_ID = 0, /* GP IRQ block */ + IRQ1_ID, /* Input formatter */ + IRQ2_ID, /* input system */ + IRQ3_ID, /* input selector */ + N_IRQ_ID +} irq_ID_t; + +typedef enum { + FIFO_MONITOR0_ID = 0, + N_FIFO_MONITOR_ID +} fifo_monitor_ID_t; + +typedef enum { + GP_DEVICE0_ID = 0, + N_GP_DEVICE_ID +} gp_device_ID_t; + +typedef enum { + GP_TIMER0_ID = 0, + GP_TIMER1_ID, + GP_TIMER2_ID, + GP_TIMER3_ID, + GP_TIMER4_ID, + GP_TIMER5_ID, + GP_TIMER6_ID, + GP_TIMER7_ID, + N_GP_TIMER_ID +} gp_timer_ID_t; + +typedef enum { + GPIO0_ID = 0, + N_GPIO_ID +} gpio_ID_t; + +typedef enum { + TIMED_CTRL0_ID = 0, + N_TIMED_CTRL_ID +} timed_ctrl_ID_t; + +typedef enum { + INPUT_FORMATTER0_ID = 0, + INPUT_FORMATTER1_ID, + INPUT_FORMATTER2_ID, + INPUT_FORMATTER3_ID, + N_INPUT_FORMATTER_ID +} input_formatter_ID_t; + +/* The IF RST is outside the IF */ +#define INPUT_FORMATTER0_SRST_OFFSET 0x0824 +#define INPUT_FORMATTER1_SRST_OFFSET 0x0624 +#define INPUT_FORMATTER2_SRST_OFFSET 0x0424 +#define INPUT_FORMATTER3_SRST_OFFSET 0x0224 + +#define INPUT_FORMATTER0_SRST_MASK 0x0001 +#define INPUT_FORMATTER1_SRST_MASK 0x0002 +#define INPUT_FORMATTER2_SRST_MASK 0x0004 +#define INPUT_FORMATTER3_SRST_MASK 0x0008 + +typedef enum { + INPUT_SYSTEM0_ID = 0, + N_INPUT_SYSTEM_ID +} input_system_ID_t; + +typedef enum { + RX0_ID = 0, + N_RX_ID +} rx_ID_t; + +enum mipi_port_id { + MIPI_PORT0_ID = 0, + MIPI_PORT1_ID, + MIPI_PORT2_ID, + N_MIPI_PORT_ID +}; + +#define N_RX_CHANNEL_ID 4 + +/* Generic port enumeration with an internal port type ID */ +typedef enum { + CSI_PORT0_ID = 0, + CSI_PORT1_ID, + CSI_PORT2_ID, + TPG_PORT0_ID, + PRBS_PORT0_ID, + FIFO_PORT0_ID, + MEMORY_PORT0_ID, + N_INPUT_PORT_ID +} input_port_ID_t; + +typedef enum { + CAPTURE_UNIT0_ID = 0, + CAPTURE_UNIT1_ID, + CAPTURE_UNIT2_ID, + ACQUISITION_UNIT0_ID, + DMA_UNIT0_ID, + CTRL_UNIT0_ID, + GPREGS_UNIT0_ID, + FIFO_UNIT0_ID, + IRQ_UNIT0_ID, + N_SUB_SYSTEM_ID +} sub_system_ID_t; + +#define N_CAPTURE_UNIT_ID 3 +#define N_ACQUISITION_UNIT_ID 1 +#define N_CTRL_UNIT_ID 1 + + +enum ia_css_isp_memories { + IA_CSS_ISP_PMEM0 = 0, + IA_CSS_ISP_DMEM0, + IA_CSS_ISP_VMEM0, + IA_CSS_ISP_VAMEM0, + IA_CSS_ISP_VAMEM1, + IA_CSS_ISP_VAMEM2, + IA_CSS_ISP_HMEM0, + IA_CSS_SP_DMEM0, + IA_CSS_DDR, + N_IA_CSS_MEMORIES +}; + +#define IA_CSS_NUM_MEMORIES 9 +/* For driver compatibility */ +#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES +#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES + +/* + * ISP2401 specific enums + */ + +typedef enum { + ISYS_IRQ0_ID = 0, /* port a */ + ISYS_IRQ1_ID, /* port b */ + ISYS_IRQ2_ID, /* port c */ + N_ISYS_IRQ_ID +} isys_irq_ID_t; + + +/* + * Input-buffer Controller. + */ +typedef enum { + IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */ + IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */ + IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */ + N_IBUF_CTRL_ID +} ibuf_ctrl_ID_t; +/* end of Input-buffer Controller */ + +/* + * Stream2MMIO. + */ +typedef enum { + STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */ + STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */ + STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */ + N_STREAM2MMIO_ID +} stream2mmio_ID_t; + +typedef enum { + /* + * Stream2MMIO 0 has 8 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID]. + * + * Stream2MMIO 1 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID]. + * + * Stream2MMIO 2 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID]. + */ + STREAM2MMIO_SID0_ID = 0, + STREAM2MMIO_SID1_ID, + STREAM2MMIO_SID2_ID, + STREAM2MMIO_SID3_ID, + STREAM2MMIO_SID4_ID, + STREAM2MMIO_SID5_ID, + STREAM2MMIO_SID6_ID, + STREAM2MMIO_SID7_ID, + N_STREAM2MMIO_SID_ID +} stream2mmio_sid_ID_t; +/* end of Stream2MMIO */ + +/** + * Input System 2401: CSI-MIPI recevier. + */ +typedef enum { + CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */ + CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */ + CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */ + N_CSI_RX_BACKEND_ID +} csi_rx_backend_ID_t; + +typedef enum { + CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */ + CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */ + CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */ +#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1) +} csi_rx_frontend_ID_t; + +typedef enum { + CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */ + CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */ + CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */ + CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */ + N_CSI_RX_DLANE_ID +} csi_rx_fe_dlane_ID_t; +/* end of CSI-MIPI receiver */ + +typedef enum { + ISYS2401_DMA0_ID = 0, + N_ISYS2401_DMA_ID +} isys2401_dma_ID_t; + +/** + * Pixel-generator. ("system_global.h") + */ +typedef enum { + PIXELGEN0_ID = 0, + PIXELGEN1_ID, + PIXELGEN2_ID, + N_PIXELGEN_ID +} pixelgen_ID_t; +/* end of pixel-generator. ("system_global.h") */ + +typedef enum { + INPUT_SYSTEM_CSI_PORT0_ID = 0, + INPUT_SYSTEM_CSI_PORT1_ID, + INPUT_SYSTEM_CSI_PORT2_ID, + + INPUT_SYSTEM_PIXELGEN_PORT0_ID, + INPUT_SYSTEM_PIXELGEN_PORT1_ID, + INPUT_SYSTEM_PIXELGEN_PORT2_ID, + + N_INPUT_SYSTEM_INPUT_PORT_ID +} input_system_input_port_ID_t; + +#define N_INPUT_SYSTEM_CSI_PORT 3 + +typedef enum { + ISYS2401_DMA_CHANNEL_0 = 0, + ISYS2401_DMA_CHANNEL_1, + ISYS2401_DMA_CHANNEL_2, + ISYS2401_DMA_CHANNEL_3, + ISYS2401_DMA_CHANNEL_4, + ISYS2401_DMA_CHANNEL_5, + ISYS2401_DMA_CHANNEL_6, + ISYS2401_DMA_CHANNEL_7, + ISYS2401_DMA_CHANNEL_8, + ISYS2401_DMA_CHANNEL_9, + ISYS2401_DMA_CHANNEL_10, + ISYS2401_DMA_CHANNEL_11, + N_ISYS2401_DMA_CHANNEL +} isys2401_dma_channel; + +#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/system_local.c b/drivers/staging/media/atomisp/pci/system_local.c new file mode 100644 index 000000000..4ca8569d7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/system_local.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_local.h" + +/* ISP */ +const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { + 0x0000000000020000ULL +}; + +const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { + 0x0000000000200000ULL +}; + +const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { + 0x0000000000100000ULL +}; + +/* SP */ +const hrt_address SP_CTRL_BASE[N_SP_ID] = { + 0x0000000000010000ULL +}; + +const hrt_address SP_DMEM_BASE[N_SP_ID] = { + 0x0000000000300000ULL +}; + +/* MMU */ +/* + * MMU0_ID: The data MMU + * MMU1_ID: The icache MMU + */ +const hrt_address MMU_BASE[N_MMU_ID] = { + 0x0000000000070000ULL, + 0x00000000000A0000ULL +}; + +/* DMA */ +const hrt_address DMA_BASE[N_DMA_ID] = { + 0x0000000000040000ULL +}; + +const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = { + 0x00000000000CA000ULL +}; + +/* IRQ */ +const hrt_address IRQ_BASE[N_IRQ_ID] = { + 0x0000000000000500ULL, + 0x0000000000030A00ULL, + 0x000000000008C000ULL, + 0x0000000000090200ULL +}; + +/* + 0x0000000000000500ULL}; + */ + +/* GDC */ +const hrt_address GDC_BASE[N_GDC_ID] = { + 0x0000000000050000ULL, + 0x0000000000060000ULL +}; + +/* FIFO_MONITOR (not a subset of GP_DEVICE) */ +const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { + 0x0000000000000000ULL +}; + +/* +const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { + 0x0000000000000000ULL}; + +const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x0000000000090000ULL}; +*/ + +/* GP_DEVICE (single base for all separate GP_REG instances) */ +const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x0000000000000000ULL +}; + +/*GP TIMER , all timer registers are inter-twined, + * so, having multiple base addresses for + * different timers does not help*/ +const hrt_address GP_TIMER_BASE = + (hrt_address)0x0000000000000600ULL; + +/* GPIO */ +const hrt_address GPIO_BASE[N_GPIO_ID] = { + 0x0000000000000400ULL +}; + +/* TIMED_CTRL */ +const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { + 0x0000000000000100ULL +}; + +/* INPUT_FORMATTER */ +const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { + 0x0000000000030000ULL, + 0x0000000000030200ULL, + 0x0000000000030400ULL, + 0x0000000000030600ULL +}; /* memcpy() */ + +/* INPUT_SYSTEM */ +const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { + 0x0000000000080000ULL +}; + +/* 0x0000000000081000ULL, */ /* capture A */ +/* 0x0000000000082000ULL, */ /* capture B */ +/* 0x0000000000083000ULL, */ /* capture C */ +/* 0x0000000000084000ULL, */ /* Acquisition */ +/* 0x0000000000085000ULL, */ /* DMA */ +/* 0x0000000000089000ULL, */ /* ctrl */ +/* 0x000000000008A000ULL, */ /* GP regs */ +/* 0x000000000008B000ULL, */ /* FIFO */ +/* 0x000000000008C000ULL, */ /* IRQ */ + +/* RX, the MIPI lane control regs start at offset 0 */ +const hrt_address RX_BASE[N_RX_ID] = { + 0x0000000000080100ULL +}; + +/* IBUF_CTRL, part of the Input System 2401 */ +const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = { + 0x00000000000C1800ULL, /* ibuf controller A */ + 0x00000000000C3800ULL, /* ibuf controller B */ + 0x00000000000C5800ULL /* ibuf controller C */ +}; + +/* ISYS IRQ Controllers, part of the Input System 2401 */ +const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = { + 0x00000000000C1400ULL, /* port a */ + 0x00000000000C3400ULL, /* port b */ + 0x00000000000C5400ULL /* port c */ +}; + +/* CSI FE, part of the Input System 2401 */ +const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = { + 0x00000000000C0400ULL, /* csi fe controller A */ + 0x00000000000C2400ULL, /* csi fe controller B */ + 0x00000000000C4400ULL /* csi fe controller C */ +}; + +/* CSI BE, part of the Input System 2401 */ +const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = { + 0x00000000000C0800ULL, /* csi be controller A */ + 0x00000000000C2800ULL, /* csi be controller B */ + 0x00000000000C4800ULL /* csi be controller C */ +}; + +/* PIXEL Generator, part of the Input System 2401 */ +const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = { + 0x00000000000C1000ULL, /* pixel gen controller A */ + 0x00000000000C3000ULL, /* pixel gen controller B */ + 0x00000000000C5000ULL /* pixel gen controller C */ +}; + +/* Stream2MMIO, part of the Input System 2401 */ +const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = { + 0x00000000000C0C00ULL, /* stream2mmio controller A */ + 0x00000000000C2C00ULL, /* stream2mmio controller B */ + 0x00000000000C4C00ULL /* stream2mmio controller C */ +}; diff --git a/drivers/staging/media/atomisp/pci/system_local.h b/drivers/staging/media/atomisp/pci/system_local.h new file mode 100644 index 000000000..a47258c2e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/system_local.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SYSTEM_LOCAL_H_INCLUDED__ +#define __SYSTEM_LOCAL_H_INCLUDED__ + +#ifdef HRT_ISP_CSS_CUSTOM_HOST +#ifndef HRT_USE_VIR_ADDRS +#define HRT_USE_VIR_ADDRS +#endif +#endif + +#include "system_global.h" + +/* This interface is deprecated */ +#include "hive_types.h" + +/* + * Cell specific address maps + */ + +#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */ + +/* ISP */ +extern const hrt_address ISP_CTRL_BASE[N_ISP_ID]; +extern const hrt_address ISP_DMEM_BASE[N_ISP_ID]; +extern const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID]; + +/* SP */ +extern const hrt_address SP_CTRL_BASE[N_SP_ID]; +extern const hrt_address SP_DMEM_BASE[N_SP_ID]; + +/* MMU */ + +extern const hrt_address MMU_BASE[N_MMU_ID]; + +/* DMA */ +extern const hrt_address DMA_BASE[N_DMA_ID]; +extern const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID]; + +/* IRQ */ +extern const hrt_address IRQ_BASE[N_IRQ_ID]; + +/* GDC */ +extern const hrt_address GDC_BASE[N_GDC_ID]; + +/* FIFO_MONITOR (not a subset of GP_DEVICE) */ +extern const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID]; + +/* GP_DEVICE (single base for all separate GP_REG instances) */ +extern const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID]; + +/*GP TIMER , all timer registers are inter-twined, + * so, having multiple base addresses for + * different timers does not help*/ +extern const hrt_address GP_TIMER_BASE; + +/* GPIO */ +extern const hrt_address GPIO_BASE[N_GPIO_ID]; + +/* TIMED_CTRL */ +extern const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID]; + +/* INPUT_FORMATTER */ +extern const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID]; + +/* INPUT_SYSTEM */ +extern const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID]; + +/* RX, the MIPI lane control regs start at offset 0 */ +extern const hrt_address RX_BASE[N_RX_ID]; + +/* IBUF_CTRL, part of the Input System 2401 */ +extern const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID]; + +/* ISYS IRQ Controllers, part of the Input System 2401 */ +extern const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID]; + +/* CSI FE, part of the Input System 2401 */ +extern const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID]; + +/* CSI BE, part of the Input System 2401 */ +extern const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID]; + +/* PIXEL Generator, part of the Input System 2401 */ +extern const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID]; + +/* Stream2MMIO, part of the Input System 2401 */ +extern const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID]; + +#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/timed_controller_defs.h b/drivers/staging/media/atomisp/pci/timed_controller_defs.h new file mode 100644 index 000000000..9ddad8770 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/timed_controller_defs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _timed_controller_defs_h +#define _timed_controller_defs_h + +#define _HRT_TIMED_CONTROLLER_CMD_REG_IDX 0 + +#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4 + +#endif /* _timed_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/version.h b/drivers/staging/media/atomisp/pci/version.h new file mode 100644 index 000000000..a74a7bbfd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/version.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_VERSION_H +#define HRT_VERSION_H +#define HRT_VERSION_MAJOR 1 +#define HRT_VERSION_MINOR 4 +#define HRT_VERSION 1_4 +#endif diff --git a/drivers/staging/media/deprecated/atmel/Kconfig b/drivers/staging/media/deprecated/atmel/Kconfig new file mode 100644 index 000000000..418841ea5 --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/Kconfig @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only + +comment "Atmel media platform drivers" + +config VIDEO_ATMEL_ISC + tristate "ATMEL Image Sensor Controller (ISC) support (DEPRECATED)" + depends on V4L_PLATFORM_DRIVERS + depends on VIDEO_DEV && COMMON_CLK + depends on ARCH_AT91 || COMPILE_TEST + depends on !VIDEO_MICROCHIP_ISC_BASE || COMPILE_TEST + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + select V4L2_FWNODE + select VIDEO_ATMEL_ISC_BASE + help + This module makes the ATMEL Image Sensor Controller available + as a v4l2 device. + + This driver is deprecated and is scheduled for removal by + the beginning of 2026. See the TODO file for more information. + +config VIDEO_ATMEL_XISC + tristate "ATMEL eXtended Image Sensor Controller (XISC) support (DEPRECATED)" + depends on V4L_PLATFORM_DRIVERS + depends on VIDEO_DEV && COMMON_CLK + depends on ARCH_AT91 || COMPILE_TEST + depends on !VIDEO_MICROCHIP_ISC_BASE || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + select V4L2_FWNODE + select VIDEO_ATMEL_ISC_BASE + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + help + This module makes the ATMEL eXtended Image Sensor Controller + available as a v4l2 device. + + This driver is deprecated and is scheduled for removal by + the beginning of 2026. See the TODO file for more information. + +config VIDEO_ATMEL_ISC_BASE + tristate + default n + help + ATMEL ISC and XISC common code base. diff --git a/drivers/staging/media/deprecated/atmel/Makefile b/drivers/staging/media/deprecated/atmel/Makefile new file mode 100644 index 000000000..34eaeeac5 --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +atmel-isc-objs = atmel-sama5d2-isc.o +atmel-xisc-objs = atmel-sama7g5-isc.o +atmel-isc-common-objs = atmel-isc-base.o atmel-isc-clk.o + +obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-common.o +obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o +obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o diff --git a/drivers/staging/media/deprecated/atmel/TODO b/drivers/staging/media/deprecated/atmel/TODO new file mode 100644 index 000000000..71691df07 --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/TODO @@ -0,0 +1,34 @@ +The Atmel ISC driver is not compliant with media controller specification. +In order to evolve this driver, it has to move to media controller, to +support enhanced features and future products which embed it. +The move to media controller involves several changes which are +not backwards compatible with the current usability of the driver. + +The best example is the way the format is propagated from the top video +driver /dev/videoX down to the sensor. + +In a simple configuration sensor ==> isc , the isc just calls subdev s_fmt +and controls the sensor directly. This is achieved by having a lot of code +inside the driver that will query the subdev at probe time and make a list +of formats which are usable. +Basically the user has nothing to configure, as the isc will handle +everything at the top level. This is an easy way to capture, but also comes +with the drawback of lack of flexibility. +In a more complicated pipeline +sensor ==> controller 1 ==> controller 2 ==> isc +this will not be achievable, as controller 1 and controller 2 might be +media-controller configurable, and will not propagate the formats down to +the sensor. + +After discussions with the media maintainers, the decision is to move +Atmel ISC to staging as-is, to keep the Kconfig symbols and the users +to the driver in staging. Thus, all the existing users of the non +media-controller paradigm will continue to be happy and use the old config +way. + +The new driver was added in the media subsystem with a different +symbol, with the conversion to media controller done, and new users +of the driver will be able to use all the new features. + +The replacement driver is named VIDEO_MICROCHIP_ISC or +VIDEO_MICROCHIP_XISC depending on the product flavor. diff --git a/drivers/staging/media/deprecated/atmel/atmel-isc-base.c b/drivers/staging/media/deprecated/atmel/atmel-isc-base.c new file mode 100644 index 000000000..99e61bbfc --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/atmel-isc-base.c @@ -0,0 +1,2011 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Microchip Image Sensor Controller (ISC) common driver base + * + * Copyright (C) 2016-2019 Microchip Technology, Inc. + * + * Author: Songjun Wu + * Author: Eugen Hristev + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "atmel-isc-regs.h" +#include "atmel-isc.h" + +static unsigned int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "debug level (0-2)"); + +static unsigned int sensor_preferred = 1; +module_param(sensor_preferred, uint, 0644); +MODULE_PARM_DESC(sensor_preferred, + "Sensor is preferred to output the specified format (1-on 0-off), default 1"); + +#define ISC_IS_FORMAT_RAW(mbus_code) \ + (((mbus_code) & 0xf000) == 0x3000) + +#define ISC_IS_FORMAT_GREY(mbus_code) \ + (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \ + (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8))) + +static inline void isc_update_v4l2_ctrls(struct isc_device *isc) +{ + struct isc_ctrls *ctrls = &isc->ctrls; + + /* In here we set the v4l2 controls w.r.t. our pipeline config */ + v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]); + v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]); + v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]); + v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]); + + v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]); + v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]); + v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]); + v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]); +} + +static inline void isc_update_awb_ctrls(struct isc_device *isc) +{ + struct isc_ctrls *ctrls = &isc->ctrls; + + /* In here we set our actual hw pipeline config */ + + regmap_write(isc->regmap, ISC_WB_O_RGR, + ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | + ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + regmap_write(isc->regmap, ISC_WB_O_BGB, + ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | + ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + regmap_write(isc->regmap, ISC_WB_G_RGR, + ctrls->gain[ISC_HIS_CFG_MODE_R] | + (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + regmap_write(isc->regmap, ISC_WB_G_BGB, + ctrls->gain[ISC_HIS_CFG_MODE_B] | + (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); +} + +static inline void isc_reset_awb_ctrls(struct isc_device *isc) +{ + unsigned int c; + + for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) { + /* gains have a fixed point at 9 decimals */ + isc->ctrls.gain[c] = 1 << 9; + /* offsets are in 2's complements */ + isc->ctrls.offset[c] = 0; + } +} + + +static int isc_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct isc_device *isc = vb2_get_drv_priv(vq); + unsigned int size = isc->fmt.fmt.pix.sizeimage; + + if (*nplanes) + return sizes[0] < size ? -EINVAL : 0; + + *nplanes = 1; + sizes[0] = size; + + return 0; +} + +static int isc_buffer_prepare(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); + unsigned long size = isc->fmt.fmt.pix.sizeimage; + + if (vb2_plane_size(vb, 0) < size) { + v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n", + vb2_plane_size(vb, 0), size); + return -EINVAL; + } + + vb2_set_plane_payload(vb, 0, size); + + vbuf->field = isc->fmt.fmt.pix.field; + + return 0; +} + +static void isc_crop_pfe(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + u32 h, w; + + h = isc->fmt.fmt.pix.height; + w = isc->fmt.fmt.pix.width; + + /* + * In case the sensor is not RAW, it will output a pixel (12-16 bits) + * with two samples on the ISC Data bus (which is 8-12) + * ISC will count each sample, so, we need to multiply these values + * by two, to get the real number of samples for the required pixels. + */ + if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) { + h <<= 1; + w <<= 1; + } + + /* + * We limit the column/row count that the ISC will output according + * to the configured resolution that we want. + * This will avoid the situation where the sensor is misconfigured, + * sending more data, and the ISC will just take it and DMA to memory, + * causing corruption. + */ + regmap_write(regmap, ISC_PFE_CFG1, + (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) | + (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK)); + + regmap_write(regmap, ISC_PFE_CFG2, + (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) | + (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK)); + + regmap_update_bits(regmap, ISC_PFE_CFG0, + ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN, + ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN); +} + +static void isc_start_dma(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + u32 sizeimage = isc->fmt.fmt.pix.sizeimage; + u32 dctrl_dview; + dma_addr_t addr0; + + addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); + regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0); + + switch (isc->config.fourcc) { + case V4L2_PIX_FMT_YUV420: + regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, + addr0 + (sizeimage * 2) / 3); + regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, + addr0 + (sizeimage * 5) / 6); + break; + case V4L2_PIX_FMT_YUV422P: + regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, + addr0 + sizeimage / 2); + regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, + addr0 + (sizeimage * 3) / 4); + break; + default: + break; + } + + dctrl_dview = isc->config.dctrl_dview; + + regmap_write(regmap, ISC_DCTRL + isc->offsets.dma, + dctrl_dview | ISC_DCTRL_IE_IS); + spin_lock(&isc->awb_lock); + regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE); + spin_unlock(&isc->awb_lock); +} + +static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) +{ + struct regmap *regmap = isc->regmap; + struct isc_ctrls *ctrls = &isc->ctrls; + u32 val, bay_cfg; + const u32 *gamma; + unsigned int i; + + /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ + for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { + val = pipeline & BIT(i) ? 1 : 0; + regmap_field_write(isc->pipeline[i], val); + } + + if (!pipeline) + return; + + bay_cfg = isc->config.sd_format->cfa_baycfg; + + regmap_write(regmap, ISC_WB_CFG, bay_cfg); + isc_update_awb_ctrls(isc); + isc_update_v4l2_ctrls(isc); + + regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL); + + gamma = &isc->gamma_table[ctrls->gamma_index][0]; + regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES); + regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); + regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); + + isc->config_dpc(isc); + isc->config_csc(isc); + isc->config_cbc(isc); + isc->config_cc(isc); + isc->config_gam(isc); +} + +static int isc_update_profile(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + u32 sr; + int counter = 100; + + regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO); + + regmap_read(regmap, ISC_CTRLSR, &sr); + while ((sr & ISC_CTRL_UPPRO) && counter--) { + usleep_range(1000, 2000); + regmap_read(regmap, ISC_CTRLSR, &sr); + } + + if (counter < 0) { + v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void isc_set_histogram(struct isc_device *isc, bool enable) +{ + struct regmap *regmap = isc->regmap; + struct isc_ctrls *ctrls = &isc->ctrls; + + if (enable) { + regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, + ISC_HIS_CFG_MODE_GR | + (isc->config.sd_format->cfa_baycfg + << ISC_HIS_CFG_BAYSEL_SHIFT) | + ISC_HIS_CFG_RAR); + regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, + ISC_HIS_CTRL_EN); + regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE); + ctrls->hist_id = ISC_HIS_CFG_MODE_GR; + isc_update_profile(isc); + regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); + + ctrls->hist_stat = HIST_ENABLED; + } else { + regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE); + regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, + ISC_HIS_CTRL_DIS); + + ctrls->hist_stat = HIST_DISABLED; + } +} + +static int isc_configure(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + u32 pfe_cfg0, dcfg, mask, pipeline; + struct isc_subdev_entity *subdev = isc->current_subdev; + + pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; + pipeline = isc->config.bits_pipeline; + + dcfg = isc->config.dcfg_imode | isc->dcfg; + + pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; + mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | + ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW | + ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC | + ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI; + + regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); + + isc->config_rlp(isc); + + regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); + + /* Set the pipeline */ + isc_set_pipeline(isc, pipeline); + + /* + * The current implemented histogram is available for RAW R, B, GB, GR + * channels. We need to check if sensor is outputting RAW BAYER + */ + if (isc->ctrls.awb && + ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) + isc_set_histogram(isc, true); + else + isc_set_histogram(isc, false); + + /* Update profile */ + return isc_update_profile(isc); +} + +static int isc_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct isc_device *isc = vb2_get_drv_priv(vq); + struct regmap *regmap = isc->regmap; + struct isc_buffer *buf; + unsigned long flags; + int ret; + + /* Enable stream on the sub device */ + ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1); + if (ret && ret != -ENOIOCTLCMD) { + v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n", + ret); + goto err_start_stream; + } + + ret = pm_runtime_resume_and_get(isc->dev); + if (ret < 0) { + v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n", + ret); + goto err_pm_get; + } + + ret = isc_configure(isc); + if (unlikely(ret)) + goto err_configure; + + /* Enable DMA interrupt */ + regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE); + + spin_lock_irqsave(&isc->dma_queue_lock, flags); + + isc->sequence = 0; + isc->stop = false; + reinit_completion(&isc->comp); + + isc->cur_frm = list_first_entry(&isc->dma_queue, + struct isc_buffer, list); + list_del(&isc->cur_frm->list); + + isc_crop_pfe(isc); + isc_start_dma(isc); + + spin_unlock_irqrestore(&isc->dma_queue_lock, flags); + + /* if we streaming from RAW, we can do one-shot white balance adj */ + if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) + v4l2_ctrl_activate(isc->do_wb_ctrl, true); + + return 0; + +err_configure: + pm_runtime_put_sync(isc->dev); +err_pm_get: + v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); + +err_start_stream: + spin_lock_irqsave(&isc->dma_queue_lock, flags); + list_for_each_entry(buf, &isc->dma_queue, list) + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + INIT_LIST_HEAD(&isc->dma_queue); + spin_unlock_irqrestore(&isc->dma_queue_lock, flags); + + return ret; +} + +static void isc_stop_streaming(struct vb2_queue *vq) +{ + struct isc_device *isc = vb2_get_drv_priv(vq); + unsigned long flags; + struct isc_buffer *buf; + int ret; + + mutex_lock(&isc->awb_mutex); + v4l2_ctrl_activate(isc->do_wb_ctrl, false); + + isc->stop = true; + + /* Wait until the end of the current frame */ + if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ)) + v4l2_err(&isc->v4l2_dev, + "Timeout waiting for end of the capture\n"); + + mutex_unlock(&isc->awb_mutex); + + /* Disable DMA interrupt */ + regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); + + pm_runtime_put_sync(isc->dev); + + /* Disable stream on the sub device */ + ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); + if (ret && ret != -ENOIOCTLCMD) + v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n"); + + /* Release all active buffers */ + spin_lock_irqsave(&isc->dma_queue_lock, flags); + if (unlikely(isc->cur_frm)) { + vb2_buffer_done(&isc->cur_frm->vb.vb2_buf, + VB2_BUF_STATE_ERROR); + isc->cur_frm = NULL; + } + list_for_each_entry(buf, &isc->dma_queue, list) + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + INIT_LIST_HEAD(&isc->dma_queue); + spin_unlock_irqrestore(&isc->dma_queue_lock, flags); +} + +static void isc_buffer_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb); + struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); + unsigned long flags; + + spin_lock_irqsave(&isc->dma_queue_lock, flags); + if (!isc->cur_frm && list_empty(&isc->dma_queue) && + vb2_start_streaming_called(vb->vb2_queue)) { + isc->cur_frm = buf; + isc_start_dma(isc); + } else + list_add_tail(&buf->list, &isc->dma_queue); + spin_unlock_irqrestore(&isc->dma_queue_lock, flags); +} + +static struct isc_format *find_format_by_fourcc(struct isc_device *isc, + unsigned int fourcc) +{ + unsigned int num_formats = isc->num_user_formats; + struct isc_format *fmt; + unsigned int i; + + for (i = 0; i < num_formats; i++) { + fmt = isc->user_formats[i]; + if (fmt->fourcc == fourcc) + return fmt; + } + + return NULL; +} + +static const struct vb2_ops isc_vb2_ops = { + .queue_setup = isc_queue_setup, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .buf_prepare = isc_buffer_prepare, + .start_streaming = isc_start_streaming, + .stop_streaming = isc_stop_streaming, + .buf_queue = isc_buffer_queue, +}; + +static int isc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct isc_device *isc = video_drvdata(file); + + strscpy(cap->driver, "microchip-isc", sizeof(cap->driver)); + strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), + "platform:%s", isc->v4l2_dev.name); + + return 0; +} + +static int isc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct isc_device *isc = video_drvdata(file); + u32 index = f->index; + u32 i, supported_index; + + if (index < isc->controller_formats_size) { + f->pixelformat = isc->controller_formats[index].fourcc; + return 0; + } + + index -= isc->controller_formats_size; + + supported_index = 0; + + for (i = 0; i < isc->formats_list_size; i++) { + if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) || + !isc->formats_list[i].sd_support) + continue; + if (supported_index == index) { + f->pixelformat = isc->formats_list[i].fourcc; + return 0; + } + supported_index++; + } + + return -EINVAL; +} + +static int isc_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct isc_device *isc = video_drvdata(file); + + *fmt = isc->fmt; + + return 0; +} + +/* + * Checks the current configured format, if ISC can output it, + * considering which type of format the ISC receives from the sensor + */ +static int isc_try_validate_formats(struct isc_device *isc) +{ + int ret; + bool bayer = false, yuv = false, rgb = false, grey = false; + + /* all formats supported by the RLP module are OK */ + switch (isc->try_config.fourcc) { + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + ret = 0; + bayer = true; + break; + + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: + ret = 0; + yuv = true; + break; + + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_ABGR32: + case V4L2_PIX_FMT_XBGR32: + case V4L2_PIX_FMT_ARGB444: + case V4L2_PIX_FMT_ARGB555: + ret = 0; + rgb = true; + break; + case V4L2_PIX_FMT_GREY: + case V4L2_PIX_FMT_Y10: + case V4L2_PIX_FMT_Y16: + ret = 0; + grey = true; + break; + default: + /* any other different formats are not supported */ + ret = -EINVAL; + } + v4l2_dbg(1, debug, &isc->v4l2_dev, + "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n", + rgb, yuv, grey, bayer); + + /* we cannot output RAW if we do not receive RAW */ + if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) + return -EINVAL; + + /* we cannot output GREY if we do not receive RAW/GREY */ + if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) && + !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) + return -EINVAL; + + return ret; +} + +/* + * Configures the RLP and DMA modules, depending on the output format + * configured for the ISC. + * If direct_dump == true, just dump raw data 8/16 bits depending on format. + */ +static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) +{ + isc->try_config.rlp_cfg_mode = 0; + + switch (isc->try_config.fourcc) { + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 8; + isc->try_config.bpp_v4l2 = 8; + break; + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + case V4L2_PIX_FMT_RGB565: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + case V4L2_PIX_FMT_ARGB444: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + case V4L2_PIX_FMT_ARGB555: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + case V4L2_PIX_FMT_ABGR32: + case V4L2_PIX_FMT_XBGR32: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 32; + isc->try_config.bpp_v4l2 = 32; + break; + case V4L2_PIX_FMT_YUV420: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; + isc->try_config.bpp = 12; + isc->try_config.bpp_v4l2 = 8; /* only first plane */ + break; + case V4L2_PIX_FMT_YUV422P: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 8; /* only first plane */ + break; + case V4L2_PIX_FMT_YUYV: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + case V4L2_PIX_FMT_UYVY: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + case V4L2_PIX_FMT_VYUY: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + case V4L2_PIX_FMT_GREY: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 8; + isc->try_config.bpp_v4l2 = 8; + break; + case V4L2_PIX_FMT_Y16: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; + fallthrough; + case V4L2_PIX_FMT_Y10: + isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + isc->try_config.bpp_v4l2 = 16; + break; + default: + return -EINVAL; + } + + if (direct_dump) { + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + return 0; + } + + return 0; +} + +/* + * Configuring pipeline modules, depending on which format the ISC outputs + * and considering which format it has as input from the sensor. + */ +static int isc_try_configure_pipeline(struct isc_device *isc) +{ + switch (isc->try_config.fourcc) { + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_ARGB555: + case V4L2_PIX_FMT_ARGB444: + case V4L2_PIX_FMT_ABGR32: + case V4L2_PIX_FMT_XBGR32: + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | + CC_ENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + case V4L2_PIX_FMT_YUV420: + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | GAM_ENABLES | WB_ENABLE | + SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | + DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + case V4L2_PIX_FMT_YUV422P: + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | + SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | + SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + case V4L2_PIX_FMT_GREY: + case V4L2_PIX_FMT_Y16: + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | + CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + default: + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) + isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; + else + isc->try_config.bits_pipeline = 0x0; + } + + /* Tune the pipeline to product specific */ + isc->adapt_pipeline(isc); + + return 0; +} + +static void isc_try_fse(struct isc_device *isc, + struct v4l2_subdev_state *sd_state) +{ + int ret; + struct v4l2_subdev_frame_size_enum fse = {}; + + /* + * If we do not know yet which format the subdev is using, we cannot + * do anything. + */ + if (!isc->try_config.sd_format) + return; + + fse.code = isc->try_config.sd_format->mbus_code; + fse.which = V4L2_SUBDEV_FORMAT_TRY; + + ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size, + sd_state, &fse); + /* + * Attempt to obtain format size from subdev. If not available, + * just use the maximum ISC can receive. + */ + if (ret) { + sd_state->pads->try_crop.width = isc->max_width; + sd_state->pads->try_crop.height = isc->max_height; + } else { + sd_state->pads->try_crop.width = fse.max_width; + sd_state->pads->try_crop.height = fse.max_height; + } +} + +static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f, + u32 *code) +{ + int i; + struct isc_format *sd_fmt = NULL, *direct_fmt = NULL; + struct v4l2_pix_format *pixfmt = &f->fmt.pix; + struct v4l2_subdev_pad_config pad_cfg = {}; + struct v4l2_subdev_state pad_state = { + .pads = &pad_cfg + }; + struct v4l2_subdev_format format = { + .which = V4L2_SUBDEV_FORMAT_TRY, + }; + u32 mbus_code; + int ret; + bool rlp_dma_direct_dump = false; + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + /* Step 1: find a RAW format that is supported */ + for (i = 0; i < isc->num_user_formats; i++) { + if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) { + sd_fmt = isc->user_formats[i]; + break; + } + } + /* Step 2: We can continue with this RAW format, or we can look + * for better: maybe sensor supports directly what we need. + */ + direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat); + + /* Step 3: We have both. We decide given the module parameter which + * one to use. + */ + if (direct_fmt && sd_fmt && sensor_preferred) + sd_fmt = direct_fmt; + + /* Step 4: we do not have RAW but we have a direct format. Use it. */ + if (direct_fmt && !sd_fmt) + sd_fmt = direct_fmt; + + /* Step 5: if we are using a direct format, we need to package + * everything as 8 bit data and just dump it + */ + if (sd_fmt == direct_fmt) + rlp_dma_direct_dump = true; + + /* Step 6: We have no format. This can happen if the userspace + * requests some weird/invalid format. + * In this case, default to whatever we have + */ + if (!sd_fmt && !direct_fmt) { + sd_fmt = isc->user_formats[isc->num_user_formats - 1]; + v4l2_dbg(1, debug, &isc->v4l2_dev, + "Sensor not supporting %.4s, using %.4s\n", + (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc); + } + + if (!sd_fmt) { + ret = -EINVAL; + goto isc_try_fmt_err; + } + + /* Step 7: Print out what we decided for debugging */ + v4l2_dbg(1, debug, &isc->v4l2_dev, + "Preferring to have sensor using format %.4s\n", + (char *)&sd_fmt->fourcc); + + /* Step 8: at this moment we decided which format the subdev will use */ + isc->try_config.sd_format = sd_fmt; + + /* Limit to Atmel ISC hardware capabilities */ + if (pixfmt->width > isc->max_width) + pixfmt->width = isc->max_width; + if (pixfmt->height > isc->max_height) + pixfmt->height = isc->max_height; + + /* + * The mbus format is the one the subdev outputs. + * The pixels will be transferred in this format Sensor -> ISC + */ + mbus_code = sd_fmt->mbus_code; + + /* + * Validate formats. If the required format is not OK, default to raw. + */ + + isc->try_config.fourcc = pixfmt->pixelformat; + + if (isc_try_validate_formats(isc)) { + pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc; + /* Re-try to validate the new format */ + ret = isc_try_validate_formats(isc); + if (ret) + goto isc_try_fmt_err; + } + + ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump); + if (ret) + goto isc_try_fmt_err; + + ret = isc_try_configure_pipeline(isc); + if (ret) + goto isc_try_fmt_err; + + /* Obtain frame sizes if possible to have crop requirements ready */ + isc_try_fse(isc, &pad_state); + + v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code); + ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt, + &pad_state, &format); + if (ret < 0) + goto isc_try_fmt_subdev_err; + + v4l2_fill_pix_format(pixfmt, &format.format); + + /* Limit to Atmel ISC hardware capabilities */ + if (pixfmt->width > isc->max_width) + pixfmt->width = isc->max_width; + if (pixfmt->height > isc->max_height) + pixfmt->height = isc->max_height; + + pixfmt->field = V4L2_FIELD_NONE; + pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3; + pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) * + pixfmt->height; + + if (code) + *code = mbus_code; + + return 0; + +isc_try_fmt_err: + v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n"); +isc_try_fmt_subdev_err: + memset(&isc->try_config, 0, sizeof(isc->try_config)); + + return ret; +} + +static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f) +{ + struct v4l2_subdev_format format = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + u32 mbus_code = 0; + int ret; + + ret = isc_try_fmt(isc, f, &mbus_code); + if (ret) + return ret; + + v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code); + ret = v4l2_subdev_call(isc->current_subdev->sd, pad, + set_fmt, NULL, &format); + if (ret < 0) + return ret; + + /* Limit to Atmel ISC hardware capabilities */ + if (f->fmt.pix.width > isc->max_width) + f->fmt.pix.width = isc->max_width; + if (f->fmt.pix.height > isc->max_height) + f->fmt.pix.height = isc->max_height; + + isc->fmt = *f; + + if (isc->try_config.sd_format && isc->config.sd_format && + isc->try_config.sd_format != isc->config.sd_format) { + isc->ctrls.hist_stat = HIST_INIT; + isc_reset_awb_ctrls(isc); + isc_update_v4l2_ctrls(isc); + } + /* make the try configuration active */ + isc->config = isc->try_config; + + v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n"); + + return 0; +} + +static int isc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct isc_device *isc = video_drvdata(file); + + if (vb2_is_busy(&isc->vb2_vidq)) + return -EBUSY; + + return isc_set_fmt(isc, f); +} + +static int isc_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct isc_device *isc = video_drvdata(file); + + return isc_try_fmt(isc, f, NULL); +} + +static int isc_enum_input(struct file *file, void *priv, + struct v4l2_input *inp) +{ + if (inp->index != 0) + return -EINVAL; + + inp->type = V4L2_INPUT_TYPE_CAMERA; + inp->std = 0; + strscpy(inp->name, "Camera", sizeof(inp->name)); + + return 0; +} + +static int isc_g_input(struct file *file, void *priv, unsigned int *i) +{ + *i = 0; + + return 0; +} + +static int isc_s_input(struct file *file, void *priv, unsigned int i) +{ + if (i > 0) + return -EINVAL; + + return 0; +} + +static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) +{ + struct isc_device *isc = video_drvdata(file); + + return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a); +} + +static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) +{ + struct isc_device *isc = video_drvdata(file); + + return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a); +} + +static int isc_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + struct isc_device *isc = video_drvdata(file); + int ret = -EINVAL; + int i; + + if (fsize->index) + return -EINVAL; + + for (i = 0; i < isc->num_user_formats; i++) + if (isc->user_formats[i]->fourcc == fsize->pixel_format) + ret = 0; + + for (i = 0; i < isc->controller_formats_size; i++) + if (isc->controller_formats[i].fourcc == fsize->pixel_format) + ret = 0; + + if (ret) + return ret; + + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; + + fsize->stepwise.min_width = 16; + fsize->stepwise.max_width = isc->max_width; + fsize->stepwise.min_height = 16; + fsize->stepwise.max_height = isc->max_height; + fsize->stepwise.step_width = 1; + fsize->stepwise.step_height = 1; + + return 0; +} + +static const struct v4l2_ioctl_ops isc_ioctl_ops = { + .vidioc_querycap = isc_querycap, + .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap, + + .vidioc_enum_input = isc_enum_input, + .vidioc_g_input = isc_g_input, + .vidioc_s_input = isc_s_input, + + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + + .vidioc_g_parm = isc_g_parm, + .vidioc_s_parm = isc_s_parm, + .vidioc_enum_framesizes = isc_enum_framesizes, + + .vidioc_log_status = v4l2_ctrl_log_status, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static int isc_open(struct file *file) +{ + struct isc_device *isc = video_drvdata(file); + struct v4l2_subdev *sd = isc->current_subdev->sd; + int ret; + + if (mutex_lock_interruptible(&isc->lock)) + return -ERESTARTSYS; + + ret = v4l2_fh_open(file); + if (ret < 0) + goto unlock; + + if (!v4l2_fh_is_singular_file(file)) + goto unlock; + + ret = v4l2_subdev_call(sd, core, s_power, 1); + if (ret < 0 && ret != -ENOIOCTLCMD) { + v4l2_fh_release(file); + goto unlock; + } + + ret = isc_set_fmt(isc, &isc->fmt); + if (ret) { + v4l2_subdev_call(sd, core, s_power, 0); + v4l2_fh_release(file); + } + +unlock: + mutex_unlock(&isc->lock); + return ret; +} + +static int isc_release(struct file *file) +{ + struct isc_device *isc = video_drvdata(file); + struct v4l2_subdev *sd = isc->current_subdev->sd; + bool fh_singular; + int ret; + + mutex_lock(&isc->lock); + + fh_singular = v4l2_fh_is_singular_file(file); + + ret = _vb2_fop_release(file, NULL); + + if (fh_singular) + v4l2_subdev_call(sd, core, s_power, 0); + + mutex_unlock(&isc->lock); + + return ret; +} + +static const struct v4l2_file_operations isc_fops = { + .owner = THIS_MODULE, + .open = isc_open, + .release = isc_release, + .unlocked_ioctl = video_ioctl2, + .read = vb2_fop_read, + .mmap = vb2_fop_mmap, + .poll = vb2_fop_poll, +}; + +irqreturn_t atmel_isc_interrupt(int irq, void *dev_id) +{ + struct isc_device *isc = (struct isc_device *)dev_id; + struct regmap *regmap = isc->regmap; + u32 isc_intsr, isc_intmask, pending; + irqreturn_t ret = IRQ_NONE; + + regmap_read(regmap, ISC_INTSR, &isc_intsr); + regmap_read(regmap, ISC_INTMASK, &isc_intmask); + + pending = isc_intsr & isc_intmask; + + if (likely(pending & ISC_INT_DDONE)) { + spin_lock(&isc->dma_queue_lock); + if (isc->cur_frm) { + struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb; + struct vb2_buffer *vb = &vbuf->vb2_buf; + + vb->timestamp = ktime_get_ns(); + vbuf->sequence = isc->sequence++; + vb2_buffer_done(vb, VB2_BUF_STATE_DONE); + isc->cur_frm = NULL; + } + + if (!list_empty(&isc->dma_queue) && !isc->stop) { + isc->cur_frm = list_first_entry(&isc->dma_queue, + struct isc_buffer, list); + list_del(&isc->cur_frm->list); + + isc_start_dma(isc); + } + + if (isc->stop) + complete(&isc->comp); + + ret = IRQ_HANDLED; + spin_unlock(&isc->dma_queue_lock); + } + + if (pending & ISC_INT_HISDONE) { + schedule_work(&isc->awb_work); + ret = IRQ_HANDLED; + } + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_isc_interrupt); + +static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) +{ + struct regmap *regmap = isc->regmap; + struct isc_ctrls *ctrls = &isc->ctrls; + u32 *hist_count = &ctrls->hist_count[ctrls->hist_id]; + u32 *hist_entry = &ctrls->hist_entry[0]; + u32 i; + + *min = 0; + *max = HIST_ENTRIES; + + regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, + hist_entry, HIST_ENTRIES); + + *hist_count = 0; + /* + * we deliberately ignore the end of the histogram, + * the most white pixels + */ + for (i = 1; i < HIST_ENTRIES; i++) { + if (*hist_entry && !*min) + *min = i; + if (*hist_entry) + *max = i; + *hist_count += i * (*hist_entry++); + } + + if (!*min) + *min = 1; + + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb: hist_id %u, hist_count %u", + ctrls->hist_id, *hist_count); +} + +static void isc_wb_update(struct isc_ctrls *ctrls) +{ + struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls); + u32 *hist_count = &ctrls->hist_count[0]; + u32 c, offset[4]; + u64 avg = 0; + /* We compute two gains, stretch gain and grey world gain */ + u32 s_gain[4], gw_gain[4]; + + /* + * According to Grey World, we need to set gains for R/B to normalize + * them towards the green channel. + * Thus we want to keep Green as fixed and adjust only Red/Blue + * Compute the average of the both green channels first + */ + avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] + + (u64)hist_count[ISC_HIS_CFG_MODE_GB]; + avg >>= 1; + + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb: green components average %llu\n", avg); + + /* Green histogram is null, nothing to do */ + if (!avg) + return; + + for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) { + /* + * the color offset is the minimum value of the histogram. + * we stretch this color to the full range by substracting + * this value from the color component. + */ + offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX]; + /* + * The offset is always at least 1. If the offset is 1, we do + * not need to adjust it, so our result must be zero. + * the offset is computed in a histogram on 9 bits (0..512) + * but the offset in register is based on + * 12 bits pipeline (0..4096). + * we need to shift with the 3 bits that the histogram is + * ignoring + */ + ctrls->offset[c] = (offset[c] - 1) << 3; + + /* + * the offset is then taken and converted to 2's complements, + * and must be negative, as we subtract this value from the + * color components + */ + ctrls->offset[c] = -ctrls->offset[c]; + + /* + * the stretch gain is the total number of histogram bins + * divided by the actual range of color component (Max - Min) + * If we compute gain like this, the actual color component + * will be stretched to the full histogram. + * We need to shift 9 bits for precision, we have 9 bits for + * decimals + */ + s_gain[c] = (HIST_ENTRIES << 9) / + (ctrls->hist_minmax[c][HIST_MAX_INDEX] - + ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1); + + /* + * Now we have to compute the gain w.r.t. the average. + * Add/lose gain to the component towards the average. + * If it happens that the component is zero, use the + * fixed point value : 1.0 gain. + */ + if (hist_count[c]) + gw_gain[c] = div_u64(avg << 9, hist_count[c]); + else + gw_gain[c] = 1 << 9; + + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb: component %d, s_gain %u, gw_gain %u\n", + c, s_gain[c], gw_gain[c]); + /* multiply both gains and adjust for decimals */ + ctrls->gain[c] = s_gain[c] * gw_gain[c]; + ctrls->gain[c] >>= 9; + + /* make sure we are not out of range */ + ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0)); + + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb: component %d, final gain %u\n", + c, ctrls->gain[c]); + } +} + +static void isc_awb_work(struct work_struct *w) +{ + struct isc_device *isc = + container_of(w, struct isc_device, awb_work); + struct regmap *regmap = isc->regmap; + struct isc_ctrls *ctrls = &isc->ctrls; + u32 hist_id = ctrls->hist_id; + u32 baysel; + unsigned long flags; + u32 min, max; + int ret; + + if (ctrls->hist_stat != HIST_ENABLED) + return; + + isc_hist_count(isc, &min, &max); + + v4l2_dbg(1, debug, &isc->v4l2_dev, + "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max); + + ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min; + ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max; + + if (hist_id != ISC_HIS_CFG_MODE_B) { + hist_id++; + } else { + isc_wb_update(ctrls); + hist_id = ISC_HIS_CFG_MODE_GR; + } + + ctrls->hist_id = hist_id; + baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT; + + ret = pm_runtime_resume_and_get(isc->dev); + if (ret < 0) + return; + + /* + * only update if we have all the required histograms and controls + * if awb has been disabled, we need to reset registers as well. + */ + if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) { + /* + * It may happen that DMA Done IRQ will trigger while we are + * updating white balance registers here. + * In that case, only parts of the controls have been updated. + * We can avoid that by locking the section. + */ + spin_lock_irqsave(&isc->awb_lock, flags); + isc_update_awb_ctrls(isc); + spin_unlock_irqrestore(&isc->awb_lock, flags); + + /* + * if we are doing just the one time white balance adjustment, + * we are basically done. + */ + if (ctrls->awb == ISC_WB_ONETIME) { + v4l2_info(&isc->v4l2_dev, + "Completed one time white-balance adjustment.\n"); + /* update the v4l2 controls values */ + isc_update_v4l2_ctrls(isc); + ctrls->awb = ISC_WB_NONE; + } + } + regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, + hist_id | baysel | ISC_HIS_CFG_RAR); + + /* + * We have to make sure the streaming has not stopped meanwhile. + * ISC requires a frame to clock the internal profile update. + * To avoid issues, lock the sequence with a mutex + */ + mutex_lock(&isc->awb_mutex); + + /* streaming is not active anymore */ + if (isc->stop) { + mutex_unlock(&isc->awb_mutex); + return; + } + + isc_update_profile(isc); + + mutex_unlock(&isc->awb_mutex); + + /* if awb has been disabled, we don't need to start another histogram */ + if (ctrls->awb) + regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); + + pm_runtime_put_sync(isc->dev); +} + +static int isc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct isc_device *isc = container_of(ctrl->handler, + struct isc_device, ctrls.handler); + struct isc_ctrls *ctrls = &isc->ctrls; + + if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) + return 0; + + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK; + break; + case V4L2_CID_CONTRAST: + ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK; + break; + case V4L2_CID_GAMMA: + ctrls->gamma_index = ctrl->val; + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ctrl_ops isc_ctrl_ops = { + .s_ctrl = isc_s_ctrl, +}; + +static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) +{ + struct isc_device *isc = container_of(ctrl->handler, + struct isc_device, ctrls.handler); + struct isc_ctrls *ctrls = &isc->ctrls; + + if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) + return 0; + + switch (ctrl->id) { + case V4L2_CID_AUTO_WHITE_BALANCE: + if (ctrl->val == 1) + ctrls->awb = ISC_WB_AUTO; + else + ctrls->awb = ISC_WB_NONE; + + /* configure the controls with new values from v4l2 */ + if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new) + ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val; + if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new) + ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val; + if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new) + ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val; + if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new) + ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val; + + if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new) + ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val; + if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new) + ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val; + if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new) + ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val; + if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new) + ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val; + + isc_update_awb_ctrls(isc); + + mutex_lock(&isc->awb_mutex); + if (vb2_is_streaming(&isc->vb2_vidq)) { + /* + * If we are streaming, we can update profile to + * have the new settings in place. + */ + isc_update_profile(isc); + } else { + /* + * The auto cluster will activate automatically this + * control. This has to be deactivated when not + * streaming. + */ + v4l2_ctrl_activate(isc->do_wb_ctrl, false); + } + mutex_unlock(&isc->awb_mutex); + + /* if we have autowhitebalance on, start histogram procedure */ + if (ctrls->awb == ISC_WB_AUTO && + vb2_is_streaming(&isc->vb2_vidq) && + ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) + isc_set_histogram(isc, true); + + /* + * for one time whitebalance adjustment, check the button, + * if it's pressed, perform the one time operation. + */ + if (ctrls->awb == ISC_WB_NONE && + ctrl->cluster[ISC_CTRL_DO_WB]->is_new && + !(ctrl->cluster[ISC_CTRL_DO_WB]->flags & + V4L2_CTRL_FLAG_INACTIVE)) { + ctrls->awb = ISC_WB_ONETIME; + isc_set_histogram(isc, true); + v4l2_dbg(1, debug, &isc->v4l2_dev, + "One time white-balance started.\n"); + } + return 0; + } + return 0; +} + +static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl) +{ + struct isc_device *isc = container_of(ctrl->handler, + struct isc_device, ctrls.handler); + struct isc_ctrls *ctrls = &isc->ctrls; + + switch (ctrl->id) { + /* being a cluster, this id will be called for every control */ + case V4L2_CID_AUTO_WHITE_BALANCE: + ctrl->cluster[ISC_CTRL_R_GAIN]->val = + ctrls->gain[ISC_HIS_CFG_MODE_R]; + ctrl->cluster[ISC_CTRL_B_GAIN]->val = + ctrls->gain[ISC_HIS_CFG_MODE_B]; + ctrl->cluster[ISC_CTRL_GR_GAIN]->val = + ctrls->gain[ISC_HIS_CFG_MODE_GR]; + ctrl->cluster[ISC_CTRL_GB_GAIN]->val = + ctrls->gain[ISC_HIS_CFG_MODE_GB]; + + ctrl->cluster[ISC_CTRL_R_OFF]->val = + ctrls->offset[ISC_HIS_CFG_MODE_R]; + ctrl->cluster[ISC_CTRL_B_OFF]->val = + ctrls->offset[ISC_HIS_CFG_MODE_B]; + ctrl->cluster[ISC_CTRL_GR_OFF]->val = + ctrls->offset[ISC_HIS_CFG_MODE_GR]; + ctrl->cluster[ISC_CTRL_GB_OFF]->val = + ctrls->offset[ISC_HIS_CFG_MODE_GB]; + break; + } + return 0; +} + +static const struct v4l2_ctrl_ops isc_awb_ops = { + .s_ctrl = isc_s_awb_ctrl, + .g_volatile_ctrl = isc_g_volatile_awb_ctrl, +}; + +#define ISC_CTRL_OFF(_name, _id, _name_str) \ + static const struct v4l2_ctrl_config _name = { \ + .ops = &isc_awb_ops, \ + .id = _id, \ + .name = _name_str, \ + .type = V4L2_CTRL_TYPE_INTEGER, \ + .flags = V4L2_CTRL_FLAG_SLIDER, \ + .min = -4095, \ + .max = 4095, \ + .step = 1, \ + .def = 0, \ + } + +ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset"); +ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset"); +ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset"); +ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset"); + +#define ISC_CTRL_GAIN(_name, _id, _name_str) \ + static const struct v4l2_ctrl_config _name = { \ + .ops = &isc_awb_ops, \ + .id = _id, \ + .name = _name_str, \ + .type = V4L2_CTRL_TYPE_INTEGER, \ + .flags = V4L2_CTRL_FLAG_SLIDER, \ + .min = 0, \ + .max = 8191, \ + .step = 1, \ + .def = 512, \ + } + +ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain"); +ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain"); +ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain"); +ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain"); + +static int isc_ctrl_init(struct isc_device *isc) +{ + const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops; + struct isc_ctrls *ctrls = &isc->ctrls; + struct v4l2_ctrl_handler *hdl = &ctrls->handler; + int ret; + + ctrls->hist_stat = HIST_INIT; + isc_reset_awb_ctrls(isc); + + ret = v4l2_ctrl_handler_init(hdl, 13); + if (ret < 0) + return ret; + + /* Initialize product specific controls. For example, contrast */ + isc->config_ctrls(isc, ops); + + ctrls->brightness = 0; + + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, + isc->gamma_max); + isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, + V4L2_CID_AUTO_WHITE_BALANCE, + 0, 1, 1, 1); + + /* do_white_balance is a button, so min,max,step,default are ignored */ + isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, + V4L2_CID_DO_WHITE_BALANCE, + 0, 0, 0, 0); + + if (!isc->do_wb_ctrl) { + ret = hdl->error; + v4l2_ctrl_handler_free(hdl); + return ret; + } + + v4l2_ctrl_activate(isc->do_wb_ctrl, false); + + isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL); + isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL); + isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL); + isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL); + isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL); + isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL); + isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL); + isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL); + + /* + * The cluster is in auto mode with autowhitebalance enabled + * and manual mode otherwise. + */ + v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true); + + v4l2_ctrl_handler_setup(hdl); + + return 0; +} + +static int isc_async_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct isc_device *isc = container_of(notifier->v4l2_dev, + struct isc_device, v4l2_dev); + struct isc_subdev_entity *subdev_entity = + container_of(notifier, struct isc_subdev_entity, notifier); + + if (video_is_registered(&isc->video_dev)) { + v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n"); + return -EBUSY; + } + + subdev_entity->sd = subdev; + + return 0; +} + +static void isc_async_unbind(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct isc_device *isc = container_of(notifier->v4l2_dev, + struct isc_device, v4l2_dev); + mutex_destroy(&isc->awb_mutex); + cancel_work_sync(&isc->awb_work); + video_unregister_device(&isc->video_dev); + v4l2_ctrl_handler_free(&isc->ctrls.handler); +} + +static struct isc_format *find_format_by_code(struct isc_device *isc, + unsigned int code, int *index) +{ + struct isc_format *fmt = &isc->formats_list[0]; + unsigned int i; + + for (i = 0; i < isc->formats_list_size; i++) { + if (fmt->mbus_code == code) { + *index = i; + return fmt; + } + + fmt++; + } + + return NULL; +} + +static int isc_formats_init(struct isc_device *isc) +{ + struct isc_format *fmt; + struct v4l2_subdev *subdev = isc->current_subdev->sd; + unsigned int num_fmts, i, j; + u32 list_size = isc->formats_list_size; + struct v4l2_subdev_mbus_code_enum mbus_code = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + num_fmts = 0; + while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, + NULL, &mbus_code)) { + mbus_code.index++; + + fmt = find_format_by_code(isc, mbus_code.code, &i); + if (!fmt) { + v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n", + mbus_code.code); + continue; + } + + fmt->sd_support = true; + num_fmts++; + } + + if (!num_fmts) + return -ENXIO; + + isc->num_user_formats = num_fmts; + isc->user_formats = devm_kcalloc(isc->dev, + num_fmts, sizeof(*isc->user_formats), + GFP_KERNEL); + if (!isc->user_formats) + return -ENOMEM; + + fmt = &isc->formats_list[0]; + for (i = 0, j = 0; i < list_size; i++) { + if (fmt->sd_support) + isc->user_formats[j++] = fmt; + fmt++; + } + + return 0; +} + +static int isc_set_default_fmt(struct isc_device *isc) +{ + struct v4l2_format f = { + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, + .fmt.pix = { + .width = VGA_WIDTH, + .height = VGA_HEIGHT, + .field = V4L2_FIELD_NONE, + .pixelformat = isc->user_formats[0]->fourcc, + }, + }; + int ret; + + ret = isc_try_fmt(isc, &f, NULL); + if (ret) + return ret; + + isc->fmt = f; + return 0; +} + +static int isc_async_complete(struct v4l2_async_notifier *notifier) +{ + struct isc_device *isc = container_of(notifier->v4l2_dev, + struct isc_device, v4l2_dev); + struct video_device *vdev = &isc->video_dev; + struct vb2_queue *q = &isc->vb2_vidq; + int ret = 0; + + INIT_WORK(&isc->awb_work, isc_awb_work); + + ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev); + if (ret < 0) { + v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n"); + return ret; + } + + isc->current_subdev = container_of(notifier, + struct isc_subdev_entity, notifier); + mutex_init(&isc->lock); + mutex_init(&isc->awb_mutex); + + init_completion(&isc->comp); + + /* Initialize videobuf2 queue */ + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; + q->drv_priv = isc; + q->buf_struct_size = sizeof(struct isc_buffer); + q->ops = &isc_vb2_ops; + q->mem_ops = &vb2_dma_contig_memops; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->lock = &isc->lock; + q->min_buffers_needed = 1; + q->dev = isc->dev; + + ret = vb2_queue_init(q); + if (ret < 0) { + v4l2_err(&isc->v4l2_dev, + "vb2_queue_init() failed: %d\n", ret); + goto isc_async_complete_err; + } + + /* Init video dma queues */ + INIT_LIST_HEAD(&isc->dma_queue); + spin_lock_init(&isc->dma_queue_lock); + spin_lock_init(&isc->awb_lock); + + ret = isc_formats_init(isc); + if (ret < 0) { + v4l2_err(&isc->v4l2_dev, + "Init format failed: %d\n", ret); + goto isc_async_complete_err; + } + + ret = isc_set_default_fmt(isc); + if (ret) { + v4l2_err(&isc->v4l2_dev, "Could not set default format\n"); + goto isc_async_complete_err; + } + + ret = isc_ctrl_init(isc); + if (ret) { + v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret); + goto isc_async_complete_err; + } + + /* Register video device */ + strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name)); + vdev->release = video_device_release_empty; + vdev->fops = &isc_fops; + vdev->ioctl_ops = &isc_ioctl_ops; + vdev->v4l2_dev = &isc->v4l2_dev; + vdev->vfl_dir = VFL_DIR_RX; + vdev->queue = q; + vdev->lock = &isc->lock; + vdev->ctrl_handler = &isc->ctrls.handler; + vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE; + video_set_drvdata(vdev, isc); + + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret < 0) { + v4l2_err(&isc->v4l2_dev, + "video_register_device failed: %d\n", ret); + goto isc_async_complete_err; + } + + return 0; + +isc_async_complete_err: + mutex_destroy(&isc->awb_mutex); + mutex_destroy(&isc->lock); + return ret; +} + +const struct v4l2_async_notifier_operations atmel_isc_async_ops = { + .bound = isc_async_bound, + .unbind = isc_async_unbind, + .complete = isc_async_complete, +}; +EXPORT_SYMBOL_GPL(atmel_isc_async_ops); + +void atmel_isc_subdev_cleanup(struct isc_device *isc) +{ + struct isc_subdev_entity *subdev_entity; + + list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { + v4l2_async_nf_unregister(&subdev_entity->notifier); + v4l2_async_nf_cleanup(&subdev_entity->notifier); + } + + INIT_LIST_HEAD(&isc->subdev_entities); +} +EXPORT_SYMBOL_GPL(atmel_isc_subdev_cleanup); + +int atmel_isc_pipeline_init(struct isc_device *isc) +{ + struct device *dev = isc->dev; + struct regmap *regmap = isc->regmap; + struct regmap_field *regs; + unsigned int i; + + /* + * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC--> + * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420 + */ + const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = { + REG_FIELD(ISC_DPC_CTRL, 0, 0), + REG_FIELD(ISC_DPC_CTRL, 1, 1), + REG_FIELD(ISC_DPC_CTRL, 2, 2), + REG_FIELD(ISC_WB_CTRL, 0, 0), + REG_FIELD(ISC_CFA_CTRL, 0, 0), + REG_FIELD(ISC_CC_CTRL, 0, 0), + REG_FIELD(ISC_GAM_CTRL, 0, 0), + REG_FIELD(ISC_GAM_CTRL, 1, 1), + REG_FIELD(ISC_GAM_CTRL, 2, 2), + REG_FIELD(ISC_GAM_CTRL, 3, 3), + REG_FIELD(ISC_VHXS_CTRL, 0, 0), + REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), + REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), + REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), + REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0), + }; + + for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { + regs = devm_regmap_field_alloc(dev, regmap, regfields[i]); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + isc->pipeline[i] = regs; + } + + return 0; +} +EXPORT_SYMBOL_GPL(atmel_isc_pipeline_init); + +/* regmap configuration */ +#define ATMEL_ISC_REG_MAX 0xd5c +const struct regmap_config atmel_isc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = ATMEL_ISC_REG_MAX, +}; +EXPORT_SYMBOL_GPL(atmel_isc_regmap_config); + +MODULE_AUTHOR("Songjun Wu"); +MODULE_AUTHOR("Eugen Hristev"); +MODULE_DESCRIPTION("Atmel ISC common code base"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/media/deprecated/atmel/atmel-isc-clk.c b/drivers/staging/media/deprecated/atmel/atmel-isc-clk.c new file mode 100644 index 000000000..d442b5f4c --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/atmel-isc-clk.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Microchip Image Sensor Controller (ISC) common clock driver setup + * + * Copyright (C) 2016 Microchip Technology, Inc. + * + * Author: Songjun Wu + * Author: Eugen Hristev + * + */ +#include +#include +#include +#include +#include + +#include "atmel-isc-regs.h" +#include "atmel-isc.h" + +static int isc_wait_clk_stable(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + struct regmap *regmap = isc_clk->regmap; + unsigned long timeout = jiffies + usecs_to_jiffies(1000); + unsigned int status; + + while (time_before(jiffies, timeout)) { + regmap_read(regmap, ISC_CLKSR, &status); + if (!(status & ISC_CLKSR_SIP)) + return 0; + + usleep_range(10, 250); + } + + return -ETIMEDOUT; +} + +static int isc_clk_prepare(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + int ret; + + ret = pm_runtime_resume_and_get(isc_clk->dev); + if (ret < 0) + return ret; + + return isc_wait_clk_stable(hw); +} + +static void isc_clk_unprepare(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + + isc_wait_clk_stable(hw); + + pm_runtime_put_sync(isc_clk->dev); +} + +static int isc_clk_enable(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 id = isc_clk->id; + struct regmap *regmap = isc_clk->regmap; + unsigned long flags; + unsigned int status; + + dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", + __func__, id, isc_clk->div, isc_clk->parent_id); + + spin_lock_irqsave(&isc_clk->lock, flags); + regmap_update_bits(regmap, ISC_CLKCFG, + ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id), + (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) | + (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id))); + + regmap_write(regmap, ISC_CLKEN, ISC_CLK(id)); + spin_unlock_irqrestore(&isc_clk->lock, flags); + + regmap_read(regmap, ISC_CLKSR, &status); + if (status & ISC_CLK(id)) + return 0; + else + return -EINVAL; +} + +static void isc_clk_disable(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 id = isc_clk->id; + unsigned long flags; + + spin_lock_irqsave(&isc_clk->lock, flags); + regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id)); + spin_unlock_irqrestore(&isc_clk->lock, flags); +} + +static int isc_clk_is_enabled(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 status; + int ret; + + ret = pm_runtime_resume_and_get(isc_clk->dev); + if (ret < 0) + return 0; + + regmap_read(isc_clk->regmap, ISC_CLKSR, &status); + + pm_runtime_put_sync(isc_clk->dev); + + return status & ISC_CLK(isc_clk->id) ? 1 : 0; +} + +static unsigned long +isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + + return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1); +} + +static int isc_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + long best_rate = -EINVAL; + int best_diff = -1; + unsigned int i, div; + + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent; + unsigned long parent_rate; + + parent = clk_hw_get_parent_by_index(hw, i); + if (!parent) + continue; + + parent_rate = clk_hw_get_rate(parent); + if (!parent_rate) + continue; + + for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) { + unsigned long rate; + int diff; + + rate = DIV_ROUND_CLOSEST(parent_rate, div); + diff = abs(req->rate - rate); + + if (best_diff < 0 || best_diff > diff) { + best_rate = rate; + best_diff = diff; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; + } + + if (!best_diff || rate < req->rate) + break; + } + + if (!best_diff) + break; + } + + dev_dbg(isc_clk->dev, + "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", + __func__, best_rate, + __clk_get_name((req->best_parent_hw)->clk), + req->best_parent_rate); + + if (best_rate < 0) + return best_rate; + + req->rate = best_rate; + + return 0; +} + +static int isc_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + + if (index >= clk_hw_get_num_parents(hw)) + return -EINVAL; + + isc_clk->parent_id = index; + + return 0; +} + +static u8 isc_clk_get_parent(struct clk_hw *hw) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + + return isc_clk->parent_id; +} + +static int isc_clk_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct isc_clk *isc_clk = to_isc_clk(hw); + u32 div; + + if (!rate) + return -EINVAL; + + div = DIV_ROUND_CLOSEST(parent_rate, rate); + if (div > (ISC_CLK_MAX_DIV + 1) || !div) + return -EINVAL; + + isc_clk->div = div - 1; + + return 0; +} + +static const struct clk_ops isc_clk_ops = { + .prepare = isc_clk_prepare, + .unprepare = isc_clk_unprepare, + .enable = isc_clk_enable, + .disable = isc_clk_disable, + .is_enabled = isc_clk_is_enabled, + .recalc_rate = isc_clk_recalc_rate, + .determine_rate = isc_clk_determine_rate, + .set_parent = isc_clk_set_parent, + .get_parent = isc_clk_get_parent, + .set_rate = isc_clk_set_rate, +}; + +static int isc_clk_register(struct isc_device *isc, unsigned int id) +{ + struct regmap *regmap = isc->regmap; + struct device_node *np = isc->dev->of_node; + struct isc_clk *isc_clk; + struct clk_init_data init; + const char *clk_name = np->name; + const char *parent_names[3]; + int num_parents; + + if (id == ISC_ISPCK && !isc->ispck_required) + return 0; + + num_parents = of_clk_get_parent_count(np); + if (num_parents < 1 || num_parents > 3) + return -EINVAL; + + if (num_parents > 2 && id == ISC_ISPCK) + num_parents = 2; + + of_clk_parent_fill(np, parent_names, num_parents); + + if (id == ISC_MCK) + of_property_read_string(np, "clock-output-names", &clk_name); + else + clk_name = "isc-ispck"; + + init.parent_names = parent_names; + init.num_parents = num_parents; + init.name = clk_name; + init.ops = &isc_clk_ops; + init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; + + isc_clk = &isc->isc_clks[id]; + isc_clk->hw.init = &init; + isc_clk->regmap = regmap; + isc_clk->id = id; + isc_clk->dev = isc->dev; + spin_lock_init(&isc_clk->lock); + + isc_clk->clk = clk_register(isc->dev, &isc_clk->hw); + if (IS_ERR(isc_clk->clk)) { + dev_err(isc->dev, "%s: clock register fail\n", clk_name); + return PTR_ERR(isc_clk->clk); + } else if (id == ISC_MCK) { + of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk); + } + + return 0; +} + +int atmel_isc_clk_init(struct isc_device *isc) +{ + unsigned int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) + isc->isc_clks[i].clk = ERR_PTR(-EINVAL); + + for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) { + ret = isc_clk_register(isc, i); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(atmel_isc_clk_init); + +void atmel_isc_clk_cleanup(struct isc_device *isc) +{ + unsigned int i; + + of_clk_del_provider(isc->dev->of_node); + + for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) { + struct isc_clk *isc_clk = &isc->isc_clks[i]; + + if (!IS_ERR(isc_clk->clk)) + clk_unregister(isc_clk->clk); + } +} +EXPORT_SYMBOL_GPL(atmel_isc_clk_cleanup); diff --git a/drivers/staging/media/deprecated/atmel/atmel-isc-regs.h b/drivers/staging/media/deprecated/atmel/atmel-isc-regs.h new file mode 100644 index 000000000..d06b72228 --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/atmel-isc-regs.h @@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ATMEL_ISC_REGS_H +#define __ATMEL_ISC_REGS_H + +#include + +/* ISC Control Enable Register 0 */ +#define ISC_CTRLEN 0x00000000 + +/* ISC Control Disable Register 0 */ +#define ISC_CTRLDIS 0x00000004 + +/* ISC Control Status Register 0 */ +#define ISC_CTRLSR 0x00000008 + +#define ISC_CTRL_CAPTURE BIT(0) +#define ISC_CTRL_UPPRO BIT(1) +#define ISC_CTRL_HISREQ BIT(2) +#define ISC_CTRL_HISCLR BIT(3) + +/* ISC Parallel Front End Configuration 0 Register */ +#define ISC_PFE_CFG0 0x0000000c + +#define ISC_PFE_CFG0_HPOL_LOW BIT(0) +#define ISC_PFE_CFG0_VPOL_LOW BIT(1) +#define ISC_PFE_CFG0_PPOL_LOW BIT(2) +#define ISC_PFE_CFG0_CCIR656 BIT(9) +#define ISC_PFE_CFG0_CCIR_CRC BIT(10) +#define ISC_PFE_CFG0_MIPI BIT(14) + +#define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4) +#define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) + +#define ISC_PFE_CFG0_BPS_EIGHT (0x4 << 28) +#define ISC_PFG_CFG0_BPS_NINE (0x3 << 28) +#define ISC_PFG_CFG0_BPS_TEN (0x2 << 28) +#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28) +#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28) +#define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28) + +#define ISC_PFE_CFG0_COLEN BIT(12) +#define ISC_PFE_CFG0_ROWEN BIT(13) + +/* ISC Parallel Front End Configuration 1 Register */ +#define ISC_PFE_CFG1 0x00000010 + +#define ISC_PFE_CFG1_COLMIN(v) ((v)) +#define ISC_PFE_CFG1_COLMIN_MASK GENMASK(15, 0) +#define ISC_PFE_CFG1_COLMAX(v) ((v) << 16) +#define ISC_PFE_CFG1_COLMAX_MASK GENMASK(31, 16) + +/* ISC Parallel Front End Configuration 2 Register */ +#define ISC_PFE_CFG2 0x00000014 + +#define ISC_PFE_CFG2_ROWMIN(v) ((v)) +#define ISC_PFE_CFG2_ROWMIN_MASK GENMASK(15, 0) +#define ISC_PFE_CFG2_ROWMAX(v) ((v) << 16) +#define ISC_PFE_CFG2_ROWMAX_MASK GENMASK(31, 16) + +/* ISC Clock Enable Register */ +#define ISC_CLKEN 0x00000018 + +/* ISC Clock Disable Register */ +#define ISC_CLKDIS 0x0000001c + +/* ISC Clock Status Register */ +#define ISC_CLKSR 0x00000020 +#define ISC_CLKSR_SIP BIT(31) + +#define ISC_CLK(n) BIT(n) + +/* ISC Clock Configuration Register */ +#define ISC_CLKCFG 0x00000024 +#define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16) +#define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n)*16 + 7), (n)*16) +#define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8) +#define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n)*17 + 8), ((n)*16 + 8)) + +/* ISC Interrupt Enable Register */ +#define ISC_INTEN 0x00000028 + +/* ISC Interrupt Disable Register */ +#define ISC_INTDIS 0x0000002c + +/* ISC Interrupt Mask Register */ +#define ISC_INTMASK 0x00000030 + +/* ISC Interrupt Status Register */ +#define ISC_INTSR 0x00000034 + +#define ISC_INT_DDONE BIT(8) +#define ISC_INT_HISDONE BIT(12) + +/* ISC DPC Control Register */ +#define ISC_DPC_CTRL 0x40 + +#define ISC_DPC_CTRL_DPCEN BIT(0) +#define ISC_DPC_CTRL_GDCEN BIT(1) +#define ISC_DPC_CTRL_BLCEN BIT(2) + +/* ISC DPC Config Register */ +#define ISC_DPC_CFG 0x44 + +#define ISC_DPC_CFG_BAYSEL_SHIFT 0 + +#define ISC_DPC_CFG_EITPOL BIT(4) + +#define ISC_DPC_CFG_TA_ENABLE BIT(14) +#define ISC_DPC_CFG_TC_ENABLE BIT(13) +#define ISC_DPC_CFG_TM_ENABLE BIT(12) + +#define ISC_DPC_CFG_RE_MODE BIT(17) + +#define ISC_DPC_CFG_GDCCLP_SHIFT 20 +#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20) + +#define ISC_DPC_CFG_BLOFF_SHIFT 24 +#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24) + +#define ISC_DPC_CFG_BAYCFG_SHIFT 0 +#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0) +/* ISC DPC Threshold Median Register */ +#define ISC_DPC_THRESHM 0x48 + +/* ISC DPC Threshold Closest Register */ +#define ISC_DPC_THRESHC 0x4C + +/* ISC DPC Threshold Average Register */ +#define ISC_DPC_THRESHA 0x50 + +/* ISC DPC STatus Register */ +#define ISC_DPC_SR 0x54 + +/* ISC White Balance Control Register */ +#define ISC_WB_CTRL 0x00000058 + +/* ISC White Balance Configuration Register */ +#define ISC_WB_CFG 0x0000005c + +/* ISC White Balance Offset for R, GR Register */ +#define ISC_WB_O_RGR 0x00000060 + +/* ISC White Balance Offset for B, GB Register */ +#define ISC_WB_O_BGB 0x00000064 + +/* ISC White Balance Gain for R, GR Register */ +#define ISC_WB_G_RGR 0x00000068 + +/* ISC White Balance Gain for B, GB Register */ +#define ISC_WB_G_BGB 0x0000006c + +/* ISC Color Filter Array Control Register */ +#define ISC_CFA_CTRL 0x00000070 + +/* ISC Color Filter Array Configuration Register */ +#define ISC_CFA_CFG 0x00000074 +#define ISC_CFA_CFG_EITPOL BIT(4) + +#define ISC_BAY_CFG_GRGR 0x0 +#define ISC_BAY_CFG_RGRG 0x1 +#define ISC_BAY_CFG_GBGB 0x2 +#define ISC_BAY_CFG_BGBG 0x3 + +/* ISC Color Correction Control Register */ +#define ISC_CC_CTRL 0x00000078 + +/* ISC Color Correction RR RG Register */ +#define ISC_CC_RR_RG 0x0000007c + +/* ISC Color Correction RB OR Register */ +#define ISC_CC_RB_OR 0x00000080 + +/* ISC Color Correction GR GG Register */ +#define ISC_CC_GR_GG 0x00000084 + +/* ISC Color Correction GB OG Register */ +#define ISC_CC_GB_OG 0x00000088 + +/* ISC Color Correction BR BG Register */ +#define ISC_CC_BR_BG 0x0000008c + +/* ISC Color Correction BB OB Register */ +#define ISC_CC_BB_OB 0x00000090 + +/* ISC Gamma Correction Control Register */ +#define ISC_GAM_CTRL 0x00000094 + +#define ISC_GAM_CTRL_BIPART BIT(4) + +/* ISC_Gamma Correction Blue Entry Register */ +#define ISC_GAM_BENTRY 0x00000098 + +/* ISC_Gamma Correction Green Entry Register */ +#define ISC_GAM_GENTRY 0x00000198 + +/* ISC_Gamma Correction Green Entry Register */ +#define ISC_GAM_RENTRY 0x00000298 + +/* ISC VHXS Control Register */ +#define ISC_VHXS_CTRL 0x398 + +/* ISC VHXS Source Size Register */ +#define ISC_VHXS_SS 0x39C + +/* ISC VHXS Destination Size Register */ +#define ISC_VHXS_DS 0x3A0 + +/* ISC Vertical Factor Register */ +#define ISC_VXS_FACT 0x3a4 + +/* ISC Horizontal Factor Register */ +#define ISC_HXS_FACT 0x3a8 + +/* ISC Vertical Config Register */ +#define ISC_VXS_CFG 0x3ac + +/* ISC Horizontal Config Register */ +#define ISC_HXS_CFG 0x3b0 + +/* ISC Vertical Tap Register */ +#define ISC_VXS_TAP 0x3b4 + +/* ISC Horizontal Tap Register */ +#define ISC_HXS_TAP 0x434 + +/* Offset for CSC register specific to sama5d2 product */ +#define ISC_SAMA5D2_CSC_OFFSET 0 +/* Offset for CSC register specific to sama7g5 product */ +#define ISC_SAMA7G5_CSC_OFFSET 0x11c + +/* Color Space Conversion Control Register */ +#define ISC_CSC_CTRL 0x00000398 + +/* Color Space Conversion YR YG Register */ +#define ISC_CSC_YR_YG 0x0000039c + +/* Color Space Conversion YB OY Register */ +#define ISC_CSC_YB_OY 0x000003a0 + +/* Color Space Conversion CBR CBG Register */ +#define ISC_CSC_CBR_CBG 0x000003a4 + +/* Color Space Conversion CBB OCB Register */ +#define ISC_CSC_CBB_OCB 0x000003a8 + +/* Color Space Conversion CRR CRG Register */ +#define ISC_CSC_CRR_CRG 0x000003ac + +/* Color Space Conversion CRB OCR Register */ +#define ISC_CSC_CRB_OCR 0x000003b0 + +/* Offset for CBC register specific to sama5d2 product */ +#define ISC_SAMA5D2_CBC_OFFSET 0 +/* Offset for CBC register specific to sama7g5 product */ +#define ISC_SAMA7G5_CBC_OFFSET 0x11c + +/* Contrast And Brightness Control Register */ +#define ISC_CBC_CTRL 0x000003b4 + +/* Contrast And Brightness Configuration Register */ +#define ISC_CBC_CFG 0x000003b8 + +/* Brightness Register */ +#define ISC_CBC_BRIGHT 0x000003bc +#define ISC_CBC_BRIGHT_MASK GENMASK(10, 0) + +/* Contrast Register */ +#define ISC_CBC_CONTRAST 0x000003c0 +#define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) + +/* Hue Register */ +#define ISC_CBCHS_HUE 0x4e0 +/* Saturation Register */ +#define ISC_CBCHS_SAT 0x4e4 + +/* Offset for SUB422 register specific to sama5d2 product */ +#define ISC_SAMA5D2_SUB422_OFFSET 0 +/* Offset for SUB422 register specific to sama7g5 product */ +#define ISC_SAMA7G5_SUB422_OFFSET 0x124 + +/* Subsampling 4:4:4 to 4:2:2 Control Register */ +#define ISC_SUB422_CTRL 0x000003c4 + +/* Offset for SUB420 register specific to sama5d2 product */ +#define ISC_SAMA5D2_SUB420_OFFSET 0 +/* Offset for SUB420 register specific to sama7g5 product */ +#define ISC_SAMA7G5_SUB420_OFFSET 0x124 +/* Subsampling 4:2:2 to 4:2:0 Control Register */ +#define ISC_SUB420_CTRL 0x000003cc + +/* Offset for RLP register specific to sama5d2 product */ +#define ISC_SAMA5D2_RLP_OFFSET 0 +/* Offset for RLP register specific to sama7g5 product */ +#define ISC_SAMA7G5_RLP_OFFSET 0x124 +/* Rounding, Limiting and Packing Configuration Register */ +#define ISC_RLP_CFG 0x000003d0 + +#define ISC_RLP_CFG_MODE_DAT8 0x0 +#define ISC_RLP_CFG_MODE_DAT9 0x1 +#define ISC_RLP_CFG_MODE_DAT10 0x2 +#define ISC_RLP_CFG_MODE_DAT11 0x3 +#define ISC_RLP_CFG_MODE_DAT12 0x4 +#define ISC_RLP_CFG_MODE_DATY8 0x5 +#define ISC_RLP_CFG_MODE_DATY10 0x6 +#define ISC_RLP_CFG_MODE_ARGB444 0x7 +#define ISC_RLP_CFG_MODE_ARGB555 0x8 +#define ISC_RLP_CFG_MODE_RGB565 0x9 +#define ISC_RLP_CFG_MODE_ARGB32 0xa +#define ISC_RLP_CFG_MODE_YYCC 0xb +#define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc +#define ISC_RLP_CFG_MODE_YCYC 0xd +#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) + +#define ISC_RLP_CFG_LSH BIT(5) + +#define ISC_RLP_CFG_YMODE_YUYV (3 << 6) +#define ISC_RLP_CFG_YMODE_YVYU (2 << 6) +#define ISC_RLP_CFG_YMODE_VYUY (0 << 6) +#define ISC_RLP_CFG_YMODE_UYVY (1 << 6) + +#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6) + +/* Offset for HIS register specific to sama5d2 product */ +#define ISC_SAMA5D2_HIS_OFFSET 0 +/* Offset for HIS register specific to sama7g5 product */ +#define ISC_SAMA7G5_HIS_OFFSET 0x124 +/* Histogram Control Register */ +#define ISC_HIS_CTRL 0x000003d4 + +#define ISC_HIS_CTRL_EN BIT(0) +#define ISC_HIS_CTRL_DIS 0x0 + +/* Histogram Configuration Register */ +#define ISC_HIS_CFG 0x000003d8 + +#define ISC_HIS_CFG_MODE_GR 0x0 +#define ISC_HIS_CFG_MODE_R 0x1 +#define ISC_HIS_CFG_MODE_GB 0x2 +#define ISC_HIS_CFG_MODE_B 0x3 +#define ISC_HIS_CFG_MODE_Y 0x4 +#define ISC_HIS_CFG_MODE_RAW 0x5 +#define ISC_HIS_CFG_MODE_YCCIR656 0x6 + +#define ISC_HIS_CFG_BAYSEL_SHIFT 4 + +#define ISC_HIS_CFG_RAR BIT(8) + +/* Offset for DMA register specific to sama5d2 product */ +#define ISC_SAMA5D2_DMA_OFFSET 0 +/* Offset for DMA register specific to sama7g5 product */ +#define ISC_SAMA7G5_DMA_OFFSET 0x13c + +/* DMA Configuration Register */ +#define ISC_DCFG 0x000003e0 +#define ISC_DCFG_IMODE_PACKED8 0x0 +#define ISC_DCFG_IMODE_PACKED16 0x1 +#define ISC_DCFG_IMODE_PACKED32 0x2 +#define ISC_DCFG_IMODE_YC422SP 0x3 +#define ISC_DCFG_IMODE_YC422P 0x4 +#define ISC_DCFG_IMODE_YC420SP 0x5 +#define ISC_DCFG_IMODE_YC420P 0x6 +#define ISC_DCFG_IMODE_MASK GENMASK(2, 0) + +#define ISC_DCFG_YMBSIZE_SINGLE (0x0 << 4) +#define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) +#define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) +#define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) +#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4) +#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4) + +#define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) +#define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) +#define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) +#define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) +#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8) +#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8) + +/* DMA Control Register */ +#define ISC_DCTRL 0x000003e4 + +#define ISC_DCTRL_DVIEW_PACKED (0x0 << 1) +#define ISC_DCTRL_DVIEW_SEMIPLANAR (0x1 << 1) +#define ISC_DCTRL_DVIEW_PLANAR (0x2 << 1) +#define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1) + +#define ISC_DCTRL_IE_IS (0x0 << 4) + +/* DMA Descriptor Address Register */ +#define ISC_DNDA 0x000003e8 + +/* DMA Address 0 Register */ +#define ISC_DAD0 0x000003ec + +/* DMA Address 1 Register */ +#define ISC_DAD1 0x000003f4 + +/* DMA Address 2 Register */ +#define ISC_DAD2 0x000003fc + +/* Offset for version register specific to sama5d2 product */ +#define ISC_SAMA5D2_VERSION_OFFSET 0 +#define ISC_SAMA7G5_VERSION_OFFSET 0x13c +/* Version Register */ +#define ISC_VERSION 0x0000040c + +/* Offset for version register specific to sama5d2 product */ +#define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 +/* Offset for version register specific to sama7g5 product */ +#define ISC_SAMA7G5_HIS_ENTRY_OFFSET 0x14c +/* Histogram Entry */ +#define ISC_HIS_ENTRY 0x00000410 + +#endif diff --git a/drivers/staging/media/deprecated/atmel/atmel-isc.h b/drivers/staging/media/deprecated/atmel/atmel-isc.h new file mode 100644 index 000000000..dfc030b5a --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/atmel-isc.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Microchip Image Sensor Controller (ISC) driver header file + * + * Copyright (C) 2016-2019 Microchip Technology, Inc. + * + * Author: Songjun Wu + * Author: Eugen Hristev + * + */ +#ifndef _ATMEL_ISC_H_ + +#include +#include + +#include +#include +#include + +#define ISC_CLK_MAX_DIV 255 + +enum isc_clk_id { + ISC_ISPCK = 0, + ISC_MCK = 1, +}; + +struct isc_clk { + struct clk_hw hw; + struct clk *clk; + struct regmap *regmap; + spinlock_t lock; /* serialize access to clock registers */ + u8 id; + u8 parent_id; + u32 div; + struct device *dev; +}; + +#define to_isc_clk(v) container_of(v, struct isc_clk, hw) + +struct isc_buffer { + struct vb2_v4l2_buffer vb; + struct list_head list; +}; + +struct isc_subdev_entity { + struct v4l2_subdev *sd; + struct v4l2_async_subdev *asd; + struct device_node *epn; + struct v4l2_async_notifier notifier; + + u32 pfe_cfg0; + + struct list_head list; +}; + +/* + * struct isc_format - ISC media bus format information + This structure represents the interface between the ISC + and the sensor. It's the input format received by + the ISC. + * @fourcc: Fourcc code for this format + * @mbus_code: V4L2 media bus format code. + * @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer. + this is either BGBG, RGRG, etc. + * @pfe_cfg0_bps: Number of hardware data lines connected to the ISC + */ + +struct isc_format { + u32 fourcc; + u32 mbus_code; + u32 cfa_baycfg; + + bool sd_support; + u32 pfe_cfg0_bps; +}; + +/* Pipeline bitmap */ +#define DPC_DPCENABLE BIT(0) +#define DPC_GDCENABLE BIT(1) +#define DPC_BLCENABLE BIT(2) +#define WB_ENABLE BIT(3) +#define CFA_ENABLE BIT(4) +#define CC_ENABLE BIT(5) +#define GAM_ENABLE BIT(6) +#define GAM_BENABLE BIT(7) +#define GAM_GENABLE BIT(8) +#define GAM_RENABLE BIT(9) +#define VHXS_ENABLE BIT(10) +#define CSC_ENABLE BIT(11) +#define CBC_ENABLE BIT(12) +#define SUB422_ENABLE BIT(13) +#define SUB420_ENABLE BIT(14) + +#define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE) + +/* + * struct fmt_config - ISC format configuration and internal pipeline + This structure represents the internal configuration + of the ISC. + It also holds the format that ISC will present to v4l2. + * @sd_format: Pointer to an isc_format struct that holds the sensor + configuration. + * @fourcc: Fourcc code for this format. + * @bpp: Bytes per pixel in the current format. + * @bpp_v4l2: Bytes per pixel in the current format, for v4l2. + This differs from 'bpp' in the sense that in planar + formats, it refers only to the first plane. + * @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging) + * @dcfg_imode: Configuration of the input of the DMA module + * @dctrl_dview: Configuration of the output of the DMA module + * @bits_pipeline: Configuration of the pipeline, which modules are enabled + */ +struct fmt_config { + struct isc_format *sd_format; + + u32 fourcc; + u8 bpp; + u8 bpp_v4l2; + + u32 rlp_cfg_mode; + u32 dcfg_imode; + u32 dctrl_dview; + + u32 bits_pipeline; +}; + +#define HIST_ENTRIES 512 +#define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1) + +enum{ + HIST_INIT = 0, + HIST_ENABLED, + HIST_DISABLED, +}; + +struct isc_ctrls { + struct v4l2_ctrl_handler handler; + + u32 brightness; + u32 contrast; + u8 gamma_index; +#define ISC_WB_NONE 0 +#define ISC_WB_AUTO 1 +#define ISC_WB_ONETIME 2 + u8 awb; + + /* one for each component : GR, R, GB, B */ + u32 gain[HIST_BAYER]; + s32 offset[HIST_BAYER]; + + u32 hist_entry[HIST_ENTRIES]; + u32 hist_count[HIST_BAYER]; + u8 hist_id; + u8 hist_stat; +#define HIST_MIN_INDEX 0 +#define HIST_MAX_INDEX 1 + u32 hist_minmax[HIST_BAYER][2]; +}; + +#define ISC_PIPE_LINE_NODE_NUM 15 + +/* + * struct isc_reg_offsets - ISC device register offsets + * @csc: Offset for the CSC register + * @cbc: Offset for the CBC register + * @sub422: Offset for the SUB422 register + * @sub420: Offset for the SUB420 register + * @rlp: Offset for the RLP register + * @his: Offset for the HIS related registers + * @dma: Offset for the DMA related registers + * @version: Offset for the version register + * @his_entry: Offset for the HIS entries registers + */ +struct isc_reg_offsets { + u32 csc; + u32 cbc; + u32 sub422; + u32 sub420; + u32 rlp; + u32 his; + u32 dma; + u32 version; + u32 his_entry; +}; + +/* + * struct isc_device - ISC device driver data/config struct + * @regmap: Register map + * @hclock: Hclock clock input (refer datasheet) + * @ispck: iscpck clock (refer datasheet) + * @isc_clks: ISC clocks + * @ispck_required: ISC requires ISP Clock initialization + * @dcfg: DMA master configuration, architecture dependent + * + * @dev: Registered device driver + * @v4l2_dev: v4l2 registered device + * @video_dev: registered video device + * + * @vb2_vidq: video buffer 2 video queue + * @dma_queue_lock: lock to serialize the dma buffer queue + * @dma_queue: the queue for dma buffers + * @cur_frm: current isc frame/buffer + * @sequence: current frame number + * @stop: true if isc is not streaming, false if streaming + * @comp: completion reference that signals frame completion + * + * @fmt: current v42l format + * @user_formats: list of formats that are supported and agreed with sd + * @num_user_formats: how many formats are in user_formats + * + * @config: current ISC format configuration + * @try_config: the current ISC try format , not yet activated + * + * @ctrls: holds information about ISC controls + * @do_wb_ctrl: control regarding the DO_WHITE_BALANCE button + * @awb_work: workqueue reference for autowhitebalance histogram + * analysis + * + * @lock: lock for serializing userspace file operations + * with ISC operations + * @awb_mutex: serialize access to streaming status from awb work queue + * @awb_lock: lock for serializing awb work queue operations + * with DMA/buffer operations + * + * @pipeline: configuration of the ISC pipeline + * + * @current_subdev: current subdevice: the sensor + * @subdev_entities: list of subdevice entitites + * + * @gamma_table: pointer to the table with gamma values, has + * gamma_max sets of GAMMA_ENTRIES entries each + * @gamma_max: maximum number of sets of inside the gamma_table + * + * @max_width: maximum frame width, dependent on the internal RAM + * @max_height: maximum frame height, dependent on the internal RAM + * + * @config_dpc: pointer to a function that initializes product + * specific DPC module + * @config_csc: pointer to a function that initializes product + * specific CSC module + * @config_cbc: pointer to a function that initializes product + * specific CBC module + * @config_cc: pointer to a function that initializes product + * specific CC module + * @config_gam: pointer to a function that initializes product + * specific GAMMA module + * @config_rlp: pointer to a function that initializes product + * specific RLP module + * @config_ctrls: pointer to a functoin that initializes product + * specific v4l2 controls. + * + * @adapt_pipeline: pointer to a function that adapts the pipeline bits + * to the product specific pipeline + * + * @offsets: struct holding the product specific register offsets + * @controller_formats: pointer to the array of possible formats that the + * controller can output + * @formats_list: pointer to the array of possible formats that can + * be used as an input to the controller + * @controller_formats_size: size of controller_formats array + * @formats_list_size: size of formats_list array + */ +struct isc_device { + struct regmap *regmap; + struct clk *hclock; + struct clk *ispck; + struct isc_clk isc_clks[2]; + bool ispck_required; + u32 dcfg; + + struct device *dev; + struct v4l2_device v4l2_dev; + struct video_device video_dev; + + struct vb2_queue vb2_vidq; + spinlock_t dma_queue_lock; + struct list_head dma_queue; + struct isc_buffer *cur_frm; + unsigned int sequence; + bool stop; + struct completion comp; + + struct v4l2_format fmt; + struct isc_format **user_formats; + unsigned int num_user_formats; + + struct fmt_config config; + struct fmt_config try_config; + + struct isc_ctrls ctrls; + struct work_struct awb_work; + + struct mutex lock; + struct mutex awb_mutex; + spinlock_t awb_lock; + + struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; + + struct isc_subdev_entity *current_subdev; + struct list_head subdev_entities; + + struct { +#define ISC_CTRL_DO_WB 1 +#define ISC_CTRL_R_GAIN 2 +#define ISC_CTRL_B_GAIN 3 +#define ISC_CTRL_GR_GAIN 4 +#define ISC_CTRL_GB_GAIN 5 +#define ISC_CTRL_R_OFF 6 +#define ISC_CTRL_B_OFF 7 +#define ISC_CTRL_GR_OFF 8 +#define ISC_CTRL_GB_OFF 9 + struct v4l2_ctrl *awb_ctrl; + struct v4l2_ctrl *do_wb_ctrl; + struct v4l2_ctrl *r_gain_ctrl; + struct v4l2_ctrl *b_gain_ctrl; + struct v4l2_ctrl *gr_gain_ctrl; + struct v4l2_ctrl *gb_gain_ctrl; + struct v4l2_ctrl *r_off_ctrl; + struct v4l2_ctrl *b_off_ctrl; + struct v4l2_ctrl *gr_off_ctrl; + struct v4l2_ctrl *gb_off_ctrl; + }; + +#define GAMMA_ENTRIES 64 + /* pointer to the defined gamma table */ + const u32 (*gamma_table)[GAMMA_ENTRIES]; + u32 gamma_max; + + u32 max_width; + u32 max_height; + + struct { + void (*config_dpc)(struct isc_device *isc); + void (*config_csc)(struct isc_device *isc); + void (*config_cbc)(struct isc_device *isc); + void (*config_cc)(struct isc_device *isc); + void (*config_gam)(struct isc_device *isc); + void (*config_rlp)(struct isc_device *isc); + + void (*config_ctrls)(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops); + + void (*adapt_pipeline)(struct isc_device *isc); + }; + + struct isc_reg_offsets offsets; + const struct isc_format *controller_formats; + struct isc_format *formats_list; + u32 controller_formats_size; + u32 formats_list_size; +}; + +extern const struct regmap_config atmel_isc_regmap_config; +extern const struct v4l2_async_notifier_operations atmel_isc_async_ops; + +irqreturn_t atmel_isc_interrupt(int irq, void *dev_id); +int atmel_isc_pipeline_init(struct isc_device *isc); +int atmel_isc_clk_init(struct isc_device *isc); +void atmel_isc_subdev_cleanup(struct isc_device *isc); +void atmel_isc_clk_cleanup(struct isc_device *isc); + +#endif diff --git a/drivers/staging/media/deprecated/atmel/atmel-sama5d2-isc.c b/drivers/staging/media/deprecated/atmel/atmel-sama5d2-isc.c new file mode 100644 index 000000000..ba0614f98 --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/atmel-sama5d2-isc.c @@ -0,0 +1,653 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip Image Sensor Controller (ISC) driver + * + * Copyright (C) 2016-2019 Microchip Technology, Inc. + * + * Author: Songjun Wu + * Author: Eugen Hristev + * + * + * Sensor-->PFE-->WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB-->RLP-->DMA + * + * ISC video pipeline integrates the following submodules: + * PFE: Parallel Front End to sample the camera sensor input stream + * WB: Programmable white balance in the Bayer domain + * CFA: Color filter array interpolation module + * CC: Programmable color correction + * GAM: Gamma correction + * CSC: Programmable color space conversion + * CBC: Contrast and Brightness control + * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling + * RLP: This module performs rounding, range limiting + * and packing of the incoming data + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "atmel-isc-regs.h" +#include "atmel-isc.h" + +#define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 +#define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 + +#define ISC_SAMA5D2_PIPELINE \ + (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ + CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) + +/* This is a list of the formats that the ISC can *output* */ +static const struct isc_format sama5d2_controller_formats[] = { + { + .fourcc = V4L2_PIX_FMT_ARGB444, + }, { + .fourcc = V4L2_PIX_FMT_ARGB555, + }, { + .fourcc = V4L2_PIX_FMT_RGB565, + }, { + .fourcc = V4L2_PIX_FMT_ABGR32, + }, { + .fourcc = V4L2_PIX_FMT_XBGR32, + }, { + .fourcc = V4L2_PIX_FMT_YUV420, + }, { + .fourcc = V4L2_PIX_FMT_YUYV, + }, { + .fourcc = V4L2_PIX_FMT_YUV422P, + }, { + .fourcc = V4L2_PIX_FMT_GREY, + }, { + .fourcc = V4L2_PIX_FMT_Y10, + }, { + .fourcc = V4L2_PIX_FMT_SBGGR8, + }, { + .fourcc = V4L2_PIX_FMT_SGBRG8, + }, { + .fourcc = V4L2_PIX_FMT_SGRBG8, + }, { + .fourcc = V4L2_PIX_FMT_SRGGB8, + }, { + .fourcc = V4L2_PIX_FMT_SBGGR10, + }, { + .fourcc = V4L2_PIX_FMT_SGBRG10, + }, { + .fourcc = V4L2_PIX_FMT_SGRBG10, + }, { + .fourcc = V4L2_PIX_FMT_SRGGB10, + }, +}; + +/* This is a list of formats that the ISC can receive as *input* */ +static struct isc_format sama5d2_formats_list[] = { + { + .fourcc = V4L2_PIX_FMT_SBGGR8, + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_BGBG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG8, + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG8, + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB8, + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SBGGR10, + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG10, + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG10, + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB10, + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SBGGR12, + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_BGBG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG12, + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG12, + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB12, + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_GREY, + .mbus_code = MEDIA_BUS_FMT_Y8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_RGB565, + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_Y10, + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + }, + +}; + +static void isc_sama5d2_config_csc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Convert RGB to YUV */ + regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, + 0x42 | (0x81 << 16)); + regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, + 0x19 | (0x10 << 16)); + regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, + 0xFDA | (0xFB6 << 16)); + regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, + 0x70 | (0x80 << 16)); + regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, + 0x70 | (0xFA2 << 16)); + regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, + 0xFEE | (0x80 << 16)); +} + +static void isc_sama5d2_config_cbc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, + isc->ctrls.brightness); + regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, + isc->ctrls.contrast); +} + +static void isc_sama5d2_config_cc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Configure each register at the neutral fixed point 1.0 or 0.0 */ + regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); + regmap_write(regmap, ISC_CC_RB_OR, 0); + regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); + regmap_write(regmap, ISC_CC_GB_OG, 0); + regmap_write(regmap, ISC_CC_BR_BG, 0); + regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); +} + +static void isc_sama5d2_config_ctrls(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops) +{ + struct isc_ctrls *ctrls = &isc->ctrls; + struct v4l2_ctrl_handler *hdl = &ctrls->handler; + + ctrls->contrast = 256; + + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); +} + +static void isc_sama5d2_config_dpc(struct isc_device *isc) +{ + /* This module is not present on sama5d2 pipeline */ +} + +static void isc_sama5d2_config_gam(struct isc_device *isc) +{ + /* No specific gamma configuration */ +} + +static void isc_sama5d2_config_rlp(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + u32 rlp_mode = isc->config.rlp_cfg_mode; + + /* + * In sama5d2, the YUV planar modes and the YUYV modes are treated + * in the same way in RLP register. + * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n) + * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n) + * but in sama5d2, the YCYC mode does not exist, and YYCC must be + * selected for both planar and interleaved modes, as in fact + * both modes are supported. + * + * Thus, if the YCYC mode is selected, replace it with the + * sama5d2-compliant mode which is YYCC . + */ + if ((rlp_mode & ISC_RLP_CFG_MODE_MASK) == ISC_RLP_CFG_MODE_YCYC) { + rlp_mode &= ~ISC_RLP_CFG_MODE_MASK; + rlp_mode |= ISC_RLP_CFG_MODE_YYCC; + } + + regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, + ISC_RLP_CFG_MODE_MASK, rlp_mode); +} + +static void isc_sama5d2_adapt_pipeline(struct isc_device *isc) +{ + isc->try_config.bits_pipeline &= ISC_SAMA5D2_PIPELINE; +} + +/* Gamma table with gamma 1/2.2 */ +static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ + { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, + 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, + 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, + 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, + 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, + 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, + 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, + 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, + 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, + 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, + 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, + + /* 1 --> gamma 1/2 */ + { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, + 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, + 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, + 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, + 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, + 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, + 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, + 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, + 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, + 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, + 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, + + /* 2 --> gamma 1/2.2 */ + { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, + 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, + 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, + 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, + 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, + 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, + 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, + 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, + 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, + 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, + 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, +}; + +static int isc_parse_dt(struct device *dev, struct isc_device *isc) +{ + struct device_node *np = dev->of_node; + struct device_node *epn = NULL; + struct isc_subdev_entity *subdev_entity; + unsigned int flags; + int ret; + + INIT_LIST_HEAD(&isc->subdev_entities); + + while (1) { + struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 }; + + epn = of_graph_get_next_endpoint(np, epn); + if (!epn) + return 0; + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), + &v4l2_epn); + if (ret) { + ret = -EINVAL; + dev_err(dev, "Could not parse the endpoint\n"); + break; + } + + subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity), + GFP_KERNEL); + if (!subdev_entity) { + ret = -ENOMEM; + break; + } + subdev_entity->epn = epn; + + flags = v4l2_epn.bus.parallel.flags; + + if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) + subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW; + + if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW; + + if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW; + + if (v4l2_epn.bus_type == V4L2_MBUS_BT656) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | + ISC_PFE_CFG0_CCIR656; + + list_add_tail(&subdev_entity->list, &isc->subdev_entities); + } + of_node_put(epn); + + return ret; +} + +static int atmel_isc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct isc_device *isc; + struct resource *res; + void __iomem *io_base; + struct isc_subdev_entity *subdev_entity; + int irq; + int ret; + u32 ver; + + isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); + if (!isc) + return -ENOMEM; + + platform_set_drvdata(pdev, isc); + isc->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + io_base = devm_ioremap_resource(dev, res); + if (IS_ERR(io_base)) + return PTR_ERR(io_base); + + isc->regmap = devm_regmap_init_mmio(dev, io_base, &atmel_isc_regmap_config); + if (IS_ERR(isc->regmap)) { + ret = PTR_ERR(isc->regmap); + dev_err(dev, "failed to init register map: %d\n", ret); + return ret; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(dev, irq, atmel_isc_interrupt, 0, + "atmel-sama5d2-isc", isc); + if (ret < 0) { + dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", + irq, ret); + return ret; + } + + isc->gamma_table = isc_sama5d2_gamma_table; + isc->gamma_max = 2; + + isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; + isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + + isc->config_dpc = isc_sama5d2_config_dpc; + isc->config_csc = isc_sama5d2_config_csc; + isc->config_cbc = isc_sama5d2_config_cbc; + isc->config_cc = isc_sama5d2_config_cc; + isc->config_gam = isc_sama5d2_config_gam; + isc->config_rlp = isc_sama5d2_config_rlp; + isc->config_ctrls = isc_sama5d2_config_ctrls; + + isc->adapt_pipeline = isc_sama5d2_adapt_pipeline; + + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; + isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; + isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; + isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; + isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; + isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; + isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; + isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; + isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; + + isc->controller_formats = sama5d2_controller_formats; + isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats); + isc->formats_list = sama5d2_formats_list; + isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list); + + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; + + /* sama5d2-isc : ISPCK is required and mandatory */ + isc->ispck_required = true; + + ret = atmel_isc_pipeline_init(isc); + if (ret) + return ret; + + isc->hclock = devm_clk_get(dev, "hclock"); + if (IS_ERR(isc->hclock)) { + ret = PTR_ERR(isc->hclock); + dev_err(dev, "failed to get hclock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(isc->hclock); + if (ret) { + dev_err(dev, "failed to enable hclock: %d\n", ret); + return ret; + } + + ret = atmel_isc_clk_init(isc); + if (ret) { + dev_err(dev, "failed to init isc clock: %d\n", ret); + goto unprepare_hclk; + } + ret = v4l2_device_register(dev, &isc->v4l2_dev); + if (ret) { + dev_err(dev, "unable to register v4l2 device.\n"); + goto unprepare_clk; + } + + ret = isc_parse_dt(dev, isc); + if (ret) { + dev_err(dev, "fail to parse device tree\n"); + goto unregister_v4l2_device; + } + + if (list_empty(&isc->subdev_entities)) { + dev_err(dev, "no subdev found\n"); + ret = -ENODEV; + goto unregister_v4l2_device; + } + + list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { + struct v4l2_async_subdev *asd; + struct fwnode_handle *fwnode = + of_fwnode_handle(subdev_entity->epn); + + v4l2_async_nf_init(&subdev_entity->notifier); + + asd = v4l2_async_nf_add_fwnode_remote(&subdev_entity->notifier, + fwnode, + struct v4l2_async_subdev); + + of_node_put(subdev_entity->epn); + subdev_entity->epn = NULL; + + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + goto cleanup_subdev; + } + + subdev_entity->notifier.ops = &atmel_isc_async_ops; + + ret = v4l2_async_nf_register(&isc->v4l2_dev, + &subdev_entity->notifier); + if (ret) { + dev_err(dev, "fail to register async notifier\n"); + goto cleanup_subdev; + } + + if (video_is_registered(&isc->video_dev)) + break; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_request_idle(dev); + + isc->ispck = isc->isc_clks[ISC_ISPCK].clk; + + ret = clk_prepare_enable(isc->ispck); + if (ret) { + dev_err(dev, "failed to enable ispck: %d\n", ret); + goto disable_pm; + } + + /* ispck should be greater or equal to hclock */ + ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock)); + if (ret) { + dev_err(dev, "failed to set ispck rate: %d\n", ret); + goto unprepare_clk; + } + + regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); + dev_info(dev, "Microchip ISC version %x\n", ver); + + return 0; + +unprepare_clk: + clk_disable_unprepare(isc->ispck); + +disable_pm: + pm_runtime_disable(dev); + +cleanup_subdev: + atmel_isc_subdev_cleanup(isc); + +unregister_v4l2_device: + v4l2_device_unregister(&isc->v4l2_dev); + +unprepare_hclk: + clk_disable_unprepare(isc->hclock); + + atmel_isc_clk_cleanup(isc); + + return ret; +} + +static int atmel_isc_remove(struct platform_device *pdev) +{ + struct isc_device *isc = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + + atmel_isc_subdev_cleanup(isc); + + v4l2_device_unregister(&isc->v4l2_dev); + + clk_disable_unprepare(isc->ispck); + clk_disable_unprepare(isc->hclock); + + atmel_isc_clk_cleanup(isc); + + return 0; +} + +static int __maybe_unused isc_runtime_suspend(struct device *dev) +{ + struct isc_device *isc = dev_get_drvdata(dev); + + clk_disable_unprepare(isc->ispck); + clk_disable_unprepare(isc->hclock); + + return 0; +} + +static int __maybe_unused isc_runtime_resume(struct device *dev) +{ + struct isc_device *isc = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(isc->hclock); + if (ret) + return ret; + + ret = clk_prepare_enable(isc->ispck); + if (ret) + clk_disable_unprepare(isc->hclock); + + return ret; +} + +static const struct dev_pm_ops atmel_isc_dev_pm_ops = { + SET_RUNTIME_PM_OPS(isc_runtime_suspend, isc_runtime_resume, NULL) +}; + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id atmel_isc_of_match[] = { + { .compatible = "atmel,sama5d2-isc" }, + { } +}; +MODULE_DEVICE_TABLE(of, atmel_isc_of_match); +#endif + +static struct platform_driver atmel_isc_driver = { + .probe = atmel_isc_probe, + .remove = atmel_isc_remove, + .driver = { + .name = "atmel-sama5d2-isc", + .pm = &atmel_isc_dev_pm_ops, + .of_match_table = of_match_ptr(atmel_isc_of_match), + }, +}; + +module_platform_driver(atmel_isc_driver); + +MODULE_AUTHOR("Songjun Wu"); +MODULE_DESCRIPTION("The V4L2 driver for Atmel-ISC"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/media/deprecated/atmel/atmel-sama7g5-isc.c b/drivers/staging/media/deprecated/atmel/atmel-sama7g5-isc.c new file mode 100644 index 000000000..01ababdfc --- /dev/null +++ b/drivers/staging/media/deprecated/atmel/atmel-sama7g5-isc.c @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip eXtended Image Sensor Controller (XISC) driver + * + * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Eugen Hristev + * + * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS + * + * ISC video pipeline integrates the following submodules: + * PFE: Parallel Front End to sample the camera sensor input stream + * DPC: Defective Pixel Correction with black offset correction, green disparity + * correction and defective pixel correction (3 modules total) + * WB: Programmable white balance in the Bayer domain + * CFA: Color filter array interpolation module + * CC: Programmable color correction + * GAM: Gamma correction + *VHXS: Vertical and Horizontal Scaler + * CSC: Programmable color space conversion + *CBHS: Contrast Brightness Hue and Saturation control + * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling + * RLP: This module performs rounding, range limiting + * and packing of the incoming data + * DMA: This module performs DMA master accesses to write frames to external RAM + * HIS: Histogram module performs statistic counters on the frames + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "atmel-isc-regs.h" +#include "atmel-isc.h" + +#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264 +#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464 + +#define ISC_SAMA7G5_PIPELINE \ + (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ + CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) + +/* This is a list of the formats that the ISC can *output* */ +static const struct isc_format sama7g5_controller_formats[] = { + { + .fourcc = V4L2_PIX_FMT_ARGB444, + }, { + .fourcc = V4L2_PIX_FMT_ARGB555, + }, { + .fourcc = V4L2_PIX_FMT_RGB565, + }, { + .fourcc = V4L2_PIX_FMT_ABGR32, + }, { + .fourcc = V4L2_PIX_FMT_XBGR32, + }, { + .fourcc = V4L2_PIX_FMT_YUV420, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + }, { + .fourcc = V4L2_PIX_FMT_VYUY, + }, { + .fourcc = V4L2_PIX_FMT_YUYV, + }, { + .fourcc = V4L2_PIX_FMT_YUV422P, + }, { + .fourcc = V4L2_PIX_FMT_GREY, + }, { + .fourcc = V4L2_PIX_FMT_Y10, + }, { + .fourcc = V4L2_PIX_FMT_Y16, + }, { + .fourcc = V4L2_PIX_FMT_SBGGR8, + }, { + .fourcc = V4L2_PIX_FMT_SGBRG8, + }, { + .fourcc = V4L2_PIX_FMT_SGRBG8, + }, { + .fourcc = V4L2_PIX_FMT_SRGGB8, + }, { + .fourcc = V4L2_PIX_FMT_SBGGR10, + }, { + .fourcc = V4L2_PIX_FMT_SGBRG10, + }, { + .fourcc = V4L2_PIX_FMT_SGRBG10, + }, { + .fourcc = V4L2_PIX_FMT_SRGGB10, + }, +}; + +/* This is a list of formats that the ISC can receive as *input* */ +static struct isc_format sama7g5_formats_list[] = { + { + .fourcc = V4L2_PIX_FMT_SBGGR8, + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_BGBG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG8, + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG8, + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB8, + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SBGGR10, + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG10, + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG10, + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB10, + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SBGGR12, + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_BGBG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG12, + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG12, + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB12, + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_GREY, + .mbus_code = MEDIA_BUS_FMT_Y8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_UYVY, + .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_RGB565, + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_Y10, + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + }, +}; + +static void isc_sama7g5_config_csc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Convert RGB to YUV */ + regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, + 0x42 | (0x81 << 16)); + regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, + 0x19 | (0x10 << 16)); + regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, + 0xFDA | (0xFB6 << 16)); + regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, + 0x70 | (0x80 << 16)); + regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, + 0x70 | (0xFA2 << 16)); + regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, + 0xFEE | (0x80 << 16)); +} + +static void isc_sama7g5_config_cbc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Configure what is set via v4l2 ctrls */ + regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness); + regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast); + /* Configure Hue and Saturation as neutral midpoint */ + regmap_write(regmap, ISC_CBCHS_HUE, 0); + regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4)); +} + +static void isc_sama7g5_config_cc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Configure each register at the neutral fixed point 1.0 or 0.0 */ + regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); + regmap_write(regmap, ISC_CC_RB_OR, 0); + regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); + regmap_write(regmap, ISC_CC_GB_OG, 0); + regmap_write(regmap, ISC_CC_BR_BG, 0); + regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); +} + +static void isc_sama7g5_config_ctrls(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops) +{ + struct isc_ctrls *ctrls = &isc->ctrls; + struct v4l2_ctrl_handler *hdl = &ctrls->handler; + + ctrls->contrast = 16; + + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16); +} + +static void isc_sama7g5_config_dpc(struct isc_device *isc) +{ + u32 bay_cfg = isc->config.sd_format->cfa_baycfg; + struct regmap *regmap = isc->regmap; + + regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, + (64 << ISC_DPC_CFG_BLOFF_SHIFT)); + regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, + (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); +} + +static void isc_sama7g5_config_gam(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART, + ISC_GAM_CTRL_BIPART); +} + +static void isc_sama7g5_config_rlp(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + u32 rlp_mode = isc->config.rlp_cfg_mode; + + regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, + ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH | + ISC_RLP_CFG_YMODE_MASK, rlp_mode); +} + +static void isc_sama7g5_adapt_pipeline(struct isc_device *isc) +{ + isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE; +} + +/* Gamma table with gamma 1/2.2 */ +static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = { + /* index 0 --> gamma bipartite */ + { + 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, + 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, + 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, + 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, + 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, + 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, + 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, + 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, + 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, + 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, + 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, +}; + +static int xisc_parse_dt(struct device *dev, struct isc_device *isc) +{ + struct device_node *np = dev->of_node; + struct device_node *epn = NULL; + struct isc_subdev_entity *subdev_entity; + unsigned int flags; + int ret; + bool mipi_mode; + + INIT_LIST_HEAD(&isc->subdev_entities); + + mipi_mode = of_property_read_bool(np, "microchip,mipi-mode"); + + while (1) { + struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 }; + + epn = of_graph_get_next_endpoint(np, epn); + if (!epn) + return 0; + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), + &v4l2_epn); + if (ret) { + ret = -EINVAL; + dev_err(dev, "Could not parse the endpoint\n"); + break; + } + + subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity), + GFP_KERNEL); + if (!subdev_entity) { + ret = -ENOMEM; + break; + } + subdev_entity->epn = epn; + + flags = v4l2_epn.bus.parallel.flags; + + if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) + subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW; + + if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW; + + if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW; + + if (v4l2_epn.bus_type == V4L2_MBUS_BT656) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | + ISC_PFE_CFG0_CCIR656; + + if (mipi_mode) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI; + + list_add_tail(&subdev_entity->list, &isc->subdev_entities); + } + of_node_put(epn); + + return ret; +} + +static int microchip_xisc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct isc_device *isc; + struct resource *res; + void __iomem *io_base; + struct isc_subdev_entity *subdev_entity; + int irq; + int ret; + u32 ver; + + isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); + if (!isc) + return -ENOMEM; + + platform_set_drvdata(pdev, isc); + isc->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + io_base = devm_ioremap_resource(dev, res); + if (IS_ERR(io_base)) + return PTR_ERR(io_base); + + isc->regmap = devm_regmap_init_mmio(dev, io_base, &atmel_isc_regmap_config); + if (IS_ERR(isc->regmap)) { + ret = PTR_ERR(isc->regmap); + dev_err(dev, "failed to init register map: %d\n", ret); + return ret; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(dev, irq, atmel_isc_interrupt, 0, + "microchip-sama7g5-xisc", isc); + if (ret < 0) { + dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", + irq, ret); + return ret; + } + + isc->gamma_table = isc_sama7g5_gamma_table; + isc->gamma_max = 0; + + isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH; + isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; + + isc->config_dpc = isc_sama7g5_config_dpc; + isc->config_csc = isc_sama7g5_config_csc; + isc->config_cbc = isc_sama7g5_config_cbc; + isc->config_cc = isc_sama7g5_config_cc; + isc->config_gam = isc_sama7g5_config_gam; + isc->config_rlp = isc_sama7g5_config_rlp; + isc->config_ctrls = isc_sama7g5_config_ctrls; + + isc->adapt_pipeline = isc_sama7g5_adapt_pipeline; + + isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; + isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET; + isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET; + isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET; + isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET; + isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET; + isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET; + isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET; + isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET; + + isc->controller_formats = sama7g5_controller_formats; + isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats); + isc->formats_list = sama7g5_formats_list; + isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list); + + /* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32; + + /* sama7g5-isc : ISPCK does not exist, ISC is clocked by MCK */ + isc->ispck_required = false; + + ret = atmel_isc_pipeline_init(isc); + if (ret) + return ret; + + isc->hclock = devm_clk_get(dev, "hclock"); + if (IS_ERR(isc->hclock)) { + ret = PTR_ERR(isc->hclock); + dev_err(dev, "failed to get hclock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(isc->hclock); + if (ret) { + dev_err(dev, "failed to enable hclock: %d\n", ret); + return ret; + } + + ret = atmel_isc_clk_init(isc); + if (ret) { + dev_err(dev, "failed to init isc clock: %d\n", ret); + goto unprepare_hclk; + } + + ret = v4l2_device_register(dev, &isc->v4l2_dev); + if (ret) { + dev_err(dev, "unable to register v4l2 device.\n"); + goto unprepare_hclk; + } + + ret = xisc_parse_dt(dev, isc); + if (ret) { + dev_err(dev, "fail to parse device tree\n"); + goto unregister_v4l2_device; + } + + if (list_empty(&isc->subdev_entities)) { + dev_err(dev, "no subdev found\n"); + ret = -ENODEV; + goto unregister_v4l2_device; + } + + list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { + struct v4l2_async_subdev *asd; + struct fwnode_handle *fwnode = + of_fwnode_handle(subdev_entity->epn); + + v4l2_async_nf_init(&subdev_entity->notifier); + + asd = v4l2_async_nf_add_fwnode_remote(&subdev_entity->notifier, + fwnode, + struct v4l2_async_subdev); + + of_node_put(subdev_entity->epn); + subdev_entity->epn = NULL; + + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + goto cleanup_subdev; + } + + subdev_entity->notifier.ops = &atmel_isc_async_ops; + + ret = v4l2_async_nf_register(&isc->v4l2_dev, + &subdev_entity->notifier); + if (ret) { + dev_err(dev, "fail to register async notifier\n"); + goto cleanup_subdev; + } + + if (video_is_registered(&isc->video_dev)) + break; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_request_idle(dev); + + regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); + dev_info(dev, "Microchip XISC version %x\n", ver); + + return 0; + +cleanup_subdev: + atmel_isc_subdev_cleanup(isc); + +unregister_v4l2_device: + v4l2_device_unregister(&isc->v4l2_dev); + +unprepare_hclk: + clk_disable_unprepare(isc->hclock); + + atmel_isc_clk_cleanup(isc); + + return ret; +} + +static int microchip_xisc_remove(struct platform_device *pdev) +{ + struct isc_device *isc = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + + atmel_isc_subdev_cleanup(isc); + + v4l2_device_unregister(&isc->v4l2_dev); + + clk_disable_unprepare(isc->hclock); + + atmel_isc_clk_cleanup(isc); + + return 0; +} + +static int __maybe_unused xisc_runtime_suspend(struct device *dev) +{ + struct isc_device *isc = dev_get_drvdata(dev); + + clk_disable_unprepare(isc->hclock); + + return 0; +} + +static int __maybe_unused xisc_runtime_resume(struct device *dev) +{ + struct isc_device *isc = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(isc->hclock); + if (ret) + return ret; + + return ret; +} + +static const struct dev_pm_ops microchip_xisc_dev_pm_ops = { + SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL) +}; + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id microchip_xisc_of_match[] = { + { .compatible = "microchip,sama7g5-isc" }, + { } +}; +MODULE_DEVICE_TABLE(of, microchip_xisc_of_match); +#endif + +static struct platform_driver microchip_xisc_driver = { + .probe = microchip_xisc_probe, + .remove = microchip_xisc_remove, + .driver = { + .name = "microchip-sama7g5-xisc", + .pm = µchip_xisc_dev_pm_ops, + .of_match_table = of_match_ptr(microchip_xisc_of_match), + }, +}; + +module_platform_driver(microchip_xisc_driver); + +MODULE_AUTHOR("Eugen Hristev "); +MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/media/deprecated/cpia2/Kconfig b/drivers/staging/media/deprecated/cpia2/Kconfig new file mode 100644 index 000000000..ee3b25a75 --- /dev/null +++ b/drivers/staging/media/deprecated/cpia2/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_CPIA2 + tristate "CPiA2 Video For Linux (DEPRECATED)" + depends on USB && VIDEO_DEV + help + This is the video4linux driver for cameras based on Vision's CPiA2 + (Colour Processor Interface ASIC), such as the Digital Blue QX5 + Microscope. If you have one of these cameras, say Y here + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + This driver is also available as a module (cpia2). diff --git a/drivers/staging/media/deprecated/cpia2/Makefile b/drivers/staging/media/deprecated/cpia2/Makefile new file mode 100644 index 000000000..05664141f --- /dev/null +++ b/drivers/staging/media/deprecated/cpia2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +cpia2-objs := cpia2_v4l.o cpia2_usb.o cpia2_core.o + +obj-$(CONFIG_VIDEO_CPIA2) += cpia2.o diff --git a/drivers/staging/media/deprecated/cpia2/TODO b/drivers/staging/media/deprecated/cpia2/TODO new file mode 100644 index 000000000..92ac8718d --- /dev/null +++ b/drivers/staging/media/deprecated/cpia2/TODO @@ -0,0 +1,6 @@ +The cpia2 driver does not use the vb2 framework for streaming +video, instead it implements this in the driver. + +To prevent removal of this driver early 2023 it has to be +converted to use vb2. Contact the linux-media@vger.kernel.org +mailing list if you want to do this. diff --git a/drivers/staging/media/deprecated/cpia2/cpia2.h b/drivers/staging/media/deprecated/cpia2/cpia2.h new file mode 100644 index 000000000..57b7f1ea6 --- /dev/null +++ b/drivers/staging/media/deprecated/cpia2/cpia2.h @@ -0,0 +1,475 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + * + * Filename: cpia2.h + * + * Copyright 2001, STMicrolectronics, Inc. + * + * Contact: steve.miller@st.com + * + * Description: + * This is a USB driver for CPiA2 based video cameras. + * + * This driver is modelled on the cpia usb driver by + * Jochen Scharrlach and Johannes Erdfeldt. + * + ****************************************************************************/ + +#ifndef __CPIA2_H__ +#define __CPIA2_H__ + +#include +#include +#include +#include +#include +#include + +#include "cpia2_registers.h" + +/* define for verbose debug output */ +//#define _CPIA2_DEBUG_ + +/*** + * Image defines + ***/ + +/* Misc constants */ +#define ALLOW_CORRUPT 0 /* Causes collater to discard checksum */ + +/* USB Transfer mode */ +#define XFER_ISOC 0 +#define XFER_BULK 1 + +/* USB Alternates */ +#define USBIF_CMDONLY 0 +#define USBIF_BULK 1 +#define USBIF_ISO_1 2 /* 128 bytes/ms */ +#define USBIF_ISO_2 3 /* 384 bytes/ms */ +#define USBIF_ISO_3 4 /* 640 bytes/ms */ +#define USBIF_ISO_4 5 /* 768 bytes/ms */ +#define USBIF_ISO_5 6 /* 896 bytes/ms */ +#define USBIF_ISO_6 7 /* 1023 bytes/ms */ + +/* Flicker Modes */ +#define NEVER_FLICKER 0 +#define FLICKER_60 60 +#define FLICKER_50 50 + +/* Debug flags */ +#define DEBUG_NONE 0 +#define DEBUG_REG 0x00000001 +#define DEBUG_DUMP_PATCH 0x00000002 +#define DEBUG_DUMP_REGS 0x00000004 + +/*** + * Video frame sizes + ***/ +enum { + VIDEOSIZE_VGA = 0, /* 640x480 */ + VIDEOSIZE_CIF, /* 352x288 */ + VIDEOSIZE_QVGA, /* 320x240 */ + VIDEOSIZE_QCIF, /* 176x144 */ + VIDEOSIZE_288_216, + VIDEOSIZE_256_192, + VIDEOSIZE_224_168, + VIDEOSIZE_192_144, +}; + +#define STV_IMAGE_CIF_ROWS 288 +#define STV_IMAGE_CIF_COLS 352 + +#define STV_IMAGE_QCIF_ROWS 144 +#define STV_IMAGE_QCIF_COLS 176 + +#define STV_IMAGE_VGA_ROWS 480 +#define STV_IMAGE_VGA_COLS 640 + +#define STV_IMAGE_QVGA_ROWS 240 +#define STV_IMAGE_QVGA_COLS 320 + +#define JPEG_MARKER_COM (1<<6) /* Comment segment */ + +/*** + * Enums + ***/ +/* Sensor types available with cpia2 asics */ +enum sensors { + CPIA2_SENSOR_410, + CPIA2_SENSOR_500 +}; + +/* Asic types available in the CPiA2 architecture */ +#define CPIA2_ASIC_672 0x67 + +/* Device types (stv672, stv676, etc) */ +#define DEVICE_STV_672 0x0001 +#define DEVICE_STV_676 0x0002 + +enum frame_status { + FRAME_EMPTY, + FRAME_READING, /* In the process of being grabbed into */ + FRAME_READY, /* Ready to be read */ + FRAME_ERROR, +}; + +/*** + * Register access (for USB request byte) + ***/ +enum { + CAMERAACCESS_SYSTEM = 0, + CAMERAACCESS_VC, + CAMERAACCESS_VP, + CAMERAACCESS_IDATA +}; + +#define CAMERAACCESS_TYPE_BLOCK 0x00 +#define CAMERAACCESS_TYPE_RANDOM 0x04 +#define CAMERAACCESS_TYPE_MASK 0x08 +#define CAMERAACCESS_TYPE_REPEAT 0x0C + +#define TRANSFER_READ 0 +#define TRANSFER_WRITE 1 + +#define DEFAULT_ALT USBIF_ISO_6 +#define DEFAULT_BRIGHTNESS 0x46 +#define DEFAULT_CONTRAST 0x93 +#define DEFAULT_SATURATION 0x7f + +/* Power state */ +#define HI_POWER_MODE CPIA2_SYSTEM_CONTROL_HIGH_POWER +#define LO_POWER_MODE CPIA2_SYSTEM_CONTROL_LOW_POWER + + +/******** + * Commands + *******/ +enum { + CPIA2_CMD_NONE = 0, + CPIA2_CMD_GET_VERSION, + CPIA2_CMD_GET_PNP_ID, + CPIA2_CMD_GET_ASIC_TYPE, + CPIA2_CMD_GET_SENSOR, + CPIA2_CMD_GET_VP_DEVICE, + CPIA2_CMD_GET_VP_BRIGHTNESS, + CPIA2_CMD_SET_VP_BRIGHTNESS, + CPIA2_CMD_GET_CONTRAST, + CPIA2_CMD_SET_CONTRAST, + CPIA2_CMD_GET_VP_SATURATION, + CPIA2_CMD_SET_VP_SATURATION, + CPIA2_CMD_GET_VP_GPIO_DIRECTION, + CPIA2_CMD_SET_VP_GPIO_DIRECTION, + CPIA2_CMD_GET_VP_GPIO_DATA, + CPIA2_CMD_SET_VP_GPIO_DATA, + CPIA2_CMD_GET_VC_MP_GPIO_DIRECTION, + CPIA2_CMD_SET_VC_MP_GPIO_DIRECTION, + CPIA2_CMD_GET_VC_MP_GPIO_DATA, + CPIA2_CMD_SET_VC_MP_GPIO_DATA, + CPIA2_CMD_ENABLE_PACKET_CTRL, + CPIA2_CMD_GET_FLICKER_MODES, + CPIA2_CMD_SET_FLICKER_MODES, + CPIA2_CMD_RESET_FIFO, /* clear fifo and enable stream block */ + CPIA2_CMD_SET_HI_POWER, + CPIA2_CMD_SET_LOW_POWER, + CPIA2_CMD_CLEAR_V2W_ERR, + CPIA2_CMD_SET_USER_MODE, + CPIA2_CMD_GET_USER_MODE, + CPIA2_CMD_FRAMERATE_REQ, + CPIA2_CMD_SET_COMPRESSION_STATE, + CPIA2_CMD_GET_WAKEUP, + CPIA2_CMD_SET_WAKEUP, + CPIA2_CMD_GET_PW_CONTROL, + CPIA2_CMD_SET_PW_CONTROL, + CPIA2_CMD_GET_SYSTEM_CTRL, + CPIA2_CMD_SET_SYSTEM_CTRL, + CPIA2_CMD_GET_VP_SYSTEM_STATE, + CPIA2_CMD_GET_VP_SYSTEM_CTRL, + CPIA2_CMD_SET_VP_SYSTEM_CTRL, + CPIA2_CMD_GET_VP_EXP_MODES, + CPIA2_CMD_SET_VP_EXP_MODES, + CPIA2_CMD_GET_DEVICE_CONFIG, + CPIA2_CMD_SET_DEVICE_CONFIG, + CPIA2_CMD_SET_SERIAL_ADDR, + CPIA2_CMD_SET_SENSOR_CR1, + CPIA2_CMD_GET_VC_CONTROL, + CPIA2_CMD_SET_VC_CONTROL, + CPIA2_CMD_SET_TARGET_KB, + CPIA2_CMD_SET_DEF_JPEG_OPT, + CPIA2_CMD_REHASH_VP4, + CPIA2_CMD_GET_USER_EFFECTS, + CPIA2_CMD_SET_USER_EFFECTS +}; + +enum user_cmd { + COMMAND_NONE = 0x00000001, + COMMAND_SET_FPS = 0x00000002, + COMMAND_SET_COLOR_PARAMS = 0x00000004, + COMMAND_GET_COLOR_PARAMS = 0x00000008, + COMMAND_SET_FORMAT = 0x00000010, /* size, etc */ + COMMAND_SET_FLICKER = 0x00000020 +}; + +/*** + * Some defines specific to the 676 chip + ***/ +#define CAMACC_CIF 0x01 +#define CAMACC_VGA 0x02 +#define CAMACC_QCIF 0x04 +#define CAMACC_QVGA 0x08 + + +struct cpia2_register { + u8 index; + u8 value; +}; + +struct cpia2_reg_mask { + u8 index; + u8 and_mask; + u8 or_mask; + u8 fill; +}; + +struct cpia2_command { + u32 command; + u8 req_mode; /* (Block or random) | registerBank */ + u8 reg_count; + u8 direction; + u8 start; + union reg_types { + struct cpia2_register registers[32]; + struct cpia2_reg_mask masks[16]; + u8 block_data[64]; + u8 *patch_data; /* points to function defined block */ + } buffer; +}; + +struct camera_params { + struct { + u8 firmware_revision_hi; /* For system register set (bank 0) */ + u8 firmware_revision_lo; + u8 asic_id; /* Video Compressor set (bank 1) */ + u8 asic_rev; + u8 vp_device_hi; /* Video Processor set (bank 2) */ + u8 vp_device_lo; + u8 sensor_flags; + u8 sensor_rev; + } version; + + struct { + u32 device_type; /* enumerated from vendor/product ids. + * Currently, either STV_672 or STV_676 */ + u16 vendor; + u16 product; + u16 device_revision; + } pnp_id; + + struct { + u8 brightness; /* CPIA2_VP_EXPOSURE_TARGET */ + u8 contrast; /* Note: this is CPIA2_VP_YRANGE */ + u8 saturation; /* CPIA2_VP_SATURATION */ + } color_params; + + struct { + u8 cam_register; + u8 flicker_mode_req; /* 1 if flicker on, else never flicker */ + } flicker_control; + + struct { + u8 jpeg_options; + u8 creep_period; + u8 user_squeeze; + u8 inhibit_htables; + } compression; + + struct { + u8 ohsize; /* output image size */ + u8 ovsize; + u8 hcrop; /* cropping start_pos/4 */ + u8 vcrop; + u8 hphase; /* scaling registers */ + u8 vphase; + u8 hispan; + u8 vispan; + u8 hicrop; + u8 vicrop; + u8 hifraction; + u8 vifraction; + } image_size; + + struct { + int width; /* actual window width */ + int height; /* actual window height */ + } roi; + + struct { + u8 video_mode; + u8 frame_rate; + u8 video_size; /* Not a register, just a convenience for cropped sizes */ + u8 gpio_direction; + u8 gpio_data; + u8 system_ctrl; + u8 system_state; + u8 lowlight_boost; /* Bool: 0 = off, 1 = on */ + u8 device_config; + u8 exposure_modes; + u8 user_effects; + } vp_params; + + struct { + u8 pw_control; + u8 wakeup; + u8 vc_control; + u8 vc_mp_direction; + u8 vc_mp_data; + u8 quality; + } vc_params; + + struct { + u8 power_mode; + u8 system_ctrl; + u8 stream_mode; /* This is the current alternate for usb drivers */ + u8 allow_corrupt; + } camera_state; +}; + +#define NUM_SBUF 2 + +struct cpia2_sbuf { + char *data; + struct urb *urb; +}; + +struct framebuf { + u64 ts; + unsigned long seq; + int num; + int length; + int max_length; + volatile enum frame_status status; + u8 *data; + struct framebuf *next; +}; + +struct camera_data { + /* locks */ + struct v4l2_device v4l2_dev; + struct mutex v4l2_lock; /* serialize file operations */ + struct v4l2_ctrl_handler hdl; + struct { + /* Lights control cluster */ + struct v4l2_ctrl *top_light; + struct v4l2_ctrl *bottom_light; + }; + struct v4l2_ctrl *usb_alt; + + /* camera status */ + int first_image_seen; + enum sensors sensor_type; + u8 flush; + struct v4l2_fh *stream_fh; + u8 mmapped; + int streaming; /* 0 = no, 1 = yes */ + int xfer_mode; /* XFER_BULK or XFER_ISOC */ + struct camera_params params; /* camera settings */ + + /* v4l */ + int video_size; /* VIDEO_SIZE_ */ + struct video_device vdev; /* v4l videodev */ + u32 width; + u32 height; /* Its size */ + __u32 pixelformat; /* Format fourcc */ + + /* USB */ + struct usb_device *dev; + unsigned char iface; + unsigned int cur_alt; + unsigned int old_alt; + struct cpia2_sbuf sbuf[NUM_SBUF]; /* Double buffering */ + + wait_queue_head_t wq_stream; + + /* Buffering */ + u32 frame_size; + int num_frames; + unsigned long frame_count; + u8 *frame_buffer; /* frame buffer data */ + struct framebuf *buffers; + struct framebuf * volatile curbuff; + struct framebuf *workbuff; + + /* MJPEG Extension */ + int APPn; /* Number of APP segment to be written, must be 0..15 */ + int APP_len; /* Length of data in JPEG APPn segment */ + char APP_data[60]; /* Data in the JPEG APPn segment. */ + + int COM_len; /* Length of data in JPEG COM segment */ + char COM_data[60]; /* Data in JPEG COM segment */ +}; + +/* v4l */ +int cpia2_register_camera(struct camera_data *cam); +void cpia2_unregister_camera(struct camera_data *cam); +void cpia2_camera_release(struct v4l2_device *v4l2_dev); + +/* core */ +int cpia2_reset_camera(struct camera_data *cam); +int cpia2_set_low_power(struct camera_data *cam); +void cpia2_dbg_dump_registers(struct camera_data *cam); +int cpia2_match_video_size(int width, int height); +void cpia2_set_camera_state(struct camera_data *cam); +void cpia2_save_camera_state(struct camera_data *cam); +void cpia2_set_color_params(struct camera_data *cam); +void cpia2_set_brightness(struct camera_data *cam, unsigned char value); +void cpia2_set_contrast(struct camera_data *cam, unsigned char value); +void cpia2_set_saturation(struct camera_data *cam, unsigned char value); +int cpia2_set_flicker_mode(struct camera_data *cam, int mode); +void cpia2_set_format(struct camera_data *cam); +int cpia2_send_command(struct camera_data *cam, struct cpia2_command *cmd); +int cpia2_do_command(struct camera_data *cam, + unsigned int command, + unsigned char direction, unsigned char param); +void cpia2_deinit_camera_struct(struct camera_data *cam, struct usb_interface *intf); +struct camera_data *cpia2_init_camera_struct(struct usb_interface *intf); +int cpia2_init_camera(struct camera_data *cam); +int cpia2_allocate_buffers(struct camera_data *cam); +void cpia2_free_buffers(struct camera_data *cam); +long cpia2_read(struct camera_data *cam, + char __user *buf, unsigned long count, int noblock); +__poll_t cpia2_poll(struct camera_data *cam, + struct file *filp, poll_table *wait); +int cpia2_remap_buffer(struct camera_data *cam, struct vm_area_struct *vma); +void cpia2_set_property_flip(struct camera_data *cam, int prop_val); +void cpia2_set_property_mirror(struct camera_data *cam, int prop_val); +int cpia2_set_gpio(struct camera_data *cam, unsigned char setting); +int cpia2_set_fps(struct camera_data *cam, int framerate); + +/* usb */ +int cpia2_usb_init(void); +void cpia2_usb_cleanup(void); +int cpia2_usb_transfer_cmd(struct camera_data *cam, void *registers, + u8 request, u8 start, u8 count, u8 direction); +int cpia2_usb_stream_start(struct camera_data *cam, unsigned int alternate); +int cpia2_usb_stream_stop(struct camera_data *cam); +int cpia2_usb_stream_pause(struct camera_data *cam); +int cpia2_usb_stream_resume(struct camera_data *cam); +int cpia2_usb_change_streaming_alternate(struct camera_data *cam, + unsigned int alt); + + +/* ----------------------- debug functions ---------------------- */ +#ifdef _CPIA2_DEBUG_ +#define ALOG(lev, fmt, args...) printk(lev "%s:%d %s(): " fmt, __FILE__, __LINE__, __func__, ## args) +#define LOG(fmt, args...) ALOG(KERN_INFO, fmt, ## args) +#define ERR(fmt, args...) ALOG(KERN_ERR, fmt, ## args) +#define DBG(fmt, args...) ALOG(KERN_DEBUG, fmt, ## args) +#else +#define ALOG(fmt,args...) printk(fmt,##args) +#define LOG(fmt,args...) ALOG(KERN_INFO "cpia2: "fmt,##args) +#define ERR(fmt,args...) ALOG(KERN_ERR "cpia2: "fmt,##args) +#define DBG(fmn,args...) do {} while(0) +#endif +/* No function or lineno, for shorter lines */ +#define KINFO(fmt, args...) printk(KERN_INFO fmt,##args) + +#endif diff --git a/drivers/staging/media/deprecated/cpia2/cpia2_core.c b/drivers/staging/media/deprecated/cpia2/cpia2_core.c new file mode 100644 index 000000000..b5a2d06fb --- /dev/null +++ b/drivers/staging/media/deprecated/cpia2/cpia2_core.c @@ -0,0 +1,2434 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/**************************************************************************** + * + * Filename: cpia2_core.c + * + * Copyright 2001, STMicrolectronics, Inc. + * Contact: steve.miller@st.com + * + * Description: + * This is a USB driver for CPia2 based video cameras. + * The infrastructure of this driver is based on the cpia usb driver by + * Jochen Scharrlach and Johannes Erdfeldt. + * + * Stripped of 2.4 stuff ready for main kernel submit by + * Alan Cox + * + ****************************************************************************/ + +#include "cpia2.h" + +#include +#include +#include +#include +#include +#include + +#define FIRMWARE "cpia2/stv0672_vp4.bin" +MODULE_FIRMWARE(FIRMWARE); + +/* #define _CPIA2_DEBUG_ */ + +#ifdef _CPIA2_DEBUG_ + +static const char *block_name[] = { + "System", + "VC", + "VP", + "IDATA" +}; +#endif + +static unsigned int debugs_on; /* default 0 - DEBUG_REG */ + + +/****************************************************************************** + * + * Forward Declarations + * + *****************************************************************************/ +static int apply_vp_patch(struct camera_data *cam); +static int set_default_user_mode(struct camera_data *cam); +static int set_vw_size(struct camera_data *cam, int size); +static int configure_sensor(struct camera_data *cam, + int reqwidth, int reqheight); +static int config_sensor_410(struct camera_data *cam, + int reqwidth, int reqheight); +static int config_sensor_500(struct camera_data *cam, + int reqwidth, int reqheight); +static int set_all_properties(struct camera_data *cam); +static void wake_system(struct camera_data *cam); +static void set_lowlight_boost(struct camera_data *cam); +static void reset_camera_struct(struct camera_data *cam); +static int cpia2_set_high_power(struct camera_data *cam); + +/* Here we want the physical address of the memory. + * This is used when initializing the contents of the + * area and marking the pages as reserved. + */ +static inline unsigned long kvirt_to_pa(unsigned long adr) +{ + unsigned long kva, ret; + + kva = (unsigned long) page_address(vmalloc_to_page((void *)adr)); + kva |= adr & (PAGE_SIZE-1); /* restore the offset */ + ret = __pa(kva); + return ret; +} + +static void *rvmalloc(unsigned long size) +{ + void *mem; + unsigned long adr; + + /* Round it off to PAGE_SIZE */ + size = PAGE_ALIGN(size); + + mem = vmalloc_32(size); + if (!mem) + return NULL; + + memset(mem, 0, size); /* Clear the ram out, no junk to the user */ + adr = (unsigned long) mem; + + while ((long)size > 0) { + SetPageReserved(vmalloc_to_page((void *)adr)); + adr += PAGE_SIZE; + size -= PAGE_SIZE; + } + return mem; +} + +static void rvfree(void *mem, unsigned long size) +{ + unsigned long adr; + + if (!mem) + return; + + size = PAGE_ALIGN(size); + + adr = (unsigned long) mem; + while ((long)size > 0) { + ClearPageReserved(vmalloc_to_page((void *)adr)); + adr += PAGE_SIZE; + size -= PAGE_SIZE; + } + vfree(mem); +} + +/****************************************************************************** + * + * cpia2_do_command + * + * Send an arbitrary command to the camera. For commands that read from + * the camera, copy the buffers into the proper param structures. + *****************************************************************************/ +int cpia2_do_command(struct camera_data *cam, + u32 command, u8 direction, u8 param) +{ + int retval = 0; + struct cpia2_command cmd; + unsigned int device = cam->params.pnp_id.device_type; + + cmd.command = command; + cmd.reg_count = 2; /* default */ + cmd.direction = direction; + + /*** + * Set up the command. + ***/ + switch (command) { + case CPIA2_CMD_GET_VERSION: + cmd.req_mode = + CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_SYSTEM; + cmd.start = CPIA2_SYSTEM_DEVICE_HI; + break; + case CPIA2_CMD_GET_PNP_ID: + cmd.req_mode = + CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_SYSTEM; + cmd.reg_count = 8; + cmd.start = CPIA2_SYSTEM_DESCRIP_VID_HI; + break; + case CPIA2_CMD_GET_ASIC_TYPE: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.start = CPIA2_VC_ASIC_ID; + break; + case CPIA2_CMD_GET_SENSOR: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.start = CPIA2_VP_SENSOR_FLAGS; + break; + case CPIA2_CMD_GET_VP_DEVICE: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.start = CPIA2_VP_DEVICEH; + break; + case CPIA2_CMD_SET_VP_BRIGHTNESS: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VP_BRIGHTNESS: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + if (device == DEVICE_STV_672) + cmd.start = CPIA2_VP4_EXPOSURE_TARGET; + else + cmd.start = CPIA2_VP5_EXPOSURE_TARGET; + break; + case CPIA2_CMD_SET_CONTRAST: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_CONTRAST: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_YRANGE; + break; + case CPIA2_CMD_SET_VP_SATURATION: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VP_SATURATION: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + if (device == DEVICE_STV_672) + cmd.start = CPIA2_VP_SATURATION; + else + cmd.start = CPIA2_VP5_MCUVSATURATION; + break; + case CPIA2_CMD_SET_VP_GPIO_DATA: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VP_GPIO_DATA: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_GPIO_DATA; + break; + case CPIA2_CMD_SET_VP_GPIO_DIRECTION: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VP_GPIO_DIRECTION: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_GPIO_DIRECTION; + break; + case CPIA2_CMD_SET_VC_MP_GPIO_DATA: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VC_MP_GPIO_DATA: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.reg_count = 1; + cmd.start = CPIA2_VC_MP_DATA; + break; + case CPIA2_CMD_SET_VC_MP_GPIO_DIRECTION: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VC_MP_GPIO_DIRECTION: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.reg_count = 1; + cmd.start = CPIA2_VC_MP_DIR; + break; + case CPIA2_CMD_ENABLE_PACKET_CTRL: + cmd.req_mode = + CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_SYSTEM; + cmd.start = CPIA2_SYSTEM_INT_PACKET_CTRL; + cmd.reg_count = 1; + cmd.buffer.block_data[0] = param; + break; + case CPIA2_CMD_SET_FLICKER_MODES: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_FLICKER_MODES: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_FLICKER_MODES; + break; + case CPIA2_CMD_RESET_FIFO: /* clear fifo and enable stream block */ + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VC; + cmd.reg_count = 2; + cmd.start = 0; + cmd.buffer.registers[0].index = CPIA2_VC_ST_CTRL; + cmd.buffer.registers[0].value = CPIA2_VC_ST_CTRL_SRC_VC | + CPIA2_VC_ST_CTRL_DST_USB | CPIA2_VC_ST_CTRL_EOF_DETECT; + cmd.buffer.registers[1].index = CPIA2_VC_ST_CTRL; + cmd.buffer.registers[1].value = CPIA2_VC_ST_CTRL_SRC_VC | + CPIA2_VC_ST_CTRL_DST_USB | + CPIA2_VC_ST_CTRL_EOF_DETECT | + CPIA2_VC_ST_CTRL_FIFO_ENABLE; + break; + case CPIA2_CMD_SET_HI_POWER: + cmd.req_mode = + CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_SYSTEM; + cmd.reg_count = 2; + cmd.buffer.registers[0].index = + CPIA2_SYSTEM_SYSTEM_CONTROL; + cmd.buffer.registers[1].index = + CPIA2_SYSTEM_SYSTEM_CONTROL; + cmd.buffer.registers[0].value = CPIA2_SYSTEM_CONTROL_CLEAR_ERR; + cmd.buffer.registers[1].value = + CPIA2_SYSTEM_CONTROL_HIGH_POWER; + break; + case CPIA2_CMD_SET_LOW_POWER: + cmd.req_mode = + CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_SYSTEM; + cmd.reg_count = 1; + cmd.start = CPIA2_SYSTEM_SYSTEM_CONTROL; + cmd.buffer.block_data[0] = 0; + break; + case CPIA2_CMD_CLEAR_V2W_ERR: + cmd.req_mode = + CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_SYSTEM; + cmd.reg_count = 1; + cmd.start = CPIA2_SYSTEM_SYSTEM_CONTROL; + cmd.buffer.block_data[0] = CPIA2_SYSTEM_CONTROL_CLEAR_ERR; + break; + case CPIA2_CMD_SET_USER_MODE: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_USER_MODE: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + if (device == DEVICE_STV_672) + cmd.start = CPIA2_VP4_USER_MODE; + else + cmd.start = CPIA2_VP5_USER_MODE; + break; + case CPIA2_CMD_FRAMERATE_REQ: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + if (device == DEVICE_STV_672) + cmd.start = CPIA2_VP4_FRAMERATE_REQUEST; + else + cmd.start = CPIA2_VP5_FRAMERATE_REQUEST; + cmd.buffer.block_data[0] = param; + break; + case CPIA2_CMD_SET_WAKEUP: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_WAKEUP: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.reg_count = 1; + cmd.start = CPIA2_VC_WAKEUP; + break; + case CPIA2_CMD_SET_PW_CONTROL: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_PW_CONTROL: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.reg_count = 1; + cmd.start = CPIA2_VC_PW_CTRL; + break; + case CPIA2_CMD_GET_VP_SYSTEM_STATE: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_SYSTEMSTATE; + break; + case CPIA2_CMD_SET_SYSTEM_CTRL: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_SYSTEM_CTRL: + cmd.req_mode = + CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_SYSTEM; + cmd.reg_count = 1; + cmd.start = CPIA2_SYSTEM_SYSTEM_CONTROL; + break; + case CPIA2_CMD_SET_VP_SYSTEM_CTRL: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VP_SYSTEM_CTRL: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_SYSTEMCTRL; + break; + case CPIA2_CMD_SET_VP_EXP_MODES: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VP_EXP_MODES: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_EXPOSURE_MODES; + break; + case CPIA2_CMD_SET_DEVICE_CONFIG: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_DEVICE_CONFIG: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_DEVICE_CONFIG; + break; + case CPIA2_CMD_SET_SERIAL_ADDR: + cmd.buffer.block_data[0] = param; + cmd.req_mode = + CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_SYSTEM; + cmd.reg_count = 1; + cmd.start = CPIA2_SYSTEM_VP_SERIAL_ADDR; + break; + case CPIA2_CMD_SET_SENSOR_CR1: + cmd.buffer.block_data[0] = param; + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_SENSOR_CR1; + break; + case CPIA2_CMD_SET_VC_CONTROL: + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_VC_CONTROL: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.reg_count = 1; + cmd.start = CPIA2_VC_VC_CTRL; + break; + case CPIA2_CMD_SET_TARGET_KB: + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VC; + cmd.reg_count = 1; + cmd.buffer.registers[0].index = CPIA2_VC_VC_TARGET_KB; + cmd.buffer.registers[0].value = param; + break; + case CPIA2_CMD_SET_DEF_JPEG_OPT: + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VC; + cmd.reg_count = 4; + cmd.buffer.registers[0].index = CPIA2_VC_VC_JPEG_OPT; + cmd.buffer.registers[0].value = + CPIA2_VC_VC_JPEG_OPT_DOUBLE_SQUEEZE; + cmd.buffer.registers[1].index = CPIA2_VC_VC_USER_SQUEEZE; + cmd.buffer.registers[1].value = 20; + cmd.buffer.registers[2].index = CPIA2_VC_VC_CREEP_PERIOD; + cmd.buffer.registers[2].value = 2; + cmd.buffer.registers[3].index = CPIA2_VC_VC_JPEG_OPT; + cmd.buffer.registers[3].value = CPIA2_VC_VC_JPEG_OPT_DEFAULT; + break; + case CPIA2_CMD_REHASH_VP4: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + cmd.start = CPIA2_VP_REHASH_VALUES; + cmd.buffer.block_data[0] = param; + break; + case CPIA2_CMD_SET_USER_EFFECTS: /* Note: Be careful with this as + this register can also affect + flicker modes */ + cmd.buffer.block_data[0] = param; + fallthrough; + case CPIA2_CMD_GET_USER_EFFECTS: + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 1; + if (device == DEVICE_STV_672) + cmd.start = CPIA2_VP4_USER_EFFECTS; + else + cmd.start = CPIA2_VP5_USER_EFFECTS; + break; + default: + LOG("DoCommand received invalid command\n"); + return -EINVAL; + } + + retval = cpia2_send_command(cam, &cmd); + if (retval) { + return retval; + } + + /*** + * Now copy any results from a read into the appropriate param struct. + ***/ + switch (command) { + case CPIA2_CMD_GET_VERSION: + cam->params.version.firmware_revision_hi = + cmd.buffer.block_data[0]; + cam->params.version.firmware_revision_lo = + cmd.buffer.block_data[1]; + break; + case CPIA2_CMD_GET_PNP_ID: + cam->params.pnp_id.vendor = (cmd.buffer.block_data[0] << 8) | + cmd.buffer.block_data[1]; + cam->params.pnp_id.product = (cmd.buffer.block_data[2] << 8) | + cmd.buffer.block_data[3]; + cam->params.pnp_id.device_revision = + (cmd.buffer.block_data[4] << 8) | + cmd.buffer.block_data[5]; + if (cam->params.pnp_id.vendor == 0x553) { + if (cam->params.pnp_id.product == 0x100) { + cam->params.pnp_id.device_type = DEVICE_STV_672; + } else if (cam->params.pnp_id.product == 0x140 || + cam->params.pnp_id.product == 0x151) { + cam->params.pnp_id.device_type = DEVICE_STV_676; + } + } + break; + case CPIA2_CMD_GET_ASIC_TYPE: + cam->params.version.asic_id = cmd.buffer.block_data[0]; + cam->params.version.asic_rev = cmd.buffer.block_data[1]; + break; + case CPIA2_CMD_GET_SENSOR: + cam->params.version.sensor_flags = cmd.buffer.block_data[0]; + cam->params.version.sensor_rev = cmd.buffer.block_data[1]; + break; + case CPIA2_CMD_GET_VP_DEVICE: + cam->params.version.vp_device_hi = cmd.buffer.block_data[0]; + cam->params.version.vp_device_lo = cmd.buffer.block_data[1]; + break; + case CPIA2_CMD_GET_VP_GPIO_DATA: + cam->params.vp_params.gpio_data = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_VP_GPIO_DIRECTION: + cam->params.vp_params.gpio_direction = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_VC_MP_GPIO_DIRECTION: + cam->params.vc_params.vc_mp_direction =cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_VC_MP_GPIO_DATA: + cam->params.vc_params.vc_mp_data = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_FLICKER_MODES: + cam->params.flicker_control.cam_register = + cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_WAKEUP: + cam->params.vc_params.wakeup = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_PW_CONTROL: + cam->params.vc_params.pw_control = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_SYSTEM_CTRL: + cam->params.camera_state.system_ctrl = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_VP_SYSTEM_STATE: + cam->params.vp_params.system_state = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_VP_SYSTEM_CTRL: + cam->params.vp_params.system_ctrl = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_VP_EXP_MODES: + cam->params.vp_params.exposure_modes = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_DEVICE_CONFIG: + cam->params.vp_params.device_config = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_VC_CONTROL: + cam->params.vc_params.vc_control = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_USER_MODE: + cam->params.vp_params.video_mode = cmd.buffer.block_data[0]; + break; + case CPIA2_CMD_GET_USER_EFFECTS: + cam->params.vp_params.user_effects = cmd.buffer.block_data[0]; + break; + default: + break; + } + return retval; +} + +/****************************************************************************** + * + * cpia2_send_command + * + *****************************************************************************/ + +#define DIR(cmd) ((cmd->direction == TRANSFER_WRITE) ? "Write" : "Read") +#define BINDEX(cmd) (cmd->req_mode & 0x03) + +int cpia2_send_command(struct camera_data *cam, struct cpia2_command *cmd) +{ + u8 count; + u8 start; + u8 *buffer; + int retval; + + switch (cmd->req_mode & 0x0c) { + case CAMERAACCESS_TYPE_RANDOM: + count = cmd->reg_count * sizeof(struct cpia2_register); + start = 0; + buffer = (u8 *) & cmd->buffer; + if (debugs_on & DEBUG_REG) + DBG("%s Random: Register block %s\n", DIR(cmd), + block_name[BINDEX(cmd)]); + break; + case CAMERAACCESS_TYPE_BLOCK: + count = cmd->reg_count; + start = cmd->start; + buffer = cmd->buffer.block_data; + if (debugs_on & DEBUG_REG) + DBG("%s Block: Register block %s\n", DIR(cmd), + block_name[BINDEX(cmd)]); + break; + case CAMERAACCESS_TYPE_MASK: + count = cmd->reg_count * sizeof(struct cpia2_reg_mask); + start = 0; + buffer = (u8 *) & cmd->buffer; + if (debugs_on & DEBUG_REG) + DBG("%s Mask: Register block %s\n", DIR(cmd), + block_name[BINDEX(cmd)]); + break; + case CAMERAACCESS_TYPE_REPEAT: /* For patch blocks only */ + count = cmd->reg_count; + start = cmd->start; + buffer = cmd->buffer.block_data; + if (debugs_on & DEBUG_REG) + DBG("%s Repeat: Register block %s\n", DIR(cmd), + block_name[BINDEX(cmd)]); + break; + default: + LOG("%s: invalid request mode\n",__func__); + return -EINVAL; + } + + retval = cpia2_usb_transfer_cmd(cam, + buffer, + cmd->req_mode, + start, count, cmd->direction); +#ifdef _CPIA2_DEBUG_ + if (debugs_on & DEBUG_REG) { + int i; + for (i = 0; i < cmd->reg_count; i++) { + if((cmd->req_mode & 0x0c) == CAMERAACCESS_TYPE_BLOCK) + KINFO("%s Block: [0x%02X] = 0x%02X\n", + DIR(cmd), start + i, buffer[i]); + if((cmd->req_mode & 0x0c) == CAMERAACCESS_TYPE_RANDOM) + KINFO("%s Random: [0x%02X] = 0x%02X\n", + DIR(cmd), cmd->buffer.registers[i].index, + cmd->buffer.registers[i].value); + } + } +#endif + + return retval; +}; + +/************* + * Functions to implement camera functionality + *************/ +/****************************************************************************** + * + * cpia2_get_version_info + * + *****************************************************************************/ +static void cpia2_get_version_info(struct camera_data *cam) +{ + cpia2_do_command(cam, CPIA2_CMD_GET_VERSION, TRANSFER_READ, 0); + cpia2_do_command(cam, CPIA2_CMD_GET_PNP_ID, TRANSFER_READ, 0); + cpia2_do_command(cam, CPIA2_CMD_GET_ASIC_TYPE, TRANSFER_READ, 0); + cpia2_do_command(cam, CPIA2_CMD_GET_SENSOR, TRANSFER_READ, 0); + cpia2_do_command(cam, CPIA2_CMD_GET_VP_DEVICE, TRANSFER_READ, 0); +} + +/****************************************************************************** + * + * cpia2_reset_camera + * + * Called at least during the open process, sets up initial params. + *****************************************************************************/ +int cpia2_reset_camera(struct camera_data *cam) +{ + u8 tmp_reg; + int retval = 0; + int target_kb; + int i; + struct cpia2_command cmd; + + /*** + * VC setup + ***/ + retval = configure_sensor(cam, + cam->params.roi.width, + cam->params.roi.height); + if (retval < 0) { + ERR("Couldn't configure sensor, error=%d\n", retval); + return retval; + } + + /* Clear FIFO and route/enable stream block */ + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VC; + cmd.direction = TRANSFER_WRITE; + cmd.reg_count = 2; + cmd.buffer.registers[0].index = CPIA2_VC_ST_CTRL; + cmd.buffer.registers[0].value = CPIA2_VC_ST_CTRL_SRC_VC | + CPIA2_VC_ST_CTRL_DST_USB | CPIA2_VC_ST_CTRL_EOF_DETECT; + cmd.buffer.registers[1].index = CPIA2_VC_ST_CTRL; + cmd.buffer.registers[1].value = CPIA2_VC_ST_CTRL_SRC_VC | + CPIA2_VC_ST_CTRL_DST_USB | + CPIA2_VC_ST_CTRL_EOF_DETECT | CPIA2_VC_ST_CTRL_FIFO_ENABLE; + + cpia2_send_command(cam, &cmd); + + cpia2_set_high_power(cam); + + if (cam->params.pnp_id.device_type == DEVICE_STV_672) { + /* Enable button notification */ + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_SYSTEM; + cmd.buffer.registers[0].index = CPIA2_SYSTEM_INT_PACKET_CTRL; + cmd.buffer.registers[0].value = + CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_SW_XX; + cmd.reg_count = 1; + cpia2_send_command(cam, &cmd); + } + + schedule_timeout_interruptible(msecs_to_jiffies(100)); + + if (cam->params.pnp_id.device_type == DEVICE_STV_672) + retval = apply_vp_patch(cam); + + /* wait for vp to go to sleep */ + schedule_timeout_interruptible(msecs_to_jiffies(100)); + + /*** + * If this is a 676, apply VP5 fixes before we start streaming + ***/ + if (cam->params.pnp_id.device_type == DEVICE_STV_676) { + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VP; + + /* The following writes improve the picture */ + cmd.buffer.registers[0].index = CPIA2_VP5_MYBLACK_LEVEL; + cmd.buffer.registers[0].value = 0; /* reduce from the default + * rec 601 pedestal of 16 */ + cmd.buffer.registers[1].index = CPIA2_VP5_MCYRANGE; + cmd.buffer.registers[1].value = 0x92; /* increase from 100% to + * (256/256 - 31) to fill + * available range */ + cmd.buffer.registers[2].index = CPIA2_VP5_MYCEILING; + cmd.buffer.registers[2].value = 0xFF; /* Increase from the + * default rec 601 ceiling + * of 240 */ + cmd.buffer.registers[3].index = CPIA2_VP5_MCUVSATURATION; + cmd.buffer.registers[3].value = 0xFF; /* Increase from the rec + * 601 100% level (128) + * to 145-192 */ + cmd.buffer.registers[4].index = CPIA2_VP5_ANTIFLKRSETUP; + cmd.buffer.registers[4].value = 0x80; /* Inhibit the + * anti-flicker */ + + /* The following 4 writes are a fix to allow QVGA to work at 30 fps */ + cmd.buffer.registers[5].index = CPIA2_VP_RAM_ADDR_H; + cmd.buffer.registers[5].value = 0x01; + cmd.buffer.registers[6].index = CPIA2_VP_RAM_ADDR_L; + cmd.buffer.registers[6].value = 0xE3; + cmd.buffer.registers[7].index = CPIA2_VP_RAM_DATA; + cmd.buffer.registers[7].value = 0x02; + cmd.buffer.registers[8].index = CPIA2_VP_RAM_DATA; + cmd.buffer.registers[8].value = 0xFC; + + cmd.direction = TRANSFER_WRITE; + cmd.reg_count = 9; + + cpia2_send_command(cam, &cmd); + } + + /* Activate all settings and start the data stream */ + /* Set user mode */ + set_default_user_mode(cam); + + /* Give VP time to wake up */ + schedule_timeout_interruptible(msecs_to_jiffies(100)); + + set_all_properties(cam); + + cpia2_do_command(cam, CPIA2_CMD_GET_USER_MODE, TRANSFER_READ, 0); + DBG("After SetAllProperties(cam), user mode is 0x%0X\n", + cam->params.vp_params.video_mode); + + /*** + * Set audio regulator off. This and the code to set the compresison + * state are too complex to form a CPIA2_CMD_, and seem to be somewhat + * intertwined. This stuff came straight from the windows driver. + ***/ + /* Turn AutoExposure off in VP and enable the serial bridge to the sensor */ + cpia2_do_command(cam, CPIA2_CMD_GET_VP_SYSTEM_CTRL, TRANSFER_READ, 0); + tmp_reg = cam->params.vp_params.system_ctrl; + cmd.buffer.registers[0].value = tmp_reg & + (tmp_reg & (CPIA2_VP_SYSTEMCTRL_HK_CONTROL ^ 0xFF)); + + cpia2_do_command(cam, CPIA2_CMD_GET_DEVICE_CONFIG, TRANSFER_READ, 0); + cmd.buffer.registers[1].value = cam->params.vp_params.device_config | + CPIA2_VP_DEVICE_CONFIG_SERIAL_BRIDGE; + cmd.buffer.registers[0].index = CPIA2_VP_SYSTEMCTRL; + cmd.buffer.registers[1].index = CPIA2_VP_DEVICE_CONFIG; + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VP; + cmd.reg_count = 2; + cmd.direction = TRANSFER_WRITE; + cmd.start = 0; + cpia2_send_command(cam, &cmd); + + /* Set the correct I2C address in the CPiA-2 system register */ + cpia2_do_command(cam, + CPIA2_CMD_SET_SERIAL_ADDR, + TRANSFER_WRITE, + CPIA2_SYSTEM_VP_SERIAL_ADDR_SENSOR); + + /* Now have sensor access - set bit to turn the audio regulator off */ + cpia2_do_command(cam, + CPIA2_CMD_SET_SENSOR_CR1, + TRANSFER_WRITE, CPIA2_SENSOR_CR1_DOWN_AUDIO_REGULATOR); + + /* Set the correct I2C address in the CPiA-2 system register */ + if (cam->params.pnp_id.device_type == DEVICE_STV_672) + cpia2_do_command(cam, + CPIA2_CMD_SET_SERIAL_ADDR, + TRANSFER_WRITE, + CPIA2_SYSTEM_VP_SERIAL_ADDR_VP); // 0x88 + else + cpia2_do_command(cam, + CPIA2_CMD_SET_SERIAL_ADDR, + TRANSFER_WRITE, + CPIA2_SYSTEM_VP_SERIAL_ADDR_676_VP); // 0x8a + + /* increase signal drive strength */ + if (cam->params.pnp_id.device_type == DEVICE_STV_676) + cpia2_do_command(cam, + CPIA2_CMD_SET_VP_EXP_MODES, + TRANSFER_WRITE, + CPIA2_VP_EXPOSURE_MODES_COMPILE_EXP); + + /* Start autoexposure */ + cpia2_do_command(cam, CPIA2_CMD_GET_DEVICE_CONFIG, TRANSFER_READ, 0); + cmd.buffer.registers[0].value = cam->params.vp_params.device_config & + (CPIA2_VP_DEVICE_CONFIG_SERIAL_BRIDGE ^ 0xFF); + + cpia2_do_command(cam, CPIA2_CMD_GET_VP_SYSTEM_CTRL, TRANSFER_READ, 0); + cmd.buffer.registers[1].value = + cam->params.vp_params.system_ctrl | CPIA2_VP_SYSTEMCTRL_HK_CONTROL; + + cmd.buffer.registers[0].index = CPIA2_VP_DEVICE_CONFIG; + cmd.buffer.registers[1].index = CPIA2_VP_SYSTEMCTRL; + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VP; + cmd.reg_count = 2; + cmd.direction = TRANSFER_WRITE; + + cpia2_send_command(cam, &cmd); + + /* Set compression state */ + cpia2_do_command(cam, CPIA2_CMD_GET_VC_CONTROL, TRANSFER_READ, 0); + if (cam->params.compression.inhibit_htables) { + tmp_reg = cam->params.vc_params.vc_control | + CPIA2_VC_VC_CTRL_INHIBIT_H_TABLES; + } else { + tmp_reg = cam->params.vc_params.vc_control & + ~CPIA2_VC_VC_CTRL_INHIBIT_H_TABLES; + } + cpia2_do_command(cam, CPIA2_CMD_SET_VC_CONTROL, TRANSFER_WRITE,tmp_reg); + + /* Set target size (kb) on vc + This is a heuristic based on the quality parameter and the raw + framesize in kB divided by 16 (the compression factor when the + quality is 100%) */ + target_kb = (cam->width * cam->height * 2 / 16384) * + cam->params.vc_params.quality / 100; + if (target_kb < 1) + target_kb = 1; + cpia2_do_command(cam, CPIA2_CMD_SET_TARGET_KB, + TRANSFER_WRITE, target_kb); + + /* Wiggle VC Reset */ + /*** + * First read and wait a bit. + ***/ + for (i = 0; i < 50; i++) { + cpia2_do_command(cam, CPIA2_CMD_GET_PW_CONTROL, + TRANSFER_READ, 0); + } + + tmp_reg = cam->params.vc_params.pw_control; + tmp_reg &= ~CPIA2_VC_PW_CTRL_VC_RESET_N; + + cpia2_do_command(cam, CPIA2_CMD_SET_PW_CONTROL, TRANSFER_WRITE,tmp_reg); + + tmp_reg |= CPIA2_VC_PW_CTRL_VC_RESET_N; + cpia2_do_command(cam, CPIA2_CMD_SET_PW_CONTROL, TRANSFER_WRITE,tmp_reg); + + cpia2_do_command(cam, CPIA2_CMD_SET_DEF_JPEG_OPT, TRANSFER_WRITE, 0); + + cpia2_do_command(cam, CPIA2_CMD_GET_USER_MODE, TRANSFER_READ, 0); + DBG("After VC RESET, user mode is 0x%0X\n", + cam->params.vp_params.video_mode); + + return retval; +} + +/****************************************************************************** + * + * cpia2_set_high_power + * + *****************************************************************************/ +static int cpia2_set_high_power(struct camera_data *cam) +{ + int i; + for (i = 0; i <= 50; i++) { + /* Read system status */ + cpia2_do_command(cam,CPIA2_CMD_GET_SYSTEM_CTRL,TRANSFER_READ,0); + + /* If there is an error, clear it */ + if(cam->params.camera_state.system_ctrl & + CPIA2_SYSTEM_CONTROL_V2W_ERR) + cpia2_do_command(cam, CPIA2_CMD_CLEAR_V2W_ERR, + TRANSFER_WRITE, 0); + + /* Try to set high power mode */ + cpia2_do_command(cam, CPIA2_CMD_SET_SYSTEM_CTRL, + TRANSFER_WRITE, 1); + + /* Try to read something in VP to check if everything is awake */ + cpia2_do_command(cam, CPIA2_CMD_GET_VP_SYSTEM_STATE, + TRANSFER_READ, 0); + if (cam->params.vp_params.system_state & + CPIA2_VP_SYSTEMSTATE_HK_ALIVE) { + break; + } else if (i == 50) { + cam->params.camera_state.power_mode = LO_POWER_MODE; + ERR("Camera did not wake up\n"); + return -EIO; + } + } + + DBG("System now in high power state\n"); + cam->params.camera_state.power_mode = HI_POWER_MODE; + return 0; +} + +/****************************************************************************** + * + * cpia2_set_low_power + * + *****************************************************************************/ +int cpia2_set_low_power(struct camera_data *cam) +{ + cam->params.camera_state.power_mode = LO_POWER_MODE; + cpia2_do_command(cam, CPIA2_CMD_SET_SYSTEM_CTRL, TRANSFER_WRITE, 0); + return 0; +} + +/****************************************************************************** + * + * apply_vp_patch + * + *****************************************************************************/ +static int cpia2_send_onebyte_command(struct camera_data *cam, + struct cpia2_command *cmd, + u8 start, u8 datum) +{ + cmd->buffer.block_data[0] = datum; + cmd->start = start; + cmd->reg_count = 1; + return cpia2_send_command(cam, cmd); +} + +static int apply_vp_patch(struct camera_data *cam) +{ + const struct firmware *fw; + const char fw_name[] = FIRMWARE; + int i, ret; + struct cpia2_command cmd; + + ret = request_firmware(&fw, fw_name, &cam->dev->dev); + if (ret) { + printk(KERN_ERR "cpia2: failed to load VP patch \"%s\"\n", + fw_name); + return ret; + } + + cmd.req_mode = CAMERAACCESS_TYPE_REPEAT | CAMERAACCESS_VP; + cmd.direction = TRANSFER_WRITE; + + /* First send the start address... */ + cpia2_send_onebyte_command(cam, &cmd, 0x0A, fw->data[0]); /* hi */ + cpia2_send_onebyte_command(cam, &cmd, 0x0B, fw->data[1]); /* lo */ + + /* ... followed by the data payload */ + for (i = 2; i < fw->size; i += 64) { + cmd.start = 0x0C; /* Data */ + cmd.reg_count = min_t(uint, 64, fw->size - i); + memcpy(cmd.buffer.block_data, &fw->data[i], cmd.reg_count); + cpia2_send_command(cam, &cmd); + } + + /* Next send the start address... */ + cpia2_send_onebyte_command(cam, &cmd, 0x0A, fw->data[0]); /* hi */ + cpia2_send_onebyte_command(cam, &cmd, 0x0B, fw->data[1]); /* lo */ + + /* ... followed by the 'goto' command */ + cpia2_send_onebyte_command(cam, &cmd, 0x0D, 1); + + release_firmware(fw); + return 0; +} + +/****************************************************************************** + * + * set_default_user_mode + * + *****************************************************************************/ +static int set_default_user_mode(struct camera_data *cam) +{ + unsigned char user_mode; + unsigned char frame_rate; + int width = cam->params.roi.width; + int height = cam->params.roi.height; + + switch (cam->params.version.sensor_flags) { + case CPIA2_VP_SENSOR_FLAGS_404: + case CPIA2_VP_SENSOR_FLAGS_407: + case CPIA2_VP_SENSOR_FLAGS_409: + case CPIA2_VP_SENSOR_FLAGS_410: + if ((width > STV_IMAGE_QCIF_COLS) + || (height > STV_IMAGE_QCIF_ROWS)) { + user_mode = CPIA2_VP_USER_MODE_CIF; + } else { + user_mode = CPIA2_VP_USER_MODE_QCIFDS; + } + frame_rate = CPIA2_VP_FRAMERATE_30; + break; + case CPIA2_VP_SENSOR_FLAGS_500: + if ((width > STV_IMAGE_CIF_COLS) + || (height > STV_IMAGE_CIF_ROWS)) { + user_mode = CPIA2_VP_USER_MODE_VGA; + } else { + user_mode = CPIA2_VP_USER_MODE_QVGADS; + } + if (cam->params.pnp_id.device_type == DEVICE_STV_672) + frame_rate = CPIA2_VP_FRAMERATE_15; + else + frame_rate = CPIA2_VP_FRAMERATE_30; + break; + default: + LOG("%s: Invalid sensor flag value 0x%0X\n",__func__, + cam->params.version.sensor_flags); + return -EINVAL; + } + + DBG("Sensor flag = 0x%0x, user mode = 0x%0x, frame rate = 0x%X\n", + cam->params.version.sensor_flags, user_mode, frame_rate); + cpia2_do_command(cam, CPIA2_CMD_SET_USER_MODE, TRANSFER_WRITE, + user_mode); + if(cam->params.vp_params.frame_rate > 0 && + frame_rate > cam->params.vp_params.frame_rate) + frame_rate = cam->params.vp_params.frame_rate; + + cpia2_set_fps(cam, frame_rate); + +// if (cam->params.pnp_id.device_type == DEVICE_STV_676) +// cpia2_do_command(cam, +// CPIA2_CMD_SET_VP_SYSTEM_CTRL, +// TRANSFER_WRITE, +// CPIA2_VP_SYSTEMCTRL_HK_CONTROL | +// CPIA2_VP_SYSTEMCTRL_POWER_CONTROL); + + return 0; +} + +/****************************************************************************** + * + * cpia2_match_video_size + * + * return the best match, where 'best' is as always + * the largest that is not bigger than what is requested. + *****************************************************************************/ +int cpia2_match_video_size(int width, int height) +{ + if (width >= STV_IMAGE_VGA_COLS && height >= STV_IMAGE_VGA_ROWS) + return VIDEOSIZE_VGA; + + if (width >= STV_IMAGE_CIF_COLS && height >= STV_IMAGE_CIF_ROWS) + return VIDEOSIZE_CIF; + + if (width >= STV_IMAGE_QVGA_COLS && height >= STV_IMAGE_QVGA_ROWS) + return VIDEOSIZE_QVGA; + + if (width >= 288 && height >= 216) + return VIDEOSIZE_288_216; + + if (width >= 256 && height >= 192) + return VIDEOSIZE_256_192; + + if (width >= 224 && height >= 168) + return VIDEOSIZE_224_168; + + if (width >= 192 && height >= 144) + return VIDEOSIZE_192_144; + + if (width >= STV_IMAGE_QCIF_COLS && height >= STV_IMAGE_QCIF_ROWS) + return VIDEOSIZE_QCIF; + + return -1; +} + +/****************************************************************************** + * + * SetVideoSize + * + *****************************************************************************/ +static int set_vw_size(struct camera_data *cam, int size) +{ + int retval = 0; + + cam->params.vp_params.video_size = size; + + switch (size) { + case VIDEOSIZE_VGA: + DBG("Setting size to VGA\n"); + cam->params.roi.width = STV_IMAGE_VGA_COLS; + cam->params.roi.height = STV_IMAGE_VGA_ROWS; + cam->width = STV_IMAGE_VGA_COLS; + cam->height = STV_IMAGE_VGA_ROWS; + break; + case VIDEOSIZE_CIF: + DBG("Setting size to CIF\n"); + cam->params.roi.width = STV_IMAGE_CIF_COLS; + cam->params.roi.height = STV_IMAGE_CIF_ROWS; + cam->width = STV_IMAGE_CIF_COLS; + cam->height = STV_IMAGE_CIF_ROWS; + break; + case VIDEOSIZE_QVGA: + DBG("Setting size to QVGA\n"); + cam->params.roi.width = STV_IMAGE_QVGA_COLS; + cam->params.roi.height = STV_IMAGE_QVGA_ROWS; + cam->width = STV_IMAGE_QVGA_COLS; + cam->height = STV_IMAGE_QVGA_ROWS; + break; + case VIDEOSIZE_288_216: + cam->params.roi.width = 288; + cam->params.roi.height = 216; + cam->width = 288; + cam->height = 216; + break; + case VIDEOSIZE_256_192: + cam->width = 256; + cam->height = 192; + cam->params.roi.width = 256; + cam->params.roi.height = 192; + break; + case VIDEOSIZE_224_168: + cam->width = 224; + cam->height = 168; + cam->params.roi.width = 224; + cam->params.roi.height = 168; + break; + case VIDEOSIZE_192_144: + cam->width = 192; + cam->height = 144; + cam->params.roi.width = 192; + cam->params.roi.height = 144; + break; + case VIDEOSIZE_QCIF: + DBG("Setting size to QCIF\n"); + cam->params.roi.width = STV_IMAGE_QCIF_COLS; + cam->params.roi.height = STV_IMAGE_QCIF_ROWS; + cam->width = STV_IMAGE_QCIF_COLS; + cam->height = STV_IMAGE_QCIF_ROWS; + break; + default: + retval = -EINVAL; + } + return retval; +} + +/****************************************************************************** + * + * configure_sensor + * + *****************************************************************************/ +static int configure_sensor(struct camera_data *cam, + int req_width, int req_height) +{ + int retval; + + switch (cam->params.version.sensor_flags) { + case CPIA2_VP_SENSOR_FLAGS_404: + case CPIA2_VP_SENSOR_FLAGS_407: + case CPIA2_VP_SENSOR_FLAGS_409: + case CPIA2_VP_SENSOR_FLAGS_410: + retval = config_sensor_410(cam, req_width, req_height); + break; + case CPIA2_VP_SENSOR_FLAGS_500: + retval = config_sensor_500(cam, req_width, req_height); + break; + default: + return -EINVAL; + } + + return retval; +} + +/****************************************************************************** + * + * config_sensor_410 + * + *****************************************************************************/ +static int config_sensor_410(struct camera_data *cam, + int req_width, int req_height) +{ + struct cpia2_command cmd; + int i = 0; + int image_size; + int image_type; + int width = req_width; + int height = req_height; + + /*** + * Make sure size doesn't exceed CIF. + ***/ + if (width > STV_IMAGE_CIF_COLS) + width = STV_IMAGE_CIF_COLS; + if (height > STV_IMAGE_CIF_ROWS) + height = STV_IMAGE_CIF_ROWS; + + image_size = cpia2_match_video_size(width, height); + + DBG("Config 410: width = %d, height = %d\n", width, height); + DBG("Image size returned is %d\n", image_size); + if (image_size >= 0) { + set_vw_size(cam, image_size); + width = cam->params.roi.width; + height = cam->params.roi.height; + + DBG("After set_vw_size(), width = %d, height = %d\n", + width, height); + if (width <= 176 && height <= 144) { + DBG("image type = VIDEOSIZE_QCIF\n"); + image_type = VIDEOSIZE_QCIF; + } + else if (width <= 320 && height <= 240) { + DBG("image type = VIDEOSIZE_QVGA\n"); + image_type = VIDEOSIZE_QVGA; + } + else { + DBG("image type = VIDEOSIZE_CIF\n"); + image_type = VIDEOSIZE_CIF; + } + } else { + ERR("ConfigSensor410 failed\n"); + return -EINVAL; + } + + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VC; + cmd.direction = TRANSFER_WRITE; + + /* VC Format */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_FORMAT; + if (image_type == VIDEOSIZE_CIF) { + cmd.buffer.registers[i++].value = + (u8) (CPIA2_VC_VC_FORMAT_UFIRST | + CPIA2_VC_VC_FORMAT_SHORTLINE); + } else { + cmd.buffer.registers[i++].value = + (u8) CPIA2_VC_VC_FORMAT_UFIRST; + } + + /* VC Clocks */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_CLOCKS; + if (image_type == VIDEOSIZE_QCIF) { + if (cam->params.pnp_id.device_type == DEVICE_STV_672) { + cmd.buffer.registers[i++].value= + (u8)(CPIA2_VC_VC_672_CLOCKS_CIF_DIV_BY_3 | + CPIA2_VC_VC_672_CLOCKS_SCALING | + CPIA2_VC_VC_CLOCKS_LOGDIV2); + DBG("VC_Clocks (0xc4) should be B\n"); + } + else { + cmd.buffer.registers[i++].value= + (u8)(CPIA2_VC_VC_676_CLOCKS_CIF_DIV_BY_3 | + CPIA2_VC_VC_CLOCKS_LOGDIV2); + } + } else { + if (cam->params.pnp_id.device_type == DEVICE_STV_672) { + cmd.buffer.registers[i++].value = + (u8) (CPIA2_VC_VC_672_CLOCKS_CIF_DIV_BY_3 | + CPIA2_VC_VC_CLOCKS_LOGDIV0); + } + else { + cmd.buffer.registers[i++].value = + (u8) (CPIA2_VC_VC_676_CLOCKS_CIF_DIV_BY_3 | + CPIA2_VC_VC_676_CLOCKS_SCALING | + CPIA2_VC_VC_CLOCKS_LOGDIV0); + } + } + DBG("VC_Clocks (0xc4) = 0x%0X\n", cmd.buffer.registers[i-1].value); + + /* Input reqWidth from VC */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_IHSIZE_LO; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = + (u8) (STV_IMAGE_QCIF_COLS / 4); + else + cmd.buffer.registers[i++].value = + (u8) (STV_IMAGE_CIF_COLS / 4); + + /* Timings */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_XLIM_HI; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 0; + else + cmd.buffer.registers[i++].value = (u8) 1; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_XLIM_LO; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 208; + else + cmd.buffer.registers[i++].value = (u8) 160; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_YLIM_HI; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 0; + else + cmd.buffer.registers[i++].value = (u8) 1; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_YLIM_LO; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 160; + else + cmd.buffer.registers[i++].value = (u8) 64; + + /* Output Image Size */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_OHSIZE; + cmd.buffer.registers[i++].value = cam->params.roi.width / 4; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_OVSIZE; + cmd.buffer.registers[i++].value = cam->params.roi.height / 4; + + /* Cropping */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_HCROP; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_QCIF_COLS / 4) - (width / 4)) / 2); + else + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_CIF_COLS / 4) - (width / 4)) / 2); + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VCROP; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_QCIF_ROWS / 4) - (height / 4)) / 2); + else + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_CIF_ROWS / 4) - (height / 4)) / 2); + + /* Scaling registers (defaults) */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_HPHASE; + cmd.buffer.registers[i++].value = (u8) 0; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VPHASE; + cmd.buffer.registers[i++].value = (u8) 0; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_HISPAN; + cmd.buffer.registers[i++].value = (u8) 31; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VISPAN; + cmd.buffer.registers[i++].value = (u8) 31; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_HICROP; + cmd.buffer.registers[i++].value = (u8) 0; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VICROP; + cmd.buffer.registers[i++].value = (u8) 0; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_HFRACT; + cmd.buffer.registers[i++].value = (u8) 0x81; /* = 8/1 = 8 (HIBYTE/LOBYTE) */ + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VFRACT; + cmd.buffer.registers[i++].value = (u8) 0x81; /* = 8/1 = 8 (HIBYTE/LOBYTE) */ + + cmd.reg_count = i; + + cpia2_send_command(cam, &cmd); + + return i; +} + + +/****************************************************************************** + * + * config_sensor_500(cam) + * + *****************************************************************************/ +static int config_sensor_500(struct camera_data *cam, + int req_width, int req_height) +{ + struct cpia2_command cmd; + int i = 0; + int image_size = VIDEOSIZE_CIF; + int image_type = VIDEOSIZE_VGA; + int width = req_width; + int height = req_height; + unsigned int device = cam->params.pnp_id.device_type; + + image_size = cpia2_match_video_size(width, height); + + if (width > STV_IMAGE_CIF_COLS || height > STV_IMAGE_CIF_ROWS) + image_type = VIDEOSIZE_VGA; + else if (width > STV_IMAGE_QVGA_COLS || height > STV_IMAGE_QVGA_ROWS) + image_type = VIDEOSIZE_CIF; + else if (width > STV_IMAGE_QCIF_COLS || height > STV_IMAGE_QCIF_ROWS) + image_type = VIDEOSIZE_QVGA; + else + image_type = VIDEOSIZE_QCIF; + + if (image_size >= 0) { + set_vw_size(cam, image_size); + width = cam->params.roi.width; + height = cam->params.roi.height; + } else { + ERR("ConfigSensor500 failed\n"); + return -EINVAL; + } + + DBG("image_size = %d, width = %d, height = %d, type = %d\n", + image_size, width, height, image_type); + + cmd.req_mode = CAMERAACCESS_TYPE_RANDOM | CAMERAACCESS_VC; + cmd.direction = TRANSFER_WRITE; + i = 0; + + /* VC Format */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_FORMAT; + cmd.buffer.registers[i].value = (u8) CPIA2_VC_VC_FORMAT_UFIRST; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i].value |= (u8) CPIA2_VC_VC_FORMAT_DECIMATING; + i++; + + /* VC Clocks */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_CLOCKS; + if (device == DEVICE_STV_672) { + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i].value = + (u8)CPIA2_VC_VC_CLOCKS_LOGDIV1; + else + cmd.buffer.registers[i].value = + (u8)(CPIA2_VC_VC_672_CLOCKS_SCALING | + CPIA2_VC_VC_CLOCKS_LOGDIV3); + } else { + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i].value = + (u8)CPIA2_VC_VC_CLOCKS_LOGDIV0; + else + cmd.buffer.registers[i].value = + (u8)(CPIA2_VC_VC_676_CLOCKS_SCALING | + CPIA2_VC_VC_CLOCKS_LOGDIV2); + } + i++; + + DBG("VC_CLOCKS = 0x%X\n", cmd.buffer.registers[i-1].value); + + /* Input width from VP */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_IHSIZE_LO; + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i].value = + (u8) (STV_IMAGE_VGA_COLS / 4); + else + cmd.buffer.registers[i].value = + (u8) (STV_IMAGE_QVGA_COLS / 4); + i++; + DBG("Input width = %d\n", cmd.buffer.registers[i-1].value); + + /* Timings */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_XLIM_HI; + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i++].value = (u8) 2; + else + cmd.buffer.registers[i++].value = (u8) 1; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_XLIM_LO; + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i++].value = (u8) 250; + else if (image_type == VIDEOSIZE_QVGA) + cmd.buffer.registers[i++].value = (u8) 125; + else + cmd.buffer.registers[i++].value = (u8) 160; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_YLIM_HI; + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i++].value = (u8) 2; + else + cmd.buffer.registers[i++].value = (u8) 1; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_YLIM_LO; + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i++].value = (u8) 12; + else if (image_type == VIDEOSIZE_QVGA) + cmd.buffer.registers[i++].value = (u8) 64; + else + cmd.buffer.registers[i++].value = (u8) 6; + + /* Output Image Size */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_OHSIZE; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = STV_IMAGE_CIF_COLS / 4; + else + cmd.buffer.registers[i++].value = width / 4; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_OVSIZE; + if (image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = STV_IMAGE_CIF_ROWS / 4; + else + cmd.buffer.registers[i++].value = height / 4; + + /* Cropping */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_HCROP; + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_VGA_COLS / 4) - (width / 4)) / 2); + else if (image_type == VIDEOSIZE_QVGA) + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_QVGA_COLS / 4) - (width / 4)) / 2); + else if (image_type == VIDEOSIZE_CIF) + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_CIF_COLS / 4) - (width / 4)) / 2); + else /*if (image_type == VIDEOSIZE_QCIF)*/ + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_QCIF_COLS / 4) - (width / 4)) / 2); + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VCROP; + if (image_type == VIDEOSIZE_VGA) + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_VGA_ROWS / 4) - (height / 4)) / 2); + else if (image_type == VIDEOSIZE_QVGA) + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_QVGA_ROWS / 4) - (height / 4)) / 2); + else if (image_type == VIDEOSIZE_CIF) + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_CIF_ROWS / 4) - (height / 4)) / 2); + else /*if (image_type == VIDEOSIZE_QCIF)*/ + cmd.buffer.registers[i++].value = + (u8) (((STV_IMAGE_QCIF_ROWS / 4) - (height / 4)) / 2); + + /* Scaling registers (defaults) */ + cmd.buffer.registers[i].index = CPIA2_VC_VC_HPHASE; + if (image_type == VIDEOSIZE_CIF || image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 36; + else + cmd.buffer.registers[i++].value = (u8) 0; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VPHASE; + if (image_type == VIDEOSIZE_CIF || image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 32; + else + cmd.buffer.registers[i++].value = (u8) 0; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_HISPAN; + if (image_type == VIDEOSIZE_CIF || image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 26; + else + cmd.buffer.registers[i++].value = (u8) 31; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VISPAN; + if (image_type == VIDEOSIZE_CIF || image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 21; + else + cmd.buffer.registers[i++].value = (u8) 31; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_HICROP; + cmd.buffer.registers[i++].value = (u8) 0; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VICROP; + cmd.buffer.registers[i++].value = (u8) 0; + + cmd.buffer.registers[i].index = CPIA2_VC_VC_HFRACT; + if (image_type == VIDEOSIZE_CIF || image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 0x2B; /* 2/11 */ + else + cmd.buffer.registers[i++].value = (u8) 0x81; /* 8/1 */ + + cmd.buffer.registers[i].index = CPIA2_VC_VC_VFRACT; + if (image_type == VIDEOSIZE_CIF || image_type == VIDEOSIZE_QCIF) + cmd.buffer.registers[i++].value = (u8) 0x13; /* 1/3 */ + else + cmd.buffer.registers[i++].value = (u8) 0x81; /* 8/1 */ + + cmd.reg_count = i; + + cpia2_send_command(cam, &cmd); + + return i; +} + + +/****************************************************************************** + * + * setallproperties + * + * This sets all user changeable properties to the values in cam->params. + *****************************************************************************/ +static int set_all_properties(struct camera_data *cam) +{ + /** + * Don't set target_kb here, it will be set later. + * framerate and user_mode were already set (set_default_user_mode). + **/ + + cpia2_usb_change_streaming_alternate(cam, + cam->params.camera_state.stream_mode); + + cpia2_do_command(cam, + CPIA2_CMD_SET_VC_MP_GPIO_DIRECTION, + TRANSFER_WRITE, cam->params.vp_params.gpio_direction); + cpia2_do_command(cam, CPIA2_CMD_SET_VC_MP_GPIO_DATA, TRANSFER_WRITE, + cam->params.vp_params.gpio_data); + + v4l2_ctrl_handler_setup(&cam->hdl); + + wake_system(cam); + + set_lowlight_boost(cam); + + return 0; +} + +/****************************************************************************** + * + * cpia2_save_camera_state + * + *****************************************************************************/ +void cpia2_save_camera_state(struct camera_data *cam) +{ + cpia2_do_command(cam, CPIA2_CMD_GET_USER_EFFECTS, TRANSFER_READ, 0); + cpia2_do_command(cam, CPIA2_CMD_GET_VC_MP_GPIO_DIRECTION, TRANSFER_READ, + 0); + cpia2_do_command(cam, CPIA2_CMD_GET_VC_MP_GPIO_DATA, TRANSFER_READ, 0); + /* Don't get framerate or target_kb. Trust the values we already have */ +} + + +/****************************************************************************** + * + * cpia2_set_flicker_mode + * + *****************************************************************************/ +int cpia2_set_flicker_mode(struct camera_data *cam, int mode) +{ + unsigned char cam_reg; + int err = 0; + + if(cam->params.pnp_id.device_type != DEVICE_STV_672) + return -EINVAL; + + /* Set the appropriate bits in FLICKER_MODES, preserving the rest */ + if((err = cpia2_do_command(cam, CPIA2_CMD_GET_FLICKER_MODES, + TRANSFER_READ, 0))) + return err; + cam_reg = cam->params.flicker_control.cam_register; + + switch(mode) { + case NEVER_FLICKER: + cam_reg |= CPIA2_VP_FLICKER_MODES_NEVER_FLICKER; + cam_reg &= ~CPIA2_VP_FLICKER_MODES_50HZ; + break; + case FLICKER_60: + cam_reg &= ~CPIA2_VP_FLICKER_MODES_NEVER_FLICKER; + cam_reg &= ~CPIA2_VP_FLICKER_MODES_50HZ; + break; + case FLICKER_50: + cam_reg &= ~CPIA2_VP_FLICKER_MODES_NEVER_FLICKER; + cam_reg |= CPIA2_VP_FLICKER_MODES_50HZ; + break; + default: + return -EINVAL; + } + + if((err = cpia2_do_command(cam, CPIA2_CMD_SET_FLICKER_MODES, + TRANSFER_WRITE, cam_reg))) + return err; + + /* Set the appropriate bits in EXP_MODES, preserving the rest */ + if((err = cpia2_do_command(cam, CPIA2_CMD_GET_VP_EXP_MODES, + TRANSFER_READ, 0))) + return err; + cam_reg = cam->params.vp_params.exposure_modes; + + if (mode == NEVER_FLICKER) { + cam_reg |= CPIA2_VP_EXPOSURE_MODES_INHIBIT_FLICKER; + } else { + cam_reg &= ~CPIA2_VP_EXPOSURE_MODES_INHIBIT_FLICKER; + } + + if((err = cpia2_do_command(cam, CPIA2_CMD_SET_VP_EXP_MODES, + TRANSFER_WRITE, cam_reg))) + return err; + + if((err = cpia2_do_command(cam, CPIA2_CMD_REHASH_VP4, + TRANSFER_WRITE, 1))) + return err; + + switch(mode) { + case NEVER_FLICKER: + case FLICKER_60: + case FLICKER_50: + cam->params.flicker_control.flicker_mode_req = mode; + break; + default: + err = -EINVAL; + } + + return err; +} + +/****************************************************************************** + * + * cpia2_set_property_flip + * + *****************************************************************************/ +void cpia2_set_property_flip(struct camera_data *cam, int prop_val) +{ + unsigned char cam_reg; + + cpia2_do_command(cam, CPIA2_CMD_GET_USER_EFFECTS, TRANSFER_READ, 0); + cam_reg = cam->params.vp_params.user_effects; + + if (prop_val) + { + cam_reg |= CPIA2_VP_USER_EFFECTS_FLIP; + } + else + { + cam_reg &= ~CPIA2_VP_USER_EFFECTS_FLIP; + } + cam->params.vp_params.user_effects = cam_reg; + cpia2_do_command(cam, CPIA2_CMD_SET_USER_EFFECTS, TRANSFER_WRITE, + cam_reg); +} + +/****************************************************************************** + * + * cpia2_set_property_mirror + * + *****************************************************************************/ +void cpia2_set_property_mirror(struct camera_data *cam, int prop_val) +{ + unsigned char cam_reg; + + cpia2_do_command(cam, CPIA2_CMD_GET_USER_EFFECTS, TRANSFER_READ, 0); + cam_reg = cam->params.vp_params.user_effects; + + if (prop_val) + { + cam_reg |= CPIA2_VP_USER_EFFECTS_MIRROR; + } + else + { + cam_reg &= ~CPIA2_VP_USER_EFFECTS_MIRROR; + } + cam->params.vp_params.user_effects = cam_reg; + cpia2_do_command(cam, CPIA2_CMD_SET_USER_EFFECTS, TRANSFER_WRITE, + cam_reg); +} + +/****************************************************************************** + * + * cpia2_set_gpio + * + *****************************************************************************/ +int cpia2_set_gpio(struct camera_data *cam, unsigned char setting) +{ + int ret; + + /* Set the microport direction (register 0x90, should be defined + * already) to 1 (user output), and set the microport data (0x91) to + * the value in the ioctl argument. + */ + + ret = cpia2_do_command(cam, + CPIA2_CMD_SET_VC_MP_GPIO_DIRECTION, + CPIA2_VC_MP_DIR_OUTPUT, + 255); + if (ret < 0) + return ret; + cam->params.vp_params.gpio_direction = 255; + + ret = cpia2_do_command(cam, + CPIA2_CMD_SET_VC_MP_GPIO_DATA, + CPIA2_VC_MP_DIR_OUTPUT, + setting); + if (ret < 0) + return ret; + cam->params.vp_params.gpio_data = setting; + + return 0; +} + +/****************************************************************************** + * + * cpia2_set_fps + * + *****************************************************************************/ +int cpia2_set_fps(struct camera_data *cam, int framerate) +{ + int retval; + + switch(framerate) { + case CPIA2_VP_FRAMERATE_30: + case CPIA2_VP_FRAMERATE_25: + if(cam->params.pnp_id.device_type == DEVICE_STV_672 && + cam->params.version.sensor_flags == + CPIA2_VP_SENSOR_FLAGS_500) { + return -EINVAL; + } + fallthrough; + case CPIA2_VP_FRAMERATE_15: + case CPIA2_VP_FRAMERATE_12_5: + case CPIA2_VP_FRAMERATE_7_5: + case CPIA2_VP_FRAMERATE_6_25: + break; + default: + return -EINVAL; + } + + if (cam->params.pnp_id.device_type == DEVICE_STV_672 && + framerate == CPIA2_VP_FRAMERATE_15) + framerate = 0; /* Work around bug in VP4 */ + + retval = cpia2_do_command(cam, + CPIA2_CMD_FRAMERATE_REQ, + TRANSFER_WRITE, + framerate); + + if(retval == 0) + cam->params.vp_params.frame_rate = framerate; + + return retval; +} + +/****************************************************************************** + * + * cpia2_set_brightness + * + *****************************************************************************/ +void cpia2_set_brightness(struct camera_data *cam, unsigned char value) +{ + /*** + * Don't let the register be set to zero - bug in VP4 - flash of full + * brightness + ***/ + if (cam->params.pnp_id.device_type == DEVICE_STV_672 && value == 0) + value++; + DBG("Setting brightness to %d (0x%0x)\n", value, value); + cpia2_do_command(cam, CPIA2_CMD_SET_VP_BRIGHTNESS, TRANSFER_WRITE, value); +} + +/****************************************************************************** + * + * cpia2_set_contrast + * + *****************************************************************************/ +void cpia2_set_contrast(struct camera_data *cam, unsigned char value) +{ + DBG("Setting contrast to %d (0x%0x)\n", value, value); + cpia2_do_command(cam, CPIA2_CMD_SET_CONTRAST, TRANSFER_WRITE, value); +} + +/****************************************************************************** + * + * cpia2_set_saturation + * + *****************************************************************************/ +void cpia2_set_saturation(struct camera_data *cam, unsigned char value) +{ + DBG("Setting saturation to %d (0x%0x)\n", value, value); + cpia2_do_command(cam,CPIA2_CMD_SET_VP_SATURATION, TRANSFER_WRITE,value); +} + +/****************************************************************************** + * + * wake_system + * + *****************************************************************************/ +static void wake_system(struct camera_data *cam) +{ + cpia2_do_command(cam, CPIA2_CMD_SET_WAKEUP, TRANSFER_WRITE, 0); +} + +/****************************************************************************** + * + * set_lowlight_boost + * + * Valid for STV500 sensor only + *****************************************************************************/ +static void set_lowlight_boost(struct camera_data *cam) +{ + struct cpia2_command cmd; + + if (cam->params.pnp_id.device_type != DEVICE_STV_672 || + cam->params.version.sensor_flags != CPIA2_VP_SENSOR_FLAGS_500) + return; + + cmd.direction = TRANSFER_WRITE; + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 3; + cmd.start = CPIA2_VP_RAM_ADDR_H; + + cmd.buffer.block_data[0] = 0; /* High byte of address to write to */ + cmd.buffer.block_data[1] = 0x59; /* Low byte of address to write to */ + cmd.buffer.block_data[2] = 0; /* High byte of data to write */ + + cpia2_send_command(cam, &cmd); + + if (cam->params.vp_params.lowlight_boost) { + cmd.buffer.block_data[0] = 0x02; /* Low byte data to write */ + } else { + cmd.buffer.block_data[0] = 0x06; + } + cmd.start = CPIA2_VP_RAM_DATA; + cmd.reg_count = 1; + cpia2_send_command(cam, &cmd); + + /* Rehash the VP4 values */ + cpia2_do_command(cam, CPIA2_CMD_REHASH_VP4, TRANSFER_WRITE, 1); +} + +/****************************************************************************** + * + * cpia2_set_format + * + * Assumes that new size is already set in param struct. + *****************************************************************************/ +void cpia2_set_format(struct camera_data *cam) +{ + cam->flush = true; + + cpia2_usb_stream_pause(cam); + + /* reset camera to new size */ + cpia2_set_low_power(cam); + cpia2_reset_camera(cam); + cam->flush = false; + + cpia2_dbg_dump_registers(cam); + + cpia2_usb_stream_resume(cam); +} + +/****************************************************************************** + * + * cpia2_dbg_dump_registers + * + *****************************************************************************/ +void cpia2_dbg_dump_registers(struct camera_data *cam) +{ +#ifdef _CPIA2_DEBUG_ + struct cpia2_command cmd; + + if (!(debugs_on & DEBUG_DUMP_REGS)) + return; + + cmd.direction = TRANSFER_READ; + + /* Start with bank 0 (SYSTEM) */ + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_SYSTEM; + cmd.reg_count = 3; + cmd.start = 0; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "System Device Hi = 0x%X\n", + cmd.buffer.block_data[0]); + printk(KERN_DEBUG "System Device Lo = 0x%X\n", + cmd.buffer.block_data[1]); + printk(KERN_DEBUG "System_system control = 0x%X\n", + cmd.buffer.block_data[2]); + + /* Bank 1 (VC) */ + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.reg_count = 4; + cmd.start = 0x80; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "ASIC_ID = 0x%X\n", + cmd.buffer.block_data[0]); + printk(KERN_DEBUG "ASIC_REV = 0x%X\n", + cmd.buffer.block_data[1]); + printk(KERN_DEBUG "PW_CONTRL = 0x%X\n", + cmd.buffer.block_data[2]); + printk(KERN_DEBUG "WAKEUP = 0x%X\n", + cmd.buffer.block_data[3]); + + cmd.start = 0xA0; /* ST_CTRL */ + cmd.reg_count = 1; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "Stream ctrl = 0x%X\n", + cmd.buffer.block_data[0]); + + cmd.start = 0xA4; /* Stream status */ + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "Stream status = 0x%X\n", + cmd.buffer.block_data[0]); + + cmd.start = 0xA8; /* USB status */ + cmd.reg_count = 3; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "USB_CTRL = 0x%X\n", + cmd.buffer.block_data[0]); + printk(KERN_DEBUG "USB_STRM = 0x%X\n", + cmd.buffer.block_data[1]); + printk(KERN_DEBUG "USB_STATUS = 0x%X\n", + cmd.buffer.block_data[2]); + + cmd.start = 0xAF; /* USB settings */ + cmd.reg_count = 1; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "USB settings = 0x%X\n", + cmd.buffer.block_data[0]); + + cmd.start = 0xC0; /* VC stuff */ + cmd.reg_count = 26; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "VC Control = 0x%0X\n", + cmd.buffer.block_data[0]); + printk(KERN_DEBUG "VC Format = 0x%0X\n", + cmd.buffer.block_data[3]); + printk(KERN_DEBUG "VC Clocks = 0x%0X\n", + cmd.buffer.block_data[4]); + printk(KERN_DEBUG "VC IHSize = 0x%0X\n", + cmd.buffer.block_data[5]); + printk(KERN_DEBUG "VC Xlim Hi = 0x%0X\n", + cmd.buffer.block_data[6]); + printk(KERN_DEBUG "VC XLim Lo = 0x%0X\n", + cmd.buffer.block_data[7]); + printk(KERN_DEBUG "VC YLim Hi = 0x%0X\n", + cmd.buffer.block_data[8]); + printk(KERN_DEBUG "VC YLim Lo = 0x%0X\n", + cmd.buffer.block_data[9]); + printk(KERN_DEBUG "VC OHSize = 0x%0X\n", + cmd.buffer.block_data[10]); + printk(KERN_DEBUG "VC OVSize = 0x%0X\n", + cmd.buffer.block_data[11]); + printk(KERN_DEBUG "VC HCrop = 0x%0X\n", + cmd.buffer.block_data[12]); + printk(KERN_DEBUG "VC VCrop = 0x%0X\n", + cmd.buffer.block_data[13]); + printk(KERN_DEBUG "VC HPhase = 0x%0X\n", + cmd.buffer.block_data[14]); + printk(KERN_DEBUG "VC VPhase = 0x%0X\n", + cmd.buffer.block_data[15]); + printk(KERN_DEBUG "VC HIspan = 0x%0X\n", + cmd.buffer.block_data[16]); + printk(KERN_DEBUG "VC VIspan = 0x%0X\n", + cmd.buffer.block_data[17]); + printk(KERN_DEBUG "VC HiCrop = 0x%0X\n", + cmd.buffer.block_data[18]); + printk(KERN_DEBUG "VC ViCrop = 0x%0X\n", + cmd.buffer.block_data[19]); + printk(KERN_DEBUG "VC HiFract = 0x%0X\n", + cmd.buffer.block_data[20]); + printk(KERN_DEBUG "VC ViFract = 0x%0X\n", + cmd.buffer.block_data[21]); + printk(KERN_DEBUG "VC JPeg Opt = 0x%0X\n", + cmd.buffer.block_data[22]); + printk(KERN_DEBUG "VC Creep Per = 0x%0X\n", + cmd.buffer.block_data[23]); + printk(KERN_DEBUG "VC User Sq. = 0x%0X\n", + cmd.buffer.block_data[24]); + printk(KERN_DEBUG "VC Target KB = 0x%0X\n", + cmd.buffer.block_data[25]); + + /*** VP ***/ + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VP; + cmd.reg_count = 14; + cmd.start = 0; + cpia2_send_command(cam, &cmd); + + printk(KERN_DEBUG "VP Dev Hi = 0x%0X\n", + cmd.buffer.block_data[0]); + printk(KERN_DEBUG "VP Dev Lo = 0x%0X\n", + cmd.buffer.block_data[1]); + printk(KERN_DEBUG "VP Sys State = 0x%0X\n", + cmd.buffer.block_data[2]); + printk(KERN_DEBUG "VP Sys Ctrl = 0x%0X\n", + cmd.buffer.block_data[3]); + printk(KERN_DEBUG "VP Sensor flg = 0x%0X\n", + cmd.buffer.block_data[5]); + printk(KERN_DEBUG "VP Sensor Rev = 0x%0X\n", + cmd.buffer.block_data[6]); + printk(KERN_DEBUG "VP Dev Config = 0x%0X\n", + cmd.buffer.block_data[7]); + printk(KERN_DEBUG "VP GPIO_DIR = 0x%0X\n", + cmd.buffer.block_data[8]); + printk(KERN_DEBUG "VP GPIO_DATA = 0x%0X\n", + cmd.buffer.block_data[9]); + printk(KERN_DEBUG "VP Ram ADDR H = 0x%0X\n", + cmd.buffer.block_data[10]); + printk(KERN_DEBUG "VP Ram ADDR L = 0x%0X\n", + cmd.buffer.block_data[11]); + printk(KERN_DEBUG "VP RAM Data = 0x%0X\n", + cmd.buffer.block_data[12]); + printk(KERN_DEBUG "Do Call = 0x%0X\n", + cmd.buffer.block_data[13]); + + if (cam->params.pnp_id.device_type == DEVICE_STV_672) { + cmd.reg_count = 9; + cmd.start = 0x0E; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "VP Clock Ctrl = 0x%0X\n", + cmd.buffer.block_data[0]); + printk(KERN_DEBUG "VP Patch Rev = 0x%0X\n", + cmd.buffer.block_data[1]); + printk(KERN_DEBUG "VP Vid Mode = 0x%0X\n", + cmd.buffer.block_data[2]); + printk(KERN_DEBUG "VP Framerate = 0x%0X\n", + cmd.buffer.block_data[3]); + printk(KERN_DEBUG "VP UserEffect = 0x%0X\n", + cmd.buffer.block_data[4]); + printk(KERN_DEBUG "VP White Bal = 0x%0X\n", + cmd.buffer.block_data[5]); + printk(KERN_DEBUG "VP WB thresh = 0x%0X\n", + cmd.buffer.block_data[6]); + printk(KERN_DEBUG "VP Exp Modes = 0x%0X\n", + cmd.buffer.block_data[7]); + printk(KERN_DEBUG "VP Exp Target = 0x%0X\n", + cmd.buffer.block_data[8]); + + cmd.reg_count = 1; + cmd.start = 0x1B; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "VP FlickerMds = 0x%0X\n", + cmd.buffer.block_data[0]); + } else { + cmd.reg_count = 8 ; + cmd.start = 0x0E; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "VP Clock Ctrl = 0x%0X\n", + cmd.buffer.block_data[0]); + printk(KERN_DEBUG "VP Patch Rev = 0x%0X\n", + cmd.buffer.block_data[1]); + printk(KERN_DEBUG "VP Vid Mode = 0x%0X\n", + cmd.buffer.block_data[5]); + printk(KERN_DEBUG "VP Framerate = 0x%0X\n", + cmd.buffer.block_data[6]); + printk(KERN_DEBUG "VP UserEffect = 0x%0X\n", + cmd.buffer.block_data[7]); + + cmd.reg_count = 1; + cmd.start = CPIA2_VP5_EXPOSURE_TARGET; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "VP5 Exp Target= 0x%0X\n", + cmd.buffer.block_data[0]); + + cmd.reg_count = 4; + cmd.start = 0x3A; + cpia2_send_command(cam, &cmd); + printk(KERN_DEBUG "VP5 MY Black = 0x%0X\n", + cmd.buffer.block_data[0]); + printk(KERN_DEBUG "VP5 MCY Range = 0x%0X\n", + cmd.buffer.block_data[1]); + printk(KERN_DEBUG "VP5 MYCEILING = 0x%0X\n", + cmd.buffer.block_data[2]); + printk(KERN_DEBUG "VP5 MCUV Sat = 0x%0X\n", + cmd.buffer.block_data[3]); + } +#endif +} + +/****************************************************************************** + * + * reset_camera_struct + * + * Sets all values to the defaults + *****************************************************************************/ +static void reset_camera_struct(struct camera_data *cam) +{ + /*** + * The following parameter values are the defaults from the register map. + ***/ + cam->params.vp_params.lowlight_boost = 0; + + /* FlickerModes */ + cam->params.flicker_control.flicker_mode_req = NEVER_FLICKER; + + /* jpeg params */ + cam->params.compression.jpeg_options = CPIA2_VC_VC_JPEG_OPT_DEFAULT; + cam->params.compression.creep_period = 2; + cam->params.compression.user_squeeze = 20; + cam->params.compression.inhibit_htables = false; + + /* gpio params */ + cam->params.vp_params.gpio_direction = 0; /* write, the default safe mode */ + cam->params.vp_params.gpio_data = 0; + + /* Target kb params */ + cam->params.vc_params.quality = 100; + + /*** + * Set Sensor FPS as fast as possible. + ***/ + if(cam->params.pnp_id.device_type == DEVICE_STV_672) { + if(cam->params.version.sensor_flags == CPIA2_VP_SENSOR_FLAGS_500) + cam->params.vp_params.frame_rate = CPIA2_VP_FRAMERATE_15; + else + cam->params.vp_params.frame_rate = CPIA2_VP_FRAMERATE_30; + } else { + cam->params.vp_params.frame_rate = CPIA2_VP_FRAMERATE_30; + } + + /*** + * Set default video mode as large as possible : + * for vga sensor set to vga, for cif sensor set to CIF. + ***/ + if (cam->params.version.sensor_flags == CPIA2_VP_SENSOR_FLAGS_500) { + cam->sensor_type = CPIA2_SENSOR_500; + cam->video_size = VIDEOSIZE_VGA; + cam->params.roi.width = STV_IMAGE_VGA_COLS; + cam->params.roi.height = STV_IMAGE_VGA_ROWS; + } else { + cam->sensor_type = CPIA2_SENSOR_410; + cam->video_size = VIDEOSIZE_CIF; + cam->params.roi.width = STV_IMAGE_CIF_COLS; + cam->params.roi.height = STV_IMAGE_CIF_ROWS; + } + + cam->width = cam->params.roi.width; + cam->height = cam->params.roi.height; +} + +/****************************************************************************** + * + * cpia2_init_camera_struct + * + * Deinitialize camera struct + *****************************************************************************/ +void cpia2_deinit_camera_struct(struct camera_data *cam, struct usb_interface *intf) +{ + v4l2_device_unregister(&cam->v4l2_dev); + kfree(cam); +} + +/****************************************************************************** + * + * cpia2_init_camera_struct + * + * Initializes camera struct, does not call reset to fill in defaults. + *****************************************************************************/ +struct camera_data *cpia2_init_camera_struct(struct usb_interface *intf) +{ + struct camera_data *cam; + + cam = kzalloc(sizeof(*cam), GFP_KERNEL); + + if (!cam) { + ERR("couldn't kmalloc cpia2 struct\n"); + return NULL; + } + + cam->v4l2_dev.release = cpia2_camera_release; + if (v4l2_device_register(&intf->dev, &cam->v4l2_dev) < 0) { + v4l2_err(&cam->v4l2_dev, "couldn't register v4l2_device\n"); + kfree(cam); + return NULL; + } + + mutex_init(&cam->v4l2_lock); + init_waitqueue_head(&cam->wq_stream); + + return cam; +} + +/****************************************************************************** + * + * cpia2_init_camera + * + * Initializes camera. + *****************************************************************************/ +int cpia2_init_camera(struct camera_data *cam) +{ + DBG("Start\n"); + + cam->mmapped = false; + + /* Get sensor and asic types before reset. */ + cpia2_set_high_power(cam); + cpia2_get_version_info(cam); + if (cam->params.version.asic_id != CPIA2_ASIC_672) { + ERR("Device IO error (asicID has incorrect value of 0x%X\n", + cam->params.version.asic_id); + return -ENODEV; + } + + /* Set GPIO direction and data to a safe state. */ + cpia2_do_command(cam, CPIA2_CMD_SET_VC_MP_GPIO_DIRECTION, + TRANSFER_WRITE, 0); + cpia2_do_command(cam, CPIA2_CMD_SET_VC_MP_GPIO_DATA, + TRANSFER_WRITE, 0); + + /* resetting struct requires version info for sensor and asic types */ + reset_camera_struct(cam); + + cpia2_set_low_power(cam); + + DBG("End\n"); + + return 0; +} + +/****************************************************************************** + * + * cpia2_allocate_buffers + * + *****************************************************************************/ +int cpia2_allocate_buffers(struct camera_data *cam) +{ + int i; + + if(!cam->buffers) { + u32 size = cam->num_frames*sizeof(struct framebuf); + cam->buffers = kmalloc(size, GFP_KERNEL); + if(!cam->buffers) { + ERR("couldn't kmalloc frame buffer structures\n"); + return -ENOMEM; + } + } + + if(!cam->frame_buffer) { + cam->frame_buffer = rvmalloc(cam->frame_size*cam->num_frames); + if (!cam->frame_buffer) { + ERR("couldn't vmalloc frame buffer data area\n"); + kfree(cam->buffers); + cam->buffers = NULL; + return -ENOMEM; + } + } + + for(i=0; inum_frames-1; ++i) { + cam->buffers[i].next = &cam->buffers[i+1]; + cam->buffers[i].data = cam->frame_buffer +i*cam->frame_size; + cam->buffers[i].status = FRAME_EMPTY; + cam->buffers[i].length = 0; + cam->buffers[i].max_length = 0; + cam->buffers[i].num = i; + } + cam->buffers[i].next = cam->buffers; + cam->buffers[i].data = cam->frame_buffer +i*cam->frame_size; + cam->buffers[i].status = FRAME_EMPTY; + cam->buffers[i].length = 0; + cam->buffers[i].max_length = 0; + cam->buffers[i].num = i; + cam->curbuff = cam->buffers; + cam->workbuff = cam->curbuff->next; + DBG("buffers=%p, curbuff=%p, workbuff=%p\n", cam->buffers, cam->curbuff, + cam->workbuff); + return 0; +} + +/****************************************************************************** + * + * cpia2_free_buffers + * + *****************************************************************************/ +void cpia2_free_buffers(struct camera_data *cam) +{ + if(cam->buffers) { + kfree(cam->buffers); + cam->buffers = NULL; + } + if(cam->frame_buffer) { + rvfree(cam->frame_buffer, cam->frame_size*cam->num_frames); + cam->frame_buffer = NULL; + } +} + +/****************************************************************************** + * + * cpia2_read + * + *****************************************************************************/ +long cpia2_read(struct camera_data *cam, + char __user *buf, unsigned long count, int noblock) +{ + struct framebuf *frame; + + if (!count) + return 0; + + if (!buf) { + ERR("%s: buffer NULL\n",__func__); + return -EINVAL; + } + + if (!cam) { + ERR("%s: Internal error, camera_data NULL!\n",__func__); + return -EINVAL; + } + + if (!cam->streaming) { + /* Start streaming */ + cpia2_usb_stream_start(cam, + cam->params.camera_state.stream_mode); + } + + /* Copy cam->curbuff in case it changes while we're processing */ + frame = cam->curbuff; + if (noblock && frame->status != FRAME_READY) { + return -EAGAIN; + } + + if (frame->status != FRAME_READY) { + mutex_unlock(&cam->v4l2_lock); + wait_event_interruptible(cam->wq_stream, + !video_is_registered(&cam->vdev) || + (frame = cam->curbuff)->status == FRAME_READY); + mutex_lock(&cam->v4l2_lock); + if (signal_pending(current)) + return -ERESTARTSYS; + if (!video_is_registered(&cam->vdev)) + return 0; + } + + /* copy data to user space */ + if (frame->length > count) + return -EFAULT; + if (copy_to_user(buf, frame->data, frame->length)) + return -EFAULT; + + count = frame->length; + + frame->status = FRAME_EMPTY; + + return count; +} + +/****************************************************************************** + * + * cpia2_poll + * + *****************************************************************************/ +__poll_t cpia2_poll(struct camera_data *cam, struct file *filp, + poll_table *wait) +{ + __poll_t status = v4l2_ctrl_poll(filp, wait); + + if ((poll_requested_events(wait) & (EPOLLIN | EPOLLRDNORM)) && + !cam->streaming) { + /* Start streaming */ + cpia2_usb_stream_start(cam, + cam->params.camera_state.stream_mode); + } + + poll_wait(filp, &cam->wq_stream, wait); + + if (cam->curbuff->status == FRAME_READY) + status |= EPOLLIN | EPOLLRDNORM; + + return status; +} + +/****************************************************************************** + * + * cpia2_remap_buffer + * + *****************************************************************************/ +int cpia2_remap_buffer(struct camera_data *cam, struct vm_area_struct *vma) +{ + const char *adr = (const char *)vma->vm_start; + unsigned long size = vma->vm_end-vma->vm_start; + unsigned long start_offset = vma->vm_pgoff << PAGE_SHIFT; + unsigned long start = (unsigned long) adr; + unsigned long page, pos; + + DBG("mmap offset:%ld size:%ld\n", start_offset, size); + + if (!video_is_registered(&cam->vdev)) + return -ENODEV; + + if (size > cam->frame_size*cam->num_frames || + (start_offset % cam->frame_size) != 0 || + (start_offset+size > cam->frame_size*cam->num_frames)) + return -EINVAL; + + pos = ((unsigned long) (cam->frame_buffer)) + start_offset; + while (size > 0) { + page = kvirt_to_pa(pos); + if (remap_pfn_range(vma, start, page >> PAGE_SHIFT, PAGE_SIZE, PAGE_SHARED)) + return -EAGAIN; + start += PAGE_SIZE; + pos += PAGE_SIZE; + if (size > PAGE_SIZE) + size -= PAGE_SIZE; + else + size = 0; + } + + cam->mmapped = true; + return 0; +} diff --git a/drivers/staging/media/deprecated/cpia2/cpia2_registers.h b/drivers/staging/media/deprecated/cpia2/cpia2_registers.h new file mode 100644 index 000000000..8c73812a1 --- /dev/null +++ b/drivers/staging/media/deprecated/cpia2/cpia2_registers.h @@ -0,0 +1,463 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/**************************************************************************** + * + * Filename: cpia2registers.h + * + * Copyright 2001, STMicrolectronics, Inc. + * + * Description: + * Definitions for the CPia2 register set + * + ****************************************************************************/ + +#ifndef CPIA2_REGISTER_HEADER +#define CPIA2_REGISTER_HEADER + +/*** + * System register set (Bank 0) + ***/ +#define CPIA2_SYSTEM_DEVICE_HI 0x00 +#define CPIA2_SYSTEM_DEVICE_LO 0x01 + +#define CPIA2_SYSTEM_SYSTEM_CONTROL 0x02 +#define CPIA2_SYSTEM_CONTROL_LOW_POWER 0x00 +#define CPIA2_SYSTEM_CONTROL_HIGH_POWER 0x01 +#define CPIA2_SYSTEM_CONTROL_SUSPEND 0x02 +#define CPIA2_SYSTEM_CONTROL_V2W_ERR 0x10 +#define CPIA2_SYSTEM_CONTROL_RB_ERR 0x10 +#define CPIA2_SYSTEM_CONTROL_CLEAR_ERR 0x80 + +#define CPIA2_SYSTEM_INT_PACKET_CTRL 0x04 +#define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_SW_XX 0x01 +#define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_EOF 0x02 +#define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_INT1 0x04 + +#define CPIA2_SYSTEM_CACHE_CTRL 0x05 +#define CPIA2_SYSTEM_CACHE_CTRL_CACHE_RESET 0x01 +#define CPIA2_SYSTEM_CACHE_CTRL_CACHE_FLUSH 0x02 + +#define CPIA2_SYSTEM_SERIAL_CTRL 0x06 +#define CPIA2_SYSTEM_SERIAL_CTRL_NULL_CMD 0x00 +#define CPIA2_SYSTEM_SERIAL_CTRL_START_CMD 0x01 +#define CPIA2_SYSTEM_SERIAL_CTRL_STOP_CMD 0x02 +#define CPIA2_SYSTEM_SERIAL_CTRL_WRITE_CMD 0x03 +#define CPIA2_SYSTEM_SERIAL_CTRL_READ_ACK_CMD 0x04 +#define CPIA2_SYSTEM_SERIAL_CTRL_READ_NACK_CMD 0x05 + +#define CPIA2_SYSTEM_SERIAL_DATA 0x07 + +#define CPIA2_SYSTEM_VP_SERIAL_ADDR 0x08 + +/*** + * I2C addresses for various devices in CPiA2 + ***/ +#define CPIA2_SYSTEM_VP_SERIAL_ADDR_SENSOR 0x20 +#define CPIA2_SYSTEM_VP_SERIAL_ADDR_VP 0x88 +#define CPIA2_SYSTEM_VP_SERIAL_ADDR_676_VP 0x8A + +#define CPIA2_SYSTEM_SPARE_REG1 0x09 +#define CPIA2_SYSTEM_SPARE_REG2 0x0A +#define CPIA2_SYSTEM_SPARE_REG3 0x0B + +#define CPIA2_SYSTEM_MC_PORT_0 0x0C +#define CPIA2_SYSTEM_MC_PORT_1 0x0D +#define CPIA2_SYSTEM_MC_PORT_2 0x0E +#define CPIA2_SYSTEM_MC_PORT_3 0x0F + +#define CPIA2_SYSTEM_STATUS_PKT 0x20 +#define CPIA2_SYSTEM_STATUS_PKT_END 0x27 + +#define CPIA2_SYSTEM_DESCRIP_VID_HI 0x30 +#define CPIA2_SYSTEM_DESCRIP_VID_LO 0x31 +#define CPIA2_SYSTEM_DESCRIP_PID_HI 0x32 +#define CPIA2_SYSTEM_DESCRIP_PID_LO 0x33 + +#define CPIA2_SYSTEM_FW_VERSION_HI 0x34 +#define CPIA2_SYSTEM_FW_VERSION_LO 0x35 + +#define CPIA2_SYSTEM_CACHE_START_INDEX 0x80 +#define CPIA2_SYSTEM_CACHE_MAX_WRITES 0x10 + +/*** + * VC register set (Bank 1) + ***/ +#define CPIA2_VC_ASIC_ID 0x80 + +#define CPIA2_VC_ASIC_REV 0x81 + +#define CPIA2_VC_PW_CTRL 0x82 +#define CPIA2_VC_PW_CTRL_COLDSTART 0x01 +#define CPIA2_VC_PW_CTRL_CP_CLK_EN 0x02 +#define CPIA2_VC_PW_CTRL_VP_RESET_N 0x04 +#define CPIA2_VC_PW_CTRL_VC_CLK_EN 0x08 +#define CPIA2_VC_PW_CTRL_VC_RESET_N 0x10 +#define CPIA2_VC_PW_CTRL_GOTO_SUSPEND 0x20 +#define CPIA2_VC_PW_CTRL_UDC_SUSPEND 0x40 +#define CPIA2_VC_PW_CTRL_PWR_DOWN 0x80 + +#define CPIA2_VC_WAKEUP 0x83 +#define CPIA2_VC_WAKEUP_SW_ENABLE 0x01 +#define CPIA2_VC_WAKEUP_XX_ENABLE 0x02 +#define CPIA2_VC_WAKEUP_SW_ATWAKEUP 0x04 +#define CPIA2_VC_WAKEUP_XX_ATWAKEUP 0x08 + +#define CPIA2_VC_CLOCK_CTRL 0x84 +#define CPIA2_VC_CLOCK_CTRL_TESTUP72 0x01 + +#define CPIA2_VC_INT_ENABLE 0x88 +#define CPIA2_VC_INT_ENABLE_XX_IE 0x01 +#define CPIA2_VC_INT_ENABLE_SW_IE 0x02 +#define CPIA2_VC_INT_ENABLE_VC_IE 0x04 +#define CPIA2_VC_INT_ENABLE_USBDATA_IE 0x08 +#define CPIA2_VC_INT_ENABLE_USBSETUP_IE 0x10 +#define CPIA2_VC_INT_ENABLE_USBCFG_IE 0x20 + +#define CPIA2_VC_INT_FLAG 0x89 +#define CPIA2_VC_INT_ENABLE_XX_FLAG 0x01 +#define CPIA2_VC_INT_ENABLE_SW_FLAG 0x02 +#define CPIA2_VC_INT_ENABLE_VC_FLAG 0x04 +#define CPIA2_VC_INT_ENABLE_USBDATA_FLAG 0x08 +#define CPIA2_VC_INT_ENABLE_USBSETUP_FLAG 0x10 +#define CPIA2_VC_INT_ENABLE_USBCFG_FLAG 0x20 +#define CPIA2_VC_INT_ENABLE_SET_RESET_BIT 0x80 + +#define CPIA2_VC_INT_STATE 0x8A +#define CPIA2_VC_INT_STATE_XX_STATE 0x01 +#define CPIA2_VC_INT_STATE_SW_STATE 0x02 + +#define CPIA2_VC_MP_DIR 0x90 +#define CPIA2_VC_MP_DIR_INPUT 0x00 +#define CPIA2_VC_MP_DIR_OUTPUT 0x01 + +#define CPIA2_VC_MP_DATA 0x91 + +#define CPIA2_VC_DP_CTRL 0x98 +#define CPIA2_VC_DP_CTRL_MODE_0 0x00 +#define CPIA2_VC_DP_CTRL_MODE_A 0x01 +#define CPIA2_VC_DP_CTRL_MODE_B 0x02 +#define CPIA2_VC_DP_CTRL_MODE_C 0x03 +#define CPIA2_VC_DP_CTRL_FAKE_FST 0x04 + +#define CPIA2_VC_AD_CTRL 0x99 +#define CPIA2_VC_AD_CTRL_SRC_0 0x00 +#define CPIA2_VC_AD_CTRL_SRC_DIGI_A 0x01 +#define CPIA2_VC_AD_CTRL_SRC_REG 0x02 +#define CPIA2_VC_AD_CTRL_DST_USB 0x00 +#define CPIA2_VC_AD_CTRL_DST_REG 0x04 + +#define CPIA2_VC_AD_TEST_IN 0x9B + +#define CPIA2_VC_AD_TEST_OUT 0x9C + +#define CPIA2_VC_AD_STATUS 0x9D +#define CPIA2_VC_AD_STATUS_EMPTY 0x01 +#define CPIA2_VC_AD_STATUS_FULL 0x02 + +#define CPIA2_VC_DP_DATA 0x9E + +#define CPIA2_VC_ST_CTRL 0xA0 +#define CPIA2_VC_ST_CTRL_SRC_VC 0x00 +#define CPIA2_VC_ST_CTRL_SRC_DP 0x01 +#define CPIA2_VC_ST_CTRL_SRC_REG 0x02 + +#define CPIA2_VC_ST_CTRL_RAW_SELECT 0x04 + +#define CPIA2_VC_ST_CTRL_DST_USB 0x00 +#define CPIA2_VC_ST_CTRL_DST_DP 0x08 +#define CPIA2_VC_ST_CTRL_DST_REG 0x10 + +#define CPIA2_VC_ST_CTRL_FIFO_ENABLE 0x20 +#define CPIA2_VC_ST_CTRL_EOF_DETECT 0x40 + +#define CPIA2_VC_ST_TEST 0xA1 +#define CPIA2_VC_ST_TEST_MODE_MANUAL 0x00 +#define CPIA2_VC_ST_TEST_MODE_INCREMENT 0x02 + +#define CPIA2_VC_ST_TEST_AUTO_FILL 0x08 + +#define CPIA2_VC_ST_TEST_REPEAT_FIFO 0x10 + +#define CPIA2_VC_ST_TEST_IN 0xA2 + +#define CPIA2_VC_ST_TEST_OUT 0xA3 + +#define CPIA2_VC_ST_STATUS 0xA4 +#define CPIA2_VC_ST_STATUS_EMPTY 0x01 +#define CPIA2_VC_ST_STATUS_FULL 0x02 + +#define CPIA2_VC_ST_FRAME_DETECT_1 0xA5 + +#define CPIA2_VC_ST_FRAME_DETECT_2 0xA6 + +#define CPIA2_VC_USB_CTRL 0xA8 +#define CPIA2_VC_USB_CTRL_CMD_STALLED 0x01 +#define CPIA2_VC_USB_CTRL_CMD_READY 0x02 +#define CPIA2_VC_USB_CTRL_CMD_STATUS 0x04 +#define CPIA2_VC_USB_CTRL_CMD_STATUS_DIR 0x08 +#define CPIA2_VC_USB_CTRL_CMD_NO_CLASH 0x10 +#define CPIA2_VC_USB_CTRL_CMD_MICRO_ACCESS 0x80 + +#define CPIA2_VC_USB_STRM 0xA9 +#define CPIA2_VC_USB_STRM_ISO_ENABLE 0x01 +#define CPIA2_VC_USB_STRM_BLK_ENABLE 0x02 +#define CPIA2_VC_USB_STRM_INT_ENABLE 0x04 +#define CPIA2_VC_USB_STRM_AUD_ENABLE 0x08 + +#define CPIA2_VC_USB_STATUS 0xAA +#define CPIA2_VC_USB_STATUS_CMD_IN_PROGRESS 0x01 +#define CPIA2_VC_USB_STATUS_CMD_STATUS_STALL 0x02 +#define CPIA2_VC_USB_STATUS_CMD_HANDSHAKE 0x04 +#define CPIA2_VC_USB_STATUS_CMD_OVERRIDE 0x08 +#define CPIA2_VC_USB_STATUS_CMD_FIFO_BUSY 0x10 +#define CPIA2_VC_USB_STATUS_BULK_REPEAT_TXN 0x20 +#define CPIA2_VC_USB_STATUS_CONFIG_DONE 0x40 +#define CPIA2_VC_USB_STATUS_USB_SUSPEND 0x80 + +#define CPIA2_VC_USB_CMDW 0xAB + +#define CPIA2_VC_USB_DATARW 0xAC + +#define CPIA2_VC_USB_INFO 0xAD + +#define CPIA2_VC_USB_CONFIG 0xAE + +#define CPIA2_VC_USB_SETTINGS 0xAF +#define CPIA2_VC_USB_SETTINGS_CONFIG_MASK 0x03 +#define CPIA2_VC_USB_SETTINGS_INTERFACE_MASK 0x0C +#define CPIA2_VC_USB_SETTINGS_ALTERNATE_MASK 0x70 + +#define CPIA2_VC_USB_ISOLIM 0xB0 + +#define CPIA2_VC_USB_ISOFAILS 0xB1 + +#define CPIA2_VC_USB_ISOMAXPKTHI 0xB2 + +#define CPIA2_VC_USB_ISOMAXPKTLO 0xB3 + +#define CPIA2_VC_V2W_CTRL 0xB8 +#define CPIA2_VC_V2W_SELECT 0x01 + +#define CPIA2_VC_V2W_SCL 0xB9 + +#define CPIA2_VC_V2W_SDA 0xBA + +#define CPIA2_VC_VC_CTRL 0xC0 +#define CPIA2_VC_VC_CTRL_RUN 0x01 +#define CPIA2_VC_VC_CTRL_SINGLESHOT 0x02 +#define CPIA2_VC_VC_CTRL_IDLING 0x04 +#define CPIA2_VC_VC_CTRL_INHIBIT_H_TABLES 0x10 +#define CPIA2_VC_VC_CTRL_INHIBIT_Q_TABLES 0x20 +#define CPIA2_VC_VC_CTRL_INHIBIT_PRIVATE 0x40 + +#define CPIA2_VC_VC_RESTART_IVAL_HI 0xC1 + +#define CPIA2_VC_VC_RESTART_IVAL_LO 0xC2 + +#define CPIA2_VC_VC_FORMAT 0xC3 +#define CPIA2_VC_VC_FORMAT_UFIRST 0x01 +#define CPIA2_VC_VC_FORMAT_MONO 0x02 +#define CPIA2_VC_VC_FORMAT_DECIMATING 0x04 +#define CPIA2_VC_VC_FORMAT_SHORTLINE 0x08 +#define CPIA2_VC_VC_FORMAT_SELFTEST 0x10 + +#define CPIA2_VC_VC_CLOCKS 0xC4 +#define CPIA2_VC_VC_CLOCKS_CLKDIV_MASK 0x03 +#define CPIA2_VC_VC_672_CLOCKS_CIF_DIV_BY_3 0x04 +#define CPIA2_VC_VC_672_CLOCKS_SCALING 0x08 +#define CPIA2_VC_VC_CLOCKS_LOGDIV0 0x00 +#define CPIA2_VC_VC_CLOCKS_LOGDIV1 0x01 +#define CPIA2_VC_VC_CLOCKS_LOGDIV2 0x02 +#define CPIA2_VC_VC_CLOCKS_LOGDIV3 0x03 +#define CPIA2_VC_VC_676_CLOCKS_CIF_DIV_BY_3 0x08 +#define CPIA2_VC_VC_676_CLOCKS_SCALING 0x10 + +#define CPIA2_VC_VC_IHSIZE_LO 0xC5 + +#define CPIA2_VC_VC_XLIM_HI 0xC6 + +#define CPIA2_VC_VC_XLIM_LO 0xC7 + +#define CPIA2_VC_VC_YLIM_HI 0xC8 + +#define CPIA2_VC_VC_YLIM_LO 0xC9 + +#define CPIA2_VC_VC_OHSIZE 0xCA + +#define CPIA2_VC_VC_OVSIZE 0xCB + +#define CPIA2_VC_VC_HCROP 0xCC + +#define CPIA2_VC_VC_VCROP 0xCD + +#define CPIA2_VC_VC_HPHASE 0xCE + +#define CPIA2_VC_VC_VPHASE 0xCF + +#define CPIA2_VC_VC_HISPAN 0xD0 + +#define CPIA2_VC_VC_VISPAN 0xD1 + +#define CPIA2_VC_VC_HICROP 0xD2 + +#define CPIA2_VC_VC_VICROP 0xD3 + +#define CPIA2_VC_VC_HFRACT 0xD4 +#define CPIA2_VC_VC_HFRACT_DEN_MASK 0x0F +#define CPIA2_VC_VC_HFRACT_NUM_MASK 0xF0 + +#define CPIA2_VC_VC_VFRACT 0xD5 +#define CPIA2_VC_VC_VFRACT_DEN_MASK 0x0F +#define CPIA2_VC_VC_VFRACT_NUM_MASK 0xF0 + +#define CPIA2_VC_VC_JPEG_OPT 0xD6 +#define CPIA2_VC_VC_JPEG_OPT_DOUBLE_SQUEEZE 0x01 +#define CPIA2_VC_VC_JPEG_OPT_NO_DC_AUTO_SQUEEZE 0x02 +#define CPIA2_VC_VC_JPEG_OPT_AUTO_SQUEEZE 0x04 +#define CPIA2_VC_VC_JPEG_OPT_DEFAULT (CPIA2_VC_VC_JPEG_OPT_DOUBLE_SQUEEZE|\ + CPIA2_VC_VC_JPEG_OPT_AUTO_SQUEEZE) + + +#define CPIA2_VC_VC_CREEP_PERIOD 0xD7 +#define CPIA2_VC_VC_USER_SQUEEZE 0xD8 +#define CPIA2_VC_VC_TARGET_KB 0xD9 + +#define CPIA2_VC_VC_AUTO_SQUEEZE 0xE6 + + +/*** + * VP register set (Bank 2) + ***/ +#define CPIA2_VP_DEVICEH 0 +#define CPIA2_VP_DEVICEL 1 + +#define CPIA2_VP_SYSTEMSTATE 0x02 +#define CPIA2_VP_SYSTEMSTATE_HK_ALIVE 0x01 + +#define CPIA2_VP_SYSTEMCTRL 0x03 +#define CPIA2_VP_SYSTEMCTRL_REQ_CLEAR_ERROR 0x80 +#define CPIA2_VP_SYSTEMCTRL_POWER_DOWN_PLL 0x20 +#define CPIA2_VP_SYSTEMCTRL_REQ_SUSPEND_STATE 0x10 +#define CPIA2_VP_SYSTEMCTRL_REQ_SERIAL_WAKEUP 0x08 +#define CPIA2_VP_SYSTEMCTRL_REQ_AUTOLOAD 0x04 +#define CPIA2_VP_SYSTEMCTRL_HK_CONTROL 0x02 +#define CPIA2_VP_SYSTEMCTRL_POWER_CONTROL 0x01 + +#define CPIA2_VP_SENSOR_FLAGS 0x05 +#define CPIA2_VP_SENSOR_FLAGS_404 0x01 +#define CPIA2_VP_SENSOR_FLAGS_407 0x02 +#define CPIA2_VP_SENSOR_FLAGS_409 0x04 +#define CPIA2_VP_SENSOR_FLAGS_410 0x08 +#define CPIA2_VP_SENSOR_FLAGS_500 0x10 + +#define CPIA2_VP_SENSOR_REV 0x06 + +#define CPIA2_VP_DEVICE_CONFIG 0x07 +#define CPIA2_VP_DEVICE_CONFIG_SERIAL_BRIDGE 0x01 + +#define CPIA2_VP_GPIO_DIRECTION 0x08 +#define CPIA2_VP_GPIO_READ 0xFF +#define CPIA2_VP_GPIO_WRITE 0x00 + +#define CPIA2_VP_GPIO_DATA 0x09 + +#define CPIA2_VP_RAM_ADDR_H 0x0A +#define CPIA2_VP_RAM_ADDR_L 0x0B +#define CPIA2_VP_RAM_DATA 0x0C + +#define CPIA2_VP_PATCH_REV 0x0F + +#define CPIA2_VP4_USER_MODE 0x10 +#define CPIA2_VP5_USER_MODE 0x13 +#define CPIA2_VP_USER_MODE_CIF 0x01 +#define CPIA2_VP_USER_MODE_QCIFDS 0x02 +#define CPIA2_VP_USER_MODE_QCIFPTC 0x04 +#define CPIA2_VP_USER_MODE_QVGADS 0x08 +#define CPIA2_VP_USER_MODE_QVGAPTC 0x10 +#define CPIA2_VP_USER_MODE_VGA 0x20 + +#define CPIA2_VP4_FRAMERATE_REQUEST 0x11 +#define CPIA2_VP5_FRAMERATE_REQUEST 0x14 +#define CPIA2_VP_FRAMERATE_60 0x80 +#define CPIA2_VP_FRAMERATE_50 0x40 +#define CPIA2_VP_FRAMERATE_30 0x20 +#define CPIA2_VP_FRAMERATE_25 0x10 +#define CPIA2_VP_FRAMERATE_15 0x08 +#define CPIA2_VP_FRAMERATE_12_5 0x04 +#define CPIA2_VP_FRAMERATE_7_5 0x02 +#define CPIA2_VP_FRAMERATE_6_25 0x01 + +#define CPIA2_VP4_USER_EFFECTS 0x12 +#define CPIA2_VP5_USER_EFFECTS 0x15 +#define CPIA2_VP_USER_EFFECTS_COLBARS 0x01 +#define CPIA2_VP_USER_EFFECTS_COLBARS_GRAD 0x02 +#define CPIA2_VP_USER_EFFECTS_MIRROR 0x04 +#define CPIA2_VP_USER_EFFECTS_FLIP 0x40 // VP5 only + +/* NOTE: CPIA2_VP_EXPOSURE_MODES shares the same register as VP5 User + * Effects */ +#define CPIA2_VP_EXPOSURE_MODES 0x15 +#define CPIA2_VP_EXPOSURE_MODES_INHIBIT_FLICKER 0x20 +#define CPIA2_VP_EXPOSURE_MODES_COMPILE_EXP 0x10 + +#define CPIA2_VP4_EXPOSURE_TARGET 0x16 // VP4 +#define CPIA2_VP5_EXPOSURE_TARGET 0x20 // VP5 + +#define CPIA2_VP_FLICKER_MODES 0x1B +#define CPIA2_VP_FLICKER_MODES_50HZ 0x80 +#define CPIA2_VP_FLICKER_MODES_CUSTOM_FLT_FFREQ 0x40 +#define CPIA2_VP_FLICKER_MODES_NEVER_FLICKER 0x20 +#define CPIA2_VP_FLICKER_MODES_INHIBIT_RUB 0x10 +#define CPIA2_VP_FLICKER_MODES_ADJUST_LINE_FREQ 0x08 +#define CPIA2_VP_FLICKER_MODES_CUSTOM_INT_FFREQ 0x04 + +#define CPIA2_VP_UMISC 0x1D +#define CPIA2_VP_UMISC_FORCE_MONO 0x80 +#define CPIA2_VP_UMISC_FORCE_ID_MASK 0x40 +#define CPIA2_VP_UMISC_INHIBIT_AUTO_FGS 0x20 +#define CPIA2_VP_UMISC_INHIBIT_AUTO_DIMS 0x08 +#define CPIA2_VP_UMISC_OPT_FOR_SENSOR_DS 0x04 +#define CPIA2_VP_UMISC_INHIBIT_AUTO_MODE_INT 0x02 + +#define CPIA2_VP5_ANTIFLKRSETUP 0x22 //34 + +#define CPIA2_VP_INTERPOLATION 0x24 +#define CPIA2_VP_INTERPOLATION_EVEN_FIRST 0x40 +#define CPIA2_VP_INTERPOLATION_HJOG 0x20 +#define CPIA2_VP_INTERPOLATION_VJOG 0x10 + +#define CPIA2_VP_GAMMA 0x25 +#define CPIA2_VP_DEFAULT_GAMMA 0x10 + +#define CPIA2_VP_YRANGE 0x26 + +#define CPIA2_VP_SATURATION 0x27 + +#define CPIA2_VP5_MYBLACK_LEVEL 0x3A //58 +#define CPIA2_VP5_MCYRANGE 0x3B //59 +#define CPIA2_VP5_MYCEILING 0x3C //60 +#define CPIA2_VP5_MCUVSATURATION 0x3D //61 + + +#define CPIA2_VP_REHASH_VALUES 0x60 + + +/*** + * Common sensor registers + ***/ +#define CPIA2_SENSOR_DEVICE_H 0x00 +#define CPIA2_SENSOR_DEVICE_L 0x01 + +#define CPIA2_SENSOR_DATA_FORMAT 0x16 +#define CPIA2_SENSOR_DATA_FORMAT_HMIRROR 0x08 +#define CPIA2_SENSOR_DATA_FORMAT_VMIRROR 0x10 + +#define CPIA2_SENSOR_CR1 0x76 +#define CPIA2_SENSOR_CR1_STAND_BY 0x01 +#define CPIA2_SENSOR_CR1_DOWN_RAMP_GEN 0x02 +#define CPIA2_SENSOR_CR1_DOWN_COLUMN_ADC 0x04 +#define CPIA2_SENSOR_CR1_DOWN_CAB_REGULATOR 0x08 +#define CPIA2_SENSOR_CR1_DOWN_AUDIO_REGULATOR 0x10 +#define CPIA2_SENSOR_CR1_DOWN_VRT_AMP 0x20 +#define CPIA2_SENSOR_CR1_DOWN_BAND_GAP 0x40 + +#endif diff --git a/drivers/staging/media/deprecated/cpia2/cpia2_usb.c b/drivers/staging/media/deprecated/cpia2/cpia2_usb.c new file mode 100644 index 000000000..cba03b286 --- /dev/null +++ b/drivers/staging/media/deprecated/cpia2/cpia2_usb.c @@ -0,0 +1,966 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/**************************************************************************** + * + * Filename: cpia2_usb.c + * + * Copyright 2001, STMicrolectronics, Inc. + * Contact: steve.miller@st.com + * + * Description: + * This is a USB driver for CPia2 based video cameras. + * The infrastructure of this driver is based on the cpia usb driver by + * Jochen Scharrlach and Johannes Erdfeldt. + * + * Stripped of 2.4 stuff ready for main kernel submit by + * Alan Cox + ****************************************************************************/ + +#include +#include +#include +#include + +#include "cpia2.h" + +static int frame_sizes[] = { + 0, // USBIF_CMDONLY + 0, // USBIF_BULK + 128, // USBIF_ISO_1 + 384, // USBIF_ISO_2 + 640, // USBIF_ISO_3 + 768, // USBIF_ISO_4 + 896, // USBIF_ISO_5 + 1023, // USBIF_ISO_6 +}; + +#define FRAMES_PER_DESC 10 +#define FRAME_SIZE_PER_DESC frame_sizes[cam->cur_alt] + +static void process_frame(struct camera_data *cam); +static void cpia2_usb_complete(struct urb *urb); +static int cpia2_usb_probe(struct usb_interface *intf, + const struct usb_device_id *id); +static void cpia2_usb_disconnect(struct usb_interface *intf); +static int cpia2_usb_suspend(struct usb_interface *intf, pm_message_t message); +static int cpia2_usb_resume(struct usb_interface *intf); + +static void free_sbufs(struct camera_data *cam); +static void add_APPn(struct camera_data *cam); +static void add_COM(struct camera_data *cam); +static int submit_urbs(struct camera_data *cam); +static int set_alternate(struct camera_data *cam, unsigned int alt); +static int configure_transfer_mode(struct camera_data *cam, unsigned int alt); + +static const struct usb_device_id cpia2_id_table[] = { + {USB_DEVICE(0x0553, 0x0100)}, + {USB_DEVICE(0x0553, 0x0140)}, + {USB_DEVICE(0x0553, 0x0151)}, /* STV0676 */ + {} /* Terminating entry */ +}; +MODULE_DEVICE_TABLE(usb, cpia2_id_table); + +static struct usb_driver cpia2_driver = { + .name = "cpia2", + .probe = cpia2_usb_probe, + .disconnect = cpia2_usb_disconnect, + .suspend = cpia2_usb_suspend, + .resume = cpia2_usb_resume, + .reset_resume = cpia2_usb_resume, + .id_table = cpia2_id_table +}; + + +/****************************************************************************** + * + * process_frame + * + *****************************************************************************/ +static void process_frame(struct camera_data *cam) +{ + static int frame_count; + + unsigned char *inbuff = cam->workbuff->data; + + DBG("Processing frame #%d, current:%d\n", + cam->workbuff->num, cam->curbuff->num); + + if(cam->workbuff->length > cam->workbuff->max_length) + cam->workbuff->max_length = cam->workbuff->length; + + if ((inbuff[0] == 0xFF) && (inbuff[1] == 0xD8)) { + frame_count++; + } else { + cam->workbuff->status = FRAME_ERROR; + DBG("Start of frame not found\n"); + return; + } + + /*** + * Now the output buffer should have a JPEG image in it. + ***/ + if(!cam->first_image_seen) { + /* Always skip the first image after streaming + * starts. It is almost certainly corrupt. */ + cam->first_image_seen = 1; + cam->workbuff->status = FRAME_EMPTY; + return; + } + if (cam->workbuff->length > 3) { + if(cam->mmapped && + cam->workbuff->length < cam->workbuff->max_length) { + /* No junk in the buffers */ + memset(cam->workbuff->data+cam->workbuff->length, + 0, cam->workbuff->max_length- + cam->workbuff->length); + } + cam->workbuff->max_length = cam->workbuff->length; + cam->workbuff->status = FRAME_READY; + + if(!cam->mmapped && cam->num_frames > 2) { + /* During normal reading, the most recent + * frame will be read. If the current frame + * hasn't started reading yet, it will never + * be read, so mark it empty. If the buffer is + * mmapped, or we have few buffers, we need to + * wait for the user to free the buffer. + * + * NOTE: This is not entirely foolproof with 3 + * buffers, but it would take an EXTREMELY + * overloaded system to cause problems (possible + * image data corruption). Basically, it would + * need to take more time to execute cpia2_read + * than it would for the camera to send + * cam->num_frames-2 frames before problems + * could occur. + */ + cam->curbuff->status = FRAME_EMPTY; + } + cam->curbuff = cam->workbuff; + cam->workbuff = cam->workbuff->next; + DBG("Changed buffers, work:%d, current:%d\n", + cam->workbuff->num, cam->curbuff->num); + return; + } else { + DBG("Not enough data for an image.\n"); + } + + cam->workbuff->status = FRAME_ERROR; + return; +} + +/****************************************************************************** + * + * add_APPn + * + * Adds a user specified APPn record + *****************************************************************************/ +static void add_APPn(struct camera_data *cam) +{ + if(cam->APP_len > 0) { + cam->workbuff->data[cam->workbuff->length++] = 0xFF; + cam->workbuff->data[cam->workbuff->length++] = 0xE0+cam->APPn; + cam->workbuff->data[cam->workbuff->length++] = 0; + cam->workbuff->data[cam->workbuff->length++] = cam->APP_len+2; + memcpy(cam->workbuff->data+cam->workbuff->length, + cam->APP_data, cam->APP_len); + cam->workbuff->length += cam->APP_len; + } +} + +/****************************************************************************** + * + * add_COM + * + * Adds a user specified COM record + *****************************************************************************/ +static void add_COM(struct camera_data *cam) +{ + if(cam->COM_len > 0) { + cam->workbuff->data[cam->workbuff->length++] = 0xFF; + cam->workbuff->data[cam->workbuff->length++] = 0xFE; + cam->workbuff->data[cam->workbuff->length++] = 0; + cam->workbuff->data[cam->workbuff->length++] = cam->COM_len+2; + memcpy(cam->workbuff->data+cam->workbuff->length, + cam->COM_data, cam->COM_len); + cam->workbuff->length += cam->COM_len; + } +} + +/****************************************************************************** + * + * cpia2_usb_complete + * + * callback when incoming packet is received + *****************************************************************************/ +static void cpia2_usb_complete(struct urb *urb) +{ + int i; + unsigned char *cdata; + static bool frame_ready = false; + struct camera_data *cam = (struct camera_data *) urb->context; + + if (urb->status!=0) { + if (!(urb->status == -ENOENT || + urb->status == -ECONNRESET || + urb->status == -ESHUTDOWN)) + { + DBG("urb->status = %d!\n", urb->status); + } + DBG("Stopping streaming\n"); + return; + } + + if (!cam->streaming || !video_is_registered(&cam->vdev)) { + LOG("Will now stop the streaming: streaming = %d, present=%d\n", + cam->streaming, video_is_registered(&cam->vdev)); + return; + } + + /*** + * Packet collater + ***/ + //DBG("Collating %d packets\n", urb->number_of_packets); + for (i = 0; i < urb->number_of_packets; i++) { + u16 checksum, iso_checksum; + int j; + int n = urb->iso_frame_desc[i].actual_length; + int st = urb->iso_frame_desc[i].status; + + if(cam->workbuff->status == FRAME_READY) { + struct framebuf *ptr; + /* Try to find an available buffer */ + DBG("workbuff full, searching\n"); + for (ptr = cam->workbuff->next; + ptr != cam->workbuff; + ptr = ptr->next) + { + if (ptr->status == FRAME_EMPTY) { + ptr->status = FRAME_READING; + ptr->length = 0; + break; + } + } + if (ptr == cam->workbuff) + break; /* No READING or EMPTY buffers left */ + + cam->workbuff = ptr; + } + + if (cam->workbuff->status == FRAME_EMPTY || + cam->workbuff->status == FRAME_ERROR) { + cam->workbuff->status = FRAME_READING; + cam->workbuff->length = 0; + } + + //DBG(" Packet %d length = %d, status = %d\n", i, n, st); + cdata = urb->transfer_buffer + urb->iso_frame_desc[i].offset; + + if (st) { + LOG("cpia2 data error: [%d] len=%d, status = %d\n", + i, n, st); + if(!ALLOW_CORRUPT) + cam->workbuff->status = FRAME_ERROR; + continue; + } + + if(n<=2) + continue; + + checksum = 0; + for(j=0; jworkbuff->status = FRAME_ERROR; + continue; + } + } + n -= 2; + + if(cam->workbuff->status != FRAME_READING) { + if((0xFF == cdata[0] && 0xD8 == cdata[1]) || + (0xD8 == cdata[0] && 0xFF == cdata[1] && + 0 != cdata[2])) { + /* frame is skipped, but increment total + * frame count anyway */ + cam->frame_count++; + } + DBG("workbuff not reading, status=%d\n", + cam->workbuff->status); + continue; + } + + if (cam->frame_size < cam->workbuff->length + n) { + ERR("buffer overflow! length: %d, n: %d\n", + cam->workbuff->length, n); + cam->workbuff->status = FRAME_ERROR; + if(cam->workbuff->length > cam->workbuff->max_length) + cam->workbuff->max_length = + cam->workbuff->length; + continue; + } + + if (cam->workbuff->length == 0) { + int data_offset; + if ((0xD8 == cdata[0]) && (0xFF == cdata[1])) { + data_offset = 1; + } else if((0xFF == cdata[0]) && (0xD8 == cdata[1]) + && (0xFF == cdata[2])) { + data_offset = 2; + } else { + DBG("Ignoring packet, not beginning!\n"); + continue; + } + DBG("Start of frame pattern found\n"); + cam->workbuff->ts = ktime_get_ns(); + cam->workbuff->seq = cam->frame_count++; + cam->workbuff->data[0] = 0xFF; + cam->workbuff->data[1] = 0xD8; + cam->workbuff->length = 2; + add_APPn(cam); + add_COM(cam); + memcpy(cam->workbuff->data+cam->workbuff->length, + cdata+data_offset, n-data_offset); + cam->workbuff->length += n-data_offset; + } else if (cam->workbuff->length > 0) { + memcpy(cam->workbuff->data + cam->workbuff->length, + cdata, n); + cam->workbuff->length += n; + } + + if ((cam->workbuff->length >= 3) && + (cam->workbuff->data[cam->workbuff->length - 3] == 0xFF) && + (cam->workbuff->data[cam->workbuff->length - 2] == 0xD9) && + (cam->workbuff->data[cam->workbuff->length - 1] == 0xFF)) { + frame_ready = true; + cam->workbuff->data[cam->workbuff->length - 1] = 0; + cam->workbuff->length -= 1; + } else if ((cam->workbuff->length >= 2) && + (cam->workbuff->data[cam->workbuff->length - 2] == 0xFF) && + (cam->workbuff->data[cam->workbuff->length - 1] == 0xD9)) { + frame_ready = true; + } + + if (frame_ready) { + DBG("Workbuff image size = %d\n",cam->workbuff->length); + process_frame(cam); + + frame_ready = false; + + if (waitqueue_active(&cam->wq_stream)) + wake_up_interruptible(&cam->wq_stream); + } + } + + if(cam->streaming) { + /* resubmit */ + urb->dev = cam->dev; + if ((i = usb_submit_urb(urb, GFP_ATOMIC)) != 0) + ERR("%s: usb_submit_urb ret %d!\n", __func__, i); + } +} + +/****************************************************************************** + * + * configure_transfer_mode + * + *****************************************************************************/ +static int configure_transfer_mode(struct camera_data *cam, unsigned int alt) +{ + static unsigned char iso_regs[8][4] = { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0xB9, 0x00, 0x00, 0x7E}, + {0xB9, 0x00, 0x01, 0x7E}, + {0xB9, 0x00, 0x02, 0x7E}, + {0xB9, 0x00, 0x02, 0xFE}, + {0xB9, 0x00, 0x03, 0x7E}, + {0xB9, 0x00, 0x03, 0xFD} + }; + struct cpia2_command cmd; + unsigned char reg; + + if (!video_is_registered(&cam->vdev)) + return -ENODEV; + + /*** + * Write the isoc registers according to the alternate selected + ***/ + cmd.direction = TRANSFER_WRITE; + cmd.buffer.block_data[0] = iso_regs[alt][0]; + cmd.buffer.block_data[1] = iso_regs[alt][1]; + cmd.buffer.block_data[2] = iso_regs[alt][2]; + cmd.buffer.block_data[3] = iso_regs[alt][3]; + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.start = CPIA2_VC_USB_ISOLIM; + cmd.reg_count = 4; + cpia2_send_command(cam, &cmd); + + /*** + * Enable relevant streams before starting polling. + * First read USB Stream Config Register. + ***/ + cmd.direction = TRANSFER_READ; + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cmd.start = CPIA2_VC_USB_STRM; + cmd.reg_count = 1; + cpia2_send_command(cam, &cmd); + reg = cmd.buffer.block_data[0]; + + /* Clear iso, bulk, and int */ + reg &= ~(CPIA2_VC_USB_STRM_BLK_ENABLE | + CPIA2_VC_USB_STRM_ISO_ENABLE | + CPIA2_VC_USB_STRM_INT_ENABLE); + + if (alt == USBIF_BULK) { + DBG("Enabling bulk xfer\n"); + reg |= CPIA2_VC_USB_STRM_BLK_ENABLE; /* Enable Bulk */ + cam->xfer_mode = XFER_BULK; + } else if (alt >= USBIF_ISO_1) { + DBG("Enabling ISOC xfer\n"); + reg |= CPIA2_VC_USB_STRM_ISO_ENABLE; + cam->xfer_mode = XFER_ISOC; + } + + cmd.buffer.block_data[0] = reg; + cmd.direction = TRANSFER_WRITE; + cmd.start = CPIA2_VC_USB_STRM; + cmd.reg_count = 1; + cmd.req_mode = CAMERAACCESS_TYPE_BLOCK | CAMERAACCESS_VC; + cpia2_send_command(cam, &cmd); + + return 0; +} + +/****************************************************************************** + * + * cpia2_usb_change_streaming_alternate + * + *****************************************************************************/ +int cpia2_usb_change_streaming_alternate(struct camera_data *cam, + unsigned int alt) +{ + int ret = 0; + + if(alt < USBIF_ISO_1 || alt > USBIF_ISO_6) + return -EINVAL; + + if(alt == cam->params.camera_state.stream_mode) + return 0; + + cpia2_usb_stream_pause(cam); + + configure_transfer_mode(cam, alt); + + cam->params.camera_state.stream_mode = alt; + + /* Reset the camera to prevent image quality degradation */ + cpia2_reset_camera(cam); + + cpia2_usb_stream_resume(cam); + + return ret; +} + +/****************************************************************************** + * + * set_alternate + * + *****************************************************************************/ +static int set_alternate(struct camera_data *cam, unsigned int alt) +{ + int ret = 0; + + if(alt == cam->cur_alt) + return 0; + + if (cam->cur_alt != USBIF_CMDONLY) { + DBG("Changing from alt %d to %d\n", cam->cur_alt, USBIF_CMDONLY); + ret = usb_set_interface(cam->dev, cam->iface, USBIF_CMDONLY); + if (ret != 0) + return ret; + } + if (alt != USBIF_CMDONLY) { + DBG("Changing from alt %d to %d\n", USBIF_CMDONLY, alt); + ret = usb_set_interface(cam->dev, cam->iface, alt); + if (ret != 0) + return ret; + } + + cam->old_alt = cam->cur_alt; + cam->cur_alt = alt; + + return ret; +} + +/****************************************************************************** + * + * free_sbufs + * + * Free all cam->sbuf[]. All non-NULL .data and .urb members that are non-NULL + * are assumed to be allocated. Non-NULL .urb members are also assumed to be + * submitted (and must therefore be killed before they are freed). + *****************************************************************************/ +static void free_sbufs(struct camera_data *cam) +{ + int i; + + for (i = 0; i < NUM_SBUF; i++) { + if(cam->sbuf[i].urb) { + usb_kill_urb(cam->sbuf[i].urb); + usb_free_urb(cam->sbuf[i].urb); + cam->sbuf[i].urb = NULL; + } + if(cam->sbuf[i].data) { + kfree(cam->sbuf[i].data); + cam->sbuf[i].data = NULL; + } + } +} + +/******* +* Convenience functions +*******/ +/**************************************************************************** + * + * write_packet + * + ***************************************************************************/ +static int write_packet(struct usb_device *udev, + u8 request, u8 * registers, u16 start, size_t size) +{ + unsigned char *buf; + int ret; + + if (!registers || size <= 0) + return -EINVAL; + + buf = kmemdup(registers, size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = usb_control_msg(udev, + usb_sndctrlpipe(udev, 0), + request, + USB_TYPE_VENDOR | USB_RECIP_DEVICE, + start, /* value */ + 0, /* index */ + buf, /* buffer */ + size, + 1000); + + kfree(buf); + return ret; +} + +/**************************************************************************** + * + * read_packet + * + ***************************************************************************/ +static int read_packet(struct usb_device *udev, + u8 request, u8 * registers, u16 start, size_t size) +{ + unsigned char *buf; + int ret; + + if (!registers || size <= 0) + return -EINVAL; + + buf = kmalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = usb_control_msg(udev, + usb_rcvctrlpipe(udev, 0), + request, + USB_DIR_IN|USB_TYPE_VENDOR|USB_RECIP_DEVICE, + start, /* value */ + 0, /* index */ + buf, /* buffer */ + size, + 1000); + + if (ret >= 0) + memcpy(registers, buf, size); + + kfree(buf); + + return ret; +} + +/****************************************************************************** + * + * cpia2_usb_transfer_cmd + * + *****************************************************************************/ +int cpia2_usb_transfer_cmd(struct camera_data *cam, + void *registers, + u8 request, u8 start, u8 count, u8 direction) +{ + int err = 0; + struct usb_device *udev = cam->dev; + + if (!udev) { + ERR("%s: Internal driver error: udev is NULL\n", __func__); + return -EINVAL; + } + + if (!registers) { + ERR("%s: Internal driver error: register array is NULL\n", __func__); + return -EINVAL; + } + + if (direction == TRANSFER_READ) { + err = read_packet(udev, request, (u8 *)registers, start, count); + if (err > 0) + err = 0; + } else if (direction == TRANSFER_WRITE) { + err =write_packet(udev, request, (u8 *)registers, start, count); + if (err < 0) { + LOG("Control message failed, err val = %d\n", err); + LOG("Message: request = 0x%0X, start = 0x%0X\n", + request, start); + LOG("Message: count = %d, register[0] = 0x%0X\n", + count, ((unsigned char *) registers)[0]); + } else + err=0; + } else { + LOG("Unexpected first byte of direction: %d\n", + direction); + return -EINVAL; + } + + if(err != 0) + LOG("Unexpected error: %d\n", err); + return err; +} + + +/****************************************************************************** + * + * submit_urbs + * + *****************************************************************************/ +static int submit_urbs(struct camera_data *cam) +{ + struct urb *urb; + int fx, err, i, j; + + for(i=0; isbuf[i].data) + continue; + cam->sbuf[i].data = + kmalloc_array(FRAME_SIZE_PER_DESC, FRAMES_PER_DESC, + GFP_KERNEL); + if (!cam->sbuf[i].data) { + while (--i >= 0) { + kfree(cam->sbuf[i].data); + cam->sbuf[i].data = NULL; + } + return -ENOMEM; + } + } + + /* We double buffer the Isoc lists, and also know the polling + * interval is every frame (1 == (1 << (bInterval -1))). + */ + for(i=0; isbuf[i].urb) { + continue; + } + urb = usb_alloc_urb(FRAMES_PER_DESC, GFP_KERNEL); + if (!urb) { + for (j = 0; j < i; j++) + usb_free_urb(cam->sbuf[j].urb); + for (j = 0; j < NUM_SBUF; j++) { + kfree(cam->sbuf[j].data); + cam->sbuf[j].data = NULL; + } + return -ENOMEM; + } + + cam->sbuf[i].urb = urb; + urb->dev = cam->dev; + urb->context = cam; + urb->pipe = usb_rcvisocpipe(cam->dev, 1 /*ISOC endpoint*/); + urb->transfer_flags = URB_ISO_ASAP; + urb->transfer_buffer = cam->sbuf[i].data; + urb->complete = cpia2_usb_complete; + urb->number_of_packets = FRAMES_PER_DESC; + urb->interval = 1; + urb->transfer_buffer_length = + FRAME_SIZE_PER_DESC * FRAMES_PER_DESC; + + for (fx = 0; fx < FRAMES_PER_DESC; fx++) { + urb->iso_frame_desc[fx].offset = + FRAME_SIZE_PER_DESC * fx; + urb->iso_frame_desc[fx].length = FRAME_SIZE_PER_DESC; + } + } + + + /* Queue the ISO urbs, and resubmit in the completion handler */ + for(i=0; isbuf[i].urb, GFP_KERNEL); + if (err) { + ERR("usb_submit_urb[%d]() = %d\n", i, err); + return err; + } + } + + return 0; +} + +/****************************************************************************** + * + * cpia2_usb_stream_start + * + *****************************************************************************/ +int cpia2_usb_stream_start(struct camera_data *cam, unsigned int alternate) +{ + int ret; + int old_alt; + + if(cam->streaming) + return 0; + + if (cam->flush) { + int i; + DBG("Flushing buffers\n"); + for(i=0; inum_frames; ++i) { + cam->buffers[i].status = FRAME_EMPTY; + cam->buffers[i].length = 0; + } + cam->curbuff = &cam->buffers[0]; + cam->workbuff = cam->curbuff->next; + cam->flush = false; + } + + old_alt = cam->params.camera_state.stream_mode; + cam->params.camera_state.stream_mode = 0; + ret = cpia2_usb_change_streaming_alternate(cam, alternate); + if (ret < 0) { + int ret2; + ERR("cpia2_usb_change_streaming_alternate() = %d!\n", ret); + cam->params.camera_state.stream_mode = old_alt; + ret2 = set_alternate(cam, USBIF_CMDONLY); + if (ret2 < 0) { + ERR("cpia2_usb_change_streaming_alternate(%d) =%d has already failed. Then tried to call set_alternate(USBIF_CMDONLY) = %d.\n", + alternate, ret, ret2); + } + } else { + cam->frame_count = 0; + cam->streaming = 1; + ret = cpia2_usb_stream_resume(cam); + } + return ret; +} + +/****************************************************************************** + * + * cpia2_usb_stream_pause + * + *****************************************************************************/ +int cpia2_usb_stream_pause(struct camera_data *cam) +{ + int ret = 0; + if(cam->streaming) { + free_sbufs(cam); + ret = set_alternate(cam, USBIF_CMDONLY); + } + return ret; +} + +/****************************************************************************** + * + * cpia2_usb_stream_resume + * + *****************************************************************************/ +int cpia2_usb_stream_resume(struct camera_data *cam) +{ + int ret = 0; + if(cam->streaming) { + cam->first_image_seen = 0; + ret = set_alternate(cam, cam->params.camera_state.stream_mode); + if(ret == 0) { + /* for some reason the user effects need to be set + again when starting streaming. */ + cpia2_do_command(cam, CPIA2_CMD_SET_USER_EFFECTS, TRANSFER_WRITE, + cam->params.vp_params.user_effects); + ret = submit_urbs(cam); + } + } + return ret; +} + +/****************************************************************************** + * + * cpia2_usb_stream_stop + * + *****************************************************************************/ +int cpia2_usb_stream_stop(struct camera_data *cam) +{ + int ret; + + ret = cpia2_usb_stream_pause(cam); + cam->streaming = 0; + configure_transfer_mode(cam, 0); + return ret; +} + +/****************************************************************************** + * + * cpia2_usb_probe + * + * Probe and initialize. + *****************************************************************************/ +static int cpia2_usb_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + struct usb_device *udev = interface_to_usbdev(intf); + struct usb_interface_descriptor *interface; + struct camera_data *cam; + int ret; + + /* A multi-config CPiA2 camera? */ + if (udev->descriptor.bNumConfigurations != 1) + return -ENODEV; + interface = &intf->cur_altsetting->desc; + + /* If we get to this point, we found a CPiA2 camera */ + LOG("CPiA2 USB camera found\n"); + + cam = cpia2_init_camera_struct(intf); + if (cam == NULL) + return -ENOMEM; + + cam->dev = udev; + cam->iface = interface->bInterfaceNumber; + + ret = set_alternate(cam, USBIF_CMDONLY); + if (ret < 0) { + ERR("%s: usb_set_interface error (ret = %d)\n", __func__, ret); + goto alt_err; + } + + + if((ret = cpia2_init_camera(cam)) < 0) { + ERR("%s: failed to initialize cpia2 camera (ret = %d)\n", __func__, ret); + goto alt_err; + } + LOG(" CPiA Version: %d.%02d (%d.%d)\n", + cam->params.version.firmware_revision_hi, + cam->params.version.firmware_revision_lo, + cam->params.version.asic_id, + cam->params.version.asic_rev); + LOG(" CPiA PnP-ID: %04x:%04x:%04x\n", + cam->params.pnp_id.vendor, + cam->params.pnp_id.product, + cam->params.pnp_id.device_revision); + LOG(" SensorID: %d.(version %d)\n", + cam->params.version.sensor_flags, + cam->params.version.sensor_rev); + + usb_set_intfdata(intf, cam); + + ret = cpia2_register_camera(cam); + if (ret < 0) { + ERR("%s: Failed to register cpia2 camera (ret = %d)\n", __func__, ret); + goto alt_err; + } + + return 0; + +alt_err: + cpia2_deinit_camera_struct(cam, intf); + return ret; +} + +/****************************************************************************** + * + * cpia2_disconnect + * + *****************************************************************************/ +static void cpia2_usb_disconnect(struct usb_interface *intf) +{ + struct camera_data *cam = usb_get_intfdata(intf); + usb_set_intfdata(intf, NULL); + + DBG("Stopping stream\n"); + cpia2_usb_stream_stop(cam); + + mutex_lock(&cam->v4l2_lock); + DBG("Unregistering camera\n"); + cpia2_unregister_camera(cam); + v4l2_device_disconnect(&cam->v4l2_dev); + mutex_unlock(&cam->v4l2_lock); + + if(cam->buffers) { + DBG("Wakeup waiting processes\n"); + cam->curbuff->status = FRAME_READY; + cam->curbuff->length = 0; + wake_up_interruptible(&cam->wq_stream); + } + + v4l2_device_put(&cam->v4l2_dev); + + LOG("CPiA2 camera disconnected.\n"); +} + +static int cpia2_usb_suspend(struct usb_interface *intf, pm_message_t message) +{ + struct camera_data *cam = usb_get_intfdata(intf); + + mutex_lock(&cam->v4l2_lock); + if (cam->streaming) { + cpia2_usb_stream_stop(cam); + cam->streaming = 1; + } + mutex_unlock(&cam->v4l2_lock); + + dev_info(&intf->dev, "going into suspend..\n"); + return 0; +} + +/* Resume device - start device. */ +static int cpia2_usb_resume(struct usb_interface *intf) +{ + struct camera_data *cam = usb_get_intfdata(intf); + + mutex_lock(&cam->v4l2_lock); + v4l2_ctrl_handler_setup(&cam->hdl); + if (cam->streaming) { + cam->streaming = 0; + cpia2_usb_stream_start(cam, + cam->params.camera_state.stream_mode); + } + mutex_unlock(&cam->v4l2_lock); + + dev_info(&intf->dev, "coming out of suspend..\n"); + return 0; +} + +/****************************************************************************** + * + * usb_cpia2_init + * + *****************************************************************************/ +int cpia2_usb_init(void) +{ + return usb_register(&cpia2_driver); +} + +/****************************************************************************** + * + * usb_cpia_cleanup + * + *****************************************************************************/ +void cpia2_usb_cleanup(void) +{ + schedule_timeout(2 * HZ); + usb_deregister(&cpia2_driver); +} diff --git a/drivers/staging/media/deprecated/cpia2/cpia2_v4l.c b/drivers/staging/media/deprecated/cpia2/cpia2_v4l.c new file mode 100644 index 000000000..926ecfc9b --- /dev/null +++ b/drivers/staging/media/deprecated/cpia2/cpia2_v4l.c @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/**************************************************************************** + * + * Filename: cpia2_v4l.c + * + * Copyright 2001, STMicrolectronics, Inc. + * Contact: steve.miller@st.com + * Copyright 2001,2005, Scott J. Bertin + * + * Description: + * This is a USB driver for CPia2 based video cameras. + * The infrastructure of this driver is based on the cpia usb driver by + * Jochen Scharrlach and Johannes Erdfeldt. + * + * Stripped of 2.4 stuff ready for main kernel submit by + * Alan Cox + ****************************************************************************/ + +#define CPIA_VERSION "3.0.1" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpia2.h" + +static int video_nr = -1; +module_param(video_nr, int, 0); +MODULE_PARM_DESC(video_nr, "video device to register (0=/dev/video0, etc)"); + +static int buffer_size = 68 * 1024; +module_param(buffer_size, int, 0); +MODULE_PARM_DESC(buffer_size, "Size for each frame buffer in bytes (default 68k)"); + +static int num_buffers = 3; +module_param(num_buffers, int, 0); +MODULE_PARM_DESC(num_buffers, "Number of frame buffers (1-" + __stringify(VIDEO_MAX_FRAME) ", default 3)"); + +static int alternate = DEFAULT_ALT; +module_param(alternate, int, 0); +MODULE_PARM_DESC(alternate, "USB Alternate (" __stringify(USBIF_ISO_1) "-" + __stringify(USBIF_ISO_6) ", default " + __stringify(DEFAULT_ALT) ")"); + +static int flicker_mode; +module_param(flicker_mode, int, 0); +MODULE_PARM_DESC(flicker_mode, "Flicker frequency (0 (disabled), " __stringify(50) " or " + __stringify(60) ", default 0)"); + +MODULE_AUTHOR("Steve Miller (STMicroelectronics) "); +MODULE_DESCRIPTION("V4L-driver for STMicroelectronics CPiA2 based cameras"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(CPIA_VERSION); + +#define ABOUT "V4L-Driver for Vision CPiA2 based cameras" +#define CPIA2_CID_USB_ALT (V4L2_CID_USER_BASE | 0xf000) + +/****************************************************************************** + * + * cpia2_open + * + *****************************************************************************/ +static int cpia2_open(struct file *file) +{ + struct camera_data *cam = video_drvdata(file); + int retval; + + if (mutex_lock_interruptible(&cam->v4l2_lock)) + return -ERESTARTSYS; + retval = v4l2_fh_open(file); + if (retval) + goto open_unlock; + + if (v4l2_fh_is_singular_file(file)) { + if (cpia2_allocate_buffers(cam)) { + v4l2_fh_release(file); + retval = -ENOMEM; + goto open_unlock; + } + + /* reset the camera */ + if (cpia2_reset_camera(cam) < 0) { + v4l2_fh_release(file); + retval = -EIO; + goto open_unlock; + } + + cam->APP_len = 0; + cam->COM_len = 0; + } + + cpia2_dbg_dump_registers(cam); +open_unlock: + mutex_unlock(&cam->v4l2_lock); + return retval; +} + +/****************************************************************************** + * + * cpia2_close + * + *****************************************************************************/ +static int cpia2_close(struct file *file) +{ + struct video_device *dev = video_devdata(file); + struct camera_data *cam = video_get_drvdata(dev); + + mutex_lock(&cam->v4l2_lock); + if (video_is_registered(&cam->vdev) && v4l2_fh_is_singular_file(file)) { + cpia2_usb_stream_stop(cam); + + /* save camera state for later open */ + cpia2_save_camera_state(cam); + + cpia2_set_low_power(cam); + cpia2_free_buffers(cam); + } + + if (cam->stream_fh == file->private_data) { + cam->stream_fh = NULL; + cam->mmapped = 0; + } + mutex_unlock(&cam->v4l2_lock); + return v4l2_fh_release(file); +} + +/****************************************************************************** + * + * cpia2_v4l_read + * + *****************************************************************************/ +static ssize_t cpia2_v4l_read(struct file *file, char __user *buf, size_t count, + loff_t *off) +{ + struct camera_data *cam = video_drvdata(file); + int noblock = file->f_flags & O_NONBLOCK; + ssize_t ret; + + if (!cam) + return -EINVAL; + + if (mutex_lock_interruptible(&cam->v4l2_lock)) + return -ERESTARTSYS; + ret = cpia2_read(cam, buf, count, noblock); + mutex_unlock(&cam->v4l2_lock); + return ret; +} + +/****************************************************************************** + * + * cpia2_v4l_poll + * + *****************************************************************************/ +static __poll_t cpia2_v4l_poll(struct file *filp, struct poll_table_struct *wait) +{ + struct camera_data *cam = video_drvdata(filp); + __poll_t res; + + mutex_lock(&cam->v4l2_lock); + res = cpia2_poll(cam, filp, wait); + mutex_unlock(&cam->v4l2_lock); + return res; +} + +static int sync(struct camera_data *cam, int frame_nr) +{ + struct framebuf *frame = &cam->buffers[frame_nr]; + + while (1) { + if (frame->status == FRAME_READY) + return 0; + + if (!cam->streaming) { + frame->status = FRAME_READY; + frame->length = 0; + return 0; + } + + mutex_unlock(&cam->v4l2_lock); + wait_event_interruptible(cam->wq_stream, + !cam->streaming || + frame->status == FRAME_READY); + mutex_lock(&cam->v4l2_lock); + if (signal_pending(current)) + return -ERESTARTSYS; + if (!video_is_registered(&cam->vdev)) + return -ENOTTY; + } +} + +/****************************************************************************** + * + * ioctl_querycap + * + * V4L2 device capabilities + * + *****************************************************************************/ + +static int cpia2_querycap(struct file *file, void *fh, struct v4l2_capability *vc) +{ + struct camera_data *cam = video_drvdata(file); + + strscpy(vc->driver, "cpia2", sizeof(vc->driver)); + + if (cam->params.pnp_id.product == 0x151) + strscpy(vc->card, "QX5 Microscope", sizeof(vc->card)); + else + strscpy(vc->card, "CPiA2 Camera", sizeof(vc->card)); + switch (cam->params.pnp_id.device_type) { + case DEVICE_STV_672: + strcat(vc->card, " (672/"); + break; + case DEVICE_STV_676: + strcat(vc->card, " (676/"); + break; + default: + strcat(vc->card, " (XXX/"); + break; + } + switch (cam->params.version.sensor_flags) { + case CPIA2_VP_SENSOR_FLAGS_404: + strcat(vc->card, "404)"); + break; + case CPIA2_VP_SENSOR_FLAGS_407: + strcat(vc->card, "407)"); + break; + case CPIA2_VP_SENSOR_FLAGS_409: + strcat(vc->card, "409)"); + break; + case CPIA2_VP_SENSOR_FLAGS_410: + strcat(vc->card, "410)"); + break; + case CPIA2_VP_SENSOR_FLAGS_500: + strcat(vc->card, "500)"); + break; + default: + strcat(vc->card, "XXX)"); + break; + } + + if (usb_make_path(cam->dev, vc->bus_info, sizeof(vc->bus_info)) < 0) + memset(vc->bus_info, 0, sizeof(vc->bus_info)); + return 0; +} + +/****************************************************************************** + * + * ioctl_input + * + * V4L2 input get/set/enumerate + * + *****************************************************************************/ + +static int cpia2_enum_input(struct file *file, void *fh, struct v4l2_input *i) +{ + if (i->index) + return -EINVAL; + strscpy(i->name, "Camera", sizeof(i->name)); + i->type = V4L2_INPUT_TYPE_CAMERA; + return 0; +} + +static int cpia2_g_input(struct file *file, void *fh, unsigned int *i) +{ + *i = 0; + return 0; +} + +static int cpia2_s_input(struct file *file, void *fh, unsigned int i) +{ + return i ? -EINVAL : 0; +} + +/****************************************************************************** + * + * ioctl_enum_fmt + * + * V4L2 format enumerate + * + *****************************************************************************/ + +static int cpia2_enum_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_fmtdesc *f) +{ + if (f->index > 1) + return -EINVAL; + + if (f->index == 0) + f->pixelformat = V4L2_PIX_FMT_MJPEG; + else + f->pixelformat = V4L2_PIX_FMT_JPEG; + return 0; +} + +/****************************************************************************** + * + * ioctl_try_fmt + * + * V4L2 format try + * + *****************************************************************************/ + +static int cpia2_try_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct camera_data *cam = video_drvdata(file); + + if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_MJPEG && + f->fmt.pix.pixelformat != V4L2_PIX_FMT_JPEG) + return -EINVAL; + + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.bytesperline = 0; + f->fmt.pix.sizeimage = cam->frame_size; + f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; + + switch (cpia2_match_video_size(f->fmt.pix.width, f->fmt.pix.height)) { + case VIDEOSIZE_VGA: + f->fmt.pix.width = 640; + f->fmt.pix.height = 480; + break; + case VIDEOSIZE_CIF: + f->fmt.pix.width = 352; + f->fmt.pix.height = 288; + break; + case VIDEOSIZE_QVGA: + f->fmt.pix.width = 320; + f->fmt.pix.height = 240; + break; + case VIDEOSIZE_288_216: + f->fmt.pix.width = 288; + f->fmt.pix.height = 216; + break; + case VIDEOSIZE_256_192: + f->fmt.pix.width = 256; + f->fmt.pix.height = 192; + break; + case VIDEOSIZE_224_168: + f->fmt.pix.width = 224; + f->fmt.pix.height = 168; + break; + case VIDEOSIZE_192_144: + f->fmt.pix.width = 192; + f->fmt.pix.height = 144; + break; + case VIDEOSIZE_QCIF: + default: + f->fmt.pix.width = 176; + f->fmt.pix.height = 144; + break; + } + + return 0; +} + +/****************************************************************************** + * + * ioctl_set_fmt + * + * V4L2 format set + * + *****************************************************************************/ + +static int cpia2_s_fmt_vid_cap(struct file *file, void *_fh, + struct v4l2_format *f) +{ + struct camera_data *cam = video_drvdata(file); + int err, frame; + + err = cpia2_try_fmt_vid_cap(file, _fh, f); + if (err != 0) + return err; + + cam->pixelformat = f->fmt.pix.pixelformat; + + /* NOTE: This should be set to 1 for MJPEG, but some apps don't handle + * the missing Huffman table properly. + */ + cam->params.compression.inhibit_htables = 0; + /*f->fmt.pix.pixelformat == V4L2_PIX_FMT_MJPEG;*/ + + /* we set the video window to something smaller or equal to what + * is requested by the user??? + */ + DBG("Requested width = %d, height = %d\n", + f->fmt.pix.width, f->fmt.pix.height); + if (f->fmt.pix.width != cam->width || + f->fmt.pix.height != cam->height) { + cam->width = f->fmt.pix.width; + cam->height = f->fmt.pix.height; + cam->params.roi.width = f->fmt.pix.width; + cam->params.roi.height = f->fmt.pix.height; + cpia2_set_format(cam); + } + + for (frame = 0; frame < cam->num_frames; ++frame) { + if (cam->buffers[frame].status == FRAME_READING) + if ((err = sync(cam, frame)) < 0) + return err; + + cam->buffers[frame].status = FRAME_EMPTY; + } + + return 0; +} + +/****************************************************************************** + * + * ioctl_get_fmt + * + * V4L2 format get + * + *****************************************************************************/ + +static int cpia2_g_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct camera_data *cam = video_drvdata(file); + + f->fmt.pix.width = cam->width; + f->fmt.pix.height = cam->height; + f->fmt.pix.pixelformat = cam->pixelformat; + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.bytesperline = 0; + f->fmt.pix.sizeimage = cam->frame_size; + f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; + + return 0; +} + +/****************************************************************************** + * + * ioctl_cropcap + * + * V4L2 query cropping capabilities + * NOTE: cropping is currently disabled + * + *****************************************************************************/ + +static int cpia2_g_selection(struct file *file, void *fh, + struct v4l2_selection *s) +{ + struct camera_data *cam = video_drvdata(file); + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + switch (s->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + s->r.left = 0; + s->r.top = 0; + s->r.width = cam->width; + s->r.height = cam->height; + break; + default: + return -EINVAL; + } + return 0; +} + +struct framerate_info { + int value; + struct v4l2_fract period; +}; + +static const struct framerate_info framerate_controls[] = { + { CPIA2_VP_FRAMERATE_6_25, { 4, 25 } }, + { CPIA2_VP_FRAMERATE_7_5, { 2, 15 } }, + { CPIA2_VP_FRAMERATE_12_5, { 2, 25 } }, + { CPIA2_VP_FRAMERATE_15, { 1, 15 } }, + { CPIA2_VP_FRAMERATE_25, { 1, 25 } }, + { CPIA2_VP_FRAMERATE_30, { 1, 30 } }, +}; + +static int cpia2_g_parm(struct file *file, void *fh, struct v4l2_streamparm *p) +{ + struct camera_data *cam = video_drvdata(file); + struct v4l2_captureparm *cap = &p->parm.capture; + int i; + + if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + cap->capability = V4L2_CAP_TIMEPERFRAME; + cap->readbuffers = cam->num_frames; + for (i = 0; i < ARRAY_SIZE(framerate_controls); i++) + if (cam->params.vp_params.frame_rate == framerate_controls[i].value) { + cap->timeperframe = framerate_controls[i].period; + break; + } + return 0; +} + +static int cpia2_s_parm(struct file *file, void *fh, struct v4l2_streamparm *p) +{ + struct camera_data *cam = video_drvdata(file); + struct v4l2_captureparm *cap = &p->parm.capture; + struct v4l2_fract tpf = cap->timeperframe; + int max = ARRAY_SIZE(framerate_controls) - 1; + int ret; + int i; + + ret = cpia2_g_parm(file, fh, p); + if (ret || !tpf.denominator || !tpf.numerator) + return ret; + + /* Maximum 15 fps for this model */ + if (cam->params.pnp_id.device_type == DEVICE_STV_672 && + cam->params.version.sensor_flags == CPIA2_VP_SENSOR_FLAGS_500) + max -= 2; + for (i = 0; i <= max; i++) { + struct v4l2_fract f1 = tpf; + struct v4l2_fract f2 = framerate_controls[i].period; + + f1.numerator *= f2.denominator; + f2.numerator *= f1.denominator; + if (f1.numerator >= f2.numerator) + break; + } + if (i > max) + i = max; + cap->timeperframe = framerate_controls[i].period; + return cpia2_set_fps(cam, framerate_controls[i].value); +} + +static const struct { + u32 width; + u32 height; +} cpia2_framesizes[] = { + { 640, 480 }, + { 352, 288 }, + { 320, 240 }, + { 288, 216 }, + { 256, 192 }, + { 224, 168 }, + { 192, 144 }, + { 176, 144 }, +}; + +static int cpia2_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + if (fsize->pixel_format != V4L2_PIX_FMT_MJPEG && + fsize->pixel_format != V4L2_PIX_FMT_JPEG) + return -EINVAL; + if (fsize->index >= ARRAY_SIZE(cpia2_framesizes)) + return -EINVAL; + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; + fsize->discrete.width = cpia2_framesizes[fsize->index].width; + fsize->discrete.height = cpia2_framesizes[fsize->index].height; + + return 0; +} + +static int cpia2_enum_frameintervals(struct file *file, void *fh, + struct v4l2_frmivalenum *fival) +{ + struct camera_data *cam = video_drvdata(file); + int max = ARRAY_SIZE(framerate_controls) - 1; + int i; + + if (fival->pixel_format != V4L2_PIX_FMT_MJPEG && + fival->pixel_format != V4L2_PIX_FMT_JPEG) + return -EINVAL; + + /* Maximum 15 fps for this model */ + if (cam->params.pnp_id.device_type == DEVICE_STV_672 && + cam->params.version.sensor_flags == CPIA2_VP_SENSOR_FLAGS_500) + max -= 2; + if (fival->index > max) + return -EINVAL; + for (i = 0; i < ARRAY_SIZE(cpia2_framesizes); i++) + if (fival->width == cpia2_framesizes[i].width && + fival->height == cpia2_framesizes[i].height) + break; + if (i == ARRAY_SIZE(cpia2_framesizes)) + return -EINVAL; + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; + fival->discrete = framerate_controls[fival->index].period; + return 0; +} + +/****************************************************************************** + * + * ioctl_s_ctrl + * + * V4L2 set the value of a control variable + * + *****************************************************************************/ + +static int cpia2_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct camera_data *cam = + container_of(ctrl->handler, struct camera_data, hdl); + static const int flicker_table[] = { + NEVER_FLICKER, + FLICKER_50, + FLICKER_60, + }; + + DBG("Set control id:%d, value:%d\n", ctrl->id, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + cpia2_set_brightness(cam, ctrl->val); + break; + case V4L2_CID_CONTRAST: + cpia2_set_contrast(cam, ctrl->val); + break; + case V4L2_CID_SATURATION: + cpia2_set_saturation(cam, ctrl->val); + break; + case V4L2_CID_HFLIP: + cpia2_set_property_mirror(cam, ctrl->val); + break; + case V4L2_CID_VFLIP: + cpia2_set_property_flip(cam, ctrl->val); + break; + case V4L2_CID_POWER_LINE_FREQUENCY: + return cpia2_set_flicker_mode(cam, flicker_table[ctrl->val]); + case V4L2_CID_ILLUMINATORS_1: + return cpia2_set_gpio(cam, (cam->top_light->val << 6) | + (cam->bottom_light->val << 7)); + case V4L2_CID_JPEG_ACTIVE_MARKER: + cam->params.compression.inhibit_htables = + !(ctrl->val & V4L2_JPEG_ACTIVE_MARKER_DHT); + break; + case V4L2_CID_JPEG_COMPRESSION_QUALITY: + cam->params.vc_params.quality = ctrl->val; + break; + case CPIA2_CID_USB_ALT: + cam->params.camera_state.stream_mode = ctrl->val; + break; + default: + return -EINVAL; + } + + return 0; +} + +/****************************************************************************** + * + * ioctl_g_jpegcomp + * + * V4L2 get the JPEG compression parameters + * + *****************************************************************************/ + +static int cpia2_g_jpegcomp(struct file *file, void *fh, struct v4l2_jpegcompression *parms) +{ + struct camera_data *cam = video_drvdata(file); + + memset(parms, 0, sizeof(*parms)); + + parms->quality = 80; // TODO: Can this be made meaningful? + + parms->jpeg_markers = V4L2_JPEG_MARKER_DQT | V4L2_JPEG_MARKER_DRI; + if (!cam->params.compression.inhibit_htables) + parms->jpeg_markers |= V4L2_JPEG_MARKER_DHT; + + parms->APPn = cam->APPn; + parms->APP_len = cam->APP_len; + if (cam->APP_len > 0) { + memcpy(parms->APP_data, cam->APP_data, cam->APP_len); + parms->jpeg_markers |= V4L2_JPEG_MARKER_APP; + } + + parms->COM_len = cam->COM_len; + if (cam->COM_len > 0) { + memcpy(parms->COM_data, cam->COM_data, cam->COM_len); + parms->jpeg_markers |= JPEG_MARKER_COM; + } + + DBG("G_JPEGCOMP APP_len:%d COM_len:%d\n", + parms->APP_len, parms->COM_len); + + return 0; +} + +/****************************************************************************** + * + * ioctl_s_jpegcomp + * + * V4L2 set the JPEG compression parameters + * NOTE: quality and some jpeg_markers are ignored. + * + *****************************************************************************/ + +static int cpia2_s_jpegcomp(struct file *file, void *fh, + const struct v4l2_jpegcompression *parms) +{ + struct camera_data *cam = video_drvdata(file); + + DBG("S_JPEGCOMP APP_len:%d COM_len:%d\n", + parms->APP_len, parms->COM_len); + + cam->params.compression.inhibit_htables = + !(parms->jpeg_markers & V4L2_JPEG_MARKER_DHT); + + if (parms->APP_len != 0) { + if (parms->APP_len > 0 && + parms->APP_len <= sizeof(cam->APP_data) && + parms->APPn >= 0 && parms->APPn <= 15) { + cam->APPn = parms->APPn; + cam->APP_len = parms->APP_len; + memcpy(cam->APP_data, parms->APP_data, parms->APP_len); + } else { + LOG("Bad APPn Params n=%d len=%d\n", + parms->APPn, parms->APP_len); + return -EINVAL; + } + } else { + cam->APP_len = 0; + } + + if (parms->COM_len != 0) { + if (parms->COM_len > 0 && + parms->COM_len <= sizeof(cam->COM_data)) { + cam->COM_len = parms->COM_len; + memcpy(cam->COM_data, parms->COM_data, parms->COM_len); + } else { + LOG("Bad COM_len=%d\n", parms->COM_len); + return -EINVAL; + } + } + + return 0; +} + +/****************************************************************************** + * + * ioctl_reqbufs + * + * V4L2 Initiate memory mapping. + * NOTE: The user's request is ignored. For now the buffers are fixed. + * + *****************************************************************************/ + +static int cpia2_reqbufs(struct file *file, void *fh, struct v4l2_requestbuffers *req) +{ + struct camera_data *cam = video_drvdata(file); + + if (req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || + req->memory != V4L2_MEMORY_MMAP) + return -EINVAL; + + DBG("REQBUFS requested:%d returning:%d\n", req->count, cam->num_frames); + req->count = cam->num_frames; + memset(&req->reserved, 0, sizeof(req->reserved)); + + return 0; +} + +/****************************************************************************** + * + * ioctl_querybuf + * + * V4L2 Query memory buffer status. + * + *****************************************************************************/ + +static int cpia2_querybuf(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + struct camera_data *cam = video_drvdata(file); + + if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || + buf->index >= cam->num_frames) + return -EINVAL; + + buf->m.offset = cam->buffers[buf->index].data - cam->frame_buffer; + buf->length = cam->frame_size; + + buf->memory = V4L2_MEMORY_MMAP; + + if (cam->mmapped) + buf->flags = V4L2_BUF_FLAG_MAPPED; + else + buf->flags = 0; + + buf->flags |= V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + + switch (cam->buffers[buf->index].status) { + case FRAME_EMPTY: + case FRAME_ERROR: + case FRAME_READING: + buf->bytesused = 0; + buf->flags = V4L2_BUF_FLAG_QUEUED; + break; + case FRAME_READY: + buf->bytesused = cam->buffers[buf->index].length; + v4l2_buffer_set_timestamp(buf, cam->buffers[buf->index].ts); + buf->sequence = cam->buffers[buf->index].seq; + buf->flags = V4L2_BUF_FLAG_DONE; + break; + } + + DBG("QUERYBUF index:%d offset:%d flags:%d seq:%d bytesused:%d\n", + buf->index, buf->m.offset, buf->flags, buf->sequence, + buf->bytesused); + + return 0; +} + +/****************************************************************************** + * + * ioctl_qbuf + * + * V4L2 User is freeing buffer + * + *****************************************************************************/ + +static int cpia2_qbuf(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + struct camera_data *cam = video_drvdata(file); + + if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || + buf->memory != V4L2_MEMORY_MMAP || + buf->index >= cam->num_frames) + return -EINVAL; + + DBG("QBUF #%d\n", buf->index); + + if (cam->buffers[buf->index].status == FRAME_READY) + cam->buffers[buf->index].status = FRAME_EMPTY; + + return 0; +} + +/****************************************************************************** + * + * find_earliest_filled_buffer + * + * Helper for ioctl_dqbuf. Find the next ready buffer. + * + *****************************************************************************/ + +static int find_earliest_filled_buffer(struct camera_data *cam) +{ + int i; + int found = -1; + + for (i = 0; i < cam->num_frames; i++) { + if (cam->buffers[i].status == FRAME_READY) { + if (found < 0) { + found = i; + } else { + /* find which buffer is earlier */ + if (cam->buffers[i].ts < cam->buffers[found].ts) + found = i; + } + } + } + return found; +} + +/****************************************************************************** + * + * ioctl_dqbuf + * + * V4L2 User is asking for a filled buffer. + * + *****************************************************************************/ + +static int cpia2_dqbuf(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + struct camera_data *cam = video_drvdata(file); + int frame; + + if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || + buf->memory != V4L2_MEMORY_MMAP) + return -EINVAL; + + frame = find_earliest_filled_buffer(cam); + + if (frame < 0 && file->f_flags & O_NONBLOCK) + return -EAGAIN; + + if (frame < 0) { + /* Wait for a frame to become available */ + struct framebuf *cb = cam->curbuff; + + mutex_unlock(&cam->v4l2_lock); + wait_event_interruptible(cam->wq_stream, + !video_is_registered(&cam->vdev) || + (cb = cam->curbuff)->status == FRAME_READY); + mutex_lock(&cam->v4l2_lock); + if (signal_pending(current)) + return -ERESTARTSYS; + if (!video_is_registered(&cam->vdev)) + return -ENOTTY; + frame = cb->num; + } + + buf->index = frame; + buf->bytesused = cam->buffers[buf->index].length; + buf->flags = V4L2_BUF_FLAG_MAPPED | V4L2_BUF_FLAG_DONE + | V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + buf->field = V4L2_FIELD_NONE; + v4l2_buffer_set_timestamp(buf, cam->buffers[buf->index].ts); + buf->sequence = cam->buffers[buf->index].seq; + buf->m.offset = cam->buffers[buf->index].data - cam->frame_buffer; + buf->length = cam->frame_size; + buf->reserved2 = 0; + buf->request_fd = 0; + memset(&buf->timecode, 0, sizeof(buf->timecode)); + + DBG("DQBUF #%d status:%d seq:%d length:%d\n", buf->index, + cam->buffers[buf->index].status, buf->sequence, buf->bytesused); + + return 0; +} + +static int cpia2_streamon(struct file *file, void *fh, enum v4l2_buf_type type) +{ + struct camera_data *cam = video_drvdata(file); + int ret = -EINVAL; + + DBG("VIDIOC_STREAMON, streaming=%d\n", cam->streaming); + if (!cam->mmapped || type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (!cam->streaming) { + ret = cpia2_usb_stream_start(cam, + cam->params.camera_state.stream_mode); + if (!ret) + v4l2_ctrl_grab(cam->usb_alt, true); + } + return ret; +} + +static int cpia2_streamoff(struct file *file, void *fh, enum v4l2_buf_type type) +{ + struct camera_data *cam = video_drvdata(file); + int ret = -EINVAL; + + DBG("VIDIOC_STREAMOFF, streaming=%d\n", cam->streaming); + if (!cam->mmapped || type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (cam->streaming) { + ret = cpia2_usb_stream_stop(cam); + if (!ret) + v4l2_ctrl_grab(cam->usb_alt, false); + } + return ret; +} + +/****************************************************************************** + * + * cpia2_mmap + * + *****************************************************************************/ +static int cpia2_mmap(struct file *file, struct vm_area_struct *area) +{ + struct camera_data *cam = video_drvdata(file); + int retval; + + if (mutex_lock_interruptible(&cam->v4l2_lock)) + return -ERESTARTSYS; + retval = cpia2_remap_buffer(cam, area); + + if (!retval) + cam->stream_fh = file->private_data; + mutex_unlock(&cam->v4l2_lock); + return retval; +} + +/****************************************************************************** + * + * reset_camera_struct_v4l + * + * Sets all values to the defaults + *****************************************************************************/ +static void reset_camera_struct_v4l(struct camera_data *cam) +{ + cam->width = cam->params.roi.width; + cam->height = cam->params.roi.height; + + cam->frame_size = buffer_size; + cam->num_frames = num_buffers; + + /* Flicker modes */ + cam->params.flicker_control.flicker_mode_req = flicker_mode; + + /* stream modes */ + cam->params.camera_state.stream_mode = alternate; + + cam->pixelformat = V4L2_PIX_FMT_JPEG; +} + +static const struct v4l2_ioctl_ops cpia2_ioctl_ops = { + .vidioc_querycap = cpia2_querycap, + .vidioc_enum_input = cpia2_enum_input, + .vidioc_g_input = cpia2_g_input, + .vidioc_s_input = cpia2_s_input, + .vidioc_enum_fmt_vid_cap = cpia2_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = cpia2_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = cpia2_s_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = cpia2_try_fmt_vid_cap, + .vidioc_g_jpegcomp = cpia2_g_jpegcomp, + .vidioc_s_jpegcomp = cpia2_s_jpegcomp, + .vidioc_g_selection = cpia2_g_selection, + .vidioc_reqbufs = cpia2_reqbufs, + .vidioc_querybuf = cpia2_querybuf, + .vidioc_qbuf = cpia2_qbuf, + .vidioc_dqbuf = cpia2_dqbuf, + .vidioc_streamon = cpia2_streamon, + .vidioc_streamoff = cpia2_streamoff, + .vidioc_s_parm = cpia2_s_parm, + .vidioc_g_parm = cpia2_g_parm, + .vidioc_enum_framesizes = cpia2_enum_framesizes, + .vidioc_enum_frameintervals = cpia2_enum_frameintervals, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +/*** + * The v4l video device structure initialized for this device + ***/ +static const struct v4l2_file_operations cpia2_fops = { + .owner = THIS_MODULE, + .open = cpia2_open, + .release = cpia2_close, + .read = cpia2_v4l_read, + .poll = cpia2_v4l_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = cpia2_mmap, +}; + +static const struct video_device cpia2_template = { + /* I could not find any place for the old .initialize initializer?? */ + .name = "CPiA2 Camera", + .fops = &cpia2_fops, + .ioctl_ops = &cpia2_ioctl_ops, + .release = video_device_release_empty, +}; + +void cpia2_camera_release(struct v4l2_device *v4l2_dev) +{ + struct camera_data *cam = + container_of(v4l2_dev, struct camera_data, v4l2_dev); + + v4l2_ctrl_handler_free(&cam->hdl); + v4l2_device_unregister(&cam->v4l2_dev); + kfree(cam); +} + +static const struct v4l2_ctrl_ops cpia2_ctrl_ops = { + .s_ctrl = cpia2_s_ctrl, +}; + +/****************************************************************************** + * + * cpia2_register_camera + * + *****************************************************************************/ +int cpia2_register_camera(struct camera_data *cam) +{ + struct v4l2_ctrl_handler *hdl = &cam->hdl; + struct v4l2_ctrl_config cpia2_usb_alt = { + .ops = &cpia2_ctrl_ops, + .id = CPIA2_CID_USB_ALT, + .name = "USB Alternate", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = USBIF_ISO_1, + .max = USBIF_ISO_6, + .step = 1, + }; + int ret; + + v4l2_ctrl_handler_init(hdl, 12); + v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_BRIGHTNESS, + cam->params.pnp_id.device_type == DEVICE_STV_672 ? 1 : 0, + 255, 1, DEFAULT_BRIGHTNESS); + v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_CONTRAST, 0, 255, 1, DEFAULT_CONTRAST); + v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_SATURATION, 0, 255, 1, DEFAULT_SATURATION); + v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_JPEG_ACTIVE_MARKER, 0, + V4L2_JPEG_ACTIVE_MARKER_DHT, 0, + V4L2_JPEG_ACTIVE_MARKER_DHT); + v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_JPEG_COMPRESSION_QUALITY, 1, + 100, 1, 100); + cpia2_usb_alt.def = alternate; + cam->usb_alt = v4l2_ctrl_new_custom(hdl, &cpia2_usb_alt, NULL); + /* VP5 Only */ + if (cam->params.pnp_id.device_type != DEVICE_STV_672) + v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + /* Flicker control only valid for 672 */ + if (cam->params.pnp_id.device_type == DEVICE_STV_672) + v4l2_ctrl_new_std_menu(hdl, &cpia2_ctrl_ops, + V4L2_CID_POWER_LINE_FREQUENCY, + V4L2_CID_POWER_LINE_FREQUENCY_60HZ, + 0, 0); + /* Light control only valid for the QX5 Microscope */ + if (cam->params.pnp_id.product == 0x151) { + cam->top_light = v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_ILLUMINATORS_1, + 0, 1, 1, 0); + cam->bottom_light = v4l2_ctrl_new_std(hdl, &cpia2_ctrl_ops, + V4L2_CID_ILLUMINATORS_2, + 0, 1, 1, 0); + v4l2_ctrl_cluster(2, &cam->top_light); + } + + if (hdl->error) { + ret = hdl->error; + v4l2_ctrl_handler_free(hdl); + return ret; + } + + cam->vdev = cpia2_template; + video_set_drvdata(&cam->vdev, cam); + cam->vdev.lock = &cam->v4l2_lock; + cam->vdev.ctrl_handler = hdl; + cam->vdev.v4l2_dev = &cam->v4l2_dev; + cam->vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING; + + reset_camera_struct_v4l(cam); + + /* register v4l device */ + if (video_register_device(&cam->vdev, VFL_TYPE_VIDEO, video_nr) < 0) { + ERR("video_register_device failed\n"); + return -ENODEV; + } + + return 0; +} + +/****************************************************************************** + * + * cpia2_unregister_camera + * + *****************************************************************************/ +void cpia2_unregister_camera(struct camera_data *cam) +{ + video_unregister_device(&cam->vdev); +} + +/****************************************************************************** + * + * check_parameters + * + * Make sure that all user-supplied parameters are sensible + *****************************************************************************/ +static void __init check_parameters(void) +{ + if (buffer_size < PAGE_SIZE) { + buffer_size = PAGE_SIZE; + LOG("buffer_size too small, setting to %d\n", buffer_size); + } else if (buffer_size > 1024 * 1024) { + /* arbitrary upper limiit */ + buffer_size = 1024 * 1024; + LOG("buffer_size ridiculously large, setting to %d\n", + buffer_size); + } else { + buffer_size += PAGE_SIZE - 1; + buffer_size &= ~(PAGE_SIZE - 1); + } + + if (num_buffers < 1) { + num_buffers = 1; + LOG("num_buffers too small, setting to %d\n", num_buffers); + } else if (num_buffers > VIDEO_MAX_FRAME) { + num_buffers = VIDEO_MAX_FRAME; + LOG("num_buffers too large, setting to %d\n", num_buffers); + } + + if (alternate < USBIF_ISO_1 || alternate > USBIF_ISO_6) { + alternate = DEFAULT_ALT; + LOG("alternate specified is invalid, using %d\n", alternate); + } + + if (flicker_mode != 0 && flicker_mode != FLICKER_50 && flicker_mode != FLICKER_60) { + flicker_mode = 0; + LOG("Flicker mode specified is invalid, using %d\n", + flicker_mode); + } + + DBG("Using %d buffers, each %d bytes, alternate=%d\n", + num_buffers, buffer_size, alternate); +} + +/************ Module Stuff ***************/ + +/****************************************************************************** + * + * cpia2_init/module_init + * + *****************************************************************************/ +static int __init cpia2_init(void) +{ + LOG("%s v%s\n", + ABOUT, CPIA_VERSION); + check_parameters(); + return cpia2_usb_init(); +} + +/****************************************************************************** + * + * cpia2_exit/module_exit + * + *****************************************************************************/ +static void __exit cpia2_exit(void) +{ + cpia2_usb_cleanup(); + schedule_timeout(2 * HZ); +} + +module_init(cpia2_init); +module_exit(cpia2_exit); diff --git a/drivers/staging/media/deprecated/fsl-viu/Kconfig b/drivers/staging/media/deprecated/fsl-viu/Kconfig new file mode 100644 index 000000000..399892c69 --- /dev/null +++ b/drivers/staging/media/deprecated/fsl-viu/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_VIU + tristate "NXP VIU Video Driver (DEPRECATED)" + depends on V4L_PLATFORM_DRIVERS + depends on VIDEO_DEV && (PPC_MPC512x || COMPILE_TEST) && I2C + select VIDEOBUF_DMA_CONTIG + help + Support for Freescale VIU video driver. This device captures + video data, or overlays video on DIU frame buffer. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + Say Y here if you want to enable VIU device on MPC5121e Rev2+. + In doubt, say N. diff --git a/drivers/staging/media/deprecated/fsl-viu/Makefile b/drivers/staging/media/deprecated/fsl-viu/Makefile new file mode 100644 index 000000000..931ec56ad --- /dev/null +++ b/drivers/staging/media/deprecated/fsl-viu/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_VIDEO_VIU) += fsl-viu.o diff --git a/drivers/staging/media/deprecated/fsl-viu/TODO b/drivers/staging/media/deprecated/fsl-viu/TODO new file mode 100644 index 000000000..ecb30a429 --- /dev/null +++ b/drivers/staging/media/deprecated/fsl-viu/TODO @@ -0,0 +1,7 @@ +This is one of the few drivers still not using the vb2 +framework, so this driver is now deprecated with the intent of +removing it altogether by the beginning of 2023. + +In order to keep this driver it has to be converted to vb2. +If someone is interested in doing this work, then contact the +linux-media mailinglist (https://linuxtv.org/lists.php). diff --git a/drivers/staging/media/deprecated/fsl-viu/fsl-viu.c b/drivers/staging/media/deprecated/fsl-viu/fsl-viu.c new file mode 100644 index 000000000..afc96f6db --- /dev/null +++ b/drivers/staging/media/deprecated/fsl-viu/fsl-viu.c @@ -0,0 +1,1599 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Freescale VIU video driver + * + * Authors: Hongjun Chen + * Porting to 2.6.35 by DENX Software Engineering, + * Anatolij Gustschin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "fsl_viu" +#define VIU_VERSION "0.5.1" + +#define BUFFER_TIMEOUT msecs_to_jiffies(500) /* 0.5 seconds */ + +#define VIU_VID_MEM_LIMIT 4 /* Video memory limit, in Mb */ + +/* I2C address of video decoder chip is 0x4A */ +#define VIU_VIDEO_DECODER_ADDR 0x25 + +static int info_level; + +#define dprintk(level, fmt, arg...) \ + do { \ + if (level <= info_level) \ + printk(KERN_DEBUG "viu: " fmt , ## arg); \ + } while (0) + +/* + * Basic structures + */ +struct viu_fmt { + u32 fourcc; /* v4l2 format id */ + u32 pixelformat; + int depth; +}; + +static struct viu_fmt formats[] = { + { + .fourcc = V4L2_PIX_FMT_RGB565, + .pixelformat = V4L2_PIX_FMT_RGB565, + .depth = 16, + }, { + .fourcc = V4L2_PIX_FMT_RGB32, + .pixelformat = V4L2_PIX_FMT_RGB32, + .depth = 32, + } +}; + +struct viu_dev; +struct viu_buf; + +/* buffer for one video frame */ +struct viu_buf { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + struct viu_fmt *fmt; +}; + +struct viu_dmaqueue { + struct viu_dev *dev; + struct list_head active; + struct list_head queued; + struct timer_list timeout; +}; + +struct viu_status { + u32 field_irq; + u32 vsync_irq; + u32 hsync_irq; + u32 vstart_irq; + u32 dma_end_irq; + u32 error_irq; +}; + +struct viu_reg { + u32 status_cfg; + u32 luminance; + u32 chroma_r; + u32 chroma_g; + u32 chroma_b; + u32 field_base_addr; + u32 dma_inc; + u32 picture_count; + u32 req_alarm; + u32 alpha; +} __attribute__ ((packed)); + +struct viu_dev { + struct v4l2_device v4l2_dev; + struct v4l2_ctrl_handler hdl; + struct mutex lock; + spinlock_t slock; + int users; + + struct device *dev; + /* various device info */ + struct video_device *vdev; + struct viu_dmaqueue vidq; + enum v4l2_field capfield; + int field; + int first; + int dma_done; + + /* Hardware register area */ + struct viu_reg __iomem *vr; + + /* Interrupt vector */ + int irq; + struct viu_status irqs; + + /* video overlay */ + struct v4l2_framebuffer ovbuf; + struct viu_fmt *ovfmt; + unsigned int ovenable; + enum v4l2_field ovfield; + + /* crop */ + struct v4l2_rect crop_current; + + /* clock pointer */ + struct clk *clk; + + /* decoder */ + struct v4l2_subdev *decoder; + + v4l2_std_id std; +}; + +struct viu_fh { + /* must remain the first field of this struct */ + struct v4l2_fh fh; + struct viu_dev *dev; + + /* video capture */ + struct videobuf_queue vb_vidq; + spinlock_t vbq_lock; /* spinlock for the videobuf queue */ + + /* video overlay */ + struct v4l2_window win; + struct v4l2_clip clips[1]; + + /* video capture */ + struct viu_fmt *fmt; + int width, height, sizeimage; + enum v4l2_buf_type type; +}; + +static struct viu_reg reg_val; + +/* + * Macro definitions of VIU registers + */ + +/* STATUS_CONFIG register */ +enum status_config { + SOFT_RST = 1 << 0, + + ERR_MASK = 0x0f << 4, /* Error code mask */ + ERR_NO = 0x00, /* No error */ + ERR_DMA_V = 0x01 << 4, /* DMA in vertical active */ + ERR_DMA_VB = 0x02 << 4, /* DMA in vertical blanking */ + ERR_LINE_TOO_LONG = 0x04 << 4, /* Line too long */ + ERR_TOO_MANG_LINES = 0x05 << 4, /* Too many lines in field */ + ERR_LINE_TOO_SHORT = 0x06 << 4, /* Line too short */ + ERR_NOT_ENOUGH_LINE = 0x07 << 4, /* Not enough lines in field */ + ERR_FIFO_OVERFLOW = 0x08 << 4, /* FIFO overflow */ + ERR_FIFO_UNDERFLOW = 0x09 << 4, /* FIFO underflow */ + ERR_1bit_ECC = 0x0a << 4, /* One bit ECC error */ + ERR_MORE_ECC = 0x0b << 4, /* Two/more bits ECC error */ + + INT_FIELD_EN = 0x01 << 8, /* Enable field interrupt */ + INT_VSYNC_EN = 0x01 << 9, /* Enable vsync interrupt */ + INT_HSYNC_EN = 0x01 << 10, /* Enable hsync interrupt */ + INT_VSTART_EN = 0x01 << 11, /* Enable vstart interrupt */ + INT_DMA_END_EN = 0x01 << 12, /* Enable DMA end interrupt */ + INT_ERROR_EN = 0x01 << 13, /* Enable error interrupt */ + INT_ECC_EN = 0x01 << 14, /* Enable ECC interrupt */ + + INT_FIELD_STATUS = 0x01 << 16, /* field interrupt status */ + INT_VSYNC_STATUS = 0x01 << 17, /* vsync interrupt status */ + INT_HSYNC_STATUS = 0x01 << 18, /* hsync interrupt status */ + INT_VSTART_STATUS = 0x01 << 19, /* vstart interrupt status */ + INT_DMA_END_STATUS = 0x01 << 20, /* DMA end interrupt status */ + INT_ERROR_STATUS = 0x01 << 21, /* error interrupt status */ + + DMA_ACT = 0x01 << 27, /* Enable DMA transfer */ + FIELD_NO = 0x01 << 28, /* Field number */ + DITHER_ON = 0x01 << 29, /* Dithering is on */ + ROUND_ON = 0x01 << 30, /* Round is on */ + MODE_32BIT = 1UL << 31, /* Data in RGBa888, + * 0 in RGB565 + */ +}; + +#define norm_maxw() 720 +#define norm_maxh() 576 + +#define INT_ALL_STATUS (INT_FIELD_STATUS | INT_VSYNC_STATUS | \ + INT_HSYNC_STATUS | INT_VSTART_STATUS | \ + INT_DMA_END_STATUS | INT_ERROR_STATUS) + +#define NUM_FORMATS ARRAY_SIZE(formats) + +static irqreturn_t viu_intr(int irq, void *dev_id); + +static struct viu_fmt *format_by_fourcc(int fourcc) +{ + int i; + + for (i = 0; i < NUM_FORMATS; i++) { + if (formats[i].pixelformat == fourcc) + return formats + i; + } + + dprintk(0, "unknown pixelformat:'%4.4s'\n", (char *)&fourcc); + return NULL; +} + +static void viu_start_dma(struct viu_dev *dev) +{ + struct viu_reg __iomem *vr = dev->vr; + + dev->field = 0; + + /* Enable DMA operation */ + iowrite32be(SOFT_RST, &vr->status_cfg); + iowrite32be(INT_FIELD_EN, &vr->status_cfg); +} + +static void viu_stop_dma(struct viu_dev *dev) +{ + struct viu_reg __iomem *vr = dev->vr; + int cnt = 100; + u32 status_cfg; + + iowrite32be(0, &vr->status_cfg); + + /* Clear pending interrupts */ + status_cfg = ioread32be(&vr->status_cfg); + if (status_cfg & 0x3f0000) + iowrite32be(status_cfg & 0x3f0000, &vr->status_cfg); + + if (status_cfg & DMA_ACT) { + do { + status_cfg = ioread32be(&vr->status_cfg); + if (status_cfg & INT_DMA_END_STATUS) + break; + } while (cnt--); + + if (cnt < 0) { + /* timed out, issue soft reset */ + iowrite32be(SOFT_RST, &vr->status_cfg); + iowrite32be(0, &vr->status_cfg); + } else { + /* clear DMA_END and other pending irqs */ + iowrite32be(status_cfg & 0x3f0000, &vr->status_cfg); + } + } + + dev->field = 0; +} + +static int restart_video_queue(struct viu_dmaqueue *vidq) +{ + struct viu_buf *buf, *prev; + + dprintk(1, "%s vidq=%p\n", __func__, vidq); + if (!list_empty(&vidq->active)) { + buf = list_entry(vidq->active.next, struct viu_buf, vb.queue); + dprintk(2, "restart_queue [%p/%d]: restart dma\n", + buf, buf->vb.i); + + viu_stop_dma(vidq->dev); + + /* cancel all outstanding capture requests */ + list_for_each_entry_safe(buf, prev, &vidq->active, vb.queue) { + list_del(&buf->vb.queue); + buf->vb.state = VIDEOBUF_ERROR; + wake_up(&buf->vb.done); + } + mod_timer(&vidq->timeout, jiffies+BUFFER_TIMEOUT); + return 0; + } + + prev = NULL; + for (;;) { + if (list_empty(&vidq->queued)) + return 0; + buf = list_entry(vidq->queued.next, struct viu_buf, vb.queue); + if (prev == NULL) { + list_move_tail(&buf->vb.queue, &vidq->active); + + dprintk(1, "Restarting video dma\n"); + viu_stop_dma(vidq->dev); + viu_start_dma(vidq->dev); + + buf->vb.state = VIDEOBUF_ACTIVE; + mod_timer(&vidq->timeout, jiffies+BUFFER_TIMEOUT); + dprintk(2, "[%p/%d] restart_queue - first active\n", + buf, buf->vb.i); + + } else if (prev->vb.width == buf->vb.width && + prev->vb.height == buf->vb.height && + prev->fmt == buf->fmt) { + list_move_tail(&buf->vb.queue, &vidq->active); + buf->vb.state = VIDEOBUF_ACTIVE; + dprintk(2, "[%p/%d] restart_queue - move to active\n", + buf, buf->vb.i); + } else { + return 0; + } + prev = buf; + } +} + +static void viu_vid_timeout(struct timer_list *t) +{ + struct viu_dev *dev = from_timer(dev, t, vidq.timeout); + struct viu_buf *buf; + struct viu_dmaqueue *vidq = &dev->vidq; + + while (!list_empty(&vidq->active)) { + buf = list_entry(vidq->active.next, struct viu_buf, vb.queue); + list_del(&buf->vb.queue); + buf->vb.state = VIDEOBUF_ERROR; + wake_up(&buf->vb.done); + dprintk(1, "viu/0: [%p/%d] timeout\n", buf, buf->vb.i); + } + + restart_video_queue(vidq); +} + +/* + * Videobuf operations + */ +static int buffer_setup(struct videobuf_queue *vq, unsigned int *count, + unsigned int *size) +{ + struct viu_fh *fh = vq->priv_data; + + *size = fh->width * fh->height * fh->fmt->depth >> 3; + if (*count == 0) + *count = 32; + + while (*size * *count > VIU_VID_MEM_LIMIT * 1024 * 1024) + (*count)--; + + dprintk(1, "%s, count=%d, size=%d\n", __func__, *count, *size); + return 0; +} + +static void free_buffer(struct videobuf_queue *vq, struct viu_buf *buf) +{ + struct videobuf_buffer *vb = &buf->vb; + void *vaddr = NULL; + + videobuf_waiton(vq, &buf->vb, 0, 0); + + if (vq->int_ops && vq->int_ops->vaddr) + vaddr = vq->int_ops->vaddr(vb); + + if (vaddr) + videobuf_dma_contig_free(vq, &buf->vb); + + buf->vb.state = VIDEOBUF_NEEDS_INIT; +} + +inline int buffer_activate(struct viu_dev *dev, struct viu_buf *buf) +{ + struct viu_reg __iomem *vr = dev->vr; + int bpp; + + /* setup the DMA base address */ + reg_val.field_base_addr = videobuf_to_dma_contig(&buf->vb); + + dprintk(1, "buffer_activate [%p/%d]: dma addr 0x%lx\n", + buf, buf->vb.i, (unsigned long)reg_val.field_base_addr); + + /* interlace is on by default, set horizontal DMA increment */ + reg_val.status_cfg = 0; + bpp = buf->fmt->depth >> 3; + switch (bpp) { + case 2: + reg_val.status_cfg &= ~MODE_32BIT; + reg_val.dma_inc = buf->vb.width * 2; + break; + case 4: + reg_val.status_cfg |= MODE_32BIT; + reg_val.dma_inc = buf->vb.width * 4; + break; + default: + dprintk(0, "doesn't support color depth(%d)\n", + bpp * 8); + return -EINVAL; + } + + /* setup picture_count register */ + reg_val.picture_count = (buf->vb.height / 2) << 16 | + buf->vb.width; + + reg_val.status_cfg |= DMA_ACT | INT_DMA_END_EN | INT_FIELD_EN; + + buf->vb.state = VIDEOBUF_ACTIVE; + dev->capfield = buf->vb.field; + + /* reset dma increment if needed */ + if (!V4L2_FIELD_HAS_BOTH(buf->vb.field)) + reg_val.dma_inc = 0; + + iowrite32be(reg_val.dma_inc, &vr->dma_inc); + iowrite32be(reg_val.picture_count, &vr->picture_count); + iowrite32be(reg_val.field_base_addr, &vr->field_base_addr); + mod_timer(&dev->vidq.timeout, jiffies + BUFFER_TIMEOUT); + return 0; +} + +static int buffer_prepare(struct videobuf_queue *vq, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct viu_fh *fh = vq->priv_data; + struct viu_buf *buf = container_of(vb, struct viu_buf, vb); + int rc; + + BUG_ON(fh->fmt == NULL); + + if (fh->width < 48 || fh->width > norm_maxw() || + fh->height < 32 || fh->height > norm_maxh()) + return -EINVAL; + buf->vb.size = (fh->width * fh->height * fh->fmt->depth) >> 3; + if (buf->vb.baddr != 0 && buf->vb.bsize < buf->vb.size) + return -EINVAL; + + if (buf->fmt != fh->fmt || + buf->vb.width != fh->width || + buf->vb.height != fh->height || + buf->vb.field != field) { + buf->fmt = fh->fmt; + buf->vb.width = fh->width; + buf->vb.height = fh->height; + buf->vb.field = field; + } + + if (buf->vb.state == VIDEOBUF_NEEDS_INIT) { + rc = videobuf_iolock(vq, &buf->vb, NULL); + if (rc != 0) + goto fail; + + buf->vb.width = fh->width; + buf->vb.height = fh->height; + buf->vb.field = field; + buf->fmt = fh->fmt; + } + + buf->vb.state = VIDEOBUF_PREPARED; + return 0; + +fail: + free_buffer(vq, buf); + return rc; +} + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct viu_buf *buf = container_of(vb, struct viu_buf, vb); + struct viu_fh *fh = vq->priv_data; + struct viu_dev *dev = fh->dev; + struct viu_dmaqueue *vidq = &dev->vidq; + struct viu_buf *prev; + + if (!list_empty(&vidq->queued)) { + dprintk(1, "adding vb queue=%p\n", &buf->vb.queue); + dprintk(1, "vidq pointer 0x%p, queued 0x%p\n", + vidq, &vidq->queued); + dprintk(1, "dev %p, queued: self %p, next %p, head %p\n", + dev, &vidq->queued, vidq->queued.next, + vidq->queued.prev); + list_add_tail(&buf->vb.queue, &vidq->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - append to queued\n", + buf, buf->vb.i); + } else if (list_empty(&vidq->active)) { + dprintk(1, "adding vb active=%p\n", &buf->vb.queue); + list_add_tail(&buf->vb.queue, &vidq->active); + buf->vb.state = VIDEOBUF_ACTIVE; + mod_timer(&vidq->timeout, jiffies+BUFFER_TIMEOUT); + dprintk(2, "[%p/%d] buffer_queue - first active\n", + buf, buf->vb.i); + + buffer_activate(dev, buf); + } else { + dprintk(1, "adding vb queue2=%p\n", &buf->vb.queue); + prev = list_entry(vidq->active.prev, struct viu_buf, vb.queue); + if (prev->vb.width == buf->vb.width && + prev->vb.height == buf->vb.height && + prev->fmt == buf->fmt) { + list_add_tail(&buf->vb.queue, &vidq->active); + buf->vb.state = VIDEOBUF_ACTIVE; + dprintk(2, "[%p/%d] buffer_queue - append to active\n", + buf, buf->vb.i); + } else { + list_add_tail(&buf->vb.queue, &vidq->queued); + buf->vb.state = VIDEOBUF_QUEUED; + dprintk(2, "[%p/%d] buffer_queue - first queued\n", + buf, buf->vb.i); + } + } +} + +static void buffer_release(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct viu_buf *buf = container_of(vb, struct viu_buf, vb); + struct viu_fh *fh = vq->priv_data; + struct viu_dev *dev = (struct viu_dev *)fh->dev; + + viu_stop_dma(dev); + free_buffer(vq, buf); +} + +static const struct videobuf_queue_ops viu_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +/* + * IOCTL vidioc handling + */ +static int vidioc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + strscpy(cap->driver, "viu", sizeof(cap->driver)); + strscpy(cap->card, "viu", sizeof(cap->card)); + strscpy(cap->bus_info, "platform:viu", sizeof(cap->bus_info)); + return 0; +} + +static int vidioc_enum_fmt(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + int index = f->index; + + if (f->index >= NUM_FORMATS) + return -EINVAL; + + f->pixelformat = formats[index].fourcc; + return 0; +} + +static int vidioc_g_fmt_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viu_fh *fh = priv; + + f->fmt.pix.width = fh->width; + f->fmt.pix.height = fh->height; + f->fmt.pix.field = fh->vb_vidq.field; + f->fmt.pix.pixelformat = fh->fmt->pixelformat; + f->fmt.pix.bytesperline = + (f->fmt.pix.width * fh->fmt->depth) >> 3; + f->fmt.pix.sizeimage = fh->sizeimage; + f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; + return 0; +} + +static int vidioc_try_fmt_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viu_fmt *fmt; + unsigned int maxw, maxh; + + fmt = format_by_fourcc(f->fmt.pix.pixelformat); + if (!fmt) { + dprintk(1, "Fourcc format (0x%08x) invalid.", + f->fmt.pix.pixelformat); + return -EINVAL; + } + + maxw = norm_maxw(); + maxh = norm_maxh(); + + f->fmt.pix.field = V4L2_FIELD_INTERLACED; + if (f->fmt.pix.height < 32) + f->fmt.pix.height = 32; + if (f->fmt.pix.height > maxh) + f->fmt.pix.height = maxh; + if (f->fmt.pix.width < 48) + f->fmt.pix.width = 48; + if (f->fmt.pix.width > maxw) + f->fmt.pix.width = maxw; + f->fmt.pix.width &= ~0x03; + f->fmt.pix.bytesperline = + (f->fmt.pix.width * fmt->depth) >> 3; + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; + + return 0; +} + +static int vidioc_s_fmt_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viu_fh *fh = priv; + int ret; + + ret = vidioc_try_fmt_cap(file, fh, f); + if (ret < 0) + return ret; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->width = f->fmt.pix.width; + fh->height = f->fmt.pix.height; + fh->sizeimage = f->fmt.pix.sizeimage; + fh->vb_vidq.field = f->fmt.pix.field; + fh->type = f->type; + return 0; +} + +static int vidioc_g_fmt_overlay(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viu_fh *fh = priv; + + f->fmt.win = fh->win; + return 0; +} + +static int verify_preview(struct viu_dev *dev, struct v4l2_window *win) +{ + enum v4l2_field field; + int maxw, maxh; + + if (dev->ovbuf.base == NULL) + return -EINVAL; + if (dev->ovfmt == NULL) + return -EINVAL; + if (win->w.width < 48 || win->w.height < 32) + return -EINVAL; + + field = win->field; + maxw = dev->crop_current.width; + maxh = dev->crop_current.height; + + if (field == V4L2_FIELD_ANY) { + field = (win->w.height > maxh/2) + ? V4L2_FIELD_INTERLACED + : V4L2_FIELD_TOP; + } + switch (field) { + case V4L2_FIELD_TOP: + case V4L2_FIELD_BOTTOM: + maxh = maxh / 2; + break; + case V4L2_FIELD_INTERLACED: + break; + default: + return -EINVAL; + } + + win->field = field; + if (win->w.width > maxw) + win->w.width = maxw; + if (win->w.height > maxh) + win->w.height = maxh; + return 0; +} + +inline void viu_activate_overlay(struct viu_reg __iomem *vr) +{ + iowrite32be(reg_val.field_base_addr, &vr->field_base_addr); + iowrite32be(reg_val.dma_inc, &vr->dma_inc); + iowrite32be(reg_val.picture_count, &vr->picture_count); +} + +static int viu_setup_preview(struct viu_dev *dev, struct viu_fh *fh) +{ + int bpp; + + dprintk(1, "%s %dx%d\n", __func__, + fh->win.w.width, fh->win.w.height); + + reg_val.status_cfg = 0; + + /* setup window */ + reg_val.picture_count = (fh->win.w.height / 2) << 16 | + fh->win.w.width; + + /* setup color depth and dma increment */ + bpp = dev->ovfmt->depth / 8; + switch (bpp) { + case 2: + reg_val.status_cfg &= ~MODE_32BIT; + reg_val.dma_inc = fh->win.w.width * 2; + break; + case 4: + reg_val.status_cfg |= MODE_32BIT; + reg_val.dma_inc = fh->win.w.width * 4; + break; + default: + dprintk(0, "device doesn't support color depth(%d)\n", + bpp * 8); + return -EINVAL; + } + + dev->ovfield = fh->win.field; + if (!V4L2_FIELD_HAS_BOTH(dev->ovfield)) + reg_val.dma_inc = 0; + + reg_val.status_cfg |= DMA_ACT | INT_DMA_END_EN | INT_FIELD_EN; + + /* setup the base address of the overlay buffer */ + reg_val.field_base_addr = (u32)(long)dev->ovbuf.base; + + return 0; +} + +static int vidioc_s_fmt_overlay(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct viu_fh *fh = priv; + struct viu_dev *dev = (struct viu_dev *)fh->dev; + unsigned long flags; + int err; + + err = verify_preview(dev, &f->fmt.win); + if (err) + return err; + + fh->win = f->fmt.win; + + spin_lock_irqsave(&dev->slock, flags); + viu_setup_preview(dev, fh); + spin_unlock_irqrestore(&dev->slock, flags); + return 0; +} + +static int vidioc_try_fmt_overlay(struct file *file, void *priv, + struct v4l2_format *f) +{ + return 0; +} + +static int vidioc_overlay(struct file *file, void *priv, unsigned int on) +{ + struct viu_fh *fh = priv; + struct viu_dev *dev = (struct viu_dev *)fh->dev; + unsigned long flags; + + if (on) { + spin_lock_irqsave(&dev->slock, flags); + viu_activate_overlay(dev->vr); + dev->ovenable = 1; + + /* start dma */ + viu_start_dma(dev); + spin_unlock_irqrestore(&dev->slock, flags); + } else { + viu_stop_dma(dev); + dev->ovenable = 0; + } + + return 0; +} + +static int vidioc_g_fbuf(struct file *file, void *priv, struct v4l2_framebuffer *arg) +{ + struct viu_fh *fh = priv; + struct viu_dev *dev = fh->dev; + struct v4l2_framebuffer *fb = arg; + + *fb = dev->ovbuf; + fb->capability = V4L2_FBUF_CAP_LIST_CLIPPING; + return 0; +} + +static int vidioc_s_fbuf(struct file *file, void *priv, const struct v4l2_framebuffer *arg) +{ + struct viu_fh *fh = priv; + struct viu_dev *dev = fh->dev; + const struct v4l2_framebuffer *fb = arg; + struct viu_fmt *fmt; + + if (!capable(CAP_SYS_ADMIN) && !capable(CAP_SYS_RAWIO)) + return -EPERM; + + /* check args */ + fmt = format_by_fourcc(fb->fmt.pixelformat); + if (fmt == NULL) + return -EINVAL; + + /* ok, accept it */ + dev->ovbuf = *fb; + dev->ovfmt = fmt; + if (dev->ovbuf.fmt.bytesperline == 0) { + dev->ovbuf.fmt.bytesperline = + dev->ovbuf.fmt.width * fmt->depth / 8; + } + return 0; +} + +static int vidioc_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *p) +{ + struct viu_fh *fh = priv; + + return videobuf_reqbufs(&fh->vb_vidq, p); +} + +static int vidioc_querybuf(struct file *file, void *priv, + struct v4l2_buffer *p) +{ + struct viu_fh *fh = priv; + + return videobuf_querybuf(&fh->vb_vidq, p); +} + +static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct viu_fh *fh = priv; + + return videobuf_qbuf(&fh->vb_vidq, p); +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct viu_fh *fh = priv; + + return videobuf_dqbuf(&fh->vb_vidq, p, + file->f_flags & O_NONBLOCK); +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct viu_fh *fh = priv; + struct viu_dev *dev = fh->dev; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (fh->type != i) + return -EINVAL; + + if (dev->ovenable) + dev->ovenable = 0; + + viu_start_dma(fh->dev); + + return videobuf_streamon(&fh->vb_vidq); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct viu_fh *fh = priv; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (fh->type != i) + return -EINVAL; + + viu_stop_dma(fh->dev); + + return videobuf_streamoff(&fh->vb_vidq); +} + +#define decoder_call(viu, o, f, args...) \ + v4l2_subdev_call(viu->decoder, o, f, ##args) + +static int vidioc_querystd(struct file *file, void *priv, v4l2_std_id *std_id) +{ + struct viu_fh *fh = priv; + + decoder_call(fh->dev, video, querystd, std_id); + return 0; +} + +static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id) +{ + struct viu_fh *fh = priv; + + fh->dev->std = id; + decoder_call(fh->dev, video, s_std, id); + return 0; +} + +static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *std_id) +{ + struct viu_fh *fh = priv; + + *std_id = fh->dev->std; + return 0; +} + +/* only one input in this driver */ +static int vidioc_enum_input(struct file *file, void *priv, + struct v4l2_input *inp) +{ + struct viu_fh *fh = priv; + + if (inp->index != 0) + return -EINVAL; + + inp->type = V4L2_INPUT_TYPE_CAMERA; + inp->std = fh->dev->vdev->tvnorms; + strscpy(inp->name, "Camera", sizeof(inp->name)); + return 0; +} + +static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) +{ + *i = 0; + return 0; +} + +static int vidioc_s_input(struct file *file, void *priv, unsigned int i) +{ + struct viu_fh *fh = priv; + + if (i) + return -EINVAL; + + decoder_call(fh->dev, video, s_routing, i, 0, 0); + return 0; +} + +inline void viu_activate_next_buf(struct viu_dev *dev, + struct viu_dmaqueue *viuq) +{ + struct viu_dmaqueue *vidq = viuq; + struct viu_buf *buf; + + /* launch another DMA operation for an active/queued buffer */ + if (!list_empty(&vidq->active)) { + buf = list_entry(vidq->active.next, struct viu_buf, + vb.queue); + dprintk(1, "start another queued buffer: 0x%p\n", buf); + buffer_activate(dev, buf); + } else if (!list_empty(&vidq->queued)) { + buf = list_entry(vidq->queued.next, struct viu_buf, + vb.queue); + list_del(&buf->vb.queue); + + dprintk(1, "start another queued buffer: 0x%p\n", buf); + list_add_tail(&buf->vb.queue, &vidq->active); + buf->vb.state = VIDEOBUF_ACTIVE; + buffer_activate(dev, buf); + } +} + +inline void viu_default_settings(struct viu_reg __iomem *vr) +{ + iowrite32be(0x9512A254, &vr->luminance); + iowrite32be(0x03310000, &vr->chroma_r); + iowrite32be(0x06600F38, &vr->chroma_g); + iowrite32be(0x00000409, &vr->chroma_b); + iowrite32be(0x000000ff, &vr->alpha); + iowrite32be(0x00000090, &vr->req_alarm); + dprintk(1, "status reg: 0x%08x, field base: 0x%08x\n", + ioread32be(&vr->status_cfg), ioread32be(&vr->field_base_addr)); +} + +static void viu_overlay_intr(struct viu_dev *dev, u32 status) +{ + struct viu_reg __iomem *vr = dev->vr; + + if (status & INT_DMA_END_STATUS) + dev->dma_done = 1; + + if (status & INT_FIELD_STATUS) { + if (dev->dma_done) { + u32 addr = reg_val.field_base_addr; + + dev->dma_done = 0; + if (status & FIELD_NO) + addr += reg_val.dma_inc; + + iowrite32be(addr, &vr->field_base_addr); + iowrite32be(reg_val.dma_inc, &vr->dma_inc); + iowrite32be((status & 0xffc0ffff) | + (status & INT_ALL_STATUS) | + reg_val.status_cfg, &vr->status_cfg); + } else if (status & INT_VSYNC_STATUS) { + iowrite32be((status & 0xffc0ffff) | + (status & INT_ALL_STATUS) | + reg_val.status_cfg, &vr->status_cfg); + } + } +} + +static void viu_capture_intr(struct viu_dev *dev, u32 status) +{ + struct viu_dmaqueue *vidq = &dev->vidq; + struct viu_reg __iomem *vr = dev->vr; + struct viu_buf *buf; + int field_num; + int need_two; + int dma_done = 0; + + field_num = status & FIELD_NO; + need_two = V4L2_FIELD_HAS_BOTH(dev->capfield); + + if (status & INT_DMA_END_STATUS) { + dma_done = 1; + if (((field_num == 0) && (dev->field == 0)) || + (field_num && (dev->field == 1))) + dev->field++; + } + + if (status & INT_FIELD_STATUS) { + dprintk(1, "irq: field %d, done %d\n", + !!field_num, dma_done); + if (unlikely(dev->first)) { + if (field_num == 0) { + dev->first = 0; + dprintk(1, "activate first buf\n"); + viu_activate_next_buf(dev, vidq); + } else + dprintk(1, "wait field 0\n"); + return; + } + + /* setup buffer address for next dma operation */ + if (!list_empty(&vidq->active)) { + u32 addr = reg_val.field_base_addr; + + if (field_num && need_two) { + addr += reg_val.dma_inc; + dprintk(1, "field 1, 0x%lx, dev field %d\n", + (unsigned long)addr, dev->field); + } + iowrite32be(addr, &vr->field_base_addr); + iowrite32be(reg_val.dma_inc, &vr->dma_inc); + iowrite32be((status & 0xffc0ffff) | + (status & INT_ALL_STATUS) | + reg_val.status_cfg, &vr->status_cfg); + return; + } + } + + if (dma_done && field_num && (dev->field == 2)) { + dev->field = 0; + buf = list_entry(vidq->active.next, + struct viu_buf, vb.queue); + dprintk(1, "viu/0: [%p/%d] 0x%lx/0x%lx: dma complete\n", + buf, buf->vb.i, + (unsigned long)videobuf_to_dma_contig(&buf->vb), + (unsigned long)ioread32be(&vr->field_base_addr)); + + if (waitqueue_active(&buf->vb.done)) { + list_del(&buf->vb.queue); + buf->vb.ts = ktime_get_ns(); + buf->vb.state = VIDEOBUF_DONE; + buf->vb.field_count++; + wake_up(&buf->vb.done); + } + /* activate next dma buffer */ + viu_activate_next_buf(dev, vidq); + } +} + +static irqreturn_t viu_intr(int irq, void *dev_id) +{ + struct viu_dev *dev = (struct viu_dev *)dev_id; + struct viu_reg __iomem *vr = dev->vr; + u32 status; + u32 error; + + status = ioread32be(&vr->status_cfg); + + if (status & INT_ERROR_STATUS) { + dev->irqs.error_irq++; + error = status & ERR_MASK; + if (error) + dprintk(1, "Err: error(%d), times:%d!\n", + error >> 4, dev->irqs.error_irq); + /* Clear interrupt error bit and error flags */ + iowrite32be((status & 0xffc0ffff) | INT_ERROR_STATUS, + &vr->status_cfg); + } + + if (status & INT_DMA_END_STATUS) { + dev->irqs.dma_end_irq++; + dev->dma_done = 1; + dprintk(2, "VIU DMA end interrupt times: %d\n", + dev->irqs.dma_end_irq); + } + + if (status & INT_HSYNC_STATUS) + dev->irqs.hsync_irq++; + + if (status & INT_FIELD_STATUS) { + dev->irqs.field_irq++; + dprintk(2, "VIU field interrupt times: %d\n", + dev->irqs.field_irq); + } + + if (status & INT_VSTART_STATUS) + dev->irqs.vstart_irq++; + + if (status & INT_VSYNC_STATUS) { + dev->irqs.vsync_irq++; + dprintk(2, "VIU vsync interrupt times: %d\n", + dev->irqs.vsync_irq); + } + + /* clear all pending irqs */ + status = ioread32be(&vr->status_cfg); + iowrite32be((status & 0xffc0ffff) | (status & INT_ALL_STATUS), + &vr->status_cfg); + + if (dev->ovenable) { + viu_overlay_intr(dev, status); + return IRQ_HANDLED; + } + + /* Capture mode */ + viu_capture_intr(dev, status); + return IRQ_HANDLED; +} + +/* + * File operations for the device + */ +static int viu_open(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct viu_dev *dev = video_get_drvdata(vdev); + struct viu_fh *fh; + struct viu_reg __iomem *vr; + int minor = vdev->minor; + u32 status_cfg; + + dprintk(1, "viu: open (minor=%d)\n", minor); + + dev->users++; + if (dev->users > 1) { + dev->users--; + return -EBUSY; + } + + vr = dev->vr; + + dprintk(1, "open minor=%d type=%s users=%d\n", minor, + v4l2_type_names[V4L2_BUF_TYPE_VIDEO_CAPTURE], dev->users); + + if (mutex_lock_interruptible(&dev->lock)) { + dev->users--; + return -ERESTARTSYS; + } + + /* allocate and initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (!fh) { + dev->users--; + mutex_unlock(&dev->lock); + return -ENOMEM; + } + + v4l2_fh_init(&fh->fh, vdev); + file->private_data = fh; + fh->dev = dev; + + fh->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + fh->fmt = format_by_fourcc(V4L2_PIX_FMT_RGB32); + fh->width = norm_maxw(); + fh->height = norm_maxh(); + dev->crop_current.width = fh->width; + dev->crop_current.height = fh->height; + + dprintk(1, "Open: fh=%p, dev=%p, dev->vidq=%p\n", fh, dev, &dev->vidq); + dprintk(1, "Open: list_empty queued=%d\n", + list_empty(&dev->vidq.queued)); + dprintk(1, "Open: list_empty active=%d\n", + list_empty(&dev->vidq.active)); + + viu_default_settings(vr); + + status_cfg = ioread32be(&vr->status_cfg); + iowrite32be(status_cfg & ~(INT_VSYNC_EN | INT_HSYNC_EN | + INT_FIELD_EN | INT_VSTART_EN | + INT_DMA_END_EN | INT_ERROR_EN | INT_ECC_EN), + &vr->status_cfg); + + status_cfg = ioread32be(&vr->status_cfg); + iowrite32be(status_cfg | INT_ALL_STATUS, &vr->status_cfg); + + spin_lock_init(&fh->vbq_lock); + videobuf_queue_dma_contig_init(&fh->vb_vidq, &viu_video_qops, + dev->dev, &fh->vbq_lock, + fh->type, V4L2_FIELD_INTERLACED, + sizeof(struct viu_buf), fh, + &fh->dev->lock); + v4l2_fh_add(&fh->fh); + mutex_unlock(&dev->lock); + return 0; +} + +static ssize_t viu_read(struct file *file, char __user *data, size_t count, + loff_t *ppos) +{ + struct viu_fh *fh = file->private_data; + struct viu_dev *dev = fh->dev; + int ret = 0; + + dprintk(2, "%s\n", __func__); + if (dev->ovenable) + dev->ovenable = 0; + + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + if (mutex_lock_interruptible(&dev->lock)) + return -ERESTARTSYS; + viu_start_dma(dev); + ret = videobuf_read_stream(&fh->vb_vidq, data, count, + ppos, 0, file->f_flags & O_NONBLOCK); + mutex_unlock(&dev->lock); + return ret; + } + return 0; +} + +static __poll_t viu_poll(struct file *file, struct poll_table_struct *wait) +{ + struct viu_fh *fh = file->private_data; + struct videobuf_queue *q = &fh->vb_vidq; + struct viu_dev *dev = fh->dev; + __poll_t req_events = poll_requested_events(wait); + __poll_t res = v4l2_ctrl_poll(file, wait); + + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != fh->type) + return EPOLLERR; + + if (!(req_events & (EPOLLIN | EPOLLRDNORM))) + return res; + + mutex_lock(&dev->lock); + res |= videobuf_poll_stream(file, q, wait); + mutex_unlock(&dev->lock); + return res; +} + +static int viu_release(struct file *file) +{ + struct viu_fh *fh = file->private_data; + struct viu_dev *dev = fh->dev; + int minor = video_devdata(file)->minor; + + mutex_lock(&dev->lock); + viu_stop_dma(dev); + videobuf_stop(&fh->vb_vidq); + videobuf_mmap_free(&fh->vb_vidq); + v4l2_fh_del(&fh->fh); + v4l2_fh_exit(&fh->fh); + mutex_unlock(&dev->lock); + + kfree(fh); + + dev->users--; + dprintk(1, "close (minor=%d, users=%d)\n", + minor, dev->users); + return 0; +} + +static void viu_reset(struct viu_reg __iomem *reg) +{ + iowrite32be(0, ®->status_cfg); + iowrite32be(0x9512a254, ®->luminance); + iowrite32be(0x03310000, ®->chroma_r); + iowrite32be(0x06600f38, ®->chroma_g); + iowrite32be(0x00000409, ®->chroma_b); + iowrite32be(0, ®->field_base_addr); + iowrite32be(0, ®->dma_inc); + iowrite32be(0x01e002d0, ®->picture_count); + iowrite32be(0x00000090, ®->req_alarm); + iowrite32be(0x000000ff, ®->alpha); +} + +static int viu_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct viu_fh *fh = file->private_data; + struct viu_dev *dev = fh->dev; + int ret; + + dprintk(1, "mmap called, vma=%p\n", vma); + + if (mutex_lock_interruptible(&dev->lock)) + return -ERESTARTSYS; + ret = videobuf_mmap_mapper(&fh->vb_vidq, vma); + mutex_unlock(&dev->lock); + + dprintk(1, "vma start=0x%08lx, size=%ld, ret=%d\n", + (unsigned long)vma->vm_start, + (unsigned long)vma->vm_end-(unsigned long)vma->vm_start, + ret); + + return ret; +} + +static const struct v4l2_file_operations viu_fops = { + .owner = THIS_MODULE, + .open = viu_open, + .release = viu_release, + .read = viu_read, + .poll = viu_poll, + .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ + .mmap = viu_mmap, +}; + +static const struct v4l2_ioctl_ops viu_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_cap, + .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt, + .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_overlay, + .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_overlay, + .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_overlay, + .vidioc_overlay = vidioc_overlay, + .vidioc_g_fbuf = vidioc_g_fbuf, + .vidioc_s_fbuf = vidioc_s_fbuf, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_g_std = vidioc_g_std, + .vidioc_s_std = vidioc_s_std, + .vidioc_querystd = vidioc_querystd, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = v4l2_ctrl_log_status, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static const struct video_device viu_template = { + .name = "FSL viu", + .fops = &viu_fops, + .minor = -1, + .ioctl_ops = &viu_ioctl_ops, + .release = video_device_release, + + .tvnorms = V4L2_STD_NTSC_M | V4L2_STD_PAL, + .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | + V4L2_CAP_VIDEO_OVERLAY | V4L2_CAP_READWRITE, +}; + +static int viu_of_probe(struct platform_device *op) +{ + struct viu_dev *viu_dev; + struct video_device *vdev; + struct resource r; + struct viu_reg __iomem *viu_regs; + struct i2c_adapter *ad; + int ret, viu_irq; + struct clk *clk; + + ret = of_address_to_resource(op->dev.of_node, 0, &r); + if (ret) { + dev_err(&op->dev, "Can't parse device node resource\n"); + return -ENODEV; + } + + viu_irq = irq_of_parse_and_map(op->dev.of_node, 0); + if (!viu_irq) { + dev_err(&op->dev, "Error while mapping the irq\n"); + return -EINVAL; + } + + /* request mem region */ + if (!devm_request_mem_region(&op->dev, r.start, + sizeof(struct viu_reg), DRV_NAME)) { + dev_err(&op->dev, "Error while requesting mem region\n"); + ret = -EBUSY; + goto err_irq; + } + + /* remap registers */ + viu_regs = devm_ioremap(&op->dev, r.start, sizeof(struct viu_reg)); + if (!viu_regs) { + dev_err(&op->dev, "Can't map register set\n"); + ret = -ENOMEM; + goto err_irq; + } + + /* Prepare our private structure */ + viu_dev = devm_kzalloc(&op->dev, sizeof(struct viu_dev), GFP_KERNEL); + if (!viu_dev) { + dev_err(&op->dev, "Can't allocate private structure\n"); + ret = -ENOMEM; + goto err_irq; + } + + viu_dev->vr = viu_regs; + viu_dev->irq = viu_irq; + viu_dev->dev = &op->dev; + + /* init video dma queues */ + INIT_LIST_HEAD(&viu_dev->vidq.active); + INIT_LIST_HEAD(&viu_dev->vidq.queued); + + snprintf(viu_dev->v4l2_dev.name, + sizeof(viu_dev->v4l2_dev.name), "%s", "VIU"); + ret = v4l2_device_register(viu_dev->dev, &viu_dev->v4l2_dev); + if (ret < 0) { + dev_err(&op->dev, "v4l2_device_register() failed: %d\n", ret); + goto err_irq; + } + + ad = i2c_get_adapter(0); + if (!ad) { + ret = -EFAULT; + dev_err(&op->dev, "couldn't get i2c adapter\n"); + goto err_v4l2; + } + + v4l2_ctrl_handler_init(&viu_dev->hdl, 5); + if (viu_dev->hdl.error) { + ret = viu_dev->hdl.error; + dev_err(&op->dev, "couldn't register control\n"); + goto err_i2c; + } + /* This control handler will inherit the control(s) from the + sub-device(s). */ + viu_dev->v4l2_dev.ctrl_handler = &viu_dev->hdl; + viu_dev->decoder = v4l2_i2c_new_subdev(&viu_dev->v4l2_dev, ad, + "saa7113", VIU_VIDEO_DECODER_ADDR, NULL); + + timer_setup(&viu_dev->vidq.timeout, viu_vid_timeout, 0); + viu_dev->std = V4L2_STD_NTSC_M; + viu_dev->first = 1; + + /* Allocate memory for video device */ + vdev = video_device_alloc(); + if (vdev == NULL) { + ret = -ENOMEM; + goto err_hdl; + } + + *vdev = viu_template; + + vdev->v4l2_dev = &viu_dev->v4l2_dev; + + viu_dev->vdev = vdev; + + /* initialize locks */ + mutex_init(&viu_dev->lock); + viu_dev->vdev->lock = &viu_dev->lock; + spin_lock_init(&viu_dev->slock); + + video_set_drvdata(viu_dev->vdev, viu_dev); + + mutex_lock(&viu_dev->lock); + + ret = video_register_device(viu_dev->vdev, VFL_TYPE_VIDEO, -1); + if (ret < 0) { + video_device_release(viu_dev->vdev); + goto err_unlock; + } + + /* enable VIU clock */ + clk = devm_clk_get(&op->dev, "ipg"); + if (IS_ERR(clk)) { + dev_err(&op->dev, "failed to lookup the clock!\n"); + ret = PTR_ERR(clk); + goto err_vdev; + } + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(&op->dev, "failed to enable the clock!\n"); + goto err_vdev; + } + viu_dev->clk = clk; + + /* reset VIU module */ + viu_reset(viu_dev->vr); + + /* install interrupt handler */ + if (request_irq(viu_dev->irq, viu_intr, 0, "viu", (void *)viu_dev)) { + dev_err(&op->dev, "Request VIU IRQ failed.\n"); + ret = -ENODEV; + goto err_clk; + } + + mutex_unlock(&viu_dev->lock); + + dev_info(&op->dev, "Freescale VIU Video Capture Board\n"); + return ret; + +err_clk: + clk_disable_unprepare(viu_dev->clk); +err_vdev: + video_unregister_device(viu_dev->vdev); +err_unlock: + mutex_unlock(&viu_dev->lock); +err_hdl: + v4l2_ctrl_handler_free(&viu_dev->hdl); +err_i2c: + i2c_put_adapter(ad); +err_v4l2: + v4l2_device_unregister(&viu_dev->v4l2_dev); +err_irq: + irq_dispose_mapping(viu_irq); + return ret; +} + +static int viu_of_remove(struct platform_device *op) +{ + struct v4l2_device *v4l2_dev = platform_get_drvdata(op); + struct viu_dev *dev = container_of(v4l2_dev, struct viu_dev, v4l2_dev); + struct v4l2_subdev *sdev = list_entry(v4l2_dev->subdevs.next, + struct v4l2_subdev, list); + struct i2c_client *client = v4l2_get_subdevdata(sdev); + + free_irq(dev->irq, (void *)dev); + irq_dispose_mapping(dev->irq); + + clk_disable_unprepare(dev->clk); + + v4l2_ctrl_handler_free(&dev->hdl); + video_unregister_device(dev->vdev); + i2c_put_adapter(client->adapter); + v4l2_device_unregister(&dev->v4l2_dev); + return 0; +} + +#ifdef CONFIG_PM +static int viu_suspend(struct platform_device *op, pm_message_t state) +{ + struct v4l2_device *v4l2_dev = platform_get_drvdata(op); + struct viu_dev *dev = container_of(v4l2_dev, struct viu_dev, v4l2_dev); + + clk_disable(dev->clk); + return 0; +} + +static int viu_resume(struct platform_device *op) +{ + struct v4l2_device *v4l2_dev = platform_get_drvdata(op); + struct viu_dev *dev = container_of(v4l2_dev, struct viu_dev, v4l2_dev); + + clk_enable(dev->clk); + return 0; +} +#endif + +/* + * Initialization and module stuff + */ +static const struct of_device_id mpc512x_viu_of_match[] = { + { + .compatible = "fsl,mpc5121-viu", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpc512x_viu_of_match); + +static struct platform_driver viu_of_platform_driver = { + .probe = viu_of_probe, + .remove = viu_of_remove, +#ifdef CONFIG_PM + .suspend = viu_suspend, + .resume = viu_resume, +#endif + .driver = { + .name = DRV_NAME, + .of_match_table = mpc512x_viu_of_match, + }, +}; + +module_platform_driver(viu_of_platform_driver); + +MODULE_DESCRIPTION("Freescale Video-In(VIU)"); +MODULE_AUTHOR("Hongjun Chen"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(VIU_VERSION); diff --git a/drivers/staging/media/deprecated/meye/Kconfig b/drivers/staging/media/deprecated/meye/Kconfig new file mode 100644 index 000000000..f135f8568 --- /dev/null +++ b/drivers/staging/media/deprecated/meye/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_MEYE + tristate "Sony Vaio Picturebook Motion Eye Video For Linux (DEPRECATED)" + depends on PCI && VIDEO_DEV + depends on SONY_LAPTOP + depends on X86 || COMPILE_TEST + help + This is the video4linux driver for the Motion Eye camera found + in the Vaio Picturebook laptops. Please read the material in + for more information. + + If you say Y or M here, you need to say Y or M to "Sony Laptop + Extras" in the misc device section. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + To compile this driver as a module, choose M here: the + module will be called meye. diff --git a/drivers/staging/media/deprecated/meye/Makefile b/drivers/staging/media/deprecated/meye/Makefile new file mode 100644 index 000000000..36f1f86f0 --- /dev/null +++ b/drivers/staging/media/deprecated/meye/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_VIDEO_MEYE) += meye.o diff --git a/drivers/staging/media/deprecated/meye/TODO b/drivers/staging/media/deprecated/meye/TODO new file mode 100644 index 000000000..6d1d1433d --- /dev/null +++ b/drivers/staging/media/deprecated/meye/TODO @@ -0,0 +1,6 @@ +The meye driver does not use the vb2 framework for streaming +video, instead it implements this in the driver. + +To prevent removal of this driver early 2023 it has to be +converted to use vb2. Contact the linux-media@vger.kernel.org +mailing list if you want to do this. diff --git a/drivers/staging/media/deprecated/meye/meye.c b/drivers/staging/media/deprecated/meye/meye.c new file mode 100644 index 000000000..5d87efd9b --- /dev/null +++ b/drivers/staging/media/deprecated/meye/meye.c @@ -0,0 +1,1814 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Motion Eye video4linux driver for Sony Vaio PictureBook + * + * Copyright (C) 2001-2004 Stelian Pop + * + * Copyright (C) 2001-2002 Alcôve + * + * Copyright (C) 2000 Andrew Tridgell + * + * Earlier work by Werner Almesberger, Paul `Rusty' Russell and Paul Mackerras. + * + * Some parts borrowed from various video4linux drivers, especially + * bttv-driver.c and zoran.c, see original files for credits. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "meye.h" +#include + +MODULE_AUTHOR("Stelian Pop "); +MODULE_DESCRIPTION("v4l2 driver for the MotionEye camera"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(MEYE_DRIVER_VERSION); + +/* number of grab buffers */ +static unsigned int gbuffers = 2; +module_param(gbuffers, int, 0444); +MODULE_PARM_DESC(gbuffers, "number of capture buffers, default is 2 (32 max)"); + +/* size of a grab buffer */ +static unsigned int gbufsize = MEYE_MAX_BUFSIZE; +module_param(gbufsize, int, 0444); +MODULE_PARM_DESC(gbufsize, "size of the capture buffers, default is 614400 (will be rounded up to a page multiple)"); + +/* /dev/videoX registration number */ +static int video_nr = -1; +module_param(video_nr, int, 0444); +MODULE_PARM_DESC(video_nr, "video device to register (0=/dev/video0, etc)"); + +/* driver structure - only one possible */ +static struct meye meye; + +/****************************************************************************/ +/* Memory allocation routines (stolen from bttv-driver.c) */ +/****************************************************************************/ +static void *rvmalloc(unsigned long size) +{ + void *mem; + unsigned long adr; + + size = PAGE_ALIGN(size); + mem = vmalloc_32(size); + if (mem) { + memset(mem, 0, size); + adr = (unsigned long) mem; + while (size > 0) { + SetPageReserved(vmalloc_to_page((void *)adr)); + adr += PAGE_SIZE; + size -= PAGE_SIZE; + } + } + return mem; +} + +static void rvfree(void * mem, unsigned long size) +{ + unsigned long adr; + + if (mem) { + adr = (unsigned long) mem; + while ((long) size > 0) { + ClearPageReserved(vmalloc_to_page((void *)adr)); + adr += PAGE_SIZE; + size -= PAGE_SIZE; + } + vfree(mem); + } +} + +/* + * return a page table pointing to N pages of locked memory + * + * NOTE: The meye device expects DMA addresses on 32 bits, we build + * a table of 1024 entries = 4 bytes * 1024 = 4096 bytes. + */ +static int ptable_alloc(void) +{ + u32 *pt; + int i; + + memset(meye.mchip_ptable, 0, sizeof(meye.mchip_ptable)); + + /* give only 32 bit DMA addresses */ + if (dma_set_mask(&meye.mchip_dev->dev, DMA_BIT_MASK(32))) + return -1; + + meye.mchip_ptable_toc = dma_alloc_coherent(&meye.mchip_dev->dev, + PAGE_SIZE, + &meye.mchip_dmahandle, + GFP_KERNEL); + if (!meye.mchip_ptable_toc) { + meye.mchip_dmahandle = 0; + return -1; + } + + pt = meye.mchip_ptable_toc; + for (i = 0; i < MCHIP_NB_PAGES; i++) { + dma_addr_t dma; + meye.mchip_ptable[i] = dma_alloc_coherent(&meye.mchip_dev->dev, + PAGE_SIZE, + &dma, + GFP_KERNEL); + if (!meye.mchip_ptable[i]) { + int j; + pt = meye.mchip_ptable_toc; + for (j = 0; j < i; ++j) { + dma = (dma_addr_t) *pt; + dma_free_coherent(&meye.mchip_dev->dev, + PAGE_SIZE, + meye.mchip_ptable[j], dma); + pt++; + } + dma_free_coherent(&meye.mchip_dev->dev, + PAGE_SIZE, + meye.mchip_ptable_toc, + meye.mchip_dmahandle); + meye.mchip_ptable_toc = NULL; + meye.mchip_dmahandle = 0; + return -1; + } + *pt = (u32) dma; + pt++; + } + return 0; +} + +static void ptable_free(void) +{ + u32 *pt; + int i; + + pt = meye.mchip_ptable_toc; + for (i = 0; i < MCHIP_NB_PAGES; i++) { + dma_addr_t dma = (dma_addr_t) *pt; + if (meye.mchip_ptable[i]) + dma_free_coherent(&meye.mchip_dev->dev, + PAGE_SIZE, + meye.mchip_ptable[i], dma); + pt++; + } + + if (meye.mchip_ptable_toc) + dma_free_coherent(&meye.mchip_dev->dev, + PAGE_SIZE, + meye.mchip_ptable_toc, + meye.mchip_dmahandle); + + memset(meye.mchip_ptable, 0, sizeof(meye.mchip_ptable)); + meye.mchip_ptable_toc = NULL; + meye.mchip_dmahandle = 0; +} + +/* copy data from ptable into buf */ +static void ptable_copy(u8 *buf, int start, int size, int pt_pages) +{ + int i; + + for (i = 0; i < (size / PAGE_SIZE) * PAGE_SIZE; i += PAGE_SIZE) { + memcpy(buf + i, meye.mchip_ptable[start++], PAGE_SIZE); + if (start >= pt_pages) + start = 0; + } + memcpy(buf + i, meye.mchip_ptable[start], size % PAGE_SIZE); +} + +/****************************************************************************/ +/* JPEG tables at different qualities to load into the VRJ chip */ +/****************************************************************************/ + +/* return a set of quantisation tables based on a quality from 1 to 10 */ +static u16 *jpeg_quantisation_tables(int *length, int quality) +{ + static u16 jpeg_tables[][70] = { { + 0xdbff, 0x4300, 0xff00, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, + 0xdbff, 0x4300, 0xff01, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, + }, + { + 0xdbff, 0x4300, 0x5000, 0x3c37, 0x3c46, 0x5032, 0x4146, 0x5a46, + 0x5055, 0x785f, 0x82c8, 0x6e78, 0x786e, 0xaff5, 0x91b9, 0xffc8, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, + 0xdbff, 0x4300, 0x5501, 0x5a5a, 0x6978, 0xeb78, 0x8282, 0xffeb, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, + }, + { + 0xdbff, 0x4300, 0x2800, 0x1e1c, 0x1e23, 0x2819, 0x2123, 0x2d23, + 0x282b, 0x3c30, 0x4164, 0x373c, 0x3c37, 0x587b, 0x495d, 0x9164, + 0x9980, 0x8f96, 0x8c80, 0xa08a, 0xe6b4, 0xa0c3, 0xdaaa, 0x8aad, + 0xc88c, 0xcbff, 0xeeda, 0xfff5, 0xffff, 0xc19b, 0xffff, 0xfaff, + 0xe6ff, 0xfffd, 0xfff8, + 0xdbff, 0x4300, 0x2b01, 0x2d2d, 0x353c, 0x763c, 0x4141, 0xf876, + 0x8ca5, 0xf8a5, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, + 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, + 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, 0xf8f8, + 0xf8f8, 0xf8f8, 0xfff8, + }, + { + 0xdbff, 0x4300, 0x1b00, 0x1412, 0x1417, 0x1b11, 0x1617, 0x1e17, + 0x1b1c, 0x2820, 0x2b42, 0x2528, 0x2825, 0x3a51, 0x303d, 0x6042, + 0x6555, 0x5f64, 0x5d55, 0x6a5b, 0x9978, 0x6a81, 0x9071, 0x5b73, + 0x855d, 0x86b5, 0x9e90, 0xaba3, 0xabad, 0x8067, 0xc9bc, 0xa6ba, + 0x99c7, 0xaba8, 0xffa4, + 0xdbff, 0x4300, 0x1c01, 0x1e1e, 0x2328, 0x4e28, 0x2b2b, 0xa44e, + 0x5d6e, 0xa46e, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, + 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, + 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, + 0xa4a4, 0xa4a4, 0xffa4, + }, + { + 0xdbff, 0x4300, 0x1400, 0x0f0e, 0x0f12, 0x140d, 0x1012, 0x1712, + 0x1415, 0x1e18, 0x2132, 0x1c1e, 0x1e1c, 0x2c3d, 0x242e, 0x4932, + 0x4c40, 0x474b, 0x4640, 0x5045, 0x735a, 0x5062, 0x6d55, 0x4556, + 0x6446, 0x6588, 0x776d, 0x817b, 0x8182, 0x604e, 0x978d, 0x7d8c, + 0x7396, 0x817e, 0xff7c, + 0xdbff, 0x4300, 0x1501, 0x1717, 0x1a1e, 0x3b1e, 0x2121, 0x7c3b, + 0x4653, 0x7c53, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, + 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, + 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, 0x7c7c, + 0x7c7c, 0x7c7c, 0xff7c, + }, + { + 0xdbff, 0x4300, 0x1000, 0x0c0b, 0x0c0e, 0x100a, 0x0d0e, 0x120e, + 0x1011, 0x1813, 0x1a28, 0x1618, 0x1816, 0x2331, 0x1d25, 0x3a28, + 0x3d33, 0x393c, 0x3833, 0x4037, 0x5c48, 0x404e, 0x5744, 0x3745, + 0x5038, 0x516d, 0x5f57, 0x6762, 0x6768, 0x4d3e, 0x7971, 0x6470, + 0x5c78, 0x6765, 0xff63, + 0xdbff, 0x4300, 0x1101, 0x1212, 0x1518, 0x2f18, 0x1a1a, 0x632f, + 0x3842, 0x6342, 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, + 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, + 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, 0x6363, + 0x6363, 0x6363, 0xff63, + }, + { + 0xdbff, 0x4300, 0x0d00, 0x0a09, 0x0a0b, 0x0d08, 0x0a0b, 0x0e0b, + 0x0d0e, 0x130f, 0x1520, 0x1213, 0x1312, 0x1c27, 0x171e, 0x2e20, + 0x3129, 0x2e30, 0x2d29, 0x332c, 0x4a3a, 0x333e, 0x4636, 0x2c37, + 0x402d, 0x4157, 0x4c46, 0x524e, 0x5253, 0x3e32, 0x615a, 0x505a, + 0x4a60, 0x5251, 0xff4f, + 0xdbff, 0x4300, 0x0e01, 0x0e0e, 0x1113, 0x2613, 0x1515, 0x4f26, + 0x2d35, 0x4f35, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, + 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, + 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, 0x4f4f, + 0x4f4f, 0x4f4f, 0xff4f, + }, + { + 0xdbff, 0x4300, 0x0a00, 0x0707, 0x0708, 0x0a06, 0x0808, 0x0b08, + 0x0a0a, 0x0e0b, 0x1018, 0x0d0e, 0x0e0d, 0x151d, 0x1116, 0x2318, + 0x251f, 0x2224, 0x221f, 0x2621, 0x372b, 0x262f, 0x3429, 0x2129, + 0x3022, 0x3141, 0x3934, 0x3e3b, 0x3e3e, 0x2e25, 0x4944, 0x3c43, + 0x3748, 0x3e3d, 0xff3b, + 0xdbff, 0x4300, 0x0a01, 0x0b0b, 0x0d0e, 0x1c0e, 0x1010, 0x3b1c, + 0x2228, 0x3b28, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, + 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, + 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, 0x3b3b, + 0x3b3b, 0x3b3b, 0xff3b, + }, + { + 0xdbff, 0x4300, 0x0600, 0x0504, 0x0506, 0x0604, 0x0506, 0x0706, + 0x0607, 0x0a08, 0x0a10, 0x090a, 0x0a09, 0x0e14, 0x0c0f, 0x1710, + 0x1814, 0x1718, 0x1614, 0x1a16, 0x251d, 0x1a1f, 0x231b, 0x161c, + 0x2016, 0x202c, 0x2623, 0x2927, 0x292a, 0x1f19, 0x302d, 0x282d, + 0x2530, 0x2928, 0xff28, + 0xdbff, 0x4300, 0x0701, 0x0707, 0x080a, 0x130a, 0x0a0a, 0x2813, + 0x161a, 0x281a, 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, + 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, + 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, 0x2828, + 0x2828, 0x2828, 0xff28, + }, + { + 0xdbff, 0x4300, 0x0300, 0x0202, 0x0203, 0x0302, 0x0303, 0x0403, + 0x0303, 0x0504, 0x0508, 0x0405, 0x0504, 0x070a, 0x0607, 0x0c08, + 0x0c0a, 0x0b0c, 0x0b0a, 0x0d0b, 0x120e, 0x0d10, 0x110e, 0x0b0e, + 0x100b, 0x1016, 0x1311, 0x1514, 0x1515, 0x0f0c, 0x1817, 0x1416, + 0x1218, 0x1514, 0xff14, + 0xdbff, 0x4300, 0x0301, 0x0404, 0x0405, 0x0905, 0x0505, 0x1409, + 0x0b0d, 0x140d, 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, + 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, + 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, 0x1414, + 0x1414, 0x1414, 0xff14, + }, + { + 0xdbff, 0x4300, 0x0100, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0101, 0x0101, 0xff01, + 0xdbff, 0x4300, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0101, 0x0101, 0xff01, + } }; + + if (quality < 0 || quality > 10) { + printk(KERN_WARNING + "meye: invalid quality level %d - using 8\n", quality); + quality = 8; + } + + *length = ARRAY_SIZE(jpeg_tables[quality]); + return jpeg_tables[quality]; +} + +/* return a generic set of huffman tables */ +static u16 *jpeg_huffman_tables(int *length) +{ + static u16 tables[] = { + 0xC4FF, 0xB500, 0x0010, 0x0102, 0x0303, 0x0402, 0x0503, 0x0405, + 0x0004, 0x0100, 0x017D, 0x0302, 0x0400, 0x0511, 0x2112, 0x4131, + 0x1306, 0x6151, 0x2207, 0x1471, 0x8132, 0xA191, 0x2308, 0xB142, + 0x15C1, 0xD152, 0x24F0, 0x6233, 0x8272, 0x0A09, 0x1716, 0x1918, + 0x251A, 0x2726, 0x2928, 0x342A, 0x3635, 0x3837, 0x3A39, 0x4443, + 0x4645, 0x4847, 0x4A49, 0x5453, 0x5655, 0x5857, 0x5A59, 0x6463, + 0x6665, 0x6867, 0x6A69, 0x7473, 0x7675, 0x7877, 0x7A79, 0x8483, + 0x8685, 0x8887, 0x8A89, 0x9392, 0x9594, 0x9796, 0x9998, 0xA29A, + 0xA4A3, 0xA6A5, 0xA8A7, 0xAAA9, 0xB3B2, 0xB5B4, 0xB7B6, 0xB9B8, + 0xC2BA, 0xC4C3, 0xC6C5, 0xC8C7, 0xCAC9, 0xD3D2, 0xD5D4, 0xD7D6, + 0xD9D8, 0xE1DA, 0xE3E2, 0xE5E4, 0xE7E6, 0xE9E8, 0xF1EA, 0xF3F2, + 0xF5F4, 0xF7F6, 0xF9F8, 0xFFFA, + 0xC4FF, 0xB500, 0x0011, 0x0102, 0x0402, 0x0304, 0x0704, 0x0405, + 0x0004, 0x0201, 0x0077, 0x0201, 0x1103, 0x0504, 0x3121, 0x1206, + 0x5141, 0x6107, 0x1371, 0x3222, 0x0881, 0x4214, 0xA191, 0xC1B1, + 0x2309, 0x5233, 0x15F0, 0x7262, 0x0AD1, 0x2416, 0xE134, 0xF125, + 0x1817, 0x1A19, 0x2726, 0x2928, 0x352A, 0x3736, 0x3938, 0x433A, + 0x4544, 0x4746, 0x4948, 0x534A, 0x5554, 0x5756, 0x5958, 0x635A, + 0x6564, 0x6766, 0x6968, 0x736A, 0x7574, 0x7776, 0x7978, 0x827A, + 0x8483, 0x8685, 0x8887, 0x8A89, 0x9392, 0x9594, 0x9796, 0x9998, + 0xA29A, 0xA4A3, 0xA6A5, 0xA8A7, 0xAAA9, 0xB3B2, 0xB5B4, 0xB7B6, + 0xB9B8, 0xC2BA, 0xC4C3, 0xC6C5, 0xC8C7, 0xCAC9, 0xD3D2, 0xD5D4, + 0xD7D6, 0xD9D8, 0xE2DA, 0xE4E3, 0xE6E5, 0xE8E7, 0xEAE9, 0xF3F2, + 0xF5F4, 0xF7F6, 0xF9F8, 0xFFFA, + 0xC4FF, 0x1F00, 0x0000, 0x0501, 0x0101, 0x0101, 0x0101, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0201, 0x0403, 0x0605, 0x0807, 0x0A09, + 0xFF0B, + 0xC4FF, 0x1F00, 0x0001, 0x0103, 0x0101, 0x0101, 0x0101, 0x0101, + 0x0000, 0x0000, 0x0000, 0x0201, 0x0403, 0x0605, 0x0807, 0x0A09, + 0xFF0B + }; + + *length = ARRAY_SIZE(tables); + return tables; +} + +/****************************************************************************/ +/* MCHIP low-level functions */ +/****************************************************************************/ + +/* returns the horizontal capture size */ +static inline int mchip_hsize(void) +{ + return meye.params.subsample ? 320 : 640; +} + +/* returns the vertical capture size */ +static inline int mchip_vsize(void) +{ + return meye.params.subsample ? 240 : 480; +} + +/* waits for a register to be available */ +static void mchip_sync(int reg) +{ + u32 status; + int i; + + if (reg == MCHIP_MM_FIFO_DATA) { + for (i = 0; i < MCHIP_REG_TIMEOUT; i++) { + status = readl(meye.mchip_mmregs + + MCHIP_MM_FIFO_STATUS); + if (!(status & MCHIP_MM_FIFO_WAIT)) { + printk(KERN_WARNING "meye: fifo not ready\n"); + return; + } + if (status & MCHIP_MM_FIFO_READY) + return; + udelay(1); + } + } else if (reg > 0x80) { + u32 mask = (reg < 0x100) ? MCHIP_HIC_STATUS_MCC_RDY + : MCHIP_HIC_STATUS_VRJ_RDY; + for (i = 0; i < MCHIP_REG_TIMEOUT; i++) { + status = readl(meye.mchip_mmregs + MCHIP_HIC_STATUS); + if (status & mask) + return; + udelay(1); + } + } else + return; + printk(KERN_WARNING + "meye: mchip_sync() timeout on reg 0x%x status=0x%x\n", + reg, status); +} + +/* sets a value into the register */ +static inline void mchip_set(int reg, u32 v) +{ + mchip_sync(reg); + writel(v, meye.mchip_mmregs + reg); +} + +/* get the register value */ +static inline u32 mchip_read(int reg) +{ + mchip_sync(reg); + return readl(meye.mchip_mmregs + reg); +} + +/* wait for a register to become a particular value */ +static inline int mchip_delay(u32 reg, u32 v) +{ + int n = 10; + while (--n && mchip_read(reg) != v) + udelay(1); + return n; +} + +/* setup subsampling */ +static void mchip_subsample(void) +{ + mchip_set(MCHIP_MCC_R_SAMPLING, meye.params.subsample); + mchip_set(MCHIP_MCC_R_XRANGE, mchip_hsize()); + mchip_set(MCHIP_MCC_R_YRANGE, mchip_vsize()); + mchip_set(MCHIP_MCC_B_XRANGE, mchip_hsize()); + mchip_set(MCHIP_MCC_B_YRANGE, mchip_vsize()); + mchip_delay(MCHIP_HIC_STATUS, MCHIP_HIC_STATUS_IDLE); +} + +/* set the framerate into the mchip */ +static void mchip_set_framerate(void) +{ + mchip_set(MCHIP_HIC_S_RATE, meye.params.framerate); +} + +/* load some huffman and quantisation tables into the VRJ chip ready + for JPEG compression */ +static void mchip_load_tables(void) +{ + int i; + int length; + u16 *tables; + + tables = jpeg_huffman_tables(&length); + for (i = 0; i < length; i++) + writel(tables[i], meye.mchip_mmregs + MCHIP_VRJ_TABLE_DATA); + + tables = jpeg_quantisation_tables(&length, meye.params.quality); + for (i = 0; i < length; i++) + writel(tables[i], meye.mchip_mmregs + MCHIP_VRJ_TABLE_DATA); +} + +/* setup the VRJ parameters in the chip */ +static void mchip_vrj_setup(u8 mode) +{ + mchip_set(MCHIP_VRJ_BUS_MODE, 5); + mchip_set(MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL, 0x1f); + mchip_set(MCHIP_VRJ_PDAT_USE, 1); + mchip_set(MCHIP_VRJ_IRQ_FLAG, 0xa0); + mchip_set(MCHIP_VRJ_MODE_SPECIFY, mode); + mchip_set(MCHIP_VRJ_NUM_LINES, mchip_vsize()); + mchip_set(MCHIP_VRJ_NUM_PIXELS, mchip_hsize()); + mchip_set(MCHIP_VRJ_NUM_COMPONENTS, 0x1b); + mchip_set(MCHIP_VRJ_LIMIT_COMPRESSED_LO, 0xFFFF); + mchip_set(MCHIP_VRJ_LIMIT_COMPRESSED_HI, 0xFFFF); + mchip_set(MCHIP_VRJ_COMP_DATA_FORMAT, 0xC); + mchip_set(MCHIP_VRJ_RESTART_INTERVAL, 0); + mchip_set(MCHIP_VRJ_SOF1, 0x601); + mchip_set(MCHIP_VRJ_SOF2, 0x1502); + mchip_set(MCHIP_VRJ_SOF3, 0x1503); + mchip_set(MCHIP_VRJ_SOF4, 0x1596); + mchip_set(MCHIP_VRJ_SOS, 0x0ed0); + + mchip_load_tables(); +} + +/* sets the DMA parameters into the chip */ +static void mchip_dma_setup(dma_addr_t dma_addr) +{ + int i; + + mchip_set(MCHIP_MM_PT_ADDR, (u32)dma_addr); + for (i = 0; i < 4; i++) + mchip_set(MCHIP_MM_FIR(i), 0); + meye.mchip_fnum = 0; +} + +/* setup for DMA transfers - also zeros the framebuffer */ +static int mchip_dma_alloc(void) +{ + if (!meye.mchip_dmahandle) + if (ptable_alloc()) + return -1; + return 0; +} + +/* frees the DMA buffer */ +static void mchip_dma_free(void) +{ + if (meye.mchip_dmahandle) { + mchip_dma_setup(0); + ptable_free(); + } +} + +/* stop any existing HIC action and wait for any dma to complete then + reset the dma engine */ +static void mchip_hic_stop(void) +{ + int i, j; + + meye.mchip_mode = MCHIP_HIC_MODE_NOOP; + if (!(mchip_read(MCHIP_HIC_STATUS) & MCHIP_HIC_STATUS_BUSY)) + return; + for (i = 0; i < 20; ++i) { + mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_STOP); + mchip_delay(MCHIP_HIC_CMD, 0); + for (j = 0; j < 100; ++j) { + if (mchip_delay(MCHIP_HIC_STATUS, + MCHIP_HIC_STATUS_IDLE)) + return; + msleep(1); + } + printk(KERN_ERR "meye: need to reset HIC!\n"); + + mchip_set(MCHIP_HIC_CTL, MCHIP_HIC_CTL_SOFT_RESET); + msleep(250); + } + printk(KERN_ERR "meye: resetting HIC hanged!\n"); +} + +/****************************************************************************/ +/* MCHIP frame processing functions */ +/****************************************************************************/ + +/* get the next ready frame from the dma engine */ +static u32 mchip_get_frame(void) +{ + return mchip_read(MCHIP_MM_FIR(meye.mchip_fnum)); +} + +/* frees the current frame from the dma engine */ +static void mchip_free_frame(void) +{ + mchip_set(MCHIP_MM_FIR(meye.mchip_fnum), 0); + meye.mchip_fnum++; + meye.mchip_fnum %= 4; +} + +/* read one frame from the framebuffer assuming it was captured using + a uncompressed transfer */ +static void mchip_cont_read_frame(u32 v, u8 *buf, int size) +{ + int pt_id; + + pt_id = (v >> 17) & 0x3FF; + + ptable_copy(buf, pt_id, size, MCHIP_NB_PAGES); +} + +/* read a compressed frame from the framebuffer */ +static int mchip_comp_read_frame(u32 v, u8 *buf, int size) +{ + int pt_start, pt_end, trailer; + int fsize; + int i; + + pt_start = (v >> 19) & 0xFF; + pt_end = (v >> 11) & 0xFF; + trailer = (v >> 1) & 0x3FF; + + if (pt_end < pt_start) + fsize = (MCHIP_NB_PAGES_MJPEG - pt_start) * PAGE_SIZE + + pt_end * PAGE_SIZE + trailer * 4; + else + fsize = (pt_end - pt_start) * PAGE_SIZE + trailer * 4; + + if (fsize > size) { + printk(KERN_WARNING "meye: oversized compressed frame %d\n", + fsize); + return -1; + } + + ptable_copy(buf, pt_start, fsize, MCHIP_NB_PAGES_MJPEG); + +#ifdef MEYE_JPEG_CORRECTION + + /* Some mchip generated jpeg frames are incorrect. In most + * (all ?) of those cases, the final EOI (0xff 0xd9) marker + * is not present at the end of the frame. + * + * Since adding the final marker is not enough to restore + * the jpeg integrity, we drop the frame. + */ + + for (i = fsize - 1; i > 0 && buf[i] == 0xff; i--) ; + + if (i < 2 || buf[i - 1] != 0xff || buf[i] != 0xd9) + return -1; + +#endif + + return fsize; +} + +/* take a picture into SDRAM */ +static void mchip_take_picture(void) +{ + int i; + + mchip_hic_stop(); + mchip_subsample(); + mchip_dma_setup(meye.mchip_dmahandle); + + mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_STILL_CAP); + mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START); + + mchip_delay(MCHIP_HIC_CMD, 0); + + for (i = 0; i < 100; ++i) { + if (mchip_delay(MCHIP_HIC_STATUS, MCHIP_HIC_STATUS_IDLE)) + break; + msleep(1); + } +} + +/* dma a previously taken picture into a buffer */ +static void mchip_get_picture(u8 *buf, int bufsize) +{ + u32 v; + int i; + + mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_STILL_OUT); + mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START); + + mchip_delay(MCHIP_HIC_CMD, 0); + for (i = 0; i < 100; ++i) { + if (mchip_delay(MCHIP_HIC_STATUS, MCHIP_HIC_STATUS_IDLE)) + break; + msleep(1); + } + for (i = 0; i < 4; ++i) { + v = mchip_get_frame(); + if (v & MCHIP_MM_FIR_RDY) { + mchip_cont_read_frame(v, buf, bufsize); + break; + } + mchip_free_frame(); + } +} + +/* start continuous dma capture */ +static void mchip_continuous_start(void) +{ + mchip_hic_stop(); + mchip_subsample(); + mchip_set_framerate(); + mchip_dma_setup(meye.mchip_dmahandle); + + meye.mchip_mode = MCHIP_HIC_MODE_CONT_OUT; + + mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_CONT_OUT); + mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START); + + mchip_delay(MCHIP_HIC_CMD, 0); +} + +/* compress one frame into a buffer */ +static int mchip_compress_frame(u8 *buf, int bufsize) +{ + u32 v; + int len = -1, i; + + mchip_vrj_setup(0x3f); + udelay(50); + + mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_STILL_COMP); + mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START); + + mchip_delay(MCHIP_HIC_CMD, 0); + for (i = 0; i < 100; ++i) { + if (mchip_delay(MCHIP_HIC_STATUS, MCHIP_HIC_STATUS_IDLE)) + break; + msleep(1); + } + + for (i = 0; i < 4; ++i) { + v = mchip_get_frame(); + if (v & MCHIP_MM_FIR_RDY) { + len = mchip_comp_read_frame(v, buf, bufsize); + break; + } + mchip_free_frame(); + } + return len; +} + +#if 0 +/* uncompress one image into a buffer */ +static int mchip_uncompress_frame(u8 *img, int imgsize, u8 *buf, int bufsize) +{ + mchip_vrj_setup(0x3f); + udelay(50); + + mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_STILL_DECOMP); + mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START); + + mchip_delay(MCHIP_HIC_CMD, 0); + + return mchip_comp_read_frame(buf, bufsize); +} +#endif + +/* start continuous compressed capture */ +static void mchip_cont_compression_start(void) +{ + mchip_hic_stop(); + mchip_vrj_setup(0x3f); + mchip_subsample(); + mchip_set_framerate(); + mchip_dma_setup(meye.mchip_dmahandle); + + meye.mchip_mode = MCHIP_HIC_MODE_CONT_COMP; + + mchip_set(MCHIP_HIC_MODE, MCHIP_HIC_MODE_CONT_COMP); + mchip_set(MCHIP_HIC_CMD, MCHIP_HIC_CMD_START); + + mchip_delay(MCHIP_HIC_CMD, 0); +} + +/****************************************************************************/ +/* Interrupt handling */ +/****************************************************************************/ + +static irqreturn_t meye_irq(int irq, void *dev_id) +{ + u32 v; + int reqnr; + static int sequence; + + v = mchip_read(MCHIP_MM_INTA); + + if (meye.mchip_mode != MCHIP_HIC_MODE_CONT_OUT && + meye.mchip_mode != MCHIP_HIC_MODE_CONT_COMP) + return IRQ_NONE; + +again: + v = mchip_get_frame(); + if (!(v & MCHIP_MM_FIR_RDY)) + return IRQ_HANDLED; + + if (meye.mchip_mode == MCHIP_HIC_MODE_CONT_OUT) { + if (kfifo_out_locked(&meye.grabq, (unsigned char *)&reqnr, + sizeof(int), &meye.grabq_lock) != sizeof(int)) { + mchip_free_frame(); + return IRQ_HANDLED; + } + mchip_cont_read_frame(v, meye.grab_fbuffer + gbufsize * reqnr, + mchip_hsize() * mchip_vsize() * 2); + meye.grab_buffer[reqnr].size = mchip_hsize() * mchip_vsize() * 2; + meye.grab_buffer[reqnr].state = MEYE_BUF_DONE; + meye.grab_buffer[reqnr].ts = ktime_get_ns(); + meye.grab_buffer[reqnr].sequence = sequence++; + kfifo_in_locked(&meye.doneq, (unsigned char *)&reqnr, + sizeof(int), &meye.doneq_lock); + wake_up_interruptible(&meye.proc_list); + } else { + int size; + size = mchip_comp_read_frame(v, meye.grab_temp, gbufsize); + if (size == -1) { + mchip_free_frame(); + goto again; + } + if (kfifo_out_locked(&meye.grabq, (unsigned char *)&reqnr, + sizeof(int), &meye.grabq_lock) != sizeof(int)) { + mchip_free_frame(); + goto again; + } + memcpy(meye.grab_fbuffer + gbufsize * reqnr, meye.grab_temp, + size); + meye.grab_buffer[reqnr].size = size; + meye.grab_buffer[reqnr].state = MEYE_BUF_DONE; + meye.grab_buffer[reqnr].ts = ktime_get_ns(); + meye.grab_buffer[reqnr].sequence = sequence++; + kfifo_in_locked(&meye.doneq, (unsigned char *)&reqnr, + sizeof(int), &meye.doneq_lock); + wake_up_interruptible(&meye.proc_list); + } + mchip_free_frame(); + goto again; +} + +/****************************************************************************/ +/* video4linux integration */ +/****************************************************************************/ + +static int meye_open(struct file *file) +{ + int i; + + if (test_and_set_bit(0, &meye.in_use)) + return -EBUSY; + + mchip_hic_stop(); + + if (mchip_dma_alloc()) { + printk(KERN_ERR "meye: mchip framebuffer allocation failed\n"); + clear_bit(0, &meye.in_use); + return -ENOBUFS; + } + + for (i = 0; i < MEYE_MAX_BUFNBRS; i++) + meye.grab_buffer[i].state = MEYE_BUF_UNUSED; + kfifo_reset(&meye.grabq); + kfifo_reset(&meye.doneq); + return v4l2_fh_open(file); +} + +static int meye_release(struct file *file) +{ + mchip_hic_stop(); + mchip_dma_free(); + clear_bit(0, &meye.in_use); + return v4l2_fh_release(file); +} + +static int meyeioc_g_params(struct meye_params *p) +{ + *p = meye.params; + return 0; +} + +static int meyeioc_s_params(struct meye_params *jp) +{ + if (jp->subsample > 1) + return -EINVAL; + + if (jp->quality > 10) + return -EINVAL; + + if (jp->sharpness > 63 || jp->agc > 63 || jp->picture > 63) + return -EINVAL; + + if (jp->framerate > 31) + return -EINVAL; + + mutex_lock(&meye.lock); + + if (meye.params.subsample != jp->subsample || + meye.params.quality != jp->quality) + mchip_hic_stop(); /* need restart */ + + meye.params = *jp; + sony_pic_camera_command(SONY_PIC_COMMAND_SETCAMERASHARPNESS, + meye.params.sharpness); + sony_pic_camera_command(SONY_PIC_COMMAND_SETCAMERAAGC, + meye.params.agc); + sony_pic_camera_command(SONY_PIC_COMMAND_SETCAMERAPICTURE, + meye.params.picture); + mutex_unlock(&meye.lock); + + return 0; +} + +static int meyeioc_qbuf_capt(int *nb) +{ + if (!meye.grab_fbuffer) + return -EINVAL; + + if (*nb >= gbuffers) + return -EINVAL; + + if (*nb < 0) { + /* stop capture */ + mchip_hic_stop(); + return 0; + } + + if (meye.grab_buffer[*nb].state != MEYE_BUF_UNUSED) + return -EBUSY; + + mutex_lock(&meye.lock); + + if (meye.mchip_mode != MCHIP_HIC_MODE_CONT_COMP) + mchip_cont_compression_start(); + + meye.grab_buffer[*nb].state = MEYE_BUF_USING; + kfifo_in_locked(&meye.grabq, (unsigned char *)nb, sizeof(int), + &meye.grabq_lock); + mutex_unlock(&meye.lock); + + return 0; +} + +static int meyeioc_sync(struct file *file, void *fh, int *i) +{ + int unused; + + if (*i < 0 || *i >= gbuffers) + return -EINVAL; + + mutex_lock(&meye.lock); + switch (meye.grab_buffer[*i].state) { + + case MEYE_BUF_UNUSED: + mutex_unlock(&meye.lock); + return -EINVAL; + case MEYE_BUF_USING: + if (file->f_flags & O_NONBLOCK) { + mutex_unlock(&meye.lock); + return -EAGAIN; + } + if (wait_event_interruptible(meye.proc_list, + (meye.grab_buffer[*i].state != MEYE_BUF_USING))) { + mutex_unlock(&meye.lock); + return -EINTR; + } + fallthrough; + case MEYE_BUF_DONE: + meye.grab_buffer[*i].state = MEYE_BUF_UNUSED; + if (kfifo_out_locked(&meye.doneq, (unsigned char *)&unused, + sizeof(int), &meye.doneq_lock) != sizeof(int)) + break; + } + *i = meye.grab_buffer[*i].size; + mutex_unlock(&meye.lock); + return 0; +} + +static int meyeioc_stillcapt(void) +{ + if (!meye.grab_fbuffer) + return -EINVAL; + + if (meye.grab_buffer[0].state != MEYE_BUF_UNUSED) + return -EBUSY; + + mutex_lock(&meye.lock); + meye.grab_buffer[0].state = MEYE_BUF_USING; + mchip_take_picture(); + + mchip_get_picture(meye.grab_fbuffer, + mchip_hsize() * mchip_vsize() * 2); + + meye.grab_buffer[0].state = MEYE_BUF_DONE; + mutex_unlock(&meye.lock); + + return 0; +} + +static int meyeioc_stilljcapt(int *len) +{ + if (!meye.grab_fbuffer) + return -EINVAL; + + if (meye.grab_buffer[0].state != MEYE_BUF_UNUSED) + return -EBUSY; + + mutex_lock(&meye.lock); + meye.grab_buffer[0].state = MEYE_BUF_USING; + *len = -1; + + while (*len == -1) { + mchip_take_picture(); + *len = mchip_compress_frame(meye.grab_fbuffer, gbufsize); + } + + meye.grab_buffer[0].state = MEYE_BUF_DONE; + mutex_unlock(&meye.lock); + return 0; +} + +static int vidioc_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + strscpy(cap->driver, "meye", sizeof(cap->driver)); + strscpy(cap->card, "meye", sizeof(cap->card)); + return 0; +} + +static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i) +{ + if (i->index != 0) + return -EINVAL; + + strscpy(i->name, "Camera", sizeof(i->name)); + i->type = V4L2_INPUT_TYPE_CAMERA; + + return 0; +} + +static int vidioc_g_input(struct file *file, void *fh, unsigned int *i) +{ + *i = 0; + return 0; +} + +static int vidioc_s_input(struct file *file, void *fh, unsigned int i) +{ + if (i != 0) + return -EINVAL; + + return 0; +} + +static int meye_s_ctrl(struct v4l2_ctrl *ctrl) +{ + mutex_lock(&meye.lock); + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + sony_pic_camera_command( + SONY_PIC_COMMAND_SETCAMERABRIGHTNESS, ctrl->val); + meye.brightness = ctrl->val << 10; + break; + case V4L2_CID_HUE: + sony_pic_camera_command( + SONY_PIC_COMMAND_SETCAMERAHUE, ctrl->val); + meye.hue = ctrl->val << 10; + break; + case V4L2_CID_CONTRAST: + sony_pic_camera_command( + SONY_PIC_COMMAND_SETCAMERACONTRAST, ctrl->val); + meye.contrast = ctrl->val << 10; + break; + case V4L2_CID_SATURATION: + sony_pic_camera_command( + SONY_PIC_COMMAND_SETCAMERACOLOR, ctrl->val); + meye.colour = ctrl->val << 10; + break; + case V4L2_CID_MEYE_AGC: + sony_pic_camera_command( + SONY_PIC_COMMAND_SETCAMERAAGC, ctrl->val); + meye.params.agc = ctrl->val; + break; + case V4L2_CID_SHARPNESS: + sony_pic_camera_command( + SONY_PIC_COMMAND_SETCAMERASHARPNESS, ctrl->val); + meye.params.sharpness = ctrl->val; + break; + case V4L2_CID_MEYE_PICTURE: + sony_pic_camera_command( + SONY_PIC_COMMAND_SETCAMERAPICTURE, ctrl->val); + meye.params.picture = ctrl->val; + break; + case V4L2_CID_JPEG_COMPRESSION_QUALITY: + meye.params.quality = ctrl->val; + break; + case V4L2_CID_MEYE_FRAMERATE: + meye.params.framerate = ctrl->val; + break; + default: + mutex_unlock(&meye.lock); + return -EINVAL; + } + mutex_unlock(&meye.lock); + + return 0; +} + +static int vidioc_enum_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_fmtdesc *f) +{ + if (f->index > 1) + return -EINVAL; + + if (f->index == 0) { + /* standard YUV 422 capture */ + f->flags = 0; + f->pixelformat = V4L2_PIX_FMT_YUYV; + } else { + /* compressed MJPEG capture */ + f->pixelformat = V4L2_PIX_FMT_MJPEG; + } + + return 0; +} + +static int vidioc_try_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_YUYV && + f->fmt.pix.pixelformat != V4L2_PIX_FMT_MJPEG) + return -EINVAL; + + if (f->fmt.pix.field != V4L2_FIELD_ANY && + f->fmt.pix.field != V4L2_FIELD_NONE) + return -EINVAL; + + f->fmt.pix.field = V4L2_FIELD_NONE; + + if (f->fmt.pix.width <= 320) { + f->fmt.pix.width = 320; + f->fmt.pix.height = 240; + } else { + f->fmt.pix.width = 640; + f->fmt.pix.height = 480; + } + + f->fmt.pix.bytesperline = f->fmt.pix.width * 2; + f->fmt.pix.sizeimage = f->fmt.pix.height * + f->fmt.pix.bytesperline; + f->fmt.pix.colorspace = 0; + + return 0; +} + +static int vidioc_g_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + switch (meye.mchip_mode) { + case MCHIP_HIC_MODE_CONT_OUT: + default: + f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUYV; + break; + case MCHIP_HIC_MODE_CONT_COMP: + f->fmt.pix.pixelformat = V4L2_PIX_FMT_MJPEG; + break; + } + + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.width = mchip_hsize(); + f->fmt.pix.height = mchip_vsize(); + f->fmt.pix.bytesperline = f->fmt.pix.width * 2; + f->fmt.pix.sizeimage = f->fmt.pix.height * + f->fmt.pix.bytesperline; + + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_YUYV && + f->fmt.pix.pixelformat != V4L2_PIX_FMT_MJPEG) + return -EINVAL; + + if (f->fmt.pix.field != V4L2_FIELD_ANY && + f->fmt.pix.field != V4L2_FIELD_NONE) + return -EINVAL; + + f->fmt.pix.field = V4L2_FIELD_NONE; + mutex_lock(&meye.lock); + + if (f->fmt.pix.width <= 320) { + f->fmt.pix.width = 320; + f->fmt.pix.height = 240; + meye.params.subsample = 1; + } else { + f->fmt.pix.width = 640; + f->fmt.pix.height = 480; + meye.params.subsample = 0; + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUYV: + meye.mchip_mode = MCHIP_HIC_MODE_CONT_OUT; + break; + case V4L2_PIX_FMT_MJPEG: + meye.mchip_mode = MCHIP_HIC_MODE_CONT_COMP; + break; + } + + mutex_unlock(&meye.lock); + f->fmt.pix.bytesperline = f->fmt.pix.width * 2; + f->fmt.pix.sizeimage = f->fmt.pix.height * + f->fmt.pix.bytesperline; + f->fmt.pix.colorspace = 0; + + return 0; +} + +static int vidioc_reqbufs(struct file *file, void *fh, + struct v4l2_requestbuffers *req) +{ + int i; + + if (req->memory != V4L2_MEMORY_MMAP) + return -EINVAL; + + if (meye.grab_fbuffer && req->count == gbuffers) { + /* already allocated, no modifications */ + return 0; + } + + mutex_lock(&meye.lock); + if (meye.grab_fbuffer) { + for (i = 0; i < gbuffers; i++) + if (meye.vma_use_count[i]) { + mutex_unlock(&meye.lock); + return -EINVAL; + } + rvfree(meye.grab_fbuffer, gbuffers * gbufsize); + meye.grab_fbuffer = NULL; + } + + gbuffers = max(2, min((int)req->count, MEYE_MAX_BUFNBRS)); + req->count = gbuffers; + meye.grab_fbuffer = rvmalloc(gbuffers * gbufsize); + + if (!meye.grab_fbuffer) { + printk(KERN_ERR "meye: v4l framebuffer allocation failed\n"); + mutex_unlock(&meye.lock); + return -ENOMEM; + } + + for (i = 0; i < gbuffers; i++) + meye.vma_use_count[i] = 0; + + mutex_unlock(&meye.lock); + + return 0; +} + +static int vidioc_querybuf(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + unsigned int index = buf->index; + + if (index >= gbuffers) + return -EINVAL; + + buf->bytesused = meye.grab_buffer[index].size; + buf->flags = V4L2_BUF_FLAG_MAPPED | V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + + if (meye.grab_buffer[index].state == MEYE_BUF_USING) + buf->flags |= V4L2_BUF_FLAG_QUEUED; + + if (meye.grab_buffer[index].state == MEYE_BUF_DONE) + buf->flags |= V4L2_BUF_FLAG_DONE; + + buf->field = V4L2_FIELD_NONE; + v4l2_buffer_set_timestamp(buf, meye.grab_buffer[index].ts); + buf->sequence = meye.grab_buffer[index].sequence; + buf->memory = V4L2_MEMORY_MMAP; + buf->m.offset = index * gbufsize; + buf->length = gbufsize; + + return 0; +} + +static int vidioc_qbuf(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + if (buf->memory != V4L2_MEMORY_MMAP) + return -EINVAL; + + if (buf->index >= gbuffers) + return -EINVAL; + + if (meye.grab_buffer[buf->index].state != MEYE_BUF_UNUSED) + return -EINVAL; + + mutex_lock(&meye.lock); + buf->flags |= V4L2_BUF_FLAG_QUEUED; + buf->flags &= ~V4L2_BUF_FLAG_DONE; + meye.grab_buffer[buf->index].state = MEYE_BUF_USING; + kfifo_in_locked(&meye.grabq, (unsigned char *)&buf->index, + sizeof(int), &meye.grabq_lock); + mutex_unlock(&meye.lock); + + return 0; +} + +static int vidioc_dqbuf(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + int reqnr; + + if (buf->memory != V4L2_MEMORY_MMAP) + return -EINVAL; + + mutex_lock(&meye.lock); + + if (kfifo_len(&meye.doneq) == 0 && file->f_flags & O_NONBLOCK) { + mutex_unlock(&meye.lock); + return -EAGAIN; + } + + if (wait_event_interruptible(meye.proc_list, + kfifo_len(&meye.doneq) != 0) < 0) { + mutex_unlock(&meye.lock); + return -EINTR; + } + + if (!kfifo_out_locked(&meye.doneq, (unsigned char *)&reqnr, + sizeof(int), &meye.doneq_lock)) { + mutex_unlock(&meye.lock); + return -EBUSY; + } + + if (meye.grab_buffer[reqnr].state != MEYE_BUF_DONE) { + mutex_unlock(&meye.lock); + return -EINVAL; + } + + buf->index = reqnr; + buf->bytesused = meye.grab_buffer[reqnr].size; + buf->flags = V4L2_BUF_FLAG_MAPPED | V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + buf->field = V4L2_FIELD_NONE; + v4l2_buffer_set_timestamp(buf, meye.grab_buffer[reqnr].ts); + buf->sequence = meye.grab_buffer[reqnr].sequence; + buf->memory = V4L2_MEMORY_MMAP; + buf->m.offset = reqnr * gbufsize; + buf->length = gbufsize; + meye.grab_buffer[reqnr].state = MEYE_BUF_UNUSED; + mutex_unlock(&meye.lock); + + return 0; +} + +static int vidioc_streamon(struct file *file, void *fh, enum v4l2_buf_type i) +{ + mutex_lock(&meye.lock); + + switch (meye.mchip_mode) { + case MCHIP_HIC_MODE_CONT_OUT: + mchip_continuous_start(); + break; + case MCHIP_HIC_MODE_CONT_COMP: + mchip_cont_compression_start(); + break; + default: + mutex_unlock(&meye.lock); + return -EINVAL; + } + + mutex_unlock(&meye.lock); + + return 0; +} + +static int vidioc_streamoff(struct file *file, void *fh, enum v4l2_buf_type i) +{ + mutex_lock(&meye.lock); + mchip_hic_stop(); + kfifo_reset(&meye.grabq); + kfifo_reset(&meye.doneq); + + for (i = 0; i < MEYE_MAX_BUFNBRS; i++) + meye.grab_buffer[i].state = MEYE_BUF_UNUSED; + + mutex_unlock(&meye.lock); + return 0; +} + +static long vidioc_default(struct file *file, void *fh, bool valid_prio, + unsigned int cmd, void *arg) +{ + switch (cmd) { + case MEYEIOC_G_PARAMS: + return meyeioc_g_params((struct meye_params *) arg); + + case MEYEIOC_S_PARAMS: + return meyeioc_s_params((struct meye_params *) arg); + + case MEYEIOC_QBUF_CAPT: + return meyeioc_qbuf_capt((int *) arg); + + case MEYEIOC_SYNC: + return meyeioc_sync(file, fh, (int *) arg); + + case MEYEIOC_STILLCAPT: + return meyeioc_stillcapt(); + + case MEYEIOC_STILLJCAPT: + return meyeioc_stilljcapt((int *) arg); + + default: + return -ENOTTY; + } + +} + +static __poll_t meye_poll(struct file *file, poll_table *wait) +{ + __poll_t res = v4l2_ctrl_poll(file, wait); + + mutex_lock(&meye.lock); + poll_wait(file, &meye.proc_list, wait); + if (kfifo_len(&meye.doneq)) + res |= EPOLLIN | EPOLLRDNORM; + mutex_unlock(&meye.lock); + return res; +} + +static void meye_vm_open(struct vm_area_struct *vma) +{ + long idx = (long)vma->vm_private_data; + meye.vma_use_count[idx]++; +} + +static void meye_vm_close(struct vm_area_struct *vma) +{ + long idx = (long)vma->vm_private_data; + meye.vma_use_count[idx]--; +} + +static const struct vm_operations_struct meye_vm_ops = { + .open = meye_vm_open, + .close = meye_vm_close, +}; + +static int meye_mmap(struct file *file, struct vm_area_struct *vma) +{ + unsigned long start = vma->vm_start; + unsigned long size = vma->vm_end - vma->vm_start; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + unsigned long page, pos; + + mutex_lock(&meye.lock); + if (size > gbuffers * gbufsize || offset > gbuffers * gbufsize - size) { + mutex_unlock(&meye.lock); + return -EINVAL; + } + if (!meye.grab_fbuffer) { + int i; + + /* lazy allocation */ + meye.grab_fbuffer = rvmalloc(gbuffers*gbufsize); + if (!meye.grab_fbuffer) { + printk(KERN_ERR "meye: v4l framebuffer allocation failed\n"); + mutex_unlock(&meye.lock); + return -ENOMEM; + } + for (i = 0; i < gbuffers; i++) + meye.vma_use_count[i] = 0; + } + pos = (unsigned long)meye.grab_fbuffer + offset; + + while (size > 0) { + page = vmalloc_to_pfn((void *)pos); + if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED)) { + mutex_unlock(&meye.lock); + return -EAGAIN; + } + start += PAGE_SIZE; + pos += PAGE_SIZE; + if (size > PAGE_SIZE) + size -= PAGE_SIZE; + else + size = 0; + } + + vma->vm_ops = &meye_vm_ops; + vma->vm_flags &= ~VM_IO; /* not I/O memory */ + vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_private_data = (void *) (offset / gbufsize); + meye_vm_open(vma); + + mutex_unlock(&meye.lock); + return 0; +} + +static const struct v4l2_file_operations meye_fops = { + .owner = THIS_MODULE, + .open = meye_open, + .release = meye_release, + .mmap = meye_mmap, + .unlocked_ioctl = video_ioctl2, + .poll = meye_poll, +}; + +static const struct v4l2_ioctl_ops meye_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_log_status = v4l2_ctrl_log_status, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + .vidioc_default = vidioc_default, +}; + +static const struct video_device meye_template = { + .name = "meye", + .fops = &meye_fops, + .ioctl_ops = &meye_ioctl_ops, + .release = video_device_release_empty, + .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING, +}; + +static const struct v4l2_ctrl_ops meye_ctrl_ops = { + .s_ctrl = meye_s_ctrl, +}; + +static int __maybe_unused meye_suspend(struct device *dev) +{ + meye.pm_mchip_mode = meye.mchip_mode; + mchip_hic_stop(); + mchip_set(MCHIP_MM_INTA, 0x0); + return 0; +} + +static int __maybe_unused meye_resume(struct device *dev) +{ + pci_write_config_word(meye.mchip_dev, MCHIP_PCI_SOFTRESET_SET, 1); + + mchip_delay(MCHIP_HIC_CMD, 0); + mchip_delay(MCHIP_HIC_STATUS, MCHIP_HIC_STATUS_IDLE); + msleep(1); + mchip_set(MCHIP_VRJ_SOFT_RESET, 1); + msleep(1); + mchip_set(MCHIP_MM_PCI_MODE, 5); + msleep(1); + mchip_set(MCHIP_MM_INTA, MCHIP_MM_INTA_HIC_1_MASK); + + switch (meye.pm_mchip_mode) { + case MCHIP_HIC_MODE_CONT_OUT: + mchip_continuous_start(); + break; + case MCHIP_HIC_MODE_CONT_COMP: + mchip_cont_compression_start(); + break; + } + return 0; +} + +static int meye_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) +{ + static const struct v4l2_ctrl_config ctrl_agc = { + .id = V4L2_CID_MEYE_AGC, + .type = V4L2_CTRL_TYPE_INTEGER, + .ops = &meye_ctrl_ops, + .name = "AGC", + .max = 63, + .step = 1, + .def = 48, + .flags = V4L2_CTRL_FLAG_SLIDER, + }; + static const struct v4l2_ctrl_config ctrl_picture = { + .id = V4L2_CID_MEYE_PICTURE, + .type = V4L2_CTRL_TYPE_INTEGER, + .ops = &meye_ctrl_ops, + .name = "Picture", + .max = 63, + .step = 1, + }; + static const struct v4l2_ctrl_config ctrl_framerate = { + .id = V4L2_CID_MEYE_FRAMERATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .ops = &meye_ctrl_ops, + .name = "Framerate", + .max = 31, + .step = 1, + }; + struct v4l2_device *v4l2_dev = &meye.v4l2_dev; + int ret = -EBUSY; + unsigned long mchip_adr; + + if (meye.mchip_dev != NULL) { + printk(KERN_ERR "meye: only one device allowed!\n"); + return ret; + } + + ret = v4l2_device_register(&pcidev->dev, v4l2_dev); + if (ret < 0) { + v4l2_err(v4l2_dev, "Could not register v4l2_device\n"); + return ret; + } + ret = -ENOMEM; + meye.mchip_dev = pcidev; + + meye.grab_temp = vmalloc(array_size(PAGE_SIZE, MCHIP_NB_PAGES_MJPEG)); + if (!meye.grab_temp) + goto outvmalloc; + + spin_lock_init(&meye.grabq_lock); + if (kfifo_alloc(&meye.grabq, sizeof(int) * MEYE_MAX_BUFNBRS, + GFP_KERNEL)) + goto outkfifoalloc1; + + spin_lock_init(&meye.doneq_lock); + if (kfifo_alloc(&meye.doneq, sizeof(int) * MEYE_MAX_BUFNBRS, + GFP_KERNEL)) + goto outkfifoalloc2; + + meye.vdev = meye_template; + meye.vdev.v4l2_dev = &meye.v4l2_dev; + + ret = sony_pic_camera_command(SONY_PIC_COMMAND_SETCAMERA, 1); + if (ret) { + v4l2_err(v4l2_dev, "meye: unable to power on the camera\n"); + v4l2_err(v4l2_dev, "meye: did you enable the camera in sonypi using the module options ?\n"); + goto outsonypienable; + } + + ret = pci_enable_device(meye.mchip_dev); + if (ret) { + v4l2_err(v4l2_dev, "meye: pci_enable_device failed\n"); + goto outenabledev; + } + + ret = -EIO; + mchip_adr = pci_resource_start(meye.mchip_dev,0); + if (!mchip_adr) { + v4l2_err(v4l2_dev, "meye: mchip has no device base address\n"); + goto outregions; + } + if (!request_mem_region(pci_resource_start(meye.mchip_dev, 0), + pci_resource_len(meye.mchip_dev, 0), + "meye")) { + v4l2_err(v4l2_dev, "meye: request_mem_region failed\n"); + goto outregions; + } + meye.mchip_mmregs = ioremap(mchip_adr, MCHIP_MM_REGS); + if (!meye.mchip_mmregs) { + v4l2_err(v4l2_dev, "meye: ioremap failed\n"); + goto outremap; + } + + meye.mchip_irq = pcidev->irq; + if (request_irq(meye.mchip_irq, meye_irq, + IRQF_SHARED, "meye", meye_irq)) { + v4l2_err(v4l2_dev, "request_irq failed\n"); + goto outreqirq; + } + + pci_write_config_byte(meye.mchip_dev, PCI_CACHE_LINE_SIZE, 8); + pci_write_config_byte(meye.mchip_dev, PCI_LATENCY_TIMER, 64); + + pci_set_master(meye.mchip_dev); + + /* Ask the camera to perform a soft reset. */ + pci_write_config_word(meye.mchip_dev, MCHIP_PCI_SOFTRESET_SET, 1); + + mchip_delay(MCHIP_HIC_CMD, 0); + mchip_delay(MCHIP_HIC_STATUS, MCHIP_HIC_STATUS_IDLE); + + msleep(1); + mchip_set(MCHIP_VRJ_SOFT_RESET, 1); + + msleep(1); + mchip_set(MCHIP_MM_PCI_MODE, 5); + + msleep(1); + mchip_set(MCHIP_MM_INTA, MCHIP_MM_INTA_HIC_1_MASK); + + mutex_init(&meye.lock); + init_waitqueue_head(&meye.proc_list); + + v4l2_ctrl_handler_init(&meye.hdl, 3); + v4l2_ctrl_new_std(&meye.hdl, &meye_ctrl_ops, + V4L2_CID_BRIGHTNESS, 0, 63, 1, 32); + v4l2_ctrl_new_std(&meye.hdl, &meye_ctrl_ops, + V4L2_CID_HUE, 0, 63, 1, 32); + v4l2_ctrl_new_std(&meye.hdl, &meye_ctrl_ops, + V4L2_CID_CONTRAST, 0, 63, 1, 32); + v4l2_ctrl_new_std(&meye.hdl, &meye_ctrl_ops, + V4L2_CID_SATURATION, 0, 63, 1, 32); + v4l2_ctrl_new_custom(&meye.hdl, &ctrl_agc, NULL); + v4l2_ctrl_new_std(&meye.hdl, &meye_ctrl_ops, + V4L2_CID_SHARPNESS, 0, 63, 1, 32); + v4l2_ctrl_new_custom(&meye.hdl, &ctrl_picture, NULL); + v4l2_ctrl_new_std(&meye.hdl, &meye_ctrl_ops, + V4L2_CID_JPEG_COMPRESSION_QUALITY, 0, 10, 1, 8); + v4l2_ctrl_new_custom(&meye.hdl, &ctrl_framerate, NULL); + if (meye.hdl.error) { + v4l2_err(v4l2_dev, "couldn't register controls\n"); + goto outvideoreg; + } + + v4l2_ctrl_handler_setup(&meye.hdl); + meye.vdev.ctrl_handler = &meye.hdl; + + if (video_register_device(&meye.vdev, VFL_TYPE_VIDEO, + video_nr) < 0) { + v4l2_err(v4l2_dev, "video_register_device failed\n"); + goto outvideoreg; + } + + v4l2_info(v4l2_dev, "Motion Eye Camera Driver v%s.\n", + MEYE_DRIVER_VERSION); + v4l2_info(v4l2_dev, "mchip KL5A72002 rev. %d, base %lx, irq %d\n", + meye.mchip_dev->revision, mchip_adr, meye.mchip_irq); + + return 0; + +outvideoreg: + v4l2_ctrl_handler_free(&meye.hdl); + free_irq(meye.mchip_irq, meye_irq); +outreqirq: + iounmap(meye.mchip_mmregs); +outremap: + release_mem_region(pci_resource_start(meye.mchip_dev, 0), + pci_resource_len(meye.mchip_dev, 0)); +outregions: + pci_disable_device(meye.mchip_dev); +outenabledev: + sony_pic_camera_command(SONY_PIC_COMMAND_SETCAMERA, 0); +outsonypienable: + kfifo_free(&meye.doneq); +outkfifoalloc2: + kfifo_free(&meye.grabq); +outkfifoalloc1: + vfree(meye.grab_temp); +outvmalloc: + return ret; +} + +static void meye_remove(struct pci_dev *pcidev) +{ + video_unregister_device(&meye.vdev); + + mchip_hic_stop(); + + mchip_dma_free(); + + /* disable interrupts */ + mchip_set(MCHIP_MM_INTA, 0x0); + + free_irq(meye.mchip_irq, meye_irq); + + iounmap(meye.mchip_mmregs); + + release_mem_region(pci_resource_start(meye.mchip_dev, 0), + pci_resource_len(meye.mchip_dev, 0)); + + pci_disable_device(meye.mchip_dev); + + sony_pic_camera_command(SONY_PIC_COMMAND_SETCAMERA, 0); + + kfifo_free(&meye.doneq); + kfifo_free(&meye.grabq); + + vfree(meye.grab_temp); + + if (meye.grab_fbuffer) { + rvfree(meye.grab_fbuffer, gbuffers*gbufsize); + meye.grab_fbuffer = NULL; + } + + printk(KERN_INFO "meye: removed\n"); +} + +static const struct pci_device_id meye_pci_tbl[] = { + { PCI_VDEVICE(KAWASAKI, PCI_DEVICE_ID_MCHIP_KL5A72002), 0 }, + { } +}; + +MODULE_DEVICE_TABLE(pci, meye_pci_tbl); + +static SIMPLE_DEV_PM_OPS(meye_pm_ops, meye_suspend, meye_resume); + +static struct pci_driver meye_driver = { + .name = "meye", + .id_table = meye_pci_tbl, + .probe = meye_probe, + .remove = meye_remove, + .driver.pm = &meye_pm_ops, +}; + +static int __init meye_init(void) +{ + gbuffers = max(2, min((int)gbuffers, MEYE_MAX_BUFNBRS)); + if (gbufsize > MEYE_MAX_BUFSIZE) + gbufsize = MEYE_MAX_BUFSIZE; + gbufsize = PAGE_ALIGN(gbufsize); + printk(KERN_INFO "meye: using %d buffers with %dk (%dk total) for capture\n", + gbuffers, + gbufsize / 1024, gbuffers * gbufsize / 1024); + return pci_register_driver(&meye_driver); +} + +static void __exit meye_exit(void) +{ + pci_unregister_driver(&meye_driver); +} + +module_init(meye_init); +module_exit(meye_exit); diff --git a/drivers/staging/media/deprecated/meye/meye.h b/drivers/staging/media/deprecated/meye/meye.h new file mode 100644 index 000000000..5fa6552cf --- /dev/null +++ b/drivers/staging/media/deprecated/meye/meye.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Motion Eye video4linux driver for Sony Vaio PictureBook + * + * Copyright (C) 2001-2004 Stelian Pop + * + * Copyright (C) 2001-2002 Alcôve + * + * Copyright (C) 2000 Andrew Tridgell + * + * Earlier work by Werner Almesberger, Paul `Rusty' Russell and Paul Mackerras. + * + * Some parts borrowed from various video4linux drivers, especially + * bttv-driver.c and zoran.c, see original files for credits. + */ + +#ifndef _MEYE_PRIV_H_ +#define _MEYE_PRIV_H_ + +#define MEYE_DRIVER_MAJORVERSION 1 +#define MEYE_DRIVER_MINORVERSION 14 + +#define MEYE_DRIVER_VERSION __stringify(MEYE_DRIVER_MAJORVERSION) "." \ + __stringify(MEYE_DRIVER_MINORVERSION) + +#include +#include +#include +#include + +/****************************************************************************/ +/* Motion JPEG chip registers */ +/****************************************************************************/ + +/* Motion JPEG chip PCI configuration registers */ +#define MCHIP_PCI_POWER_CSR 0x54 +#define MCHIP_PCI_MCORE_STATUS 0x60 /* see HIC_STATUS */ +#define MCHIP_PCI_HOSTUSEREQ_SET 0x64 +#define MCHIP_PCI_HOSTUSEREQ_CLR 0x68 +#define MCHIP_PCI_LOWPOWER_SET 0x6c +#define MCHIP_PCI_LOWPOWER_CLR 0x70 +#define MCHIP_PCI_SOFTRESET_SET 0x74 + +/* Motion JPEG chip memory mapped registers */ +#define MCHIP_MM_REGS 0x200 /* 512 bytes */ +#define MCHIP_REG_TIMEOUT 1000 /* reg access, ~us */ +#define MCHIP_MCC_VRJ_TIMEOUT 1000 /* MCC & VRJ access */ + +#define MCHIP_MM_PCI_MODE 0x00 /* PCI access mode */ +#define MCHIP_MM_PCI_MODE_RETRY 0x00000001 /* retry mode */ +#define MCHIP_MM_PCI_MODE_MASTER 0x00000002 /* master access */ +#define MCHIP_MM_PCI_MODE_READ_LINE 0x00000004 /* read line */ + +#define MCHIP_MM_INTA 0x04 /* Int status/mask */ +#define MCHIP_MM_INTA_MCC 0x00000001 /* MCC interrupt */ +#define MCHIP_MM_INTA_VRJ 0x00000002 /* VRJ interrupt */ +#define MCHIP_MM_INTA_HIC_1 0x00000004 /* one frame done */ +#define MCHIP_MM_INTA_HIC_1_MASK 0x00000400 /* 1: enable */ +#define MCHIP_MM_INTA_HIC_END 0x00000008 /* all frames done */ +#define MCHIP_MM_INTA_HIC_END_MASK 0x00000800 +#define MCHIP_MM_INTA_JPEG 0x00000010 /* decompress. error */ +#define MCHIP_MM_INTA_JPEG_MASK 0x00001000 +#define MCHIP_MM_INTA_CAPTURE 0x00000020 /* capture end */ +#define MCHIP_MM_INTA_PCI_ERR 0x00000040 /* PCI error */ +#define MCHIP_MM_INTA_PCI_ERR_MASK 0x00004000 + +#define MCHIP_MM_PT_ADDR 0x08 /* page table address*/ + /* n*4kB */ +#define MCHIP_NB_PAGES 1024 /* pages for display */ +#define MCHIP_NB_PAGES_MJPEG 256 /* pages for mjpeg */ + +#define MCHIP_MM_FIR(n) (0x0c+(n)*4) /* Frame info 0-3 */ +#define MCHIP_MM_FIR_RDY 0x00000001 /* frame ready */ +#define MCHIP_MM_FIR_FAILFR_MASK 0xf8000000 /* # of failed frames */ +#define MCHIP_MM_FIR_FAILFR_SHIFT 27 + + /* continuous comp/decomp mode */ +#define MCHIP_MM_FIR_C_ENDL_MASK 0x000007fe /* end DW [10] */ +#define MCHIP_MM_FIR_C_ENDL_SHIFT 1 +#define MCHIP_MM_FIR_C_ENDP_MASK 0x0007f800 /* end page [8] */ +#define MCHIP_MM_FIR_C_ENDP_SHIFT 11 +#define MCHIP_MM_FIR_C_STARTP_MASK 0x07f80000 /* start page [8] */ +#define MCHIP_MM_FIR_C_STARTP_SHIFT 19 + + /* continuous picture output mode */ +#define MCHIP_MM_FIR_O_STARTP_MASK 0x7ffe0000 /* start page [10] */ +#define MCHIP_MM_FIR_O_STARTP_SHIFT 17 + +#define MCHIP_MM_FIFO_DATA 0x1c /* PCI TGT FIFO data */ +#define MCHIP_MM_FIFO_STATUS 0x20 /* PCI TGT FIFO stat */ +#define MCHIP_MM_FIFO_MASK 0x00000003 +#define MCHIP_MM_FIFO_WAIT_OR_READY 0x00000002 /* Bits common to WAIT & READY*/ +#define MCHIP_MM_FIFO_IDLE 0x0 /* HIC idle */ +#define MCHIP_MM_FIFO_IDLE1 0x1 /* idem ??? */ +#define MCHIP_MM_FIFO_WAIT 0x2 /* wait request */ +#define MCHIP_MM_FIFO_READY 0x3 /* data ready */ + +#define MCHIP_HIC_HOST_USEREQ 0x40 /* host uses MCORE */ + +#define MCHIP_HIC_TP_BUSY 0x44 /* taking picture */ + +#define MCHIP_HIC_PIC_SAVED 0x48 /* pic in SDRAM */ + +#define MCHIP_HIC_LOWPOWER 0x4c /* clock stopped */ + +#define MCHIP_HIC_CTL 0x50 /* HIC control */ +#define MCHIP_HIC_CTL_SOFT_RESET 0x00000001 /* MCORE reset */ +#define MCHIP_HIC_CTL_MCORE_RDY 0x00000002 /* MCORE ready */ + +#define MCHIP_HIC_CMD 0x54 /* HIC command */ +#define MCHIP_HIC_CMD_BITS 0x00000003 /* cmd width=[1:0]*/ +#define MCHIP_HIC_CMD_NOOP 0x0 +#define MCHIP_HIC_CMD_START 0x1 +#define MCHIP_HIC_CMD_STOP 0x2 + +#define MCHIP_HIC_MODE 0x58 +#define MCHIP_HIC_MODE_NOOP 0x0 +#define MCHIP_HIC_MODE_STILL_CAP 0x1 /* still pic capt */ +#define MCHIP_HIC_MODE_DISPLAY 0x2 /* display */ +#define MCHIP_HIC_MODE_STILL_COMP 0x3 /* still pic comp. */ +#define MCHIP_HIC_MODE_STILL_DECOMP 0x4 /* still pic decomp. */ +#define MCHIP_HIC_MODE_CONT_COMP 0x5 /* cont capt+comp */ +#define MCHIP_HIC_MODE_CONT_DECOMP 0x6 /* cont decomp+disp */ +#define MCHIP_HIC_MODE_STILL_OUT 0x7 /* still pic output */ +#define MCHIP_HIC_MODE_CONT_OUT 0x8 /* cont output */ + +#define MCHIP_HIC_STATUS 0x5c +#define MCHIP_HIC_STATUS_MCC_RDY 0x00000001 /* MCC reg acc ok */ +#define MCHIP_HIC_STATUS_VRJ_RDY 0x00000002 /* VRJ reg acc ok */ +#define MCHIP_HIC_STATUS_IDLE 0x00000003 +#define MCHIP_HIC_STATUS_CAPDIS 0x00000004 /* cap/disp in prog */ +#define MCHIP_HIC_STATUS_COMPDEC 0x00000008 /* (de)comp in prog */ +#define MCHIP_HIC_STATUS_BUSY 0x00000010 /* HIC busy */ + +#define MCHIP_HIC_S_RATE 0x60 /* MJPEG # frames */ + +#define MCHIP_HIC_PCI_VFMT 0x64 /* video format */ +#define MCHIP_HIC_PCI_VFMT_YVYU 0x00000001 /* 0: V Y' U Y */ + /* 1: Y' V Y U */ + +#define MCHIP_MCC_CMD 0x80 /* MCC commands */ +#define MCHIP_MCC_CMD_INITIAL 0x0 /* idle ? */ +#define MCHIP_MCC_CMD_IIC_START_SET 0x1 +#define MCHIP_MCC_CMD_IIC_END_SET 0x2 +#define MCHIP_MCC_CMD_FM_WRITE 0x3 /* frame memory */ +#define MCHIP_MCC_CMD_FM_READ 0x4 +#define MCHIP_MCC_CMD_FM_STOP 0x5 +#define MCHIP_MCC_CMD_CAPTURE 0x6 +#define MCHIP_MCC_CMD_DISPLAY 0x7 +#define MCHIP_MCC_CMD_END_DISP 0x8 +#define MCHIP_MCC_CMD_STILL_COMP 0x9 +#define MCHIP_MCC_CMD_STILL_DECOMP 0xa +#define MCHIP_MCC_CMD_STILL_OUTPUT 0xb +#define MCHIP_MCC_CMD_CONT_OUTPUT 0xc +#define MCHIP_MCC_CMD_CONT_COMP 0xd +#define MCHIP_MCC_CMD_CONT_DECOMP 0xe +#define MCHIP_MCC_CMD_RESET 0xf /* MCC reset */ + +#define MCHIP_MCC_IIC_WR 0x84 + +#define MCHIP_MCC_MCC_WR 0x88 + +#define MCHIP_MCC_MCC_RD 0x8c + +#define MCHIP_MCC_STATUS 0x90 +#define MCHIP_MCC_STATUS_CAPT 0x00000001 /* capturing */ +#define MCHIP_MCC_STATUS_DISP 0x00000002 /* displaying */ +#define MCHIP_MCC_STATUS_COMP 0x00000004 /* compressing */ +#define MCHIP_MCC_STATUS_DECOMP 0x00000008 /* decompressing */ +#define MCHIP_MCC_STATUS_MCC_WR 0x00000010 /* register ready */ +#define MCHIP_MCC_STATUS_MCC_RD 0x00000020 /* register ready */ +#define MCHIP_MCC_STATUS_IIC_WR 0x00000040 /* register ready */ +#define MCHIP_MCC_STATUS_OUTPUT 0x00000080 /* output in prog */ + +#define MCHIP_MCC_SIG_POLARITY 0x94 +#define MCHIP_MCC_SIG_POL_VS_H 0x00000001 /* VS active-high */ +#define MCHIP_MCC_SIG_POL_HS_H 0x00000002 /* HS active-high */ +#define MCHIP_MCC_SIG_POL_DOE_H 0x00000004 /* DOE active-high */ + +#define MCHIP_MCC_IRQ 0x98 +#define MCHIP_MCC_IRQ_CAPDIS_STRT 0x00000001 /* cap/disp started */ +#define MCHIP_MCC_IRQ_CAPDIS_STRT_MASK 0x00000010 +#define MCHIP_MCC_IRQ_CAPDIS_END 0x00000002 /* cap/disp ended */ +#define MCHIP_MCC_IRQ_CAPDIS_END_MASK 0x00000020 +#define MCHIP_MCC_IRQ_COMPDEC_STRT 0x00000004 /* (de)comp started */ +#define MCHIP_MCC_IRQ_COMPDEC_STRT_MASK 0x00000040 +#define MCHIP_MCC_IRQ_COMPDEC_END 0x00000008 /* (de)comp ended */ +#define MCHIP_MCC_IRQ_COMPDEC_END_MASK 0x00000080 + +#define MCHIP_MCC_HSTART 0x9c /* video in */ +#define MCHIP_MCC_VSTART 0xa0 +#define MCHIP_MCC_HCOUNT 0xa4 +#define MCHIP_MCC_VCOUNT 0xa8 +#define MCHIP_MCC_R_XBASE 0xac /* capt/disp */ +#define MCHIP_MCC_R_YBASE 0xb0 +#define MCHIP_MCC_R_XRANGE 0xb4 +#define MCHIP_MCC_R_YRANGE 0xb8 +#define MCHIP_MCC_B_XBASE 0xbc /* comp/decomp */ +#define MCHIP_MCC_B_YBASE 0xc0 +#define MCHIP_MCC_B_XRANGE 0xc4 +#define MCHIP_MCC_B_YRANGE 0xc8 + +#define MCHIP_MCC_R_SAMPLING 0xcc /* 1: 1:4 */ + +#define MCHIP_VRJ_CMD 0x100 /* VRJ commands */ + +/* VRJ registers (see table 12.2.4) */ +#define MCHIP_VRJ_COMPRESSED_DATA 0x1b0 +#define MCHIP_VRJ_PIXEL_DATA 0x1b8 + +#define MCHIP_VRJ_BUS_MODE 0x100 +#define MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL 0x108 +#define MCHIP_VRJ_PDAT_USE 0x110 +#define MCHIP_VRJ_MODE_SPECIFY 0x118 +#define MCHIP_VRJ_LIMIT_COMPRESSED_LO 0x120 +#define MCHIP_VRJ_LIMIT_COMPRESSED_HI 0x124 +#define MCHIP_VRJ_COMP_DATA_FORMAT 0x128 +#define MCHIP_VRJ_TABLE_DATA 0x140 +#define MCHIP_VRJ_RESTART_INTERVAL 0x148 +#define MCHIP_VRJ_NUM_LINES 0x150 +#define MCHIP_VRJ_NUM_PIXELS 0x158 +#define MCHIP_VRJ_NUM_COMPONENTS 0x160 +#define MCHIP_VRJ_SOF1 0x168 +#define MCHIP_VRJ_SOF2 0x170 +#define MCHIP_VRJ_SOF3 0x178 +#define MCHIP_VRJ_SOF4 0x180 +#define MCHIP_VRJ_SOS 0x188 +#define MCHIP_VRJ_SOFT_RESET 0x190 + +#define MCHIP_VRJ_STATUS 0x1c0 +#define MCHIP_VRJ_STATUS_BUSY 0x00001 +#define MCHIP_VRJ_STATUS_COMP_ACCESS 0x00002 +#define MCHIP_VRJ_STATUS_PIXEL_ACCESS 0x00004 +#define MCHIP_VRJ_STATUS_ERROR 0x00008 + +#define MCHIP_VRJ_IRQ_FLAG 0x1c8 +#define MCHIP_VRJ_ERROR_REPORT 0x1d8 + +#define MCHIP_VRJ_START_COMMAND 0x1a0 + +/****************************************************************************/ +/* Driver definitions. */ +/****************************************************************************/ + +/* Sony Programmable I/O Controller for accessing the camera commands */ +#include + +/* private API definitions */ +#include +#include + + +/* Enable jpg software correction */ +#define MEYE_JPEG_CORRECTION 1 + +/* Maximum size of a buffer */ +#define MEYE_MAX_BUFSIZE 614400 /* 640 * 480 * 2 */ + +/* Maximum number of buffers */ +#define MEYE_MAX_BUFNBRS 32 + +/* State of a buffer */ +#define MEYE_BUF_UNUSED 0 /* not used */ +#define MEYE_BUF_USING 1 /* currently grabbing / playing */ +#define MEYE_BUF_DONE 2 /* done */ + +/* grab buffer */ +struct meye_grab_buffer { + int state; /* state of buffer */ + unsigned long size; /* size of jpg frame */ + u64 ts; /* timestamp */ + unsigned long sequence; /* sequence number */ +}; + +/* size of kfifos containing buffer indices */ +#define MEYE_QUEUE_SIZE MEYE_MAX_BUFNBRS + +/* Motion Eye device structure */ +struct meye { + struct v4l2_device v4l2_dev; /* Main v4l2_device struct */ + struct v4l2_ctrl_handler hdl; + struct pci_dev *mchip_dev; /* pci device */ + u8 mchip_irq; /* irq */ + u8 mchip_mode; /* actual mchip mode: HIC_MODE... */ + u8 mchip_fnum; /* current mchip frame number */ + unsigned char __iomem *mchip_mmregs;/* mchip: memory mapped registers */ + u8 *mchip_ptable[MCHIP_NB_PAGES];/* mchip: ptable */ + void *mchip_ptable_toc; /* mchip: ptable toc */ + dma_addr_t mchip_dmahandle; /* mchip: dma handle to ptable toc */ + unsigned char *grab_fbuffer; /* capture framebuffer */ + unsigned char *grab_temp; /* temporary buffer */ + /* list of buffers */ + struct meye_grab_buffer grab_buffer[MEYE_MAX_BUFNBRS]; + int vma_use_count[MEYE_MAX_BUFNBRS]; /* mmap count */ + struct mutex lock; /* mutex for open/mmap... */ + struct kfifo grabq; /* queue for buffers to be grabbed */ + spinlock_t grabq_lock; /* lock protecting the queue */ + struct kfifo doneq; /* queue for grabbed buffers */ + spinlock_t doneq_lock; /* lock protecting the queue */ + wait_queue_head_t proc_list; /* wait queue */ + struct video_device vdev; /* video device parameters */ + u16 brightness; + u16 hue; + u16 contrast; + u16 colour; + struct meye_params params; /* additional parameters */ + unsigned long in_use; /* set to 1 if the device is in use */ + u8 pm_mchip_mode; /* old mchip mode */ +}; + +#endif diff --git a/drivers/staging/media/deprecated/saa7146/Kconfig b/drivers/staging/media/deprecated/saa7146/Kconfig new file mode 100644 index 000000000..54154da79 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +source "drivers/staging/media/deprecated/saa7146/common/Kconfig" +source "drivers/staging/media/deprecated/saa7146/av7110/Kconfig" +source "drivers/staging/media/deprecated/saa7146/saa7146/Kconfig" +source "drivers/staging/media/deprecated/saa7146/ttpci/Kconfig" diff --git a/drivers/staging/media/deprecated/saa7146/Makefile b/drivers/staging/media/deprecated/saa7146/Makefile new file mode 100644 index 000000000..68e7aa10c --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/Makefile @@ -0,0 +1,2 @@ + # SPDX-License-Identifier: GPL-2.0-only +obj-y += common/ av7110/ saa7146/ ttpci/ diff --git a/drivers/staging/media/deprecated/saa7146/av7110/Kconfig b/drivers/staging/media/deprecated/saa7146/av7110/Kconfig new file mode 100644 index 000000000..1571eab31 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/Kconfig @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DVB_AV7110_IR + bool + depends on RC_CORE=y || RC_CORE = DVB_AV7110 + default DVB_AV7110 + +config DVB_AV7110 + tristate "AV7110 cards (DEPRECATED)" + depends on DVB_CORE && PCI && I2C + select TTPCI_EEPROM + select VIDEO_SAA7146_VV + depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV + select DVB_VES1820 if MEDIA_SUBDRV_AUTOSELECT + select DVB_VES1X93 if MEDIA_SUBDRV_AUTOSELECT + select DVB_STV0299 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA8083 if MEDIA_SUBDRV_AUTOSELECT + select DVB_SP8870 if MEDIA_SUBDRV_AUTOSELECT + select DVB_STV0297 if MEDIA_SUBDRV_AUTOSELECT + select DVB_L64781 if MEDIA_SUBDRV_AUTOSELECT + select DVB_LNBP21 if MEDIA_SUBDRV_AUTOSELECT + help + Support for SAA7146 and AV7110 based DVB cards as produced + by Fujitsu-Siemens, Technotrend, Hauppauge and others. + + This driver only supports the fullfeatured cards with + onboard MPEG2 decoder. + + This driver needs an external firmware. Please use the script + "/scripts/get_dvb_firmware av7110" to + download/extract it, and then copy it to /usr/lib/hotplug/firmware + or /lib/firmware (depending on configuration of firmware hotplug). + + Alternatively, you can download the file and use the kernel's + EXTRA_FIRMWARE configuration option to build it into your + kernel image by adding the filename to the EXTRA_FIRMWARE + configuration option string. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + Say Y if you own such a card and want to use it. + +config DVB_AV7110_OSD + bool "AV7110 OSD support (DEPRECATED)" + depends on DVB_AV7110 + default y if DVB_AV7110=y || DVB_AV7110=m + help + The AV7110 firmware provides some code to generate an OnScreenDisplay + on the video output. This is kind of nonstandard and not guaranteed to + be maintained. + + Anyway, some popular DVB software like VDR uses this OSD to render + its menus, so say Y if you want to use this software. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + All other people say N. + +config DVB_BUDGET_PATCH + tristate "AV7110 cards with Budget Patch (DEPRECATED)" + depends on DVB_BUDGET_CORE && I2C + depends on DVB_AV7110 + select DVB_STV0299 if MEDIA_SUBDRV_AUTOSELECT + select DVB_VES1X93 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA8083 if MEDIA_SUBDRV_AUTOSELECT + help + Support for Budget Patch (full TS) modification on + SAA7146+AV7110 based cards (DVB-S cards). This + driver doesn't use onboard MPEG2 decoder. The + card is driven in Budget-only mode. Card is + required to have loaded firmware to tune properly. + Firmware can be loaded by insertion and removal of + standard AV7110 driver prior to loading this + driver. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + Say Y if you own such a card and want to use it. + + To compile this driver as a module, choose M here: the + module will be called budget-patch. + +if DVB_AV7110 + +# Frontend driver that it is used only by AV7110 driver +# While technically independent, it doesn't make sense to keep +# it if we drop support for AV7110, as no other driver will use it. + +config DVB_SP8870 + tristate "Spase sp8870 based (DEPRECATED)" + depends on DVB_CORE && I2C + default m if !MEDIA_SUBDRV_AUTOSELECT + help + A DVB-T tuner module. Say Y when you want to support this frontend. + + This driver needs external firmware. Please use the command + "/scripts/get_dvb_firmware sp8870" to + download/extract it, and then copy it to /usr/lib/hotplug/firmware + or /lib/firmware (depending on configuration of firmware hotplug). + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + +endif diff --git a/drivers/staging/media/deprecated/saa7146/av7110/Makefile b/drivers/staging/media/deprecated/saa7146/av7110/Makefile new file mode 100644 index 000000000..c04cd0a59 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/Makefile @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the AV7110 DVB device driver +# + +dvb-ttpci-objs := av7110_hw.o av7110_v4l.o av7110_av.o av7110_ca.o av7110.o \ + av7110_ipack.o dvb_filter.o + +ifdef CONFIG_DVB_AV7110_IR +dvb-ttpci-objs += av7110_ir.o +endif + +obj-$(CONFIG_DVB_BUDGET_PATCH) += budget-patch.o + +obj-$(CONFIG_DVB_AV7110) += dvb-ttpci.o + +obj-$(CONFIG_DVB_SP8870) += sp8870.o + +ccflags-y += -I $(srctree)/drivers/media/dvb-frontends +ccflags-y += -I $(srctree)/drivers/media/tuners +ccflags-y += -I $(srctree)/drivers/media/common +ccflags-y += -I $(srctree)/drivers/staging/media/deprecated/saa7146/ttpci +ccflags-y += -I $(srctree)/drivers/staging/media/deprecated/saa7146/common diff --git a/drivers/staging/media/deprecated/saa7146/av7110/TODO b/drivers/staging/media/deprecated/saa7146/av7110/TODO new file mode 100644 index 000000000..38817e04b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/TODO @@ -0,0 +1,9 @@ +- This driver is too old and relies on a different API. + Drop it from Kernel on a couple of versions. +- Cleanup patches for the drivers here won't be accepted. + +These drivers are now deprecated with the intent of +removing them altogether by the beginning of 2023. + +If someone is interested in doing this work, then contact the +linux-media mailinglist (https://linuxtv.org/lists.php). diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-bilingual-channel-select.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-bilingual-channel-select.rst new file mode 100644 index 000000000..33b536331 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-bilingual-channel-select.rst @@ -0,0 +1,58 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_BILINGUAL_CHANNEL_SELECT: + +============================== +AUDIO_BILINGUAL_CHANNEL_SELECT +============================== + +Name +---- + +AUDIO_BILINGUAL_CHANNEL_SELECT + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_BILINGUAL_CHANNEL_SELECT + +``int ioctl(int fd, AUDIO_BILINGUAL_CHANNEL_SELECT, struct audio_channel_select *select)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - audio_channel_select_t ch + + - Select the output format of the audio (mono left/right, stereo). + +Description +----------- + +This ioctl is obsolete. Do not use in new drivers. It has been replaced +by the V4L2 ``V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK`` control +for MPEG decoders controlled through V4L2. + +This ioctl call asks the Audio Device to select the requested channel +for bilingual streams if possible. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-channel-select.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-channel-select.rst new file mode 100644 index 000000000..74093df92 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-channel-select.rst @@ -0,0 +1,57 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_CHANNEL_SELECT: + +==================== +AUDIO_CHANNEL_SELECT +==================== + +Name +---- + +AUDIO_CHANNEL_SELECT + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_CHANNEL_SELECT + +``int ioctl(int fd, AUDIO_CHANNEL_SELECT, struct audio_channel_select *select)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - audio_channel_select_t ch + + - Select the output format of the audio (mono left/right, stereo). + +Description +----------- + +This ioctl is for Digital TV devices only. To control a V4L2 decoder use the +V4L2 ``V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK`` control instead. + +This ioctl call asks the Audio Device to select the requested channel if +possible. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-clear-buffer.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-clear-buffer.rst new file mode 100644 index 000000000..a0ebb0278 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-clear-buffer.rst @@ -0,0 +1,48 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_CLEAR_BUFFER: + +================== +AUDIO_CLEAR_BUFFER +================== + +Name +---- + +AUDIO_CLEAR_BUFFER + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_CLEAR_BUFFER + +``int ioctl(int fd, AUDIO_CLEAR_BUFFER)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + +Description +----------- + +This ioctl call asks the Audio Device to clear all software and hardware +buffers of the audio decoder device. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-continue.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-continue.rst new file mode 100644 index 000000000..a2e9850f3 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-continue.rst @@ -0,0 +1,48 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_CONTINUE: + +============== +AUDIO_CONTINUE +============== + +Name +---- + +AUDIO_CONTINUE + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_CONTINUE + +``int ioctl(int fd, AUDIO_CONTINUE)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + +Description +----------- + +This ioctl restarts the decoding and playing process previously paused +with AUDIO_PAUSE command. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-fclose.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-fclose.rst new file mode 100644 index 000000000..77857d578 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-fclose.rst @@ -0,0 +1,51 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _audio_fclose: + +======================== +Digital TV audio close() +======================== + +Name +---- + +Digital TV audio close() + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:function:: int close(int fd) + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + +Description +----------- + +This system call closes a previously opened audio device. + +Return Value +------------ + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EBADF`` + + - fd is not a valid open file descriptor. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-fopen.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-fopen.rst new file mode 100644 index 000000000..774daaab3 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-fopen.rst @@ -0,0 +1,103 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _audio_fopen: + +======================= +Digital TV audio open() +======================= + +Name +---- + +Digital TV audio open() + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:function:: int open(const char *deviceName, int flags) + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - const char \*deviceName + + - Name of specific audio device. + + - .. row 2 + + - int flags + + - A bit-wise OR of the following flags: + + - .. row 3 + + - + - O_RDONLY read-only access + + - .. row 4 + + - + - O_RDWR read/write access + + - .. row 5 + + - + - O_NONBLOCK open in non-blocking mode + + - .. row 6 + + - + - (blocking mode is the default) + +Description +----------- + +This system call opens a named audio device (e.g. +/dev/dvb/adapter0/audio0) for subsequent use. When an open() call has +succeeded, the device will be ready for use. The significance of +blocking or non-blocking mode is described in the documentation for +functions where there is a difference. It does not affect the semantics +of the open() call itself. A device opened in blocking mode can later be +put into non-blocking mode (and vice versa) using the F_SETFL command +of the fcntl system call. This is a standard system call, documented in +the Linux manual page for fcntl. Only one user can open the Audio Device +in O_RDWR mode. All other attempts to open the device in this mode will +fail, and an error code will be returned. If the Audio Device is opened +in O_RDONLY mode, the only ioctl call that can be used is +AUDIO_GET_STATUS. All other call will return with an error code. + +Return Value +------------ + +.. tabularcolumns:: |p{2.5cm}|p{15.0cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``ENODEV`` + + - Device driver not loaded/available. + + - .. row 2 + + - ``EBUSY`` + + - Device or resource busy. + + - .. row 3 + + - ``EINVAL`` + + - Invalid argument. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-fwrite.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-fwrite.rst new file mode 100644 index 000000000..7b096ac2b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-fwrite.rst @@ -0,0 +1,79 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _audio_fwrite: + +========================= +Digital TV audio write() +========================= + +Name +---- + +Digital TV audio write() + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:function:: size_t write(int fd, const void *buf, size_t count) + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - void \*buf + + - Pointer to the buffer containing the PES data. + + - .. row 3 + + - size_t count + + - Size of buf. + +Description +----------- + +This system call can only be used if AUDIO_SOURCE_MEMORY is selected +in the ioctl call AUDIO_SELECT_SOURCE. The data provided shall be in +PES format. If O_NONBLOCK is not specified the function will block +until buffer space is available. The amount of data to be transferred is +implied by count. + +Return Value +------------ + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EPERM`` + + - Mode AUDIO_SOURCE_MEMORY not selected. + + - .. row 2 + + - ``ENOMEM`` + + - Attempted to write more data than the internal buffer can hold. + + - .. row 3 + + - ``EBADF`` + + - fd is not a valid open file descriptor. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-get-capabilities.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-get-capabilities.rst new file mode 100644 index 000000000..6d9eb71da --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-get-capabilities.rst @@ -0,0 +1,54 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_GET_CAPABILITIES: + +====================== +AUDIO_GET_CAPABILITIES +====================== + +Name +---- + +AUDIO_GET_CAPABILITIES + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_GET_CAPABILITIES + +``int ioctl(int fd, AUDIO_GET_CAPABILITIES, unsigned int *cap)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - unsigned int \*cap + + - Returns a bit array of supported sound formats. + +Description +----------- + +This ioctl call asks the Audio Device to tell us about the decoding +capabilities of the audio hardware. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-get-status.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-get-status.rst new file mode 100644 index 000000000..7ae8db2e6 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-get-status.rst @@ -0,0 +1,54 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_GET_STATUS: + +================ +AUDIO_GET_STATUS +================ + +Name +---- + +AUDIO_GET_STATUS + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_GET_STATUS + +``int ioctl(int fd, AUDIO_GET_STATUS, struct audio_status *status)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - struct audio_status \*status + + - Returns the current state of Audio Device. + +Description +----------- + +This ioctl call asks the Audio Device to return the current state of the +Audio Device. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-pause.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-pause.rst new file mode 100644 index 000000000..d37d1ddce --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-pause.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_PAUSE: + +=========== +AUDIO_PAUSE +=========== + +Name +---- + +AUDIO_PAUSE + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_PAUSE + +``int ioctl(int fd, AUDIO_PAUSE)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + +Description +----------- + +This ioctl call suspends the audio stream being played. Decoding and +playing are paused. It is then possible to restart again decoding and +playing process of the audio stream using AUDIO_CONTINUE command. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-play.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-play.rst new file mode 100644 index 000000000..e591930b6 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-play.rst @@ -0,0 +1,48 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_PLAY: + +========== +AUDIO_PLAY +========== + +Name +---- + +AUDIO_PLAY + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_PLAY + +``int ioctl(int fd, AUDIO_PLAY)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + +Description +----------- + +This ioctl call asks the Audio Device to start playing an audio stream +from the selected source. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-select-source.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-select-source.rst new file mode 100644 index 000000000..6a0c0f365 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-select-source.rst @@ -0,0 +1,56 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_SELECT_SOURCE: + +=================== +AUDIO_SELECT_SOURCE +=================== + +Name +---- + +AUDIO_SELECT_SOURCE + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_SELECT_SOURCE + +``int ioctl(int fd, AUDIO_SELECT_SOURCE, struct audio_stream_source *source)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - audio_stream_source_t source + + - Indicates the source that shall be used for the Audio stream. + +Description +----------- + +This ioctl call informs the audio device which source shall be used for +the input data. The possible sources are demux or memory. If +AUDIO_SOURCE_MEMORY is selected, the data is fed to the Audio Device +through the write command. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-set-av-sync.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-av-sync.rst new file mode 100644 index 000000000..85a8016bf --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-av-sync.rst @@ -0,0 +1,58 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_SET_AV_SYNC: + +================= +AUDIO_SET_AV_SYNC +================= + +Name +---- + +AUDIO_SET_AV_SYNC + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_SET_AV_SYNC + +``int ioctl(int fd, AUDIO_SET_AV_SYNC, boolean state)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - boolean state + + - Tells the Digital TV subsystem if A/V synchronization shall be ON or OFF. + + TRUE: AV-sync ON + + FALSE: AV-sync OFF + +Description +----------- + +This ioctl call asks the Audio Device to turn ON or OFF A/V +synchronization. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-set-bypass-mode.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-bypass-mode.rst new file mode 100644 index 000000000..80d551a20 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-bypass-mode.rst @@ -0,0 +1,62 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_SET_BYPASS_MODE: + +===================== +AUDIO_SET_BYPASS_MODE +===================== + +Name +---- + +AUDIO_SET_BYPASS_MODE + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_SET_BYPASS_MODE + +``int ioctl(int fd, AUDIO_SET_BYPASS_MODE, boolean mode)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - boolean mode + + - Enables or disables the decoding of the current Audio stream in + the Digital TV subsystem. + + TRUE: Bypass is disabled + + FALSE: Bypass is enabled + +Description +----------- + +This ioctl call asks the Audio Device to bypass the Audio decoder and +forward the stream without decoding. This mode shall be used if streams +that can't be handled by the Digital TV system shall be decoded. Dolby +DigitalTM streams are automatically forwarded by the Digital TV subsystem if +the hardware can handle it. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-set-id.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-id.rst new file mode 100644 index 000000000..39ad846d4 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-id.rst @@ -0,0 +1,59 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_SET_ID: + +============ +AUDIO_SET_ID +============ + +Name +---- + +AUDIO_SET_ID + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_SET_ID + +``int ioctl(int fd, AUDIO_SET_ID, int id)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - int id + + - audio sub-stream id + +Description +----------- + +This ioctl selects which sub-stream is to be decoded if a program or +system stream is sent to the video device. If no audio stream type is +set the id has to be in [0xC0,0xDF] for MPEG sound, in [0x80,0x87] for +AC3 and in [0xA0,0xA7] for LPCM. More specifications may follow for +other stream types. If the stream type is set the id just specifies the +substream id of the audio stream and only the first 5 bits are +recognized. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-set-mixer.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-mixer.rst new file mode 100644 index 000000000..45dbdf480 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-mixer.rst @@ -0,0 +1,53 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_SET_MIXER: + +=============== +AUDIO_SET_MIXER +=============== + +Name +---- + +AUDIO_SET_MIXER + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_SET_MIXER + +``int ioctl(int fd, AUDIO_SET_MIXER, struct audio_mixer *mix)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - audio_mixer_t \*mix + + - mixer settings. + +Description +----------- + +This ioctl lets you adjust the mixer settings of the audio decoder. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-set-mute.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-mute.rst new file mode 100644 index 000000000..987751f92 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-mute.rst @@ -0,0 +1,62 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_SET_MUTE: + +============== +AUDIO_SET_MUTE +============== + +Name +---- + +AUDIO_SET_MUTE + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_SET_MUTE + +``int ioctl(int fd, AUDIO_SET_MUTE, boolean state)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - boolean state + + - Indicates if audio device shall mute or not. + + TRUE: Audio Mute + + FALSE: Audio Un-mute + +Description +----------- + +This ioctl is for Digital TV devices only. To control a V4L2 decoder use the +V4L2 :ref:`VIDIOC_DECODER_CMD` with the +``V4L2_DEC_CMD_START_MUTE_AUDIO`` flag instead. + +This ioctl call asks the audio device to mute the stream that is +currently being played. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-set-streamtype.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-streamtype.rst new file mode 100644 index 000000000..77d73c748 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-set-streamtype.rst @@ -0,0 +1,66 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_SET_STREAMTYPE: + +==================== +AUDIO_SET_STREAMTYPE +==================== + +Name +---- + +AUDIO_SET_STREAMTYPE + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_SET_STREAMTYPE + +``int ioctl(fd, AUDIO_SET_STREAMTYPE, int type)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - + + - int fd + + - File descriptor returned by a previous call to open(). + + - + + - int type + + - stream type + +Description +----------- + +This ioctl tells the driver which kind of audio stream to expect. This +is useful if the stream offers several audio sub-streams like LPCM and +AC3. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. + + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EINVAL`` + + - type is not a valid or supported stream type. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio-stop.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio-stop.rst new file mode 100644 index 000000000..d77f786fd --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio-stop.rst @@ -0,0 +1,48 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.audio + +.. _AUDIO_STOP: + +========== +AUDIO_STOP +========== + +Name +---- + +AUDIO_STOP + +.. attention:: This ioctl is deprecated + +Synopsis +-------- + +.. c:macro:: AUDIO_STOP + +``int ioctl(int fd, AUDIO_STOP)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + +Description +----------- + +This ioctl call asks the Audio Device to stop playing the current +stream. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio.rst new file mode 100644 index 000000000..aa753336b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio.rst @@ -0,0 +1,27 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later + +.. _dvb_audio: + +####################### +Digital TV Audio Device +####################### + +The Digital TV audio device controls the MPEG2 audio decoder of the Digital +TV hardware. It can be accessed through ``/dev/dvb/adapter?/audio?``. Data +types and ioctl definitions can be accessed by including +``linux/dvb/audio.h`` in your application. + +Please note that some Digital TV cards don't have their own MPEG decoder, which +results in the omission of the audio and video device. + +These ioctls were also used by V4L2 to control MPEG decoders implemented +in V4L2. The use of these ioctls for that purpose has been made obsolete +and proper V4L2 ioctls or controls have been created to replace that +functionality. + + +.. toctree:: + :maxdepth: 1 + + audio_data_types + audio_function_calls diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio_data_types.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio_data_types.rst new file mode 100644 index 000000000..474452913 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio_data_types.rst @@ -0,0 +1,116 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later + +.. _audio_data_types: + +**************** +Audio Data Types +**************** + +This section describes the structures, data types and defines used when +talking to the audio device. + +.. c:type:: audio_stream_source + +The audio stream source is set through the AUDIO_SELECT_SOURCE call +and can take the following values, depending on whether we are replaying +from an internal (demux) or external (user write) source. + + +.. code-block:: c + + typedef enum { + AUDIO_SOURCE_DEMUX, + AUDIO_SOURCE_MEMORY + } audio_stream_source_t; + +AUDIO_SOURCE_DEMUX selects the demultiplexer (fed either by the +frontend or the DVR device) as the source of the video stream. If +AUDIO_SOURCE_MEMORY is selected the stream comes from the application +through the ``write()`` system call. + + +.. c:type:: audio_play_state + +The following values can be returned by the AUDIO_GET_STATUS call +representing the state of audio playback. + + +.. code-block:: c + + typedef enum { + AUDIO_STOPPED, + AUDIO_PLAYING, + AUDIO_PAUSED + } audio_play_state_t; + + +.. c:type:: audio_channel_select + +The audio channel selected via AUDIO_CHANNEL_SELECT is determined by +the following values. + + +.. code-block:: c + + typedef enum { + AUDIO_STEREO, + AUDIO_MONO_LEFT, + AUDIO_MONO_RIGHT, + AUDIO_MONO, + AUDIO_STEREO_SWAPPED + } audio_channel_select_t; + + +.. c:type:: audio_status + +The AUDIO_GET_STATUS call returns the following structure informing +about various states of the playback operation. + + +.. code-block:: c + + typedef struct audio_status { + boolean AV_sync_state; + boolean mute_state; + audio_play_state_t play_state; + audio_stream_source_t stream_source; + audio_channel_select_t channel_select; + boolean bypass_mode; + audio_mixer_t mixer_state; + } audio_status_t; + + +.. c:type:: audio_mixer + +The following structure is used by the AUDIO_SET_MIXER call to set the +audio volume. + + +.. code-block:: c + + typedef struct audio_mixer { + unsigned int volume_left; + unsigned int volume_right; + } audio_mixer_t; + + +.. _audio_encodings: + +audio encodings +=============== + +A call to AUDIO_GET_CAPABILITIES returns an unsigned integer with the +following bits set according to the hardwares capabilities. + + +.. code-block:: c + + #define AUDIO_CAP_DTS 1 + #define AUDIO_CAP_LPCM 2 + #define AUDIO_CAP_MP1 4 + #define AUDIO_CAP_MP2 8 + #define AUDIO_CAP_MP3 16 + #define AUDIO_CAP_AAC 32 + #define AUDIO_CAP_OGG 64 + #define AUDIO_CAP_SDDS 128 + #define AUDIO_CAP_AC3 256 diff --git a/drivers/staging/media/deprecated/saa7146/av7110/audio_function_calls.rst b/drivers/staging/media/deprecated/saa7146/av7110/audio_function_calls.rst new file mode 100644 index 000000000..fa5ba9539 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/audio_function_calls.rst @@ -0,0 +1,30 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later + +.. _audio_function_calls: + +******************** +Audio Function Calls +******************** + +.. toctree:: + :maxdepth: 1 + + audio-fopen + audio-fclose + audio-fwrite + audio-stop + audio-play + audio-pause + audio-continue + audio-select-source + audio-set-mute + audio-set-av-sync + audio-set-bypass-mode + audio-channel-select + audio-bilingual-channel-select + audio-get-status + audio-get-capabilities + audio-clear-buffer + audio-set-id + audio-set-mixer + audio-set-streamtype diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110.c b/drivers/staging/media/deprecated/saa7146/av7110/av7110.c new file mode 100644 index 000000000..df81a9b74 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110.c @@ -0,0 +1,2919 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * driver for the SAA7146 based AV110 cards (like the Fujitsu-Siemens DVB) + * av7110.c: initialization and demux stuff + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * originally based on code by: + * Copyright (C) 1998,1999 Christian Theiss + * + * the project's page is at https://linuxtv.org + */ + + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#include + +#include + +#include "ttpci-eeprom.h" +#include "av7110.h" +#include "av7110_hw.h" +#include "av7110_av.h" +#include "av7110_ca.h" +#include "av7110_ipack.h" + +#include "bsbe1.h" +#include "lnbp21.h" +#include "bsru6.h" + +#define TS_WIDTH 376 +#define TS_HEIGHT 512 +#define TS_BUFLEN (TS_WIDTH*TS_HEIGHT) +#define TS_MAX_PACKETS (TS_BUFLEN/TS_SIZE) + + +int av7110_debug; + +static int vidmode = CVBS_RGB_OUT; +static int pids_off; +static int adac = DVB_ADAC_TI; +static int hw_sections; +static int rgb_on; +static int volume = 255; +static int budgetpatch; +static int wss_cfg_4_3 = 0x4008; +static int wss_cfg_16_9 = 0x0007; +static int tv_standard; +static int full_ts; + +module_param_named(debug, av7110_debug, int, 0644); +MODULE_PARM_DESC(debug, "debug level (bitmask, default 0)"); +module_param(vidmode, int, 0444); +MODULE_PARM_DESC(vidmode,"analog video out: 0 off, 1 CVBS+RGB (default), 2 CVBS+YC, 3 YC"); +module_param(pids_off, int, 0444); +MODULE_PARM_DESC(pids_off,"clear video/audio/PCR PID filters when demux is closed"); +module_param(adac, int, 0444); +MODULE_PARM_DESC(adac,"audio DAC type: 0 TI, 1 CRYSTAL, 2 MSP (use if autodetection fails)"); +module_param(hw_sections, int, 0444); +MODULE_PARM_DESC(hw_sections, "0 use software section filter, 1 use hardware"); +module_param(rgb_on, int, 0444); +MODULE_PARM_DESC(rgb_on, "For Siemens DVB-C cards only: Enable RGB control signal on SCART pin 16 to switch SCART video mode from CVBS to RGB"); +module_param(volume, int, 0444); +MODULE_PARM_DESC(volume, "initial volume: default 255 (range 0-255)"); +module_param(budgetpatch, int, 0444); +MODULE_PARM_DESC(budgetpatch, "use budget-patch hardware modification: default 0 (0 no, 1 autodetect, 2 always)"); +module_param(full_ts, int, 0444); +MODULE_PARM_DESC(full_ts, "enable code for full-ts hardware modification: 0 disable (default), 1 enable"); +module_param(wss_cfg_4_3, int, 0444); +MODULE_PARM_DESC(wss_cfg_4_3, "WSS 4:3 - default 0x4008 - bit 15: disable, 14: burst mode, 13..0: wss data"); +module_param(wss_cfg_16_9, int, 0444); +MODULE_PARM_DESC(wss_cfg_16_9, "WSS 16:9 - default 0x0007 - bit 15: disable, 14: burst mode, 13..0: wss data"); +module_param(tv_standard, int, 0444); +MODULE_PARM_DESC(tv_standard, "TV standard: 0 PAL (default), 1 NTSC"); + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +static void restart_feeds(struct av7110 *av7110); +static int budget_start_feed(struct dvb_demux_feed *feed); +static int budget_stop_feed(struct dvb_demux_feed *feed); + +static int av7110_num; + +#define FE_FUNC_OVERRIDE(fe_func, av7110_copy, av7110_func) \ +{\ + if (fe_func != NULL) { \ + av7110_copy = fe_func; \ + fe_func = av7110_func; \ + } \ +} + + +static void init_av7110_av(struct av7110 *av7110) +{ + int ret; + struct saa7146_dev *dev = av7110->dev; + + /* set internal volume control to maximum */ + av7110->adac_type = DVB_ADAC_TI; + ret = av7110_set_volume(av7110, av7110->mixer.volume_left, av7110->mixer.volume_right); + if (ret < 0) + printk("dvb-ttpci:cannot set internal volume to maximum:%d\n",ret); + + ret = av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetMonitorType, + 1, (u16) av7110->display_ar); + if (ret < 0) + printk("dvb-ttpci: unable to set aspect ratio\n"); + ret = av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetPanScanType, + 1, av7110->display_panscan); + if (ret < 0) + printk("dvb-ttpci: unable to set pan scan\n"); + + ret = av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetWSSConfig, 2, 2, wss_cfg_4_3); + if (ret < 0) + printk("dvb-ttpci: unable to configure 4:3 wss\n"); + ret = av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetWSSConfig, 2, 3, wss_cfg_16_9); + if (ret < 0) + printk("dvb-ttpci: unable to configure 16:9 wss\n"); + + ret = av7710_set_video_mode(av7110, vidmode); + if (ret < 0) + printk("dvb-ttpci:cannot set video mode:%d\n",ret); + + /* handle different card types */ + /* remaining inits according to card and frontend type */ + av7110->analog_tuner_flags = 0; + av7110->current_input = 0; + if (dev->pci->subsystem_vendor == 0x13c2 && dev->pci->subsystem_device == 0x000a) + av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, ADSwitch, 1, 0); // SPDIF on + if (i2c_writereg(av7110, 0x20, 0x00, 0x00) == 1) { + printk ("dvb-ttpci: Crystal audio DAC @ card %d detected\n", + av7110->dvb_adapter.num); + av7110->adac_type = DVB_ADAC_CRYSTAL; + i2c_writereg(av7110, 0x20, 0x01, 0xd2); + i2c_writereg(av7110, 0x20, 0x02, 0x49); + i2c_writereg(av7110, 0x20, 0x03, 0x00); + i2c_writereg(av7110, 0x20, 0x04, 0x00); + + /** + * some special handling for the Siemens DVB-C cards... + */ + } else if (0 == av7110_init_analog_module(av7110)) { + /* done. */ + } + else if (dev->pci->subsystem_vendor == 0x110a) { + printk("dvb-ttpci: DVB-C w/o analog module @ card %d detected\n", + av7110->dvb_adapter.num); + av7110->adac_type = DVB_ADAC_NONE; + } + else { + av7110->adac_type = adac; + printk("dvb-ttpci: adac type set to %d @ card %d\n", + av7110->adac_type, av7110->dvb_adapter.num); + } + + if (av7110->adac_type == DVB_ADAC_NONE || av7110->adac_type == DVB_ADAC_MSP34x0) { + // switch DVB SCART on + ret = av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, MainSwitch, 1, 0); + if (ret < 0) + printk("dvb-ttpci:cannot switch on SCART(Main):%d\n",ret); + ret = av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, ADSwitch, 1, 1); + if (ret < 0) + printk("dvb-ttpci:cannot switch on SCART(AD):%d\n",ret); + if (rgb_on && + ((av7110->dev->pci->subsystem_vendor == 0x110a) || + (av7110->dev->pci->subsystem_vendor == 0x13c2)) && + (av7110->dev->pci->subsystem_device == 0x0000)) { + saa7146_setgpio(dev, 1, SAA7146_GPIO_OUTHI); // RGB on, SCART pin 16 + //saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); // SCARTpin 8 + } + } + + if (dev->pci->subsystem_vendor == 0x13c2 && dev->pci->subsystem_device == 0x000e) + av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, SpdifSwitch, 1, 0); // SPDIF on + + ret = av7110_set_volume(av7110, av7110->mixer.volume_left, av7110->mixer.volume_right); + if (ret < 0) + printk("dvb-ttpci:cannot set volume :%d\n",ret); +} + +static void recover_arm(struct av7110 *av7110) +{ + dprintk(4, "%p\n",av7110); + + av7110_bootarm(av7110); + msleep(100); + + init_av7110_av(av7110); + + /* card-specific recovery */ + if (av7110->recover) + av7110->recover(av7110); + + restart_feeds(av7110); + +#if IS_ENABLED(CONFIG_DVB_AV7110_IR) + av7110_set_ir_config(av7110); +#endif +} + +static void av7110_arm_sync(struct av7110 *av7110) +{ + if (av7110->arm_thread) + kthread_stop(av7110->arm_thread); + + av7110->arm_thread = NULL; +} + +static int arm_thread(void *data) +{ + struct av7110 *av7110 = data; + u16 newloops = 0; + int timeout; + + dprintk(4, "%p\n",av7110); + + for (;;) { + timeout = wait_event_interruptible_timeout(av7110->arm_wait, + kthread_should_stop(), 5 * HZ); + + if (-ERESTARTSYS == timeout || kthread_should_stop()) { + /* got signal or told to quit*/ + break; + } + + if (!av7110->arm_ready) + continue; + + if (mutex_lock_interruptible(&av7110->dcomlock)) + break; + newloops = rdebi(av7110, DEBINOSWAP, STATUS_LOOPS, 0, 2); + mutex_unlock(&av7110->dcomlock); + + if (newloops == av7110->arm_loops || av7110->arm_errors > 3) { + printk(KERN_ERR "dvb-ttpci: ARM crashed @ card %d\n", + av7110->dvb_adapter.num); + + recover_arm(av7110); + + if (mutex_lock_interruptible(&av7110->dcomlock)) + break; + newloops = rdebi(av7110, DEBINOSWAP, STATUS_LOOPS, 0, 2) - 1; + mutex_unlock(&av7110->dcomlock); + } + av7110->arm_loops = newloops; + av7110->arm_errors = 0; + } + + return 0; +} + + +/**************************************************************************** + * IRQ handling + ****************************************************************************/ + +static int DvbDmxFilterCallback(u8 *buffer1, size_t buffer1_len, + u8 *buffer2, size_t buffer2_len, + struct dvb_demux_filter *dvbdmxfilter, + struct av7110 *av7110) +{ + if (!dvbdmxfilter->feed->demux->dmx.frontend) + return 0; + if (dvbdmxfilter->feed->demux->dmx.frontend->source == DMX_MEMORY_FE) + return 0; + + switch (dvbdmxfilter->type) { + case DMX_TYPE_SEC: + if ((((buffer1[1] << 8) | buffer1[2]) & 0xfff) + 3 != buffer1_len) + return 0; + if (dvbdmxfilter->doneq) { + struct dmx_section_filter *filter = &dvbdmxfilter->filter; + int i; + u8 xor, neq = 0; + + for (i = 0; i < DVB_DEMUX_MASK_MAX; i++) { + xor = filter->filter_value[i] ^ buffer1[i]; + neq |= dvbdmxfilter->maskandnotmode[i] & xor; + } + if (!neq) + return 0; + } + return dvbdmxfilter->feed->cb.sec(buffer1, buffer1_len, + buffer2, buffer2_len, + &dvbdmxfilter->filter, NULL); + case DMX_TYPE_TS: + if (!(dvbdmxfilter->feed->ts_type & TS_PACKET)) + return 0; + if (dvbdmxfilter->feed->ts_type & TS_PAYLOAD_ONLY) + return dvbdmxfilter->feed->cb.ts(buffer1, buffer1_len, + buffer2, buffer2_len, + &dvbdmxfilter->feed->feed.ts, + NULL); + else + av7110_p2t_write(buffer1, buffer1_len, + dvbdmxfilter->feed->pid, + &av7110->p2t_filter[dvbdmxfilter->index]); + return 0; + default: + return 0; + } +} + + +//#define DEBUG_TIMING +static inline void print_time(char *s) +{ +#ifdef DEBUG_TIMING + struct timespec64 ts; + ktime_get_real_ts64(&ts); + printk("%s: %lld.%09ld\n", s, (s64)ts.tv_sec, ts.tv_nsec); +#endif +} + +#define DEBI_READ 0 +#define DEBI_WRITE 1 +static inline void start_debi_dma(struct av7110 *av7110, int dir, + unsigned long addr, unsigned int len) +{ + dprintk(8, "%c %08lx %u\n", dir == DEBI_READ ? 'R' : 'W', addr, len); + if (saa7146_wait_for_debi_done(av7110->dev, 0)) { + printk(KERN_ERR "%s: saa7146_wait_for_debi_done timed out\n", __func__); + return; + } + + SAA7146_ISR_CLEAR(av7110->dev, MASK_19); /* for good measure */ + SAA7146_IER_ENABLE(av7110->dev, MASK_19); + if (len < 5) + len = 5; /* we want a real DEBI DMA */ + if (dir == DEBI_WRITE) + iwdebi(av7110, DEBISWAB, addr, 0, (len + 3) & ~3); + else + irdebi(av7110, DEBISWAB, addr, 0, len); +} + +static void debiirq(struct tasklet_struct *t) +{ + struct av7110 *av7110 = from_tasklet(av7110, t, debi_tasklet); + int type = av7110->debitype; + int handle = (type >> 8) & 0x1f; + unsigned int xfer = 0; + + print_time("debi"); + dprintk(4, "type 0x%04x\n", type); + + if (type == -1) { + printk("DEBI irq oops @ %ld, psr:0x%08x, ssr:0x%08x\n", + jiffies, saa7146_read(av7110->dev, PSR), + saa7146_read(av7110->dev, SSR)); + goto debi_done; + } + av7110->debitype = -1; + + switch (type & 0xff) { + + case DATA_TS_RECORD: + dvb_dmx_swfilter_packets(&av7110->demux, + (const u8 *) av7110->debi_virt, + av7110->debilen / 188); + xfer = RX_BUFF; + break; + + case DATA_PES_RECORD: + if (av7110->demux.recording) + av7110_record_cb(&av7110->p2t[handle], + (u8 *) av7110->debi_virt, + av7110->debilen); + xfer = RX_BUFF; + break; + + case DATA_IPMPE: + case DATA_FSECTION: + case DATA_PIPING: + if (av7110->handle2filter[handle]) + DvbDmxFilterCallback((u8 *)av7110->debi_virt, + av7110->debilen, NULL, 0, + av7110->handle2filter[handle], + av7110); + xfer = RX_BUFF; + break; + + case DATA_CI_GET: + { + u8 *data = av7110->debi_virt; + u8 data_0 = data[0]; + + if (data_0 < 2 && data[2] == 0xff) { + int flags = 0; + if (data[5] > 0) + flags |= CA_CI_MODULE_PRESENT; + if (data[5] > 5) + flags |= CA_CI_MODULE_READY; + av7110->ci_slot[data_0].flags = flags; + } else + ci_get_data(&av7110->ci_rbuffer, + av7110->debi_virt, + av7110->debilen); + xfer = RX_BUFF; + break; + } + + case DATA_COMMON_INTERFACE: + CI_handle(av7110, (u8 *)av7110->debi_virt, av7110->debilen); + xfer = RX_BUFF; + break; + + case DATA_DEBUG_MESSAGE: + ((s8*)av7110->debi_virt)[Reserved_SIZE - 1] = 0; + printk("%s\n", (s8 *) av7110->debi_virt); + xfer = RX_BUFF; + break; + + case DATA_CI_PUT: + dprintk(4, "debi DATA_CI_PUT\n"); + xfer = TX_BUFF; + break; + case DATA_MPEG_PLAY: + dprintk(4, "debi DATA_MPEG_PLAY\n"); + xfer = TX_BUFF; + break; + case DATA_BMP_LOAD: + dprintk(4, "debi DATA_BMP_LOAD\n"); + xfer = TX_BUFF; + break; + default: + break; + } +debi_done: + spin_lock(&av7110->debilock); + if (xfer) + iwdebi(av7110, DEBINOSWAP, xfer, 0, 2); + ARM_ClearMailBox(av7110); + spin_unlock(&av7110->debilock); +} + +/* irq from av7110 firmware writing the mailbox register in the DPRAM */ +static void gpioirq(struct tasklet_struct *t) +{ + struct av7110 *av7110 = from_tasklet(av7110, t, gpio_tasklet); + u32 rxbuf, txbuf; + int len; + + if (av7110->debitype != -1) + /* we shouldn't get any irq while a debi xfer is running */ + printk("dvb-ttpci: GPIO0 irq oops @ %ld, psr:0x%08x, ssr:0x%08x\n", + jiffies, saa7146_read(av7110->dev, PSR), + saa7146_read(av7110->dev, SSR)); + + if (saa7146_wait_for_debi_done(av7110->dev, 0)) { + printk(KERN_ERR "%s: saa7146_wait_for_debi_done timed out\n", __func__); + BUG(); /* maybe we should try resetting the debi? */ + } + + spin_lock(&av7110->debilock); + ARM_ClearIrq(av7110); + + /* see what the av7110 wants */ + av7110->debitype = irdebi(av7110, DEBINOSWAP, IRQ_STATE, 0, 2); + av7110->debilen = irdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, 0, 2); + rxbuf = irdebi(av7110, DEBINOSWAP, RX_BUFF, 0, 2); + txbuf = irdebi(av7110, DEBINOSWAP, TX_BUFF, 0, 2); + len = (av7110->debilen + 3) & ~3; + + print_time("gpio"); + dprintk(8, "GPIO0 irq 0x%04x %d\n", av7110->debitype, av7110->debilen); + + switch (av7110->debitype & 0xff) { + + case DATA_TS_PLAY: + case DATA_PES_PLAY: + break; + + case DATA_MPEG_VIDEO_EVENT: + { + u32 h_ar; + struct video_event event; + + av7110->video_size.w = irdebi(av7110, DEBINOSWAP, STATUS_MPEG_WIDTH, 0, 2); + h_ar = irdebi(av7110, DEBINOSWAP, STATUS_MPEG_HEIGHT_AR, 0, 2); + + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, 0, 2); + iwdebi(av7110, DEBINOSWAP, RX_BUFF, 0, 2); + + av7110->video_size.h = h_ar & 0xfff; + + event.type = VIDEO_EVENT_SIZE_CHANGED; + event.u.size.w = av7110->video_size.w; + event.u.size.h = av7110->video_size.h; + switch ((h_ar >> 12) & 0xf) + { + case 3: + av7110->video_size.aspect_ratio = VIDEO_FORMAT_16_9; + event.u.size.aspect_ratio = VIDEO_FORMAT_16_9; + av7110->videostate.video_format = VIDEO_FORMAT_16_9; + break; + case 4: + av7110->video_size.aspect_ratio = VIDEO_FORMAT_221_1; + event.u.size.aspect_ratio = VIDEO_FORMAT_221_1; + av7110->videostate.video_format = VIDEO_FORMAT_221_1; + break; + default: + av7110->video_size.aspect_ratio = VIDEO_FORMAT_4_3; + event.u.size.aspect_ratio = VIDEO_FORMAT_4_3; + av7110->videostate.video_format = VIDEO_FORMAT_4_3; + } + + dprintk(8, "GPIO0 irq: DATA_MPEG_VIDEO_EVENT: w/h/ar = %u/%u/%u\n", + av7110->video_size.w, av7110->video_size.h, + av7110->video_size.aspect_ratio); + + dvb_video_add_event(av7110, &event); + break; + } + + case DATA_CI_PUT: + { + int avail; + struct dvb_ringbuffer *cibuf = &av7110->ci_wbuffer; + + avail = dvb_ringbuffer_avail(cibuf); + if (avail <= 2) { + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_LEN, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_BUFF, 0, 2); + break; + } + len = DVB_RINGBUFFER_PEEK(cibuf, 0) << 8; + len |= DVB_RINGBUFFER_PEEK(cibuf, 1); + if (avail < len + 2) { + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_LEN, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_BUFF, 0, 2); + break; + } + DVB_RINGBUFFER_SKIP(cibuf, 2); + + dvb_ringbuffer_read(cibuf, av7110->debi_virt, len); + + iwdebi(av7110, DEBINOSWAP, TX_LEN, len, 2); + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, len, 2); + dprintk(8, "DMA: CI\n"); + start_debi_dma(av7110, DEBI_WRITE, DPRAM_BASE + txbuf, len); + spin_unlock(&av7110->debilock); + wake_up(&cibuf->queue); + return; + } + + case DATA_MPEG_PLAY: + if (!av7110->playing) { + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_LEN, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_BUFF, 0, 2); + break; + } + len = 0; + if (av7110->debitype & 0x100) { + spin_lock(&av7110->aout.lock); + len = av7110_pes_play(av7110->debi_virt, &av7110->aout, 2048); + spin_unlock(&av7110->aout.lock); + } + if (len <= 0 && (av7110->debitype & 0x200) + &&av7110->videostate.play_state != VIDEO_FREEZED) { + spin_lock(&av7110->avout.lock); + len = av7110_pes_play(av7110->debi_virt, &av7110->avout, 2048); + spin_unlock(&av7110->avout.lock); + } + if (len <= 0) { + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_LEN, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_BUFF, 0, 2); + break; + } + dprintk(8, "GPIO0 PES_PLAY len=%04x\n", len); + iwdebi(av7110, DEBINOSWAP, TX_LEN, len, 2); + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, len, 2); + dprintk(8, "DMA: MPEG_PLAY\n"); + start_debi_dma(av7110, DEBI_WRITE, DPRAM_BASE + txbuf, len); + spin_unlock(&av7110->debilock); + return; + + case DATA_BMP_LOAD: + len = av7110->debilen; + dprintk(8, "gpio DATA_BMP_LOAD len %d\n", len); + if (!len) { + av7110->bmp_state = BMP_LOADED; + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_LEN, 0, 2); + iwdebi(av7110, DEBINOSWAP, TX_BUFF, 0, 2); + wake_up(&av7110->bmpq); + dprintk(8, "gpio DATA_BMP_LOAD done\n"); + break; + } + if (len > av7110->bmplen) + len = av7110->bmplen; + if (len > 2 * 1024) + len = 2 * 1024; + iwdebi(av7110, DEBINOSWAP, TX_LEN, len, 2); + iwdebi(av7110, DEBINOSWAP, IRQ_STATE_EXT, len, 2); + memcpy(av7110->debi_virt, av7110->bmpbuf+av7110->bmpp, len); + av7110->bmpp += len; + av7110->bmplen -= len; + dprintk(8, "gpio DATA_BMP_LOAD DMA len %d\n", len); + start_debi_dma(av7110, DEBI_WRITE, DPRAM_BASE+txbuf, len); + spin_unlock(&av7110->debilock); + return; + + case DATA_CI_GET: + case DATA_COMMON_INTERFACE: + case DATA_FSECTION: + case DATA_IPMPE: + case DATA_PIPING: + if (!len || len > 4 * 1024) { + iwdebi(av7110, DEBINOSWAP, RX_BUFF, 0, 2); + break; + } + fallthrough; + + case DATA_TS_RECORD: + case DATA_PES_RECORD: + dprintk(8, "DMA: TS_REC etc.\n"); + start_debi_dma(av7110, DEBI_READ, DPRAM_BASE+rxbuf, len); + spin_unlock(&av7110->debilock); + return; + + case DATA_DEBUG_MESSAGE: + if (!len || len > 0xff) { + iwdebi(av7110, DEBINOSWAP, RX_BUFF, 0, 2); + break; + } + start_debi_dma(av7110, DEBI_READ, Reserved, len); + spin_unlock(&av7110->debilock); + return; + + case DATA_IRCOMMAND: +#if IS_ENABLED(CONFIG_DVB_AV7110_IR) + av7110_ir_handler(av7110, + swahw32(irdebi(av7110, DEBINOSWAP, Reserved, + 0, 4))); +#endif + iwdebi(av7110, DEBINOSWAP, RX_BUFF, 0, 2); + break; + + default: + printk("dvb-ttpci: gpioirq unknown type=%d len=%d\n", + av7110->debitype, av7110->debilen); + break; + } + av7110->debitype = -1; + ARM_ClearMailBox(av7110); + spin_unlock(&av7110->debilock); +} + + +#ifdef CONFIG_DVB_AV7110_OSD +static int dvb_osd_ioctl(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + + dprintk(4, "%p\n", av7110); + + if (cmd == OSD_SEND_CMD) + return av7110_osd_cmd(av7110, (osd_cmd_t *) parg); + if (cmd == OSD_GET_CAPABILITY) + return av7110_osd_capability(av7110, (osd_cap_t *) parg); + + return -EINVAL; +} + + +static const struct file_operations dvb_osd_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = dvb_generic_ioctl, + .open = dvb_generic_open, + .release = dvb_generic_release, + .llseek = noop_llseek, +}; + +static struct dvb_device dvbdev_osd = { + .priv = NULL, + .users = 1, + .writers = 1, + .fops = &dvb_osd_fops, + .kernel_ioctl = dvb_osd_ioctl, +}; +#endif /* CONFIG_DVB_AV7110_OSD */ + + +static inline int SetPIDs(struct av7110 *av7110, u16 vpid, u16 apid, u16 ttpid, + u16 subpid, u16 pcrpid) +{ + u16 aflags = 0; + + dprintk(4, "%p\n", av7110); + + if (vpid == 0x1fff || apid == 0x1fff || + ttpid == 0x1fff || subpid == 0x1fff || pcrpid == 0x1fff) { + vpid = apid = ttpid = subpid = pcrpid = 0; + av7110->pids[DMX_PES_VIDEO] = 0; + av7110->pids[DMX_PES_AUDIO] = 0; + av7110->pids[DMX_PES_TELETEXT] = 0; + av7110->pids[DMX_PES_PCR] = 0; + } + + if (av7110->audiostate.bypass_mode) + aflags |= 0x8000; + + return av7110_fw_cmd(av7110, COMTYPE_PIDFILTER, MultiPID, 6, + pcrpid, vpid, apid, ttpid, subpid, aflags); +} + +int ChangePIDs(struct av7110 *av7110, u16 vpid, u16 apid, u16 ttpid, + u16 subpid, u16 pcrpid) +{ + int ret = 0; + dprintk(4, "%p\n", av7110); + + if (mutex_lock_interruptible(&av7110->pid_mutex)) + return -ERESTARTSYS; + + if (!(vpid & 0x8000)) + av7110->pids[DMX_PES_VIDEO] = vpid; + if (!(apid & 0x8000)) + av7110->pids[DMX_PES_AUDIO] = apid; + if (!(ttpid & 0x8000)) + av7110->pids[DMX_PES_TELETEXT] = ttpid; + if (!(pcrpid & 0x8000)) + av7110->pids[DMX_PES_PCR] = pcrpid; + + av7110->pids[DMX_PES_SUBTITLE] = 0; + + if (av7110->fe_synced) { + pcrpid = av7110->pids[DMX_PES_PCR]; + ret = SetPIDs(av7110, vpid, apid, ttpid, subpid, pcrpid); + } + + mutex_unlock(&av7110->pid_mutex); + return ret; +} + + +/****************************************************************************** + * hardware filter functions + ******************************************************************************/ + +static int StartHWFilter(struct dvb_demux_filter *dvbdmxfilter) +{ + struct dvb_demux_feed *dvbdmxfeed = dvbdmxfilter->feed; + struct av7110 *av7110 = dvbdmxfeed->demux->priv; + u16 buf[20]; + int ret, i; + u16 handle; +// u16 mode = 0x0320; + u16 mode = 0xb96a; + + dprintk(4, "%p\n", av7110); + + if (av7110->full_ts) + return 0; + + if (dvbdmxfilter->type == DMX_TYPE_SEC) { + if (hw_sections) { + buf[4] = (dvbdmxfilter->filter.filter_value[0] << 8) | + dvbdmxfilter->maskandmode[0]; + for (i = 3; i < 18; i++) + buf[i + 4 - 2] = + (dvbdmxfilter->filter.filter_value[i] << 8) | + dvbdmxfilter->maskandmode[i]; + mode = 4; + } + } else if ((dvbdmxfeed->ts_type & TS_PACKET) && + !(dvbdmxfeed->ts_type & TS_PAYLOAD_ONLY)) { + av7110_p2t_init(&av7110->p2t_filter[dvbdmxfilter->index], dvbdmxfeed); + } + + buf[0] = (COMTYPE_PID_FILTER << 8) + AddPIDFilter; + buf[1] = 16; + buf[2] = dvbdmxfeed->pid; + buf[3] = mode; + + ret = av7110_fw_request(av7110, buf, 20, &handle, 1); + if (ret != 0 || handle >= 32) { + printk(KERN_ERR "dvb-ttpci: %s error buf %04x %04x %04x %04x ret %d handle %04x\n", + __func__, buf[0], buf[1], buf[2], buf[3], + ret, handle); + dvbdmxfilter->hw_handle = 0xffff; + if (!ret) + ret = -1; + return ret; + } + + av7110->handle2filter[handle] = dvbdmxfilter; + dvbdmxfilter->hw_handle = handle; + + return ret; +} + +static int StopHWFilter(struct dvb_demux_filter *dvbdmxfilter) +{ + struct av7110 *av7110 = dvbdmxfilter->feed->demux->priv; + u16 buf[3]; + u16 answ[2]; + int ret; + u16 handle; + + dprintk(4, "%p\n", av7110); + + if (av7110->full_ts) + return 0; + + handle = dvbdmxfilter->hw_handle; + if (handle >= 32) { + printk("%s tried to stop invalid filter %04x, filter type = %x\n", + __func__, handle, dvbdmxfilter->type); + return -EINVAL; + } + + av7110->handle2filter[handle] = NULL; + + buf[0] = (COMTYPE_PID_FILTER << 8) + DelPIDFilter; + buf[1] = 1; + buf[2] = handle; + ret = av7110_fw_request(av7110, buf, 3, answ, 2); + if (ret != 0 || answ[1] != handle) { + printk(KERN_ERR "dvb-ttpci: %s error cmd %04x %04x %04x ret %x resp %04x %04x pid %d\n", + __func__, buf[0], buf[1], buf[2], ret, + answ[0], answ[1], dvbdmxfilter->feed->pid); + if (!ret) + ret = -1; + } + return ret; +} + + +static int dvb_feed_start_pid(struct dvb_demux_feed *dvbdmxfeed) +{ + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + struct av7110 *av7110 = dvbdmx->priv; + u16 *pid = dvbdmx->pids, npids[5]; + int i; + int ret = 0; + + dprintk(4, "%p\n", av7110); + + npids[0] = npids[1] = npids[2] = npids[3] = npids[4] = 0xffff; + i = dvbdmxfeed->pes_type; + npids[i] = (pid[i]&0x8000) ? 0 : pid[i]; + if ((i == 2) && npids[i] && (dvbdmxfeed->ts_type & TS_PACKET)) { + npids[i] = 0; + ret = ChangePIDs(av7110, npids[1], npids[0], npids[2], npids[3], npids[4]); + if (!ret) + ret = StartHWFilter(dvbdmxfeed->filter); + return ret; + } + if (dvbdmxfeed->pes_type <= 2 || dvbdmxfeed->pes_type == 4) { + ret = ChangePIDs(av7110, npids[1], npids[0], npids[2], npids[3], npids[4]); + if (ret) + return ret; + } + + if (dvbdmxfeed->pes_type < 2 && npids[0]) + if (av7110->fe_synced) + { + ret = av7110_fw_cmd(av7110, COMTYPE_PIDFILTER, Scan, 0); + if (ret) + return ret; + } + + if ((dvbdmxfeed->ts_type & TS_PACKET) && !av7110->full_ts) { + if (dvbdmxfeed->pes_type == 0 && !(dvbdmx->pids[0] & 0x8000)) + ret = av7110_av_start_record(av7110, RP_AUDIO, dvbdmxfeed); + if (dvbdmxfeed->pes_type == 1 && !(dvbdmx->pids[1] & 0x8000)) + ret = av7110_av_start_record(av7110, RP_VIDEO, dvbdmxfeed); + } + return ret; +} + +static int dvb_feed_stop_pid(struct dvb_demux_feed *dvbdmxfeed) +{ + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + struct av7110 *av7110 = dvbdmx->priv; + u16 *pid = dvbdmx->pids, npids[5]; + int i; + + int ret = 0; + + dprintk(4, "%p\n", av7110); + + if (dvbdmxfeed->pes_type <= 1) { + ret = av7110_av_stop(av7110, dvbdmxfeed->pes_type ? RP_VIDEO : RP_AUDIO); + if (ret) + return ret; + if (!av7110->rec_mode) + dvbdmx->recording = 0; + if (!av7110->playing) + dvbdmx->playing = 0; + } + npids[0] = npids[1] = npids[2] = npids[3] = npids[4] = 0xffff; + i = dvbdmxfeed->pes_type; + switch (i) { + case 2: //teletext + if (dvbdmxfeed->ts_type & TS_PACKET) + ret = StopHWFilter(dvbdmxfeed->filter); + npids[2] = 0; + break; + case 0: + case 1: + case 4: + if (!pids_off) + return 0; + npids[i] = (pid[i]&0x8000) ? 0 : pid[i]; + break; + } + if (!ret) + ret = ChangePIDs(av7110, npids[1], npids[0], npids[2], npids[3], npids[4]); + return ret; +} + +static int av7110_start_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct av7110 *av7110 = demux->priv; + int ret = 0; + + dprintk(4, "%p\n", av7110); + + if (!demux->dmx.frontend) + return -EINVAL; + + if (!av7110->full_ts && feed->pid > 0x1fff) + return -EINVAL; + + if (feed->type == DMX_TYPE_TS) { + if ((feed->ts_type & TS_DECODER) && + (feed->pes_type <= DMX_PES_PCR)) { + switch (demux->dmx.frontend->source) { + case DMX_MEMORY_FE: + if (feed->ts_type & TS_DECODER) + if (feed->pes_type < 2 && + !(demux->pids[0] & 0x8000) && + !(demux->pids[1] & 0x8000)) { + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->avout); + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->aout); + ret = av7110_av_start_play(av7110,RP_AV); + if (!ret) + demux->playing = 1; + } + break; + default: + ret = dvb_feed_start_pid(feed); + break; + } + } else if ((feed->ts_type & TS_PACKET) && + (demux->dmx.frontend->source != DMX_MEMORY_FE)) { + ret = StartHWFilter(feed->filter); + } + } + + if (av7110->full_ts) { + budget_start_feed(feed); + return ret; + } + + if (feed->type == DMX_TYPE_SEC) { + int i; + + for (i = 0; i < demux->filternum; i++) { + if (demux->filter[i].state != DMX_STATE_READY) + continue; + if (demux->filter[i].type != DMX_TYPE_SEC) + continue; + if (demux->filter[i].filter.parent != &feed->feed.sec) + continue; + demux->filter[i].state = DMX_STATE_GO; + if (demux->dmx.frontend->source != DMX_MEMORY_FE) { + ret = StartHWFilter(&demux->filter[i]); + if (ret) + break; + } + } + } + + return ret; +} + + +static int av7110_stop_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct av7110 *av7110 = demux->priv; + int i, rc, ret = 0; + dprintk(4, "%p\n", av7110); + + if (feed->type == DMX_TYPE_TS) { + if (feed->ts_type & TS_DECODER) { + if (feed->pes_type >= DMX_PES_OTHER || + !demux->pesfilter[feed->pes_type]) + return -EINVAL; + demux->pids[feed->pes_type] |= 0x8000; + demux->pesfilter[feed->pes_type] = NULL; + } + if (feed->ts_type & TS_DECODER && + feed->pes_type < DMX_PES_OTHER) { + ret = dvb_feed_stop_pid(feed); + } else + if ((feed->ts_type & TS_PACKET) && + (demux->dmx.frontend->source != DMX_MEMORY_FE)) + ret = StopHWFilter(feed->filter); + } + + if (av7110->full_ts) { + budget_stop_feed(feed); + return ret; + } + + if (feed->type == DMX_TYPE_SEC) { + for (i = 0; ifilternum; i++) { + if (demux->filter[i].state == DMX_STATE_GO && + demux->filter[i].filter.parent == &feed->feed.sec) { + demux->filter[i].state = DMX_STATE_READY; + if (demux->dmx.frontend->source != DMX_MEMORY_FE) { + rc = StopHWFilter(&demux->filter[i]); + if (!ret) + ret = rc; + /* keep going, stop as many filters as possible */ + } + } + } + } + + return ret; +} + + +static void restart_feeds(struct av7110 *av7110) +{ + struct dvb_demux *dvbdmx = &av7110->demux; + struct dvb_demux_feed *feed; + int mode; + int feeding; + int i, j; + + dprintk(4, "%p\n", av7110); + + mode = av7110->playing; + av7110->playing = 0; + av7110->rec_mode = 0; + + feeding = av7110->feeding1; /* full_ts mod */ + + for (i = 0; i < dvbdmx->feednum; i++) { + feed = &dvbdmx->feed[i]; + if (feed->state == DMX_STATE_GO) { + if (feed->type == DMX_TYPE_SEC) { + for (j = 0; j < dvbdmx->filternum; j++) { + if (dvbdmx->filter[j].type != DMX_TYPE_SEC) + continue; + if (dvbdmx->filter[j].filter.parent != &feed->feed.sec) + continue; + if (dvbdmx->filter[j].state == DMX_STATE_GO) + dvbdmx->filter[j].state = DMX_STATE_READY; + } + } + av7110_start_feed(feed); + } + } + + av7110->feeding1 = feeding; /* full_ts mod */ + + if (mode) + av7110_av_start_play(av7110, mode); +} + +static int dvb_get_stc(struct dmx_demux *demux, unsigned int num, + uint64_t *stc, unsigned int *base) +{ + int ret; + u16 fwstc[4]; + u16 tag = ((COMTYPE_REQUEST << 8) + ReqSTC); + struct dvb_demux *dvbdemux; + struct av7110 *av7110; + + /* pointer casting paranoia... */ + BUG_ON(!demux); + dvbdemux = demux->priv; + BUG_ON(!dvbdemux); + av7110 = dvbdemux->priv; + + dprintk(4, "%p\n", av7110); + + if (num != 0) + return -EINVAL; + + ret = av7110_fw_request(av7110, &tag, 0, fwstc, 4); + if (ret) { + printk(KERN_ERR "%s: av7110_fw_request error\n", __func__); + return ret; + } + dprintk(2, "fwstc = %04hx %04hx %04hx %04hx\n", + fwstc[0], fwstc[1], fwstc[2], fwstc[3]); + + *stc = (((uint64_t) ((fwstc[3] & 0x8000) >> 15)) << 32) | + (((uint64_t) fwstc[1]) << 16) | ((uint64_t) fwstc[0]); + *base = 1; + + dprintk(4, "stc = %lu\n", (unsigned long)*stc); + + return 0; +} + + +/****************************************************************************** + * SEC device file operations + ******************************************************************************/ + + +static int av7110_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) +{ + struct av7110* av7110 = fe->dvb->priv; + + switch (tone) { + case SEC_TONE_ON: + return Set22K(av7110, 1); + + case SEC_TONE_OFF: + return Set22K(av7110, 0); + + default: + return -EINVAL; + } +} + +static int av7110_diseqc_send_master_cmd(struct dvb_frontend* fe, + struct dvb_diseqc_master_cmd* cmd) +{ + struct av7110* av7110 = fe->dvb->priv; + + return av7110_diseqc_send(av7110, cmd->msg_len, cmd->msg, -1); +} + +static int av7110_diseqc_send_burst(struct dvb_frontend* fe, + enum fe_sec_mini_cmd minicmd) +{ + struct av7110* av7110 = fe->dvb->priv; + + return av7110_diseqc_send(av7110, 0, NULL, minicmd); +} + +/* simplified code from budget-core.c */ +static int stop_ts_capture(struct av7110 *budget) +{ + dprintk(2, "budget: %p\n", budget); + + if (--budget->feeding1) + return budget->feeding1; + saa7146_write(budget->dev, MC1, MASK_20); /* DMA3 off */ + SAA7146_IER_DISABLE(budget->dev, MASK_10); + SAA7146_ISR_CLEAR(budget->dev, MASK_10); + return 0; +} + +static int start_ts_capture(struct av7110 *budget) +{ + unsigned y; + + dprintk(2, "budget: %p\n", budget); + + if (budget->feeding1) + return ++budget->feeding1; + for (y = 0; y < TS_HEIGHT; y++) + memset(budget->grabbing + y * TS_WIDTH, 0x00, TS_WIDTH); + budget->ttbp = 0; + SAA7146_ISR_CLEAR(budget->dev, MASK_10); /* VPE */ + SAA7146_IER_ENABLE(budget->dev, MASK_10); /* VPE */ + saa7146_write(budget->dev, MC1, (MASK_04 | MASK_20)); /* DMA3 on */ + return ++budget->feeding1; +} + +static int budget_start_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct av7110 *budget = demux->priv; + int status; + + dprintk(2, "av7110: %p\n", budget); + + spin_lock(&budget->feedlock1); + feed->pusi_seen = false; /* have a clean section start */ + status = start_ts_capture(budget); + spin_unlock(&budget->feedlock1); + return status; +} + +static int budget_stop_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct av7110 *budget = demux->priv; + int status; + + dprintk(2, "budget: %p\n", budget); + + spin_lock(&budget->feedlock1); + status = stop_ts_capture(budget); + spin_unlock(&budget->feedlock1); + return status; +} + +static void vpeirq(struct tasklet_struct *t) +{ + struct av7110 *budget = from_tasklet(budget, t, vpe_tasklet); + u8 *mem = (u8 *) (budget->grabbing); + u32 olddma = budget->ttbp; + u32 newdma = saa7146_read(budget->dev, PCI_VDP3); + struct dvb_demux *demux = budget->full_ts ? &budget->demux : &budget->demux1; + + /* nearest lower position divisible by 188 */ + newdma -= newdma % 188; + + if (newdma >= TS_BUFLEN) + return; + + budget->ttbp = newdma; + + if (!budget->feeding1 || (newdma == olddma)) + return; + + /* Ensure streamed PCI data is synced to CPU */ + dma_sync_sg_for_cpu(&budget->dev->pci->dev, budget->pt.slist, + budget->pt.nents, DMA_FROM_DEVICE); + +#if 0 + /* track rps1 activity */ + printk("vpeirq: %02x Event Counter 1 0x%04x\n", + mem[olddma], + saa7146_read(budget->dev, EC1R) & 0x3fff); +#endif + + if (newdma > olddma) + /* no wraparound, dump olddma..newdma */ + dvb_dmx_swfilter_packets(demux, mem + olddma, (newdma - olddma) / 188); + else { + /* wraparound, dump olddma..buflen and 0..newdma */ + dvb_dmx_swfilter_packets(demux, mem + olddma, (TS_BUFLEN - olddma) / 188); + dvb_dmx_swfilter_packets(demux, mem, newdma / 188); + } +} + +static int av7110_register(struct av7110 *av7110) +{ + int ret, i; + struct dvb_demux *dvbdemux = &av7110->demux; + struct dvb_demux *dvbdemux1 = &av7110->demux1; + + dprintk(4, "%p\n", av7110); + + if (av7110->registered) + return -1; + + av7110->registered = 1; + + dvbdemux->priv = (void *) av7110; + + for (i = 0; i < 32; i++) + av7110->handle2filter[i] = NULL; + + dvbdemux->filternum = (av7110->full_ts) ? 256 : 32; + dvbdemux->feednum = (av7110->full_ts) ? 256 : 32; + dvbdemux->start_feed = av7110_start_feed; + dvbdemux->stop_feed = av7110_stop_feed; + dvbdemux->write_to_decoder = av7110_write_to_decoder; + dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | DMX_SECTION_FILTERING | + DMX_MEMORY_BASED_FILTERING); + + dvb_dmx_init(&av7110->demux); + av7110->demux.dmx.get_stc = dvb_get_stc; + + av7110->dmxdev.filternum = (av7110->full_ts) ? 256 : 32; + av7110->dmxdev.demux = &dvbdemux->dmx; + av7110->dmxdev.capabilities = 0; + + dvb_dmxdev_init(&av7110->dmxdev, &av7110->dvb_adapter); + + av7110->hw_frontend.source = DMX_FRONTEND_0; + + ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &av7110->hw_frontend); + + if (ret < 0) + return ret; + + av7110->mem_frontend.source = DMX_MEMORY_FE; + + ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &av7110->mem_frontend); + + if (ret < 0) + return ret; + + ret = dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, + &av7110->hw_frontend); + if (ret < 0) + return ret; + + av7110_av_register(av7110); + av7110_ca_register(av7110); + +#ifdef CONFIG_DVB_AV7110_OSD + dvb_register_device(&av7110->dvb_adapter, &av7110->osd_dev, + &dvbdev_osd, av7110, DVB_DEVICE_OSD, 0); +#endif + + dvb_net_init(&av7110->dvb_adapter, &av7110->dvb_net, &dvbdemux->dmx); + + if (budgetpatch) { + /* initialize software demux1 without its own frontend + * demux1 hardware is connected to frontend0 of demux0 + */ + dvbdemux1->priv = (void *) av7110; + + dvbdemux1->filternum = 256; + dvbdemux1->feednum = 256; + dvbdemux1->start_feed = budget_start_feed; + dvbdemux1->stop_feed = budget_stop_feed; + dvbdemux1->write_to_decoder = NULL; + + dvbdemux1->dmx.capabilities = (DMX_TS_FILTERING | DMX_SECTION_FILTERING | + DMX_MEMORY_BASED_FILTERING); + + dvb_dmx_init(&av7110->demux1); + + av7110->dmxdev1.filternum = 256; + av7110->dmxdev1.demux = &dvbdemux1->dmx; + av7110->dmxdev1.capabilities = 0; + + dvb_dmxdev_init(&av7110->dmxdev1, &av7110->dvb_adapter); + + dvb_net_init(&av7110->dvb_adapter, &av7110->dvb_net1, &dvbdemux1->dmx); + printk("dvb-ttpci: additional demux1 for budget-patch registered\n"); + } + return 0; +} + + +static void dvb_unregister(struct av7110 *av7110) +{ + struct dvb_demux *dvbdemux = &av7110->demux; + struct dvb_demux *dvbdemux1 = &av7110->demux1; + + dprintk(4, "%p\n", av7110); + + if (!av7110->registered) + return; + + if (budgetpatch) { + dvb_net_release(&av7110->dvb_net1); + dvbdemux->dmx.close(&dvbdemux1->dmx); + dvb_dmxdev_release(&av7110->dmxdev1); + dvb_dmx_release(&av7110->demux1); + } + + dvb_net_release(&av7110->dvb_net); + + dvbdemux->dmx.close(&dvbdemux->dmx); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &av7110->hw_frontend); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &av7110->mem_frontend); + + dvb_dmxdev_release(&av7110->dmxdev); + dvb_dmx_release(&av7110->demux); + + if (av7110->fe != NULL) { + dvb_unregister_frontend(av7110->fe); + dvb_frontend_detach(av7110->fe); + } + dvb_unregister_device(av7110->osd_dev); + av7110_av_unregister(av7110); + av7110_ca_unregister(av7110); +} + + +/**************************************************************************** + * I2C client commands + ****************************************************************************/ + +int i2c_writereg(struct av7110 *av7110, u8 id, u8 reg, u8 val) +{ + u8 msg[2] = { reg, val }; + struct i2c_msg msgs; + + msgs.flags = 0; + msgs.addr = id / 2; + msgs.len = 2; + msgs.buf = msg; + return i2c_transfer(&av7110->i2c_adap, &msgs, 1); +} + +u8 i2c_readreg(struct av7110 *av7110, u8 id, u8 reg) +{ + u8 mm1[] = {0x00}; + u8 mm2[] = {0x00}; + struct i2c_msg msgs[2]; + + msgs[0].flags = 0; + msgs[1].flags = I2C_M_RD; + msgs[0].addr = msgs[1].addr = id / 2; + mm1[0] = reg; + msgs[0].len = 1; msgs[1].len = 1; + msgs[0].buf = mm1; msgs[1].buf = mm2; + i2c_transfer(&av7110->i2c_adap, msgs, 2); + + return mm2[0]; +} + +/**************************************************************************** + * INITIALIZATION + ****************************************************************************/ + + +static int check_firmware(struct av7110* av7110) +{ + u32 crc = 0, len = 0; + unsigned char *ptr; + + /* check for firmware magic */ + ptr = av7110->bin_fw; + if (ptr[0] != 'A' || ptr[1] != 'V' || + ptr[2] != 'F' || ptr[3] != 'W') { + printk("dvb-ttpci: this is not an av7110 firmware\n"); + return -EINVAL; + } + ptr += 4; + + /* check dpram file */ + crc = get_unaligned_be32(ptr); + ptr += 4; + len = get_unaligned_be32(ptr); + ptr += 4; + if (len >= 512) { + printk("dvb-ttpci: dpram file is way too big.\n"); + return -EINVAL; + } + if (crc != crc32_le(0, ptr, len)) { + printk("dvb-ttpci: crc32 of dpram file does not match.\n"); + return -EINVAL; + } + av7110->bin_dpram = ptr; + av7110->size_dpram = len; + ptr += len; + + /* check root file */ + crc = get_unaligned_be32(ptr); + ptr += 4; + len = get_unaligned_be32(ptr); + ptr += 4; + + if (len <= 200000 || len >= 300000 || + len > ((av7110->bin_fw + av7110->size_fw) - ptr)) { + printk("dvb-ttpci: root file has strange size (%d). aborting.\n", len); + return -EINVAL; + } + if( crc != crc32_le(0, ptr, len)) { + printk("dvb-ttpci: crc32 of root file does not match.\n"); + return -EINVAL; + } + av7110->bin_root = ptr; + av7110->size_root = len; + return 0; +} + +static void put_firmware(struct av7110* av7110) +{ + vfree(av7110->bin_fw); +} + +static int get_firmware(struct av7110* av7110) +{ + int ret; + const struct firmware *fw; + + /* request the av7110 firmware, this will block until someone uploads it */ + ret = request_firmware(&fw, "dvb-ttpci-01.fw", &av7110->dev->pci->dev); + if (ret) { + if (ret == -ENOENT) { + printk(KERN_ERR "dvb-ttpci: could not load firmware, file not found: dvb-ttpci-01.fw\n"); + printk(KERN_ERR "dvb-ttpci: usually this should be in /usr/lib/hotplug/firmware or /lib/firmware\n"); + printk(KERN_ERR "dvb-ttpci: and can be downloaded from https://linuxtv.org/download/dvb/firmware/\n"); + } else + printk(KERN_ERR "dvb-ttpci: cannot request firmware (error %i)\n", + ret); + return -EINVAL; + } + + if (fw->size <= 200000) { + printk("dvb-ttpci: this firmware is way too small.\n"); + release_firmware(fw); + return -EINVAL; + } + + /* check if the firmware is available */ + av7110->bin_fw = vmalloc(fw->size); + if (NULL == av7110->bin_fw) { + dprintk(1, "out of memory\n"); + release_firmware(fw); + return -ENOMEM; + } + + memcpy(av7110->bin_fw, fw->data, fw->size); + av7110->size_fw = fw->size; + if ((ret = check_firmware(av7110))) + vfree(av7110->bin_fw); + + release_firmware(fw); + return ret; +} + +static int alps_bsrv2_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct av7110* av7110 = fe->dvb->priv; + u8 pwr = 0; + u8 buf[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) }; + u32 div = (p->frequency + 479500) / 125; + + if (p->frequency > 2000000) + pwr = 3; + else if (p->frequency > 1800000) + pwr = 2; + else if (p->frequency > 1600000) + pwr = 1; + else if (p->frequency > 1200000) + pwr = 0; + else if (p->frequency >= 1100000) + pwr = 1; + else + pwr = 2; + + buf[0] = (div >> 8) & 0x7f; + buf[1] = div & 0xff; + buf[2] = ((div & 0x18000) >> 10) | 0x95; + buf[3] = (pwr << 6) | 0x30; + + // NOTE: since we're using a prescaler of 2, we set the + // divisor frequency to 62.5kHz and divide by 125 above + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&av7110->i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static struct ves1x93_config alps_bsrv2_config = { + .demod_address = 0x08, + .xin = 90100000UL, + .invert_pwm = 0, +}; + +static int alps_tdbe2_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct av7110* av7110 = fe->dvb->priv; + u32 div; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x62, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = (p->frequency + 35937500 + 31250) / 62500; + + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0x85 | ((div >> 10) & 0x60); + data[3] = (p->frequency < 174000000 ? 0x88 : p->frequency < 470000000 ? 0x84 : 0x81); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&av7110->i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static struct ves1820_config alps_tdbe2_config = { + .demod_address = 0x09, + .xin = 57840000UL, + .invert = 1, + .selagc = VES1820_SELAGC_SIGNAMPERR, +}; + + + + +static int grundig_29504_451_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct av7110* av7110 = fe->dvb->priv; + u32 div; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = p->frequency / 125; + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0x8e; + data[3] = 0x00; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&av7110->i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static struct tda8083_config grundig_29504_451_config = { + .demod_address = 0x68, +}; + + + +static int philips_cd1516_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct av7110* av7110 = fe->dvb->priv; + u32 div; + u32 f = p->frequency; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = (f + 36125000 + 31250) / 62500; + + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0x8e; + data[3] = (f < 174000000 ? 0xa1 : f < 470000000 ? 0x92 : 0x34); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&av7110->i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static struct ves1820_config philips_cd1516_config = { + .demod_address = 0x09, + .xin = 57840000UL, + .invert = 1, + .selagc = VES1820_SELAGC_SIGNAMPERR, +}; + + + +static int alps_tdlb7_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct av7110* av7110 = fe->dvb->priv; + u32 div, pwr; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x60, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = (p->frequency + 36200000) / 166666; + + if (p->frequency <= 782000000) + pwr = 1; + else + pwr = 2; + + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0x85; + data[3] = pwr << 6; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&av7110->i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int alps_tdlb7_request_firmware(struct dvb_frontend* fe, const struct firmware **fw, char* name) +{ +#if IS_ENABLED(CONFIG_DVB_SP8870) + struct av7110* av7110 = fe->dvb->priv; + + return request_firmware(fw, name, &av7110->dev->pci->dev); +#else + return -EINVAL; +#endif +} + +static const struct sp8870_config alps_tdlb7_config = { + + .demod_address = 0x71, + .request_firmware = alps_tdlb7_request_firmware, +}; + + +static u8 nexusca_stv0297_inittab[] = { + 0x80, 0x01, + 0x80, 0x00, + 0x81, 0x01, + 0x81, 0x00, + 0x00, 0x09, + 0x01, 0x69, + 0x03, 0x00, + 0x04, 0x00, + 0x07, 0x00, + 0x08, 0x00, + 0x20, 0x00, + 0x21, 0x40, + 0x22, 0x00, + 0x23, 0x00, + 0x24, 0x40, + 0x25, 0x88, + 0x30, 0xff, + 0x31, 0x00, + 0x32, 0xff, + 0x33, 0x00, + 0x34, 0x50, + 0x35, 0x7f, + 0x36, 0x00, + 0x37, 0x20, + 0x38, 0x00, + 0x40, 0x1c, + 0x41, 0xff, + 0x42, 0x29, + 0x43, 0x00, + 0x44, 0xff, + 0x45, 0x00, + 0x46, 0x00, + 0x49, 0x04, + 0x4a, 0x00, + 0x4b, 0x7b, + 0x52, 0x30, + 0x55, 0xae, + 0x56, 0x47, + 0x57, 0xe1, + 0x58, 0x3a, + 0x5a, 0x1e, + 0x5b, 0x34, + 0x60, 0x00, + 0x63, 0x00, + 0x64, 0x00, + 0x65, 0x00, + 0x66, 0x00, + 0x67, 0x00, + 0x68, 0x00, + 0x69, 0x00, + 0x6a, 0x02, + 0x6b, 0x00, + 0x70, 0xff, + 0x71, 0x00, + 0x72, 0x00, + 0x73, 0x00, + 0x74, 0x0c, + 0x80, 0x00, + 0x81, 0x00, + 0x82, 0x00, + 0x83, 0x00, + 0x84, 0x04, + 0x85, 0x80, + 0x86, 0x24, + 0x87, 0x78, + 0x88, 0x10, + 0x89, 0x00, + 0x90, 0x01, + 0x91, 0x01, + 0xa0, 0x04, + 0xa1, 0x00, + 0xa2, 0x00, + 0xb0, 0x91, + 0xb1, 0x0b, + 0xc0, 0x53, + 0xc1, 0x70, + 0xc2, 0x12, + 0xd0, 0x00, + 0xd1, 0x00, + 0xd2, 0x00, + 0xd3, 0x00, + 0xd4, 0x00, + 0xd5, 0x00, + 0xde, 0x00, + 0xdf, 0x00, + 0x61, 0x49, + 0x62, 0x0b, + 0x53, 0x08, + 0x59, 0x08, + 0xff, 0xff, +}; + +static int nexusca_stv0297_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct av7110* av7110 = fe->dvb->priv; + u32 div; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x63, .flags = 0, .buf = data, .len = sizeof(data) }; + struct i2c_msg readmsg = { .addr = 0x63, .flags = I2C_M_RD, .buf = data, .len = 1 }; + int i; + + div = (p->frequency + 36150000 + 31250) / 62500; + + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0xce; + + if (p->frequency < 45000000) + return -EINVAL; + else if (p->frequency < 137000000) + data[3] = 0x01; + else if (p->frequency < 403000000) + data[3] = 0x02; + else if (p->frequency < 860000000) + data[3] = 0x04; + else + return -EINVAL; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&av7110->i2c_adap, &msg, 1) != 1) { + printk("nexusca: pll transfer failed!\n"); + return -EIO; + } + + // wait for PLL lock + for(i = 0; i < 20; i++) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&av7110->i2c_adap, &readmsg, 1) == 1) + if (data[0] & 0x40) break; + msleep(10); + } + + return 0; +} + +static struct stv0297_config nexusca_stv0297_config = { + + .demod_address = 0x1C, + .inittab = nexusca_stv0297_inittab, + .invert = 1, + .stop_during_read = 1, +}; + + + +static int grundig_29504_401_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct av7110* av7110 = fe->dvb->priv; + u32 div; + u8 cfg, cpump, band_select; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = (36125000 + p->frequency) / 166666; + + cfg = 0x88; + + if (p->frequency < 175000000) + cpump = 2; + else if (p->frequency < 390000000) + cpump = 1; + else if (p->frequency < 470000000) + cpump = 2; + else if (p->frequency < 750000000) + cpump = 1; + else + cpump = 3; + + if (p->frequency < 175000000) + band_select = 0x0e; + else if (p->frequency < 470000000) + band_select = 0x05; + else + band_select = 0x03; + + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = ((div >> 10) & 0x60) | cfg; + data[3] = (cpump << 6) | band_select; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&av7110->i2c_adap, &msg, 1) != 1) return -EIO; + return 0; +} + +static struct l64781_config grundig_29504_401_config = { + .demod_address = 0x55, +}; + + + +static int av7110_fe_lock_fix(struct av7110 *av7110, enum fe_status status) +{ + int ret = 0; + int synced = (status & FE_HAS_LOCK) ? 1 : 0; + + av7110->fe_status = status; + + if (av7110->fe_synced == synced) + return 0; + + if (av7110->playing) { + av7110->fe_synced = synced; + return 0; + } + + if (mutex_lock_interruptible(&av7110->pid_mutex)) + return -ERESTARTSYS; + + if (synced) { + ret = SetPIDs(av7110, av7110->pids[DMX_PES_VIDEO], + av7110->pids[DMX_PES_AUDIO], + av7110->pids[DMX_PES_TELETEXT], 0, + av7110->pids[DMX_PES_PCR]); + if (!ret) + ret = av7110_fw_cmd(av7110, COMTYPE_PIDFILTER, Scan, 0); + } else { + ret = SetPIDs(av7110, 0, 0, 0, 0, 0); + if (!ret) { + ret = av7110_fw_cmd(av7110, COMTYPE_PID_FILTER, FlushTSQueue, 0); + if (!ret) + ret = av7110_wait_msgstate(av7110, GPMQBusy); + } + } + + if (!ret) + av7110->fe_synced = synced; + + mutex_unlock(&av7110->pid_mutex); + return ret; +} + +static int av7110_fe_set_frontend(struct dvb_frontend *fe) +{ + struct av7110* av7110 = fe->dvb->priv; + + int ret = av7110_fe_lock_fix(av7110, 0); + if (!ret) + ret = av7110->fe_set_frontend(fe); + + return ret; +} + +static int av7110_fe_init(struct dvb_frontend* fe) +{ + struct av7110* av7110 = fe->dvb->priv; + + int ret = av7110_fe_lock_fix(av7110, 0); + if (!ret) + ret = av7110->fe_init(fe); + return ret; +} + +static int av7110_fe_read_status(struct dvb_frontend *fe, + enum fe_status *status) +{ + struct av7110* av7110 = fe->dvb->priv; + + /* call the real implementation */ + int ret = av7110->fe_read_status(fe, status); + if (!ret) + if (((*status ^ av7110->fe_status) & FE_HAS_LOCK) && (*status & FE_HAS_LOCK)) + ret = av7110_fe_lock_fix(av7110, *status); + return ret; +} + +static int av7110_fe_diseqc_reset_overload(struct dvb_frontend* fe) +{ + struct av7110* av7110 = fe->dvb->priv; + + int ret = av7110_fe_lock_fix(av7110, 0); + if (!ret) + ret = av7110->fe_diseqc_reset_overload(fe); + return ret; +} + +static int av7110_fe_diseqc_send_master_cmd(struct dvb_frontend* fe, + struct dvb_diseqc_master_cmd* cmd) +{ + struct av7110* av7110 = fe->dvb->priv; + + int ret = av7110_fe_lock_fix(av7110, 0); + if (!ret) { + av7110->saved_master_cmd = *cmd; + ret = av7110->fe_diseqc_send_master_cmd(fe, cmd); + } + return ret; +} + +static int av7110_fe_diseqc_send_burst(struct dvb_frontend *fe, + enum fe_sec_mini_cmd minicmd) +{ + struct av7110* av7110 = fe->dvb->priv; + + int ret = av7110_fe_lock_fix(av7110, 0); + if (!ret) { + av7110->saved_minicmd = minicmd; + ret = av7110->fe_diseqc_send_burst(fe, minicmd); + } + return ret; +} + +static int av7110_fe_set_tone(struct dvb_frontend *fe, + enum fe_sec_tone_mode tone) +{ + struct av7110* av7110 = fe->dvb->priv; + + int ret = av7110_fe_lock_fix(av7110, 0); + if (!ret) { + av7110->saved_tone = tone; + ret = av7110->fe_set_tone(fe, tone); + } + return ret; +} + +static int av7110_fe_set_voltage(struct dvb_frontend *fe, + enum fe_sec_voltage voltage) +{ + struct av7110* av7110 = fe->dvb->priv; + + int ret = av7110_fe_lock_fix(av7110, 0); + if (!ret) { + av7110->saved_voltage = voltage; + ret = av7110->fe_set_voltage(fe, voltage); + } + return ret; +} + +static int av7110_fe_dishnetwork_send_legacy_command(struct dvb_frontend* fe, unsigned long cmd) +{ + struct av7110* av7110 = fe->dvb->priv; + + int ret = av7110_fe_lock_fix(av7110, 0); + if (!ret) + ret = av7110->fe_dishnetwork_send_legacy_command(fe, cmd); + return ret; +} + +static void dvb_s_recover(struct av7110* av7110) +{ + av7110_fe_init(av7110->fe); + + av7110_fe_set_voltage(av7110->fe, av7110->saved_voltage); + if (av7110->saved_master_cmd.msg_len) { + msleep(20); + av7110_fe_diseqc_send_master_cmd(av7110->fe, &av7110->saved_master_cmd); + } + msleep(20); + av7110_fe_diseqc_send_burst(av7110->fe, av7110->saved_minicmd); + msleep(20); + av7110_fe_set_tone(av7110->fe, av7110->saved_tone); + + av7110_fe_set_frontend(av7110->fe); +} + +static u8 read_pwm(struct av7110* av7110) +{ + u8 b = 0xff; + u8 pwm; + struct i2c_msg msg[] = { { .addr = 0x50,.flags = 0,.buf = &b,.len = 1 }, + { .addr = 0x50,.flags = I2C_M_RD,.buf = &pwm,.len = 1} }; + + if ((i2c_transfer(&av7110->i2c_adap, msg, 2) != 2) || (pwm == 0xff)) + pwm = 0x48; + + return pwm; +} + +static int frontend_init(struct av7110 *av7110) +{ + int ret; + + if (av7110->dev->pci->subsystem_vendor == 0x110a) { + switch(av7110->dev->pci->subsystem_device) { + case 0x0000: // Fujitsu/Siemens DVB-Cable (ves1820/Philips CD1516(??)) + av7110->fe = dvb_attach(ves1820_attach, &philips_cd1516_config, + &av7110->i2c_adap, read_pwm(av7110)); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = philips_cd1516_tuner_set_params; + } + break; + } + + } else if (av7110->dev->pci->subsystem_vendor == 0x13c2) { + switch(av7110->dev->pci->subsystem_device) { + case 0x0000: // Hauppauge/TT WinTV DVB-S rev1.X + case 0x0003: // Hauppauge/TT WinTV Nexus-S Rev 2.X + case 0x1002: // Hauppauge/TT WinTV DVB-S rev1.3SE + + // try the ALPS BSRV2 first of all + av7110->fe = dvb_attach(ves1x93_attach, &alps_bsrv2_config, &av7110->i2c_adap); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = alps_bsrv2_tuner_set_params; + av7110->fe->ops.diseqc_send_master_cmd = av7110_diseqc_send_master_cmd; + av7110->fe->ops.diseqc_send_burst = av7110_diseqc_send_burst; + av7110->fe->ops.set_tone = av7110_set_tone; + av7110->recover = dvb_s_recover; + break; + } + + // try the ALPS BSRU6 now + av7110->fe = dvb_attach(stv0299_attach, &alps_bsru6_config, &av7110->i2c_adap); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params; + av7110->fe->tuner_priv = &av7110->i2c_adap; + + av7110->fe->ops.diseqc_send_master_cmd = av7110_diseqc_send_master_cmd; + av7110->fe->ops.diseqc_send_burst = av7110_diseqc_send_burst; + av7110->fe->ops.set_tone = av7110_set_tone; + av7110->recover = dvb_s_recover; + break; + } + + // Try the grundig 29504-451 + av7110->fe = dvb_attach(tda8083_attach, &grundig_29504_451_config, &av7110->i2c_adap); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = grundig_29504_451_tuner_set_params; + av7110->fe->ops.diseqc_send_master_cmd = av7110_diseqc_send_master_cmd; + av7110->fe->ops.diseqc_send_burst = av7110_diseqc_send_burst; + av7110->fe->ops.set_tone = av7110_set_tone; + av7110->recover = dvb_s_recover; + break; + } + + /* Try DVB-C cards */ + switch(av7110->dev->pci->subsystem_device) { + case 0x0000: + /* Siemens DVB-C (full-length card) VES1820/Philips CD1516 */ + av7110->fe = dvb_attach(ves1820_attach, &philips_cd1516_config, &av7110->i2c_adap, + read_pwm(av7110)); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = philips_cd1516_tuner_set_params; + } + break; + case 0x0003: + /* Hauppauge DVB-C 2.1 VES1820/ALPS TDBE2 */ + av7110->fe = dvb_attach(ves1820_attach, &alps_tdbe2_config, &av7110->i2c_adap, + read_pwm(av7110)); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = alps_tdbe2_tuner_set_params; + } + break; + } + break; + + case 0x0001: // Hauppauge/TT Nexus-T premium rev1.X + { + struct dvb_frontend *fe; + + // try ALPS TDLB7 first, then Grundig 29504-401 + fe = dvb_attach(sp8870_attach, &alps_tdlb7_config, &av7110->i2c_adap); + if (fe) { + fe->ops.tuner_ops.set_params = alps_tdlb7_tuner_set_params; + av7110->fe = fe; + break; + } + } + fallthrough; + + case 0x0008: // Hauppauge/TT DVB-T + // Grundig 29504-401 + av7110->fe = dvb_attach(l64781_attach, &grundig_29504_401_config, &av7110->i2c_adap); + if (av7110->fe) + av7110->fe->ops.tuner_ops.set_params = grundig_29504_401_tuner_set_params; + break; + + case 0x0002: // Hauppauge/TT DVB-C premium rev2.X + + av7110->fe = dvb_attach(ves1820_attach, &alps_tdbe2_config, &av7110->i2c_adap, read_pwm(av7110)); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = alps_tdbe2_tuner_set_params; + } + break; + + case 0x0004: // Galaxis DVB-S rev1.3 + /* ALPS BSRV2 */ + av7110->fe = dvb_attach(ves1x93_attach, &alps_bsrv2_config, &av7110->i2c_adap); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = alps_bsrv2_tuner_set_params; + av7110->fe->ops.diseqc_send_master_cmd = av7110_diseqc_send_master_cmd; + av7110->fe->ops.diseqc_send_burst = av7110_diseqc_send_burst; + av7110->fe->ops.set_tone = av7110_set_tone; + av7110->recover = dvb_s_recover; + } + break; + + case 0x0006: /* Fujitsu-Siemens DVB-S rev 1.6 */ + /* Grundig 29504-451 */ + av7110->fe = dvb_attach(tda8083_attach, &grundig_29504_451_config, &av7110->i2c_adap); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = grundig_29504_451_tuner_set_params; + av7110->fe->ops.diseqc_send_master_cmd = av7110_diseqc_send_master_cmd; + av7110->fe->ops.diseqc_send_burst = av7110_diseqc_send_burst; + av7110->fe->ops.set_tone = av7110_set_tone; + av7110->recover = dvb_s_recover; + } + break; + + case 0x000A: // Hauppauge/TT Nexus-CA rev1.X + + av7110->fe = dvb_attach(stv0297_attach, &nexusca_stv0297_config, &av7110->i2c_adap); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = nexusca_stv0297_tuner_set_params; + + /* set TDA9819 into DVB mode */ + saa7146_setgpio(av7110->dev, 1, SAA7146_GPIO_OUTLO); // TDA9819 pin9(STD) + saa7146_setgpio(av7110->dev, 3, SAA7146_GPIO_OUTLO); // TDA9819 pin30(VIF) + + /* tuner on this needs a slower i2c bus speed */ + av7110->dev->i2c_bitrate = SAA7146_I2C_BUS_BIT_RATE_240; + break; + } + break; + + case 0x000E: /* Hauppauge/TT Nexus-S rev 2.3 */ + /* ALPS BSBE1 */ + av7110->fe = dvb_attach(stv0299_attach, &alps_bsbe1_config, &av7110->i2c_adap); + if (av7110->fe) { + av7110->fe->ops.tuner_ops.set_params = alps_bsbe1_tuner_set_params; + av7110->fe->tuner_priv = &av7110->i2c_adap; + + if (dvb_attach(lnbp21_attach, av7110->fe, &av7110->i2c_adap, 0, 0) == NULL) { + printk("dvb-ttpci: LNBP21 not found!\n"); + if (av7110->fe->ops.release) + av7110->fe->ops.release(av7110->fe); + av7110->fe = NULL; + } else { + av7110->fe->ops.dishnetwork_send_legacy_command = NULL; + av7110->recover = dvb_s_recover; + } + } + break; + } + } + + if (!av7110->fe) { + /* FIXME: propagate the failure code from the lower layers */ + ret = -ENOMEM; + printk("dvb-ttpci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n", + av7110->dev->pci->vendor, + av7110->dev->pci->device, + av7110->dev->pci->subsystem_vendor, + av7110->dev->pci->subsystem_device); + } else { + FE_FUNC_OVERRIDE(av7110->fe->ops.init, av7110->fe_init, av7110_fe_init); + FE_FUNC_OVERRIDE(av7110->fe->ops.read_status, av7110->fe_read_status, av7110_fe_read_status); + FE_FUNC_OVERRIDE(av7110->fe->ops.diseqc_reset_overload, av7110->fe_diseqc_reset_overload, av7110_fe_diseqc_reset_overload); + FE_FUNC_OVERRIDE(av7110->fe->ops.diseqc_send_master_cmd, av7110->fe_diseqc_send_master_cmd, av7110_fe_diseqc_send_master_cmd); + FE_FUNC_OVERRIDE(av7110->fe->ops.diseqc_send_burst, av7110->fe_diseqc_send_burst, av7110_fe_diseqc_send_burst); + FE_FUNC_OVERRIDE(av7110->fe->ops.set_tone, av7110->fe_set_tone, av7110_fe_set_tone); + FE_FUNC_OVERRIDE(av7110->fe->ops.set_voltage, av7110->fe_set_voltage, av7110_fe_set_voltage); + FE_FUNC_OVERRIDE(av7110->fe->ops.dishnetwork_send_legacy_command, av7110->fe_dishnetwork_send_legacy_command, av7110_fe_dishnetwork_send_legacy_command); + FE_FUNC_OVERRIDE(av7110->fe->ops.set_frontend, av7110->fe_set_frontend, av7110_fe_set_frontend); + + ret = dvb_register_frontend(&av7110->dvb_adapter, av7110->fe); + if (ret < 0) { + printk("av7110: Frontend registration failed!\n"); + dvb_frontend_detach(av7110->fe); + av7110->fe = NULL; + } + } + return ret; +} + +/* Budgetpatch note: + * Original hardware design by Roberto Deza: + * There is a DVB_Wiki at + * https://linuxtv.org + * + * New software triggering design by Emard that works on + * original Roberto Deza's hardware: + * + * rps1 code for budgetpatch will copy internal HS event to GPIO3 pin. + * GPIO3 is in budget-patch hardware connectd to port B VSYNC + * HS is an internal event of 7146, accessible with RPS + * and temporarily raised high every n lines + * (n in defined in the RPS_THRESH1 counter threshold) + * I think HS is raised high on the beginning of the n-th line + * and remains high until this n-th line that triggered + * it is completely received. When the reception of n-th line + * ends, HS is lowered. + * + * To transmit data over DMA, 7146 needs changing state at + * port B VSYNC pin. Any changing of port B VSYNC will + * cause some DMA data transfer, with more or less packets loss. + * It depends on the phase and frequency of VSYNC and + * the way of 7146 is instructed to trigger on port B (defined + * in DD1_INIT register, 3rd nibble from the right valid + * numbers are 0-7, see datasheet) + * + * The correct triggering can minimize packet loss, + * dvbtraffic should give this stable bandwidths: + * 22k transponder = 33814 kbit/s + * 27.5k transponder = 38045 kbit/s + * by experiment it is found that the best results + * (stable bandwidths and almost no packet loss) + * are obtained using DD1_INIT triggering number 2 + * (Va at rising edge of VS Fa = HS x VS-failing forced toggle) + * and a VSYNC phase that occurs in the middle of DMA transfer + * (about byte 188*512=96256 in the DMA window). + * + * Phase of HS is still not clear to me how to control, + * It just happens to be so. It can be seen if one enables + * RPS_IRQ and print Event Counter 1 in vpeirq(). Every + * time RPS_INTERRUPT is called, the Event Counter 1 will + * increment. That's how the 7146 is programmed to do event + * counting in this budget-patch.c + * I *think* HPS setting has something to do with the phase + * of HS but I can't be 100% sure in that. + * + * hardware debug note: a working budget card (including budget patch) + * with vpeirq() interrupt setup in mode "0x90" (every 64K) will + * generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes + * and that means 3*25=75 Hz of interrupt frequency, as seen by + * watch cat /proc/interrupts + * + * If this frequency is 3x lower (and data received in the DMA + * buffer don't start with 0x47, but in the middle of packets, + * whose lengths appear to be like 188 292 188 104 etc. + * this means VSYNC line is not connected in the hardware. + * (check soldering pcb and pins) + * The same behaviour of missing VSYNC can be duplicated on budget + * cards, by setting DD1_INIT trigger mode 7 in 3rd nibble. + */ +static int av7110_attach(struct saa7146_dev* dev, + struct saa7146_pci_extension_data *pci_ext) +{ + const int length = TS_WIDTH * TS_HEIGHT; + struct pci_dev *pdev = dev->pci; + struct av7110 *av7110; + struct task_struct *thread; + int ret, count = 0; + + dprintk(4, "dev: %p\n", dev); + + /* Set RPS_IRQ to 1 to track rps1 activity. + * Enabling this won't send any interrupt to PC CPU. + */ +#define RPS_IRQ 0 + + if (budgetpatch == 1) { + budgetpatch = 0; + /* autodetect the presence of budget patch + * this only works if saa7146 has been recently + * reset with MASK_31 to MC1 + * + * will wait for VBI_B event (vertical blank at port B) + * and will reset GPIO3 after VBI_B is detected. + * (GPIO3 should be raised high by CPU to + * test if GPIO3 will generate vertical blank signal + * in budget patch GPIO3 is connected to VSYNC_B + */ + + /* RESET SAA7146 */ + saa7146_write(dev, MC1, MASK_31); + /* autodetection success seems to be time-dependend after reset */ + + /* Fix VSYNC level */ + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); + /* set vsync_b triggering */ + saa7146_write(dev, DD1_STREAM_B, 0); + /* port B VSYNC at rising edge */ + saa7146_write(dev, DD1_INIT, 0x00000200); + saa7146_write(dev, BRS_CTRL, 0x00000000); // VBI + saa7146_write(dev, MC2, + 1 * (MASK_08 | MASK_24) | // BRS control + 0 * (MASK_09 | MASK_25) | // a + 1 * (MASK_10 | MASK_26) | // b + 0 * (MASK_06 | MASK_22) | // HPS_CTRL1 + 0 * (MASK_05 | MASK_21) | // HPS_CTRL2 + 0 * (MASK_01 | MASK_15) // DEBI + ); + + /* start writing RPS1 code from beginning */ + count = 0; + /* Disable RPS1 */ + saa7146_write(dev, MC1, MASK_29); + /* RPS1 timeout disable */ + saa7146_write(dev, RPS_TOV1, 0); + WRITE_RPS1(CMD_PAUSE | EVT_VBI_B); + WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2)); + WRITE_RPS1(GPIO3_MSK); + WRITE_RPS1(SAA7146_GPIO_OUTLO<<24); +#if RPS_IRQ + /* issue RPS1 interrupt to increment counter */ + WRITE_RPS1(CMD_INTERRUPT); +#endif + WRITE_RPS1(CMD_STOP); + /* Jump to begin of RPS program as safety measure (p37) */ + WRITE_RPS1(CMD_JUMP); + WRITE_RPS1(dev->d_rps1.dma_handle); + +#if RPS_IRQ + /* set event counter 1 source as RPS1 interrupt (0x03) (rE4 p53) + * use 0x03 to track RPS1 interrupts - increase by 1 every gpio3 is toggled + * use 0x15 to track VPE interrupts - increase by 1 every vpeirq() is called + */ + saa7146_write(dev, EC1SSR, (0x03<<2) | 3 ); + /* set event counter 1 threshold to maximum allowed value (rEC p55) */ + saa7146_write(dev, ECT1R, 0x3fff ); +#endif + /* Set RPS1 Address register to point to RPS code (r108 p42) */ + saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); + /* Enable RPS1, (rFC p33) */ + saa7146_write(dev, MC1, (MASK_13 | MASK_29 )); + + mdelay(10); + /* now send VSYNC_B to rps1 by rising GPIO3 */ + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI); + mdelay(10); + /* if rps1 responded by lowering the GPIO3, + * then we have budgetpatch hardware + */ + if ((saa7146_read(dev, GPIO_CTRL) & 0x10000000) == 0) { + budgetpatch = 1; + printk("dvb-ttpci: BUDGET-PATCH DETECTED.\n"); + } + /* Disable RPS1 */ + saa7146_write(dev, MC1, ( MASK_29 )); +#if RPS_IRQ + printk("dvb-ttpci: Event Counter 1 0x%04x\n", saa7146_read(dev, EC1R) & 0x3fff ); +#endif + } + + /* prepare the av7110 device struct */ + av7110 = kzalloc(sizeof(struct av7110), GFP_KERNEL); + if (!av7110) { + dprintk(1, "out of memory\n"); + return -ENOMEM; + } + + av7110->card_name = (char*) pci_ext->ext_priv; + av7110->dev = dev; + dev->ext_priv = av7110; + + ret = get_firmware(av7110); + if (ret < 0) + goto err_kfree_0; + + ret = dvb_register_adapter(&av7110->dvb_adapter, av7110->card_name, + THIS_MODULE, &dev->pci->dev, adapter_nr); + if (ret < 0) + goto err_put_firmware_1; + + /* the Siemens DVB needs this if you want to have the i2c chips + get recognized before the main driver is fully loaded */ + saa7146_write(dev, GPIO_CTRL, 0x500000); + + strscpy(av7110->i2c_adap.name, pci_ext->ext_priv, + sizeof(av7110->i2c_adap.name)); + + saa7146_i2c_adapter_prepare(dev, &av7110->i2c_adap, SAA7146_I2C_BUS_BIT_RATE_120); /* 275 kHz */ + + ret = i2c_add_adapter(&av7110->i2c_adap); + if (ret < 0) + goto err_dvb_unregister_adapter_2; + + ttpci_eeprom_parse_mac(&av7110->i2c_adap, + av7110->dvb_adapter.proposed_mac); + ret = -ENOMEM; + + /* full-ts mod? */ + if (full_ts) + av7110->full_ts = true; + + /* check for full-ts flag in eeprom */ + if (i2c_readreg(av7110, 0xaa, 0) == 0x4f && i2c_readreg(av7110, 0xaa, 1) == 0x45) { + u8 flags = i2c_readreg(av7110, 0xaa, 2); + if (flags != 0xff && (flags & 0x01)) + av7110->full_ts = true; + } + + if (av7110->full_ts) { + printk(KERN_INFO "dvb-ttpci: full-ts mode enabled for saa7146 port B\n"); + spin_lock_init(&av7110->feedlock1); + av7110->grabbing = saa7146_vmalloc_build_pgtable(pdev, length, + &av7110->pt); + if (!av7110->grabbing) + goto err_i2c_del_3; + + saa7146_write(dev, DD1_STREAM_B, 0x00000000); + saa7146_write(dev, MC2, (MASK_10 | MASK_26)); + + saa7146_write(dev, DD1_INIT, 0x00000600); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + + saa7146_write(dev, BRS_CTRL, 0x60000000); + saa7146_write(dev, MC2, MASK_08 | MASK_24); + + /* dma3 */ + saa7146_write(dev, PCI_BT_V1, 0x001c0000 | (saa7146_read(dev, PCI_BT_V1) & ~0x001f0000)); + saa7146_write(dev, BASE_ODD3, 0); + saa7146_write(dev, BASE_EVEN3, 0); + saa7146_write(dev, PROT_ADDR3, TS_WIDTH * TS_HEIGHT); + saa7146_write(dev, PITCH3, TS_WIDTH); + saa7146_write(dev, BASE_PAGE3, av7110->pt.dma | ME1 | 0x90); + saa7146_write(dev, NUM_LINE_BYTE3, (TS_HEIGHT << 16) | TS_WIDTH); + saa7146_write(dev, MC2, MASK_04 | MASK_20); + + tasklet_setup(&av7110->vpe_tasklet, vpeirq); + + } else if (budgetpatch) { + spin_lock_init(&av7110->feedlock1); + av7110->grabbing = saa7146_vmalloc_build_pgtable(pdev, length, + &av7110->pt); + if (!av7110->grabbing) + goto err_i2c_del_3; + + saa7146_write(dev, PCI_BT_V1, 0x1c1f101f); + saa7146_write(dev, BCS_CTRL, 0x80400040); + /* set dd1 stream a & b */ + saa7146_write(dev, DD1_STREAM_B, 0x00000000); + saa7146_write(dev, DD1_INIT, 0x03000200); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + saa7146_write(dev, BRS_CTRL, 0x60000000); + saa7146_write(dev, BASE_ODD3, 0); + saa7146_write(dev, BASE_EVEN3, 0); + saa7146_write(dev, PROT_ADDR3, TS_WIDTH * TS_HEIGHT); + saa7146_write(dev, BASE_PAGE3, av7110->pt.dma | ME1 | 0x90); + + saa7146_write(dev, PITCH3, TS_WIDTH); + saa7146_write(dev, NUM_LINE_BYTE3, (TS_HEIGHT << 16) | TS_WIDTH); + + /* upload all */ + saa7146_write(dev, MC2, 0x077c077c); + saa7146_write(dev, GPIO_CTRL, 0x000000); +#if RPS_IRQ + /* set event counter 1 source as RPS1 interrupt (0x03) (rE4 p53) + * use 0x03 to track RPS1 interrupts - increase by 1 every gpio3 is toggled + * use 0x15 to track VPE interrupts - increase by 1 every vpeirq() is called + */ + saa7146_write(dev, EC1SSR, (0x03<<2) | 3 ); + /* set event counter 1 threshold to maximum allowed value (rEC p55) */ + saa7146_write(dev, ECT1R, 0x3fff ); +#endif + /* Setup BUDGETPATCH MAIN RPS1 "program" (p35) */ + count = 0; + + /* Wait Source Line Counter Threshold (p36) */ + WRITE_RPS1(CMD_PAUSE | EVT_HS); + /* Set GPIO3=1 (p42) */ + WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2)); + WRITE_RPS1(GPIO3_MSK); + WRITE_RPS1(SAA7146_GPIO_OUTHI<<24); +#if RPS_IRQ + /* issue RPS1 interrupt */ + WRITE_RPS1(CMD_INTERRUPT); +#endif + /* Wait reset Source Line Counter Threshold (p36) */ + WRITE_RPS1(CMD_PAUSE | RPS_INV | EVT_HS); + /* Set GPIO3=0 (p42) */ + WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2)); + WRITE_RPS1(GPIO3_MSK); + WRITE_RPS1(SAA7146_GPIO_OUTLO<<24); +#if RPS_IRQ + /* issue RPS1 interrupt */ + WRITE_RPS1(CMD_INTERRUPT); +#endif + /* Jump to begin of RPS program (p37) */ + WRITE_RPS1(CMD_JUMP); + WRITE_RPS1(dev->d_rps1.dma_handle); + + /* Fix VSYNC level */ + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); + /* Set RPS1 Address register to point to RPS code (r108 p42) */ + saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); + /* Set Source Line Counter Threshold, using BRS (rCC p43) + * It generates HS event every TS_HEIGHT lines + * this is related to TS_WIDTH set in register + * NUM_LINE_BYTE3. If NUM_LINE_BYTE low 16 bits + * are set to TS_WIDTH bytes (TS_WIDTH=2*188), + * then RPS_THRESH1 should be set to trigger + * every TS_HEIGHT (512) lines. + */ + saa7146_write(dev, RPS_THRESH1, (TS_HEIGHT*1) | MASK_12 ); + + /* Enable RPS1 (rFC p33) */ + saa7146_write(dev, MC1, (MASK_13 | MASK_29)); + + /* end of budgetpatch register initialization */ + tasklet_setup(&av7110->vpe_tasklet, vpeirq); + } else { + saa7146_write(dev, PCI_BT_V1, 0x1c00101f); + saa7146_write(dev, BCS_CTRL, 0x80400040); + + /* set dd1 stream a & b */ + saa7146_write(dev, DD1_STREAM_B, 0x00000000); + saa7146_write(dev, DD1_INIT, 0x03000000); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + + /* upload all */ + saa7146_write(dev, MC2, 0x077c077c); + saa7146_write(dev, GPIO_CTRL, 0x000000); + } + + tasklet_setup(&av7110->debi_tasklet, debiirq); + tasklet_setup(&av7110->gpio_tasklet, gpioirq); + + mutex_init(&av7110->pid_mutex); + + /* locks for data transfers from/to AV7110 */ + spin_lock_init(&av7110->debilock); + mutex_init(&av7110->dcomlock); + av7110->debitype = -1; + + /* default OSD window */ + av7110->osdwin = 1; + mutex_init(&av7110->osd_mutex); + + /* TV standard */ + av7110->vidmode = tv_standard == 1 ? AV7110_VIDEO_MODE_NTSC + : AV7110_VIDEO_MODE_PAL; + + /* ARM "watchdog" */ + init_waitqueue_head(&av7110->arm_wait); + av7110->arm_thread = NULL; + + /* allocate and init buffers */ + av7110->debi_virt = dma_alloc_coherent(&pdev->dev, 8192, + &av7110->debi_bus, GFP_KERNEL); + if (!av7110->debi_virt) + goto err_saa71466_vfree_4; + + + av7110->iobuf = vmalloc(AVOUTLEN+AOUTLEN+BMPLEN+4*IPACKS); + if (!av7110->iobuf) + goto err_pci_free_5; + + ret = av7110_av_init(av7110); + if (ret < 0) + goto err_iobuf_vfree_6; + + /* init BMP buffer */ + av7110->bmpbuf = av7110->iobuf+AVOUTLEN+AOUTLEN; + init_waitqueue_head(&av7110->bmpq); + + ret = av7110_ca_init(av7110); + if (ret < 0) + goto err_av7110_av_exit_7; + + /* load firmware into AV7110 cards */ + ret = av7110_bootarm(av7110); + if (ret < 0) + goto err_av7110_ca_exit_8; + + ret = av7110_firmversion(av7110); + if (ret < 0) + goto err_stop_arm_9; + + if (FW_VERSION(av7110->arm_app)<0x2501) + printk(KERN_WARNING + "dvb-ttpci: Warning, firmware version 0x%04x is too old. System might be unstable!\n", + FW_VERSION(av7110->arm_app)); + + thread = kthread_run(arm_thread, (void *) av7110, "arm_mon"); + if (IS_ERR(thread)) { + ret = PTR_ERR(thread); + goto err_stop_arm_9; + } + av7110->arm_thread = thread; + + /* set initial volume in mixer struct */ + av7110->mixer.volume_left = volume; + av7110->mixer.volume_right = volume; + + ret = av7110_register(av7110); + if (ret < 0) + goto err_arm_thread_stop_10; + + init_av7110_av(av7110); + + /* special case DVB-C: these cards have an analog tuner + plus need some special handling, so we have separate + saa7146_ext_vv data for these... */ + ret = av7110_init_v4l(av7110); + if (ret < 0) + goto err_av7110_unregister_11; + + av7110->dvb_adapter.priv = av7110; + ret = frontend_init(av7110); + if (ret < 0) + goto err_av7110_exit_v4l_12; + + mutex_init(&av7110->ioctl_mutex); + +#if IS_ENABLED(CONFIG_DVB_AV7110_IR) + av7110_ir_init(av7110); +#endif + printk(KERN_INFO "dvb-ttpci: found av7110-%d.\n", av7110_num); + av7110_num++; +out: + return ret; + +err_av7110_exit_v4l_12: + av7110_exit_v4l(av7110); +err_av7110_unregister_11: + dvb_unregister(av7110); +err_arm_thread_stop_10: + av7110_arm_sync(av7110); +err_stop_arm_9: + /* Nothing to do. Rejoice. */ +err_av7110_ca_exit_8: + av7110_ca_exit(av7110); +err_av7110_av_exit_7: + av7110_av_exit(av7110); +err_iobuf_vfree_6: + vfree(av7110->iobuf); +err_pci_free_5: + dma_free_coherent(&pdev->dev, 8192, av7110->debi_virt, + av7110->debi_bus); +err_saa71466_vfree_4: + if (av7110->grabbing) + saa7146_vfree_destroy_pgtable(pdev, av7110->grabbing, &av7110->pt); +err_i2c_del_3: + i2c_del_adapter(&av7110->i2c_adap); +err_dvb_unregister_adapter_2: + dvb_unregister_adapter(&av7110->dvb_adapter); +err_put_firmware_1: + put_firmware(av7110); +err_kfree_0: + kfree(av7110); + goto out; +} + +static int av7110_detach(struct saa7146_dev* saa) +{ + struct av7110 *av7110 = saa->ext_priv; + dprintk(4, "%p\n", av7110); + +#if IS_ENABLED(CONFIG_DVB_AV7110_IR) + av7110_ir_exit(av7110); +#endif + if (budgetpatch || av7110->full_ts) { + if (budgetpatch) { + /* Disable RPS1 */ + saa7146_write(saa, MC1, MASK_29); + /* VSYNC LOW (inactive) */ + saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTLO); + } + saa7146_write(saa, MC1, MASK_20); /* DMA3 off */ + SAA7146_IER_DISABLE(saa, MASK_10); + SAA7146_ISR_CLEAR(saa, MASK_10); + msleep(50); + tasklet_kill(&av7110->vpe_tasklet); + saa7146_vfree_destroy_pgtable(saa->pci, av7110->grabbing, &av7110->pt); + } + av7110_exit_v4l(av7110); + + av7110_arm_sync(av7110); + + tasklet_kill(&av7110->debi_tasklet); + tasklet_kill(&av7110->gpio_tasklet); + + dvb_unregister(av7110); + + SAA7146_IER_DISABLE(saa, MASK_19 | MASK_03); + SAA7146_ISR_CLEAR(saa, MASK_19 | MASK_03); + + av7110_ca_exit(av7110); + av7110_av_exit(av7110); + + vfree(av7110->iobuf); + dma_free_coherent(&saa->pci->dev, 8192, av7110->debi_virt, + av7110->debi_bus); + + i2c_del_adapter(&av7110->i2c_adap); + + dvb_unregister_adapter (&av7110->dvb_adapter); + + av7110_num--; + + put_firmware(av7110); + + kfree(av7110); + + saa->ext_priv = NULL; + + return 0; +} + + +static void av7110_irq(struct saa7146_dev* dev, u32 *isr) +{ + struct av7110 *av7110 = dev->ext_priv; + + //print_time("av7110_irq"); + + /* Note: Don't try to handle the DEBI error irq (MASK_18), in + * intel mode the timeout is asserted all the time... + */ + + if (*isr & MASK_19) { + //printk("av7110_irq: DEBI\n"); + /* Note 1: The DEBI irq is level triggered: We must enable it + * only after we started a DMA xfer, and disable it here + * immediately, or it will be signalled all the time while + * DEBI is idle. + * Note 2: You would think that an irq which is masked is + * not signalled by the hardware. Not so for the SAA7146: + * An irq is signalled as long as the corresponding bit + * in the ISR is set, and disabling irqs just prevents the + * hardware from setting the ISR bit. This means a) that we + * must clear the ISR *after* disabling the irq (which is why + * we must do it here even though saa7146_core did it already), + * and b) that if we were to disable an edge triggered irq + * (like the gpio irqs sadly are) temporarily we would likely + * loose some. This sucks :-( + */ + SAA7146_IER_DISABLE(av7110->dev, MASK_19); + SAA7146_ISR_CLEAR(av7110->dev, MASK_19); + tasklet_schedule(&av7110->debi_tasklet); + } + + if (*isr & MASK_03) { + //printk("av7110_irq: GPIO\n"); + tasklet_schedule(&av7110->gpio_tasklet); + } + + if (*isr & MASK_10) + tasklet_schedule(&av7110->vpe_tasklet); +} + + +static struct saa7146_extension av7110_extension_driver; + +#define MAKE_AV7110_INFO(x_var,x_name) \ +static struct saa7146_pci_extension_data x_var = { \ + .ext_priv = x_name, \ + .ext = &av7110_extension_driver } + +MAKE_AV7110_INFO(tts_1_X_fsc,"Technotrend/Hauppauge WinTV DVB-S rev1.X or Fujitsu Siemens DVB-C"); +MAKE_AV7110_INFO(ttt_1_X, "Technotrend/Hauppauge WinTV DVB-T rev1.X"); +MAKE_AV7110_INFO(ttc_1_X, "Technotrend/Hauppauge WinTV Nexus-CA rev1.X"); +MAKE_AV7110_INFO(ttc_2_X, "Technotrend/Hauppauge WinTV DVB-C rev2.X"); +MAKE_AV7110_INFO(tts_2_X, "Technotrend/Hauppauge WinTV Nexus-S rev2.X"); +MAKE_AV7110_INFO(tts_2_3, "Technotrend/Hauppauge WinTV Nexus-S rev2.3"); +MAKE_AV7110_INFO(tts_1_3se, "Technotrend/Hauppauge WinTV DVB-S rev1.3 SE"); +MAKE_AV7110_INFO(ttt, "Technotrend/Hauppauge DVB-T"); +MAKE_AV7110_INFO(fsc, "Fujitsu Siemens DVB-C"); +MAKE_AV7110_INFO(fss, "Fujitsu Siemens DVB-S rev1.6"); +MAKE_AV7110_INFO(gxs_1_3, "Galaxis DVB-S rev1.3"); + +static const struct pci_device_id pci_tbl[] = { + MAKE_EXTENSION_PCI(fsc, 0x110a, 0x0000), + MAKE_EXTENSION_PCI(tts_1_X_fsc, 0x13c2, 0x0000), + MAKE_EXTENSION_PCI(ttt_1_X, 0x13c2, 0x0001), + MAKE_EXTENSION_PCI(ttc_2_X, 0x13c2, 0x0002), + MAKE_EXTENSION_PCI(tts_2_X, 0x13c2, 0x0003), + MAKE_EXTENSION_PCI(gxs_1_3, 0x13c2, 0x0004), + MAKE_EXTENSION_PCI(fss, 0x13c2, 0x0006), + MAKE_EXTENSION_PCI(ttt, 0x13c2, 0x0008), + MAKE_EXTENSION_PCI(ttc_1_X, 0x13c2, 0x000a), + MAKE_EXTENSION_PCI(tts_2_3, 0x13c2, 0x000e), + MAKE_EXTENSION_PCI(tts_1_3se, 0x13c2, 0x1002), + +/* MAKE_EXTENSION_PCI(???, 0x13c2, 0x0005), UNDEFINED CARD */ // Technisat SkyStar1 +/* MAKE_EXTENSION_PCI(???, 0x13c2, 0x0009), UNDEFINED CARD */ // TT/Hauppauge WinTV Nexus-CA v???? + + { + .vendor = 0, + } +}; + +MODULE_DEVICE_TABLE(pci, pci_tbl); + + +static struct saa7146_extension av7110_extension_driver = { + .name = "av7110", + .flags = SAA7146_USE_I2C_IRQ, + + .module = THIS_MODULE, + .pci_tbl = &pci_tbl[0], + .attach = av7110_attach, + .detach = av7110_detach, + + .irq_mask = MASK_19 | MASK_03 | MASK_10, + .irq_func = av7110_irq, +}; + + +static int __init av7110_init(void) +{ + return saa7146_register_extension(&av7110_extension_driver); +} + + +static void __exit av7110_exit(void) +{ + saa7146_unregister_extension(&av7110_extension_driver); +} + +module_init(av7110_init); +module_exit(av7110_exit); + +MODULE_DESCRIPTION("driver for the SAA7146 based AV110 PCI DVB cards by Siemens, Technotrend, Hauppauge"); +MODULE_AUTHOR("Ralph Metzler, Marcus Metzler, others"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110.h b/drivers/staging/media/deprecated/saa7146/av7110/av7110.h new file mode 100644 index 000000000..9fde69b38 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110.h @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AV7110_H_ +#define _AV7110_H_ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "dvb_filter.h" +#include +#include +#include +#include "ves1820.h" +#include "ves1x93.h" +#include "stv0299.h" +#include "tda8083.h" +#include "sp8870.h" +#include "stv0297.h" +#include "l64781.h" + +#include "saa7146_vv.h" + + +#define ANALOG_TUNER_VES1820 1 +#define ANALOG_TUNER_STV0297 2 + +extern int av7110_debug; + +#define dprintk(level, fmt, arg...) do { \ + if (level & av7110_debug) \ + printk(KERN_DEBUG KBUILD_MODNAME ": %s(): " fmt, \ + __func__, ##arg); \ +} while (0) + +#define MAXFILT 32 + +enum {AV_PES_STREAM, PS_STREAM, TS_STREAM, PES_STREAM}; + +enum av7110_video_mode { + AV7110_VIDEO_MODE_PAL = 0, + AV7110_VIDEO_MODE_NTSC = 1 +}; + +struct av7110_p2t { + u8 pes[TS_SIZE]; + u8 counter; + long int pos; + int frags; + struct dvb_demux_feed *feed; +}; + +/* video MPEG decoder events: */ +/* (code copied from dvb_frontend.c, should maybe be factored out...) */ +#define MAX_VIDEO_EVENT 8 +struct dvb_video_events { + struct video_event events[MAX_VIDEO_EVENT]; + int eventw; + int eventr; + int overflow; + wait_queue_head_t wait_queue; + spinlock_t lock; +}; + + +struct av7110; + +/* infrared remote control */ +struct infrared { + struct rc_dev *rcdev; + char input_phys[32]; + u32 ir_config; +}; + +/* place to store all the necessary device information */ +struct av7110 { + + /* devices */ + + struct dvb_device dvb_dev; + struct dvb_net dvb_net; + + struct video_device v4l_dev; + struct video_device vbi_dev; + + struct saa7146_dev *dev; + + struct i2c_adapter i2c_adap; + + char *card_name; + + /* support for analog module of dvb-c */ + int analog_tuner_flags; + int current_input; + u32 current_freq; + + struct tasklet_struct debi_tasklet; + struct tasklet_struct gpio_tasklet; + + int adac_type; /* audio DAC type */ +#define DVB_ADAC_TI 0 +#define DVB_ADAC_CRYSTAL 1 +#define DVB_ADAC_MSP34x0 2 +#define DVB_ADAC_MSP34x5 3 +#define DVB_ADAC_NONE -1 + + + /* buffers */ + + void *iobuf; /* memory for all buffers */ + struct dvb_ringbuffer avout; /* buffer for video or A/V mux */ +#define AVOUTLEN (128*1024) + struct dvb_ringbuffer aout; /* buffer for audio */ +#define AOUTLEN (64*1024) + void *bmpbuf; +#define BMPLEN (8*32768+1024) + + /* bitmap buffers and states */ + + int bmpp; + int bmplen; + volatile int bmp_state; +#define BMP_NONE 0 +#define BMP_LOADING 1 +#define BMP_LOADED 2 + wait_queue_head_t bmpq; + + + /* DEBI and polled command interface */ + + spinlock_t debilock; + struct mutex dcomlock; + volatile int debitype; + volatile int debilen; + + + /* Recording and playback flags */ + + int rec_mode; + int playing; +#define RP_NONE 0 +#define RP_VIDEO 1 +#define RP_AUDIO 2 +#define RP_AV 3 + + + /* OSD */ + + int osdwin; /* currently active window */ + u16 osdbpp[8]; + struct mutex osd_mutex; + + /* CA */ + + struct ca_slot_info ci_slot[2]; + + enum av7110_video_mode vidmode; + struct dmxdev dmxdev; + struct dvb_demux demux; + + struct dmx_frontend hw_frontend; + struct dmx_frontend mem_frontend; + + /* for budget mode demux1 */ + struct dmxdev dmxdev1; + struct dvb_demux demux1; + struct dvb_net dvb_net1; + spinlock_t feedlock1; + int feeding1; + u32 ttbp; + unsigned char *grabbing; + struct saa7146_pgtable pt; + struct tasklet_struct vpe_tasklet; + bool full_ts; + + int fe_synced; + struct mutex pid_mutex; + + int video_blank; + struct video_status videostate; + u16 display_panscan; + int display_ar; + int trickmode; +#define TRICK_NONE 0 +#define TRICK_FAST 1 +#define TRICK_SLOW 2 +#define TRICK_FREEZE 3 + struct audio_status audiostate; + + struct dvb_demux_filter *handle2filter[32]; + struct av7110_p2t p2t_filter[MAXFILT]; + struct dvb_filter_pes2ts p2t[2]; + struct ipack ipack[2]; + u8 *kbuf[2]; + + int sinfo; + int feeding; + + int arm_errors; + int registered; + + + /* AV711X */ + + u32 arm_fw; + u32 arm_rtsl; + u32 arm_vid; + u32 arm_app; + u32 avtype; + int arm_ready; + struct task_struct *arm_thread; + wait_queue_head_t arm_wait; + u16 arm_loops; + + void *debi_virt; + dma_addr_t debi_bus; + + u16 pids[DMX_PES_OTHER]; + + struct dvb_ringbuffer ci_rbuffer; + struct dvb_ringbuffer ci_wbuffer; + + struct audio_mixer mixer; + + struct dvb_adapter dvb_adapter; + struct dvb_device *video_dev; + struct dvb_device *audio_dev; + struct dvb_device *ca_dev; + struct dvb_device *osd_dev; + + struct dvb_video_events video_events; + video_size_t video_size; + + u16 wssMode; + u16 wssData; + + struct infrared ir; + + /* firmware stuff */ + unsigned char *bin_fw; + unsigned long size_fw; + + unsigned char *bin_dpram; + unsigned long size_dpram; + + unsigned char *bin_root; + unsigned long size_root; + + struct dvb_frontend* fe; + enum fe_status fe_status; + + struct mutex ioctl_mutex; + + /* crash recovery */ + void (*recover)(struct av7110* av7110); + enum fe_sec_voltage saved_voltage; + enum fe_sec_tone_mode saved_tone; + struct dvb_diseqc_master_cmd saved_master_cmd; + enum fe_sec_mini_cmd saved_minicmd; + + int (*fe_init)(struct dvb_frontend* fe); + int (*fe_read_status)(struct dvb_frontend *fe, enum fe_status *status); + int (*fe_diseqc_reset_overload)(struct dvb_frontend *fe); + int (*fe_diseqc_send_master_cmd)(struct dvb_frontend *fe, + struct dvb_diseqc_master_cmd *cmd); + int (*fe_diseqc_send_burst)(struct dvb_frontend *fe, + enum fe_sec_mini_cmd minicmd); + int (*fe_set_tone)(struct dvb_frontend *fe, + enum fe_sec_tone_mode tone); + int (*fe_set_voltage)(struct dvb_frontend *fe, + enum fe_sec_voltage voltage); + int (*fe_dishnetwork_send_legacy_command)(struct dvb_frontend *fe, + unsigned long cmd); + int (*fe_set_frontend)(struct dvb_frontend *fe); +}; + + +extern int ChangePIDs(struct av7110 *av7110, u16 vpid, u16 apid, u16 ttpid, + u16 subpid, u16 pcrpid); + +void av7110_ir_handler(struct av7110 *av7110, u32 ircom); +int av7110_set_ir_config(struct av7110 *av7110); +int av7110_ir_init(struct av7110 *av7110); +void av7110_ir_exit(struct av7110 *av7110); + +/* msp3400 i2c subaddresses */ +#define MSP_WR_DEM 0x10 +#define MSP_RD_DEM 0x11 +#define MSP_WR_DSP 0x12 +#define MSP_RD_DSP 0x13 + +extern int i2c_writereg(struct av7110 *av7110, u8 id, u8 reg, u8 val); +extern u8 i2c_readreg(struct av7110 *av7110, u8 id, u8 reg); +extern int msp_writereg(struct av7110 *av7110, u8 dev, u16 reg, u16 val); + + +extern int av7110_init_analog_module(struct av7110 *av7110); +extern int av7110_init_v4l(struct av7110 *av7110); +extern int av7110_exit_v4l(struct av7110 *av7110); + +#endif /* _AV7110_H_ */ diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_av.c b/drivers/staging/media/deprecated/saa7146/av7110/av7110_av.c new file mode 100644 index 000000000..0bf513c26 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_av.c @@ -0,0 +1,1681 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * av7110_av.c: audio and video MPEG decoder stuff + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * originally based on code by: + * Copyright (C) 1998,1999 Christian Theiss + * + * the project's page is at https://linuxtv.org + */ + +#include +#include +#include +#include +#include +#include + +#include "av7110.h" +#include "av7110_hw.h" +#include "av7110_av.h" +#include "av7110_ipack.h" + +/* MPEG-2 (ISO 13818 / H.222.0) stream types */ +#define PROG_STREAM_MAP 0xBC +#define PRIVATE_STREAM1 0xBD +#define PADDING_STREAM 0xBE +#define PRIVATE_STREAM2 0xBF +#define AUDIO_STREAM_S 0xC0 +#define AUDIO_STREAM_E 0xDF +#define VIDEO_STREAM_S 0xE0 +#define VIDEO_STREAM_E 0xEF +#define ECM_STREAM 0xF0 +#define EMM_STREAM 0xF1 +#define DSM_CC_STREAM 0xF2 +#define ISO13522_STREAM 0xF3 +#define PROG_STREAM_DIR 0xFF + +#define PTS_DTS_FLAGS 0xC0 + +//pts_dts flags +#define PTS_ONLY 0x80 +#define PTS_DTS 0xC0 +#define TS_SIZE 188 +#define TRANS_ERROR 0x80 +#define PAY_START 0x40 +#define TRANS_PRIO 0x20 +#define PID_MASK_HI 0x1F +//flags +#define TRANS_SCRMBL1 0x80 +#define TRANS_SCRMBL2 0x40 +#define ADAPT_FIELD 0x20 +#define PAYLOAD 0x10 +#define COUNT_MASK 0x0F + +// adaptation flags +#define DISCON_IND 0x80 +#define RAND_ACC_IND 0x40 +#define ES_PRI_IND 0x20 +#define PCR_FLAG 0x10 +#define OPCR_FLAG 0x08 +#define SPLICE_FLAG 0x04 +#define TRANS_PRIV 0x02 +#define ADAP_EXT_FLAG 0x01 + +// adaptation extension flags +#define LTW_FLAG 0x80 +#define PIECE_RATE 0x40 +#define SEAM_SPLICE 0x20 + + +static void p_to_t(u8 const *buf, long int length, u16 pid, + u8 *counter, struct dvb_demux_feed *feed); +static int write_ts_to_decoder(struct av7110 *av7110, int type, const u8 *buf, size_t len); + + +int av7110_record_cb(struct dvb_filter_pes2ts *p2t, u8 *buf, size_t len) +{ + struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *) p2t->priv; + + if (!(dvbdmxfeed->ts_type & TS_PACKET)) + return 0; + if (buf[3] == 0xe0) // video PES do not have a length in TS + buf[4] = buf[5] = 0; + if (dvbdmxfeed->ts_type & TS_PAYLOAD_ONLY) + return dvbdmxfeed->cb.ts(buf, len, NULL, 0, + &dvbdmxfeed->feed.ts, NULL); + else + return dvb_filter_pes2ts(p2t, buf, len, 1); +} + +static int dvb_filter_pes2ts_cb(void *priv, unsigned char *data) +{ + struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *) priv; + + dvbdmxfeed->cb.ts(data, 188, NULL, 0, + &dvbdmxfeed->feed.ts, NULL); + return 0; +} + +int av7110_av_start_record(struct av7110 *av7110, int av, + struct dvb_demux_feed *dvbdmxfeed) +{ + int ret = 0; + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + + dprintk(2, "av7110:%p, dvb_demux_feed:%p\n", av7110, dvbdmxfeed); + + if (av7110->playing || (av7110->rec_mode & av)) + return -EBUSY; + av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Stop, 0); + dvbdmx->recording = 1; + av7110->rec_mode |= av; + + switch (av7110->rec_mode) { + case RP_AUDIO: + dvb_filter_pes2ts_init(&av7110->p2t[0], + dvbdmx->pesfilter[0]->pid, + dvb_filter_pes2ts_cb, + (void *) dvbdmx->pesfilter[0]); + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Record, 2, AudioPES, 0); + break; + + case RP_VIDEO: + dvb_filter_pes2ts_init(&av7110->p2t[1], + dvbdmx->pesfilter[1]->pid, + dvb_filter_pes2ts_cb, + (void *) dvbdmx->pesfilter[1]); + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Record, 2, VideoPES, 0); + break; + + case RP_AV: + dvb_filter_pes2ts_init(&av7110->p2t[0], + dvbdmx->pesfilter[0]->pid, + dvb_filter_pes2ts_cb, + (void *) dvbdmx->pesfilter[0]); + dvb_filter_pes2ts_init(&av7110->p2t[1], + dvbdmx->pesfilter[1]->pid, + dvb_filter_pes2ts_cb, + (void *) dvbdmx->pesfilter[1]); + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Record, 2, AV_PES, 0); + break; + } + return ret; +} + +int av7110_av_start_play(struct av7110 *av7110, int av) +{ + int ret = 0; + dprintk(2, "av7110:%p, \n", av7110); + + if (av7110->rec_mode) + return -EBUSY; + if (av7110->playing & av) + return -EBUSY; + + av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Stop, 0); + + if (av7110->playing == RP_NONE) { + av7110_ipack_reset(&av7110->ipack[0]); + av7110_ipack_reset(&av7110->ipack[1]); + } + + av7110->playing |= av; + switch (av7110->playing) { + case RP_AUDIO: + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Play, 2, AudioPES, 0); + break; + case RP_VIDEO: + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Play, 2, VideoPES, 0); + av7110->sinfo = 0; + break; + case RP_AV: + av7110->sinfo = 0; + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Play, 2, AV_PES, 0); + break; + } + return ret; +} + +int av7110_av_stop(struct av7110 *av7110, int av) +{ + int ret = 0; + dprintk(2, "av7110:%p, \n", av7110); + + if (!(av7110->playing & av) && !(av7110->rec_mode & av)) + return 0; + av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Stop, 0); + if (av7110->playing) { + av7110->playing &= ~av; + switch (av7110->playing) { + case RP_AUDIO: + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Play, 2, AudioPES, 0); + break; + case RP_VIDEO: + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Play, 2, VideoPES, 0); + break; + case RP_NONE: + ret = av7110_set_vidmode(av7110, av7110->vidmode); + break; + } + } else { + av7110->rec_mode &= ~av; + switch (av7110->rec_mode) { + case RP_AUDIO: + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Record, 2, AudioPES, 0); + break; + case RP_VIDEO: + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Record, 2, VideoPES, 0); + break; + case RP_NONE: + break; + } + } + return ret; +} + + +int av7110_pes_play(void *dest, struct dvb_ringbuffer *buf, int dlen) +{ + int len; + u32 sync; + u16 blen; + + if (!dlen) { + wake_up(&buf->queue); + return -1; + } + while (1) { + len = dvb_ringbuffer_avail(buf); + if (len < 6) { + wake_up(&buf->queue); + return -1; + } + sync = DVB_RINGBUFFER_PEEK(buf, 0) << 24; + sync |= DVB_RINGBUFFER_PEEK(buf, 1) << 16; + sync |= DVB_RINGBUFFER_PEEK(buf, 2) << 8; + sync |= DVB_RINGBUFFER_PEEK(buf, 3); + + if (((sync &~ 0x0f) == 0x000001e0) || + ((sync &~ 0x1f) == 0x000001c0) || + (sync == 0x000001bd)) + break; + printk("resync\n"); + DVB_RINGBUFFER_SKIP(buf, 1); + } + blen = DVB_RINGBUFFER_PEEK(buf, 4) << 8; + blen |= DVB_RINGBUFFER_PEEK(buf, 5); + blen += 6; + if (len < blen || blen > dlen) { + //printk("buffer empty - avail %d blen %u dlen %d\n", len, blen, dlen); + wake_up(&buf->queue); + return -1; + } + + dvb_ringbuffer_read(buf, dest, (size_t) blen); + + dprintk(2, "pread=0x%08lx, pwrite=0x%08lx\n", + (unsigned long) buf->pread, (unsigned long) buf->pwrite); + wake_up(&buf->queue); + return blen; +} + + +int av7110_set_volume(struct av7110 *av7110, unsigned int volleft, + unsigned int volright) +{ + unsigned int vol, val, balance = 0; + int err; + + dprintk(2, "av7110:%p, \n", av7110); + + av7110->mixer.volume_left = volleft; + av7110->mixer.volume_right = volright; + + switch (av7110->adac_type) { + case DVB_ADAC_TI: + volleft = (volleft * 256) / 1036; + volright = (volright * 256) / 1036; + if (volleft > 0x3f) + volleft = 0x3f; + if (volright > 0x3f) + volright = 0x3f; + if ((err = SendDAC(av7110, 3, 0x80 + volleft))) + return err; + return SendDAC(av7110, 4, volright); + + case DVB_ADAC_CRYSTAL: + volleft = 127 - volleft / 2; + volright = 127 - volright / 2; + i2c_writereg(av7110, 0x20, 0x03, volleft); + i2c_writereg(av7110, 0x20, 0x04, volright); + return 0; + + case DVB_ADAC_MSP34x0: + vol = (volleft > volright) ? volleft : volright; + val = (vol * 0x73 / 255) << 8; + if (vol > 0) + balance = ((volright - volleft) * 127) / vol; + msp_writereg(av7110, MSP_WR_DSP, 0x0001, balance << 8); + msp_writereg(av7110, MSP_WR_DSP, 0x0000, val); /* loudspeaker */ + msp_writereg(av7110, MSP_WR_DSP, 0x0006, val); /* headphonesr */ + return 0; + + case DVB_ADAC_MSP34x5: + vol = (volleft > volright) ? volleft : volright; + val = (vol * 0x73 / 255) << 8; + if (vol > 0) + balance = ((volright - volleft) * 127) / vol; + msp_writereg(av7110, MSP_WR_DSP, 0x0001, balance << 8); + msp_writereg(av7110, MSP_WR_DSP, 0x0000, val); /* loudspeaker */ + return 0; + } + + return 0; +} + +int av7110_set_vidmode(struct av7110 *av7110, enum av7110_video_mode mode) +{ + int ret; + dprintk(2, "av7110:%p, \n", av7110); + + ret = av7110_fw_cmd(av7110, COMTYPE_ENCODER, LoadVidCode, 1, mode); + + if (!ret && !av7110->playing) { + ret = ChangePIDs(av7110, av7110->pids[DMX_PES_VIDEO], + av7110->pids[DMX_PES_AUDIO], + av7110->pids[DMX_PES_TELETEXT], + 0, av7110->pids[DMX_PES_PCR]); + if (!ret) + ret = av7110_fw_cmd(av7110, COMTYPE_PIDFILTER, Scan, 0); + } + return ret; +} + + +static enum av7110_video_mode sw2mode[16] = { + AV7110_VIDEO_MODE_PAL, AV7110_VIDEO_MODE_NTSC, + AV7110_VIDEO_MODE_NTSC, AV7110_VIDEO_MODE_PAL, + AV7110_VIDEO_MODE_NTSC, AV7110_VIDEO_MODE_NTSC, + AV7110_VIDEO_MODE_PAL, AV7110_VIDEO_MODE_NTSC, + AV7110_VIDEO_MODE_PAL, AV7110_VIDEO_MODE_PAL, + AV7110_VIDEO_MODE_PAL, AV7110_VIDEO_MODE_PAL, + AV7110_VIDEO_MODE_PAL, AV7110_VIDEO_MODE_PAL, + AV7110_VIDEO_MODE_PAL, AV7110_VIDEO_MODE_PAL, +}; + +static int get_video_format(struct av7110 *av7110, u8 *buf, int count) +{ + int i; + int hsize, vsize; + int sw; + u8 *p; + int ret = 0; + + dprintk(2, "av7110:%p, \n", av7110); + + if (av7110->sinfo) + return 0; + for (i = 7; i < count - 10; i++) { + p = buf + i; + if (p[0] || p[1] || p[2] != 0x01 || p[3] != 0xb3) + continue; + p += 4; + hsize = ((p[1] &0xF0) >> 4) | (p[0] << 4); + vsize = ((p[1] &0x0F) << 8) | (p[2]); + sw = (p[3] & 0x0F); + ret = av7110_set_vidmode(av7110, sw2mode[sw]); + if (!ret) { + dprintk(2, "playback %dx%d fr=%d\n", hsize, vsize, sw); + av7110->sinfo = 1; + } + break; + } + return ret; +} + + +/**************************************************************************** + * I/O buffer management and control + ****************************************************************************/ + +static inline long aux_ring_buffer_write(struct dvb_ringbuffer *rbuf, + const u8 *buf, unsigned long count) +{ + unsigned long todo = count; + int free; + + while (todo > 0) { + if (dvb_ringbuffer_free(rbuf) < 2048) { + if (wait_event_interruptible(rbuf->queue, + (dvb_ringbuffer_free(rbuf) >= 2048))) + return count - todo; + } + free = dvb_ringbuffer_free(rbuf); + if (free > todo) + free = todo; + dvb_ringbuffer_write(rbuf, buf, free); + todo -= free; + buf += free; + } + + return count - todo; +} + +static void play_video_cb(u8 *buf, int count, void *priv) +{ + struct av7110 *av7110 = (struct av7110 *) priv; + dprintk(2, "av7110:%p, \n", av7110); + + if ((buf[3] & 0xe0) == 0xe0) { + get_video_format(av7110, buf, count); + aux_ring_buffer_write(&av7110->avout, buf, count); + } else + aux_ring_buffer_write(&av7110->aout, buf, count); +} + +static void play_audio_cb(u8 *buf, int count, void *priv) +{ + struct av7110 *av7110 = (struct av7110 *) priv; + dprintk(2, "av7110:%p, \n", av7110); + + aux_ring_buffer_write(&av7110->aout, buf, count); +} + + +#define FREE_COND_TS (dvb_ringbuffer_free(rb) >= 4096) + +static ssize_t ts_play(struct av7110 *av7110, const char __user *buf, + unsigned long count, int nonblock, int type) +{ + struct dvb_ringbuffer *rb; + u8 *kb; + unsigned long todo = count; + + dprintk(2, "%s: type %d cnt %lu\n", __func__, type, count); + + rb = (type) ? &av7110->avout : &av7110->aout; + kb = av7110->kbuf[type]; + + if (!kb) + return -ENOBUFS; + + if (nonblock && !FREE_COND_TS) + return -EWOULDBLOCK; + + while (todo >= TS_SIZE) { + if (!FREE_COND_TS) { + if (nonblock) + return count - todo; + if (wait_event_interruptible(rb->queue, FREE_COND_TS)) + return count - todo; + } + if (copy_from_user(kb, buf, TS_SIZE)) + return -EFAULT; + write_ts_to_decoder(av7110, type, kb, TS_SIZE); + todo -= TS_SIZE; + buf += TS_SIZE; + } + + return count - todo; +} + + +#define FREE_COND (dvb_ringbuffer_free(&av7110->avout) >= 20 * 1024 && \ + dvb_ringbuffer_free(&av7110->aout) >= 20 * 1024) + +static ssize_t dvb_play(struct av7110 *av7110, const char __user *buf, + unsigned long count, int nonblock, int type) +{ + unsigned long todo = count, n; + dprintk(2, "av7110:%p, \n", av7110); + + if (!av7110->kbuf[type]) + return -ENOBUFS; + + if (nonblock && !FREE_COND) + return -EWOULDBLOCK; + + while (todo > 0) { + if (!FREE_COND) { + if (nonblock) + return count - todo; + if (wait_event_interruptible(av7110->avout.queue, + FREE_COND)) + return count - todo; + } + n = todo; + if (n > IPACKS * 2) + n = IPACKS * 2; + if (copy_from_user(av7110->kbuf[type], buf, n)) + return -EFAULT; + av7110_ipack_instant_repack(av7110->kbuf[type], n, + &av7110->ipack[type]); + todo -= n; + buf += n; + } + return count - todo; +} + +static ssize_t dvb_play_kernel(struct av7110 *av7110, const u8 *buf, + unsigned long count, int nonblock, int type) +{ + unsigned long todo = count, n; + dprintk(2, "av7110:%p, \n", av7110); + + if (!av7110->kbuf[type]) + return -ENOBUFS; + + if (nonblock && !FREE_COND) + return -EWOULDBLOCK; + + while (todo > 0) { + if (!FREE_COND) { + if (nonblock) + return count - todo; + if (wait_event_interruptible(av7110->avout.queue, + FREE_COND)) + return count - todo; + } + n = todo; + if (n > IPACKS * 2) + n = IPACKS * 2; + av7110_ipack_instant_repack(buf, n, &av7110->ipack[type]); + todo -= n; + buf += n; + } + return count - todo; +} + +static ssize_t dvb_aplay(struct av7110 *av7110, const char __user *buf, + unsigned long count, int nonblock, int type) +{ + unsigned long todo = count, n; + dprintk(2, "av7110:%p, \n", av7110); + + if (!av7110->kbuf[type]) + return -ENOBUFS; + if (nonblock && dvb_ringbuffer_free(&av7110->aout) < 20 * 1024) + return -EWOULDBLOCK; + + while (todo > 0) { + if (dvb_ringbuffer_free(&av7110->aout) < 20 * 1024) { + if (nonblock) + return count - todo; + if (wait_event_interruptible(av7110->aout.queue, + (dvb_ringbuffer_free(&av7110->aout) >= 20 * 1024))) + return count-todo; + } + n = todo; + if (n > IPACKS * 2) + n = IPACKS * 2; + if (copy_from_user(av7110->kbuf[type], buf, n)) + return -EFAULT; + av7110_ipack_instant_repack(av7110->kbuf[type], n, + &av7110->ipack[type]); + todo -= n; + buf += n; + } + return count - todo; +} + +void av7110_p2t_init(struct av7110_p2t *p, struct dvb_demux_feed *feed) +{ + memset(p->pes, 0, TS_SIZE); + p->counter = 0; + p->pos = 0; + p->frags = 0; + if (feed) + p->feed = feed; +} + +static void clear_p2t(struct av7110_p2t *p) +{ + memset(p->pes, 0, TS_SIZE); +// p->counter = 0; + p->pos = 0; + p->frags = 0; +} + + +static int find_pes_header(u8 const *buf, long int length, int *frags) +{ + int c = 0; + int found = 0; + + *frags = 0; + + while (c < length - 3 && !found) { + if (buf[c] == 0x00 && buf[c + 1] == 0x00 && + buf[c + 2] == 0x01) { + switch ( buf[c + 3] ) { + case PROG_STREAM_MAP: + case PRIVATE_STREAM2: + case PROG_STREAM_DIR: + case ECM_STREAM: + case EMM_STREAM: + case PADDING_STREAM: + case DSM_CC_STREAM: + case ISO13522_STREAM: + case PRIVATE_STREAM1: + case AUDIO_STREAM_S ... AUDIO_STREAM_E: + case VIDEO_STREAM_S ... VIDEO_STREAM_E: + found = 1; + break; + + default: + c++; + break; + } + } else + c++; + } + if (c == length - 3 && !found) { + if (buf[length - 1] == 0x00) + *frags = 1; + if (buf[length - 2] == 0x00 && + buf[length - 1] == 0x00) + *frags = 2; + if (buf[length - 3] == 0x00 && + buf[length - 2] == 0x00 && + buf[length - 1] == 0x01) + *frags = 3; + return -1; + } + + return c; +} + +void av7110_p2t_write(u8 const *buf, long int length, u16 pid, struct av7110_p2t *p) +{ + int c, c2, l, add; + int check, rest; + + c = 0; + c2 = 0; + if (p->frags){ + check = 0; + switch(p->frags) { + case 1: + if (buf[c] == 0x00 && buf[c + 1] == 0x01) { + check = 1; + c += 2; + } + break; + case 2: + if (buf[c] == 0x01) { + check = 1; + c++; + } + break; + case 3: + check = 1; + } + if (check) { + switch (buf[c]) { + case PROG_STREAM_MAP: + case PRIVATE_STREAM2: + case PROG_STREAM_DIR: + case ECM_STREAM: + case EMM_STREAM: + case PADDING_STREAM: + case DSM_CC_STREAM: + case ISO13522_STREAM: + case PRIVATE_STREAM1: + case AUDIO_STREAM_S ... AUDIO_STREAM_E: + case VIDEO_STREAM_S ... VIDEO_STREAM_E: + p->pes[0] = 0x00; + p->pes[1] = 0x00; + p->pes[2] = 0x01; + p->pes[3] = buf[c]; + p->pos = 4; + memcpy(p->pes + p->pos, buf + c, (TS_SIZE - 4) - p->pos); + c += (TS_SIZE - 4) - p->pos; + p_to_t(p->pes, (TS_SIZE - 4), pid, &p->counter, p->feed); + clear_p2t(p); + break; + + default: + c = 0; + break; + } + } + p->frags = 0; + } + + if (p->pos) { + c2 = find_pes_header(buf + c, length - c, &p->frags); + if (c2 >= 0 && c2 < (TS_SIZE - 4) - p->pos) + l = c2+c; + else + l = (TS_SIZE - 4) - p->pos; + memcpy(p->pes + p->pos, buf, l); + c += l; + p->pos += l; + p_to_t(p->pes, p->pos, pid, &p->counter, p->feed); + clear_p2t(p); + } + + add = 0; + while (c < length) { + c2 = find_pes_header(buf + c + add, length - c - add, &p->frags); + if (c2 >= 0) { + c2 += c + add; + if (c2 > c){ + p_to_t(buf + c, c2 - c, pid, &p->counter, p->feed); + c = c2; + clear_p2t(p); + add = 0; + } else + add = 1; + } else { + l = length - c; + rest = l % (TS_SIZE - 4); + l -= rest; + p_to_t(buf + c, l, pid, &p->counter, p->feed); + memcpy(p->pes, buf + c + l, rest); + p->pos = rest; + c = length; + } + } +} + + +static int write_ts_header2(u16 pid, u8 *counter, int pes_start, u8 *buf, u8 length) +{ + int i; + int c = 0; + int fill; + u8 tshead[4] = { 0x47, 0x00, 0x00, 0x10 }; + + fill = (TS_SIZE - 4) - length; + if (pes_start) + tshead[1] = 0x40; + if (fill) + tshead[3] = 0x30; + tshead[1] |= (u8)((pid & 0x1F00) >> 8); + tshead[2] |= (u8)(pid & 0x00FF); + tshead[3] |= ((*counter)++ & 0x0F); + memcpy(buf, tshead, 4); + c += 4; + + if (fill) { + buf[4] = fill - 1; + c++; + if (fill > 1) { + buf[5] = 0x00; + c++; + } + for (i = 6; i < fill + 4; i++) { + buf[i] = 0xFF; + c++; + } + } + + return c; +} + + +static void p_to_t(u8 const *buf, long int length, u16 pid, u8 *counter, + struct dvb_demux_feed *feed) +{ + int l, pes_start; + u8 obuf[TS_SIZE]; + long c = 0; + + pes_start = 0; + if (length > 3 && + buf[0] == 0x00 && buf[1] == 0x00 && buf[2] == 0x01) + switch (buf[3]) { + case PROG_STREAM_MAP: + case PRIVATE_STREAM2: + case PROG_STREAM_DIR: + case ECM_STREAM: + case EMM_STREAM: + case PADDING_STREAM: + case DSM_CC_STREAM: + case ISO13522_STREAM: + case PRIVATE_STREAM1: + case AUDIO_STREAM_S ... AUDIO_STREAM_E: + case VIDEO_STREAM_S ... VIDEO_STREAM_E: + pes_start = 1; + break; + + default: + break; + } + + while (c < length) { + memset(obuf, 0, TS_SIZE); + if (length - c >= (TS_SIZE - 4)){ + l = write_ts_header2(pid, counter, pes_start, + obuf, (TS_SIZE - 4)); + memcpy(obuf + l, buf + c, TS_SIZE - l); + c += TS_SIZE - l; + } else { + l = write_ts_header2(pid, counter, pes_start, + obuf, length - c); + memcpy(obuf + l, buf + c, TS_SIZE - l); + c = length; + } + feed->cb.ts(obuf, 188, NULL, 0, &feed->feed.ts, NULL); + pes_start = 0; + } +} + + +static int write_ts_to_decoder(struct av7110 *av7110, int type, const u8 *buf, size_t len) +{ + struct ipack *ipack = &av7110->ipack[type]; + + if (buf[1] & TRANS_ERROR) { + av7110_ipack_reset(ipack); + return -1; + } + + if (!(buf[3] & PAYLOAD)) + return -1; + + if (buf[1] & PAY_START) + av7110_ipack_flush(ipack); + + if (buf[3] & ADAPT_FIELD) { + len -= buf[4] + 1; + buf += buf[4] + 1; + if (!len) + return 0; + } + + av7110_ipack_instant_repack(buf + 4, len - 4, ipack); + return 0; +} + + +int av7110_write_to_decoder(struct dvb_demux_feed *feed, const u8 *buf, size_t len) +{ + struct dvb_demux *demux = feed->demux; + struct av7110 *av7110 = (struct av7110 *) demux->priv; + + dprintk(2, "av7110:%p, \n", av7110); + + if (av7110->full_ts && demux->dmx.frontend->source != DMX_MEMORY_FE) + return 0; + + switch (feed->pes_type) { + case 0: + if (av7110->audiostate.stream_source == AUDIO_SOURCE_MEMORY) + return -EINVAL; + break; + case 1: + if (av7110->videostate.stream_source == VIDEO_SOURCE_MEMORY) + return -EINVAL; + break; + default: + return -1; + } + + return write_ts_to_decoder(av7110, feed->pes_type, buf, len); +} + + + +/****************************************************************************** + * Video MPEG decoder events + ******************************************************************************/ +void dvb_video_add_event(struct av7110 *av7110, struct video_event *event) +{ + struct dvb_video_events *events = &av7110->video_events; + int wp; + + spin_lock_bh(&events->lock); + + wp = (events->eventw + 1) % MAX_VIDEO_EVENT; + if (wp == events->eventr) { + events->overflow = 1; + events->eventr = (events->eventr + 1) % MAX_VIDEO_EVENT; + } + + //FIXME: timestamp? + memcpy(&events->events[events->eventw], event, sizeof(struct video_event)); + events->eventw = wp; + + spin_unlock_bh(&events->lock); + + wake_up_interruptible(&events->wait_queue); +} + + +static int dvb_video_get_event (struct av7110 *av7110, struct video_event *event, int flags) +{ + struct dvb_video_events *events = &av7110->video_events; + + if (events->overflow) { + events->overflow = 0; + return -EOVERFLOW; + } + if (events->eventw == events->eventr) { + int ret; + + if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + + ret = wait_event_interruptible(events->wait_queue, + events->eventw != events->eventr); + if (ret < 0) + return ret; + } + + spin_lock_bh(&events->lock); + + memcpy(event, &events->events[events->eventr], + sizeof(struct video_event)); + events->eventr = (events->eventr + 1) % MAX_VIDEO_EVENT; + + spin_unlock_bh(&events->lock); + + return 0; +} + +/****************************************************************************** + * DVB device file operations + ******************************************************************************/ + +static __poll_t dvb_video_poll(struct file *file, poll_table *wait) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + __poll_t mask = 0; + + dprintk(2, "av7110:%p, \n", av7110); + + if ((file->f_flags & O_ACCMODE) != O_RDONLY) + poll_wait(file, &av7110->avout.queue, wait); + + poll_wait(file, &av7110->video_events.wait_queue, wait); + + if (av7110->video_events.eventw != av7110->video_events.eventr) + mask = EPOLLPRI; + + if ((file->f_flags & O_ACCMODE) != O_RDONLY) { + if (av7110->playing) { + if (FREE_COND) + mask |= (EPOLLOUT | EPOLLWRNORM); + } else { + /* if not playing: may play if asked for */ + mask |= (EPOLLOUT | EPOLLWRNORM); + } + } + + return mask; +} + +static ssize_t dvb_video_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + unsigned char c; + + dprintk(2, "av7110:%p, \n", av7110); + + if ((file->f_flags & O_ACCMODE) == O_RDONLY) + return -EPERM; + + if (av7110->videostate.stream_source != VIDEO_SOURCE_MEMORY) + return -EPERM; + + if (get_user(c, buf)) + return -EFAULT; + if (c == 0x47 && count % TS_SIZE == 0) + return ts_play(av7110, buf, count, file->f_flags & O_NONBLOCK, 1); + else + return dvb_play(av7110, buf, count, file->f_flags & O_NONBLOCK, 1); +} + +static __poll_t dvb_audio_poll(struct file *file, poll_table *wait) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + __poll_t mask = 0; + + dprintk(2, "av7110:%p, \n", av7110); + + poll_wait(file, &av7110->aout.queue, wait); + + if (av7110->playing) { + if (dvb_ringbuffer_free(&av7110->aout) >= 20 * 1024) + mask |= (EPOLLOUT | EPOLLWRNORM); + } else /* if not playing: may play if asked for */ + mask = (EPOLLOUT | EPOLLWRNORM); + + return mask; +} + +static ssize_t dvb_audio_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + unsigned char c; + + dprintk(2, "av7110:%p, \n", av7110); + + if (av7110->audiostate.stream_source != AUDIO_SOURCE_MEMORY) { + printk(KERN_ERR "not audio source memory\n"); + return -EPERM; + } + + if (get_user(c, buf)) + return -EFAULT; + if (c == 0x47 && count % TS_SIZE == 0) + return ts_play(av7110, buf, count, file->f_flags & O_NONBLOCK, 0); + else + return dvb_aplay(av7110, buf, count, file->f_flags & O_NONBLOCK, 0); +} + +static u8 iframe_header[] = { 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x80, 0x00, 0x00 }; + +#define MIN_IFRAME 400000 + +static int play_iframe(struct av7110 *av7110, char __user *buf, unsigned int len, int nonblock) +{ + unsigned i, n; + int progressive = 0; + int match = 0; + + dprintk(2, "av7110:%p, \n", av7110); + + if (len == 0) + return 0; + + if (!(av7110->playing & RP_VIDEO)) { + if (av7110_av_start_play(av7110, RP_VIDEO) < 0) + return -EBUSY; + } + + /* search in buf for instances of 00 00 01 b5 1? */ + for (i = 0; i < len; i++) { + unsigned char c; + if (get_user(c, buf + i)) + return -EFAULT; + if (match == 5) { + progressive = c & 0x08; + match = 0; + } + if (c == 0x00) { + match = (match == 1 || match == 2) ? 2 : 1; + continue; + } + switch (match++) { + case 2: if (c == 0x01) + continue; + break; + case 3: if (c == 0xb5) + continue; + break; + case 4: if ((c & 0xf0) == 0x10) + continue; + break; + } + match = 0; + } + + /* setting n always > 1, fixes problems when playing stillframes + consisting of I- and P-Frames */ + n = MIN_IFRAME / len + 1; + + /* FIXME: nonblock? */ + dvb_play_kernel(av7110, iframe_header, sizeof(iframe_header), 0, 1); + + for (i = 0; i < n; i++) + dvb_play(av7110, buf, len, 0, 1); + + av7110_ipack_flush(&av7110->ipack[1]); + + if (progressive) + return vidcom(av7110, AV_VIDEO_CMD_FREEZE, 1); + else + return 0; +} + +#ifdef CONFIG_COMPAT +struct compat_video_still_picture { + compat_uptr_t iFrame; + int32_t size; +}; +#define VIDEO_STILLPICTURE32 _IOW('o', 30, struct compat_video_still_picture) + +struct compat_video_event { + __s32 type; + /* unused, make sure to use atomic time for y2038 if it ever gets used */ + compat_long_t timestamp; + union { + video_size_t size; + unsigned int frame_rate; /* in frames per 1000sec */ + unsigned char vsync_field; /* unknown/odd/even/progressive */ + } u; +}; +#define VIDEO_GET_EVENT32 _IOR('o', 28, struct compat_video_event) + +static int dvb_compat_video_get_event(struct av7110 *av7110, + struct compat_video_event *event, int flags) +{ + struct video_event ev; + int ret; + + ret = dvb_video_get_event(av7110, &ev, flags); + + *event = (struct compat_video_event) { + .type = ev.type, + .timestamp = ev.timestamp, + .u.size = ev.u.size, + }; + + return ret; +} +#endif + +static int dvb_video_ioctl(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + unsigned long arg = (unsigned long) parg; + int ret = 0; + + dprintk(1, "av7110:%p, cmd=%04x\n", av7110,cmd); + + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + if ( cmd != VIDEO_GET_STATUS && cmd != VIDEO_GET_EVENT && + cmd != VIDEO_GET_SIZE ) { + return -EPERM; + } + } + + if (mutex_lock_interruptible(&av7110->ioctl_mutex)) + return -ERESTARTSYS; + + switch (cmd) { + case VIDEO_STOP: + av7110->videostate.play_state = VIDEO_STOPPED; + if (av7110->videostate.stream_source == VIDEO_SOURCE_MEMORY) + ret = av7110_av_stop(av7110, RP_VIDEO); + else + ret = vidcom(av7110, AV_VIDEO_CMD_STOP, + av7110->videostate.video_blank ? 0 : 1); + if (!ret) + av7110->trickmode = TRICK_NONE; + break; + + case VIDEO_PLAY: + av7110->trickmode = TRICK_NONE; + if (av7110->videostate.play_state == VIDEO_FREEZED) { + av7110->videostate.play_state = VIDEO_PLAYING; + ret = vidcom(av7110, AV_VIDEO_CMD_PLAY, 0); + if (ret) + break; + } + if (av7110->videostate.stream_source == VIDEO_SOURCE_MEMORY) { + if (av7110->playing == RP_AV) { + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Stop, 0); + if (ret) + break; + av7110->playing &= ~RP_VIDEO; + } + ret = av7110_av_start_play(av7110, RP_VIDEO); + } + if (!ret) + ret = vidcom(av7110, AV_VIDEO_CMD_PLAY, 0); + if (!ret) + av7110->videostate.play_state = VIDEO_PLAYING; + break; + + case VIDEO_FREEZE: + av7110->videostate.play_state = VIDEO_FREEZED; + if (av7110->playing & RP_VIDEO) + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Pause, 0); + else + ret = vidcom(av7110, AV_VIDEO_CMD_FREEZE, 1); + if (!ret) + av7110->trickmode = TRICK_FREEZE; + break; + + case VIDEO_CONTINUE: + if (av7110->playing & RP_VIDEO) + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Continue, 0); + if (!ret) + ret = vidcom(av7110, AV_VIDEO_CMD_PLAY, 0); + if (!ret) { + av7110->videostate.play_state = VIDEO_PLAYING; + av7110->trickmode = TRICK_NONE; + } + break; + + case VIDEO_SELECT_SOURCE: + av7110->videostate.stream_source = (video_stream_source_t) arg; + break; + + case VIDEO_SET_BLANK: + av7110->videostate.video_blank = (int) arg; + break; + + case VIDEO_GET_STATUS: + memcpy(parg, &av7110->videostate, sizeof(struct video_status)); + break; + +#ifdef CONFIG_COMPAT + case VIDEO_GET_EVENT32: + ret = dvb_compat_video_get_event(av7110, parg, file->f_flags); + break; +#endif + + case VIDEO_GET_EVENT: + ret = dvb_video_get_event(av7110, parg, file->f_flags); + break; + + case VIDEO_GET_SIZE: + memcpy(parg, &av7110->video_size, sizeof(video_size_t)); + break; + + case VIDEO_SET_DISPLAY_FORMAT: + { + video_displayformat_t format = (video_displayformat_t) arg; + switch (format) { + case VIDEO_PAN_SCAN: + av7110->display_panscan = VID_PAN_SCAN_PREF; + break; + case VIDEO_LETTER_BOX: + av7110->display_panscan = VID_VC_AND_PS_PREF; + break; + case VIDEO_CENTER_CUT_OUT: + av7110->display_panscan = VID_CENTRE_CUT_PREF; + break; + default: + ret = -EINVAL; + } + if (ret < 0) + break; + av7110->videostate.display_format = format; + ret = av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetPanScanType, + 1, av7110->display_panscan); + break; + } + + case VIDEO_SET_FORMAT: + if (arg > 1) { + ret = -EINVAL; + break; + } + av7110->display_ar = arg; + ret = av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetMonitorType, + 1, (u16) arg); + break; + +#ifdef CONFIG_COMPAT + case VIDEO_STILLPICTURE32: + { + struct compat_video_still_picture *pic = + (struct compat_video_still_picture *) parg; + av7110->videostate.stream_source = VIDEO_SOURCE_MEMORY; + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->avout); + ret = play_iframe(av7110, compat_ptr(pic->iFrame), + pic->size, file->f_flags & O_NONBLOCK); + break; + } +#endif + + case VIDEO_STILLPICTURE: + { + struct video_still_picture *pic = + (struct video_still_picture *) parg; + av7110->videostate.stream_source = VIDEO_SOURCE_MEMORY; + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->avout); + ret = play_iframe(av7110, pic->iFrame, pic->size, + file->f_flags & O_NONBLOCK); + break; + } + + case VIDEO_FAST_FORWARD: + //note: arg is ignored by firmware + if (av7110->playing & RP_VIDEO) + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, + __Scan_I, 2, AV_PES, 0); + else + ret = vidcom(av7110, AV_VIDEO_CMD_FFWD, arg); + if (!ret) { + av7110->trickmode = TRICK_FAST; + av7110->videostate.play_state = VIDEO_PLAYING; + } + break; + + case VIDEO_SLOWMOTION: + if (av7110->playing&RP_VIDEO) { + if (av7110->trickmode != TRICK_SLOW) + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Slow, 2, 0, 0); + if (!ret) + ret = vidcom(av7110, AV_VIDEO_CMD_SLOW, arg); + } else { + ret = vidcom(av7110, AV_VIDEO_CMD_PLAY, 0); + if (!ret) + ret = vidcom(av7110, AV_VIDEO_CMD_STOP, 0); + if (!ret) + ret = vidcom(av7110, AV_VIDEO_CMD_SLOW, arg); + } + if (!ret) { + av7110->trickmode = TRICK_SLOW; + av7110->videostate.play_state = VIDEO_PLAYING; + } + break; + + case VIDEO_GET_CAPABILITIES: + *(int *)parg = VIDEO_CAP_MPEG1 | VIDEO_CAP_MPEG2 | + VIDEO_CAP_SYS | VIDEO_CAP_PROG; + break; + + case VIDEO_CLEAR_BUFFER: + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->avout); + av7110_ipack_reset(&av7110->ipack[1]); + if (av7110->playing == RP_AV) { + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, + __Play, 2, AV_PES, 0); + if (ret) + break; + if (av7110->trickmode == TRICK_FAST) + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, + __Scan_I, 2, AV_PES, 0); + if (av7110->trickmode == TRICK_SLOW) { + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, + __Slow, 2, 0, 0); + if (!ret) + ret = vidcom(av7110, AV_VIDEO_CMD_SLOW, arg); + } + if (av7110->trickmode == TRICK_FREEZE) + ret = vidcom(av7110, AV_VIDEO_CMD_STOP, 1); + } + break; + + case VIDEO_SET_STREAMTYPE: + break; + + default: + ret = -ENOIOCTLCMD; + break; + } + + mutex_unlock(&av7110->ioctl_mutex); + return ret; +} + +static int dvb_audio_ioctl(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + unsigned long arg = (unsigned long) parg; + int ret = 0; + + dprintk(1, "av7110:%p, cmd=%04x\n", av7110,cmd); + + if (((file->f_flags & O_ACCMODE) == O_RDONLY) && + (cmd != AUDIO_GET_STATUS)) + return -EPERM; + + if (mutex_lock_interruptible(&av7110->ioctl_mutex)) + return -ERESTARTSYS; + + switch (cmd) { + case AUDIO_STOP: + if (av7110->audiostate.stream_source == AUDIO_SOURCE_MEMORY) + ret = av7110_av_stop(av7110, RP_AUDIO); + else + ret = audcom(av7110, AUDIO_CMD_MUTE); + if (!ret) + av7110->audiostate.play_state = AUDIO_STOPPED; + break; + + case AUDIO_PLAY: + if (av7110->audiostate.stream_source == AUDIO_SOURCE_MEMORY) + ret = av7110_av_start_play(av7110, RP_AUDIO); + if (!ret) + ret = audcom(av7110, AUDIO_CMD_UNMUTE); + if (!ret) + av7110->audiostate.play_state = AUDIO_PLAYING; + break; + + case AUDIO_PAUSE: + ret = audcom(av7110, AUDIO_CMD_MUTE); + if (!ret) + av7110->audiostate.play_state = AUDIO_PAUSED; + break; + + case AUDIO_CONTINUE: + if (av7110->audiostate.play_state == AUDIO_PAUSED) { + av7110->audiostate.play_state = AUDIO_PLAYING; + ret = audcom(av7110, AUDIO_CMD_UNMUTE | AUDIO_CMD_PCM16); + } + break; + + case AUDIO_SELECT_SOURCE: + av7110->audiostate.stream_source = (audio_stream_source_t) arg; + break; + + case AUDIO_SET_MUTE: + { + ret = audcom(av7110, arg ? AUDIO_CMD_MUTE : AUDIO_CMD_UNMUTE); + if (!ret) + av7110->audiostate.mute_state = (int) arg; + break; + } + + case AUDIO_SET_AV_SYNC: + av7110->audiostate.AV_sync_state = (int) arg; + ret = audcom(av7110, arg ? AUDIO_CMD_SYNC_ON : AUDIO_CMD_SYNC_OFF); + break; + + case AUDIO_SET_BYPASS_MODE: + if (FW_VERSION(av7110->arm_app) < 0x2621) + ret = -EINVAL; + av7110->audiostate.bypass_mode = (int)arg; + break; + + case AUDIO_CHANNEL_SELECT: + av7110->audiostate.channel_select = (audio_channel_select_t) arg; + switch(av7110->audiostate.channel_select) { + case AUDIO_STEREO: + ret = audcom(av7110, AUDIO_CMD_STEREO); + if (!ret) { + if (av7110->adac_type == DVB_ADAC_CRYSTAL) + i2c_writereg(av7110, 0x20, 0x02, 0x49); + else if (av7110->adac_type == DVB_ADAC_MSP34x5) + msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0220); + } + break; + case AUDIO_MONO_LEFT: + ret = audcom(av7110, AUDIO_CMD_MONO_L); + if (!ret) { + if (av7110->adac_type == DVB_ADAC_CRYSTAL) + i2c_writereg(av7110, 0x20, 0x02, 0x4a); + else if (av7110->adac_type == DVB_ADAC_MSP34x5) + msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0200); + } + break; + case AUDIO_MONO_RIGHT: + ret = audcom(av7110, AUDIO_CMD_MONO_R); + if (!ret) { + if (av7110->adac_type == DVB_ADAC_CRYSTAL) + i2c_writereg(av7110, 0x20, 0x02, 0x45); + else if (av7110->adac_type == DVB_ADAC_MSP34x5) + msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0210); + } + break; + default: + ret = -EINVAL; + break; + } + break; + + case AUDIO_GET_STATUS: + memcpy(parg, &av7110->audiostate, sizeof(struct audio_status)); + break; + + case AUDIO_GET_CAPABILITIES: + if (FW_VERSION(av7110->arm_app) < 0x2621) + *(unsigned int *)parg = AUDIO_CAP_LPCM | AUDIO_CAP_MP1 | AUDIO_CAP_MP2; + else + *(unsigned int *)parg = AUDIO_CAP_LPCM | AUDIO_CAP_DTS | AUDIO_CAP_AC3 | + AUDIO_CAP_MP1 | AUDIO_CAP_MP2; + break; + + case AUDIO_CLEAR_BUFFER: + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->aout); + av7110_ipack_reset(&av7110->ipack[0]); + if (av7110->playing == RP_AV) + ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, + __Play, 2, AV_PES, 0); + break; + + case AUDIO_SET_ID: + break; + + case AUDIO_SET_MIXER: + { + struct audio_mixer *amix = (struct audio_mixer *)parg; + ret = av7110_set_volume(av7110, amix->volume_left, amix->volume_right); + break; + } + + case AUDIO_SET_STREAMTYPE: + break; + + default: + ret = -ENOIOCTLCMD; + } + + mutex_unlock(&av7110->ioctl_mutex); + return ret; +} + + +static int dvb_video_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + int err; + + dprintk(2, "av7110:%p, \n", av7110); + + if ((err = dvb_generic_open(inode, file)) < 0) + return err; + + if ((file->f_flags & O_ACCMODE) != O_RDONLY) { + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->aout); + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->avout); + av7110->video_blank = 1; + av7110->audiostate.AV_sync_state = 1; + av7110->videostate.stream_source = VIDEO_SOURCE_DEMUX; + + /* empty event queue */ + av7110->video_events.eventr = av7110->video_events.eventw = 0; + } + + return 0; +} + +static int dvb_video_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + + dprintk(2, "av7110:%p, \n", av7110); + + if ((file->f_flags & O_ACCMODE) != O_RDONLY) { + av7110_av_stop(av7110, RP_VIDEO); + } + + return dvb_generic_release(inode, file); +} + +static int dvb_audio_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + int err = dvb_generic_open(inode, file); + + dprintk(2, "av7110:%p, \n", av7110); + + if (err < 0) + return err; + dvb_ringbuffer_flush_spinlock_wakeup(&av7110->aout); + av7110->audiostate.stream_source = AUDIO_SOURCE_DEMUX; + return 0; +} + +static int dvb_audio_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + + dprintk(2, "av7110:%p, \n", av7110); + + av7110_av_stop(av7110, RP_AUDIO); + return dvb_generic_release(inode, file); +} + + + +/****************************************************************************** + * driver registration + ******************************************************************************/ + +static const struct file_operations dvb_video_fops = { + .owner = THIS_MODULE, + .write = dvb_video_write, + .unlocked_ioctl = dvb_generic_ioctl, + .compat_ioctl = dvb_generic_ioctl, + .open = dvb_video_open, + .release = dvb_video_release, + .poll = dvb_video_poll, + .llseek = noop_llseek, +}; + +static struct dvb_device dvbdev_video = { + .priv = NULL, + .users = 6, + .readers = 5, /* arbitrary */ + .writers = 1, + .fops = &dvb_video_fops, + .kernel_ioctl = dvb_video_ioctl, +}; + +static const struct file_operations dvb_audio_fops = { + .owner = THIS_MODULE, + .write = dvb_audio_write, + .unlocked_ioctl = dvb_generic_ioctl, + .compat_ioctl = dvb_generic_ioctl, + .open = dvb_audio_open, + .release = dvb_audio_release, + .poll = dvb_audio_poll, + .llseek = noop_llseek, +}; + +static struct dvb_device dvbdev_audio = { + .priv = NULL, + .users = 1, + .writers = 1, + .fops = &dvb_audio_fops, + .kernel_ioctl = dvb_audio_ioctl, +}; + + +int av7110_av_register(struct av7110 *av7110) +{ + av7110->audiostate.AV_sync_state = 0; + av7110->audiostate.mute_state = 0; + av7110->audiostate.play_state = AUDIO_STOPPED; + av7110->audiostate.stream_source = AUDIO_SOURCE_DEMUX; + av7110->audiostate.channel_select = AUDIO_STEREO; + av7110->audiostate.bypass_mode = 0; + + av7110->videostate.video_blank = 0; + av7110->videostate.play_state = VIDEO_STOPPED; + av7110->videostate.stream_source = VIDEO_SOURCE_DEMUX; + av7110->videostate.video_format = VIDEO_FORMAT_4_3; + av7110->videostate.display_format = VIDEO_LETTER_BOX; + av7110->display_ar = VIDEO_FORMAT_4_3; + av7110->display_panscan = VID_VC_AND_PS_PREF; + + init_waitqueue_head(&av7110->video_events.wait_queue); + spin_lock_init(&av7110->video_events.lock); + av7110->video_events.eventw = av7110->video_events.eventr = 0; + av7110->video_events.overflow = 0; + memset(&av7110->video_size, 0, sizeof (video_size_t)); + + dvb_register_device(&av7110->dvb_adapter, &av7110->video_dev, + &dvbdev_video, av7110, DVB_DEVICE_VIDEO, 0); + + dvb_register_device(&av7110->dvb_adapter, &av7110->audio_dev, + &dvbdev_audio, av7110, DVB_DEVICE_AUDIO, 0); + + return 0; +} + +void av7110_av_unregister(struct av7110 *av7110) +{ + dvb_unregister_device(av7110->audio_dev); + dvb_unregister_device(av7110->video_dev); +} + +int av7110_av_init(struct av7110 *av7110) +{ + void (*play[])(u8 *, int, void *) = { play_audio_cb, play_video_cb }; + int i, ret; + + for (i = 0; i < 2; i++) { + struct ipack *ipack = av7110->ipack + i; + + ret = av7110_ipack_init(ipack, IPACKS, play[i]); + if (ret < 0) { + if (i) + av7110_ipack_free(--ipack); + goto out; + } + ipack->data = av7110; + } + + dvb_ringbuffer_init(&av7110->avout, av7110->iobuf, AVOUTLEN); + dvb_ringbuffer_init(&av7110->aout, av7110->iobuf + AVOUTLEN, AOUTLEN); + + av7110->kbuf[0] = (u8 *)(av7110->iobuf + AVOUTLEN + AOUTLEN + BMPLEN); + av7110->kbuf[1] = av7110->kbuf[0] + 2 * IPACKS; +out: + return ret; +} + +void av7110_av_exit(struct av7110 *av7110) +{ + av7110_ipack_free(&av7110->ipack[0]); + av7110_ipack_free(&av7110->ipack[1]); +} diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_av.h b/drivers/staging/media/deprecated/saa7146/av7110/av7110_av.h new file mode 100644 index 000000000..71bbd4391 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_av.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AV7110_AV_H_ +#define _AV7110_AV_H_ + +struct av7110; + +extern int av7110_set_vidmode(struct av7110 *av7110, + enum av7110_video_mode mode); + +extern int av7110_record_cb(struct dvb_filter_pes2ts *p2t, u8 *buf, size_t len); +extern int av7110_pes_play(void *dest, struct dvb_ringbuffer *buf, int dlen); +extern int av7110_write_to_decoder(struct dvb_demux_feed *feed, const u8 *buf, size_t len); + +extern int av7110_set_volume(struct av7110 *av7110, unsigned int volleft, + unsigned int volright); +extern int av7110_av_stop(struct av7110 *av7110, int av); +extern int av7110_av_start_record(struct av7110 *av7110, int av, + struct dvb_demux_feed *dvbdmxfeed); +extern int av7110_av_start_play(struct av7110 *av7110, int av); + +extern void dvb_video_add_event(struct av7110 *av7110, struct video_event *event); + +extern void av7110_p2t_init(struct av7110_p2t *p, struct dvb_demux_feed *feed); +extern void av7110_p2t_write(u8 const *buf, long int length, u16 pid, struct av7110_p2t *p); + +extern int av7110_av_register(struct av7110 *av7110); +extern void av7110_av_unregister(struct av7110 *av7110); +extern int av7110_av_init(struct av7110 *av7110); +extern void av7110_av_exit(struct av7110 *av7110); + + +#endif /* _AV7110_AV_H_ */ diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_ca.c b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ca.c new file mode 100644 index 000000000..c1338e074 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ca.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * av7110_ca.c: CA and CI stuff + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * originally based on code by: + * Copyright (C) 1998,1999 Christian Theiss + * + * the project's page is at https://linuxtv.org + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "av7110.h" +#include "av7110_hw.h" +#include "av7110_ca.h" + + +void CI_handle(struct av7110 *av7110, u8 *data, u16 len) +{ + dprintk(8, "av7110:%p\n",av7110); + + if (len < 3) + return; + switch (data[0]) { + case CI_MSG_CI_INFO: + if (data[2] != 1 && data[2] != 2) + break; + switch (data[1]) { + case 0: + av7110->ci_slot[data[2] - 1].flags = 0; + break; + case 1: + av7110->ci_slot[data[2] - 1].flags |= CA_CI_MODULE_PRESENT; + break; + case 2: + av7110->ci_slot[data[2] - 1].flags |= CA_CI_MODULE_READY; + break; + } + break; + case CI_SWITCH_PRG_REPLY: + //av7110->ci_stat=data[1]; + break; + default: + break; + } +} + + +void ci_get_data(struct dvb_ringbuffer *cibuf, u8 *data, int len) +{ + if (dvb_ringbuffer_free(cibuf) < len + 2) + return; + + DVB_RINGBUFFER_WRITE_BYTE(cibuf, len >> 8); + DVB_RINGBUFFER_WRITE_BYTE(cibuf, len & 0xff); + dvb_ringbuffer_write(cibuf, data, len); + wake_up_interruptible(&cibuf->queue); +} + + +/****************************************************************************** + * CI link layer file ops + ******************************************************************************/ + +static int ci_ll_init(struct dvb_ringbuffer *cirbuf, struct dvb_ringbuffer *ciwbuf, int size) +{ + struct dvb_ringbuffer *tab[] = { cirbuf, ciwbuf, NULL }, **p; + void *data; + + for (p = tab; *p; p++) { + data = vmalloc(size); + if (!data) { + while (p-- != tab) { + vfree(p[0]->data); + p[0]->data = NULL; + } + return -ENOMEM; + } + dvb_ringbuffer_init(*p, data, size); + } + return 0; +} + +static void ci_ll_flush(struct dvb_ringbuffer *cirbuf, struct dvb_ringbuffer *ciwbuf) +{ + dvb_ringbuffer_flush_spinlock_wakeup(cirbuf); + dvb_ringbuffer_flush_spinlock_wakeup(ciwbuf); +} + +static void ci_ll_release(struct dvb_ringbuffer *cirbuf, struct dvb_ringbuffer *ciwbuf) +{ + vfree(cirbuf->data); + cirbuf->data = NULL; + vfree(ciwbuf->data); + ciwbuf->data = NULL; +} + +static int ci_ll_reset(struct dvb_ringbuffer *cibuf, struct file *file, + int slots, struct ca_slot_info *slot) +{ + int i; + int len = 0; + u8 msg[8] = { 0x00, 0x06, 0x00, 0x00, 0xff, 0x02, 0x00, 0x00 }; + + for (i = 0; i < 2; i++) { + if (slots & (1 << i)) + len += 8; + } + + if (dvb_ringbuffer_free(cibuf) < len) + return -EBUSY; + + for (i = 0; i < 2; i++) { + if (slots & (1 << i)) { + msg[2] = i; + dvb_ringbuffer_write(cibuf, msg, 8); + slot[i].flags = 0; + } + } + + return 0; +} + +static ssize_t ci_ll_write(struct dvb_ringbuffer *cibuf, struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + int free; + int non_blocking = file->f_flags & O_NONBLOCK; + u8 *page = (u8 *)__get_free_page(GFP_USER); + int res; + + if (!page) + return -ENOMEM; + + res = -EINVAL; + if (count > 2048) + goto out; + + res = -EFAULT; + if (copy_from_user(page, buf, count)) + goto out; + + free = dvb_ringbuffer_free(cibuf); + if (count + 2 > free) { + res = -EWOULDBLOCK; + if (non_blocking) + goto out; + res = -ERESTARTSYS; + if (wait_event_interruptible(cibuf->queue, + (dvb_ringbuffer_free(cibuf) >= count + 2))) + goto out; + } + + DVB_RINGBUFFER_WRITE_BYTE(cibuf, count >> 8); + DVB_RINGBUFFER_WRITE_BYTE(cibuf, count & 0xff); + + res = dvb_ringbuffer_write(cibuf, page, count); +out: + free_page((unsigned long)page); + return res; +} + +static ssize_t ci_ll_read(struct dvb_ringbuffer *cibuf, struct file *file, + char __user *buf, size_t count, loff_t *ppos) +{ + int avail; + int non_blocking = file->f_flags & O_NONBLOCK; + ssize_t len; + + if (!cibuf->data || !count) + return 0; + if (non_blocking && (dvb_ringbuffer_empty(cibuf))) + return -EWOULDBLOCK; + if (wait_event_interruptible(cibuf->queue, + !dvb_ringbuffer_empty(cibuf))) + return -ERESTARTSYS; + avail = dvb_ringbuffer_avail(cibuf); + if (avail < 4) + return 0; + len = DVB_RINGBUFFER_PEEK(cibuf, 0) << 8; + len |= DVB_RINGBUFFER_PEEK(cibuf, 1); + if (avail < len + 2 || count < len) + return -EINVAL; + DVB_RINGBUFFER_SKIP(cibuf, 2); + + return dvb_ringbuffer_read_user(cibuf, buf, len); +} + +static int dvb_ca_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + int err = dvb_generic_open(inode, file); + + dprintk(8, "av7110:%p\n",av7110); + + if (err < 0) + return err; + ci_ll_flush(&av7110->ci_rbuffer, &av7110->ci_wbuffer); + return 0; +} + +static __poll_t dvb_ca_poll (struct file *file, poll_table *wait) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + struct dvb_ringbuffer *rbuf = &av7110->ci_rbuffer; + struct dvb_ringbuffer *wbuf = &av7110->ci_wbuffer; + __poll_t mask = 0; + + dprintk(8, "av7110:%p\n",av7110); + + poll_wait(file, &rbuf->queue, wait); + poll_wait(file, &wbuf->queue, wait); + + if (!dvb_ringbuffer_empty(rbuf)) + mask |= (EPOLLIN | EPOLLRDNORM); + + if (dvb_ringbuffer_free(wbuf) > 1024) + mask |= (EPOLLOUT | EPOLLWRNORM); + + return mask; +} + +static int dvb_ca_ioctl(struct file *file, unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + unsigned long arg = (unsigned long) parg; + int ret = 0; + + dprintk(8, "av7110:%p\n",av7110); + + if (mutex_lock_interruptible(&av7110->ioctl_mutex)) + return -ERESTARTSYS; + + switch (cmd) { + case CA_RESET: + ret = ci_ll_reset(&av7110->ci_wbuffer, file, arg, + &av7110->ci_slot[0]); + break; + case CA_GET_CAP: + { + struct ca_caps cap; + + cap.slot_num = 2; + cap.slot_type = (FW_CI_LL_SUPPORT(av7110->arm_app) ? + CA_CI_LINK : CA_CI) | CA_DESCR; + cap.descr_num = 16; + cap.descr_type = CA_ECD; + memcpy(parg, &cap, sizeof(cap)); + break; + } + + case CA_GET_SLOT_INFO: + { + struct ca_slot_info *info=(struct ca_slot_info *)parg; + + if (info->num < 0 || info->num > 1) { + mutex_unlock(&av7110->ioctl_mutex); + return -EINVAL; + } + av7110->ci_slot[info->num].num = info->num; + av7110->ci_slot[info->num].type = FW_CI_LL_SUPPORT(av7110->arm_app) ? + CA_CI_LINK : CA_CI; + memcpy(info, &av7110->ci_slot[info->num], sizeof(struct ca_slot_info)); + break; + } + + case CA_GET_MSG: + break; + + case CA_SEND_MSG: + break; + + case CA_GET_DESCR_INFO: + { + struct ca_descr_info info; + + info.num = 16; + info.type = CA_ECD; + memcpy(parg, &info, sizeof (info)); + break; + } + + case CA_SET_DESCR: + { + struct ca_descr *descr = (struct ca_descr*) parg; + + if (descr->index >= 16 || descr->parity > 1) { + mutex_unlock(&av7110->ioctl_mutex); + return -EINVAL; + } + av7110_fw_cmd(av7110, COMTYPE_PIDFILTER, SetDescr, 5, + (descr->index<<8)|descr->parity, + (descr->cw[0]<<8)|descr->cw[1], + (descr->cw[2]<<8)|descr->cw[3], + (descr->cw[4]<<8)|descr->cw[5], + (descr->cw[6]<<8)|descr->cw[7]); + break; + } + + default: + ret = -EINVAL; + break; + } + + mutex_unlock(&av7110->ioctl_mutex); + return ret; +} + +static ssize_t dvb_ca_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + + dprintk(8, "av7110:%p\n",av7110); + return ci_ll_write(&av7110->ci_wbuffer, file, buf, count, ppos); +} + +static ssize_t dvb_ca_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct av7110 *av7110 = dvbdev->priv; + + dprintk(8, "av7110:%p\n",av7110); + return ci_ll_read(&av7110->ci_rbuffer, file, buf, count, ppos); +} + +static const struct file_operations dvb_ca_fops = { + .owner = THIS_MODULE, + .read = dvb_ca_read, + .write = dvb_ca_write, + .unlocked_ioctl = dvb_generic_ioctl, + .open = dvb_ca_open, + .release = dvb_generic_release, + .poll = dvb_ca_poll, + .llseek = default_llseek, +}; + +static struct dvb_device dvbdev_ca = { + .priv = NULL, + .users = 1, + .writers = 1, + .fops = &dvb_ca_fops, + .kernel_ioctl = dvb_ca_ioctl, +}; + + +int av7110_ca_register(struct av7110 *av7110) +{ + return dvb_register_device(&av7110->dvb_adapter, &av7110->ca_dev, + &dvbdev_ca, av7110, DVB_DEVICE_CA, 0); +} + +void av7110_ca_unregister(struct av7110 *av7110) +{ + dvb_unregister_device(av7110->ca_dev); +} + +int av7110_ca_init(struct av7110* av7110) +{ + return ci_ll_init(&av7110->ci_rbuffer, &av7110->ci_wbuffer, 8192); +} + +void av7110_ca_exit(struct av7110* av7110) +{ + ci_ll_release(&av7110->ci_rbuffer, &av7110->ci_wbuffer); +} diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_ca.h b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ca.h new file mode 100644 index 000000000..a6e3f2955 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ca.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AV7110_CA_H_ +#define _AV7110_CA_H_ + +struct av7110; + +extern void CI_handle(struct av7110 *av7110, u8 *data, u16 len); +extern void ci_get_data(struct dvb_ringbuffer *cibuf, u8 *data, int len); + +extern int av7110_ca_register(struct av7110 *av7110); +extern void av7110_ca_unregister(struct av7110 *av7110); +extern int av7110_ca_init(struct av7110* av7110); +extern void av7110_ca_exit(struct av7110* av7110); + +#endif /* _AV7110_CA_H_ */ diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_hw.c b/drivers/staging/media/deprecated/saa7146/av7110/av7110_hw.c new file mode 100644 index 000000000..93ca31e38 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_hw.c @@ -0,0 +1,1204 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * av7110_hw.c: av7110 low level hardware access and firmware interface + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * originally based on code by: + * Copyright (C) 1998,1999 Christian Theiss + * + * the project's page is at https://linuxtv.org + */ + +/* for debugging ARM communication: */ +//#define COM_DEBUG + +#include +#include +#include +#include +#include + +#include "av7110.h" +#include "av7110_hw.h" + +#define _NOHANDSHAKE + +/* + * Max transfer size done by av7110_fw_cmd() + * + * The maximum size passed to this function is 6 bytes. The buffer also + * uses two additional ones for type and size. So, 8 bytes is enough. + */ +#define MAX_XFER_SIZE 8 + +/**************************************************************************** + * DEBI functions + ****************************************************************************/ + +/* This DEBI code is based on the Stradis driver + by Nathan Laredo */ + +int av7110_debiwrite(struct av7110 *av7110, u32 config, + int addr, u32 val, unsigned int count) +{ + struct saa7146_dev *dev = av7110->dev; + + if (count > 32764) { + printk("%s: invalid count %d\n", __func__, count); + return -1; + } + if (saa7146_wait_for_debi_done(av7110->dev, 0) < 0) { + printk("%s: wait_for_debi_done failed\n", __func__); + return -1; + } + saa7146_write(dev, DEBI_CONFIG, config); + if (count <= 4) /* immediate transfer */ + saa7146_write(dev, DEBI_AD, val); + else /* block transfer */ + saa7146_write(dev, DEBI_AD, av7110->debi_bus); + saa7146_write(dev, DEBI_COMMAND, (count << 17) | (addr & 0xffff)); + saa7146_write(dev, MC2, (2 << 16) | 2); + return 0; +} + +u32 av7110_debiread(struct av7110 *av7110, u32 config, int addr, unsigned int count) +{ + struct saa7146_dev *dev = av7110->dev; + u32 result = 0; + + if (count > 32764) { + printk("%s: invalid count %d\n", __func__, count); + return 0; + } + if (saa7146_wait_for_debi_done(av7110->dev, 0) < 0) { + printk("%s: wait_for_debi_done #1 failed\n", __func__); + return 0; + } + saa7146_write(dev, DEBI_AD, av7110->debi_bus); + saa7146_write(dev, DEBI_COMMAND, (count << 17) | 0x10000 | (addr & 0xffff)); + + saa7146_write(dev, DEBI_CONFIG, config); + saa7146_write(dev, MC2, (2 << 16) | 2); + if (count > 4) + return count; + if (saa7146_wait_for_debi_done(av7110->dev, 0) < 0) { + printk("%s: wait_for_debi_done #2 failed\n", __func__); + return 0; + } + + result = saa7146_read(dev, DEBI_AD); + result &= (0xffffffffUL >> ((4 - count) * 8)); + return result; +} + + + +/* av7110 ARM core boot stuff */ +#if 0 +void av7110_reset_arm(struct av7110 *av7110) +{ + saa7146_setgpio(av7110->dev, RESET_LINE, SAA7146_GPIO_OUTLO); + + /* Disable DEBI and GPIO irq */ + SAA7146_IER_DISABLE(av7110->dev, MASK_19 | MASK_03); + SAA7146_ISR_CLEAR(av7110->dev, MASK_19 | MASK_03); + + saa7146_setgpio(av7110->dev, RESET_LINE, SAA7146_GPIO_OUTHI); + msleep(30); /* the firmware needs some time to initialize */ + + ARM_ResetMailBox(av7110); + + SAA7146_ISR_CLEAR(av7110->dev, MASK_19 | MASK_03); + SAA7146_IER_ENABLE(av7110->dev, MASK_03); + + av7110->arm_ready = 1; + dprintk(1, "reset ARM\n"); +} +#endif /* 0 */ + +static int waitdebi(struct av7110 *av7110, int adr, int state) +{ + int k; + + dprintk(4, "%p\n", av7110); + + for (k = 0; k < 100; k++) { + if (irdebi(av7110, DEBINOSWAP, adr, 0, 2) == state) + return 0; + udelay(5); + } + return -ETIMEDOUT; +} + +static int load_dram(struct av7110 *av7110, u32 *data, int len) +{ + int i; + int blocks, rest; + u32 base, bootblock = AV7110_BOOT_BLOCK; + + dprintk(4, "%p\n", av7110); + + blocks = len / AV7110_BOOT_MAX_SIZE; + rest = len % AV7110_BOOT_MAX_SIZE; + base = DRAM_START_CODE; + + for (i = 0; i < blocks; i++) { + if (waitdebi(av7110, AV7110_BOOT_STATE, BOOTSTATE_BUFFER_EMPTY) < 0) { + printk(KERN_ERR "dvb-ttpci: load_dram(): timeout at block %d\n", i); + return -ETIMEDOUT; + } + dprintk(4, "writing DRAM block %d\n", i); + mwdebi(av7110, DEBISWAB, bootblock, + ((u8 *)data) + i * AV7110_BOOT_MAX_SIZE, AV7110_BOOT_MAX_SIZE); + bootblock ^= 0x1400; + iwdebi(av7110, DEBISWAB, AV7110_BOOT_BASE, swab32(base), 4); + iwdebi(av7110, DEBINOSWAP, AV7110_BOOT_SIZE, AV7110_BOOT_MAX_SIZE, 2); + iwdebi(av7110, DEBINOSWAP, AV7110_BOOT_STATE, BOOTSTATE_BUFFER_FULL, 2); + base += AV7110_BOOT_MAX_SIZE; + } + + if (rest > 0) { + if (waitdebi(av7110, AV7110_BOOT_STATE, BOOTSTATE_BUFFER_EMPTY) < 0) { + printk(KERN_ERR "dvb-ttpci: load_dram(): timeout at last block\n"); + return -ETIMEDOUT; + } + if (rest > 4) + mwdebi(av7110, DEBISWAB, bootblock, + ((u8 *)data) + i * AV7110_BOOT_MAX_SIZE, rest); + else + mwdebi(av7110, DEBISWAB, bootblock, + ((u8 *)data) + i * AV7110_BOOT_MAX_SIZE - 4, rest + 4); + + iwdebi(av7110, DEBISWAB, AV7110_BOOT_BASE, swab32(base), 4); + iwdebi(av7110, DEBINOSWAP, AV7110_BOOT_SIZE, rest, 2); + iwdebi(av7110, DEBINOSWAP, AV7110_BOOT_STATE, BOOTSTATE_BUFFER_FULL, 2); + } + if (waitdebi(av7110, AV7110_BOOT_STATE, BOOTSTATE_BUFFER_EMPTY) < 0) { + printk(KERN_ERR "dvb-ttpci: load_dram(): timeout after last block\n"); + return -ETIMEDOUT; + } + iwdebi(av7110, DEBINOSWAP, AV7110_BOOT_SIZE, 0, 2); + iwdebi(av7110, DEBINOSWAP, AV7110_BOOT_STATE, BOOTSTATE_BUFFER_FULL, 2); + if (waitdebi(av7110, AV7110_BOOT_STATE, BOOTSTATE_AV7110_BOOT_COMPLETE) < 0) { + printk(KERN_ERR "dvb-ttpci: load_dram(): final handshake timeout\n"); + return -ETIMEDOUT; + } + return 0; +} + + +/* we cannot write av7110 DRAM directly, so load a bootloader into + * the DPRAM which implements a simple boot protocol */ +int av7110_bootarm(struct av7110 *av7110) +{ + const struct firmware *fw; + const char *fw_name = "av7110/bootcode.bin"; + struct saa7146_dev *dev = av7110->dev; + u32 ret; + int i; + + dprintk(4, "%p\n", av7110); + + av7110->arm_ready = 0; + + saa7146_setgpio(dev, RESET_LINE, SAA7146_GPIO_OUTLO); + + /* Disable DEBI and GPIO irq */ + SAA7146_IER_DISABLE(av7110->dev, MASK_03 | MASK_19); + SAA7146_ISR_CLEAR(av7110->dev, MASK_19 | MASK_03); + + /* enable DEBI */ + saa7146_write(av7110->dev, MC1, 0x08800880); + saa7146_write(av7110->dev, DD1_STREAM_B, 0x00000000); + saa7146_write(av7110->dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + + /* test DEBI */ + iwdebi(av7110, DEBISWAP, DPRAM_BASE, 0x76543210, 4); + /* FIXME: Why does Nexus CA require 2x iwdebi for first init? */ + iwdebi(av7110, DEBISWAP, DPRAM_BASE, 0x76543210, 4); + + if ((ret=irdebi(av7110, DEBINOSWAP, DPRAM_BASE, 0, 4)) != 0x10325476) { + printk(KERN_ERR "dvb-ttpci: debi test in av7110_bootarm() failed: %08x != %08x (check your BIOS 'Plug&Play OS' settings)\n", + ret, 0x10325476); + return -1; + } + for (i = 0; i < 8192; i += 4) + iwdebi(av7110, DEBISWAP, DPRAM_BASE + i, 0x00, 4); + dprintk(2, "debi test OK\n"); + + /* boot */ + dprintk(1, "load boot code\n"); + saa7146_setgpio(dev, ARM_IRQ_LINE, SAA7146_GPIO_IRQLO); + //saa7146_setgpio(dev, DEBI_DONE_LINE, SAA7146_GPIO_INPUT); + //saa7146_setgpio(dev, 3, SAA7146_GPIO_INPUT); + + ret = request_firmware(&fw, fw_name, &dev->pci->dev); + if (ret) { + printk(KERN_ERR "dvb-ttpci: Failed to load firmware \"%s\"\n", + fw_name); + return ret; + } + + mwdebi(av7110, DEBISWAB, DPRAM_BASE, fw->data, fw->size); + release_firmware(fw); + iwdebi(av7110, DEBINOSWAP, AV7110_BOOT_STATE, BOOTSTATE_BUFFER_FULL, 2); + + if (saa7146_wait_for_debi_done(av7110->dev, 1)) { + printk(KERN_ERR "dvb-ttpci: av7110_bootarm(): saa7146_wait_for_debi_done() timed out\n"); + return -ETIMEDOUT; + } + saa7146_setgpio(dev, RESET_LINE, SAA7146_GPIO_OUTHI); + mdelay(1); + + dprintk(1, "load dram code\n"); + if (load_dram(av7110, (u32 *)av7110->bin_root, av7110->size_root) < 0) { + printk(KERN_ERR "dvb-ttpci: av7110_bootarm(): load_dram() failed\n"); + return -1; + } + + saa7146_setgpio(dev, RESET_LINE, SAA7146_GPIO_OUTLO); + mdelay(1); + + dprintk(1, "load dpram code\n"); + mwdebi(av7110, DEBISWAB, DPRAM_BASE, av7110->bin_dpram, av7110->size_dpram); + + if (saa7146_wait_for_debi_done(av7110->dev, 1)) { + printk(KERN_ERR "dvb-ttpci: av7110_bootarm(): saa7146_wait_for_debi_done() timed out after loading DRAM\n"); + return -ETIMEDOUT; + } + saa7146_setgpio(dev, RESET_LINE, SAA7146_GPIO_OUTHI); + msleep(30); /* the firmware needs some time to initialize */ + + //ARM_ClearIrq(av7110); + ARM_ResetMailBox(av7110); + SAA7146_ISR_CLEAR(av7110->dev, MASK_19 | MASK_03); + SAA7146_IER_ENABLE(av7110->dev, MASK_03); + + av7110->arm_errors = 0; + av7110->arm_ready = 1; + return 0; +} +MODULE_FIRMWARE("av7110/bootcode.bin"); + +/**************************************************************************** + * DEBI command polling + ****************************************************************************/ + +int av7110_wait_msgstate(struct av7110 *av7110, u16 flags) +{ + unsigned long start; + u32 stat; + int err; + + if (FW_VERSION(av7110->arm_app) <= 0x261c) { + /* not supported by old firmware */ + msleep(50); + return 0; + } + + /* new firmware */ + start = jiffies; + for (;;) { + err = time_after(jiffies, start + ARM_WAIT_FREE); + if (mutex_lock_interruptible(&av7110->dcomlock)) + return -ERESTARTSYS; + stat = rdebi(av7110, DEBINOSWAP, MSGSTATE, 0, 2); + mutex_unlock(&av7110->dcomlock); + if ((stat & flags) == 0) + break; + if (err) { + printk(KERN_ERR "%s: timeout waiting for MSGSTATE %04x\n", + __func__, stat & flags); + return -ETIMEDOUT; + } + msleep(1); + } + return 0; +} + +static int __av7110_send_fw_cmd(struct av7110 *av7110, u16* buf, int length) +{ + int i; + unsigned long start; + char *type = NULL; + u16 flags[2] = {0, 0}; + u32 stat; + int err; + +// dprintk(4, "%p\n", av7110); + + if (!av7110->arm_ready) { + dprintk(1, "arm not ready.\n"); + return -ENXIO; + } + + start = jiffies; + while (1) { + err = time_after(jiffies, start + ARM_WAIT_FREE); + if (rdebi(av7110, DEBINOSWAP, COMMAND, 0, 2) == 0) + break; + if (err) { + printk(KERN_ERR "dvb-ttpci: %s(): timeout waiting for COMMAND idle\n", __func__); + av7110->arm_errors++; + return -ETIMEDOUT; + } + msleep(1); + } + + if (FW_VERSION(av7110->arm_app) <= 0x261f) + wdebi(av7110, DEBINOSWAP, COM_IF_LOCK, 0xffff, 2); + +#ifndef _NOHANDSHAKE + start = jiffies; + while (1) { + err = time_after(jiffies, start + ARM_WAIT_SHAKE); + if (rdebi(av7110, DEBINOSWAP, HANDSHAKE_REG, 0, 2) == 0) + break; + if (err) { + printk(KERN_ERR "dvb-ttpci: %s(): timeout waiting for HANDSHAKE_REG\n", __func__); + return -ETIMEDOUT; + } + msleep(1); + } +#endif + + switch ((buf[0] >> 8) & 0xff) { + case COMTYPE_PIDFILTER: + case COMTYPE_ENCODER: + case COMTYPE_REC_PLAY: + case COMTYPE_MPEGDECODER: + type = "MSG"; + flags[0] = GPMQOver; + flags[1] = GPMQFull; + break; + case COMTYPE_OSD: + type = "OSD"; + flags[0] = OSDQOver; + flags[1] = OSDQFull; + break; + case COMTYPE_MISC: + if (FW_VERSION(av7110->arm_app) >= 0x261d) { + type = "MSG"; + flags[0] = GPMQOver; + flags[1] = GPMQBusy; + } + break; + default: + break; + } + + if (type != NULL) { + /* non-immediate COMMAND type */ + start = jiffies; + for (;;) { + err = time_after(jiffies, start + ARM_WAIT_FREE); + stat = rdebi(av7110, DEBINOSWAP, MSGSTATE, 0, 2); + if (stat & flags[0]) { + printk(KERN_ERR "%s: %s QUEUE overflow\n", + __func__, type); + return -1; + } + if ((stat & flags[1]) == 0) + break; + if (err) { + printk(KERN_ERR "%s: timeout waiting on busy %s QUEUE\n", + __func__, type); + av7110->arm_errors++; + return -ETIMEDOUT; + } + msleep(1); + } + } + + for (i = 2; i < length; i++) + wdebi(av7110, DEBINOSWAP, COMMAND + 2 * i, (u32) buf[i], 2); + + if (length) + wdebi(av7110, DEBINOSWAP, COMMAND + 2, (u32) buf[1], 2); + else + wdebi(av7110, DEBINOSWAP, COMMAND + 2, 0, 2); + + wdebi(av7110, DEBINOSWAP, COMMAND, (u32) buf[0], 2); + + if (FW_VERSION(av7110->arm_app) <= 0x261f) + wdebi(av7110, DEBINOSWAP, COM_IF_LOCK, 0x0000, 2); + +#ifdef COM_DEBUG + start = jiffies; + while (1) { + err = time_after(jiffies, start + ARM_WAIT_FREE); + if (rdebi(av7110, DEBINOSWAP, COMMAND, 0, 2) == 0) + break; + if (err) { + printk(KERN_ERR "dvb-ttpci: %s(): timeout waiting for COMMAND %d to complete\n", + __func__, (buf[0] >> 8) & 0xff); + return -ETIMEDOUT; + } + msleep(1); + } + + stat = rdebi(av7110, DEBINOSWAP, MSGSTATE, 0, 2); + if (stat & GPMQOver) { + printk(KERN_ERR "dvb-ttpci: %s(): GPMQOver\n", __func__); + return -ENOSPC; + } + else if (stat & OSDQOver) { + printk(KERN_ERR "dvb-ttpci: %s(): OSDQOver\n", __func__); + return -ENOSPC; + } +#endif + + return 0; +} + +static int av7110_send_fw_cmd(struct av7110 *av7110, u16* buf, int length) +{ + int ret; + +// dprintk(4, "%p\n", av7110); + + if (!av7110->arm_ready) { + dprintk(1, "arm not ready.\n"); + return -1; + } + if (mutex_lock_interruptible(&av7110->dcomlock)) + return -ERESTARTSYS; + + ret = __av7110_send_fw_cmd(av7110, buf, length); + mutex_unlock(&av7110->dcomlock); + if (ret && ret!=-ERESTARTSYS) + printk(KERN_ERR "dvb-ttpci: %s(): av7110_send_fw_cmd error %d\n", + __func__, ret); + return ret; +} + +int av7110_fw_cmd(struct av7110 *av7110, int type, int com, int num, ...) +{ + va_list args; + u16 buf[MAX_XFER_SIZE]; + int i, ret; + +// dprintk(4, "%p\n", av7110); + + if (2 + num > ARRAY_SIZE(buf)) { + printk(KERN_WARNING + "%s: %s len=%d is too big!\n", + KBUILD_MODNAME, __func__, num); + return -EINVAL; + } + + buf[0] = ((type << 8) | com); + buf[1] = num; + + if (num) { + va_start(args, num); + for (i = 0; i < num; i++) + buf[i + 2] = va_arg(args, u32); + va_end(args); + } + + ret = av7110_send_fw_cmd(av7110, buf, num + 2); + if (ret && ret != -ERESTARTSYS) + printk(KERN_ERR "dvb-ttpci: av7110_fw_cmd error %d\n", ret); + return ret; +} + +#if 0 +int av7110_send_ci_cmd(struct av7110 *av7110, u8 subcom, u8 *buf, u8 len) +{ + int i, ret; + u16 cmd[18] = { ((COMTYPE_COMMON_IF << 8) + subcom), + 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + + dprintk(4, "%p\n", av7110); + + for(i = 0; i < len && i < 32; i++) + { + if(i % 2 == 0) + cmd[(i / 2) + 2] = (u16)(buf[i]) << 8; + else + cmd[(i / 2) + 2] |= buf[i]; + } + + ret = av7110_send_fw_cmd(av7110, cmd, 18); + if (ret && ret != -ERESTARTSYS) + printk(KERN_ERR "dvb-ttpci: av7110_send_ci_cmd error %d\n", ret); + return ret; +} +#endif /* 0 */ + +int av7110_fw_request(struct av7110 *av7110, u16 *request_buf, + int request_buf_len, u16 *reply_buf, int reply_buf_len) +{ + int err; + s16 i; + unsigned long start; +#ifdef COM_DEBUG + u32 stat; +#endif + + dprintk(4, "%p\n", av7110); + + if (!av7110->arm_ready) { + dprintk(1, "arm not ready.\n"); + return -1; + } + + if (mutex_lock_interruptible(&av7110->dcomlock)) + return -ERESTARTSYS; + + if ((err = __av7110_send_fw_cmd(av7110, request_buf, request_buf_len)) < 0) { + mutex_unlock(&av7110->dcomlock); + printk(KERN_ERR "dvb-ttpci: av7110_fw_request error %d\n", err); + return err; + } + + start = jiffies; + while (1) { + err = time_after(jiffies, start + ARM_WAIT_FREE); + if (rdebi(av7110, DEBINOSWAP, COMMAND, 0, 2) == 0) + break; + if (err) { + printk(KERN_ERR "%s: timeout waiting for COMMAND to complete\n", __func__); + mutex_unlock(&av7110->dcomlock); + return -ETIMEDOUT; + } +#ifdef _NOHANDSHAKE + msleep(1); +#endif + } + +#ifndef _NOHANDSHAKE + start = jiffies; + while (1) { + err = time_after(jiffies, start + ARM_WAIT_SHAKE); + if (rdebi(av7110, DEBINOSWAP, HANDSHAKE_REG, 0, 2) == 0) + break; + if (err) { + printk(KERN_ERR "%s: timeout waiting for HANDSHAKE_REG\n", __func__); + mutex_unlock(&av7110->dcomlock); + return -ETIMEDOUT; + } + msleep(1); + } +#endif + +#ifdef COM_DEBUG + stat = rdebi(av7110, DEBINOSWAP, MSGSTATE, 0, 2); + if (stat & GPMQOver) { + printk(KERN_ERR "%s: GPMQOver\n", __func__); + mutex_unlock(&av7110->dcomlock); + return -1; + } + else if (stat & OSDQOver) { + printk(KERN_ERR "%s: OSDQOver\n", __func__); + mutex_unlock(&av7110->dcomlock); + return -1; + } +#endif + + for (i = 0; i < reply_buf_len; i++) + reply_buf[i] = rdebi(av7110, DEBINOSWAP, COM_BUFF + 2 * i, 0, 2); + + mutex_unlock(&av7110->dcomlock); + return 0; +} + +static int av7110_fw_query(struct av7110 *av7110, u16 tag, u16* buf, s16 length) +{ + int ret; + ret = av7110_fw_request(av7110, &tag, 0, buf, length); + if (ret) + printk(KERN_ERR "dvb-ttpci: av7110_fw_query error %d\n", ret); + return ret; +} + + +/**************************************************************************** + * Firmware commands + ****************************************************************************/ + +/* get version of the firmware ROM, RTSL, video ucode and ARM application */ +int av7110_firmversion(struct av7110 *av7110) +{ + u16 buf[20]; + u16 tag = ((COMTYPE_REQUEST << 8) + ReqVersion); + + dprintk(4, "%p\n", av7110); + + if (av7110_fw_query(av7110, tag, buf, 16)) { + printk("dvb-ttpci: failed to boot firmware @ card %d\n", + av7110->dvb_adapter.num); + return -EIO; + } + + av7110->arm_fw = (buf[0] << 16) + buf[1]; + av7110->arm_rtsl = (buf[2] << 16) + buf[3]; + av7110->arm_vid = (buf[4] << 16) + buf[5]; + av7110->arm_app = (buf[6] << 16) + buf[7]; + av7110->avtype = (buf[8] << 16) + buf[9]; + + printk("dvb-ttpci: info @ card %d: firm %08x, rtsl %08x, vid %08x, app %08x\n", + av7110->dvb_adapter.num, av7110->arm_fw, + av7110->arm_rtsl, av7110->arm_vid, av7110->arm_app); + + /* print firmware capabilities */ + if (FW_CI_LL_SUPPORT(av7110->arm_app)) + printk("dvb-ttpci: firmware @ card %d supports CI link layer interface\n", + av7110->dvb_adapter.num); + else + printk("dvb-ttpci: no firmware support for CI link layer interface @ card %d\n", + av7110->dvb_adapter.num); + + return 0; +} + + +int av7110_diseqc_send(struct av7110 *av7110, int len, u8 *msg, unsigned long burst) +{ + int i, ret; + u16 buf[18] = { ((COMTYPE_AUDIODAC << 8) + SendDiSEqC), + 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + + dprintk(4, "%p\n", av7110); + + if (len > 10) + len = 10; + + buf[1] = len + 2; + buf[2] = len; + + if (burst != -1) + buf[3] = burst ? 0x01 : 0x00; + else + buf[3] = 0xffff; + + for (i = 0; i < len; i++) + buf[i + 4] = msg[i]; + + ret = av7110_send_fw_cmd(av7110, buf, 18); + if (ret && ret!=-ERESTARTSYS) + printk(KERN_ERR "dvb-ttpci: av7110_diseqc_send error %d\n", ret); + return ret; +} + + +#ifdef CONFIG_DVB_AV7110_OSD + +static inline int SetColorBlend(struct av7110 *av7110, u8 windownr) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, SetCBlend, 1, windownr); +} + +static inline int SetBlend_(struct av7110 *av7110, u8 windownr, + enum av7110_osd_palette_type colordepth, u16 index, u8 blending) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, SetBlend, 4, + windownr, colordepth, index, blending); +} + +static inline int SetColor_(struct av7110 *av7110, u8 windownr, + enum av7110_osd_palette_type colordepth, u16 index, u16 colorhi, u16 colorlo) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, SetColor, 5, + windownr, colordepth, index, colorhi, colorlo); +} + +static inline int SetFont(struct av7110 *av7110, u8 windownr, u8 fontsize, + u16 colorfg, u16 colorbg) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, Set_Font, 4, + windownr, fontsize, colorfg, colorbg); +} + +static int FlushText(struct av7110 *av7110) +{ + unsigned long start; + int err; + + if (mutex_lock_interruptible(&av7110->dcomlock)) + return -ERESTARTSYS; + start = jiffies; + while (1) { + err = time_after(jiffies, start + ARM_WAIT_OSD); + if (rdebi(av7110, DEBINOSWAP, BUFF1_BASE, 0, 2) == 0) + break; + if (err) { + printk(KERN_ERR "dvb-ttpci: %s(): timeout waiting for BUFF1_BASE == 0\n", + __func__); + mutex_unlock(&av7110->dcomlock); + return -ETIMEDOUT; + } + msleep(1); + } + mutex_unlock(&av7110->dcomlock); + return 0; +} + +static int WriteText(struct av7110 *av7110, u8 win, u16 x, u16 y, char *buf) +{ + int i, ret; + unsigned long start; + int length = strlen(buf) + 1; + u16 cbuf[5] = { (COMTYPE_OSD << 8) + DText, 3, win, x, y }; + + if (mutex_lock_interruptible(&av7110->dcomlock)) + return -ERESTARTSYS; + + start = jiffies; + while (1) { + ret = time_after(jiffies, start + ARM_WAIT_OSD); + if (rdebi(av7110, DEBINOSWAP, BUFF1_BASE, 0, 2) == 0) + break; + if (ret) { + printk(KERN_ERR "dvb-ttpci: %s: timeout waiting for BUFF1_BASE == 0\n", + __func__); + mutex_unlock(&av7110->dcomlock); + return -ETIMEDOUT; + } + msleep(1); + } +#ifndef _NOHANDSHAKE + start = jiffies; + while (1) { + ret = time_after(jiffies, start + ARM_WAIT_SHAKE); + if (rdebi(av7110, DEBINOSWAP, HANDSHAKE_REG, 0, 2) == 0) + break; + if (ret) { + printk(KERN_ERR "dvb-ttpci: %s: timeout waiting for HANDSHAKE_REG\n", + __func__); + mutex_unlock(&av7110->dcomlock); + return -ETIMEDOUT; + } + msleep(1); + } +#endif + for (i = 0; i < length / 2; i++) + wdebi(av7110, DEBINOSWAP, BUFF1_BASE + i * 2, + swab16(*(u16 *)(buf + 2 * i)), 2); + if (length & 1) + wdebi(av7110, DEBINOSWAP, BUFF1_BASE + i * 2, 0, 2); + ret = __av7110_send_fw_cmd(av7110, cbuf, 5); + mutex_unlock(&av7110->dcomlock); + if (ret && ret!=-ERESTARTSYS) + printk(KERN_ERR "dvb-ttpci: WriteText error %d\n", ret); + return ret; +} + +static inline int DrawLine(struct av7110 *av7110, u8 windownr, + u16 x, u16 y, u16 dx, u16 dy, u16 color) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, DLine, 6, + windownr, x, y, dx, dy, color); +} + +static inline int DrawBlock(struct av7110 *av7110, u8 windownr, + u16 x, u16 y, u16 dx, u16 dy, u16 color) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, DBox, 6, + windownr, x, y, dx, dy, color); +} + +static inline int HideWindow(struct av7110 *av7110, u8 windownr) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, WHide, 1, windownr); +} + +static inline int MoveWindowRel(struct av7110 *av7110, u8 windownr, u16 x, u16 y) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, WMoveD, 3, windownr, x, y); +} + +static inline int MoveWindowAbs(struct av7110 *av7110, u8 windownr, u16 x, u16 y) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, WMoveA, 3, windownr, x, y); +} + +static inline int DestroyOSDWindow(struct av7110 *av7110, u8 windownr) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, WDestroy, 1, windownr); +} + +static inline int CreateOSDWindow(struct av7110 *av7110, u8 windownr, + osd_raw_window_t disptype, + u16 width, u16 height) +{ + return av7110_fw_cmd(av7110, COMTYPE_OSD, WCreate, 4, + windownr, disptype, width, height); +} + + +static enum av7110_osd_palette_type bpp2pal[8] = { + Pal1Bit, Pal2Bit, 0, Pal4Bit, 0, 0, 0, Pal8Bit +}; +static osd_raw_window_t bpp2bit[8] = { + OSD_BITMAP1, OSD_BITMAP2, 0, OSD_BITMAP4, 0, 0, 0, OSD_BITMAP8 +}; + +static inline int WaitUntilBmpLoaded(struct av7110 *av7110) +{ + int ret = wait_event_timeout(av7110->bmpq, + av7110->bmp_state != BMP_LOADING, 10*HZ); + if (ret == 0) { + printk("dvb-ttpci: warning: timeout waiting in LoadBitmap: %d, %d\n", + ret, av7110->bmp_state); + av7110->bmp_state = BMP_NONE; + return -ETIMEDOUT; + } + return 0; +} + +static inline int LoadBitmap(struct av7110 *av7110, + u16 dx, u16 dy, int inc, u8 __user * data) +{ + u16 format; + int bpp; + int i; + int d, delta; + u8 c; + int ret; + + dprintk(4, "%p\n", av7110); + + format = bpp2bit[av7110->osdbpp[av7110->osdwin]]; + + av7110->bmp_state = BMP_LOADING; + if (format == OSD_BITMAP8) { + bpp=8; delta = 1; + } else if (format == OSD_BITMAP4) { + bpp=4; delta = 2; + } else if (format == OSD_BITMAP2) { + bpp=2; delta = 4; + } else if (format == OSD_BITMAP1) { + bpp=1; delta = 8; + } else { + av7110->bmp_state = BMP_NONE; + return -EINVAL; + } + av7110->bmplen = ((dx * dy * bpp + 7) & ~7) / 8; + av7110->bmpp = 0; + if (av7110->bmplen > 32768) { + av7110->bmp_state = BMP_NONE; + return -EINVAL; + } + for (i = 0; i < dy; i++) { + if (copy_from_user(av7110->bmpbuf + 1024 + i * dx, data + i * inc, dx)) { + av7110->bmp_state = BMP_NONE; + return -EINVAL; + } + } + if (format != OSD_BITMAP8) { + for (i = 0; i < dx * dy / delta; i++) { + c = ((u8 *)av7110->bmpbuf)[1024 + i * delta + delta - 1]; + for (d = delta - 2; d >= 0; d--) { + c |= (((u8 *)av7110->bmpbuf)[1024 + i * delta + d] + << ((delta - d - 1) * bpp)); + ((u8 *)av7110->bmpbuf)[1024 + i] = c; + } + } + } + av7110->bmplen += 1024; + dprintk(4, "av7110_fw_cmd: LoadBmp size %d\n", av7110->bmplen); + ret = av7110_fw_cmd(av7110, COMTYPE_OSD, LoadBmp, 3, format, dx, dy); + if (!ret) + ret = WaitUntilBmpLoaded(av7110); + return ret; +} + +static int BlitBitmap(struct av7110 *av7110, u16 x, u16 y) +{ + dprintk(4, "%p\n", av7110); + + return av7110_fw_cmd(av7110, COMTYPE_OSD, BlitBmp, 4, av7110->osdwin, x, y, 0); +} + +static inline int ReleaseBitmap(struct av7110 *av7110) +{ + dprintk(4, "%p\n", av7110); + + if (av7110->bmp_state != BMP_LOADED && FW_VERSION(av7110->arm_app) < 0x261e) + return -1; + if (av7110->bmp_state == BMP_LOADING) + dprintk(1,"ReleaseBitmap called while BMP_LOADING\n"); + av7110->bmp_state = BMP_NONE; + return av7110_fw_cmd(av7110, COMTYPE_OSD, ReleaseBmp, 0); +} + +static u32 RGB2YUV(u16 R, u16 G, u16 B) +{ + u16 y, u, v; + u16 Y, Cr, Cb; + + y = R * 77 + G * 150 + B * 29; /* Luma=0.299R+0.587G+0.114B 0..65535 */ + u = 2048 + B * 8 -(y >> 5); /* Cr 0..4095 */ + v = 2048 + R * 8 -(y >> 5); /* Cb 0..4095 */ + + Y = y / 256; + Cb = u / 16; + Cr = v / 16; + + return Cr | (Cb << 16) | (Y << 8); +} + +static int OSDSetColor(struct av7110 *av7110, u8 color, u8 r, u8 g, u8 b, u8 blend) +{ + int ret; + + u16 ch, cl; + u32 yuv; + + yuv = blend ? RGB2YUV(r,g,b) : 0; + cl = (yuv & 0xffff); + ch = ((yuv >> 16) & 0xffff); + ret = SetColor_(av7110, av7110->osdwin, bpp2pal[av7110->osdbpp[av7110->osdwin]], + color, ch, cl); + if (!ret) + ret = SetBlend_(av7110, av7110->osdwin, bpp2pal[av7110->osdbpp[av7110->osdwin]], + color, ((blend >> 4) & 0x0f)); + return ret; +} + +static int OSDSetPalette(struct av7110 *av7110, u32 __user * colors, u8 first, u8 last) +{ + int i; + int length = last - first + 1; + + if (length * 4 > DATA_BUFF3_SIZE) + return -EINVAL; + + for (i = 0; i < length; i++) { + u32 color, blend, yuv; + + if (get_user(color, colors + i)) + return -EFAULT; + blend = (color & 0xF0000000) >> 4; + yuv = blend ? RGB2YUV(color & 0xFF, (color >> 8) & 0xFF, + (color >> 16) & 0xFF) | blend : 0; + yuv = ((yuv & 0xFFFF0000) >> 16) | ((yuv & 0x0000FFFF) << 16); + wdebi(av7110, DEBINOSWAP, DATA_BUFF3_BASE + i * 4, yuv, 4); + } + return av7110_fw_cmd(av7110, COMTYPE_OSD, Set_Palette, 4, + av7110->osdwin, + bpp2pal[av7110->osdbpp[av7110->osdwin]], + first, last); +} + +static int OSDSetBlock(struct av7110 *av7110, int x0, int y0, + int x1, int y1, int inc, u8 __user * data) +{ + uint w, h, bpp, bpl, size, lpb, bnum, brest; + int i; + int rc,release_rc; + + w = x1 - x0 + 1; + h = y1 - y0 + 1; + if (inc <= 0) + inc = w; + if (w <= 0 || w > 720 || h <= 0 || h > 576) + return -EINVAL; + bpp = av7110->osdbpp[av7110->osdwin] + 1; + bpl = ((w * bpp + 7) & ~7) / 8; + size = h * bpl; + lpb = (32 * 1024) / bpl; + bnum = size / (lpb * bpl); + brest = size - bnum * lpb * bpl; + + if (av7110->bmp_state == BMP_LOADING) { + /* possible if syscall is repeated by -ERESTARTSYS and if firmware cannot abort */ + BUG_ON (FW_VERSION(av7110->arm_app) >= 0x261e); + rc = WaitUntilBmpLoaded(av7110); + if (rc) + return rc; + /* just continue. This should work for all fw versions + * if bnum==1 && !brest && LoadBitmap was successful + */ + } + + rc = 0; + for (i = 0; i < bnum; i++) { + rc = LoadBitmap(av7110, w, lpb, inc, data); + if (rc) + break; + rc = BlitBitmap(av7110, x0, y0 + i * lpb); + if (rc) + break; + data += lpb * inc; + } + if (!rc && brest) { + rc = LoadBitmap(av7110, w, brest / bpl, inc, data); + if (!rc) + rc = BlitBitmap(av7110, x0, y0 + bnum * lpb); + } + release_rc = ReleaseBitmap(av7110); + if (!rc) + rc = release_rc; + if (rc) + dprintk(1,"returns %d\n",rc); + return rc; +} + +int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc) +{ + int ret; + + if (mutex_lock_interruptible(&av7110->osd_mutex)) + return -ERESTARTSYS; + + switch (dc->cmd) { + case OSD_Close: + ret = DestroyOSDWindow(av7110, av7110->osdwin); + break; + case OSD_Open: + av7110->osdbpp[av7110->osdwin] = (dc->color - 1) & 7; + ret = CreateOSDWindow(av7110, av7110->osdwin, + bpp2bit[av7110->osdbpp[av7110->osdwin]], + dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1); + if (ret) + break; + if (!dc->data) { + ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0); + if (ret) + break; + ret = SetColorBlend(av7110, av7110->osdwin); + } + break; + case OSD_Show: + ret = MoveWindowRel(av7110, av7110->osdwin, 0, 0); + break; + case OSD_Hide: + ret = HideWindow(av7110, av7110->osdwin); + break; + case OSD_Clear: + ret = DrawBlock(av7110, av7110->osdwin, 0, 0, 720, 576, 0); + break; + case OSD_Fill: + ret = DrawBlock(av7110, av7110->osdwin, 0, 0, 720, 576, dc->color); + break; + case OSD_SetColor: + ret = OSDSetColor(av7110, dc->color, dc->x0, dc->y0, dc->x1, dc->y1); + break; + case OSD_SetPalette: + if (FW_VERSION(av7110->arm_app) >= 0x2618) + ret = OSDSetPalette(av7110, dc->data, dc->color, dc->x0); + else { + int i, len = dc->x0-dc->color+1; + u8 __user *colors = (u8 __user *)dc->data; + u8 r, g = 0, b = 0, blend = 0; + ret = 0; + for (i = 0; icolor + i, r, g, b, blend); + if (ret) + break; + } + } + break; + case OSD_SetPixel: + ret = DrawLine(av7110, av7110->osdwin, + dc->x0, dc->y0, 0, 0, dc->color); + break; + case OSD_SetRow: + dc->y1 = dc->y0; + fallthrough; + case OSD_SetBlock: + ret = OSDSetBlock(av7110, dc->x0, dc->y0, dc->x1, dc->y1, dc->color, dc->data); + break; + case OSD_FillRow: + ret = DrawBlock(av7110, av7110->osdwin, dc->x0, dc->y0, + dc->x1-dc->x0+1, dc->y1, dc->color); + break; + case OSD_FillBlock: + ret = DrawBlock(av7110, av7110->osdwin, dc->x0, dc->y0, + dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1, dc->color); + break; + case OSD_Line: + ret = DrawLine(av7110, av7110->osdwin, + dc->x0, dc->y0, dc->x1 - dc->x0, dc->y1 - dc->y0, dc->color); + break; + case OSD_Text: + { + char textbuf[240]; + + if (strncpy_from_user(textbuf, dc->data, 240) < 0) { + ret = -EFAULT; + break; + } + textbuf[239] = 0; + if (dc->x1 > 3) + dc->x1 = 3; + ret = SetFont(av7110, av7110->osdwin, dc->x1, + (u16) (dc->color & 0xffff), (u16) (dc->color >> 16)); + if (!ret) + ret = FlushText(av7110); + if (!ret) + ret = WriteText(av7110, av7110->osdwin, dc->x0, dc->y0, textbuf); + break; + } + case OSD_SetWindow: + if (dc->x0 < 1 || dc->x0 > 7) + ret = -EINVAL; + else { + av7110->osdwin = dc->x0; + ret = 0; + } + break; + case OSD_MoveWindow: + ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0); + if (!ret) + ret = SetColorBlend(av7110, av7110->osdwin); + break; + case OSD_OpenRaw: + if (dc->color < OSD_BITMAP1 || dc->color > OSD_CURSOR) { + ret = -EINVAL; + break; + } + if (dc->color >= OSD_BITMAP1 && dc->color <= OSD_BITMAP8HR) + av7110->osdbpp[av7110->osdwin] = (1 << (dc->color & 3)) - 1; + else + av7110->osdbpp[av7110->osdwin] = 0; + ret = CreateOSDWindow(av7110, av7110->osdwin, (osd_raw_window_t)dc->color, + dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1); + if (ret) + break; + if (!dc->data) { + ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0); + if (!ret) + ret = SetColorBlend(av7110, av7110->osdwin); + } + break; + default: + ret = -EINVAL; + break; + } + + mutex_unlock(&av7110->osd_mutex); + if (ret==-ERESTARTSYS) + dprintk(1, "av7110_osd_cmd(%d) returns with -ERESTARTSYS\n",dc->cmd); + else if (ret) + dprintk(1, "av7110_osd_cmd(%d) returns with %d\n",dc->cmd,ret); + + return ret; +} + +int av7110_osd_capability(struct av7110 *av7110, osd_cap_t *cap) +{ + switch (cap->cmd) { + case OSD_CAP_MEMSIZE: + if (FW_4M_SDRAM(av7110->arm_app)) + cap->val = 1000000; + else + cap->val = 92000; + return 0; + default: + return -EINVAL; + } +} +#endif /* CONFIG_DVB_AV7110_OSD */ diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_hw.h b/drivers/staging/media/deprecated/saa7146/av7110/av7110_hw.h new file mode 100644 index 000000000..6380d8950 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_hw.h @@ -0,0 +1,496 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AV7110_HW_H_ +#define _AV7110_HW_H_ + +#include "av7110.h" + +/* DEBI transfer mode defs */ + +#define DEBINOSWAP 0x000e0000 +#define DEBISWAB 0x001e0000 +#define DEBISWAP 0x002e0000 + +#define ARM_WAIT_FREE (HZ) +#define ARM_WAIT_SHAKE (HZ/5) +#define ARM_WAIT_OSD (HZ) + + +enum av7110_bootstate +{ + BOOTSTATE_BUFFER_EMPTY = 0, + BOOTSTATE_BUFFER_FULL = 1, + BOOTSTATE_AV7110_BOOT_COMPLETE = 2 +}; + +enum av7110_type_rec_play_format +{ RP_None, + AudioPES, + AudioMp2, + AudioPCM, + VideoPES, + AV_PES +}; + +enum av7110_osd_palette_type +{ + NoPalet = 0, /* No palette */ + Pal1Bit = 2, /* 2 colors for 1 Bit Palette */ + Pal2Bit = 4, /* 4 colors for 2 bit palette */ + Pal4Bit = 16, /* 16 colors for 4 bit palette */ + Pal8Bit = 256 /* 256 colors for 16 bit palette */ +}; + +/* switch defines */ +#define SB_GPIO 3 +#define SB_OFF SAA7146_GPIO_OUTLO /* SlowBlank off (TV-Mode) */ +#define SB_ON SAA7146_GPIO_INPUT /* SlowBlank on (AV-Mode) */ +#define SB_WIDE SAA7146_GPIO_OUTHI /* SlowBlank 6V (16/9-Mode) (not implemented) */ + +#define FB_GPIO 1 +#define FB_OFF SAA7146_GPIO_LO /* FastBlank off (CVBS-Mode) */ +#define FB_ON SAA7146_GPIO_OUTHI /* FastBlank on (RGB-Mode) */ +#define FB_LOOP SAA7146_GPIO_INPUT /* FastBlank loop-through (PC graphics ???) */ + +enum av7110_video_output_mode +{ + NO_OUT = 0, /* disable analog output */ + CVBS_RGB_OUT = 1, + CVBS_YC_OUT = 2, + YC_OUT = 3 +}; + +/* firmware internal msg q status: */ +#define GPMQFull 0x0001 /* Main Message Queue Full */ +#define GPMQOver 0x0002 /* Main Message Queue Overflow */ +#define HPQFull 0x0004 /* High Priority Msg Queue Full */ +#define HPQOver 0x0008 +#define OSDQFull 0x0010 /* OSD Queue Full */ +#define OSDQOver 0x0020 +#define GPMQBusy 0x0040 /* Queue not empty, FW >= 261d */ +#define HPQBusy 0x0080 +#define OSDQBusy 0x0100 + +/* hw section filter flags */ +#define SECTION_EIT 0x01 +#define SECTION_SINGLE 0x00 +#define SECTION_CYCLE 0x02 +#define SECTION_CONTINUOS 0x04 +#define SECTION_MODE 0x06 +#define SECTION_IPMPE 0x0C /* size up to 4k */ +#define SECTION_HIGH_SPEED 0x1C /* larger buffer */ +#define DATA_PIPING_FLAG 0x20 /* for Data Piping Filter */ + +#define PBUFSIZE_NONE 0x0000 +#define PBUFSIZE_1P 0x0100 +#define PBUFSIZE_2P 0x0200 +#define PBUFSIZE_1K 0x0300 +#define PBUFSIZE_2K 0x0400 +#define PBUFSIZE_4K 0x0500 +#define PBUFSIZE_8K 0x0600 +#define PBUFSIZE_16K 0x0700 +#define PBUFSIZE_32K 0x0800 + + +/* firmware command codes */ +enum av7110_osd_command { + WCreate, + WDestroy, + WMoveD, + WMoveA, + WHide, + WTop, + DBox, + DLine, + DText, + Set_Font, + SetColor, + SetBlend, + SetWBlend, + SetCBlend, + SetNonBlend, + LoadBmp, + BlitBmp, + ReleaseBmp, + SetWTrans, + SetWNoTrans, + Set_Palette +}; + +enum av7110_pid_command { + MultiPID, + VideoPID, + AudioPID, + InitFilt, + FiltError, + NewVersion, + CacheError, + AddPIDFilter, + DelPIDFilter, + Scan, + SetDescr, + SetIR, + FlushTSQueue +}; + +enum av7110_mpeg_command { + SelAudChannels +}; + +enum av7110_audio_command { + AudioDAC, + CabADAC, + ON22K, + OFF22K, + MainSwitch, + ADSwitch, + SendDiSEqC, + SetRegister, + SpdifSwitch +}; + +enum av7110_request_command { + AudioState, + AudioBuffState, + VideoState1, + VideoState2, + VideoState3, + CrashCounter, + ReqVersion, + ReqVCXO, + ReqRegister, + ReqSecFilterError, + ReqSTC +}; + +enum av7110_encoder_command { + SetVidMode, + SetTestMode, + LoadVidCode, + SetMonitorType, + SetPanScanType, + SetFreezeMode, + SetWSSConfig +}; + +enum av7110_rec_play_state { + __Record, + __Stop, + __Play, + __Pause, + __Slow, + __FF_IP, + __Scan_I, + __Continue +}; + +enum av7110_fw_cmd_misc { + AV7110_FW_VIDEO_ZOOM = 1, + AV7110_FW_VIDEO_COMMAND, + AV7110_FW_AUDIO_COMMAND +}; + +enum av7110_command_type { + COMTYPE_NOCOM, + COMTYPE_PIDFILTER, + COMTYPE_MPEGDECODER, + COMTYPE_OSD, + COMTYPE_BMP, + COMTYPE_ENCODER, + COMTYPE_AUDIODAC, + COMTYPE_REQUEST, + COMTYPE_SYSTEM, + COMTYPE_REC_PLAY, + COMTYPE_COMMON_IF, + COMTYPE_PID_FILTER, + COMTYPE_PES, + COMTYPE_TS, + COMTYPE_VIDEO, + COMTYPE_AUDIO, + COMTYPE_CI_LL, + COMTYPE_MISC = 0x80 +}; + +#define VID_NONE_PREF 0x00 /* No aspect ration processing preferred */ +#define VID_PAN_SCAN_PREF 0x01 /* Pan and Scan Display preferred */ +#define VID_VERT_COMP_PREF 0x02 /* Vertical compression display preferred */ +#define VID_VC_AND_PS_PREF 0x03 /* PanScan and vertical Compression if allowed */ +#define VID_CENTRE_CUT_PREF 0x05 /* PanScan with zero vector */ + +/* MPEG video decoder commands */ +#define AV_VIDEO_CMD_STOP 0x000e +#define AV_VIDEO_CMD_PLAY 0x000d +#define AV_VIDEO_CMD_FREEZE 0x0102 +#define AV_VIDEO_CMD_FFWD 0x0016 +#define AV_VIDEO_CMD_SLOW 0x0022 + +/* MPEG audio decoder commands */ +#define AUDIO_CMD_MUTE 0x0001 +#define AUDIO_CMD_UNMUTE 0x0002 +#define AUDIO_CMD_PCM16 0x0010 +#define AUDIO_CMD_STEREO 0x0080 +#define AUDIO_CMD_MONO_L 0x0100 +#define AUDIO_CMD_MONO_R 0x0200 +#define AUDIO_CMD_SYNC_OFF 0x000e +#define AUDIO_CMD_SYNC_ON 0x000f + +/* firmware data interface codes */ +#define DATA_NONE 0x00 +#define DATA_FSECTION 0x01 +#define DATA_IPMPE 0x02 +#define DATA_MPEG_RECORD 0x03 +#define DATA_DEBUG_MESSAGE 0x04 +#define DATA_COMMON_INTERFACE 0x05 +#define DATA_MPEG_PLAY 0x06 +#define DATA_BMP_LOAD 0x07 +#define DATA_IRCOMMAND 0x08 +#define DATA_PIPING 0x09 +#define DATA_STREAMING 0x0a +#define DATA_CI_GET 0x0b +#define DATA_CI_PUT 0x0c +#define DATA_MPEG_VIDEO_EVENT 0x0d + +#define DATA_PES_RECORD 0x10 +#define DATA_PES_PLAY 0x11 +#define DATA_TS_RECORD 0x12 +#define DATA_TS_PLAY 0x13 + +/* ancient CI command codes, only two are actually still used + * by the link level CI firmware */ +#define CI_CMD_ERROR 0x00 +#define CI_CMD_ACK 0x01 +#define CI_CMD_SYSTEM_READY 0x02 +#define CI_CMD_KEYPRESS 0x03 +#define CI_CMD_ON_TUNED 0x04 +#define CI_CMD_ON_SWITCH_PROGRAM 0x05 +#define CI_CMD_SECTION_ARRIVED 0x06 +#define CI_CMD_SECTION_TIMEOUT 0x07 +#define CI_CMD_TIME 0x08 +#define CI_CMD_ENTER_MENU 0x09 +#define CI_CMD_FAST_PSI 0x0a +#define CI_CMD_GET_SLOT_INFO 0x0b + +#define CI_MSG_NONE 0x00 +#define CI_MSG_CI_INFO 0x01 +#define CI_MSG_MENU 0x02 +#define CI_MSG_LIST 0x03 +#define CI_MSG_TEXT 0x04 +#define CI_MSG_REQUEST_INPUT 0x05 +#define CI_MSG_INPUT_COMPLETE 0x06 +#define CI_MSG_LIST_MORE 0x07 +#define CI_MSG_MENU_MORE 0x08 +#define CI_MSG_CLOSE_MMI_IMM 0x09 +#define CI_MSG_SECTION_REQUEST 0x0a +#define CI_MSG_CLOSE_FILTER 0x0b +#define CI_PSI_COMPLETE 0x0c +#define CI_MODULE_READY 0x0d +#define CI_SWITCH_PRG_REPLY 0x0e +#define CI_MSG_TEXT_MORE 0x0f + +#define CI_MSG_CA_PMT 0xe0 +#define CI_MSG_ERROR 0xf0 + + +/* base address of the dual ported RAM which serves as communication + * area between PCI bus and av7110, + * as seen by the DEBI bus of the saa7146 */ +#define DPRAM_BASE 0x4000 + +/* boot protocol area */ +#define AV7110_BOOT_STATE (DPRAM_BASE + 0x3F8) +#define AV7110_BOOT_SIZE (DPRAM_BASE + 0x3FA) +#define AV7110_BOOT_BASE (DPRAM_BASE + 0x3FC) +#define AV7110_BOOT_BLOCK (DPRAM_BASE + 0x400) +#define AV7110_BOOT_MAX_SIZE 0xc00 + +/* firmware command protocol area */ +#define IRQ_STATE (DPRAM_BASE + 0x0F4) +#define IRQ_STATE_EXT (DPRAM_BASE + 0x0F6) +#define MSGSTATE (DPRAM_BASE + 0x0F8) +#define COMMAND (DPRAM_BASE + 0x0FC) +#define COM_BUFF (DPRAM_BASE + 0x100) +#define COM_BUFF_SIZE 0x20 + +/* various data buffers */ +#define BUFF1_BASE (DPRAM_BASE + 0x120) +#define BUFF1_SIZE 0xE0 + +#define DATA_BUFF0_BASE (DPRAM_BASE + 0x200) +#define DATA_BUFF0_SIZE 0x0800 + +#define DATA_BUFF1_BASE (DATA_BUFF0_BASE+DATA_BUFF0_SIZE) +#define DATA_BUFF1_SIZE 0x0800 + +#define DATA_BUFF2_BASE (DATA_BUFF1_BASE+DATA_BUFF1_SIZE) +#define DATA_BUFF2_SIZE 0x0800 + +#define DATA_BUFF3_BASE (DATA_BUFF2_BASE+DATA_BUFF2_SIZE) +#define DATA_BUFF3_SIZE 0x0400 + +#define Reserved (DPRAM_BASE + 0x1E00) +#define Reserved_SIZE 0x1C0 + + +/* firmware status area */ +#define STATUS_BASE (DPRAM_BASE + 0x1FC0) +#define STATUS_LOOPS (STATUS_BASE + 0x08) + +#define STATUS_MPEG_WIDTH (STATUS_BASE + 0x0C) +/* ((aspect_ratio & 0xf) << 12) | (height & 0xfff) */ +#define STATUS_MPEG_HEIGHT_AR (STATUS_BASE + 0x0E) + +/* firmware data protocol area */ +#define RX_TYPE (DPRAM_BASE + 0x1FE8) +#define RX_LEN (DPRAM_BASE + 0x1FEA) +#define TX_TYPE (DPRAM_BASE + 0x1FEC) +#define TX_LEN (DPRAM_BASE + 0x1FEE) + +#define RX_BUFF (DPRAM_BASE + 0x1FF4) +#define TX_BUFF (DPRAM_BASE + 0x1FF6) + +#define HANDSHAKE_REG (DPRAM_BASE + 0x1FF8) +#define COM_IF_LOCK (DPRAM_BASE + 0x1FFA) + +#define IRQ_RX (DPRAM_BASE + 0x1FFC) +#define IRQ_TX (DPRAM_BASE + 0x1FFE) + +/* used by boot protocol to load firmware into av7110 DRAM */ +#define DRAM_START_CODE 0x2e000404 +#define DRAM_MAX_CODE_SIZE 0x00100000 + +/* saa7146 gpio lines */ +#define RESET_LINE 2 +#define DEBI_DONE_LINE 1 +#define ARM_IRQ_LINE 0 + + + +extern int av7110_bootarm(struct av7110 *av7110); +extern int av7110_firmversion(struct av7110 *av7110); +#define FW_CI_LL_SUPPORT(arm_app) ((arm_app) & 0x80000000) +#define FW_4M_SDRAM(arm_app) ((arm_app) & 0x40000000) +#define FW_VERSION(arm_app) ((arm_app) & 0x0000FFFF) + +extern int av7110_wait_msgstate(struct av7110 *av7110, u16 flags); +extern int av7110_fw_cmd(struct av7110 *av7110, int type, int com, int num, ...); +extern int av7110_fw_request(struct av7110 *av7110, u16 *request_buf, + int request_buf_len, u16 *reply_buf, int reply_buf_len); + + +/* DEBI (saa7146 data extension bus interface) access */ +extern int av7110_debiwrite(struct av7110 *av7110, u32 config, + int addr, u32 val, unsigned int count); +extern u32 av7110_debiread(struct av7110 *av7110, u32 config, + int addr, unsigned int count); + + +/* DEBI during interrupt */ +/* single word writes */ +static inline void iwdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) +{ + av7110_debiwrite(av7110, config, addr, val, count); +} + +/* buffer writes */ +static inline void mwdebi(struct av7110 *av7110, u32 config, int addr, + const u8 *val, int count) +{ + memcpy(av7110->debi_virt, val, count); + av7110_debiwrite(av7110, config, addr, 0, count); +} + +static inline u32 irdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) +{ + u32 res; + + res=av7110_debiread(av7110, config, addr, count); + if (count<=4) + memcpy(av7110->debi_virt, (char *) &res, count); + return res; +} + +/* DEBI outside interrupts, only for count <= 4! */ +static inline void wdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) +{ + unsigned long flags; + + spin_lock_irqsave(&av7110->debilock, flags); + av7110_debiwrite(av7110, config, addr, val, count); + spin_unlock_irqrestore(&av7110->debilock, flags); +} + +static inline u32 rdebi(struct av7110 *av7110, u32 config, int addr, u32 val, unsigned int count) +{ + unsigned long flags; + u32 res; + + spin_lock_irqsave(&av7110->debilock, flags); + res=av7110_debiread(av7110, config, addr, count); + spin_unlock_irqrestore(&av7110->debilock, flags); + return res; +} + +/* handle mailbox registers of the dual ported RAM */ +static inline void ARM_ResetMailBox(struct av7110 *av7110) +{ + unsigned long flags; + + spin_lock_irqsave(&av7110->debilock, flags); + av7110_debiread(av7110, DEBINOSWAP, IRQ_RX, 2); + av7110_debiwrite(av7110, DEBINOSWAP, IRQ_RX, 0, 2); + spin_unlock_irqrestore(&av7110->debilock, flags); +} + +static inline void ARM_ClearMailBox(struct av7110 *av7110) +{ + iwdebi(av7110, DEBINOSWAP, IRQ_RX, 0, 2); +} + +static inline void ARM_ClearIrq(struct av7110 *av7110) +{ + irdebi(av7110, DEBINOSWAP, IRQ_RX, 0, 2); +} + +/**************************************************************************** + * Firmware commands + ****************************************************************************/ + +static inline int SendDAC(struct av7110 *av7110, u8 addr, u8 data) +{ + return av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, AudioDAC, 2, addr, data); +} + +static inline int av7710_set_video_mode(struct av7110 *av7110, int mode) +{ + return av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetVidMode, 1, mode); +} + +static inline int vidcom(struct av7110 *av7110, u32 com, u32 arg) +{ + return av7110_fw_cmd(av7110, COMTYPE_MISC, AV7110_FW_VIDEO_COMMAND, 4, + (com>>16), (com&0xffff), + (arg>>16), (arg&0xffff)); +} + +static inline int audcom(struct av7110 *av7110, u32 com) +{ + return av7110_fw_cmd(av7110, COMTYPE_MISC, AV7110_FW_AUDIO_COMMAND, 2, + (com>>16), (com&0xffff)); +} + +static inline int Set22K(struct av7110 *av7110, int state) +{ + return av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, (state ? ON22K : OFF22K), 0); +} + + +extern int av7110_diseqc_send(struct av7110 *av7110, int len, u8 *msg, unsigned long burst); + + +#ifdef CONFIG_DVB_AV7110_OSD +extern int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc); +extern int av7110_osd_capability(struct av7110 *av7110, osd_cap_t *cap); +#endif /* CONFIG_DVB_AV7110_OSD */ + + + +#endif /* _AV7110_HW_H_ */ diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_ipack.c b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ipack.c new file mode 100644 index 000000000..30330ed01 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ipack.c @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "dvb_filter.h" +#include "av7110_ipack.h" +#include /* for memcpy() */ +#include + + +void av7110_ipack_reset(struct ipack *p) +{ + p->found = 0; + p->cid = 0; + p->plength = 0; + p->flag1 = 0; + p->flag2 = 0; + p->hlength = 0; + p->mpeg = 0; + p->check = 0; + p->which = 0; + p->done = 0; + p->count = 0; +} + + +int av7110_ipack_init(struct ipack *p, int size, + void (*func)(u8 *buf, int size, void *priv)) +{ + if (!(p->buf = vmalloc(size))) { + printk(KERN_WARNING "Couldn't allocate memory for ipack\n"); + return -ENOMEM; + } + p->size = size; + p->func = func; + p->repack_subids = 0; + av7110_ipack_reset(p); + return 0; +} + + +void av7110_ipack_free(struct ipack *p) +{ + vfree(p->buf); +} + + +static void send_ipack(struct ipack *p) +{ + int off; + struct dvb_audio_info ai; + int ac3_off = 0; + int streamid = 0; + int nframes = 0; + int f = 0; + + switch (p->mpeg) { + case 2: + if (p->count < 10) + return; + p->buf[3] = p->cid; + p->buf[4] = (u8)(((p->count - 6) & 0xff00) >> 8); + p->buf[5] = (u8)((p->count - 6) & 0x00ff); + if (p->repack_subids && p->cid == PRIVATE_STREAM1) { + off = 9 + p->buf[8]; + streamid = p->buf[off]; + if ((streamid & 0xf8) == 0x80) { + ai.off = 0; + ac3_off = ((p->buf[off + 2] << 8)| + p->buf[off + 3]); + if (ac3_off < p->count) + f = dvb_filter_get_ac3info(p->buf + off + 3 + ac3_off, + p->count - ac3_off, &ai, 0); + if (!f) { + nframes = (p->count - off - 3 - ac3_off) / + ai.framesize + 1; + p->buf[off + 2] = (ac3_off >> 8) & 0xff; + p->buf[off + 3] = (ac3_off) & 0xff; + p->buf[off + 1] = nframes; + ac3_off += nframes * ai.framesize - p->count; + } + } + } + p->func(p->buf, p->count, p->data); + + p->buf[6] = 0x80; + p->buf[7] = 0x00; + p->buf[8] = 0x00; + p->count = 9; + if (p->repack_subids && p->cid == PRIVATE_STREAM1 + && (streamid & 0xf8) == 0x80) { + p->count += 4; + p->buf[9] = streamid; + p->buf[10] = (ac3_off >> 8) & 0xff; + p->buf[11] = (ac3_off) & 0xff; + p->buf[12] = 0; + } + break; + + case 1: + if (p->count < 8) + return; + p->buf[3] = p->cid; + p->buf[4] = (u8)(((p->count - 6) & 0xff00) >> 8); + p->buf[5] = (u8)((p->count - 6) & 0x00ff); + p->func(p->buf, p->count, p->data); + + p->buf[6] = 0x0f; + p->count = 7; + break; + } +} + + +void av7110_ipack_flush(struct ipack *p) +{ + if (p->plength != MMAX_PLENGTH - 6 || p->found <= 6) + return; + p->plength = p->found - 6; + p->found = 0; + send_ipack(p); + av7110_ipack_reset(p); +} + + +static void write_ipack(struct ipack *p, const u8 *data, int count) +{ + u8 headr[3] = { 0x00, 0x00, 0x01 }; + + if (p->count < 6) { + memcpy(p->buf, headr, 3); + p->count = 6; + } + + if (p->count + count < p->size){ + memcpy(p->buf+p->count, data, count); + p->count += count; + } else { + int rest = p->size - p->count; + memcpy(p->buf+p->count, data, rest); + p->count += rest; + send_ipack(p); + if (count - rest > 0) + write_ipack(p, data + rest, count - rest); + } +} + + +int av7110_ipack_instant_repack (const u8 *buf, int count, struct ipack *p) +{ + int l; + int c = 0; + + while (c < count && (p->mpeg == 0 || + (p->mpeg == 1 && p->found < 7) || + (p->mpeg == 2 && p->found < 9)) + && (p->found < 5 || !p->done)) { + switch (p->found) { + case 0: + case 1: + if (buf[c] == 0x00) + p->found++; + else + p->found = 0; + c++; + break; + case 2: + if (buf[c] == 0x01) + p->found++; + else if (buf[c] == 0) + p->found = 2; + else + p->found = 0; + c++; + break; + case 3: + p->cid = 0; + switch (buf[c]) { + case PROG_STREAM_MAP: + case PRIVATE_STREAM2: + case PROG_STREAM_DIR: + case ECM_STREAM : + case EMM_STREAM : + case PADDING_STREAM : + case DSM_CC_STREAM : + case ISO13522_STREAM: + p->done = 1; + fallthrough; + case PRIVATE_STREAM1: + case VIDEO_STREAM_S ... VIDEO_STREAM_E: + case AUDIO_STREAM_S ... AUDIO_STREAM_E: + p->found++; + p->cid = buf[c]; + c++; + break; + default: + p->found = 0; + break; + } + break; + + case 4: + if (count-c > 1) { + p->plen[0] = buf[c]; + c++; + p->plen[1] = buf[c]; + c++; + p->found += 2; + p->plength = (p->plen[0] << 8) | p->plen[1]; + } else { + p->plen[0] = buf[c]; + p->found++; + return count; + } + break; + case 5: + p->plen[1] = buf[c]; + c++; + p->found++; + p->plength = (p->plen[0] << 8) | p->plen[1]; + break; + case 6: + if (!p->done) { + p->flag1 = buf[c]; + c++; + p->found++; + if ((p->flag1 & 0xc0) == 0x80) + p->mpeg = 2; + else { + p->hlength = 0; + p->which = 0; + p->mpeg = 1; + p->flag2 = 0; + } + } + break; + + case 7: + if (!p->done && p->mpeg == 2) { + p->flag2 = buf[c]; + c++; + p->found++; + } + break; + + case 8: + if (!p->done && p->mpeg == 2) { + p->hlength = buf[c]; + c++; + p->found++; + } + break; + } + } + + if (c == count) + return count; + + if (!p->plength) + p->plength = MMAX_PLENGTH - 6; + + if (p->done || ((p->mpeg == 2 && p->found >= 9) || + (p->mpeg == 1 && p->found >= 7))) { + switch (p->cid) { + case AUDIO_STREAM_S ... AUDIO_STREAM_E: + case VIDEO_STREAM_S ... VIDEO_STREAM_E: + case PRIVATE_STREAM1: + if (p->mpeg == 2 && p->found == 9) { + write_ipack(p, &p->flag1, 1); + write_ipack(p, &p->flag2, 1); + write_ipack(p, &p->hlength, 1); + } + + if (p->mpeg == 1 && p->found == 7) + write_ipack(p, &p->flag1, 1); + + if (p->mpeg == 2 && (p->flag2 & PTS_ONLY) && + p->found < 14) { + while (c < count && p->found < 14) { + p->pts[p->found - 9] = buf[c]; + write_ipack(p, buf + c, 1); + c++; + p->found++; + } + if (c == count) + return count; + } + + if (p->mpeg == 1 && p->which < 2000) { + + if (p->found == 7) { + p->check = p->flag1; + p->hlength = 1; + } + + while (!p->which && c < count && + p->check == 0xff){ + p->check = buf[c]; + write_ipack(p, buf + c, 1); + c++; + p->found++; + p->hlength++; + } + + if (c == count) + return count; + + if ((p->check & 0xc0) == 0x40 && !p->which) { + p->check = buf[c]; + write_ipack(p, buf + c, 1); + c++; + p->found++; + p->hlength++; + + p->which = 1; + if (c == count) + return count; + p->check = buf[c]; + write_ipack(p, buf + c, 1); + c++; + p->found++; + p->hlength++; + p->which = 2; + if (c == count) + return count; + } + + if (p->which == 1) { + p->check = buf[c]; + write_ipack(p, buf + c, 1); + c++; + p->found++; + p->hlength++; + p->which = 2; + if (c == count) + return count; + } + + if ((p->check & 0x30) && p->check != 0xff) { + p->flag2 = (p->check & 0xf0) << 2; + p->pts[0] = p->check; + p->which = 3; + } + + if (c == count) + return count; + if (p->which > 2){ + if ((p->flag2 & PTS_DTS_FLAGS) == PTS_ONLY) { + while (c < count && p->which < 7) { + p->pts[p->which - 2] = buf[c]; + write_ipack(p, buf + c, 1); + c++; + p->found++; + p->which++; + p->hlength++; + } + if (c == count) + return count; + } else if ((p->flag2 & PTS_DTS_FLAGS) == PTS_DTS) { + while (c < count && p->which < 12) { + if (p->which < 7) + p->pts[p->which - 2] = buf[c]; + write_ipack(p, buf + c, 1); + c++; + p->found++; + p->which++; + p->hlength++; + } + if (c == count) + return count; + } + p->which = 2000; + } + + } + + while (c < count && p->found < p->plength + 6) { + l = count - c; + if (l + p->found > p->plength + 6) + l = p->plength + 6 - p->found; + write_ipack(p, buf + c, l); + p->found += l; + c += l; + } + break; + } + + + if (p->done) { + if (p->found + count - c < p->plength + 6) { + p->found += count - c; + c = count; + } else { + c += p->plength + 6 - p->found; + p->found = p->plength + 6; + } + } + + if (p->plength && p->found == p->plength + 6) { + send_ipack(p); + av7110_ipack_reset(p); + if (c < count) + av7110_ipack_instant_repack(buf + c, count - c, p); + } + } + return count; +} diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_ipack.h b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ipack.h new file mode 100644 index 000000000..943ec899b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ipack.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AV7110_IPACK_H_ +#define _AV7110_IPACK_H_ + +extern int av7110_ipack_init(struct ipack *p, int size, + void (*func)(u8 *buf, int size, void *priv)); + +extern void av7110_ipack_reset(struct ipack *p); +extern int av7110_ipack_instant_repack(const u8 *buf, int count, struct ipack *p); +extern void av7110_ipack_free(struct ipack * p); +extern void av7110_ipack_flush(struct ipack *p); + +#endif diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_ir.c b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ir.c new file mode 100644 index 000000000..a851ba328 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_ir.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for the remote control of SAA7146 based AV7110 cards + * + * Copyright (C) 1999-2003 Holger Waechtler + * Copyright (C) 2003-2007 Oliver Endriss + * Copyright (C) 2019 Sean Young + */ + +#include +#include + +#include "av7110.h" +#include "av7110_hw.h" + +#define IR_RC5 0 +#define IR_RCMM 1 +#define IR_RC5_EXT 2 /* internal only */ + +/* interrupt handler */ +void av7110_ir_handler(struct av7110 *av7110, u32 ircom) +{ + struct rc_dev *rcdev = av7110->ir.rcdev; + enum rc_proto proto; + u32 command, addr, scancode; + u32 toggle; + + dprintk(4, "ir command = %08x\n", ircom); + + if (rcdev) { + switch (av7110->ir.ir_config) { + case IR_RC5: /* RC5: 5 bits device address, 6 bits command */ + command = ircom & 0x3f; + addr = (ircom >> 6) & 0x1f; + scancode = RC_SCANCODE_RC5(addr, command); + toggle = ircom & 0x0800; + proto = RC_PROTO_RC5; + break; + + case IR_RCMM: /* RCMM: 32 bits scancode */ + scancode = ircom & ~0x8000; + toggle = ircom & 0x8000; + proto = RC_PROTO_RCMM32; + break; + + case IR_RC5_EXT: + /* + * extended RC5: 5 bits device address, 7 bits command + * + * Extended RC5 uses only one start bit. The second + * start bit is re-assigned bit 6 of the command bit. + */ + command = ircom & 0x3f; + addr = (ircom >> 6) & 0x1f; + if (!(ircom & 0x1000)) + command |= 0x40; + scancode = RC_SCANCODE_RC5(addr, command); + toggle = ircom & 0x0800; + proto = RC_PROTO_RC5; + break; + default: + dprintk(2, "unknown ir config %d\n", + av7110->ir.ir_config); + return; + } + + rc_keydown(rcdev, proto, scancode, toggle != 0); + } +} + +int av7110_set_ir_config(struct av7110 *av7110) +{ + dprintk(4, "ir config = %08x\n", av7110->ir.ir_config); + + return av7110_fw_cmd(av7110, COMTYPE_PIDFILTER, SetIR, 1, + av7110->ir.ir_config); +} + +static int change_protocol(struct rc_dev *rcdev, u64 *rc_type) +{ + struct av7110 *av7110 = rcdev->priv; + u32 ir_config; + + if (*rc_type & RC_PROTO_BIT_RCMM32) { + ir_config = IR_RCMM; + *rc_type = RC_PROTO_BIT_RCMM32; + } else if (*rc_type & RC_PROTO_BIT_RC5) { + if (FW_VERSION(av7110->arm_app) >= 0x2620) + ir_config = IR_RC5_EXT; + else + ir_config = IR_RC5; + *rc_type = RC_PROTO_BIT_RC5; + } else { + return -EINVAL; + } + + if (ir_config == av7110->ir.ir_config) + return 0; + + av7110->ir.ir_config = ir_config; + + return av7110_set_ir_config(av7110); +} + +int av7110_ir_init(struct av7110 *av7110) +{ + struct rc_dev *rcdev; + struct pci_dev *pci; + int ret; + + rcdev = rc_allocate_device(RC_DRIVER_SCANCODE); + if (!rcdev) + return -ENOMEM; + + pci = av7110->dev->pci; + + snprintf(av7110->ir.input_phys, sizeof(av7110->ir.input_phys), + "pci-%s/ir0", pci_name(pci)); + + rcdev->device_name = av7110->card_name; + rcdev->driver_name = KBUILD_MODNAME; + rcdev->input_phys = av7110->ir.input_phys; + rcdev->input_id.bustype = BUS_PCI; + rcdev->input_id.version = 2; + if (pci->subsystem_vendor) { + rcdev->input_id.vendor = pci->subsystem_vendor; + rcdev->input_id.product = pci->subsystem_device; + } else { + rcdev->input_id.vendor = pci->vendor; + rcdev->input_id.product = pci->device; + } + + rcdev->dev.parent = &pci->dev; + rcdev->allowed_protocols = RC_PROTO_BIT_RC5 | RC_PROTO_BIT_RCMM32; + rcdev->change_protocol = change_protocol; + rcdev->map_name = RC_MAP_HAUPPAUGE; + rcdev->priv = av7110; + + av7110->ir.rcdev = rcdev; + av7110->ir.ir_config = IR_RC5; + av7110_set_ir_config(av7110); + + ret = rc_register_device(rcdev); + if (ret) { + av7110->ir.rcdev = NULL; + rc_free_device(rcdev); + } + + return ret; +} + +void av7110_ir_exit(struct av7110 *av7110) +{ + rc_unregister_device(av7110->ir.rcdev); +} + +//MODULE_AUTHOR("Holger Waechtler , Oliver Endriss "); +//MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/deprecated/saa7146/av7110/av7110_v4l.c b/drivers/staging/media/deprecated/saa7146/av7110/av7110_v4l.c new file mode 100644 index 000000000..c89f536f6 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/av7110_v4l.c @@ -0,0 +1,952 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * av7110_v4l.c: av7110 video4linux interface for DVB and Siemens DVB-C analog module + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * originally based on code by: + * Copyright (C) 1998,1999 Christian Theiss + * + * the project's page is at https://linuxtv.org + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include + +#include "av7110.h" +#include "av7110_hw.h" +#include "av7110_av.h" + +int msp_writereg(struct av7110 *av7110, u8 dev, u16 reg, u16 val) +{ + u8 msg[5] = { dev, reg >> 8, reg & 0xff, val >> 8 , val & 0xff }; + struct i2c_msg msgs = { .flags = 0, .len = 5, .buf = msg }; + + switch (av7110->adac_type) { + case DVB_ADAC_MSP34x0: + msgs.addr = 0x40; + break; + case DVB_ADAC_MSP34x5: + msgs.addr = 0x42; + break; + default: + return 0; + } + + if (i2c_transfer(&av7110->i2c_adap, &msgs, 1) != 1) { + dprintk(1, "dvb-ttpci: failed @ card %d, %u = %u\n", + av7110->dvb_adapter.num, reg, val); + return -EIO; + } + return 0; +} + +static int msp_readreg(struct av7110 *av7110, u8 dev, u16 reg, u16 *val) +{ + u8 msg1[3] = { dev, reg >> 8, reg & 0xff }; + u8 msg2[2]; + struct i2c_msg msgs[2] = { + { .flags = 0 , .len = 3, .buf = msg1 }, + { .flags = I2C_M_RD, .len = 2, .buf = msg2 } + }; + + switch (av7110->adac_type) { + case DVB_ADAC_MSP34x0: + msgs[0].addr = 0x40; + msgs[1].addr = 0x40; + break; + case DVB_ADAC_MSP34x5: + msgs[0].addr = 0x42; + msgs[1].addr = 0x42; + break; + default: + return 0; + } + + if (i2c_transfer(&av7110->i2c_adap, &msgs[0], 2) != 2) { + dprintk(1, "dvb-ttpci: failed @ card %d, %u\n", + av7110->dvb_adapter.num, reg); + return -EIO; + } + *val = (msg2[0] << 8) | msg2[1]; + return 0; +} + +static struct v4l2_input inputs[4] = { + { + .index = 0, + .name = "DVB", + .type = V4L2_INPUT_TYPE_CAMERA, + .audioset = 1, + .tuner = 0, /* ignored */ + .std = V4L2_STD_PAL_BG|V4L2_STD_NTSC_M, + .status = 0, + .capabilities = V4L2_IN_CAP_STD, + }, { + .index = 1, + .name = "Television", + .type = V4L2_INPUT_TYPE_TUNER, + .audioset = 1, + .tuner = 0, + .std = V4L2_STD_PAL_BG|V4L2_STD_NTSC_M, + .status = 0, + .capabilities = V4L2_IN_CAP_STD, + }, { + .index = 2, + .name = "Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .audioset = 0, + .tuner = 0, + .std = V4L2_STD_PAL_BG|V4L2_STD_NTSC_M, + .status = 0, + .capabilities = V4L2_IN_CAP_STD, + }, { + .index = 3, + .name = "Y/C", + .type = V4L2_INPUT_TYPE_CAMERA, + .audioset = 0, + .tuner = 0, + .std = V4L2_STD_PAL_BG|V4L2_STD_NTSC_M, + .status = 0, + .capabilities = V4L2_IN_CAP_STD, + } +}; + +static int ves1820_writereg(struct saa7146_dev *dev, u8 addr, u8 reg, u8 data) +{ + struct av7110 *av7110 = dev->ext_priv; + u8 buf[] = { 0x00, reg, data }; + struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 }; + + dprintk(4, "dev: %p\n", dev); + + if (1 != i2c_transfer(&av7110->i2c_adap, &msg, 1)) + return -1; + return 0; +} + +static int tuner_write(struct saa7146_dev *dev, u8 addr, u8 data [4]) +{ + struct av7110 *av7110 = dev->ext_priv; + struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = data, .len = 4 }; + + dprintk(4, "dev: %p\n", dev); + + if (1 != i2c_transfer(&av7110->i2c_adap, &msg, 1)) + return -1; + return 0; +} + +static int ves1820_set_tv_freq(struct saa7146_dev *dev, u32 freq) +{ + u32 div; + u8 config; + u8 buf[4]; + + dprintk(4, "freq: 0x%08x\n", freq); + + /* magic number: 614. tuning with the frequency given by v4l2 + is always off by 614*62.5 = 38375 kHz...*/ + div = freq + 614; + + buf[0] = (div >> 8) & 0x7f; + buf[1] = div & 0xff; + buf[2] = 0x8e; + + if (freq < 16U * 16825 / 100) + config = 0xa0; + else if (freq < 16U * 44725 / 100) + config = 0x90; + else + config = 0x30; + config &= ~0x02; + + buf[3] = config; + + return tuner_write(dev, 0x61, buf); +} + +static int stv0297_set_tv_freq(struct saa7146_dev *dev, u32 freq) +{ + struct av7110 *av7110 = (struct av7110*)dev->ext_priv; + u32 div; + u8 data[4]; + + div = (freq + 38900000 + 31250) / 62500; + + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0xce; + + if (freq < 45000000) + return -EINVAL; + else if (freq < 137000000) + data[3] = 0x01; + else if (freq < 403000000) + data[3] = 0x02; + else if (freq < 860000000) + data[3] = 0x04; + else + return -EINVAL; + + if (av7110->fe->ops.i2c_gate_ctrl) + av7110->fe->ops.i2c_gate_ctrl(av7110->fe, 1); + return tuner_write(dev, 0x63, data); +} + + + +static struct saa7146_standard analog_standard[]; +static struct saa7146_standard dvb_standard[]; +static struct saa7146_standard standard[]; + +static const struct v4l2_audio msp3400_v4l2_audio = { + .index = 0, + .name = "Television", + .capability = V4L2_AUDCAP_STEREO +}; + +static int av7110_dvb_c_switch(struct saa7146_fh *fh) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + struct av7110 *av7110 = (struct av7110*)dev->ext_priv; + u16 adswitch; + int source, sync, err; + + dprintk(4, "%p\n", av7110); + + if ((vv->video_status & STATUS_OVERLAY) != 0) { + vv->ov_suspend = vv->video_fh; + err = saa7146_stop_preview(vv->video_fh); /* side effect: video_status is now 0, video_fh is NULL */ + if (err != 0) { + dprintk(2, "suspending video failed\n"); + vv->ov_suspend = NULL; + } + } + + if (0 != av7110->current_input) { + dprintk(1, "switching to analog TV:\n"); + adswitch = 1; + source = SAA7146_HPS_SOURCE_PORT_B; + sync = SAA7146_HPS_SYNC_PORT_B; + memcpy(standard, analog_standard, sizeof(struct saa7146_standard) * 2); + + switch (av7110->current_input) { + case 1: + dprintk(1, "switching SAA7113 to Analog Tuner Input\n"); + msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0000); // loudspeaker source + msp_writereg(av7110, MSP_WR_DSP, 0x0009, 0x0000); // headphone source + msp_writereg(av7110, MSP_WR_DSP, 0x000a, 0x0000); // SCART 1 source + msp_writereg(av7110, MSP_WR_DSP, 0x000e, 0x3000); // FM matrix, mono + msp_writereg(av7110, MSP_WR_DSP, 0x0000, 0x4f00); // loudspeaker + headphone + msp_writereg(av7110, MSP_WR_DSP, 0x0007, 0x4f00); // SCART 1 volume + + if (av7110->analog_tuner_flags & ANALOG_TUNER_VES1820) { + if (ves1820_writereg(dev, 0x09, 0x0f, 0x60)) + dprintk(1, "setting band in demodulator failed\n"); + } else if (av7110->analog_tuner_flags & ANALOG_TUNER_STV0297) { + saa7146_setgpio(dev, 1, SAA7146_GPIO_OUTHI); // TDA9819 pin9(STD) + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI); // TDA9819 pin30(VIF) + } + if (i2c_writereg(av7110, 0x48, 0x02, 0xd0) != 1) + dprintk(1, "saa7113 write failed @ card %d", av7110->dvb_adapter.num); + break; + case 2: + dprintk(1, "switching SAA7113 to Video AV CVBS Input\n"); + if (i2c_writereg(av7110, 0x48, 0x02, 0xd2) != 1) + dprintk(1, "saa7113 write failed @ card %d", av7110->dvb_adapter.num); + break; + case 3: + dprintk(1, "switching SAA7113 to Video AV Y/C Input\n"); + if (i2c_writereg(av7110, 0x48, 0x02, 0xd9) != 1) + dprintk(1, "saa7113 write failed @ card %d", av7110->dvb_adapter.num); + break; + default: + dprintk(1, "switching SAA7113 to Input: AV7110: SAA7113: invalid input\n"); + } + } else { + adswitch = 0; + source = SAA7146_HPS_SOURCE_PORT_A; + sync = SAA7146_HPS_SYNC_PORT_A; + memcpy(standard, dvb_standard, sizeof(struct saa7146_standard) * 2); + dprintk(1, "switching DVB mode\n"); + msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0220); // loudspeaker source + msp_writereg(av7110, MSP_WR_DSP, 0x0009, 0x0220); // headphone source + msp_writereg(av7110, MSP_WR_DSP, 0x000a, 0x0220); // SCART 1 source + msp_writereg(av7110, MSP_WR_DSP, 0x000e, 0x3000); // FM matrix, mono + msp_writereg(av7110, MSP_WR_DSP, 0x0000, 0x7f00); // loudspeaker + headphone + msp_writereg(av7110, MSP_WR_DSP, 0x0007, 0x7f00); // SCART 1 volume + + if (av7110->analog_tuner_flags & ANALOG_TUNER_VES1820) { + if (ves1820_writereg(dev, 0x09, 0x0f, 0x20)) + dprintk(1, "setting band in demodulator failed\n"); + } else if (av7110->analog_tuner_flags & ANALOG_TUNER_STV0297) { + saa7146_setgpio(dev, 1, SAA7146_GPIO_OUTLO); // TDA9819 pin9(STD) + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); // TDA9819 pin30(VIF) + } + } + + /* hmm, this does not do anything!? */ + if (av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, ADSwitch, 1, adswitch)) + dprintk(1, "ADSwitch error\n"); + + saa7146_set_hps_source_and_sync(dev, source, sync); + + if (vv->ov_suspend != NULL) { + saa7146_start_preview(vv->ov_suspend); + vv->ov_suspend = NULL; + } + + return 0; +} + +static int vidioc_g_tuner(struct file *file, void *fh, struct v4l2_tuner *t) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + u16 stereo_det; + s8 stereo; + + dprintk(2, "VIDIOC_G_TUNER: %d\n", t->index); + + if (!av7110->analog_tuner_flags || t->index != 0) + return -EINVAL; + + memset(t, 0, sizeof(*t)); + strscpy((char *)t->name, "Television", sizeof(t->name)); + + t->type = V4L2_TUNER_ANALOG_TV; + t->capability = V4L2_TUNER_CAP_NORM | V4L2_TUNER_CAP_STEREO | + V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP; + t->rangelow = 772; /* 48.25 MHZ / 62.5 kHz = 772, see fi1216mk2-specs, page 2 */ + t->rangehigh = 13684; /* 855.25 MHz / 62.5 kHz = 13684 */ + /* FIXME: add the real signal strength here */ + t->signal = 0xffff; + t->afc = 0; + + /* FIXME: standard / stereo detection is still broken */ + msp_readreg(av7110, MSP_RD_DEM, 0x007e, &stereo_det); + dprintk(1, "VIDIOC_G_TUNER: msp3400 TV standard detection: 0x%04x\n", stereo_det); + msp_readreg(av7110, MSP_RD_DSP, 0x0018, &stereo_det); + dprintk(1, "VIDIOC_G_TUNER: msp3400 stereo detection: 0x%04x\n", stereo_det); + stereo = (s8)(stereo_det >> 8); + if (stereo > 0x10) { + /* stereo */ + t->rxsubchans = V4L2_TUNER_SUB_STEREO | V4L2_TUNER_SUB_MONO; + t->audmode = V4L2_TUNER_MODE_STEREO; + } else if (stereo < -0x10) { + /* bilingual */ + t->rxsubchans = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; + t->audmode = V4L2_TUNER_MODE_LANG1; + } else /* mono */ + t->rxsubchans = V4L2_TUNER_SUB_MONO; + + return 0; +} + +static int vidioc_s_tuner(struct file *file, void *fh, const struct v4l2_tuner *t) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + u16 fm_matrix, src; + dprintk(2, "VIDIOC_S_TUNER: %d\n", t->index); + + if (!av7110->analog_tuner_flags || av7110->current_input != 1) + return -EINVAL; + + switch (t->audmode) { + case V4L2_TUNER_MODE_STEREO: + dprintk(2, "VIDIOC_S_TUNER: V4L2_TUNER_MODE_STEREO\n"); + fm_matrix = 0x3001; /* stereo */ + src = 0x0020; + break; + case V4L2_TUNER_MODE_LANG1_LANG2: + dprintk(2, "VIDIOC_S_TUNER: V4L2_TUNER_MODE_LANG1_LANG2\n"); + fm_matrix = 0x3000; /* bilingual */ + src = 0x0020; + break; + case V4L2_TUNER_MODE_LANG1: + dprintk(2, "VIDIOC_S_TUNER: V4L2_TUNER_MODE_LANG1\n"); + fm_matrix = 0x3000; /* mono */ + src = 0x0000; + break; + case V4L2_TUNER_MODE_LANG2: + dprintk(2, "VIDIOC_S_TUNER: V4L2_TUNER_MODE_LANG2\n"); + fm_matrix = 0x3000; /* mono */ + src = 0x0010; + break; + default: /* case V4L2_TUNER_MODE_MONO: */ + dprintk(2, "VIDIOC_S_TUNER: TDA9840_SET_MONO\n"); + fm_matrix = 0x3000; /* mono */ + src = 0x0030; + break; + } + msp_writereg(av7110, MSP_WR_DSP, 0x000e, fm_matrix); + msp_writereg(av7110, MSP_WR_DSP, 0x0008, src); + msp_writereg(av7110, MSP_WR_DSP, 0x0009, src); + msp_writereg(av7110, MSP_WR_DSP, 0x000a, src); + return 0; +} + +static int vidioc_g_frequency(struct file *file, void *fh, struct v4l2_frequency *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_G_FREQ: freq:0x%08x\n", f->frequency); + + if (!av7110->analog_tuner_flags || av7110->current_input != 1) + return -EINVAL; + + memset(f, 0, sizeof(*f)); + f->type = V4L2_TUNER_ANALOG_TV; + f->frequency = av7110->current_freq; + return 0; +} + +static int vidioc_s_frequency(struct file *file, void *fh, const struct v4l2_frequency *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_S_FREQUENCY: freq:0x%08x\n", f->frequency); + + if (!av7110->analog_tuner_flags || av7110->current_input != 1) + return -EINVAL; + + if (V4L2_TUNER_ANALOG_TV != f->type) + return -EINVAL; + + msp_writereg(av7110, MSP_WR_DSP, 0x0000, 0xffe0); /* fast mute */ + msp_writereg(av7110, MSP_WR_DSP, 0x0007, 0xffe0); + + /* tune in desired frequency */ + if (av7110->analog_tuner_flags & ANALOG_TUNER_VES1820) + ves1820_set_tv_freq(dev, f->frequency); + else if (av7110->analog_tuner_flags & ANALOG_TUNER_STV0297) + stv0297_set_tv_freq(dev, f->frequency); + av7110->current_freq = f->frequency; + + msp_writereg(av7110, MSP_WR_DSP, 0x0015, 0x003f); /* start stereo detection */ + msp_writereg(av7110, MSP_WR_DSP, 0x0015, 0x0000); + msp_writereg(av7110, MSP_WR_DSP, 0x0000, 0x4f00); /* loudspeaker + headphone */ + msp_writereg(av7110, MSP_WR_DSP, 0x0007, 0x4f00); /* SCART 1 volume */ + return 0; +} + +static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_ENUMINPUT: %d\n", i->index); + + if (av7110->analog_tuner_flags) { + if (i->index >= 4) + return -EINVAL; + } else { + if (i->index != 0) + return -EINVAL; + } + + memcpy(i, &inputs[i->index], sizeof(struct v4l2_input)); + + return 0; +} + +static int vidioc_g_input(struct file *file, void *fh, unsigned int *input) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + *input = av7110->current_input; + dprintk(2, "VIDIOC_G_INPUT: %d\n", *input); + return 0; +} + +static int vidioc_s_input(struct file *file, void *fh, unsigned int input) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_S_INPUT: %d\n", input); + + if (!av7110->analog_tuner_flags) + return input ? -EINVAL : 0; + + if (input >= 4) + return -EINVAL; + + av7110->current_input = input; + return av7110_dvb_c_switch(fh); +} + +static int vidioc_enumaudio(struct file *file, void *fh, struct v4l2_audio *a) +{ + dprintk(2, "VIDIOC_G_AUDIO: %d\n", a->index); + if (a->index != 0) + return -EINVAL; + *a = msp3400_v4l2_audio; + return 0; +} + +static int vidioc_g_audio(struct file *file, void *fh, struct v4l2_audio *a) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_G_AUDIO: %d\n", a->index); + if (a->index != 0) + return -EINVAL; + if (av7110->current_input >= 2) + return -EINVAL; + *a = msp3400_v4l2_audio; + return 0; +} + +static int vidioc_s_audio(struct file *file, void *fh, const struct v4l2_audio *a) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_S_AUDIO: %d\n", a->index); + if (av7110->current_input >= 2) + return -EINVAL; + return a->index ? -EINVAL : 0; +} + +static int vidioc_g_sliced_vbi_cap(struct file *file, void *fh, + struct v4l2_sliced_vbi_cap *cap) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_G_SLICED_VBI_CAP\n"); + if (cap->type != V4L2_BUF_TYPE_SLICED_VBI_OUTPUT) + return -EINVAL; + if (FW_VERSION(av7110->arm_app) >= 0x2623) { + cap->service_set = V4L2_SLICED_WSS_625; + cap->service_lines[0][23] = V4L2_SLICED_WSS_625; + } + return 0; +} + +static int vidioc_g_fmt_sliced_vbi_out(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_G_FMT:\n"); + if (FW_VERSION(av7110->arm_app) < 0x2623) + return -EINVAL; + memset(&f->fmt.sliced, 0, sizeof f->fmt.sliced); + if (av7110->wssMode) { + f->fmt.sliced.service_set = V4L2_SLICED_WSS_625; + f->fmt.sliced.service_lines[0][23] = V4L2_SLICED_WSS_625; + f->fmt.sliced.io_size = sizeof(struct v4l2_sliced_vbi_data); + } + return 0; +} + +static int vidioc_s_fmt_sliced_vbi_out(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct av7110 *av7110 = (struct av7110 *)dev->ext_priv; + + dprintk(2, "VIDIOC_S_FMT\n"); + if (FW_VERSION(av7110->arm_app) < 0x2623) + return -EINVAL; + if (f->fmt.sliced.service_set != V4L2_SLICED_WSS_625 && + f->fmt.sliced.service_lines[0][23] != V4L2_SLICED_WSS_625) { + memset(&f->fmt.sliced, 0, sizeof(f->fmt.sliced)); + /* WSS controlled by firmware */ + av7110->wssMode = 0; + av7110->wssData = 0; + return av7110_fw_cmd(av7110, COMTYPE_ENCODER, + SetWSSConfig, 1, 0); + } else { + memset(&f->fmt.sliced, 0, sizeof(f->fmt.sliced)); + f->fmt.sliced.service_set = V4L2_SLICED_WSS_625; + f->fmt.sliced.service_lines[0][23] = V4L2_SLICED_WSS_625; + f->fmt.sliced.io_size = sizeof(struct v4l2_sliced_vbi_data); + /* WSS controlled by userspace */ + av7110->wssMode = 1; + av7110->wssData = 0; + } + return 0; +} + +static int av7110_vbi_reset(struct file *file) +{ + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct av7110 *av7110 = (struct av7110*) dev->ext_priv; + + dprintk(2, "%s\n", __func__); + av7110->wssMode = 0; + av7110->wssData = 0; + if (FW_VERSION(av7110->arm_app) < 0x2623) + return 0; + else + return av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetWSSConfig, 1, 0); +} + +static ssize_t av7110_vbi_write(struct file *file, const char __user *data, size_t count, loff_t *ppos) +{ + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct av7110 *av7110 = (struct av7110*) dev->ext_priv; + struct v4l2_sliced_vbi_data d; + int rc; + + dprintk(2, "%s\n", __func__); + if (FW_VERSION(av7110->arm_app) < 0x2623 || !av7110->wssMode || count != sizeof d) + return -EINVAL; + if (copy_from_user(&d, data, count)) + return -EFAULT; + if ((d.id != 0 && d.id != V4L2_SLICED_WSS_625) || d.field != 0 || d.line != 23) + return -EINVAL; + if (d.id) + av7110->wssData = ((d.data[1] << 8) & 0x3f00) | d.data[0]; + else + av7110->wssData = 0x8000; + rc = av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetWSSConfig, 2, 1, av7110->wssData); + return (rc < 0) ? rc : count; +} + +/**************************************************************************** + * INITIALIZATION + ****************************************************************************/ + +static u8 saa7113_init_regs[] = { + 0x02, 0xd0, + 0x03, 0x23, + 0x04, 0x00, + 0x05, 0x00, + 0x06, 0xe9, + 0x07, 0x0d, + 0x08, 0x98, + 0x09, 0x02, + 0x0a, 0x80, + 0x0b, 0x40, + 0x0c, 0x40, + 0x0d, 0x00, + 0x0e, 0x01, + 0x0f, 0x7c, + 0x10, 0x48, + 0x11, 0x0c, + 0x12, 0x8b, + 0x13, 0x1a, + 0x14, 0x00, + 0x15, 0x00, + 0x16, 0x00, + 0x17, 0x00, + 0x18, 0x00, + 0x19, 0x00, + 0x1a, 0x00, + 0x1b, 0x00, + 0x1c, 0x00, + 0x1d, 0x00, + 0x1e, 0x00, + + 0x41, 0x77, + 0x42, 0x77, + 0x43, 0x77, + 0x44, 0x77, + 0x45, 0x77, + 0x46, 0x77, + 0x47, 0x77, + 0x48, 0x77, + 0x49, 0x77, + 0x4a, 0x77, + 0x4b, 0x77, + 0x4c, 0x77, + 0x4d, 0x77, + 0x4e, 0x77, + 0x4f, 0x77, + 0x50, 0x77, + 0x51, 0x77, + 0x52, 0x77, + 0x53, 0x77, + 0x54, 0x77, + 0x55, 0x77, + 0x56, 0x77, + 0x57, 0xff, + + 0xff +}; + + +static struct saa7146_ext_vv av7110_vv_data_st; +static struct saa7146_ext_vv av7110_vv_data_c; + +int av7110_init_analog_module(struct av7110 *av7110) +{ + u16 version1, version2; + + if (i2c_writereg(av7110, 0x80, 0x0, 0x80) == 1 && + i2c_writereg(av7110, 0x80, 0x0, 0) == 1) { + pr_info("DVB-C analog module @ card %d detected, initializing MSP3400\n", + av7110->dvb_adapter.num); + av7110->adac_type = DVB_ADAC_MSP34x0; + } else if (i2c_writereg(av7110, 0x84, 0x0, 0x80) == 1 && + i2c_writereg(av7110, 0x84, 0x0, 0) == 1) { + pr_info("DVB-C analog module @ card %d detected, initializing MSP3415\n", + av7110->dvb_adapter.num); + av7110->adac_type = DVB_ADAC_MSP34x5; + } else + return -ENODEV; + + msleep(100); // the probing above resets the msp... + msp_readreg(av7110, MSP_RD_DSP, 0x001e, &version1); + msp_readreg(av7110, MSP_RD_DSP, 0x001f, &version2); + dprintk(1, "dvb-ttpci: @ card %d MSP34xx version 0x%04x 0x%04x\n", + av7110->dvb_adapter.num, version1, version2); + msp_writereg(av7110, MSP_WR_DSP, 0x0013, 0x0c00); + msp_writereg(av7110, MSP_WR_DSP, 0x0000, 0x7f00); // loudspeaker + headphone + msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0220); // loudspeaker source + msp_writereg(av7110, MSP_WR_DSP, 0x0009, 0x0220); // headphone source + msp_writereg(av7110, MSP_WR_DSP, 0x0004, 0x7f00); // loudspeaker volume + msp_writereg(av7110, MSP_WR_DSP, 0x000a, 0x0220); // SCART 1 source + msp_writereg(av7110, MSP_WR_DSP, 0x0007, 0x7f00); // SCART 1 volume + msp_writereg(av7110, MSP_WR_DSP, 0x000d, 0x1900); // prescale SCART + + if (i2c_writereg(av7110, 0x48, 0x01, 0x00)!=1) { + pr_info("saa7113 not accessible\n"); + } else { + u8 *i = saa7113_init_regs; + + if ((av7110->dev->pci->subsystem_vendor == 0x110a) && (av7110->dev->pci->subsystem_device == 0x0000)) { + /* Fujitsu/Siemens DVB-Cable */ + av7110->analog_tuner_flags |= ANALOG_TUNER_VES1820; + } else if ((av7110->dev->pci->subsystem_vendor == 0x13c2) && (av7110->dev->pci->subsystem_device == 0x0002)) { + /* Hauppauge/TT DVB-C premium */ + av7110->analog_tuner_flags |= ANALOG_TUNER_VES1820; + } else if ((av7110->dev->pci->subsystem_vendor == 0x13c2) && (av7110->dev->pci->subsystem_device == 0x000A)) { + /* Hauppauge/TT DVB-C premium */ + av7110->analog_tuner_flags |= ANALOG_TUNER_STV0297; + } + + /* setup for DVB by default */ + if (av7110->analog_tuner_flags & ANALOG_TUNER_VES1820) { + if (ves1820_writereg(av7110->dev, 0x09, 0x0f, 0x20)) + dprintk(1, "setting band in demodulator failed\n"); + } else if (av7110->analog_tuner_flags & ANALOG_TUNER_STV0297) { + saa7146_setgpio(av7110->dev, 1, SAA7146_GPIO_OUTLO); // TDA9819 pin9(STD) + saa7146_setgpio(av7110->dev, 3, SAA7146_GPIO_OUTLO); // TDA9819 pin30(VIF) + } + + /* init the saa7113 */ + while (*i != 0xff) { + if (i2c_writereg(av7110, 0x48, i[0], i[1]) != 1) { + dprintk(1, "saa7113 initialization failed @ card %d", av7110->dvb_adapter.num); + break; + } + i += 2; + } + /* setup msp for analog sound: B/G Dual-FM */ + msp_writereg(av7110, MSP_WR_DEM, 0x00bb, 0x02d0); // AD_CV + msp_writereg(av7110, MSP_WR_DEM, 0x0001, 3); // FIR1 + msp_writereg(av7110, MSP_WR_DEM, 0x0001, 18); // FIR1 + msp_writereg(av7110, MSP_WR_DEM, 0x0001, 27); // FIR1 + msp_writereg(av7110, MSP_WR_DEM, 0x0001, 48); // FIR1 + msp_writereg(av7110, MSP_WR_DEM, 0x0001, 66); // FIR1 + msp_writereg(av7110, MSP_WR_DEM, 0x0001, 72); // FIR1 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 4); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 64); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 0); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 3); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 18); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 27); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 48); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 66); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0005, 72); // FIR2 + msp_writereg(av7110, MSP_WR_DEM, 0x0083, 0xa000); // MODE_REG + msp_writereg(av7110, MSP_WR_DEM, 0x0093, 0x00aa); // DCO1_LO 5.74MHz + msp_writereg(av7110, MSP_WR_DEM, 0x009b, 0x04fc); // DCO1_HI + msp_writereg(av7110, MSP_WR_DEM, 0x00a3, 0x038e); // DCO2_LO 5.5MHz + msp_writereg(av7110, MSP_WR_DEM, 0x00ab, 0x04c6); // DCO2_HI + msp_writereg(av7110, MSP_WR_DEM, 0x0056, 0); // LOAD_REG 1/2 + } + + memcpy(standard, dvb_standard, sizeof(struct saa7146_standard) * 2); + /* set dd1 stream a & b */ + saa7146_write(av7110->dev, DD1_STREAM_B, 0x00000000); + saa7146_write(av7110->dev, DD1_INIT, 0x03000700); + saa7146_write(av7110->dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + + return 0; +} + +int av7110_init_v4l(struct av7110 *av7110) +{ + struct saa7146_dev* dev = av7110->dev; + struct saa7146_ext_vv *vv_data; + int ret; + + /* special case DVB-C: these cards have an analog tuner + plus need some special handling, so we have separate + saa7146_ext_vv data for these... */ + if (av7110->analog_tuner_flags) + vv_data = &av7110_vv_data_c; + else + vv_data = &av7110_vv_data_st; + ret = saa7146_vv_init(dev, vv_data); + + if (ret) { + ERR("cannot init capture device. skipping\n"); + return -ENODEV; + } + vv_data->vid_ops.vidioc_enum_input = vidioc_enum_input; + vv_data->vid_ops.vidioc_g_input = vidioc_g_input; + vv_data->vid_ops.vidioc_s_input = vidioc_s_input; + vv_data->vid_ops.vidioc_g_tuner = vidioc_g_tuner; + vv_data->vid_ops.vidioc_s_tuner = vidioc_s_tuner; + vv_data->vid_ops.vidioc_g_frequency = vidioc_g_frequency; + vv_data->vid_ops.vidioc_s_frequency = vidioc_s_frequency; + vv_data->vid_ops.vidioc_enumaudio = vidioc_enumaudio; + vv_data->vid_ops.vidioc_g_audio = vidioc_g_audio; + vv_data->vid_ops.vidioc_s_audio = vidioc_s_audio; + vv_data->vid_ops.vidioc_g_fmt_vbi_cap = NULL; + + vv_data->vbi_ops.vidioc_g_tuner = vidioc_g_tuner; + vv_data->vbi_ops.vidioc_s_tuner = vidioc_s_tuner; + vv_data->vbi_ops.vidioc_g_frequency = vidioc_g_frequency; + vv_data->vbi_ops.vidioc_s_frequency = vidioc_s_frequency; + vv_data->vbi_ops.vidioc_g_fmt_vbi_cap = NULL; + vv_data->vbi_ops.vidioc_g_sliced_vbi_cap = vidioc_g_sliced_vbi_cap; + vv_data->vbi_ops.vidioc_g_fmt_sliced_vbi_out = vidioc_g_fmt_sliced_vbi_out; + vv_data->vbi_ops.vidioc_s_fmt_sliced_vbi_out = vidioc_s_fmt_sliced_vbi_out; + + if (FW_VERSION(av7110->arm_app) < 0x2623) + vv_data->capabilities &= ~V4L2_CAP_SLICED_VBI_OUTPUT; + + if (saa7146_register_device(&av7110->v4l_dev, dev, "av7110", VFL_TYPE_VIDEO)) { + ERR("cannot register capture device. skipping\n"); + saa7146_vv_release(dev); + return -ENODEV; + } + if (FW_VERSION(av7110->arm_app) >= 0x2623) { + if (saa7146_register_device(&av7110->vbi_dev, dev, "av7110", VFL_TYPE_VBI)) + ERR("cannot register vbi v4l2 device. skipping\n"); + } + return 0; +} + +int av7110_exit_v4l(struct av7110 *av7110) +{ + struct saa7146_dev* dev = av7110->dev; + + saa7146_unregister_device(&av7110->v4l_dev, av7110->dev); + saa7146_unregister_device(&av7110->vbi_dev, av7110->dev); + + saa7146_vv_release(dev); + + return 0; +} + + + +/* FIXME: these values are experimental values that look better than the + values from the latest "official" driver -- at least for me... (MiHu) */ +static struct saa7146_standard standard[] = { + { + .name = "PAL", .id = V4L2_STD_PAL_BG, + .v_offset = 0x15, .v_field = 288, + .h_offset = 0x48, .h_pixels = 708, + .v_max_out = 576, .h_max_out = 768, + }, { + .name = "NTSC", .id = V4L2_STD_NTSC, + .v_offset = 0x10, .v_field = 244, + .h_offset = 0x40, .h_pixels = 708, + .v_max_out = 480, .h_max_out = 640, + } +}; + +static struct saa7146_standard analog_standard[] = { + { + .name = "PAL", .id = V4L2_STD_PAL_BG, + .v_offset = 0x1b, .v_field = 288, + .h_offset = 0x08, .h_pixels = 708, + .v_max_out = 576, .h_max_out = 768, + }, { + .name = "NTSC", .id = V4L2_STD_NTSC, + .v_offset = 0x10, .v_field = 244, + .h_offset = 0x40, .h_pixels = 708, + .v_max_out = 480, .h_max_out = 640, + } +}; + +static struct saa7146_standard dvb_standard[] = { + { + .name = "PAL", .id = V4L2_STD_PAL_BG, + .v_offset = 0x14, .v_field = 288, + .h_offset = 0x48, .h_pixels = 708, + .v_max_out = 576, .h_max_out = 768, + }, { + .name = "NTSC", .id = V4L2_STD_NTSC, + .v_offset = 0x10, .v_field = 244, + .h_offset = 0x40, .h_pixels = 708, + .v_max_out = 480, .h_max_out = 640, + } +}; + +static int std_callback(struct saa7146_dev* dev, struct saa7146_standard *std) +{ + struct av7110 *av7110 = (struct av7110*) dev->ext_priv; + + if (std->id & V4L2_STD_PAL) { + av7110->vidmode = AV7110_VIDEO_MODE_PAL; + av7110_set_vidmode(av7110, av7110->vidmode); + } + else if (std->id & V4L2_STD_NTSC) { + av7110->vidmode = AV7110_VIDEO_MODE_NTSC; + av7110_set_vidmode(av7110, av7110->vidmode); + } + else + return -1; + + return 0; +} + + +static struct saa7146_ext_vv av7110_vv_data_st = { + .inputs = 1, + .audios = 1, + .capabilities = V4L2_CAP_SLICED_VBI_OUTPUT | V4L2_CAP_AUDIO, + .flags = 0, + + .stds = &standard[0], + .num_stds = ARRAY_SIZE(standard), + .std_callback = &std_callback, + + .vbi_fops.open = av7110_vbi_reset, + .vbi_fops.release = av7110_vbi_reset, + .vbi_fops.write = av7110_vbi_write, +}; + +static struct saa7146_ext_vv av7110_vv_data_c = { + .inputs = 1, + .audios = 1, + .capabilities = V4L2_CAP_TUNER | V4L2_CAP_SLICED_VBI_OUTPUT | V4L2_CAP_AUDIO, + .flags = SAA7146_USE_PORT_B_FOR_VBI, + + .stds = &standard[0], + .num_stds = ARRAY_SIZE(standard), + .std_callback = &std_callback, + + .vbi_fops.open = av7110_vbi_reset, + .vbi_fops.release = av7110_vbi_reset, + .vbi_fops.write = av7110_vbi_write, +}; + diff --git a/drivers/staging/media/deprecated/saa7146/av7110/budget-patch.c b/drivers/staging/media/deprecated/saa7146/av7110/budget-patch.c new file mode 100644 index 000000000..d173c8ade --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/budget-patch.c @@ -0,0 +1,665 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * budget-patch.c: driver for Budget Patch, + * hardware modification of DVB-S cards enabling full TS + * + * Written by Emard + * + * Original idea by Roberto Deza + * + * Special thanks to Holger Waechtler, Michael Hunold, Marian Durkovic + * and Metzlerbros + * + * the project's page is at https://linuxtv.org + */ + +#include "av7110.h" +#include "av7110_hw.h" +#include "budget.h" +#include "stv0299.h" +#include "ves1x93.h" +#include "tda8083.h" + +#include "bsru6.h" + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +#define budget_patch budget + +static struct saa7146_extension budget_extension; + +MAKE_BUDGET_INFO(ttbp, "TT-Budget/Patch DVB-S 1.x PCI", BUDGET_PATCH); +//MAKE_BUDGET_INFO(satel,"TT-Budget/Patch SATELCO PCI", BUDGET_TT_HW_DISEQC); + +static const struct pci_device_id pci_tbl[] = { + MAKE_EXTENSION_PCI(ttbp,0x13c2, 0x0000), +// MAKE_EXTENSION_PCI(satel, 0x13c2, 0x1013), + { + .vendor = 0, + } +}; + +/* those lines are for budget-patch to be tried +** on a true budget card and observe the +** behaviour of VSYNC generated by rps1. +** this code was shamelessly copy/pasted from budget.c +*/ +static void gpio_Set22K (struct budget *budget, int state) +{ + struct saa7146_dev *dev=budget->dev; + dprintk(2, "budget: %p\n", budget); + saa7146_setgpio(dev, 3, (state ? SAA7146_GPIO_OUTHI : SAA7146_GPIO_OUTLO)); +} + +/* Diseqc functions only for TT Budget card */ +/* taken from the Skyvision DVB driver by + Ralph Metzler */ + +static void DiseqcSendBit (struct budget *budget, int data) +{ + struct saa7146_dev *dev=budget->dev; + dprintk(2, "budget: %p\n", budget); + + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI); + udelay(data ? 500 : 1000); + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); + udelay(data ? 1000 : 500); +} + +static void DiseqcSendByte (struct budget *budget, int data) +{ + int i, par=1, d; + + dprintk(2, "budget: %p\n", budget); + + for (i=7; i>=0; i--) { + d = (data>>i)&1; + par ^= d; + DiseqcSendBit(budget, d); + } + + DiseqcSendBit(budget, par); +} + +static int SendDiSEqCMsg (struct budget *budget, int len, u8 *msg, unsigned long burst) +{ + struct saa7146_dev *dev=budget->dev; + int i; + + dprintk(2, "budget: %p\n", budget); + + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); + mdelay(16); + + for (i=0; idvb->priv; + + switch (tone) { + case SEC_TONE_ON: + gpio_Set22K (budget, 1); + break; + + case SEC_TONE_OFF: + gpio_Set22K (budget, 0); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int budget_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd) +{ + struct budget* budget = (struct budget*) fe->dvb->priv; + + SendDiSEqCMsg (budget, cmd->msg_len, cmd->msg, 0); + + return 0; +} + +static int budget_diseqc_send_burst(struct dvb_frontend *fe, + enum fe_sec_mini_cmd minicmd) +{ + struct budget* budget = (struct budget*) fe->dvb->priv; + + SendDiSEqCMsg (budget, 0, NULL, minicmd); + + return 0; +} + +static int budget_av7110_send_fw_cmd(struct budget_patch *budget, u16* buf, int length) +{ + int i; + + dprintk(2, "budget: %p\n", budget); + + for (i = 2; i < length; i++) + { + ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2*i, 2, (u32) buf[i], 0,0); + msleep(5); + } + if (length) + ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2, 2, (u32) buf[1], 0,0); + else + ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2, 2, 0, 0,0); + msleep(5); + ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND, 2, (u32) buf[0], 0,0); + msleep(5); + return 0; +} + +static void av7110_set22k(struct budget_patch *budget, int state) +{ + u16 buf[2] = {( COMTYPE_AUDIODAC << 8) | (state ? ON22K : OFF22K), 0}; + + dprintk(2, "budget: %p\n", budget); + budget_av7110_send_fw_cmd(budget, buf, 2); +} + +static int av7110_send_diseqc_msg(struct budget_patch *budget, int len, u8 *msg, int burst) +{ + int i; + u16 buf[18] = { ((COMTYPE_AUDIODAC << 8) | SendDiSEqC), + 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + + dprintk(2, "budget: %p\n", budget); + + if (len>10) + len=10; + + buf[1] = len+2; + buf[2] = len; + + if (burst != -1) + buf[3]=burst ? 0x01 : 0x00; + else + buf[3]=0xffff; + + for (i=0; idvb->priv; + + switch (tone) { + case SEC_TONE_ON: + av7110_set22k (budget, 1); + break; + + case SEC_TONE_OFF: + av7110_set22k (budget, 0); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int budget_patch_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd) +{ + struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv; + + av7110_send_diseqc_msg (budget, cmd->msg_len, cmd->msg, 0); + + return 0; +} + +static int budget_patch_diseqc_send_burst(struct dvb_frontend *fe, + enum fe_sec_mini_cmd minicmd) +{ + struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv; + + av7110_send_diseqc_msg (budget, 0, NULL, minicmd); + + return 0; +} + +static int alps_bsrv2_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv; + u8 pwr = 0; + u8 buf[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) }; + u32 div = (p->frequency + 479500) / 125; + + if (p->frequency > 2000000) + pwr = 3; + else if (p->frequency > 1800000) + pwr = 2; + else if (p->frequency > 1600000) + pwr = 1; + else if (p->frequency > 1200000) + pwr = 0; + else if (p->frequency >= 1100000) + pwr = 1; + else pwr = 2; + + buf[0] = (div >> 8) & 0x7f; + buf[1] = div & 0xff; + buf[2] = ((div & 0x18000) >> 10) | 0x95; + buf[3] = (pwr << 6) | 0x30; + + // NOTE: since we're using a prescaler of 2, we set the + // divisor frequency to 62.5kHz and divide by 125 above + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static struct ves1x93_config alps_bsrv2_config = { + .demod_address = 0x08, + .xin = 90100000UL, + .invert_pwm = 0, +}; + +static int grundig_29504_451_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv; + u32 div; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = p->frequency / 125; + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0x8e; + data[3] = 0x00; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static struct tda8083_config grundig_29504_451_config = { + .demod_address = 0x68, +}; + +static void frontend_init(struct budget_patch* budget) +{ + switch(budget->dev->pci->subsystem_device) { + case 0x0000: // Hauppauge/TT WinTV DVB-S rev1.X + case 0x1013: // SATELCO Multimedia PCI + + // try the ALPS BSRV2 first of all + budget->dvb_frontend = dvb_attach(ves1x93_attach, &alps_bsrv2_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsrv2_tuner_set_params; + budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_patch_diseqc_send_master_cmd; + budget->dvb_frontend->ops.diseqc_send_burst = budget_patch_diseqc_send_burst; + budget->dvb_frontend->ops.set_tone = budget_patch_set_tone; + break; + } + + // try the ALPS BSRU6 now + budget->dvb_frontend = dvb_attach(stv0299_attach, &alps_bsru6_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params; + budget->dvb_frontend->tuner_priv = &budget->i2c_adap; + + budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd; + budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst; + budget->dvb_frontend->ops.set_tone = budget_set_tone; + break; + } + + // Try the grundig 29504-451 + budget->dvb_frontend = dvb_attach(tda8083_attach, &grundig_29504_451_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = grundig_29504_451_tuner_set_params; + budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd; + budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst; + budget->dvb_frontend->ops.set_tone = budget_set_tone; + break; + } + break; + } + + if (budget->dvb_frontend == NULL) { + printk("dvb-ttpci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n", + budget->dev->pci->vendor, + budget->dev->pci->device, + budget->dev->pci->subsystem_vendor, + budget->dev->pci->subsystem_device); + } else { + if (dvb_register_frontend(&budget->dvb_adapter, budget->dvb_frontend)) { + printk("budget-av: Frontend registration failed!\n"); + dvb_frontend_detach(budget->dvb_frontend); + budget->dvb_frontend = NULL; + } + } +} + +/* written by Emard */ +static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_extension_data *info) +{ + struct budget_patch *budget; + int err; + int count = 0; + int detected = 0; + +#define PATCH_RESET 0 +#define RPS_IRQ 0 +#define HPS_SETUP 0 +#if PATCH_RESET + saa7146_write(dev, MC1, MASK_31); + msleep(40); +#endif +#if HPS_SETUP + // initialize registers. Better to have it like this + // than leaving something unconfigured + saa7146_write(dev, DD1_STREAM_B, 0); + // port B VSYNC at rising edge + saa7146_write(dev, DD1_INIT, 0x00000200); // have this in budget-core too! + saa7146_write(dev, BRS_CTRL, 0x00000000); // VBI + + // debi config + // saa7146_write(dev, DEBI_CONFIG, MASK_30|MASK_28|MASK_18); + + // zero all HPS registers + saa7146_write(dev, HPS_H_PRESCALE, 0); // r68 + saa7146_write(dev, HPS_H_SCALE, 0); // r6c + saa7146_write(dev, BCS_CTRL, 0); // r70 + saa7146_write(dev, HPS_V_SCALE, 0); // r60 + saa7146_write(dev, HPS_V_GAIN, 0); // r64 + saa7146_write(dev, CHROMA_KEY_RANGE, 0); // r74 + saa7146_write(dev, CLIP_FORMAT_CTRL, 0); // r78 + // Set HPS prescaler for port B input + saa7146_write(dev, HPS_CTRL, (1<<30) | (0<<29) | (1<<28) | (0<<12) ); + saa7146_write(dev, MC2, + 0 * (MASK_08 | MASK_24) | // BRS control + 0 * (MASK_09 | MASK_25) | // a + 0 * (MASK_10 | MASK_26) | // b + 1 * (MASK_06 | MASK_22) | // HPS_CTRL1 + 1 * (MASK_05 | MASK_21) | // HPS_CTRL2 + 0 * (MASK_01 | MASK_15) // DEBI + ); +#endif + // Disable RPS1 and RPS0 + saa7146_write(dev, MC1, ( MASK_29 | MASK_28)); + // RPS1 timeout disable + saa7146_write(dev, RPS_TOV1, 0); + + // code for autodetection + // will wait for VBI_B event (vertical blank at port B) + // and will reset GPIO3 after VBI_B is detected. + // (GPIO3 should be raised high by CPU to + // test if GPIO3 will generate vertical blank signal + // in budget patch GPIO3 is connected to VSYNC_B + count = 0; +#if 0 + WRITE_RPS1(CMD_UPLOAD | + MASK_10 | MASK_09 | MASK_08 | MASK_06 | MASK_05 | MASK_04 | MASK_03 | MASK_02 ); +#endif + WRITE_RPS1(CMD_PAUSE | EVT_VBI_B); + WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2)); + WRITE_RPS1(GPIO3_MSK); + WRITE_RPS1(SAA7146_GPIO_OUTLO<<24); +#if RPS_IRQ + // issue RPS1 interrupt to increment counter + WRITE_RPS1(CMD_INTERRUPT); + // at least a NOP is neede between two interrupts + WRITE_RPS1(CMD_NOP); + // interrupt again + WRITE_RPS1(CMD_INTERRUPT); +#endif + WRITE_RPS1(CMD_STOP); + +#if RPS_IRQ + // set event counter 1 source as RPS1 interrupt (0x03) (rE4 p53) + // use 0x03 to track RPS1 interrupts - increase by 1 every gpio3 is toggled + // use 0x15 to track VPE interrupts - increase by 1 every vpeirq() is called + saa7146_write(dev, EC1SSR, (0x03<<2) | 3 ); + // set event counter 1 threshold to maximum allowed value (rEC p55) + saa7146_write(dev, ECT1R, 0x3fff ); +#endif + // Fix VSYNC level + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); + // Set RPS1 Address register to point to RPS code (r108 p42) + saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); + // Enable RPS1, (rFC p33) + saa7146_write(dev, MC1, (MASK_13 | MASK_29 )); + + + mdelay(50); + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI); + mdelay(150); + + + if( (saa7146_read(dev, GPIO_CTRL) & 0x10000000) == 0) + detected = 1; + +#if RPS_IRQ + printk("Event Counter 1 0x%04x\n", saa7146_read(dev, EC1R) & 0x3fff ); +#endif + // Disable RPS1 + saa7146_write(dev, MC1, ( MASK_29 )); + + if(detected == 0) + printk("budget-patch not detected or saa7146 in non-default state.\n" + "try enabling resetting of 7146 with MASK_31 in MC1 register\n"); + + else + printk("BUDGET-PATCH DETECTED.\n"); + + +/* OLD (Original design by Roberto Deza): +** This code will setup the SAA7146_RPS1 to generate a square +** wave on GPIO3, changing when a field (TS_HEIGHT/2 "lines" of +** TS_WIDTH packets) has been acquired on SAA7146_D1B video port; +** then, this GPIO3 output which is connected to the D1B_VSYNC +** input, will trigger the acquisition of the alternate field +** and so on. +** Currently, the TT_budget / WinTV_Nova cards have two ICs +** (74HCT4040, LVC74) for the generation of this VSYNC signal, +** which seems that can be done perfectly without this :-)). +*/ + +/* New design (By Emard) +** this rps1 code will copy internal HS event to GPIO3 pin. +** GPIO3 is in budget-patch hardware connected to port B VSYNC + +** HS is an internal event of 7146, accessible with RPS +** and temporarily raised high every n lines +** (n in defined in the RPS_THRESH1 counter threshold) +** I think HS is raised high on the beginning of the n-th line +** and remains high until this n-th line that triggered +** it is completely received. When the reception of n-th line +** ends, HS is lowered. + +** To transmit data over DMA, 7146 needs changing state at +** port B VSYNC pin. Any changing of port B VSYNC will +** cause some DMA data transfer, with more or less packets loss. +** It depends on the phase and frequency of VSYNC and +** the way of 7146 is instructed to trigger on port B (defined +** in DD1_INIT register, 3rd nibble from the right valid +** numbers are 0-7, see datasheet) +** +** The correct triggering can minimize packet loss, +** dvbtraffic should give this stable bandwidths: +** 22k transponder = 33814 kbit/s +** 27.5k transponder = 38045 kbit/s +** by experiment it is found that the best results +** (stable bandwidths and almost no packet loss) +** are obtained using DD1_INIT triggering number 2 +** (Va at rising edge of VS Fa = HS x VS-failing forced toggle) +** and a VSYNC phase that occurs in the middle of DMA transfer +** (about byte 188*512=96256 in the DMA window). +** +** Phase of HS is still not clear to me how to control, +** It just happens to be so. It can be seen if one enables +** RPS_IRQ and print Event Counter 1 in vpeirq(). Every +** time RPS_INTERRUPT is called, the Event Counter 1 will +** increment. That's how the 7146 is programmed to do event +** counting in this budget-patch.c +** I *think* HPS setting has something to do with the phase +** of HS but I can't be 100% sure in that. + +** hardware debug note: a working budget card (including budget patch) +** with vpeirq() interrupt setup in mode "0x90" (every 64K) will +** generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes +** and that means 3*25=75 Hz of interrupt frequency, as seen by +** watch cat /proc/interrupts +** +** If this frequency is 3x lower (and data received in the DMA +** buffer don't start with 0x47, but in the middle of packets, +** whose lengths appear to be like 188 292 188 104 etc. +** this means VSYNC line is not connected in the hardware. +** (check soldering pcb and pins) +** The same behaviour of missing VSYNC can be duplicated on budget +** cards, by setting DD1_INIT trigger mode 7 in 3rd nibble. +*/ + + // Setup RPS1 "program" (p35) + count = 0; + + + // Wait Source Line Counter Threshold (p36) + WRITE_RPS1(CMD_PAUSE | EVT_HS); + // Set GPIO3=1 (p42) + WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2)); + WRITE_RPS1(GPIO3_MSK); + WRITE_RPS1(SAA7146_GPIO_OUTHI<<24); +#if RPS_IRQ + // issue RPS1 interrupt + WRITE_RPS1(CMD_INTERRUPT); +#endif + // Wait reset Source Line Counter Threshold (p36) + WRITE_RPS1(CMD_PAUSE | RPS_INV | EVT_HS); + // Set GPIO3=0 (p42) + WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2)); + WRITE_RPS1(GPIO3_MSK); + WRITE_RPS1(SAA7146_GPIO_OUTLO<<24); +#if RPS_IRQ + // issue RPS1 interrupt + WRITE_RPS1(CMD_INTERRUPT); +#endif + // Jump to begin of RPS program (p37) + WRITE_RPS1(CMD_JUMP); + WRITE_RPS1(dev->d_rps1.dma_handle); + + // Fix VSYNC level + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); + // Set RPS1 Address register to point to RPS code (r108 p42) + saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); + + if (!(budget = kmalloc (sizeof(struct budget_patch), GFP_KERNEL))) + return -ENOMEM; + + dprintk(2, "budget: %p\n", budget); + + err = ttpci_budget_init(budget, dev, info, THIS_MODULE, adapter_nr); + if (err) { + kfree(budget); + return err; + } + + // Set Source Line Counter Threshold, using BRS (rCC p43) + // It generates HS event every TS_HEIGHT lines + // this is related to TS_WIDTH set in register + // NUM_LINE_BYTE3 in budget-core.c. If NUM_LINE_BYTE + // low 16 bits are set to TS_WIDTH bytes (TS_WIDTH=2*188 + //,then RPS_THRESH1 + // should be set to trigger every TS_HEIGHT (512) lines. + // + saa7146_write(dev, RPS_THRESH1, budget->buffer_height | MASK_12 ); + + // saa7146_write(dev, RPS_THRESH0, ((TS_HEIGHT/2)<<16) |MASK_28| (TS_HEIGHT/2) |MASK_12 ); + // Enable RPS1 (rFC p33) + saa7146_write(dev, MC1, (MASK_13 | MASK_29)); + + + dev->ext_priv = budget; + + budget->dvb_adapter.priv = budget; + frontend_init(budget); + + ttpci_budget_init_hooks(budget); + + return 0; +} + +static int budget_patch_detach (struct saa7146_dev* dev) +{ + struct budget_patch *budget = (struct budget_patch*) dev->ext_priv; + int err; + + if (budget->dvb_frontend) { + dvb_unregister_frontend(budget->dvb_frontend); + dvb_frontend_detach(budget->dvb_frontend); + } + err = ttpci_budget_deinit (budget); + + kfree (budget); + + return err; +} + +static int __init budget_patch_init(void) +{ + return saa7146_register_extension(&budget_extension); +} + +static void __exit budget_patch_exit(void) +{ + saa7146_unregister_extension(&budget_extension); +} + +static struct saa7146_extension budget_extension = { + .name = "budget_patch dvb", + .flags = 0, + + .module = THIS_MODULE, + .pci_tbl = pci_tbl, + .attach = budget_patch_attach, + .detach = budget_patch_detach, + + .irq_mask = MASK_10, + .irq_func = ttpci_budget_irq10_handler, +}; + +module_init(budget_patch_init); +module_exit(budget_patch_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Emard, Roberto Deza, Holger Waechtler, Michael Hunold, others"); +MODULE_DESCRIPTION("Driver for full TS modified DVB-S SAA7146+AV7110 based so-called Budget Patch cards"); diff --git a/drivers/staging/media/deprecated/saa7146/av7110/dvb_filter.c b/drivers/staging/media/deprecated/saa7146/av7110/dvb_filter.c new file mode 100644 index 000000000..8c2eca5dc --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/dvb_filter.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include "dvb_filter.h" + +static u32 freq[4] = {480, 441, 320, 0}; + +static unsigned int ac3_bitrates[32] = + {32,40,48,56,64,80,96,112,128,160,192,224,256,320,384,448,512,576,640, + 0,0,0,0,0,0,0,0,0,0,0,0,0}; + +static u32 ac3_frames[3][32] = + {{64,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024, + 1152,1280,0,0,0,0,0,0,0,0,0,0,0,0,0}, + {69,87,104,121,139,174,208,243,278,348,417,487,557,696,835,975,1114, + 1253,1393,0,0,0,0,0,0,0,0,0,0,0,0,0}, + {96,120,144,168,192,240,288,336,384,480,576,672,768,960,1152,1344, + 1536,1728,1920,0,0,0,0,0,0,0,0,0,0,0,0,0}}; + +int dvb_filter_get_ac3info(u8 *mbuf, int count, struct dvb_audio_info *ai, int pr) +{ + u8 *headr; + int found = 0; + int c = 0; + u8 frame = 0; + int fr = 0; + + while ( !found && c < count){ + u8 *b = mbuf+c; + + if ( b[0] == 0x0b && b[1] == 0x77 ) + found = 1; + else { + c++; + } + } + + if (!found) return -1; + if (pr) + printk(KERN_DEBUG "Audiostream: AC3"); + + ai->off = c; + if (c+5 >= count) return -1; + + ai->layer = 0; // 0 for AC3 + headr = mbuf+c+2; + + frame = (headr[2]&0x3f); + ai->bit_rate = ac3_bitrates[frame >> 1]*1000; + + if (pr) + printk(KERN_CONT " BRate: %d kb/s", (int) ai->bit_rate/1000); + + ai->frequency = (headr[2] & 0xc0 ) >> 6; + fr = (headr[2] & 0xc0 ) >> 6; + ai->frequency = freq[fr]*100; + if (pr) + printk(KERN_CONT " Freq: %d Hz\n", (int) ai->frequency); + + ai->framesize = ac3_frames[fr][frame >> 1]; + if ((frame & 1) && (fr == 1)) ai->framesize++; + ai->framesize = ai->framesize << 1; + if (pr) + printk(KERN_DEBUG " Framesize %d\n", (int) ai->framesize); + + return 0; +} + +void dvb_filter_pes2ts_init(struct dvb_filter_pes2ts *p2ts, unsigned short pid, + dvb_filter_pes2ts_cb_t *cb, void *priv) +{ + unsigned char *buf=p2ts->buf; + + buf[0]=0x47; + buf[1]=(pid>>8); + buf[2]=pid&0xff; + p2ts->cc=0; + p2ts->cb=cb; + p2ts->priv=priv; +} + +int dvb_filter_pes2ts(struct dvb_filter_pes2ts *p2ts, unsigned char *pes, + int len, int payload_start) +{ + unsigned char *buf=p2ts->buf; + int ret=0, rest; + + //len=6+((pes[4]<<8)|pes[5]); + + if (payload_start) + buf[1]|=0x40; + else + buf[1]&=~0x40; + while (len>=184) { + buf[3]=0x10|((p2ts->cc++)&0x0f); + memcpy(buf+4, pes, 184); + if ((ret=p2ts->cb(p2ts->priv, buf))) + return ret; + len-=184; pes+=184; + buf[1]&=~0x40; + } + if (!len) + return 0; + buf[3]=0x30|((p2ts->cc++)&0x0f); + rest=183-len; + if (rest) { + buf[5]=0x00; + if (rest-1) + memset(buf+6, 0xff, rest-1); + } + buf[4]=rest; + memcpy(buf+5+rest, pes, len); + return p2ts->cb(p2ts->priv, buf); +} diff --git a/drivers/staging/media/deprecated/saa7146/av7110/dvb_filter.h b/drivers/staging/media/deprecated/saa7146/av7110/dvb_filter.h new file mode 100644 index 000000000..67a3c6333 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/dvb_filter.h @@ -0,0 +1,242 @@ +/* + * dvb_filter.h + * + * Copyright (C) 2003 Convergence GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DVB_FILTER_H_ +#define _DVB_FILTER_H_ + +#include + +#include + +typedef int (dvb_filter_pes2ts_cb_t) (void *, unsigned char *); + +struct dvb_filter_pes2ts { + unsigned char buf[188]; + unsigned char cc; + dvb_filter_pes2ts_cb_t *cb; + void *priv; +}; + +void dvb_filter_pes2ts_init(struct dvb_filter_pes2ts *p2ts, unsigned short pid, + dvb_filter_pes2ts_cb_t *cb, void *priv); + +int dvb_filter_pes2ts(struct dvb_filter_pes2ts *p2ts, unsigned char *pes, + int len, int payload_start); + + +#define PROG_STREAM_MAP 0xBC +#define PRIVATE_STREAM1 0xBD +#define PADDING_STREAM 0xBE +#define PRIVATE_STREAM2 0xBF +#define AUDIO_STREAM_S 0xC0 +#define AUDIO_STREAM_E 0xDF +#define VIDEO_STREAM_S 0xE0 +#define VIDEO_STREAM_E 0xEF +#define ECM_STREAM 0xF0 +#define EMM_STREAM 0xF1 +#define DSM_CC_STREAM 0xF2 +#define ISO13522_STREAM 0xF3 +#define PROG_STREAM_DIR 0xFF + +#define DVB_PICTURE_START 0x00 +#define DVB_USER_START 0xb2 +#define DVB_SEQUENCE_HEADER 0xb3 +#define DVB_SEQUENCE_ERROR 0xb4 +#define DVB_EXTENSION_START 0xb5 +#define DVB_SEQUENCE_END 0xb7 +#define DVB_GOP_START 0xb8 +#define DVB_EXCEPT_SLICE 0xb0 + +#define SEQUENCE_EXTENSION 0x01 +#define SEQUENCE_DISPLAY_EXTENSION 0x02 +#define PICTURE_CODING_EXTENSION 0x08 +#define QUANT_MATRIX_EXTENSION 0x03 +#define PICTURE_DISPLAY_EXTENSION 0x07 + +#define I_FRAME 0x01 +#define B_FRAME 0x02 +#define P_FRAME 0x03 + +/* Initialize sequence_data */ +#define INIT_HORIZONTAL_SIZE 720 +#define INIT_VERTICAL_SIZE 576 +#define INIT_ASPECT_RATIO 0x02 +#define INIT_FRAME_RATE 0x03 +#define INIT_DISP_HORIZONTAL_SIZE 540 +#define INIT_DISP_VERTICAL_SIZE 576 + + +//flags2 +#define PTS_DTS_FLAGS 0xC0 +#define ESCR_FLAG 0x20 +#define ES_RATE_FLAG 0x10 +#define DSM_TRICK_FLAG 0x08 +#define ADD_CPY_FLAG 0x04 +#define PES_CRC_FLAG 0x02 +#define PES_EXT_FLAG 0x01 + +//pts_dts flags +#define PTS_ONLY 0x80 +#define PTS_DTS 0xC0 + +#define TS_SIZE 188 +#define TRANS_ERROR 0x80 +#define PAY_START 0x40 +#define TRANS_PRIO 0x20 +#define PID_MASK_HI 0x1F +//flags +#define TRANS_SCRMBL1 0x80 +#define TRANS_SCRMBL2 0x40 +#define ADAPT_FIELD 0x20 +#define PAYLOAD 0x10 +#define COUNT_MASK 0x0F + +// adaptation flags +#define DISCON_IND 0x80 +#define RAND_ACC_IND 0x40 +#define ES_PRI_IND 0x20 +#define PCR_FLAG 0x10 +#define OPCR_FLAG 0x08 +#define SPLICE_FLAG 0x04 +#define TRANS_PRIV 0x02 +#define ADAP_EXT_FLAG 0x01 + +// adaptation extension flags +#define LTW_FLAG 0x80 +#define PIECE_RATE 0x40 +#define SEAM_SPLICE 0x20 + + +#define MAX_PLENGTH 0xFFFF +#define MMAX_PLENGTH (256*MAX_PLENGTH) + +#ifndef IPACKS +#define IPACKS 2048 +#endif + +struct ipack { + int size; + int found; + u8 *buf; + u8 cid; + u32 plength; + u8 plen[2]; + u8 flag1; + u8 flag2; + u8 hlength; + u8 pts[5]; + u16 *pid; + int mpeg; + u8 check; + int which; + int done; + void *data; + void (*func)(u8 *buf, int size, void *priv); + int count; + int repack_subids; +}; + +struct dvb_video_info { + u32 horizontal_size; + u32 vertical_size; + u32 aspect_ratio; + u32 framerate; + u32 video_format; + u32 bit_rate; + u32 comp_bit_rate; + u32 vbv_buffer_size; + s16 vbv_delay; + u32 CSPF; + u32 off; +}; + +#define OFF_SIZE 4 +#define FIRST_FIELD 0 +#define SECOND_FIELD 1 +#define VIDEO_FRAME_PICTURE 0x03 + +struct mpg_picture { + int channel; + struct dvb_video_info vinfo; + u32 *sequence_gop_header; + u32 *picture_header; + s32 time_code; + int low_delay; + int closed_gop; + int broken_link; + int sequence_header_flag; + int gop_flag; + int sequence_end_flag; + + u8 profile_and_level; + s32 picture_coding_parameter; + u32 matrix[32]; + s8 matrix_change_flag; + + u8 picture_header_parameter; + /* bit 0 - 2: bwd f code + bit 3 : fpb vector + bit 4 - 6: fwd f code + bit 7 : fpf vector */ + + int mpeg1_flag; + int progressive_sequence; + int sequence_display_extension_flag; + u32 sequence_header_data; + s16 last_frame_centre_horizontal_offset; + s16 last_frame_centre_vertical_offset; + + u32 pts[2]; /* [0] 1st field, [1] 2nd field */ + int top_field_first; + int repeat_first_field; + int progressive_frame; + int bank; + int forward_bank; + int backward_bank; + int compress; + s16 frame_centre_horizontal_offset[OFF_SIZE]; + /* [0-2] 1st field, [3] 2nd field */ + s16 frame_centre_vertical_offset[OFF_SIZE]; + /* [0-2] 1st field, [3] 2nd field */ + s16 temporal_reference[2]; + /* [0] 1st field, [1] 2nd field */ + + s8 picture_coding_type[2]; + /* [0] 1st field, [1] 2nd field */ + s8 picture_structure[2]; + /* [0] 1st field, [1] 2nd field */ + s8 picture_display_extension_flag[2]; + /* [0] 1st field, [1] 2nd field */ + /* picture_display_extenion() 0:no 1:exit*/ + s8 pts_flag[2]; + /* [0] 1st field, [1] 2nd field */ +}; + +struct dvb_audio_info { + int layer; + u32 bit_rate; + u32 frequency; + u32 mode; + u32 mode_extension ; + u32 emphasis; + u32 framesize; + u32 off; +}; + +int dvb_filter_get_ac3info(u8 *mbuf, int count, struct dvb_audio_info *ai, int pr); + + +#endif diff --git a/drivers/staging/media/deprecated/saa7146/av7110/sp8870.c b/drivers/staging/media/deprecated/saa7146/av7110/sp8870.c new file mode 100644 index 000000000..9767159ae --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/sp8870.c @@ -0,0 +1,609 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + Driver for Spase SP8870 demodulator + + Copyright (C) 1999 Juergen Peitz + + +*/ +/* + * This driver needs external firmware. Please use the command + * "/scripts/get_dvb_firmware alps_tdlb7" to + * download/extract it, and then copy it to /usr/lib/hotplug/firmware + * or /lib/firmware (depending on configuration of firmware hotplug). + */ +#define SP8870_DEFAULT_FIRMWARE "dvb-fe-sp8870.fw" + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "sp8870.h" + + +struct sp8870_state { + + struct i2c_adapter* i2c; + + const struct sp8870_config* config; + + struct dvb_frontend frontend; + + /* demodulator private data */ + u8 initialised:1; +}; + +static int debug; +#define dprintk(args...) \ + do { \ + if (debug) printk(KERN_DEBUG "sp8870: " args); \ + } while (0) + +/* firmware size for sp8870 */ +#define SP8870_FIRMWARE_SIZE 16382 + +/* starting point for firmware in file 'Sc_main.mc' */ +#define SP8870_FIRMWARE_OFFSET 0x0A + +static int sp8870_writereg (struct sp8870_state* state, u16 reg, u16 data) +{ + u8 buf [] = { reg >> 8, reg & 0xff, data >> 8, data & 0xff }; + struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 4 }; + int err; + + if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { + dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data); + return -EREMOTEIO; + } + + return 0; +} + +static int sp8870_readreg (struct sp8870_state* state, u16 reg) +{ + int ret; + u8 b0 [] = { reg >> 8 , reg & 0xff }; + u8 b1 [] = { 0, 0 }; + struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, + { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 2 } }; + + ret = i2c_transfer (state->i2c, msg, 2); + + if (ret != 2) { + dprintk("%s: readreg error (ret == %i)\n", __func__, ret); + return -1; + } + + return (b1[0] << 8 | b1[1]); +} + +static int sp8870_firmware_upload (struct sp8870_state* state, const struct firmware *fw) +{ + struct i2c_msg msg; + const char *fw_buf = fw->data; + int fw_pos; + u8 tx_buf[255]; + int tx_len; + int err = 0; + + dprintk ("%s: ...\n", __func__); + + if (fw->size < SP8870_FIRMWARE_SIZE + SP8870_FIRMWARE_OFFSET) + return -EINVAL; + + // system controller stop + sp8870_writereg(state, 0x0F00, 0x0000); + + // instruction RAM register hiword + sp8870_writereg(state, 0x8F08, ((SP8870_FIRMWARE_SIZE / 2) & 0xFFFF)); + + // instruction RAM MWR + sp8870_writereg(state, 0x8F0A, ((SP8870_FIRMWARE_SIZE / 2) >> 16)); + + // do firmware upload + fw_pos = SP8870_FIRMWARE_OFFSET; + while (fw_pos < SP8870_FIRMWARE_SIZE + SP8870_FIRMWARE_OFFSET){ + tx_len = (fw_pos <= SP8870_FIRMWARE_SIZE + SP8870_FIRMWARE_OFFSET - 252) ? 252 : SP8870_FIRMWARE_SIZE + SP8870_FIRMWARE_OFFSET - fw_pos; + // write register 0xCF0A + tx_buf[0] = 0xCF; + tx_buf[1] = 0x0A; + memcpy(&tx_buf[2], fw_buf + fw_pos, tx_len); + msg.addr = state->config->demod_address; + msg.flags = 0; + msg.buf = tx_buf; + msg.len = tx_len + 2; + if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { + printk("%s: firmware upload failed!\n", __func__); + printk ("%s: i2c error (err == %i)\n", __func__, err); + return err; + } + fw_pos += tx_len; + } + + dprintk ("%s: done!\n", __func__); + return 0; +}; + +static void sp8870_microcontroller_stop (struct sp8870_state* state) +{ + sp8870_writereg(state, 0x0F08, 0x000); + sp8870_writereg(state, 0x0F09, 0x000); + + // microcontroller STOP + sp8870_writereg(state, 0x0F00, 0x000); +} + +static void sp8870_microcontroller_start (struct sp8870_state* state) +{ + sp8870_writereg(state, 0x0F08, 0x000); + sp8870_writereg(state, 0x0F09, 0x000); + + // microcontroller START + sp8870_writereg(state, 0x0F00, 0x001); + // not documented but if we don't read 0x0D01 out here + // we don't get a correct data valid signal + sp8870_readreg(state, 0x0D01); +} + +static int sp8870_read_data_valid_signal(struct sp8870_state* state) +{ + return (sp8870_readreg(state, 0x0D02) > 0); +} + +static int configure_reg0xc05 (struct dtv_frontend_properties *p, u16 *reg0xc05) +{ + int known_parameters = 1; + + *reg0xc05 = 0x000; + + switch (p->modulation) { + case QPSK: + break; + case QAM_16: + *reg0xc05 |= (1 << 10); + break; + case QAM_64: + *reg0xc05 |= (2 << 10); + break; + case QAM_AUTO: + known_parameters = 0; + break; + default: + return -EINVAL; + } + + switch (p->hierarchy) { + case HIERARCHY_NONE: + break; + case HIERARCHY_1: + *reg0xc05 |= (1 << 7); + break; + case HIERARCHY_2: + *reg0xc05 |= (2 << 7); + break; + case HIERARCHY_4: + *reg0xc05 |= (3 << 7); + break; + case HIERARCHY_AUTO: + known_parameters = 0; + break; + default: + return -EINVAL; + } + + switch (p->code_rate_HP) { + case FEC_1_2: + break; + case FEC_2_3: + *reg0xc05 |= (1 << 3); + break; + case FEC_3_4: + *reg0xc05 |= (2 << 3); + break; + case FEC_5_6: + *reg0xc05 |= (3 << 3); + break; + case FEC_7_8: + *reg0xc05 |= (4 << 3); + break; + case FEC_AUTO: + known_parameters = 0; + break; + default: + return -EINVAL; + } + + if (known_parameters) + *reg0xc05 |= (2 << 1); /* use specified parameters */ + else + *reg0xc05 |= (1 << 1); /* enable autoprobing */ + + return 0; +} + +static int sp8870_wake_up(struct sp8870_state* state) +{ + // enable TS output and interface pins + return sp8870_writereg(state, 0xC18, 0x00D); +} + +static int sp8870_set_frontend_parameters(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct sp8870_state* state = fe->demodulator_priv; + int err; + u16 reg0xc05; + + if ((err = configure_reg0xc05(p, ®0xc05))) + return err; + + // system controller stop + sp8870_microcontroller_stop(state); + + // set tuner parameters + if (fe->ops.tuner_ops.set_params) { + fe->ops.tuner_ops.set_params(fe); + if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); + } + + // sample rate correction bit [23..17] + sp8870_writereg(state, 0x0319, 0x000A); + + // sample rate correction bit [16..0] + sp8870_writereg(state, 0x031A, 0x0AAB); + + // integer carrier offset + sp8870_writereg(state, 0x0309, 0x0400); + + // fractional carrier offset + sp8870_writereg(state, 0x030A, 0x0000); + + // filter for 6/7/8 Mhz channel + if (p->bandwidth_hz == 6000000) + sp8870_writereg(state, 0x0311, 0x0002); + else if (p->bandwidth_hz == 7000000) + sp8870_writereg(state, 0x0311, 0x0001); + else + sp8870_writereg(state, 0x0311, 0x0000); + + // scan order: 2k first = 0x0000, 8k first = 0x0001 + if (p->transmission_mode == TRANSMISSION_MODE_2K) + sp8870_writereg(state, 0x0338, 0x0000); + else + sp8870_writereg(state, 0x0338, 0x0001); + + sp8870_writereg(state, 0xc05, reg0xc05); + + // read status reg in order to clear pending irqs + err = sp8870_readreg(state, 0x200); + if (err < 0) + return err; + + // system controller start + sp8870_microcontroller_start(state); + + return 0; +} + +static int sp8870_init (struct dvb_frontend* fe) +{ + struct sp8870_state* state = fe->demodulator_priv; + const struct firmware *fw = NULL; + + sp8870_wake_up(state); + if (state->initialised) return 0; + state->initialised = 1; + + dprintk ("%s\n", __func__); + + + /* request the firmware, this will block until someone uploads it */ + printk("sp8870: waiting for firmware upload (%s)...\n", SP8870_DEFAULT_FIRMWARE); + if (state->config->request_firmware(fe, &fw, SP8870_DEFAULT_FIRMWARE)) { + printk("sp8870: no firmware upload (timeout or file not found?)\n"); + return -EIO; + } + + if (sp8870_firmware_upload(state, fw)) { + printk("sp8870: writing firmware to device failed\n"); + release_firmware(fw); + return -EIO; + } + release_firmware(fw); + printk("sp8870: firmware upload complete\n"); + + /* enable TS output and interface pins */ + sp8870_writereg(state, 0xc18, 0x00d); + + // system controller stop + sp8870_microcontroller_stop(state); + + // ADC mode + sp8870_writereg(state, 0x0301, 0x0003); + + // Reed Solomon parity bytes passed to output + sp8870_writereg(state, 0x0C13, 0x0001); + + // MPEG clock is suppressed if no valid data + sp8870_writereg(state, 0x0C14, 0x0001); + + /* bit 0x010: enable data valid signal */ + sp8870_writereg(state, 0x0D00, 0x010); + sp8870_writereg(state, 0x0D01, 0x000); + + return 0; +} + +static int sp8870_read_status(struct dvb_frontend *fe, + enum fe_status *fe_status) +{ + struct sp8870_state* state = fe->demodulator_priv; + int status; + int signal; + + *fe_status = 0; + + status = sp8870_readreg (state, 0x0200); + if (status < 0) + return -EIO; + + signal = sp8870_readreg (state, 0x0303); + if (signal < 0) + return -EIO; + + if (signal > 0x0F) + *fe_status |= FE_HAS_SIGNAL; + if (status & 0x08) + *fe_status |= FE_HAS_SYNC; + if (status & 0x04) + *fe_status |= FE_HAS_LOCK | FE_HAS_CARRIER | FE_HAS_VITERBI; + + return 0; +} + +static int sp8870_read_ber (struct dvb_frontend* fe, u32 * ber) +{ + struct sp8870_state* state = fe->demodulator_priv; + int ret; + u32 tmp; + + *ber = 0; + + ret = sp8870_readreg(state, 0xC08); + if (ret < 0) + return -EIO; + + tmp = ret & 0x3F; + + ret = sp8870_readreg(state, 0xC07); + if (ret < 0) + return -EIO; + + tmp = ret << 6; + if (tmp >= 0x3FFF0) + tmp = ~0; + + *ber = tmp; + + return 0; +} + +static int sp8870_read_signal_strength(struct dvb_frontend* fe, u16 * signal) +{ + struct sp8870_state* state = fe->demodulator_priv; + int ret; + u16 tmp; + + *signal = 0; + + ret = sp8870_readreg (state, 0x306); + if (ret < 0) + return -EIO; + + tmp = ret << 8; + + ret = sp8870_readreg (state, 0x303); + if (ret < 0) + return -EIO; + + tmp |= ret; + + if (tmp) + *signal = 0xFFFF - tmp; + + return 0; +} + +static int sp8870_read_uncorrected_blocks (struct dvb_frontend* fe, u32* ublocks) +{ + struct sp8870_state* state = fe->demodulator_priv; + int ret; + + *ublocks = 0; + + ret = sp8870_readreg(state, 0xC0C); + if (ret < 0) + return -EIO; + + if (ret == 0xFFFF) + ret = ~0; + + *ublocks = ret; + + return 0; +} + +/* number of trials to recover from lockup */ +#define MAXTRIALS 5 +/* maximum checks for data valid signal */ +#define MAXCHECKS 100 + +/* only for debugging: counter for detected lockups */ +static int lockups; +/* only for debugging: counter for channel switches */ +static int switches; + +static int sp8870_set_frontend(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct sp8870_state* state = fe->demodulator_priv; + + /* + The firmware of the sp8870 sometimes locks up after setting frontend parameters. + We try to detect this by checking the data valid signal. + If it is not set after MAXCHECKS we try to recover the lockup by setting + the frontend parameters again. + */ + + int err = 0; + int valid = 0; + int trials = 0; + int check_count = 0; + + dprintk("%s: frequency = %i\n", __func__, p->frequency); + + for (trials = 1; trials <= MAXTRIALS; trials++) { + + err = sp8870_set_frontend_parameters(fe); + if (err) + return err; + + for (check_count = 0; check_count < MAXCHECKS; check_count++) { +// valid = ((sp8870_readreg(i2c, 0x0200) & 4) == 0); + valid = sp8870_read_data_valid_signal(state); + if (valid) { + dprintk("%s: delay = %i usec\n", + __func__, check_count * 10); + break; + } + udelay(10); + } + if (valid) + break; + } + + if (!valid) { + printk("%s: firmware crash!!!!!!\n", __func__); + return -EIO; + } + + if (debug) { + if (valid) { + if (trials > 1) { + printk("%s: firmware lockup!!!\n", __func__); + printk("%s: recovered after %i trial(s))\n", __func__, trials - 1); + lockups++; + } + } + switches++; + printk("%s: switches = %i lockups = %i\n", __func__, switches, lockups); + } + + return 0; +} + +static int sp8870_sleep(struct dvb_frontend* fe) +{ + struct sp8870_state* state = fe->demodulator_priv; + + // tristate TS output and disable interface pins + return sp8870_writereg(state, 0xC18, 0x000); +} + +static int sp8870_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) +{ + fesettings->min_delay_ms = 350; + fesettings->step_size = 0; + fesettings->max_drift = 0; + return 0; +} + +static int sp8870_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) +{ + struct sp8870_state* state = fe->demodulator_priv; + + if (enable) { + return sp8870_writereg(state, 0x206, 0x001); + } else { + return sp8870_writereg(state, 0x206, 0x000); + } +} + +static void sp8870_release(struct dvb_frontend* fe) +{ + struct sp8870_state* state = fe->demodulator_priv; + kfree(state); +} + +static const struct dvb_frontend_ops sp8870_ops; + +struct dvb_frontend* sp8870_attach(const struct sp8870_config* config, + struct i2c_adapter* i2c) +{ + struct sp8870_state* state = NULL; + + /* allocate memory for the internal state */ + state = kzalloc(sizeof(struct sp8870_state), GFP_KERNEL); + if (state == NULL) goto error; + + /* setup the state */ + state->config = config; + state->i2c = i2c; + state->initialised = 0; + + /* check if the demod is there */ + if (sp8870_readreg(state, 0x0200) < 0) goto error; + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &sp8870_ops, sizeof(struct dvb_frontend_ops)); + state->frontend.demodulator_priv = state; + return &state->frontend; + +error: + kfree(state); + return NULL; +} + +static const struct dvb_frontend_ops sp8870_ops = { + .delsys = { SYS_DVBT }, + .info = { + .name = "Spase SP8870 DVB-T", + .frequency_min_hz = 470 * MHz, + .frequency_max_hz = 860 * MHz, + .frequency_stepsize_hz = 166666, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | + FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | + FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER + }, + + .release = sp8870_release, + + .init = sp8870_init, + .sleep = sp8870_sleep, + .i2c_gate_ctrl = sp8870_i2c_gate_ctrl, + + .set_frontend = sp8870_set_frontend, + .get_tune_settings = sp8870_get_tune_settings, + + .read_status = sp8870_read_status, + .read_ber = sp8870_read_ber, + .read_signal_strength = sp8870_read_signal_strength, + .read_ucblocks = sp8870_read_uncorrected_blocks, +}; + +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); + +MODULE_DESCRIPTION("Spase SP8870 DVB-T Demodulator driver"); +MODULE_AUTHOR("Juergen Peitz"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(sp8870_attach); diff --git a/drivers/staging/media/deprecated/saa7146/av7110/sp8870.h b/drivers/staging/media/deprecated/saa7146/av7110/sp8870.h new file mode 100644 index 000000000..5eacf39f4 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/sp8870.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + Driver for Spase SP8870 demodulator + + Copyright (C) 1999 Juergen Peitz + + +*/ + +#ifndef SP8870_H +#define SP8870_H + +#include +#include + +struct sp8870_config +{ + /* the demodulator's i2c address */ + u8 demod_address; + + /* request firmware for device */ + int (*request_firmware)(struct dvb_frontend* fe, const struct firmware **fw, char* name); +}; + +#if IS_REACHABLE(CONFIG_DVB_SP8870) +extern struct dvb_frontend* sp8870_attach(const struct sp8870_config* config, + struct i2c_adapter* i2c); +#else +static inline struct dvb_frontend* sp8870_attach(const struct sp8870_config* config, + struct i2c_adapter* i2c) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif // CONFIG_DVB_SP8870 + +#endif // SP8870_H diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-clear-buffer.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-clear-buffer.rst new file mode 100644 index 000000000..a7730559b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-clear-buffer.rst @@ -0,0 +1,54 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_CLEAR_BUFFER: + +================== +VIDEO_CLEAR_BUFFER +================== + +Name +---- + +VIDEO_CLEAR_BUFFER + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_CLEAR_BUFFER + +``int ioctl(fd, VIDEO_CLEAR_BUFFER)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_CLEAR_BUFFER for this command. + +Description +----------- + +This ioctl call clears all video buffers in the driver and in the +decoder hardware. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-command.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-command.rst new file mode 100644 index 000000000..cae9445eb --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-command.rst @@ -0,0 +1,96 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_COMMAND: + +============= +VIDEO_COMMAND +============= + +Name +---- + +VIDEO_COMMAND + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_COMMAND + +``int ioctl(int fd, VIDEO_COMMAND, struct video_command *cmd)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_COMMAND for this command. + + - .. row 3 + + - struct video_command \*cmd + + - Commands the decoder. + +Description +----------- + +This ioctl is obsolete. Do not use in new drivers. For V4L2 decoders +this ioctl has been replaced by the +:ref:`VIDIOC_DECODER_CMD` ioctl. + +This ioctl commands the decoder. The ``video_command`` struct is a +subset of the ``v4l2_decoder_cmd`` struct, so refer to the +:ref:`VIDIOC_DECODER_CMD` documentation for +more information. + +.. c:type:: video_command + +.. code-block:: c + + /* The structure must be zeroed before use by the application + This ensures it can be extended safely in the future. */ + struct video_command { + __u32 cmd; + __u32 flags; + union { + struct { + __u64 pts; + } stop; + + struct { + /* 0 or 1000 specifies normal speed, + 1 specifies forward single stepping, + -1 specifies backward single stepping, + >1: playback at speed/1000 of the normal speed, + <-1: reverse playback at (-speed/1000) of the normal speed. */ + __s32 speed; + __u32 format; + } play; + + struct { + __u32 data[16]; + } raw; + }; + }; + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-continue.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-continue.rst new file mode 100644 index 000000000..bc34bf398 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-continue.rst @@ -0,0 +1,57 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_CONTINUE: + +============== +VIDEO_CONTINUE +============== + +Name +---- + +VIDEO_CONTINUE + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_CONTINUE + +``int ioctl(fd, VIDEO_CONTINUE)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_CONTINUE for this command. + +Description +----------- + +This ioctl is for Digital TV devices only. To control a V4L2 decoder use the +V4L2 :ref:`VIDIOC_DECODER_CMD` instead. + +This ioctl call restarts decoding and playing processes of the video +stream which was played before a call to VIDEO_FREEZE was made. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-fast-forward.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-fast-forward.rst new file mode 100644 index 000000000..e71fa8d69 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-fast-forward.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_FAST_FORWARD: + +================== +VIDEO_FAST_FORWARD +================== + +Name +---- + +VIDEO_FAST_FORWARD + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_FAST_FORWARD + +``int ioctl(fd, VIDEO_FAST_FORWARD, int nFrames)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_FAST_FORWARD for this command. + + - .. row 3 + + - int nFrames + + - The number of frames to skip. + +Description +----------- + +This ioctl call asks the Video Device to skip decoding of N number of +I-frames. This call can only be used if VIDEO_SOURCE_MEMORY is +selected. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. + + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EPERM`` + + - Mode VIDEO_SOURCE_MEMORY not selected. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-fclose.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-fclose.rst new file mode 100644 index 000000000..01d24d548 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-fclose.rst @@ -0,0 +1,51 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _video_fclose: + +================= +dvb video close() +================= + +Name +---- + +dvb video close() + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:function:: int close(int fd) + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + +Description +----------- + +This system call closes a previously opened video device. + +Return Value +------------ + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EBADF`` + + - fd is not a valid open file descriptor. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-fopen.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-fopen.rst new file mode 100644 index 000000000..1371b083e --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-fopen.rst @@ -0,0 +1,111 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _video_fopen: + +================ +dvb video open() +================ + +Name +---- + +dvb video open() + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:function:: int open(const char *deviceName, int flags) + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - const char \*deviceName + + - Name of specific video device. + + - .. row 2 + + - int flags + + - A bit-wise OR of the following flags: + + - .. row 3 + + - + - O_RDONLY read-only access + + - .. row 4 + + - + - O_RDWR read/write access + + - .. row 5 + + - + - O_NONBLOCK open in non-blocking mode + + - .. row 6 + + - + - (blocking mode is the default) + +Description +----------- + +This system call opens a named video device (e.g. +/dev/dvb/adapter0/video0) for subsequent use. + +When an open() call has succeeded, the device will be ready for use. The +significance of blocking or non-blocking mode is described in the +documentation for functions where there is a difference. It does not +affect the semantics of the open() call itself. A device opened in +blocking mode can later be put into non-blocking mode (and vice versa) +using the F_SETFL command of the fcntl system call. This is a standard +system call, documented in the Linux manual page for fcntl. Only one +user can open the Video Device in O_RDWR mode. All other attempts to +open the device in this mode will fail, and an error-code will be +returned. If the Video Device is opened in O_RDONLY mode, the only +ioctl call that can be used is VIDEO_GET_STATUS. All other call will +return an error code. + +Return Value +------------ + +.. tabularcolumns:: |p{2.5cm}|p{15.0cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``ENODEV`` + + - Device driver not loaded/available. + + - .. row 2 + + - ``EINTERNAL`` + + - Internal error. + + - .. row 3 + + - ``EBUSY`` + + - Device or resource busy. + + - .. row 4 + + - ``EINVAL`` + + - Invalid argument. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-freeze.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-freeze.rst new file mode 100644 index 000000000..4321f257c --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-freeze.rst @@ -0,0 +1,61 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_FREEZE: + +============ +VIDEO_FREEZE +============ + +Name +---- + +VIDEO_FREEZE + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_FREEZE + +``int ioctl(fd, VIDEO_FREEZE)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_FREEZE for this command. + +Description +----------- + +This ioctl is for Digital TV devices only. To control a V4L2 decoder use the +V4L2 :ref:`VIDIOC_DECODER_CMD` instead. + +This ioctl call suspends the live video stream being played. Decoding +and playing are frozen. It is then possible to restart the decoding and +playing process of the video stream using the VIDEO_CONTINUE command. +If VIDEO_SOURCE_MEMORY is selected in the ioctl call +VIDEO_SELECT_SOURCE, the Digital TV subsystem will not decode any more data +until the ioctl call VIDEO_CONTINUE or VIDEO_PLAY is performed. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-fwrite.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-fwrite.rst new file mode 100644 index 000000000..a07fd7d7a --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-fwrite.rst @@ -0,0 +1,79 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _video_fwrite: + +================= +dvb video write() +================= + +Name +---- + +dvb video write() + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:function:: size_t write(int fd, const void *buf, size_t count) + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - void \*buf + + - Pointer to the buffer containing the PES data. + + - .. row 3 + + - size_t count + + - Size of buf. + +Description +----------- + +This system call can only be used if VIDEO_SOURCE_MEMORY is selected +in the ioctl call VIDEO_SELECT_SOURCE. The data provided shall be in +PES format, unless the capability allows other formats. If O_NONBLOCK +is not specified the function will block until buffer space is +available. The amount of data to be transferred is implied by count. + +Return Value +------------ + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EPERM`` + + - Mode VIDEO_SOURCE_MEMORY not selected. + + - .. row 2 + + - ``ENOMEM`` + + - Attempted to write more data than the internal buffer can hold. + + - .. row 3 + + - ``EBADF`` + + - fd is not a valid open file descriptor. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-get-capabilities.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-get-capabilities.rst new file mode 100644 index 000000000..01e09f566 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-get-capabilities.rst @@ -0,0 +1,61 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_GET_CAPABILITIES: + +====================== +VIDEO_GET_CAPABILITIES +====================== + +Name +---- + +VIDEO_GET_CAPABILITIES + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_GET_CAPABILITIES + +``int ioctl(fd, VIDEO_GET_CAPABILITIES, unsigned int *cap)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_GET_CAPABILITIES for this command. + + - .. row 3 + + - unsigned int \*cap + + - Pointer to a location where to store the capability information. + +Description +----------- + +This ioctl call asks the video device about its decoding capabilities. +On success it returns and integer which has bits set according to the +defines in section ??. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-get-event.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-get-event.rst new file mode 100644 index 000000000..90382bc36 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-get-event.rst @@ -0,0 +1,105 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_GET_EVENT: + +=============== +VIDEO_GET_EVENT +=============== + +Name +---- + +VIDEO_GET_EVENT + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_GET_EVENT + +``int ioctl(fd, VIDEO_GET_EVENT, struct video_event *ev)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_GET_EVENT for this command. + + - .. row 3 + + - struct video_event \*ev + + - Points to the location where the event, if any, is to be stored. + +Description +----------- + +This ioctl is for Digital TV devices only. To get events from a V4L2 decoder +use the V4L2 :ref:`VIDIOC_DQEVENT` ioctl instead. + +This ioctl call returns an event of type video_event if available. If +an event is not available, the behavior depends on whether the device is +in blocking or non-blocking mode. In the latter case, the call fails +immediately with errno set to ``EWOULDBLOCK``. In the former case, the call +blocks until an event becomes available. The standard Linux poll() +and/or select() system calls can be used with the device file descriptor +to watch for new events. For select(), the file descriptor should be +included in the exceptfds argument, and for poll(), POLLPRI should be +specified as the wake-up condition. Read-only permissions are sufficient +for this ioctl call. + +.. c:type:: video_event + +.. code-block:: c + + struct video_event { + __s32 type; + #define VIDEO_EVENT_SIZE_CHANGED 1 + #define VIDEO_EVENT_FRAME_RATE_CHANGED 2 + #define VIDEO_EVENT_DECODER_STOPPED 3 + #define VIDEO_EVENT_VSYNC 4 + long timestamp; + union { + video_size_t size; + unsigned int frame_rate; /* in frames per 1000sec */ + unsigned char vsync_field; /* unknown/odd/even/progressive */ + } u; + }; + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EWOULDBLOCK`` + + - There is no event pending, and the device is in non-blocking mode. + + - .. row 2 + + - ``EOVERFLOW`` + + - Overflow in event queue - one or more events were lost. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-get-frame-count.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-get-frame-count.rst new file mode 100644 index 000000000..b48ac8c58 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-get-frame-count.rst @@ -0,0 +1,65 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_GET_FRAME_COUNT: + +===================== +VIDEO_GET_FRAME_COUNT +===================== + +Name +---- + +VIDEO_GET_FRAME_COUNT + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_GET_FRAME_COUNT + +``int ioctl(int fd, VIDEO_GET_FRAME_COUNT, __u64 *pts)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_GET_FRAME_COUNT for this command. + + - .. row 3 + + - __u64 \*pts + + - Returns the number of frames displayed since the decoder was + started. + +Description +----------- + +This ioctl is obsolete. Do not use in new drivers. For V4L2 decoders +this ioctl has been replaced by the ``V4L2_CID_MPEG_VIDEO_DEC_FRAME`` +control. + +This ioctl call asks the Video Device to return the number of displayed +frames since the decoder was started. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-get-pts.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-get-pts.rst new file mode 100644 index 000000000..fedaff41b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-get-pts.rst @@ -0,0 +1,69 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_GET_PTS: + +============= +VIDEO_GET_PTS +============= + +Name +---- + +VIDEO_GET_PTS + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_GET_PTS + +``int ioctl(int fd, VIDEO_GET_PTS, __u64 *pts)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_GET_PTS for this command. + + - .. row 3 + + - __u64 \*pts + + - Returns the 33-bit timestamp as defined in ITU T-REC-H.222.0 / + ISO/IEC 13818-1. + + The PTS should belong to the currently played frame if possible, + but may also be a value close to it like the PTS of the last + decoded frame or the last PTS extracted by the PES parser. + +Description +----------- + +This ioctl is obsolete. Do not use in new drivers. For V4L2 decoders +this ioctl has been replaced by the ``V4L2_CID_MPEG_VIDEO_DEC_PTS`` +control. + +This ioctl call asks the Video Device to return the current PTS +timestamp. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-get-size.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-get-size.rst new file mode 100644 index 000000000..de34331c5 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-get-size.rst @@ -0,0 +1,69 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_GET_SIZE: + +============== +VIDEO_GET_SIZE +============== + +Name +---- + +VIDEO_GET_SIZE + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_GET_SIZE + +``int ioctl(int fd, VIDEO_GET_SIZE, video_size_t *size)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_GET_SIZE for this command. + + - .. row 3 + + - video_size_t \*size + + - Returns the size and aspect ratio. + +Description +----------- + +This ioctl returns the size and aspect ratio. + +.. c:type:: video_size_t + +.. code-block::c + + typedef struct { + int w; + int h; + video_format_t aspect_ratio; + } video_size_t; + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-get-status.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-get-status.rst new file mode 100644 index 000000000..9b86fbf41 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-get-status.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_GET_STATUS: + +================ +VIDEO_GET_STATUS +================ + +Name +---- + +VIDEO_GET_STATUS + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_GET_STATUS + +``int ioctl(fd, VIDEO_GET_STATUS, struct video_status *status)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_GET_STATUS for this command. + + - .. row 3 + + - struct video_status \*status + + - Returns the current status of the Video Device. + +Description +----------- + +This ioctl call asks the Video Device to return the current status of +the device. + +.. c:type:: video_status + +.. code-block:: c + + struct video_status { + int video_blank; /* blank video on freeze? */ + video_play_state_t play_state; /* current state of playback */ + video_stream_source_t stream_source; /* current source (demux/memory) */ + video_format_t video_format; /* current aspect ratio of stream*/ + video_displayformat_t display_format;/* selected cropping mode */ + }; + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-play.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-play.rst new file mode 100644 index 000000000..35ac8b98f --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-play.rst @@ -0,0 +1,57 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_PLAY: + +========== +VIDEO_PLAY +========== + +Name +---- + +VIDEO_PLAY + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_PLAY + +``int ioctl(fd, VIDEO_PLAY)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_PLAY for this command. + +Description +----------- + +This ioctl is for Digital TV devices only. To control a V4L2 decoder use the +V4L2 :ref:`VIDIOC_DECODER_CMD` instead. + +This ioctl call asks the Video Device to start playing a video stream +from the selected source. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-select-source.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-select-source.rst new file mode 100644 index 000000000..929a20985 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-select-source.rst @@ -0,0 +1,76 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_SELECT_SOURCE: + +=================== +VIDEO_SELECT_SOURCE +=================== + +Name +---- + +VIDEO_SELECT_SOURCE + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_SELECT_SOURCE + +``int ioctl(fd, VIDEO_SELECT_SOURCE, video_stream_source_t source)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_SELECT_SOURCE for this command. + + - .. row 3 + + - video_stream_source_t source + + - Indicates which source shall be used for the Video stream. + +Description +----------- + +This ioctl is for Digital TV devices only. This ioctl was also supported by the +V4L2 ivtv driver, but that has been replaced by the ivtv-specific +``IVTV_IOC_PASSTHROUGH_MODE`` ioctl. + +This ioctl call informs the video device which source shall be used for +the input data. The possible sources are demux or memory. If memory is +selected, the data is fed to the video device through the write command. + +.. c:type:: video_stream_source_t + +.. code-block:: c + + typedef enum { + VIDEO_SOURCE_DEMUX, /* Select the demux as the main source */ + VIDEO_SOURCE_MEMORY /* If this source is selected, the stream + comes from the user through the write + system call */ + } video_stream_source_t; + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-set-blank.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-set-blank.rst new file mode 100644 index 000000000..70249a6ba --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-set-blank.rst @@ -0,0 +1,64 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_SET_BLANK: + +=============== +VIDEO_SET_BLANK +=============== + +Name +---- + +VIDEO_SET_BLANK + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_SET_BLANK + +``int ioctl(fd, VIDEO_SET_BLANK, boolean mode)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_SET_BLANK for this command. + + - .. row 3 + + - boolean mode + + - TRUE: Blank screen when stop. + + - .. row 4 + + - + - FALSE: Show last decoded frame. + +Description +----------- + +This ioctl call asks the Video Device to blank out the picture. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-set-display-format.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-set-display-format.rst new file mode 100644 index 000000000..1de4f40ae --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-set-display-format.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_SET_DISPLAY_FORMAT: + +======================== +VIDEO_SET_DISPLAY_FORMAT +======================== + +Name +---- + +VIDEO_SET_DISPLAY_FORMAT + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_SET_DISPLAY_FORMAT + +``int ioctl(fd, VIDEO_SET_DISPLAY_FORMAT)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_SET_DISPLAY_FORMAT for this command. + + - .. row 3 + + - video_display_format_t format + + - Selects the video format to be used. + +Description +----------- + +This ioctl call asks the Video Device to select the video format to be +applied by the MPEG chip on the video. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-set-format.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-set-format.rst new file mode 100644 index 000000000..bb64e37ae --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-set-format.rst @@ -0,0 +1,82 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_SET_FORMAT: + +================ +VIDEO_SET_FORMAT +================ + +Name +---- + +VIDEO_SET_FORMAT + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_SET_FORMAT + +``int ioctl(fd, VIDEO_SET_FORMAT, video_format_t format)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_SET_FORMAT for this command. + + - .. row 3 + + - video_format_t format + + - video format of TV as defined in section ??. + +Description +----------- + +This ioctl sets the screen format (aspect ratio) of the connected output +device (TV) so that the output of the decoder can be adjusted +accordingly. + +.. c:type:: video_format_t + +.. code-block:: c + + typedef enum { + VIDEO_FORMAT_4_3, /* Select 4:3 format */ + VIDEO_FORMAT_16_9, /* Select 16:9 format. */ + VIDEO_FORMAT_221_1 /* 2.21:1 */ + } video_format_t; + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. + + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EINVAL`` + + - format is not a valid video format. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-set-streamtype.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-set-streamtype.rst new file mode 100644 index 000000000..1f31c048b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-set-streamtype.rst @@ -0,0 +1,61 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_SET_STREAMTYPE: + +==================== +VIDEO_SET_STREAMTYPE +==================== + +Name +---- + +VIDEO_SET_STREAMTYPE + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_SET_STREAMTYPE + +``int ioctl(fd, VIDEO_SET_STREAMTYPE, int type)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_SET_STREAMTYPE for this command. + + - .. row 3 + + - int type + + - stream type + +Description +----------- + +This ioctl tells the driver which kind of stream to expect being written +to it. If this call is not used the default of video PES is used. Some +drivers might not support this call and always expect PES. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-slowmotion.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-slowmotion.rst new file mode 100644 index 000000000..1478fcc30 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-slowmotion.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_SLOWMOTION: + +================ +VIDEO_SLOWMOTION +================ + +Name +---- + +VIDEO_SLOWMOTION + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_SLOWMOTION + +``int ioctl(fd, VIDEO_SLOWMOTION, int nFrames)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_SLOWMOTION for this command. + + - .. row 3 + + - int nFrames + + - The number of times to repeat each frame. + +Description +----------- + +This ioctl call asks the video device to repeat decoding frames N number +of times. This call can only be used if VIDEO_SOURCE_MEMORY is +selected. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. + + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - ``EPERM`` + + - Mode VIDEO_SOURCE_MEMORY not selected. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-stillpicture.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-stillpicture.rst new file mode 100644 index 000000000..d25384222 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-stillpicture.rst @@ -0,0 +1,61 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_STILLPICTURE: + +================== +VIDEO_STILLPICTURE +================== + +Name +---- + +VIDEO_STILLPICTURE + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_STILLPICTURE + +``int ioctl(fd, VIDEO_STILLPICTURE, struct video_still_picture *sp)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_STILLPICTURE for this command. + + - .. row 3 + + - struct video_still_picture \*sp + + - Pointer to a location where an I-frame and size is stored. + +Description +----------- + +This ioctl call asks the Video Device to display a still picture +(I-frame). The input data shall contain an I-frame. If the pointer is +NULL, then the current displayed still picture is blanked. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-stop.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-stop.rst new file mode 100644 index 000000000..96f61c5b4 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-stop.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_STOP: + +========== +VIDEO_STOP +========== + +Name +---- + +VIDEO_STOP + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_STOP + +``int ioctl(fd, VIDEO_STOP, boolean mode)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_STOP for this command. + + - .. row 3 + + - Boolean mode + + - Indicates how the screen shall be handled. + + - .. row 4 + + - + - TRUE: Blank screen when stop. + + - .. row 5 + + - + - FALSE: Show last decoded frame. + +Description +----------- + +This ioctl is for Digital TV devices only. To control a V4L2 decoder use the +V4L2 :ref:`VIDIOC_DECODER_CMD` instead. + +This ioctl call asks the Video Device to stop playing the current +stream. Depending on the input parameter, the screen can be blanked out +or displaying the last decoded frame. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video-try-command.rst b/drivers/staging/media/deprecated/saa7146/av7110/video-try-command.rst new file mode 100644 index 000000000..79bf3dfb8 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video-try-command.rst @@ -0,0 +1,66 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later +.. c:namespace:: DTV.video + +.. _VIDEO_TRY_COMMAND: + +================= +VIDEO_TRY_COMMAND +================= + +Name +---- + +VIDEO_TRY_COMMAND + +.. attention:: This ioctl is deprecated. + +Synopsis +-------- + +.. c:macro:: VIDEO_TRY_COMMAND + +``int ioctl(int fd, VIDEO_TRY_COMMAND, struct video_command *cmd)`` + +Arguments +--------- + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + - .. row 1 + + - int fd + + - File descriptor returned by a previous call to open(). + + - .. row 2 + + - int request + + - Equals VIDEO_TRY_COMMAND for this command. + + - .. row 3 + + - struct video_command \*cmd + + - Try a decoder command. + +Description +----------- + +This ioctl is obsolete. Do not use in new drivers. For V4L2 decoders +this ioctl has been replaced by the +:ref:`VIDIOC_TRY_DECODER_CMD ` ioctl. + +This ioctl tries a decoder command. The ``video_command`` struct is a +subset of the ``v4l2_decoder_cmd`` struct, so refer to the +:ref:`VIDIOC_TRY_DECODER_CMD ` documentation +for more information. + +Return Value +------------ + +On success 0 is returned, on error -1 and the ``errno`` variable is set +appropriately. The generic error codes are described at the +:ref:`Generic Error Codes ` chapter. diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video.rst b/drivers/staging/media/deprecated/saa7146/av7110/video.rst new file mode 100644 index 000000000..808705b76 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video.rst @@ -0,0 +1,36 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later + +.. _dvb_video: + +####################### +Digital TV Video Device +####################### + +The Digital TV video device controls the MPEG2 video decoder of the Digital +TV hardware. It can be accessed through **/dev/dvb/adapter0/video0**. Data +types and ioctl definitions can be accessed by including +**linux/dvb/video.h** in your application. + +Note that the Digital TV video device only controls decoding of the MPEG video +stream, not its presentation on the TV or computer screen. On PCs this +is typically handled by an associated video4linux device, e.g. +**/dev/video**, which allows scaling and defining output windows. + +Some Digital TV cards don't have their own MPEG decoder, which results in the +omission of the audio and video device as well as the video4linux +device. + +The ioctls that deal with SPUs (sub picture units) and navigation +packets are only supported on some MPEG decoders made for DVD playback. + +These ioctls were also used by V4L2 to control MPEG decoders implemented +in V4L2. The use of these ioctls for that purpose has been made obsolete +and proper V4L2 ioctls or controls have been created to replace that +functionality. + + +.. toctree:: + :maxdepth: 1 + + video_types + video_function_calls diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video_function_calls.rst b/drivers/staging/media/deprecated/saa7146/av7110/video_function_calls.rst new file mode 100644 index 000000000..20a897be5 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video_function_calls.rst @@ -0,0 +1,35 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later + +.. _video_function_calls: + +******************** +Video Function Calls +******************** + +.. toctree:: + :maxdepth: 1 + + video-fopen + video-fclose + video-fwrite + video-stop + video-play + video-freeze + video-continue + video-select-source + video-set-blank + video-get-status + video-get-frame-count + video-get-pts + video-get-event + video-command + video-try-command + video-get-size + video-set-display-format + video-stillpicture + video-fast-forward + video-slowmotion + video-get-capabilities + video-clear-buffer + video-set-streamtype + video-set-format diff --git a/drivers/staging/media/deprecated/saa7146/av7110/video_types.rst b/drivers/staging/media/deprecated/saa7146/av7110/video_types.rst new file mode 100644 index 000000000..c4557d328 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/av7110/video_types.rst @@ -0,0 +1,248 @@ +.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later + +.. _video_types: + +**************** +Video Data Types +**************** + + +.. _video-format-t: + +video_format_t +============== + +The ``video_format_t`` data type defined by + + +.. code-block:: c + + typedef enum { + VIDEO_FORMAT_4_3, /* Select 4:3 format */ + VIDEO_FORMAT_16_9, /* Select 16:9 format. */ + VIDEO_FORMAT_221_1 /* 2.21:1 */ + } video_format_t; + +is used in the VIDEO_SET_FORMAT function (??) to tell the driver which +aspect ratio the output hardware (e.g. TV) has. It is also used in the +data structures video_status (??) returned by VIDEO_GET_STATUS (??) +and video_event (??) returned by VIDEO_GET_EVENT (??) which report +about the display format of the current video stream. + + +.. _video-displayformat-t: + +video_displayformat_t +===================== + +In case the display format of the video stream and of the display +hardware differ the application has to specify how to handle the +cropping of the picture. This can be done using the +VIDEO_SET_DISPLAY_FORMAT call (??) which accepts + + +.. code-block:: c + + typedef enum { + VIDEO_PAN_SCAN, /* use pan and scan format */ + VIDEO_LETTER_BOX, /* use letterbox format */ + VIDEO_CENTER_CUT_OUT /* use center cut out format */ + } video_displayformat_t; + +as argument. + + +.. _video-stream-source-t: + +video_stream_source_t +===================== + +The video stream source is set through the VIDEO_SELECT_SOURCE call +and can take the following values, depending on whether we are replaying +from an internal (demuxer) or external (user write) source. + + +.. code-block:: c + + typedef enum { + VIDEO_SOURCE_DEMUX, /* Select the demux as the main source */ + VIDEO_SOURCE_MEMORY /* If this source is selected, the stream + comes from the user through the write + system call */ + } video_stream_source_t; + +VIDEO_SOURCE_DEMUX selects the demultiplexer (fed either by the +frontend or the DVR device) as the source of the video stream. If +VIDEO_SOURCE_MEMORY is selected the stream comes from the application +through the **write()** system call. + + +.. _video-play-state-t: + +video_play_state_t +================== + +The following values can be returned by the VIDEO_GET_STATUS call +representing the state of video playback. + + +.. code-block:: c + + typedef enum { + VIDEO_STOPPED, /* Video is stopped */ + VIDEO_PLAYING, /* Video is currently playing */ + VIDEO_FREEZED /* Video is freezed */ + } video_play_state_t; + + +.. c:type:: video_command + +struct video_command +==================== + +The structure must be zeroed before use by the application This ensures +it can be extended safely in the future. + + +.. code-block:: c + + struct video_command { + __u32 cmd; + __u32 flags; + union { + struct { + __u64 pts; + } stop; + + struct { + /* 0 or 1000 specifies normal speed, + 1 specifies forward single stepping, + -1 specifies backward single stepping, + >>1: playback at speed/1000 of the normal speed, + <-1: reverse playback at (-speed/1000) of the normal speed. */ + __s32 speed; + __u32 format; + } play; + + struct { + __u32 data[16]; + } raw; + }; + }; + + +.. _video-size-t: + +video_size_t +============ + + +.. code-block:: c + + typedef struct { + int w; + int h; + video_format_t aspect_ratio; + } video_size_t; + + +.. c:type:: video_event + +struct video_event +================== + +The following is the structure of a video event as it is returned by the +VIDEO_GET_EVENT call. + + +.. code-block:: c + + struct video_event { + __s32 type; + #define VIDEO_EVENT_SIZE_CHANGED 1 + #define VIDEO_EVENT_FRAME_RATE_CHANGED 2 + #define VIDEO_EVENT_DECODER_STOPPED 3 + #define VIDEO_EVENT_VSYNC 4 + long timestamp; + union { + video_size_t size; + unsigned int frame_rate; /* in frames per 1000sec */ + unsigned char vsync_field; /* unknown/odd/even/progressive */ + } u; + }; + + +.. c:type:: video_status + +struct video_status +=================== + +The VIDEO_GET_STATUS call returns the following structure informing +about various states of the playback operation. + + +.. code-block:: c + + struct video_status { + int video_blank; /* blank video on freeze? */ + video_play_state_t play_state; /* current state of playback */ + video_stream_source_t stream_source; /* current source (demux/memory) */ + video_format_t video_format; /* current aspect ratio of stream */ + video_displayformat_t display_format;/* selected cropping mode */ + }; + +If video_blank is set video will be blanked out if the channel is +changed or if playback is stopped. Otherwise, the last picture will be +displayed. play_state indicates if the video is currently frozen, +stopped, or being played back. The stream_source corresponds to the +selected source for the video stream. It can come either from the +demultiplexer or from memory. The video_format indicates the aspect +ratio (one of 4:3 or 16:9) of the currently played video stream. +Finally, display_format corresponds to the selected cropping mode in +case the source video format is not the same as the format of the output +device. + + +.. c:type:: video_still_picture + +struct video_still_picture +========================== + +An I-frame displayed via the VIDEO_STILLPICTURE call is passed on +within the following structure. + + +.. code-block:: c + + /* pointer to and size of a single iframe in memory */ + struct video_still_picture { + char *iFrame; /* pointer to a single iframe in memory */ + int32_t size; + }; + + +.. _video_caps: + +video capabilities +================== + +A call to VIDEO_GET_CAPABILITIES returns an unsigned integer with the +following bits set according to the hardwares capabilities. + + +.. code-block:: c + + /* bit definitions for capabilities: */ + /* can the hardware decode MPEG1 and/or MPEG2? */ + #define VIDEO_CAP_MPEG1 1 + #define VIDEO_CAP_MPEG2 2 + /* can you send a system and/or program stream to video device? + (you still have to open the video and the audio device but only + send the stream to the video device) */ + #define VIDEO_CAP_SYS 4 + #define VIDEO_CAP_PROG 8 + /* can the driver also handle SPU, NAVI and CSS encoded data? + (CSS API is not present yet) */ + #define VIDEO_CAP_SPU 16 + #define VIDEO_CAP_NAVI 32 + #define VIDEO_CAP_CSS 64 diff --git a/drivers/staging/media/deprecated/saa7146/common/Kconfig b/drivers/staging/media/deprecated/saa7146/common/Kconfig new file mode 100644 index 000000000..a0aa155e5 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_SAA7146 + tristate + depends on I2C && PCI + +config VIDEO_SAA7146_VV + tristate + depends on VIDEO_DEV + select VIDEOBUF_DMA_SG + select VIDEO_SAA7146 diff --git a/drivers/staging/media/deprecated/saa7146/common/Makefile b/drivers/staging/media/deprecated/saa7146/common/Makefile new file mode 100644 index 000000000..2a6337fea --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +saa7146-objs := saa7146_i2c.o saa7146_core.o +saa7146_vv-objs := saa7146_fops.o saa7146_video.o saa7146_hlp.o saa7146_vbi.o + +obj-$(CONFIG_VIDEO_SAA7146) += saa7146.o +obj-$(CONFIG_VIDEO_SAA7146_VV) += saa7146_vv.o diff --git a/drivers/staging/media/deprecated/saa7146/common/saa7146.h b/drivers/staging/media/deprecated/saa7146/common/saa7146.h new file mode 100644 index 000000000..71ce63c99 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/saa7146.h @@ -0,0 +1,472 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SAA7146__ +#define __SAA7146__ + +#include /* for delay-stuff */ +#include /* for kmalloc/kfree */ +#include /* for pci-config-stuff, vendor ids etc. */ +#include /* for "__init" */ +#include /* for IMMEDIATE_BH */ +#include /* for kernel module loader */ +#include /* for i2c subsystem */ +#include /* for accessing devices */ +#include +#include +#include +#include +#include + +#include /* for vmalloc() */ +#include /* for vmalloc_to_page() */ + +#define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr))) +#define saa7146_read(sxy,adr) readl(sxy->mem+(adr)) + +extern unsigned int saa7146_debug; + +#ifndef DEBUG_VARIABLE + #define DEBUG_VARIABLE saa7146_debug +#endif + +#define ERR(fmt, ...) pr_err("%s: " fmt, __func__, ##__VA_ARGS__) + +#define _DBG(mask, fmt, ...) \ +do { \ + if (DEBUG_VARIABLE & mask) \ + pr_debug("%s(): " fmt, __func__, ##__VA_ARGS__); \ +} while (0) + +/* simple debug messages */ +#define DEB_S(fmt, ...) _DBG(0x01, fmt, ##__VA_ARGS__) +/* more detailed debug messages */ +#define DEB_D(fmt, ...) _DBG(0x02, fmt, ##__VA_ARGS__) +/* print enter and exit of functions */ +#define DEB_EE(fmt, ...) _DBG(0x04, fmt, ##__VA_ARGS__) +/* i2c debug messages */ +#define DEB_I2C(fmt, ...) _DBG(0x08, fmt, ##__VA_ARGS__) +/* vbi debug messages */ +#define DEB_VBI(fmt, ...) _DBG(0x10, fmt, ##__VA_ARGS__) +/* interrupt debug messages */ +#define DEB_INT(fmt, ...) _DBG(0x20, fmt, ##__VA_ARGS__) +/* capture debug messages */ +#define DEB_CAP(fmt, ...) _DBG(0x40, fmt, ##__VA_ARGS__) + +#define SAA7146_ISR_CLEAR(x,y) \ + saa7146_write(x, ISR, (y)); + +struct module; + +struct saa7146_dev; +struct saa7146_extension; +struct saa7146_vv; + +/* saa7146 page table */ +struct saa7146_pgtable { + unsigned int size; + __le32 *cpu; + dma_addr_t dma; + /* used for offsets for u,v planes for planar capture modes */ + unsigned long offset; + /* used for custom pagetables (used for example by budget dvb cards) */ + struct scatterlist *slist; + int nents; +}; + +struct saa7146_pci_extension_data { + struct saa7146_extension *ext; + void *ext_priv; /* most likely a name string */ +}; + +#define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \ + { \ + .vendor = PCI_VENDOR_ID_PHILIPS, \ + .device = PCI_DEVICE_ID_PHILIPS_SAA7146, \ + .subvendor = x_vendor, \ + .subdevice = x_device, \ + .driver_data = (unsigned long)& x_var, \ + } + +struct saa7146_extension +{ + char name[32]; /* name of the device */ +#define SAA7146_USE_I2C_IRQ 0x1 +#define SAA7146_I2C_SHORT_DELAY 0x2 + int flags; + + /* pairs of subvendor and subdevice ids for + supported devices, last entry 0xffff, 0xfff */ + struct module *module; + struct pci_driver driver; + const struct pci_device_id *pci_tbl; + + /* extension functions */ + int (*probe)(struct saa7146_dev *); + int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *); + int (*detach)(struct saa7146_dev*); + + u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */ + void (*irq_func)(struct saa7146_dev*, u32* irq_mask); +}; + +struct saa7146_dma +{ + dma_addr_t dma_handle; + __le32 *cpu_addr; +}; + +struct saa7146_dev +{ + struct module *module; + + struct v4l2_device v4l2_dev; + struct v4l2_ctrl_handler ctrl_handler; + + /* different device locks */ + spinlock_t slock; + struct mutex v4l2_lock; + + unsigned char __iomem *mem; /* pointer to mapped IO memory */ + u32 revision; /* chip revision; needed for bug-workarounds*/ + + /* pci-device & irq stuff*/ + char name[32]; + struct pci_dev *pci; + u32 int_todo; + spinlock_t int_slock; + + /* extension handling */ + struct saa7146_extension *ext; /* indicates if handled by extension */ + void *ext_priv; /* pointer for extension private use (most likely some private data) */ + struct saa7146_ext_vv *ext_vv_data; + + /* per device video/vbi information (if available) */ + struct saa7146_vv *vv_data; + void (*vv_callback)(struct saa7146_dev *dev, unsigned long status); + + /* i2c-stuff */ + struct mutex i2c_lock; + + u32 i2c_bitrate; + struct saa7146_dma d_i2c; /* pointer to i2c memory */ + wait_queue_head_t i2c_wq; + int i2c_op; + + /* memories */ + struct saa7146_dma d_rps0; + struct saa7146_dma d_rps1; +}; + +static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev) +{ + return container_of(v4l2_dev, struct saa7146_dev, v4l2_dev); +} + +/* from saa7146_i2c.c */ +int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); + +/* from saa7146_core.c */ +int saa7146_register_extension(struct saa7146_extension*); +int saa7146_unregister_extension(struct saa7146_extension*); +struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc); +int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt); +void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt); +int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length ); +void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); +void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt); +void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data); +int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop); + +/* some memory sizes */ +#define SAA7146_I2C_MEM ( 1*PAGE_SIZE) +#define SAA7146_RPS_MEM ( 1*PAGE_SIZE) + +/* some i2c constants */ +#define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */ +#define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */ +#define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */ + +/* unsorted defines */ +#define ME1 0x0000000800 +#define PV1 0x0000000008 + +/* gpio defines */ +#define SAA7146_GPIO_INPUT 0x00 +#define SAA7146_GPIO_IRQHI 0x10 +#define SAA7146_GPIO_IRQLO 0x20 +#define SAA7146_GPIO_IRQHL 0x30 +#define SAA7146_GPIO_OUTLO 0x40 +#define SAA7146_GPIO_OUTHI 0x50 + +/* debi defines */ +#define DEBINOSWAP 0x000e0000 + +/* define for the register programming sequencer (rps) */ +#define CMD_NOP 0x00000000 /* No operation */ +#define CMD_CLR_EVENT 0x00000000 /* Clear event */ +#define CMD_SET_EVENT 0x10000000 /* Set signal event */ +#define CMD_PAUSE 0x20000000 /* Pause */ +#define CMD_CHECK_LATE 0x30000000 /* Check late */ +#define CMD_UPLOAD 0x40000000 /* Upload */ +#define CMD_STOP 0x50000000 /* Stop */ +#define CMD_INTERRUPT 0x60000000 /* Interrupt */ +#define CMD_JUMP 0x80000000 /* Jump */ +#define CMD_WR_REG 0x90000000 /* Write (load) register */ +#define CMD_RD_REG 0xa0000000 /* Read (store) register */ +#define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */ + +#define CMD_OAN MASK_27 +#define CMD_INV MASK_26 +#define CMD_SIG4 MASK_25 +#define CMD_SIG3 MASK_24 +#define CMD_SIG2 MASK_23 +#define CMD_SIG1 MASK_22 +#define CMD_SIG0 MASK_21 +#define CMD_O_FID_B MASK_14 +#define CMD_E_FID_B MASK_13 +#define CMD_O_FID_A MASK_12 +#define CMD_E_FID_A MASK_11 + +/* some events and command modifiers for rps1 squarewave generator */ +#define EVT_HS (1<<15) // Source Line Threshold reached +#define EVT_VBI_B (1<<9) // VSYNC Event +#define RPS_OAN (1<<27) // 1: OR events, 0: AND events +#define RPS_INV (1<<26) // Invert (compound) event +#define GPIO3_MSK 0xFF000000 // GPIO #3 control bits + +/* Bit mask constants */ +#define MASK_00 0x00000001 /* Mask value for bit 0 */ +#define MASK_01 0x00000002 /* Mask value for bit 1 */ +#define MASK_02 0x00000004 /* Mask value for bit 2 */ +#define MASK_03 0x00000008 /* Mask value for bit 3 */ +#define MASK_04 0x00000010 /* Mask value for bit 4 */ +#define MASK_05 0x00000020 /* Mask value for bit 5 */ +#define MASK_06 0x00000040 /* Mask value for bit 6 */ +#define MASK_07 0x00000080 /* Mask value for bit 7 */ +#define MASK_08 0x00000100 /* Mask value for bit 8 */ +#define MASK_09 0x00000200 /* Mask value for bit 9 */ +#define MASK_10 0x00000400 /* Mask value for bit 10 */ +#define MASK_11 0x00000800 /* Mask value for bit 11 */ +#define MASK_12 0x00001000 /* Mask value for bit 12 */ +#define MASK_13 0x00002000 /* Mask value for bit 13 */ +#define MASK_14 0x00004000 /* Mask value for bit 14 */ +#define MASK_15 0x00008000 /* Mask value for bit 15 */ +#define MASK_16 0x00010000 /* Mask value for bit 16 */ +#define MASK_17 0x00020000 /* Mask value for bit 17 */ +#define MASK_18 0x00040000 /* Mask value for bit 18 */ +#define MASK_19 0x00080000 /* Mask value for bit 19 */ +#define MASK_20 0x00100000 /* Mask value for bit 20 */ +#define MASK_21 0x00200000 /* Mask value for bit 21 */ +#define MASK_22 0x00400000 /* Mask value for bit 22 */ +#define MASK_23 0x00800000 /* Mask value for bit 23 */ +#define MASK_24 0x01000000 /* Mask value for bit 24 */ +#define MASK_25 0x02000000 /* Mask value for bit 25 */ +#define MASK_26 0x04000000 /* Mask value for bit 26 */ +#define MASK_27 0x08000000 /* Mask value for bit 27 */ +#define MASK_28 0x10000000 /* Mask value for bit 28 */ +#define MASK_29 0x20000000 /* Mask value for bit 29 */ +#define MASK_30 0x40000000 /* Mask value for bit 30 */ +#define MASK_31 0x80000000 /* Mask value for bit 31 */ + +#define MASK_B0 0x000000ff /* Mask value for byte 0 */ +#define MASK_B1 0x0000ff00 /* Mask value for byte 1 */ +#define MASK_B2 0x00ff0000 /* Mask value for byte 2 */ +#define MASK_B3 0xff000000 /* Mask value for byte 3 */ + +#define MASK_W0 0x0000ffff /* Mask value for word 0 */ +#define MASK_W1 0xffff0000 /* Mask value for word 1 */ + +#define MASK_PA 0xfffffffc /* Mask value for physical address */ +#define MASK_PR 0xfffffffe /* Mask value for protection register */ +#define MASK_ER 0xffffffff /* Mask value for the entire register */ + +#define MASK_NONE 0x00000000 /* No mask */ + +/* register aliases */ +#define BASE_ODD1 0x00 /* Video DMA 1 registers */ +#define BASE_EVEN1 0x04 +#define PROT_ADDR1 0x08 +#define PITCH1 0x0C +#define BASE_PAGE1 0x10 /* Video DMA 1 base page */ +#define NUM_LINE_BYTE1 0x14 + +#define BASE_ODD2 0x18 /* Video DMA 2 registers */ +#define BASE_EVEN2 0x1C +#define PROT_ADDR2 0x20 +#define PITCH2 0x24 +#define BASE_PAGE2 0x28 /* Video DMA 2 base page */ +#define NUM_LINE_BYTE2 0x2C + +#define BASE_ODD3 0x30 /* Video DMA 3 registers */ +#define BASE_EVEN3 0x34 +#define PROT_ADDR3 0x38 +#define PITCH3 0x3C +#define BASE_PAGE3 0x40 /* Video DMA 3 base page */ +#define NUM_LINE_BYTE3 0x44 + +#define PCI_BT_V1 0x48 /* Video/FIFO 1 */ +#define PCI_BT_V2 0x49 /* Video/FIFO 2 */ +#define PCI_BT_V3 0x4A /* Video/FIFO 3 */ +#define PCI_BT_DEBI 0x4B /* DEBI */ +#define PCI_BT_A 0x4C /* Audio */ + +#define DD1_INIT 0x50 /* Init setting of DD1 interface */ + +#define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */ +#define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */ + +#define BRS_CTRL 0x58 /* BRS control register */ +#define HPS_CTRL 0x5C /* HPS control register */ +#define HPS_V_SCALE 0x60 /* HPS vertical scale */ +#define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */ +#define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */ +#define HPS_H_SCALE 0x6C /* HPS horizontal scale */ +#define BCS_CTRL 0x70 /* BCS control */ +#define CHROMA_KEY_RANGE 0x74 +#define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */ + +#define DEBI_CONFIG 0x7C +#define DEBI_COMMAND 0x80 +#define DEBI_PAGE 0x84 +#define DEBI_AD 0x88 + +#define I2C_TRANSFER 0x8C +#define I2C_STATUS 0x90 + +#define BASE_A1_IN 0x94 /* Audio 1 input DMA */ +#define PROT_A1_IN 0x98 +#define PAGE_A1_IN 0x9C + +#define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */ +#define PROT_A1_OUT 0xA4 +#define PAGE_A1_OUT 0xA8 + +#define BASE_A2_IN 0xAC /* Audio 2 input DMA */ +#define PROT_A2_IN 0xB0 +#define PAGE_A2_IN 0xB4 + +#define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */ +#define PROT_A2_OUT 0xBC +#define PAGE_A2_OUT 0xC0 + +#define RPS_PAGE0 0xC4 /* RPS task 0 page register */ +#define RPS_PAGE1 0xC8 /* RPS task 1 page register */ + +#define RPS_THRESH0 0xCC /* HBI threshold for task 0 */ +#define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */ + +#define RPS_TOV0 0xD4 /* RPS timeout for task 0 */ +#define RPS_TOV1 0xD8 /* RPS timeout for task 1 */ + +#define IER 0xDC /* Interrupt enable register */ + +#define GPIO_CTRL 0xE0 /* GPIO 0-3 register */ + +#define EC1SSR 0xE4 /* Event cnt set 1 source select */ +#define EC2SSR 0xE8 /* Event cnt set 2 source select */ +#define ECT1R 0xEC /* Event cnt set 1 thresholds */ +#define ECT2R 0xF0 /* Event cnt set 2 thresholds */ + +#define ACON1 0xF4 +#define ACON2 0xF8 + +#define MC1 0xFC /* Main control register 1 */ +#define MC2 0x100 /* Main control register 2 */ + +#define RPS_ADDR0 0x104 /* RPS task 0 address register */ +#define RPS_ADDR1 0x108 /* RPS task 1 address register */ + +#define ISR 0x10C /* Interrupt status register */ +#define PSR 0x110 /* Primary status register */ +#define SSR 0x114 /* Secondary status register */ + +#define EC1R 0x118 /* Event counter set 1 register */ +#define EC2R 0x11C /* Event counter set 2 register */ + +#define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */ +#define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */ +#define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */ +#define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */ +#define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */ +#define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */ +#define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */ +#define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */ + +#define LEVEL_REP 0x140, +#define A_TIME_SLOT1 0x180, /* from 180 - 1BC */ +#define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */ + +/* isr masks */ +#define SPCI_PPEF 0x80000000 /* PCI parity error */ +#define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */ +#define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */ +#define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */ +#define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */ +#define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */ +#define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */ +#define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */ +#define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */ +#define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */ +#define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */ +#define SPCI_UPLD 0x00100000 /* RPS in upload */ +#define SPCI_DEBI_S 0x00080000 /* DEBI status */ +#define SPCI_DEBI_E 0x00040000 /* DEBI error */ +#define SPCI_IIC_S 0x00020000 /* I2C status */ +#define SPCI_IIC_E 0x00010000 /* I2C error */ +#define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */ +#define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */ +#define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */ +#define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */ +#define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */ +#define SPCI_V_PE 0x00000400 /* Video protection address */ +#define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */ +#define SPCI_FIDA 0x00000100 /* Field ID video port A */ +#define SPCI_FIDB 0x00000080 /* Field ID video port B */ +#define SPCI_PIN3 0x00000040 /* GPIO pin 3 */ +#define SPCI_PIN2 0x00000020 /* GPIO pin 2 */ +#define SPCI_PIN1 0x00000010 /* GPIO pin 1 */ +#define SPCI_PIN0 0x00000008 /* GPIO pin 0 */ +#define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */ +#define SPCI_EC3S 0x00000002 /* Event counter 3 */ +#define SPCI_EC0S 0x00000001 /* Event counter 0 */ + +/* i2c */ +#define SAA7146_I2C_ABORT (1<<7) +#define SAA7146_I2C_SPERR (1<<6) +#define SAA7146_I2C_APERR (1<<5) +#define SAA7146_I2C_DTERR (1<<4) +#define SAA7146_I2C_DRERR (1<<3) +#define SAA7146_I2C_AL (1<<2) +#define SAA7146_I2C_ERR (1<<1) +#define SAA7146_I2C_BUSY (1<<0) + +#define SAA7146_I2C_START (0x3) +#define SAA7146_I2C_CONT (0x2) +#define SAA7146_I2C_STOP (0x1) +#define SAA7146_I2C_NOP (0x0) + +#define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500) +#define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100) +#define SAA7146_I2C_BUS_BIT_RATE_480 (0x400) +#define SAA7146_I2C_BUS_BIT_RATE_320 (0x600) +#define SAA7146_I2C_BUS_BIT_RATE_240 (0x700) +#define SAA7146_I2C_BUS_BIT_RATE_120 (0x000) +#define SAA7146_I2C_BUS_BIT_RATE_80 (0x200) +#define SAA7146_I2C_BUS_BIT_RATE_60 (0x300) + +static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y) +{ + unsigned long flags; + spin_lock_irqsave(&x->int_slock, flags); + saa7146_write(x, IER, saa7146_read(x, IER) & ~y); + spin_unlock_irqrestore(&x->int_slock, flags); +} + +static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y) +{ + unsigned long flags; + spin_lock_irqsave(&x->int_slock, flags); + saa7146_write(x, IER, saa7146_read(x, IER) | y); + spin_unlock_irqrestore(&x->int_slock, flags); +} + +#endif diff --git a/drivers/staging/media/deprecated/saa7146/common/saa7146_core.c b/drivers/staging/media/deprecated/saa7146/common/saa7146_core.c new file mode 100644 index 000000000..da21d346b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/saa7146_core.c @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + saa7146.o - driver for generic saa7146-based hardware + + Copyright (C) 1998-2003 Michael Hunold + +*/ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include "saa7146.h" + +static int saa7146_num; + +unsigned int saa7146_debug; + +module_param(saa7146_debug, uint, 0644); +MODULE_PARM_DESC(saa7146_debug, "debug level (default: 0)"); + +#if 0 +static void dump_registers(struct saa7146_dev* dev) +{ + int i = 0; + + pr_info(" @ %li jiffies:\n", jiffies); + for (i = 0; i <= 0x148; i += 4) + pr_info("0x%03x: 0x%08x\n", i, saa7146_read(dev, i)); +} +#endif + +/**************************************************************************** + * gpio and debi helper functions + ****************************************************************************/ + +void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data) +{ + u32 value = 0; + + BUG_ON(port > 3); + + value = saa7146_read(dev, GPIO_CTRL); + value &= ~(0xff << (8*port)); + value |= (data << (8*port)); + saa7146_write(dev, GPIO_CTRL, value); +} + +/* This DEBI code is based on the saa7146 Stradis driver by Nathan Laredo */ +static inline int saa7146_wait_for_debi_done_sleep(struct saa7146_dev *dev, + unsigned long us1, unsigned long us2) +{ + unsigned long timeout; + int err; + + /* wait for registers to be programmed */ + timeout = jiffies + usecs_to_jiffies(us1); + while (1) { + err = time_after(jiffies, timeout); + if (saa7146_read(dev, MC2) & 2) + break; + if (err) { + pr_debug("%s: %s timed out while waiting for registers getting programmed\n", + dev->name, __func__); + return -ETIMEDOUT; + } + msleep(1); + } + + /* wait for transfer to complete */ + timeout = jiffies + usecs_to_jiffies(us2); + while (1) { + err = time_after(jiffies, timeout); + if (!(saa7146_read(dev, PSR) & SPCI_DEBI_S)) + break; + saa7146_read(dev, MC2); + if (err) { + DEB_S("%s: %s timed out while waiting for transfer completion\n", + dev->name, __func__); + return -ETIMEDOUT; + } + msleep(1); + } + + return 0; +} + +static inline int saa7146_wait_for_debi_done_busyloop(struct saa7146_dev *dev, + unsigned long us1, unsigned long us2) +{ + unsigned long loops; + + /* wait for registers to be programmed */ + loops = us1; + while (1) { + if (saa7146_read(dev, MC2) & 2) + break; + if (!loops--) { + pr_err("%s: %s timed out while waiting for registers getting programmed\n", + dev->name, __func__); + return -ETIMEDOUT; + } + udelay(1); + } + + /* wait for transfer to complete */ + loops = us2 / 5; + while (1) { + if (!(saa7146_read(dev, PSR) & SPCI_DEBI_S)) + break; + saa7146_read(dev, MC2); + if (!loops--) { + DEB_S("%s: %s timed out while waiting for transfer completion\n", + dev->name, __func__); + return -ETIMEDOUT; + } + udelay(5); + } + + return 0; +} + +int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop) +{ + if (nobusyloop) + return saa7146_wait_for_debi_done_sleep(dev, 50000, 250000); + else + return saa7146_wait_for_debi_done_busyloop(dev, 50000, 250000); +} + +/**************************************************************************** + * general helper functions + ****************************************************************************/ + +/* this is videobuf_vmalloc_to_sg() from videobuf-dma-sg.c + make sure virt has been allocated with vmalloc_32(), otherwise the BUG() + may be triggered on highmem machines */ +static struct scatterlist* vmalloc_to_sg(unsigned char *virt, int nr_pages) +{ + struct scatterlist *sglist; + struct page *pg; + int i; + + sglist = kmalloc_array(nr_pages, sizeof(struct scatterlist), GFP_KERNEL); + if (NULL == sglist) + return NULL; + sg_init_table(sglist, nr_pages); + for (i = 0; i < nr_pages; i++, virt += PAGE_SIZE) { + pg = vmalloc_to_page(virt); + if (NULL == pg) + goto err; + BUG_ON(PageHighMem(pg)); + sg_set_page(&sglist[i], pg, PAGE_SIZE, 0); + } + return sglist; + + err: + kfree(sglist); + return NULL; +} + +/********************************************************************************/ +/* common page table functions */ + +void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt) +{ + int pages = (length+PAGE_SIZE-1)/PAGE_SIZE; + void *mem = vmalloc_32(length); + int slen = 0; + + if (NULL == mem) + goto err_null; + + if (!(pt->slist = vmalloc_to_sg(mem, pages))) + goto err_free_mem; + + if (saa7146_pgtable_alloc(pci, pt)) + goto err_free_slist; + + pt->nents = pages; + slen = dma_map_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE); + if (0 == slen) + goto err_free_pgtable; + + if (0 != saa7146_pgtable_build_single(pci, pt, pt->slist, slen)) + goto err_unmap_sg; + + return mem; + +err_unmap_sg: + dma_unmap_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE); +err_free_pgtable: + saa7146_pgtable_free(pci, pt); +err_free_slist: + kfree(pt->slist); + pt->slist = NULL; +err_free_mem: + vfree(mem); +err_null: + return NULL; +} + +void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt) +{ + dma_unmap_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE); + saa7146_pgtable_free(pci, pt); + kfree(pt->slist); + pt->slist = NULL; + vfree(mem); +} + +void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt) +{ + if (NULL == pt->cpu) + return; + dma_free_coherent(&pci->dev, pt->size, pt->cpu, pt->dma); + pt->cpu = NULL; +} + +int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt) +{ + __le32 *cpu; + dma_addr_t dma_addr = 0; + + cpu = dma_alloc_coherent(&pci->dev, PAGE_SIZE, &dma_addr, GFP_KERNEL); + if (NULL == cpu) { + return -ENOMEM; + } + pt->size = PAGE_SIZE; + pt->cpu = cpu; + pt->dma = dma_addr; + + return 0; +} + +int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, + struct scatterlist *list, int sglen ) +{ + __le32 *ptr, fill; + int nr_pages = 0; + int i,p; + + BUG_ON(0 == sglen); + BUG_ON(list->offset > PAGE_SIZE); + + /* if we have a user buffer, the first page may not be + aligned to a page boundary. */ + pt->offset = list->offset; + + ptr = pt->cpu; + for (i = 0; i < sglen; i++, list++) { +/* + pr_debug("i:%d, adr:0x%08x, len:%d, offset:%d\n", + i, sg_dma_address(list), sg_dma_len(list), + list->offset); +*/ + for (p = 0; p * 4096 < sg_dma_len(list); p++, ptr++) { + *ptr = cpu_to_le32(sg_dma_address(list) + p * 4096); + nr_pages++; + } + } + + + /* safety; fill the page table up with the last valid page */ + fill = *(ptr-1); + for(i=nr_pages;i<1024;i++) { + *ptr++ = fill; + } + +/* + ptr = pt->cpu; + pr_debug("offset: %d\n", pt->offset); + for(i=0;i<5;i++) { + pr_debug("ptr1 %d: 0x%08x\n", i, ptr[i]); + } +*/ + return 0; +} + +/********************************************************************************/ +/* interrupt handler */ +static irqreturn_t interrupt_hw(int irq, void *dev_id) +{ + struct saa7146_dev *dev = dev_id; + u32 isr; + u32 ack_isr; + + /* read out the interrupt status register */ + ack_isr = isr = saa7146_read(dev, ISR); + + /* is this our interrupt? */ + if ( 0 == isr ) { + /* nope, some other device */ + return IRQ_NONE; + } + + if (dev->ext) { + if (dev->ext->irq_mask & isr) { + if (dev->ext->irq_func) + dev->ext->irq_func(dev, &isr); + isr &= ~dev->ext->irq_mask; + } + } + if (0 != (isr & (MASK_27))) { + DEB_INT("irq: RPS0 (0x%08x)\n", isr); + if (dev->vv_data && dev->vv_callback) + dev->vv_callback(dev,isr); + isr &= ~MASK_27; + } + if (0 != (isr & (MASK_28))) { + if (dev->vv_data && dev->vv_callback) + dev->vv_callback(dev,isr); + isr &= ~MASK_28; + } + if (0 != (isr & (MASK_16|MASK_17))) { + SAA7146_IER_DISABLE(dev, MASK_16|MASK_17); + /* only wake up if we expect something */ + if (0 != dev->i2c_op) { + dev->i2c_op = 0; + wake_up(&dev->i2c_wq); + } else { + u32 psr = saa7146_read(dev, PSR); + u32 ssr = saa7146_read(dev, SSR); + pr_warn("%s: unexpected i2c irq: isr %08x psr %08x ssr %08x\n", + dev->name, isr, psr, ssr); + } + isr &= ~(MASK_16|MASK_17); + } + if( 0 != isr ) { + ERR("warning: interrupt enabled, but not handled properly.(0x%08x)\n", + isr); + ERR("disabling interrupt source(s)!\n"); + SAA7146_IER_DISABLE(dev,isr); + } + saa7146_write(dev, ISR, ack_isr); + return IRQ_HANDLED; +} + +/*********************************************************************************/ +/* configuration-functions */ + +static int saa7146_init_one(struct pci_dev *pci, const struct pci_device_id *ent) +{ + struct saa7146_pci_extension_data *pci_ext = (struct saa7146_pci_extension_data *)ent->driver_data; + struct saa7146_extension *ext = pci_ext->ext; + struct saa7146_dev *dev; + int err = -ENOMEM; + + /* clear out mem for sure */ + dev = kzalloc(sizeof(struct saa7146_dev), GFP_KERNEL); + if (!dev) { + ERR("out of memory\n"); + goto out; + } + + /* create a nice device name */ + sprintf(dev->name, "saa7146 (%d)", saa7146_num); + + DEB_EE("pci:%p\n", pci); + + err = pci_enable_device(pci); + if (err < 0) { + ERR("pci_enable_device() failed\n"); + goto err_free; + } + + /* enable bus-mastering */ + pci_set_master(pci); + + dev->pci = pci; + + /* get chip-revision; this is needed to enable bug-fixes */ + dev->revision = pci->revision; + + /* remap the memory from virtual to physical address */ + + err = pci_request_region(pci, 0, "saa7146"); + if (err < 0) + goto err_disable; + + dev->mem = ioremap(pci_resource_start(pci, 0), + pci_resource_len(pci, 0)); + if (!dev->mem) { + ERR("ioremap() failed\n"); + err = -ENODEV; + goto err_release; + } + + /* we don't do a master reset here anymore, it screws up + some boards that don't have an i2c-eeprom for configuration + values */ +/* + saa7146_write(dev, MC1, MASK_31); +*/ + + /* disable all irqs */ + saa7146_write(dev, IER, 0); + + /* shut down all dma transfers and rps tasks */ + saa7146_write(dev, MC1, 0x30ff0000); + + /* clear out any rps-signals pending */ + saa7146_write(dev, MC2, 0xf8000000); + + /* request an interrupt for the saa7146 */ + err = request_irq(pci->irq, interrupt_hw, IRQF_SHARED, + dev->name, dev); + if (err < 0) { + ERR("request_irq() failed\n"); + goto err_unmap; + } + + err = -ENOMEM; + + /* get memory for various stuff */ + dev->d_rps0.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM, + &dev->d_rps0.dma_handle, + GFP_KERNEL); + if (!dev->d_rps0.cpu_addr) + goto err_free_irq; + + dev->d_rps1.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM, + &dev->d_rps1.dma_handle, + GFP_KERNEL); + if (!dev->d_rps1.cpu_addr) + goto err_free_rps0; + + dev->d_i2c.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM, + &dev->d_i2c.dma_handle, GFP_KERNEL); + if (!dev->d_i2c.cpu_addr) + goto err_free_rps1; + + /* the rest + print status message */ + + pr_info("found saa7146 @ mem %p (revision %d, irq %d) (0x%04x,0x%04x)\n", + dev->mem, dev->revision, pci->irq, + pci->subsystem_vendor, pci->subsystem_device); + dev->ext = ext; + + mutex_init(&dev->v4l2_lock); + spin_lock_init(&dev->int_slock); + spin_lock_init(&dev->slock); + + mutex_init(&dev->i2c_lock); + + dev->module = THIS_MODULE; + init_waitqueue_head(&dev->i2c_wq); + + /* set some sane pci arbitrition values */ + saa7146_write(dev, PCI_BT_V1, 0x1c00101f); + + /* TODO: use the status code of the callback */ + + err = -ENODEV; + + if (ext->probe && ext->probe(dev)) { + DEB_D("ext->probe() failed for %p. skipping device.\n", dev); + goto err_free_i2c; + } + + if (ext->attach(dev, pci_ext)) { + DEB_D("ext->attach() failed for %p. skipping device.\n", dev); + goto err_free_i2c; + } + /* V4L extensions will set the pci drvdata to the v4l2_device in the + attach() above. So for those cards that do not use V4L we have to + set it explicitly. */ + pci_set_drvdata(pci, &dev->v4l2_dev); + + saa7146_num++; + + err = 0; +out: + return err; + +err_free_i2c: + dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_i2c.cpu_addr, + dev->d_i2c.dma_handle); +err_free_rps1: + dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_rps1.cpu_addr, + dev->d_rps1.dma_handle); +err_free_rps0: + dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_rps0.cpu_addr, + dev->d_rps0.dma_handle); +err_free_irq: + free_irq(pci->irq, (void *)dev); +err_unmap: + iounmap(dev->mem); +err_release: + pci_release_region(pci, 0); +err_disable: + pci_disable_device(pci); +err_free: + kfree(dev); + goto out; +} + +static void saa7146_remove_one(struct pci_dev *pdev) +{ + struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev); + struct saa7146_dev *dev = to_saa7146_dev(v4l2_dev); + struct { + void *addr; + dma_addr_t dma; + } dev_map[] = { + { dev->d_i2c.cpu_addr, dev->d_i2c.dma_handle }, + { dev->d_rps1.cpu_addr, dev->d_rps1.dma_handle }, + { dev->d_rps0.cpu_addr, dev->d_rps0.dma_handle }, + { NULL, 0 } + }, *p; + + DEB_EE("dev:%p\n", dev); + + dev->ext->detach(dev); + + /* shut down all video dma transfers */ + saa7146_write(dev, MC1, 0x00ff0000); + + /* disable all irqs, release irq-routine */ + saa7146_write(dev, IER, 0); + + free_irq(pdev->irq, dev); + + for (p = dev_map; p->addr; p++) + dma_free_coherent(&pdev->dev, SAA7146_RPS_MEM, p->addr, + p->dma); + + iounmap(dev->mem); + pci_release_region(pdev, 0); + pci_disable_device(pdev); + kfree(dev); + + saa7146_num--; +} + +/*********************************************************************************/ +/* extension handling functions */ + +int saa7146_register_extension(struct saa7146_extension* ext) +{ + DEB_EE("ext:%p\n", ext); + + ext->driver.name = ext->name; + ext->driver.id_table = ext->pci_tbl; + ext->driver.probe = saa7146_init_one; + ext->driver.remove = saa7146_remove_one; + + pr_info("register extension '%s'\n", ext->name); + return pci_register_driver(&ext->driver); +} + +int saa7146_unregister_extension(struct saa7146_extension* ext) +{ + DEB_EE("ext:%p\n", ext); + pr_info("unregister extension '%s'\n", ext->name); + pci_unregister_driver(&ext->driver); + return 0; +} + +EXPORT_SYMBOL_GPL(saa7146_register_extension); +EXPORT_SYMBOL_GPL(saa7146_unregister_extension); + +/* misc functions used by extension modules */ +EXPORT_SYMBOL_GPL(saa7146_pgtable_alloc); +EXPORT_SYMBOL_GPL(saa7146_pgtable_free); +EXPORT_SYMBOL_GPL(saa7146_pgtable_build_single); +EXPORT_SYMBOL_GPL(saa7146_vmalloc_build_pgtable); +EXPORT_SYMBOL_GPL(saa7146_vfree_destroy_pgtable); +EXPORT_SYMBOL_GPL(saa7146_wait_for_debi_done); + +EXPORT_SYMBOL_GPL(saa7146_setgpio); + +EXPORT_SYMBOL_GPL(saa7146_i2c_adapter_prepare); + +EXPORT_SYMBOL_GPL(saa7146_debug); + +MODULE_AUTHOR("Michael Hunold "); +MODULE_DESCRIPTION("driver for generic saa7146-based hardware"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/deprecated/saa7146/common/saa7146_fops.c b/drivers/staging/media/deprecated/saa7146/common/saa7146_fops.c new file mode 100644 index 000000000..aa14698a9 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/saa7146_fops.c @@ -0,0 +1,658 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include "saa7146_vv.h" + +/****************************************************************************/ +/* resource management functions, shamelessly stolen from saa7134 driver */ + +int saa7146_res_get(struct saa7146_fh *fh, unsigned int bit) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + + if (fh->resources & bit) { + DEB_D("already allocated! want: 0x%02x, cur:0x%02x\n", + bit, vv->resources); + /* have it already allocated */ + return 1; + } + + /* is it free? */ + if (vv->resources & bit) { + DEB_D("locked! vv->resources:0x%02x, we want:0x%02x\n", + vv->resources, bit); + /* no, someone else uses it */ + return 0; + } + /* it's free, grab it */ + fh->resources |= bit; + vv->resources |= bit; + DEB_D("res: get 0x%02x, cur:0x%02x\n", bit, vv->resources); + return 1; +} + +void saa7146_res_free(struct saa7146_fh *fh, unsigned int bits) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + + BUG_ON((fh->resources & bits) != bits); + + fh->resources &= ~bits; + vv->resources &= ~bits; + DEB_D("res: put 0x%02x, cur:0x%02x\n", bits, vv->resources); +} + + +/********************************************************************************/ +/* common dma functions */ + +void saa7146_dma_free(struct saa7146_dev *dev,struct videobuf_queue *q, + struct saa7146_buf *buf) +{ + struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb); + DEB_EE("dev:%p, buf:%p\n", dev, buf); + + videobuf_waiton(q, &buf->vb, 0, 0); + videobuf_dma_unmap(q->dev, dma); + videobuf_dma_free(dma); + buf->vb.state = VIDEOBUF_NEEDS_INIT; +} + + +/********************************************************************************/ +/* common buffer functions */ + +int saa7146_buffer_queue(struct saa7146_dev *dev, + struct saa7146_dmaqueue *q, + struct saa7146_buf *buf) +{ + assert_spin_locked(&dev->slock); + DEB_EE("dev:%p, dmaq:%p, buf:%p\n", dev, q, buf); + + BUG_ON(!q); + + if (NULL == q->curr) { + q->curr = buf; + DEB_D("immediately activating buffer %p\n", buf); + buf->activate(dev,buf,NULL); + } else { + list_add_tail(&buf->vb.queue,&q->queue); + buf->vb.state = VIDEOBUF_QUEUED; + DEB_D("adding buffer %p to queue. (active buffer present)\n", + buf); + } + return 0; +} + +void saa7146_buffer_finish(struct saa7146_dev *dev, + struct saa7146_dmaqueue *q, + int state) +{ + assert_spin_locked(&dev->slock); + DEB_EE("dev:%p, dmaq:%p, state:%d\n", dev, q, state); + DEB_EE("q->curr:%p\n", q->curr); + + /* finish current buffer */ + if (NULL == q->curr) { + DEB_D("aiii. no current buffer\n"); + return; + } + + q->curr->vb.state = state; + q->curr->vb.ts = ktime_get_ns(); + wake_up(&q->curr->vb.done); + + q->curr = NULL; +} + +void saa7146_buffer_next(struct saa7146_dev *dev, + struct saa7146_dmaqueue *q, int vbi) +{ + struct saa7146_buf *buf,*next = NULL; + + BUG_ON(!q); + + DEB_INT("dev:%p, dmaq:%p, vbi:%d\n", dev, q, vbi); + + assert_spin_locked(&dev->slock); + if (!list_empty(&q->queue)) { + /* activate next one from queue */ + buf = list_entry(q->queue.next,struct saa7146_buf,vb.queue); + list_del(&buf->vb.queue); + if (!list_empty(&q->queue)) + next = list_entry(q->queue.next,struct saa7146_buf, vb.queue); + q->curr = buf; + DEB_INT("next buffer: buf:%p, prev:%p, next:%p\n", + buf, q->queue.prev, q->queue.next); + buf->activate(dev,buf,next); + } else { + DEB_INT("no next buffer. stopping.\n"); + if( 0 != vbi ) { + /* turn off video-dma3 */ + saa7146_write(dev,MC1, MASK_20); + } else { + /* nothing to do -- just prevent next video-dma1 transfer + by lowering the protection address */ + + // fixme: fix this for vflip != 0 + + saa7146_write(dev, PROT_ADDR1, 0); + saa7146_write(dev, MC2, (MASK_02|MASK_18)); + + /* write the address of the rps-program */ + saa7146_write(dev, RPS_ADDR0, dev->d_rps0.dma_handle); + /* turn on rps */ + saa7146_write(dev, MC1, (MASK_12 | MASK_28)); + +/* + printk("vdma%d.base_even: 0x%08x\n", 1,saa7146_read(dev,BASE_EVEN1)); + printk("vdma%d.base_odd: 0x%08x\n", 1,saa7146_read(dev,BASE_ODD1)); + printk("vdma%d.prot_addr: 0x%08x\n", 1,saa7146_read(dev,PROT_ADDR1)); + printk("vdma%d.base_page: 0x%08x\n", 1,saa7146_read(dev,BASE_PAGE1)); + printk("vdma%d.pitch: 0x%08x\n", 1,saa7146_read(dev,PITCH1)); + printk("vdma%d.num_line_byte: 0x%08x\n", 1,saa7146_read(dev,NUM_LINE_BYTE1)); +*/ + } + del_timer(&q->timeout); + } +} + +void saa7146_buffer_timeout(struct timer_list *t) +{ + struct saa7146_dmaqueue *q = from_timer(q, t, timeout); + struct saa7146_dev *dev = q->dev; + unsigned long flags; + + DEB_EE("dev:%p, dmaq:%p\n", dev, q); + + spin_lock_irqsave(&dev->slock,flags); + if (q->curr) { + DEB_D("timeout on %p\n", q->curr); + saa7146_buffer_finish(dev,q,VIDEOBUF_ERROR); + } + + /* we don't restart the transfer here like other drivers do. when + a streaming capture is disabled, the timeout function will be + called for the current buffer. if we activate the next buffer now, + we mess up our capture logic. if a timeout occurs on another buffer, + then something is seriously broken before, so no need to buffer the + next capture IMHO... */ +/* + saa7146_buffer_next(dev,q); +*/ + spin_unlock_irqrestore(&dev->slock,flags); +} + +/********************************************************************************/ +/* file operations */ + +static int fops_open(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct saa7146_dev *dev = video_drvdata(file); + struct saa7146_fh *fh = NULL; + int result = 0; + + DEB_EE("file:%p, dev:%s\n", file, video_device_node_name(vdev)); + + if (mutex_lock_interruptible(vdev->lock)) + return -ERESTARTSYS; + + DEB_D("using: %p\n", dev); + + /* check if an extension is registered */ + if( NULL == dev->ext ) { + DEB_S("no extension registered for this device\n"); + result = -ENODEV; + goto out; + } + + /* allocate per open data */ + fh = kzalloc(sizeof(*fh),GFP_KERNEL); + if (NULL == fh) { + DEB_S("cannot allocate memory for per open data\n"); + result = -ENOMEM; + goto out; + } + + v4l2_fh_init(&fh->fh, vdev); + + file->private_data = &fh->fh; + fh->dev = dev; + + if (vdev->vfl_type == VFL_TYPE_VBI) { + DEB_S("initializing vbi...\n"); + if (dev->ext_vv_data->capabilities & V4L2_CAP_VBI_CAPTURE) + result = saa7146_vbi_uops.open(dev,file); + if (dev->ext_vv_data->vbi_fops.open) + dev->ext_vv_data->vbi_fops.open(file); + } else { + DEB_S("initializing video...\n"); + result = saa7146_video_uops.open(dev,file); + } + + if (0 != result) { + goto out; + } + + if( 0 == try_module_get(dev->ext->module)) { + result = -EINVAL; + goto out; + } + + result = 0; + v4l2_fh_add(&fh->fh); +out: + if (fh && result != 0) { + kfree(fh); + file->private_data = NULL; + } + mutex_unlock(vdev->lock); + return result; +} + +static int fops_release(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + + DEB_EE("file:%p\n", file); + + mutex_lock(vdev->lock); + + if (vdev->vfl_type == VFL_TYPE_VBI) { + if (dev->ext_vv_data->capabilities & V4L2_CAP_VBI_CAPTURE) + saa7146_vbi_uops.release(dev,file); + if (dev->ext_vv_data->vbi_fops.release) + dev->ext_vv_data->vbi_fops.release(file); + } else { + saa7146_video_uops.release(dev,file); + } + + v4l2_fh_del(&fh->fh); + v4l2_fh_exit(&fh->fh); + module_put(dev->ext->module); + file->private_data = NULL; + kfree(fh); + + mutex_unlock(vdev->lock); + + return 0; +} + +static int fops_mmap(struct file *file, struct vm_area_struct * vma) +{ + struct video_device *vdev = video_devdata(file); + struct saa7146_fh *fh = file->private_data; + struct videobuf_queue *q; + int res; + + switch (vdev->vfl_type) { + case VFL_TYPE_VIDEO: { + DEB_EE("V4L2_BUF_TYPE_VIDEO_CAPTURE: file:%p, vma:%p\n", + file, vma); + q = &fh->video_q; + break; + } + case VFL_TYPE_VBI: { + DEB_EE("V4L2_BUF_TYPE_VBI_CAPTURE: file:%p, vma:%p\n", + file, vma); + if (fh->dev->ext_vv_data->capabilities & V4L2_CAP_SLICED_VBI_OUTPUT) + return -ENODEV; + q = &fh->vbi_q; + break; + } + default: + BUG(); + } + + if (mutex_lock_interruptible(vdev->lock)) + return -ERESTARTSYS; + res = videobuf_mmap_mapper(q, vma); + mutex_unlock(vdev->lock); + return res; +} + +static __poll_t __fops_poll(struct file *file, struct poll_table_struct *wait) +{ + struct video_device *vdev = video_devdata(file); + struct saa7146_fh *fh = file->private_data; + struct videobuf_buffer *buf = NULL; + struct videobuf_queue *q; + __poll_t res = v4l2_ctrl_poll(file, wait); + + DEB_EE("file:%p, poll:%p\n", file, wait); + + if (vdev->vfl_type == VFL_TYPE_VBI) { + if (fh->dev->ext_vv_data->capabilities & V4L2_CAP_SLICED_VBI_OUTPUT) + return res | EPOLLOUT | EPOLLWRNORM; + if( 0 == fh->vbi_q.streaming ) + return res | videobuf_poll_stream(file, &fh->vbi_q, wait); + q = &fh->vbi_q; + } else { + DEB_D("using video queue\n"); + q = &fh->video_q; + } + + if (!list_empty(&q->stream)) + buf = list_entry(q->stream.next, struct videobuf_buffer, stream); + + if (!buf) { + DEB_D("buf == NULL!\n"); + return res | EPOLLERR; + } + + poll_wait(file, &buf->done, wait); + if (buf->state == VIDEOBUF_DONE || buf->state == VIDEOBUF_ERROR) { + DEB_D("poll succeeded!\n"); + return res | EPOLLIN | EPOLLRDNORM; + } + + DEB_D("nothing to poll for, buf->state:%d\n", buf->state); + return res; +} + +static __poll_t fops_poll(struct file *file, struct poll_table_struct *wait) +{ + struct video_device *vdev = video_devdata(file); + __poll_t res; + + mutex_lock(vdev->lock); + res = __fops_poll(file, wait); + mutex_unlock(vdev->lock); + return res; +} + +static ssize_t fops_read(struct file *file, char __user *data, size_t count, loff_t *ppos) +{ + struct video_device *vdev = video_devdata(file); + struct saa7146_fh *fh = file->private_data; + int ret; + + switch (vdev->vfl_type) { + case VFL_TYPE_VIDEO: +/* + DEB_EE("V4L2_BUF_TYPE_VIDEO_CAPTURE: file:%p, data:%p, count:%lun", + file, data, (unsigned long)count); +*/ + return saa7146_video_uops.read(file,data,count,ppos); + case VFL_TYPE_VBI: +/* + DEB_EE("V4L2_BUF_TYPE_VBI_CAPTURE: file:%p, data:%p, count:%lu\n", + file, data, (unsigned long)count); +*/ + if (fh->dev->ext_vv_data->capabilities & V4L2_CAP_VBI_CAPTURE) { + if (mutex_lock_interruptible(vdev->lock)) + return -ERESTARTSYS; + ret = saa7146_vbi_uops.read(file, data, count, ppos); + mutex_unlock(vdev->lock); + return ret; + } + return -EINVAL; + default: + BUG(); + } +} + +static ssize_t fops_write(struct file *file, const char __user *data, size_t count, loff_t *ppos) +{ + struct video_device *vdev = video_devdata(file); + struct saa7146_fh *fh = file->private_data; + int ret; + + switch (vdev->vfl_type) { + case VFL_TYPE_VIDEO: + return -EINVAL; + case VFL_TYPE_VBI: + if (fh->dev->ext_vv_data->vbi_fops.write) { + if (mutex_lock_interruptible(vdev->lock)) + return -ERESTARTSYS; + ret = fh->dev->ext_vv_data->vbi_fops.write(file, data, count, ppos); + mutex_unlock(vdev->lock); + return ret; + } + return -EINVAL; + default: + BUG(); + } +} + +static const struct v4l2_file_operations video_fops = +{ + .owner = THIS_MODULE, + .open = fops_open, + .release = fops_release, + .read = fops_read, + .write = fops_write, + .poll = fops_poll, + .mmap = fops_mmap, + .unlocked_ioctl = video_ioctl2, +}; + +static void vv_callback(struct saa7146_dev *dev, unsigned long status) +{ + u32 isr = status; + + DEB_INT("dev:%p, isr:0x%08x\n", dev, (u32)status); + + if (0 != (isr & (MASK_27))) { + DEB_INT("irq: RPS0 (0x%08x)\n", isr); + saa7146_video_uops.irq_done(dev,isr); + } + + if (0 != (isr & (MASK_28))) { + u32 mc2 = saa7146_read(dev, MC2); + if( 0 != (mc2 & MASK_15)) { + DEB_INT("irq: RPS1 vbi workaround (0x%08x)\n", isr); + wake_up(&dev->vv_data->vbi_wq); + saa7146_write(dev,MC2, MASK_31); + return; + } + DEB_INT("irq: RPS1 (0x%08x)\n", isr); + saa7146_vbi_uops.irq_done(dev,isr); + } +} + +static const struct v4l2_ctrl_ops saa7146_ctrl_ops = { + .s_ctrl = saa7146_s_ctrl, +}; + +int saa7146_vv_init(struct saa7146_dev* dev, struct saa7146_ext_vv *ext_vv) +{ + struct v4l2_ctrl_handler *hdl = &dev->ctrl_handler; + struct v4l2_pix_format *fmt; + struct v4l2_vbi_format *vbi; + struct saa7146_vv *vv; + int err; + + err = v4l2_device_register(&dev->pci->dev, &dev->v4l2_dev); + if (err) + return err; + + v4l2_ctrl_handler_init(hdl, 6); + v4l2_ctrl_new_std(hdl, &saa7146_ctrl_ops, + V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); + v4l2_ctrl_new_std(hdl, &saa7146_ctrl_ops, + V4L2_CID_CONTRAST, 0, 127, 1, 64); + v4l2_ctrl_new_std(hdl, &saa7146_ctrl_ops, + V4L2_CID_SATURATION, 0, 127, 1, 64); + v4l2_ctrl_new_std(hdl, &saa7146_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std(hdl, &saa7146_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + if (hdl->error) { + err = hdl->error; + v4l2_ctrl_handler_free(hdl); + v4l2_device_unregister(&dev->v4l2_dev); + return err; + } + dev->v4l2_dev.ctrl_handler = hdl; + + vv = kzalloc(sizeof(struct saa7146_vv), GFP_KERNEL); + if (vv == NULL) { + ERR("out of memory. aborting.\n"); + v4l2_ctrl_handler_free(hdl); + v4l2_device_unregister(&dev->v4l2_dev); + return -ENOMEM; + } + ext_vv->vid_ops = saa7146_video_ioctl_ops; + ext_vv->vbi_ops = saa7146_vbi_ioctl_ops; + ext_vv->core_ops = &saa7146_video_ioctl_ops; + + DEB_EE("dev:%p\n", dev); + + /* set default values for video parts of the saa7146 */ + saa7146_write(dev, BCS_CTRL, 0x80400040); + + /* enable video-port pins */ + saa7146_write(dev, MC1, (MASK_10 | MASK_26)); + + /* save per-device extension data (one extension can + handle different devices that might need different + configuration data) */ + dev->ext_vv_data = ext_vv; + + vv->d_clipping.cpu_addr = + dma_alloc_coherent(&dev->pci->dev, SAA7146_CLIPPING_MEM, + &vv->d_clipping.dma_handle, GFP_KERNEL); + if( NULL == vv->d_clipping.cpu_addr ) { + ERR("out of memory. aborting.\n"); + kfree(vv); + v4l2_ctrl_handler_free(hdl); + v4l2_device_unregister(&dev->v4l2_dev); + return -ENOMEM; + } + + saa7146_video_uops.init(dev,vv); + if (dev->ext_vv_data->capabilities & V4L2_CAP_VBI_CAPTURE) + saa7146_vbi_uops.init(dev,vv); + + vv->ov_fb.fmt.width = vv->standard->h_max_out; + vv->ov_fb.fmt.height = vv->standard->v_max_out; + vv->ov_fb.fmt.pixelformat = V4L2_PIX_FMT_RGB565; + vv->ov_fb.fmt.bytesperline = 2 * vv->ov_fb.fmt.width; + vv->ov_fb.fmt.sizeimage = vv->ov_fb.fmt.bytesperline * vv->ov_fb.fmt.height; + vv->ov_fb.fmt.colorspace = V4L2_COLORSPACE_SRGB; + + fmt = &vv->video_fmt; + fmt->width = 384; + fmt->height = 288; + fmt->pixelformat = V4L2_PIX_FMT_BGR24; + fmt->field = V4L2_FIELD_ANY; + fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; + fmt->bytesperline = 3 * fmt->width; + fmt->sizeimage = fmt->bytesperline * fmt->height; + + vbi = &vv->vbi_fmt; + vbi->sampling_rate = 27000000; + vbi->offset = 248; /* todo */ + vbi->samples_per_line = 720 * 2; + vbi->sample_format = V4L2_PIX_FMT_GREY; + + /* fixme: this only works for PAL */ + vbi->start[0] = 5; + vbi->count[0] = 16; + vbi->start[1] = 312; + vbi->count[1] = 16; + + timer_setup(&vv->vbi_read_timeout, NULL, 0); + + vv->ov_fb.capability = V4L2_FBUF_CAP_LIST_CLIPPING; + vv->ov_fb.flags = V4L2_FBUF_FLAG_PRIMARY; + dev->vv_data = vv; + dev->vv_callback = &vv_callback; + + return 0; +} +EXPORT_SYMBOL_GPL(saa7146_vv_init); + +int saa7146_vv_release(struct saa7146_dev* dev) +{ + struct saa7146_vv *vv = dev->vv_data; + + DEB_EE("dev:%p\n", dev); + + v4l2_device_unregister(&dev->v4l2_dev); + dma_free_coherent(&dev->pci->dev, SAA7146_CLIPPING_MEM, + vv->d_clipping.cpu_addr, vv->d_clipping.dma_handle); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(vv); + dev->vv_data = NULL; + dev->vv_callback = NULL; + + return 0; +} +EXPORT_SYMBOL_GPL(saa7146_vv_release); + +int saa7146_register_device(struct video_device *vfd, struct saa7146_dev *dev, + char *name, int type) +{ + int err; + int i; + + DEB_EE("dev:%p, name:'%s', type:%d\n", dev, name, type); + + vfd->fops = &video_fops; + if (type == VFL_TYPE_VIDEO) + vfd->ioctl_ops = &dev->ext_vv_data->vid_ops; + else + vfd->ioctl_ops = &dev->ext_vv_data->vbi_ops; + vfd->release = video_device_release_empty; + vfd->lock = &dev->v4l2_lock; + vfd->v4l2_dev = &dev->v4l2_dev; + vfd->tvnorms = 0; + for (i = 0; i < dev->ext_vv_data->num_stds; i++) + vfd->tvnorms |= dev->ext_vv_data->stds[i].id; + strscpy(vfd->name, name, sizeof(vfd->name)); + vfd->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; + vfd->device_caps |= dev->ext_vv_data->capabilities; + if (type == VFL_TYPE_VIDEO) + vfd->device_caps &= + ~(V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_OUTPUT); + else + vfd->device_caps &= + ~(V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY | V4L2_CAP_AUDIO); + video_set_drvdata(vfd, dev); + + err = video_register_device(vfd, type, -1); + if (err < 0) { + ERR("cannot register v4l2 device. skipping.\n"); + return err; + } + + pr_info("%s: registered device %s [v4l2]\n", + dev->name, video_device_node_name(vfd)); + return 0; +} +EXPORT_SYMBOL_GPL(saa7146_register_device); + +int saa7146_unregister_device(struct video_device *vfd, struct saa7146_dev *dev) +{ + DEB_EE("dev:%p\n", dev); + + video_unregister_device(vfd); + return 0; +} +EXPORT_SYMBOL_GPL(saa7146_unregister_device); + +static int __init saa7146_vv_init_module(void) +{ + return 0; +} + + +static void __exit saa7146_vv_cleanup_module(void) +{ +} + +module_init(saa7146_vv_init_module); +module_exit(saa7146_vv_cleanup_module); + +MODULE_AUTHOR("Michael Hunold "); +MODULE_DESCRIPTION("video4linux driver for saa7146-based hardware"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/deprecated/saa7146/common/saa7146_hlp.c b/drivers/staging/media/deprecated/saa7146/common/saa7146_hlp.c new file mode 100644 index 000000000..b1222a4cf --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/saa7146_hlp.c @@ -0,0 +1,1046 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include "saa7146_vv.h" + +static void calculate_output_format_register(struct saa7146_dev* saa, u32 palette, u32* clip_format) +{ + /* clear out the necessary bits */ + *clip_format &= 0x0000ffff; + /* set these bits new */ + *clip_format |= (( ((palette&0xf00)>>8) << 30) | ((palette&0x00f) << 24) | (((palette&0x0f0)>>4) << 16)); +} + +static void calculate_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync, u32* hps_ctrl) +{ + *hps_ctrl &= ~(MASK_30 | MASK_31 | MASK_28); + *hps_ctrl |= (source << 30) | (sync << 28); +} + +static void calculate_hxo_and_hyo(struct saa7146_vv *vv, u32* hps_h_scale, u32* hps_ctrl) +{ + int hyo = 0, hxo = 0; + + hyo = vv->standard->v_offset; + hxo = vv->standard->h_offset; + + *hps_h_scale &= ~(MASK_B0 | 0xf00); + *hps_h_scale |= (hxo << 0); + + *hps_ctrl &= ~(MASK_W0 | MASK_B2); + *hps_ctrl |= (hyo << 12); +} + +/* helper functions for the calculation of the horizontal- and vertical + scaling registers, clip-format-register etc ... + these functions take pointers to the (most-likely read-out + original-values) and manipulate them according to the requested + changes. +*/ + +/* hps_coeff used for CXY and CXUV; scale 1/1 -> scale 1/64 */ +static struct { + u16 hps_coeff; + u16 weight_sum; +} hps_h_coeff_tab [] = { + {0x00, 2}, {0x02, 4}, {0x00, 4}, {0x06, 8}, {0x02, 8}, + {0x08, 8}, {0x00, 8}, {0x1E, 16}, {0x0E, 8}, {0x26, 8}, + {0x06, 8}, {0x42, 8}, {0x02, 8}, {0x80, 8}, {0x00, 8}, + {0xFE, 16}, {0xFE, 8}, {0x7E, 8}, {0x7E, 8}, {0x3E, 8}, + {0x3E, 8}, {0x1E, 8}, {0x1E, 8}, {0x0E, 8}, {0x0E, 8}, + {0x06, 8}, {0x06, 8}, {0x02, 8}, {0x02, 8}, {0x00, 8}, + {0x00, 8}, {0xFE, 16}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, + {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, + {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, + {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0x7E, 8}, + {0x7E, 8}, {0x3E, 8}, {0x3E, 8}, {0x1E, 8}, {0x1E, 8}, + {0x0E, 8}, {0x0E, 8}, {0x06, 8}, {0x06, 8}, {0x02, 8}, + {0x02, 8}, {0x00, 8}, {0x00, 8}, {0xFE, 16} +}; + +/* table of attenuation values for horizontal scaling */ +static u8 h_attenuation[] = { 1, 2, 4, 8, 2, 4, 8, 16, 0}; + +/* calculate horizontal scale registers */ +static int calculate_h_scale_registers(struct saa7146_dev *dev, + int in_x, int out_x, int flip_lr, + u32* hps_ctrl, u32* hps_v_gain, u32* hps_h_prescale, u32* hps_h_scale) +{ + /* horizontal prescaler */ + u32 dcgx = 0, xpsc = 0, xacm = 0, cxy = 0, cxuv = 0; + /* horizontal scaler */ + u32 xim = 0, xp = 0, xsci =0; + /* vertical scale & gain */ + u32 pfuv = 0; + + /* helper variables */ + u32 h_atten = 0, i = 0; + + if ( 0 == out_x ) { + return -EINVAL; + } + + /* mask out vanity-bit */ + *hps_ctrl &= ~MASK_29; + + /* calculate prescale-(xspc)-value: [n .. 1/2) : 1 + [1/2 .. 1/3) : 2 + [1/3 .. 1/4) : 3 + ... */ + if (in_x > out_x) { + xpsc = in_x / out_x; + } + else { + /* zooming */ + xpsc = 1; + } + + /* if flip_lr-bit is set, number of pixels after + horizontal prescaling must be < 384 */ + if ( 0 != flip_lr ) { + + /* set vanity bit */ + *hps_ctrl |= MASK_29; + + while (in_x / xpsc >= 384 ) + xpsc++; + } + /* if zooming is wanted, number of pixels after + horizontal prescaling must be < 768 */ + else { + while ( in_x / xpsc >= 768 ) + xpsc++; + } + + /* maximum prescale is 64 (p.69) */ + if ( xpsc > 64 ) + xpsc = 64; + + /* keep xacm clear*/ + xacm = 0; + + /* set horizontal filter parameters (CXY = CXUV) */ + cxy = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].hps_coeff; + cxuv = cxy; + + /* calculate and set horizontal fine scale (xsci) */ + + /* bypass the horizontal scaler ? */ + if ( (in_x == out_x) && ( 1 == xpsc ) ) + xsci = 0x400; + else + xsci = ( (1024 * in_x) / (out_x * xpsc) ) + xpsc; + + /* set start phase for horizontal fine scale (xp) to 0 */ + xp = 0; + + /* set xim, if we bypass the horizontal scaler */ + if ( 0x400 == xsci ) + xim = 1; + else + xim = 0; + + /* if the prescaler is bypassed, enable horizontal + accumulation mode (xacm) and clear dcgx */ + if( 1 == xpsc ) { + xacm = 1; + dcgx = 0; + } else { + xacm = 0; + /* get best match in the table of attenuations + for horizontal scaling */ + h_atten = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].weight_sum; + + for (i = 0; h_attenuation[i] != 0; i++) { + if (h_attenuation[i] >= h_atten) + break; + } + + dcgx = i; + } + + /* the horizontal scaling increment controls the UV filter + to reduce the bandwidth to improve the display quality, + so set it ... */ + if ( xsci == 0x400) + pfuv = 0x00; + else if ( xsci < 0x600) + pfuv = 0x01; + else if ( xsci < 0x680) + pfuv = 0x11; + else if ( xsci < 0x700) + pfuv = 0x22; + else + pfuv = 0x33; + + + *hps_v_gain &= MASK_W0|MASK_B2; + *hps_v_gain |= (pfuv << 24); + + *hps_h_scale &= ~(MASK_W1 | 0xf000); + *hps_h_scale |= (xim << 31) | (xp << 24) | (xsci << 12); + + *hps_h_prescale |= (dcgx << 27) | ((xpsc-1) << 18) | (xacm << 17) | (cxy << 8) | (cxuv << 0); + + return 0; +} + +static struct { + u16 hps_coeff; + u16 weight_sum; +} hps_v_coeff_tab [] = { + {0x0100, 2}, {0x0102, 4}, {0x0300, 4}, {0x0106, 8}, {0x0502, 8}, + {0x0708, 8}, {0x0F00, 8}, {0x011E, 16}, {0x110E, 16}, {0x1926, 16}, + {0x3906, 16}, {0x3D42, 16}, {0x7D02, 16}, {0x7F80, 16}, {0xFF00, 16}, + {0x01FE, 32}, {0x01FE, 32}, {0x817E, 32}, {0x817E, 32}, {0xC13E, 32}, + {0xC13E, 32}, {0xE11E, 32}, {0xE11E, 32}, {0xF10E, 32}, {0xF10E, 32}, + {0xF906, 32}, {0xF906, 32}, {0xFD02, 32}, {0xFD02, 32}, {0xFF00, 32}, + {0xFF00, 32}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, + {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, + {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, + {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x01FE, 64}, {0x817E, 64}, + {0x817E, 64}, {0xC13E, 64}, {0xC13E, 64}, {0xE11E, 64}, {0xE11E, 64}, + {0xF10E, 64}, {0xF10E, 64}, {0xF906, 64}, {0xF906, 64}, {0xFD02, 64}, + {0xFD02, 64}, {0xFF00, 64}, {0xFF00, 64}, {0x01FE, 128} +}; + +/* table of attenuation values for vertical scaling */ +static u16 v_attenuation[] = { 2, 4, 8, 16, 32, 64, 128, 256, 0}; + +/* calculate vertical scale registers */ +static int calculate_v_scale_registers(struct saa7146_dev *dev, enum v4l2_field field, + int in_y, int out_y, u32* hps_v_scale, u32* hps_v_gain) +{ + int lpi = 0; + + /* vertical scaling */ + u32 yacm = 0, ysci = 0, yacl = 0, ypo = 0, ype = 0; + /* vertical scale & gain */ + u32 dcgy = 0, cya_cyb = 0; + + /* helper variables */ + u32 v_atten = 0, i = 0; + + /* error, if vertical zooming */ + if ( in_y < out_y ) { + return -EINVAL; + } + + /* linear phase interpolation may be used + if scaling is between 1 and 1/2 (both fields used) + or scaling is between 1/2 and 1/4 (if only one field is used) */ + + if (V4L2_FIELD_HAS_BOTH(field)) { + if( 2*out_y >= in_y) { + lpi = 1; + } + } else if (field == V4L2_FIELD_TOP + || field == V4L2_FIELD_ALTERNATE + || field == V4L2_FIELD_BOTTOM) { + if( 4*out_y >= in_y ) { + lpi = 1; + } + out_y *= 2; + } + if( 0 != lpi ) { + + yacm = 0; + yacl = 0; + cya_cyb = 0x00ff; + + /* calculate scaling increment */ + if ( in_y > out_y ) + ysci = ((1024 * in_y) / (out_y + 1)) - 1024; + else + ysci = 0; + + dcgy = 0; + + /* calculate ype and ypo */ + ype = ysci / 16; + ypo = ype + (ysci / 64); + + } else { + yacm = 1; + + /* calculate scaling increment */ + ysci = (((10 * 1024 * (in_y - out_y - 1)) / in_y) + 9) / 10; + + /* calculate ype and ypo */ + ypo = ype = ((ysci + 15) / 16); + + /* the sequence length interval (yacl) has to be set according + to the prescale value, e.g. [n .. 1/2) : 0 + [1/2 .. 1/3) : 1 + [1/3 .. 1/4) : 2 + ... */ + if ( ysci < 512) { + yacl = 0; + } else { + yacl = ( ysci / (1024 - ysci) ); + } + + /* get filter coefficients for cya, cyb from table hps_v_coeff_tab */ + cya_cyb = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].hps_coeff; + + /* get best match in the table of attenuations for vertical scaling */ + v_atten = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].weight_sum; + + for (i = 0; v_attenuation[i] != 0; i++) { + if (v_attenuation[i] >= v_atten) + break; + } + + dcgy = i; + } + + /* ypo and ype swapped in spec ? */ + *hps_v_scale |= (yacm << 31) | (ysci << 21) | (yacl << 15) | (ypo << 8 ) | (ype << 1); + + *hps_v_gain &= ~(MASK_W0|MASK_B2); + *hps_v_gain |= (dcgy << 16) | (cya_cyb << 0); + + return 0; +} + +/* simple bubble-sort algorithm with duplicate elimination */ +static int sort_and_eliminate(u32* values, int* count) +{ + int low = 0, high = 0, top = 0; + int cur = 0, next = 0; + + /* sanity checks */ + if( (0 > *count) || (NULL == values) ) { + return -EINVAL; + } + + /* bubble sort the first @count items of the array @values */ + for( top = *count; top > 0; top--) { + for( low = 0, high = 1; high < top; low++, high++) { + if( values[low] > values[high] ) + swap(values[low], values[high]); + } + } + + /* remove duplicate items */ + for( cur = 0, next = 1; next < *count; next++) { + if( values[cur] != values[next]) + values[++cur] = values[next]; + } + + *count = cur + 1; + + return 0; +} + +static void calculate_clipping_registers_rect(struct saa7146_dev *dev, struct saa7146_fh *fh, + struct saa7146_video_dma *vdma2, u32* clip_format, u32* arbtr_ctrl, enum v4l2_field field) +{ + struct saa7146_vv *vv = dev->vv_data; + __le32 *clipping = vv->d_clipping.cpu_addr; + + int width = vv->ov.win.w.width; + int height = vv->ov.win.w.height; + int clipcount = vv->ov.nclips; + + u32 line_list[32]; + u32 pixel_list[32]; + int numdwords = 0; + + int i = 0, j = 0; + int cnt_line = 0, cnt_pixel = 0; + + int x[32], y[32], w[32], h[32]; + + /* clear out memory */ + memset(&line_list[0], 0x00, sizeof(u32)*32); + memset(&pixel_list[0], 0x00, sizeof(u32)*32); + memset(clipping, 0x00, SAA7146_CLIPPING_MEM); + + /* fill the line and pixel-lists */ + for(i = 0; i < clipcount; i++) { + int l = 0, r = 0, t = 0, b = 0; + + x[i] = vv->ov.clips[i].c.left; + y[i] = vv->ov.clips[i].c.top; + w[i] = vv->ov.clips[i].c.width; + h[i] = vv->ov.clips[i].c.height; + + if( w[i] < 0) { + x[i] += w[i]; w[i] = -w[i]; + } + if( h[i] < 0) { + y[i] += h[i]; h[i] = -h[i]; + } + if( x[i] < 0) { + w[i] += x[i]; x[i] = 0; + } + if( y[i] < 0) { + h[i] += y[i]; y[i] = 0; + } + if( 0 != vv->vflip ) { + y[i] = height - y[i] - h[i]; + } + + l = x[i]; + r = x[i]+w[i]; + t = y[i]; + b = y[i]+h[i]; + + /* insert left/right coordinates */ + pixel_list[ 2*i ] = min_t(int, l, width); + pixel_list[(2*i)+1] = min_t(int, r, width); + /* insert top/bottom coordinates */ + line_list[ 2*i ] = min_t(int, t, height); + line_list[(2*i)+1] = min_t(int, b, height); + } + + /* sort and eliminate lists */ + cnt_line = cnt_pixel = 2*clipcount; + sort_and_eliminate( &pixel_list[0], &cnt_pixel ); + sort_and_eliminate( &line_list[0], &cnt_line ); + + /* calculate the number of used u32s */ + numdwords = max_t(int, (cnt_line+1), (cnt_pixel+1))*2; + numdwords = max_t(int, 4, numdwords); + numdwords = min_t(int, 64, numdwords); + + /* fill up cliptable */ + for(i = 0; i < cnt_pixel; i++) { + clipping[2*i] |= cpu_to_le32(pixel_list[i] << 16); + } + for(i = 0; i < cnt_line; i++) { + clipping[(2*i)+1] |= cpu_to_le32(line_list[i] << 16); + } + + /* fill up cliptable with the display infos */ + for(j = 0; j < clipcount; j++) { + + for(i = 0; i < cnt_pixel; i++) { + + if( x[j] < 0) + x[j] = 0; + + if( pixel_list[i] < (x[j] + w[j])) { + + if ( pixel_list[i] >= x[j] ) { + clipping[2*i] |= cpu_to_le32(1 << j); + } + } + } + for(i = 0; i < cnt_line; i++) { + + if( y[j] < 0) + y[j] = 0; + + if( line_list[i] < (y[j] + h[j]) ) { + + if( line_list[i] >= y[j] ) { + clipping[(2*i)+1] |= cpu_to_le32(1 << j); + } + } + } + } + + /* adjust arbitration control register */ + *arbtr_ctrl &= 0xffff00ff; + *arbtr_ctrl |= 0x00001c00; + + vdma2->base_even = vv->d_clipping.dma_handle; + vdma2->base_odd = vv->d_clipping.dma_handle; + vdma2->prot_addr = vv->d_clipping.dma_handle+((sizeof(u32))*(numdwords)); + vdma2->base_page = 0x04; + vdma2->pitch = 0x00; + vdma2->num_line_byte = (0 << 16 | (sizeof(u32))*(numdwords-1) ); + + /* set clipping-mode. this depends on the field(s) used */ + *clip_format &= 0xfffffff7; + if (V4L2_FIELD_HAS_BOTH(field)) { + *clip_format |= 0x00000008; + } else { + *clip_format |= 0x00000000; + } +} + +/* disable clipping */ +static void saa7146_disable_clipping(struct saa7146_dev *dev) +{ + u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL); + + /* mask out relevant bits (=lower word)*/ + clip_format &= MASK_W1; + + /* upload clipping-registers*/ + saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format); + saa7146_write(dev, MC2, (MASK_05 | MASK_21)); + + /* disable video dma2 */ + saa7146_write(dev, MC1, MASK_21); +} + +static void saa7146_set_clipping_rect(struct saa7146_fh *fh) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + enum v4l2_field field = vv->ov.win.field; + struct saa7146_video_dma vdma2; + u32 clip_format; + u32 arbtr_ctrl; + + /* check clipcount, disable clipping if clipcount == 0*/ + if (vv->ov.nclips == 0) { + saa7146_disable_clipping(dev); + return; + } + + clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL); + arbtr_ctrl = saa7146_read(dev, PCI_BT_V1); + + calculate_clipping_registers_rect(dev, fh, &vdma2, &clip_format, &arbtr_ctrl, field); + + /* set clipping format */ + clip_format &= 0xffff0008; + clip_format |= (SAA7146_CLIPPING_RECT << 4); + + /* prepare video dma2 */ + saa7146_write(dev, BASE_EVEN2, vdma2.base_even); + saa7146_write(dev, BASE_ODD2, vdma2.base_odd); + saa7146_write(dev, PROT_ADDR2, vdma2.prot_addr); + saa7146_write(dev, BASE_PAGE2, vdma2.base_page); + saa7146_write(dev, PITCH2, vdma2.pitch); + saa7146_write(dev, NUM_LINE_BYTE2, vdma2.num_line_byte); + + /* prepare the rest */ + saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format); + saa7146_write(dev, PCI_BT_V1, arbtr_ctrl); + + /* upload clip_control-register, clipping-registers, enable video dma2 */ + saa7146_write(dev, MC2, (MASK_05 | MASK_21 | MASK_03 | MASK_19)); + saa7146_write(dev, MC1, (MASK_05 | MASK_21)); +} + +static void saa7146_set_window(struct saa7146_dev *dev, int width, int height, enum v4l2_field field) +{ + struct saa7146_vv *vv = dev->vv_data; + + int source = vv->current_hps_source; + int sync = vv->current_hps_sync; + + u32 hps_v_scale = 0, hps_v_gain = 0, hps_ctrl = 0, hps_h_prescale = 0, hps_h_scale = 0; + + /* set vertical scale */ + hps_v_scale = 0; /* all bits get set by the function-call */ + hps_v_gain = 0; /* fixme: saa7146_read(dev, HPS_V_GAIN);*/ + calculate_v_scale_registers(dev, field, vv->standard->v_field*2, height, &hps_v_scale, &hps_v_gain); + + /* set horizontal scale */ + hps_ctrl = 0; + hps_h_prescale = 0; /* all bits get set in the function */ + hps_h_scale = 0; + calculate_h_scale_registers(dev, vv->standard->h_pixels, width, vv->hflip, &hps_ctrl, &hps_v_gain, &hps_h_prescale, &hps_h_scale); + + /* set hyo and hxo */ + calculate_hxo_and_hyo(vv, &hps_h_scale, &hps_ctrl); + calculate_hps_source_and_sync(dev, source, sync, &hps_ctrl); + + /* write out new register contents */ + saa7146_write(dev, HPS_V_SCALE, hps_v_scale); + saa7146_write(dev, HPS_V_GAIN, hps_v_gain); + saa7146_write(dev, HPS_CTRL, hps_ctrl); + saa7146_write(dev, HPS_H_PRESCALE,hps_h_prescale); + saa7146_write(dev, HPS_H_SCALE, hps_h_scale); + + /* upload shadow-ram registers */ + saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) ); +} + +/* calculate the new memory offsets for a desired position */ +static void saa7146_set_position(struct saa7146_dev *dev, int w_x, int w_y, int w_height, enum v4l2_field field, u32 pixelformat) +{ + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev, pixelformat); + + int b_depth = vv->ov_fmt->depth; + int b_bpl = vv->ov_fb.fmt.bytesperline; + /* The unsigned long cast is to remove a 64-bit compile warning since + it looks like a 64-bit address is cast to a 32-bit value, even + though the base pointer is really a 32-bit physical address that + goes into a 32-bit DMA register. + FIXME: might not work on some 64-bit platforms, but see the FIXME + in struct v4l2_framebuffer (videodev2.h) for that. + */ + u32 base = (u32)(unsigned long)vv->ov_fb.base; + + struct saa7146_video_dma vdma1; + + /* calculate memory offsets for picture, look if we shall top-down-flip */ + vdma1.pitch = 2*b_bpl; + if ( 0 == vv->vflip ) { + vdma1.base_even = base + (w_y * (vdma1.pitch/2)) + (w_x * (b_depth / 8)); + vdma1.base_odd = vdma1.base_even + (vdma1.pitch / 2); + vdma1.prot_addr = vdma1.base_even + (w_height * (vdma1.pitch / 2)); + } + else { + vdma1.base_even = base + ((w_y+w_height) * (vdma1.pitch/2)) + (w_x * (b_depth / 8)); + vdma1.base_odd = vdma1.base_even - (vdma1.pitch / 2); + vdma1.prot_addr = vdma1.base_odd - (w_height * (vdma1.pitch / 2)); + } + + if (V4L2_FIELD_HAS_BOTH(field)) { + } else if (field == V4L2_FIELD_ALTERNATE) { + /* fixme */ + vdma1.base_odd = vdma1.prot_addr; + vdma1.pitch /= 2; + } else if (field == V4L2_FIELD_TOP) { + vdma1.base_odd = vdma1.prot_addr; + vdma1.pitch /= 2; + } else if (field == V4L2_FIELD_BOTTOM) { + vdma1.base_odd = vdma1.base_even; + vdma1.base_even = vdma1.prot_addr; + vdma1.pitch /= 2; + } + + if ( 0 != vv->vflip ) { + vdma1.pitch *= -1; + } + + vdma1.base_page = sfmt->swap; + vdma1.num_line_byte = (vv->standard->v_field<<16)+vv->standard->h_pixels; + + saa7146_write_out_dma(dev, 1, &vdma1); +} + +static void saa7146_set_output_format(struct saa7146_dev *dev, unsigned long palette) +{ + u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL); + + /* call helper function */ + calculate_output_format_register(dev,palette,&clip_format); + + /* update the hps registers */ + saa7146_write(dev, CLIP_FORMAT_CTRL, clip_format); + saa7146_write(dev, MC2, (MASK_05 | MASK_21)); +} + +/* select input-source */ +void saa7146_set_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync) +{ + struct saa7146_vv *vv = dev->vv_data; + u32 hps_ctrl = 0; + + /* read old state */ + hps_ctrl = saa7146_read(dev, HPS_CTRL); + + hps_ctrl &= ~( MASK_31 | MASK_30 | MASK_28 ); + hps_ctrl |= (source << 30) | (sync << 28); + + /* write back & upload register */ + saa7146_write(dev, HPS_CTRL, hps_ctrl); + saa7146_write(dev, MC2, (MASK_05 | MASK_21)); + + vv->current_hps_source = source; + vv->current_hps_sync = sync; +} +EXPORT_SYMBOL_GPL(saa7146_set_hps_source_and_sync); + +int saa7146_enable_overlay(struct saa7146_fh *fh) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + + saa7146_set_window(dev, vv->ov.win.w.width, vv->ov.win.w.height, vv->ov.win.field); + saa7146_set_position(dev, vv->ov.win.w.left, vv->ov.win.w.top, vv->ov.win.w.height, vv->ov.win.field, vv->ov_fmt->pixelformat); + saa7146_set_output_format(dev, vv->ov_fmt->trans); + saa7146_set_clipping_rect(fh); + + /* enable video dma1 */ + saa7146_write(dev, MC1, (MASK_06 | MASK_22)); + return 0; +} + +void saa7146_disable_overlay(struct saa7146_fh *fh) +{ + struct saa7146_dev *dev = fh->dev; + + /* disable clipping + video dma1 */ + saa7146_disable_clipping(dev); + saa7146_write(dev, MC1, MASK_22); +} + +void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma) +{ + int where = 0; + + if( which < 1 || which > 3) { + return; + } + + /* calculate starting address */ + where = (which-1)*0x18; + + saa7146_write(dev, where, vdma->base_odd); + saa7146_write(dev, where+0x04, vdma->base_even); + saa7146_write(dev, where+0x08, vdma->prot_addr); + saa7146_write(dev, where+0x0c, vdma->pitch); + saa7146_write(dev, where+0x10, vdma->base_page); + saa7146_write(dev, where+0x14, vdma->num_line_byte); + + /* upload */ + saa7146_write(dev, MC2, (MASK_02<<(which-1))|(MASK_18<<(which-1))); +/* + printk("vdma%d.base_even: 0x%08x\n", which,vdma->base_even); + printk("vdma%d.base_odd: 0x%08x\n", which,vdma->base_odd); + printk("vdma%d.prot_addr: 0x%08x\n", which,vdma->prot_addr); + printk("vdma%d.base_page: 0x%08x\n", which,vdma->base_page); + printk("vdma%d.pitch: 0x%08x\n", which,vdma->pitch); + printk("vdma%d.num_line_byte: 0x%08x\n", which,vdma->num_line_byte); +*/ +} + +static int calculate_video_dma_grab_packed(struct saa7146_dev* dev, struct saa7146_buf *buf) +{ + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_video_dma vdma1; + + struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev,buf->fmt->pixelformat); + + int width = buf->fmt->width; + int height = buf->fmt->height; + int bytesperline = buf->fmt->bytesperline; + enum v4l2_field field = buf->fmt->field; + + int depth = sfmt->depth; + + DEB_CAP("[size=%dx%d,fields=%s]\n", + width, height, v4l2_field_names[field]); + + if( bytesperline != 0) { + vdma1.pitch = bytesperline*2; + } else { + vdma1.pitch = (width*depth*2)/8; + } + vdma1.num_line_byte = ((vv->standard->v_field<<16) + vv->standard->h_pixels); + vdma1.base_page = buf->pt[0].dma | ME1 | sfmt->swap; + + if( 0 != vv->vflip ) { + vdma1.prot_addr = buf->pt[0].offset; + vdma1.base_even = buf->pt[0].offset+(vdma1.pitch/2)*height; + vdma1.base_odd = vdma1.base_even - (vdma1.pitch/2); + } else { + vdma1.base_even = buf->pt[0].offset; + vdma1.base_odd = vdma1.base_even + (vdma1.pitch/2); + vdma1.prot_addr = buf->pt[0].offset+(vdma1.pitch/2)*height; + } + + if (V4L2_FIELD_HAS_BOTH(field)) { + } else if (field == V4L2_FIELD_ALTERNATE) { + /* fixme */ + if ( vv->last_field == V4L2_FIELD_TOP ) { + vdma1.base_odd = vdma1.prot_addr; + vdma1.pitch /= 2; + } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) { + vdma1.base_odd = vdma1.base_even; + vdma1.base_even = vdma1.prot_addr; + vdma1.pitch /= 2; + } + } else if (field == V4L2_FIELD_TOP) { + vdma1.base_odd = vdma1.prot_addr; + vdma1.pitch /= 2; + } else if (field == V4L2_FIELD_BOTTOM) { + vdma1.base_odd = vdma1.base_even; + vdma1.base_even = vdma1.prot_addr; + vdma1.pitch /= 2; + } + + if( 0 != vv->vflip ) { + vdma1.pitch *= -1; + } + + saa7146_write_out_dma(dev, 1, &vdma1); + return 0; +} + +static int calc_planar_422(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3) +{ + int height = buf->fmt->height; + int width = buf->fmt->width; + + vdma2->pitch = width; + vdma3->pitch = width; + + /* fixme: look at bytesperline! */ + + if( 0 != vv->vflip ) { + vdma2->prot_addr = buf->pt[1].offset; + vdma2->base_even = ((vdma2->pitch/2)*height)+buf->pt[1].offset; + vdma2->base_odd = vdma2->base_even - (vdma2->pitch/2); + + vdma3->prot_addr = buf->pt[2].offset; + vdma3->base_even = ((vdma3->pitch/2)*height)+buf->pt[2].offset; + vdma3->base_odd = vdma3->base_even - (vdma3->pitch/2); + } else { + vdma3->base_even = buf->pt[2].offset; + vdma3->base_odd = vdma3->base_even + (vdma3->pitch/2); + vdma3->prot_addr = (vdma3->pitch/2)*height+buf->pt[2].offset; + + vdma2->base_even = buf->pt[1].offset; + vdma2->base_odd = vdma2->base_even + (vdma2->pitch/2); + vdma2->prot_addr = (vdma2->pitch/2)*height+buf->pt[1].offset; + } + + return 0; +} + +static int calc_planar_420(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3) +{ + int height = buf->fmt->height; + int width = buf->fmt->width; + + vdma2->pitch = width/2; + vdma3->pitch = width/2; + + if( 0 != vv->vflip ) { + vdma2->prot_addr = buf->pt[2].offset; + vdma2->base_even = ((vdma2->pitch/2)*height)+buf->pt[2].offset; + vdma2->base_odd = vdma2->base_even - (vdma2->pitch/2); + + vdma3->prot_addr = buf->pt[1].offset; + vdma3->base_even = ((vdma3->pitch/2)*height)+buf->pt[1].offset; + vdma3->base_odd = vdma3->base_even - (vdma3->pitch/2); + + } else { + vdma3->base_even = buf->pt[2].offset; + vdma3->base_odd = vdma3->base_even + (vdma3->pitch); + vdma3->prot_addr = (vdma3->pitch/2)*height+buf->pt[2].offset; + + vdma2->base_even = buf->pt[1].offset; + vdma2->base_odd = vdma2->base_even + (vdma2->pitch); + vdma2->prot_addr = (vdma2->pitch/2)*height+buf->pt[1].offset; + } + return 0; +} + +static int calculate_video_dma_grab_planar(struct saa7146_dev* dev, struct saa7146_buf *buf) +{ + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_video_dma vdma1; + struct saa7146_video_dma vdma2; + struct saa7146_video_dma vdma3; + + struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev,buf->fmt->pixelformat); + + int width = buf->fmt->width; + int height = buf->fmt->height; + enum v4l2_field field = buf->fmt->field; + + BUG_ON(0 == buf->pt[0].dma); + BUG_ON(0 == buf->pt[1].dma); + BUG_ON(0 == buf->pt[2].dma); + + DEB_CAP("[size=%dx%d,fields=%s]\n", + width, height, v4l2_field_names[field]); + + /* fixme: look at bytesperline! */ + + /* fixme: what happens for user space buffers here?. The offsets are + most likely wrong, this version here only works for page-aligned + buffers, modifications to the pagetable-functions are necessary...*/ + + vdma1.pitch = width*2; + vdma1.num_line_byte = ((vv->standard->v_field<<16) + vv->standard->h_pixels); + vdma1.base_page = buf->pt[0].dma | ME1; + + if( 0 != vv->vflip ) { + vdma1.prot_addr = buf->pt[0].offset; + vdma1.base_even = ((vdma1.pitch/2)*height)+buf->pt[0].offset; + vdma1.base_odd = vdma1.base_even - (vdma1.pitch/2); + } else { + vdma1.base_even = buf->pt[0].offset; + vdma1.base_odd = vdma1.base_even + (vdma1.pitch/2); + vdma1.prot_addr = (vdma1.pitch/2)*height+buf->pt[0].offset; + } + + vdma2.num_line_byte = 0; /* unused */ + vdma2.base_page = buf->pt[1].dma | ME1; + + vdma3.num_line_byte = 0; /* unused */ + vdma3.base_page = buf->pt[2].dma | ME1; + + switch( sfmt->depth ) { + case 12: { + calc_planar_420(vv,buf,&vdma2,&vdma3); + break; + } + case 16: { + calc_planar_422(vv,buf,&vdma2,&vdma3); + break; + } + default: { + return -1; + } + } + + if (V4L2_FIELD_HAS_BOTH(field)) { + } else if (field == V4L2_FIELD_ALTERNATE) { + /* fixme */ + vdma1.base_odd = vdma1.prot_addr; + vdma1.pitch /= 2; + vdma2.base_odd = vdma2.prot_addr; + vdma2.pitch /= 2; + vdma3.base_odd = vdma3.prot_addr; + vdma3.pitch /= 2; + } else if (field == V4L2_FIELD_TOP) { + vdma1.base_odd = vdma1.prot_addr; + vdma1.pitch /= 2; + vdma2.base_odd = vdma2.prot_addr; + vdma2.pitch /= 2; + vdma3.base_odd = vdma3.prot_addr; + vdma3.pitch /= 2; + } else if (field == V4L2_FIELD_BOTTOM) { + vdma1.base_odd = vdma1.base_even; + vdma1.base_even = vdma1.prot_addr; + vdma1.pitch /= 2; + vdma2.base_odd = vdma2.base_even; + vdma2.base_even = vdma2.prot_addr; + vdma2.pitch /= 2; + vdma3.base_odd = vdma3.base_even; + vdma3.base_even = vdma3.prot_addr; + vdma3.pitch /= 2; + } + + if( 0 != vv->vflip ) { + vdma1.pitch *= -1; + vdma2.pitch *= -1; + vdma3.pitch *= -1; + } + + saa7146_write_out_dma(dev, 1, &vdma1); + if( (sfmt->flags & FORMAT_BYTE_SWAP) != 0 ) { + saa7146_write_out_dma(dev, 3, &vdma2); + saa7146_write_out_dma(dev, 2, &vdma3); + } else { + saa7146_write_out_dma(dev, 2, &vdma2); + saa7146_write_out_dma(dev, 3, &vdma3); + } + return 0; +} + +static void program_capture_engine(struct saa7146_dev *dev, int planar) +{ + struct saa7146_vv *vv = dev->vv_data; + int count = 0; + + unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B; + unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B; + + /* wait for o_fid_a/b / e_fid_a/b toggle only if rps register 0 is not set*/ + WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | o_wait); + WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | e_wait); + + /* set rps register 0 */ + WRITE_RPS0(CMD_WR_REG | (1 << 8) | (MC2/4)); + WRITE_RPS0(MASK_27 | MASK_11); + + /* turn on video-dma1 */ + WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4)); + WRITE_RPS0(MASK_06 | MASK_22); /* => mask */ + WRITE_RPS0(MASK_06 | MASK_22); /* => values */ + if( 0 != planar ) { + /* turn on video-dma2 */ + WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4)); + WRITE_RPS0(MASK_05 | MASK_21); /* => mask */ + WRITE_RPS0(MASK_05 | MASK_21); /* => values */ + + /* turn on video-dma3 */ + WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4)); + WRITE_RPS0(MASK_04 | MASK_20); /* => mask */ + WRITE_RPS0(MASK_04 | MASK_20); /* => values */ + } + + /* wait for o_fid_a/b / e_fid_a/b toggle */ + if ( vv->last_field == V4L2_FIELD_INTERLACED ) { + WRITE_RPS0(CMD_PAUSE | o_wait); + WRITE_RPS0(CMD_PAUSE | e_wait); + } else if ( vv->last_field == V4L2_FIELD_TOP ) { + WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09)); + WRITE_RPS0(CMD_PAUSE | o_wait); + } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) { + WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09)); + WRITE_RPS0(CMD_PAUSE | e_wait); + } + + /* turn off video-dma1 */ + WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4)); + WRITE_RPS0(MASK_22 | MASK_06); /* => mask */ + WRITE_RPS0(MASK_22); /* => values */ + if( 0 != planar ) { + /* turn off video-dma2 */ + WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4)); + WRITE_RPS0(MASK_05 | MASK_21); /* => mask */ + WRITE_RPS0(MASK_21); /* => values */ + + /* turn off video-dma3 */ + WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4)); + WRITE_RPS0(MASK_04 | MASK_20); /* => mask */ + WRITE_RPS0(MASK_20); /* => values */ + } + + /* generate interrupt */ + WRITE_RPS0(CMD_INTERRUPT); + + /* stop */ + WRITE_RPS0(CMD_STOP); +} + +void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next) +{ + struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev,buf->fmt->pixelformat); + struct saa7146_vv *vv = dev->vv_data; + u32 vdma1_prot_addr; + + DEB_CAP("buf:%p, next:%p\n", buf, next); + + vdma1_prot_addr = saa7146_read(dev, PROT_ADDR1); + if( 0 == vdma1_prot_addr ) { + /* clear out beginning of streaming bit (rps register 0)*/ + DEB_CAP("forcing sync to new frame\n"); + saa7146_write(dev, MC2, MASK_27 ); + } + + saa7146_set_window(dev, buf->fmt->width, buf->fmt->height, buf->fmt->field); + saa7146_set_output_format(dev, sfmt->trans); + saa7146_disable_clipping(dev); + + if ( vv->last_field == V4L2_FIELD_INTERLACED ) { + } else if ( vv->last_field == V4L2_FIELD_TOP ) { + vv->last_field = V4L2_FIELD_BOTTOM; + } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) { + vv->last_field = V4L2_FIELD_TOP; + } + + if( 0 != IS_PLANAR(sfmt->trans)) { + calculate_video_dma_grab_planar(dev, buf); + program_capture_engine(dev,1); + } else { + calculate_video_dma_grab_packed(dev, buf); + program_capture_engine(dev,0); + } + +/* + printk("vdma%d.base_even: 0x%08x\n", 1,saa7146_read(dev,BASE_EVEN1)); + printk("vdma%d.base_odd: 0x%08x\n", 1,saa7146_read(dev,BASE_ODD1)); + printk("vdma%d.prot_addr: 0x%08x\n", 1,saa7146_read(dev,PROT_ADDR1)); + printk("vdma%d.base_page: 0x%08x\n", 1,saa7146_read(dev,BASE_PAGE1)); + printk("vdma%d.pitch: 0x%08x\n", 1,saa7146_read(dev,PITCH1)); + printk("vdma%d.num_line_byte: 0x%08x\n", 1,saa7146_read(dev,NUM_LINE_BYTE1)); + printk("vdma%d => vptr : 0x%08x\n", 1,saa7146_read(dev,PCI_VDP1)); +*/ + + /* write the address of the rps-program */ + saa7146_write(dev, RPS_ADDR0, dev->d_rps0.dma_handle); + + /* turn on rps */ + saa7146_write(dev, MC1, (MASK_12 | MASK_28)); +} diff --git a/drivers/staging/media/deprecated/saa7146/common/saa7146_i2c.c b/drivers/staging/media/deprecated/saa7146/common/saa7146_i2c.c new file mode 100644 index 000000000..7a33fe517 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/saa7146_i2c.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0 +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include "saa7146_vv.h" + +static u32 saa7146_i2c_func(struct i2c_adapter *adapter) +{ + /* DEB_I2C("'%s'\n", adapter->name); */ + + return I2C_FUNC_I2C + | I2C_FUNC_SMBUS_QUICK + | I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE + | I2C_FUNC_SMBUS_READ_BYTE_DATA | I2C_FUNC_SMBUS_WRITE_BYTE_DATA; +} + +/* this function returns the status-register of our i2c-device */ +static inline u32 saa7146_i2c_status(struct saa7146_dev *dev) +{ + u32 iicsta = saa7146_read(dev, I2C_STATUS); + /* DEB_I2C("status: 0x%08x\n", iicsta); */ + return iicsta; +} + +/* this function runs through the i2c-messages and prepares the data to be + sent through the saa7146. have a look at the specifications p. 122 ff + to understand this. it returns the number of u32s to send, or -1 + in case of an error. */ +static int saa7146_i2c_msg_prepare(const struct i2c_msg *m, int num, __le32 *op) +{ + int h1, h2; + int i, j, addr; + int mem = 0, op_count = 0; + + /* first determine size of needed memory */ + for(i = 0; i < num; i++) { + mem += m[i].len + 1; + } + + /* worst case: we need one u32 for three bytes to be send + plus one extra byte to address the device */ + mem = 1 + ((mem-1) / 3); + + /* we assume that op points to a memory of at least + * SAA7146_I2C_MEM bytes size. if we exceed this limit... + */ + if ((4 * mem) > SAA7146_I2C_MEM) { + /* DEB_I2C("cannot prepare i2c-message\n"); */ + return -ENOMEM; + } + + /* be careful: clear out the i2c-mem first */ + memset(op,0,sizeof(__le32)*mem); + + /* loop through all messages */ + for(i = 0; i < num; i++) { + + addr = i2c_8bit_addr_from_msg(&m[i]); + h1 = op_count/3; h2 = op_count%3; + op[h1] |= cpu_to_le32( (u8)addr << ((3-h2)*8)); + op[h1] |= cpu_to_le32(SAA7146_I2C_START << ((3-h2)*2)); + op_count++; + + /* loop through all bytes of message i */ + for(j = 0; j < m[i].len; j++) { + /* insert the data bytes */ + h1 = op_count/3; h2 = op_count%3; + op[h1] |= cpu_to_le32( (u32)((u8)m[i].buf[j]) << ((3-h2)*8)); + op[h1] |= cpu_to_le32( SAA7146_I2C_CONT << ((3-h2)*2)); + op_count++; + } + + } + + /* have a look at the last byte inserted: + if it was: ...CONT change it to ...STOP */ + h1 = (op_count-1)/3; h2 = (op_count-1)%3; + if ( SAA7146_I2C_CONT == (0x3 & (le32_to_cpu(op[h1]) >> ((3-h2)*2))) ) { + op[h1] &= ~cpu_to_le32(0x2 << ((3-h2)*2)); + op[h1] |= cpu_to_le32(SAA7146_I2C_STOP << ((3-h2)*2)); + } + + /* return the number of u32s to send */ + return mem; +} + +/* this functions loops through all i2c-messages. normally, it should determine + which bytes were read through the adapter and write them back to the corresponding + i2c-message. but instead, we simply write back all bytes. + fixme: this could be improved. */ +static int saa7146_i2c_msg_cleanup(const struct i2c_msg *m, int num, __le32 *op) +{ + int i, j; + int op_count = 0; + + /* loop through all messages */ + for(i = 0; i < num; i++) { + + op_count++; + + /* loop through all bytes of message i */ + for(j = 0; j < m[i].len; j++) { + /* write back all bytes that could have been read */ + m[i].buf[j] = (le32_to_cpu(op[op_count/3]) >> ((3-(op_count%3))*8)); + op_count++; + } + } + + return 0; +} + +/* this functions resets the i2c-device and returns 0 if everything was fine, otherwise -1 */ +static int saa7146_i2c_reset(struct saa7146_dev *dev) +{ + /* get current status */ + u32 status = saa7146_i2c_status(dev); + + /* clear registers for sure */ + saa7146_write(dev, I2C_STATUS, dev->i2c_bitrate); + saa7146_write(dev, I2C_TRANSFER, 0); + + /* check if any operation is still in progress */ + if ( 0 != ( status & SAA7146_I2C_BUSY) ) { + + /* yes, kill ongoing operation */ + DEB_I2C("busy_state detected\n"); + + /* set "ABORT-OPERATION"-bit (bit 7)*/ + saa7146_write(dev, I2C_STATUS, (dev->i2c_bitrate | MASK_07)); + saa7146_write(dev, MC2, (MASK_00 | MASK_16)); + msleep(SAA7146_I2C_DELAY); + + /* clear all error-bits pending; this is needed because p.123, note 1 */ + saa7146_write(dev, I2C_STATUS, dev->i2c_bitrate); + saa7146_write(dev, MC2, (MASK_00 | MASK_16)); + msleep(SAA7146_I2C_DELAY); + } + + /* check if any error is (still) present. (this can be necessary because p.123, note 1) */ + status = saa7146_i2c_status(dev); + + if ( dev->i2c_bitrate != status ) { + + DEB_I2C("error_state detected. status:0x%08x\n", status); + + /* Repeat the abort operation. This seems to be necessary + after serious protocol errors caused by e.g. the SAA7740 */ + saa7146_write(dev, I2C_STATUS, (dev->i2c_bitrate | MASK_07)); + saa7146_write(dev, MC2, (MASK_00 | MASK_16)); + msleep(SAA7146_I2C_DELAY); + + /* clear all error-bits pending */ + saa7146_write(dev, I2C_STATUS, dev->i2c_bitrate); + saa7146_write(dev, MC2, (MASK_00 | MASK_16)); + msleep(SAA7146_I2C_DELAY); + + /* the data sheet says it might be necessary to clear the status + twice after an abort */ + saa7146_write(dev, I2C_STATUS, dev->i2c_bitrate); + saa7146_write(dev, MC2, (MASK_00 | MASK_16)); + msleep(SAA7146_I2C_DELAY); + } + + /* if any error is still present, a fatal error has occurred ... */ + status = saa7146_i2c_status(dev); + if ( dev->i2c_bitrate != status ) { + DEB_I2C("fatal error. status:0x%08x\n", status); + return -1; + } + + return 0; +} + +/* this functions writes out the data-byte 'dword' to the i2c-device. + it returns 0 if ok, -1 if the transfer failed, -2 if the transfer + failed badly (e.g. address error) */ +static int saa7146_i2c_writeout(struct saa7146_dev *dev, __le32 *dword, int short_delay) +{ + u32 status = 0, mc2 = 0; + int trial = 0; + unsigned long timeout; + + /* write out i2c-command */ + DEB_I2C("before: 0x%08x (status: 0x%08x), %d\n", + *dword, saa7146_read(dev, I2C_STATUS), dev->i2c_op); + + if( 0 != (SAA7146_USE_I2C_IRQ & dev->ext->flags)) { + + saa7146_write(dev, I2C_STATUS, dev->i2c_bitrate); + saa7146_write(dev, I2C_TRANSFER, le32_to_cpu(*dword)); + + dev->i2c_op = 1; + SAA7146_ISR_CLEAR(dev, MASK_16|MASK_17); + SAA7146_IER_ENABLE(dev, MASK_16|MASK_17); + saa7146_write(dev, MC2, (MASK_00 | MASK_16)); + + timeout = HZ/100 + 1; /* 10ms */ + timeout = wait_event_interruptible_timeout(dev->i2c_wq, dev->i2c_op == 0, timeout); + if (timeout == -ERESTARTSYS || dev->i2c_op) { + SAA7146_IER_DISABLE(dev, MASK_16|MASK_17); + SAA7146_ISR_CLEAR(dev, MASK_16|MASK_17); + if (timeout == -ERESTARTSYS) + /* a signal arrived */ + return -ERESTARTSYS; + + pr_warn("%s %s [irq]: timed out waiting for end of xfer\n", + dev->name, __func__); + return -EIO; + } + status = saa7146_read(dev, I2C_STATUS); + } else { + saa7146_write(dev, I2C_STATUS, dev->i2c_bitrate); + saa7146_write(dev, I2C_TRANSFER, le32_to_cpu(*dword)); + saa7146_write(dev, MC2, (MASK_00 | MASK_16)); + + /* do not poll for i2c-status before upload is complete */ + timeout = jiffies + HZ/100 + 1; /* 10ms */ + while(1) { + mc2 = (saa7146_read(dev, MC2) & 0x1); + if( 0 != mc2 ) { + break; + } + if (time_after(jiffies,timeout)) { + pr_warn("%s %s: timed out waiting for MC2\n", + dev->name, __func__); + return -EIO; + } + } + /* wait until we get a transfer done or error */ + timeout = jiffies + HZ/100 + 1; /* 10ms */ + /* first read usually delivers bogus results... */ + saa7146_i2c_status(dev); + while(1) { + status = saa7146_i2c_status(dev); + if ((status & 0x3) != 1) + break; + if (time_after(jiffies,timeout)) { + /* this is normal when probing the bus + * (no answer from nonexisistant device...) + */ + pr_warn("%s %s [poll]: timed out waiting for end of xfer\n", + dev->name, __func__); + return -EIO; + } + if (++trial < 50 && short_delay) + udelay(10); + else + msleep(1); + } + } + + /* give a detailed status report */ + if ( 0 != (status & (SAA7146_I2C_SPERR | SAA7146_I2C_APERR | + SAA7146_I2C_DTERR | SAA7146_I2C_DRERR | + SAA7146_I2C_AL | SAA7146_I2C_ERR | + SAA7146_I2C_BUSY)) ) { + + if ( 0 == (status & SAA7146_I2C_ERR) || + 0 == (status & SAA7146_I2C_BUSY) ) { + /* it may take some time until ERR goes high - ignore */ + DEB_I2C("unexpected i2c status %04x\n", status); + } + if( 0 != (status & SAA7146_I2C_SPERR) ) { + DEB_I2C("error due to invalid start/stop condition\n"); + } + if( 0 != (status & SAA7146_I2C_DTERR) ) { + DEB_I2C("error in data transmission\n"); + } + if( 0 != (status & SAA7146_I2C_DRERR) ) { + DEB_I2C("error when receiving data\n"); + } + if( 0 != (status & SAA7146_I2C_AL) ) { + DEB_I2C("error because arbitration lost\n"); + } + + /* we handle address-errors here */ + if( 0 != (status & SAA7146_I2C_APERR) ) { + DEB_I2C("error in address phase\n"); + return -EREMOTEIO; + } + + return -EIO; + } + + /* read back data, just in case we were reading ... */ + *dword = cpu_to_le32(saa7146_read(dev, I2C_TRANSFER)); + + DEB_I2C("after: 0x%08x\n", *dword); + return 0; +} + +static int saa7146_i2c_transfer(struct saa7146_dev *dev, const struct i2c_msg *msgs, int num, int retries) +{ + int i = 0, count = 0; + __le32 *buffer = dev->d_i2c.cpu_addr; + int err = 0; + int short_delay = 0; + + if (mutex_lock_interruptible(&dev->i2c_lock)) + return -ERESTARTSYS; + + for(i=0;i count ) { + err = -EIO; + goto out; + } + + if ( count > 3 || 0 != (SAA7146_I2C_SHORT_DELAY & dev->ext->flags) ) + short_delay = 1; + + do { + /* reset the i2c-device if necessary */ + err = saa7146_i2c_reset(dev); + if ( 0 > err ) { + DEB_I2C("could not reset i2c-device\n"); + goto out; + } + + /* write out the u32s one after another */ + for(i = 0; i < count; i++) { + err = saa7146_i2c_writeout(dev, &buffer[i], short_delay); + if ( 0 != err) { + /* this one is unsatisfying: some i2c slaves on some + dvb cards don't acknowledge correctly, so the saa7146 + thinks that an address error occurred. in that case, the + transaction should be retrying, even if an address error + occurred. analog saa7146 based cards extensively rely on + i2c address probing, however, and address errors indicate that a + device is really *not* there. retrying in that case + increases the time the device needs to probe greatly, so + it should be avoided. So we bail out in irq mode after an + address error and trust the saa7146 address error detection. */ + if (-EREMOTEIO == err && 0 != (SAA7146_USE_I2C_IRQ & dev->ext->flags)) + goto out; + DEB_I2C("error while sending message(s). starting again\n"); + break; + } + } + if( 0 == err ) { + err = num; + break; + } + + /* delay a bit before retrying */ + msleep(10); + + } while (err != num && retries--); + + /* quit if any error occurred */ + if (err != num) + goto out; + + /* if any things had to be read, get the results */ + if ( 0 != saa7146_i2c_msg_cleanup(msgs, num, buffer)) { + DEB_I2C("could not cleanup i2c-message\n"); + err = -EIO; + goto out; + } + + /* return the number of delivered messages */ + DEB_I2C("transmission successful. (msg:%d)\n", err); +out: + /* another bug in revision 0: the i2c-registers get uploaded randomly by other + uploads, so we better clear them out before continuing */ + if( 0 == dev->revision ) { + __le32 zero = 0; + saa7146_i2c_reset(dev); + if( 0 != saa7146_i2c_writeout(dev, &zero, short_delay)) { + pr_info("revision 0 error. this should never happen\n"); + } + } + + mutex_unlock(&dev->i2c_lock); + return err; +} + +/* utility functions */ +static int saa7146_i2c_xfer(struct i2c_adapter* adapter, struct i2c_msg *msg, int num) +{ + struct v4l2_device *v4l2_dev = i2c_get_adapdata(adapter); + struct saa7146_dev *dev = to_saa7146_dev(v4l2_dev); + + /* use helper function to transfer data */ + return saa7146_i2c_transfer(dev, msg, num, adapter->retries); +} + + +/*****************************************************************************/ +/* i2c-adapter helper functions */ + +/* exported algorithm data */ +static const struct i2c_algorithm saa7146_algo = { + .master_xfer = saa7146_i2c_xfer, + .functionality = saa7146_i2c_func, +}; + +int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate) +{ + DEB_EE("bitrate: 0x%08x\n", bitrate); + + /* enable i2c-port pins */ + saa7146_write(dev, MC1, (MASK_08 | MASK_24)); + + dev->i2c_bitrate = bitrate; + saa7146_i2c_reset(dev); + + if (i2c_adapter) { + i2c_set_adapdata(i2c_adapter, &dev->v4l2_dev); + i2c_adapter->dev.parent = &dev->pci->dev; + i2c_adapter->algo = &saa7146_algo; + i2c_adapter->algo_data = NULL; + i2c_adapter->timeout = SAA7146_I2C_TIMEOUT; + i2c_adapter->retries = SAA7146_I2C_RETRIES; + } + + return 0; +} diff --git a/drivers/staging/media/deprecated/saa7146/common/saa7146_vbi.c b/drivers/staging/media/deprecated/saa7146/common/saa7146_vbi.c new file mode 100644 index 000000000..2d4a05d7b --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/saa7146_vbi.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "saa7146_vv.h" + +static int vbi_pixel_to_capture = 720 * 2; + +static int vbi_workaround(struct saa7146_dev *dev) +{ + struct saa7146_vv *vv = dev->vv_data; + + u32 *cpu; + dma_addr_t dma_addr; + + int count = 0; + int i; + + DECLARE_WAITQUEUE(wait, current); + + DEB_VBI("dev:%p\n", dev); + + /* once again, a bug in the saa7146: the brs acquisition + is buggy and especially the BXO-counter does not work + as specified. there is this workaround, but please + don't let me explain it. ;-) */ + + cpu = dma_alloc_coherent(&dev->pci->dev, 4096, &dma_addr, GFP_KERNEL); + if (NULL == cpu) + return -ENOMEM; + + /* setup some basic programming, just for the workaround */ + saa7146_write(dev, BASE_EVEN3, dma_addr); + saa7146_write(dev, BASE_ODD3, dma_addr+vbi_pixel_to_capture); + saa7146_write(dev, PROT_ADDR3, dma_addr+4096); + saa7146_write(dev, PITCH3, vbi_pixel_to_capture); + saa7146_write(dev, BASE_PAGE3, 0x0); + saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0)); + saa7146_write(dev, MC2, MASK_04|MASK_20); + + /* load brs-control register */ + WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); + /* BXO = 1h, BRS to outbound */ + WRITE_RPS1(0xc000008c); + /* wait for vbi_a or vbi_b*/ + if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) { + DEB_D("...using port b\n"); + WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_E_FID_B); + WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_O_FID_B); +/* + WRITE_RPS1(CMD_PAUSE | MASK_09); +*/ + } else { + DEB_D("...using port a\n"); + WRITE_RPS1(CMD_PAUSE | MASK_10); + } + /* upload brs */ + WRITE_RPS1(CMD_UPLOAD | MASK_08); + /* load brs-control register */ + WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); + /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */ + WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19); + /* wait for brs_done */ + WRITE_RPS1(CMD_PAUSE | MASK_08); + /* upload brs */ + WRITE_RPS1(CMD_UPLOAD | MASK_08); + /* load video-dma3 NumLines3 and NumBytes3 */ + WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4)); + /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */ + WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture)); + /* load brs-control register */ + WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); + /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */ + WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start + /* wait for brs_done */ + WRITE_RPS1(CMD_PAUSE | MASK_08); + /* upload brs and video-dma3*/ + WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04); + /* load mc2 register: enable dma3 */ + WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4)); + WRITE_RPS1(MASK_20 | MASK_04); + /* generate interrupt */ + WRITE_RPS1(CMD_INTERRUPT); + /* stop rps1 */ + WRITE_RPS1(CMD_STOP); + + /* we have to do the workaround twice to be sure that + everything is ok */ + for(i = 0; i < 2; i++) { + + /* indicate to the irq handler that we do the workaround */ + saa7146_write(dev, MC2, MASK_31|MASK_15); + + saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0)); + saa7146_write(dev, MC2, MASK_04|MASK_20); + + /* enable rps1 irqs */ + SAA7146_IER_ENABLE(dev,MASK_28); + + /* prepare to wait to be woken up by the irq-handler */ + add_wait_queue(&vv->vbi_wq, &wait); + set_current_state(TASK_INTERRUPTIBLE); + + /* start rps1 to enable workaround */ + saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); + saa7146_write(dev, MC1, (MASK_13 | MASK_29)); + + schedule(); + + DEB_VBI("brs bug workaround %d/1\n", i); + + remove_wait_queue(&vv->vbi_wq, &wait); + __set_current_state(TASK_RUNNING); + + /* disable rps1 irqs */ + SAA7146_IER_DISABLE(dev,MASK_28); + + /* stop video-dma3 */ + saa7146_write(dev, MC1, MASK_20); + + if(signal_pending(current)) { + + DEB_VBI("aborted (rps:0x%08x)\n", + saa7146_read(dev, RPS_ADDR1)); + + /* stop rps1 for sure */ + saa7146_write(dev, MC1, MASK_29); + + dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr); + return -EINTR; + } + } + + dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr); + return 0; +} + +static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next) +{ + struct saa7146_vv *vv = dev->vv_data; + + struct saa7146_video_dma vdma3; + + int count = 0; + unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B; + unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B; + +/* + vdma3.base_even = 0xc8000000+2560*70; + vdma3.base_odd = 0xc8000000; + vdma3.prot_addr = 0xc8000000+2560*164; + vdma3.pitch = 2560; + vdma3.base_page = 0; + vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above! +*/ + vdma3.base_even = buf->pt[2].offset; + vdma3.base_odd = buf->pt[2].offset + 16 * vbi_pixel_to_capture; + vdma3.prot_addr = buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture; + vdma3.pitch = vbi_pixel_to_capture; + vdma3.base_page = buf->pt[2].dma | ME1; + vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture; + + saa7146_write_out_dma(dev, 3, &vdma3); + + /* write beginning of rps-program */ + count = 0; + + /* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */ + + /* we don't wait here for the first field anymore. this is different from the video + capture and might cause that the first buffer is only half filled (with only + one field). but since this is some sort of streaming data, this is not that negative. + but by doing this, we can use the whole engine from videobuf-dma-sg.c... */ + +/* + WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait); + WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait); +*/ + /* set bit 1 */ + WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4)); + WRITE_RPS1(MASK_28 | MASK_12); + + /* turn on video-dma3 */ + WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4)); + WRITE_RPS1(MASK_04 | MASK_20); /* => mask */ + WRITE_RPS1(MASK_04 | MASK_20); /* => values */ + + /* wait for o_fid_a/b / e_fid_a/b toggle */ + WRITE_RPS1(CMD_PAUSE | o_wait); + WRITE_RPS1(CMD_PAUSE | e_wait); + + /* generate interrupt */ + WRITE_RPS1(CMD_INTERRUPT); + + /* stop */ + WRITE_RPS1(CMD_STOP); + + /* enable rps1 irqs */ + SAA7146_IER_ENABLE(dev, MASK_28); + + /* write the address of the rps-program */ + saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); + + /* turn on rps */ + saa7146_write(dev, MC1, (MASK_13 | MASK_29)); +} + +static int buffer_activate(struct saa7146_dev *dev, + struct saa7146_buf *buf, + struct saa7146_buf *next) +{ + struct saa7146_vv *vv = dev->vv_data; + buf->vb.state = VIDEOBUF_ACTIVE; + + DEB_VBI("dev:%p, buf:%p, next:%p\n", dev, buf, next); + saa7146_set_vbi_capture(dev,buf,next); + + mod_timer(&vv->vbi_dmaq.timeout, jiffies+BUFFER_TIMEOUT); + return 0; +} + +static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,enum v4l2_field field) +{ + struct file *file = q->priv_data; + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct saa7146_buf *buf = (struct saa7146_buf *)vb; + + int err = 0; + int lines, llength, size; + + lines = 16 * 2 ; /* 2 fields */ + llength = vbi_pixel_to_capture; + size = lines * llength; + + DEB_VBI("vb:%p\n", vb); + + if (0 != buf->vb.baddr && buf->vb.bsize < size) { + DEB_VBI("size mismatch\n"); + return -EINVAL; + } + + if (buf->vb.size != size) + saa7146_dma_free(dev,q,buf); + + if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { + struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb); + + buf->vb.width = llength; + buf->vb.height = lines; + buf->vb.size = size; + buf->vb.field = field; // FIXME: check this + + saa7146_pgtable_free(dev->pci, &buf->pt[2]); + saa7146_pgtable_alloc(dev->pci, &buf->pt[2]); + + err = videobuf_iolock(q,&buf->vb, NULL); + if (err) + goto oops; + err = saa7146_pgtable_build_single(dev->pci, &buf->pt[2], + dma->sglist, dma->sglen); + if (0 != err) + return err; + } + buf->vb.state = VIDEOBUF_PREPARED; + buf->activate = buffer_activate; + + return 0; + + oops: + DEB_VBI("error out\n"); + saa7146_dma_free(dev,q,buf); + + return err; +} + +static int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size) +{ + int llength,lines; + + lines = 16 * 2 ; /* 2 fields */ + llength = vbi_pixel_to_capture; + + *size = lines * llength; + *count = 2; + + DEB_VBI("count:%d, size:%d\n", *count, *size); + + return 0; +} + +static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct file *file = q->priv_data; + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_buf *buf = (struct saa7146_buf *)vb; + + DEB_VBI("vb:%p\n", vb); + saa7146_buffer_queue(dev, &vv->vbi_dmaq, buf); +} + +static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct file *file = q->priv_data; + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct saa7146_buf *buf = (struct saa7146_buf *)vb; + + DEB_VBI("vb:%p\n", vb); + saa7146_dma_free(dev,q,buf); +} + +static const struct videobuf_queue_ops vbi_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +/* ------------------------------------------------------------------ */ + +static void vbi_stop(struct saa7146_fh *fh, struct file *file) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + unsigned long flags; + DEB_VBI("dev:%p, fh:%p\n", dev, fh); + + spin_lock_irqsave(&dev->slock,flags); + + /* disable rps1 */ + saa7146_write(dev, MC1, MASK_29); + + /* disable rps1 irqs */ + SAA7146_IER_DISABLE(dev, MASK_28); + + /* shut down dma 3 transfers */ + saa7146_write(dev, MC1, MASK_20); + + if (vv->vbi_dmaq.curr) + saa7146_buffer_finish(dev, &vv->vbi_dmaq, VIDEOBUF_DONE); + + videobuf_queue_cancel(&fh->vbi_q); + + vv->vbi_streaming = NULL; + + del_timer(&vv->vbi_dmaq.timeout); + del_timer(&vv->vbi_read_timeout); + + spin_unlock_irqrestore(&dev->slock, flags); +} + +static void vbi_read_timeout(struct timer_list *t) +{ + struct saa7146_vv *vv = from_timer(vv, t, vbi_read_timeout); + struct file *file = vv->vbi_read_timeout_file; + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + + DEB_VBI("dev:%p, fh:%p\n", dev, fh); + + vbi_stop(fh, file); +} + +static void vbi_init(struct saa7146_dev *dev, struct saa7146_vv *vv) +{ + DEB_VBI("dev:%p\n", dev); + + INIT_LIST_HEAD(&vv->vbi_dmaq.queue); + + timer_setup(&vv->vbi_dmaq.timeout, saa7146_buffer_timeout, 0); + vv->vbi_dmaq.dev = dev; + + init_waitqueue_head(&vv->vbi_wq); +} + +static int vbi_open(struct saa7146_dev *dev, struct file *file) +{ + struct saa7146_fh *fh = file->private_data; + struct saa7146_vv *vv = fh->dev->vv_data; + + u32 arbtr_ctrl = saa7146_read(dev, PCI_BT_V1); + int ret = 0; + + DEB_VBI("dev:%p, fh:%p\n", dev, fh); + + ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS); + if (0 == ret) { + DEB_S("cannot get vbi RESOURCE_DMA3_BRS resource\n"); + return -EBUSY; + } + + /* adjust arbitrition control for video dma 3 */ + arbtr_ctrl &= ~0x1f0000; + arbtr_ctrl |= 0x1d0000; + saa7146_write(dev, PCI_BT_V1, arbtr_ctrl); + saa7146_write(dev, MC2, (MASK_04|MASK_20)); + + videobuf_queue_sg_init(&fh->vbi_q, &vbi_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VBI_CAPTURE, + V4L2_FIELD_SEQ_TB, // FIXME: does this really work? + sizeof(struct saa7146_buf), + file, &dev->v4l2_lock); + + vv->vbi_read_timeout.function = vbi_read_timeout; + vv->vbi_read_timeout_file = file; + + /* initialize the brs */ + if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) { + saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19)); + } else { + saa7146_write(dev, BRS_CTRL, 0x00000001); + + if (0 != (ret = vbi_workaround(dev))) { + DEB_VBI("vbi workaround failed!\n"); + /* return ret;*/ + } + } + + /* upload brs register */ + saa7146_write(dev, MC2, (MASK_08|MASK_24)); + return 0; +} + +static void vbi_close(struct saa7146_dev *dev, struct file *file) +{ + struct saa7146_fh *fh = file->private_data; + struct saa7146_vv *vv = dev->vv_data; + DEB_VBI("dev:%p, fh:%p\n", dev, fh); + + if( fh == vv->vbi_streaming ) { + vbi_stop(fh, file); + } + saa7146_res_free(fh, RESOURCE_DMA3_BRS); +} + +static void vbi_irq_done(struct saa7146_dev *dev, unsigned long status) +{ + struct saa7146_vv *vv = dev->vv_data; + spin_lock(&dev->slock); + + if (vv->vbi_dmaq.curr) { + DEB_VBI("dev:%p, curr:%p\n", dev, vv->vbi_dmaq.curr); + /* this must be += 2, one count for each field */ + vv->vbi_fieldcount+=2; + vv->vbi_dmaq.curr->vb.field_count = vv->vbi_fieldcount; + saa7146_buffer_finish(dev, &vv->vbi_dmaq, VIDEOBUF_DONE); + } else { + DEB_VBI("dev:%p\n", dev); + } + saa7146_buffer_next(dev, &vv->vbi_dmaq, 1); + + spin_unlock(&dev->slock); +} + +static ssize_t vbi_read(struct file *file, char __user *data, size_t count, loff_t *ppos) +{ + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + ssize_t ret = 0; + + DEB_VBI("dev:%p, fh:%p\n", dev, fh); + + if( NULL == vv->vbi_streaming ) { + // fixme: check if dma3 is available + // fixme: activate vbi engine here if necessary. (really?) + vv->vbi_streaming = fh; + } + + if( fh != vv->vbi_streaming ) { + DEB_VBI("open %p is already using vbi capture\n", + vv->vbi_streaming); + return -EBUSY; + } + + mod_timer(&vv->vbi_read_timeout, jiffies+BUFFER_TIMEOUT); + ret = videobuf_read_stream(&fh->vbi_q, data, count, ppos, 1, + file->f_flags & O_NONBLOCK); +/* + printk("BASE_ODD3: 0x%08x\n", saa7146_read(dev, BASE_ODD3)); + printk("BASE_EVEN3: 0x%08x\n", saa7146_read(dev, BASE_EVEN3)); + printk("PROT_ADDR3: 0x%08x\n", saa7146_read(dev, PROT_ADDR3)); + printk("PITCH3: 0x%08x\n", saa7146_read(dev, PITCH3)); + printk("BASE_PAGE3: 0x%08x\n", saa7146_read(dev, BASE_PAGE3)); + printk("NUM_LINE_BYTE3: 0x%08x\n", saa7146_read(dev, NUM_LINE_BYTE3)); + printk("BRS_CTRL: 0x%08x\n", saa7146_read(dev, BRS_CTRL)); +*/ + return ret; +} + +const struct saa7146_use_ops saa7146_vbi_uops = { + .init = vbi_init, + .open = vbi_open, + .release = vbi_close, + .irq_done = vbi_irq_done, + .read = vbi_read, +}; diff --git a/drivers/staging/media/deprecated/saa7146/common/saa7146_video.c b/drivers/staging/media/deprecated/saa7146/common/saa7146_video.c new file mode 100644 index 000000000..4598a4423 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/saa7146_video.c @@ -0,0 +1,1286 @@ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include "saa7146_vv.h" + +static int max_memory = 32; + +module_param(max_memory, int, 0644); +MODULE_PARM_DESC(max_memory, "maximum memory usage for capture buffers (default: 32Mb)"); + +#define IS_CAPTURE_ACTIVE(fh) \ + (((vv->video_status & STATUS_CAPTURE) != 0) && (vv->video_fh == fh)) + +#define IS_OVERLAY_ACTIVE(fh) \ + (((vv->video_status & STATUS_OVERLAY) != 0) && (vv->video_fh == fh)) + +/* format descriptions for capture and preview */ +static struct saa7146_format formats[] = { + { + .pixelformat = V4L2_PIX_FMT_RGB332, + .trans = RGB08_COMPOSED, + .depth = 8, + .flags = 0, + }, { + .pixelformat = V4L2_PIX_FMT_RGB565, + .trans = RGB16_COMPOSED, + .depth = 16, + .flags = 0, + }, { + .pixelformat = V4L2_PIX_FMT_BGR24, + .trans = RGB24_COMPOSED, + .depth = 24, + .flags = 0, + }, { + .pixelformat = V4L2_PIX_FMT_BGR32, + .trans = RGB32_COMPOSED, + .depth = 32, + .flags = 0, + }, { + .pixelformat = V4L2_PIX_FMT_RGB32, + .trans = RGB32_COMPOSED, + .depth = 32, + .flags = 0, + .swap = 0x2, + }, { + .pixelformat = V4L2_PIX_FMT_GREY, + .trans = Y8, + .depth = 8, + .flags = 0, + }, { + .pixelformat = V4L2_PIX_FMT_YUV422P, + .trans = YUV422_DECOMPOSED, + .depth = 16, + .flags = FORMAT_BYTE_SWAP|FORMAT_IS_PLANAR, + }, { + .pixelformat = V4L2_PIX_FMT_YVU420, + .trans = YUV420_DECOMPOSED, + .depth = 12, + .flags = FORMAT_BYTE_SWAP|FORMAT_IS_PLANAR, + }, { + .pixelformat = V4L2_PIX_FMT_YUV420, + .trans = YUV420_DECOMPOSED, + .depth = 12, + .flags = FORMAT_IS_PLANAR, + }, { + .pixelformat = V4L2_PIX_FMT_UYVY, + .trans = YUV422_COMPOSED, + .depth = 16, + .flags = 0, + } +}; + +/* unfortunately, the saa7146 contains a bug which prevents it from doing on-the-fly byte swaps. + due to this, it's impossible to provide additional *packed* formats, which are simply byte swapped + (like V4L2_PIX_FMT_YUYV) ... 8-( */ + +struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(formats); i++) { + if (formats[i].pixelformat == fourcc) { + return formats+i; + } + } + + DEB_D("unknown pixelformat:'%4.4s'\n", (char *)&fourcc); + return NULL; +} + +static int vidioc_try_fmt_vid_overlay(struct file *file, void *fh, struct v4l2_format *f); + +int saa7146_start_preview(struct saa7146_fh *fh) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + struct v4l2_format fmt; + int ret = 0, err = 0; + + DEB_EE("dev:%p, fh:%p\n", dev, fh); + + /* check if we have overlay information */ + if (vv->ov.fh == NULL) { + DEB_D("no overlay data available. try S_FMT first.\n"); + return -EAGAIN; + } + + /* check if streaming capture is running */ + if (IS_CAPTURE_ACTIVE(fh) != 0) { + DEB_D("streaming capture is active\n"); + return -EBUSY; + } + + /* check if overlay is running */ + if (IS_OVERLAY_ACTIVE(fh) != 0) { + if (vv->video_fh == fh) { + DEB_D("overlay is already active\n"); + return 0; + } + DEB_D("overlay is already active in another open\n"); + return -EBUSY; + } + + if (0 == saa7146_res_get(fh, RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP)) { + DEB_D("cannot get necessary overlay resources\n"); + return -EBUSY; + } + + fmt.fmt.win = vv->ov.win; + err = vidioc_try_fmt_vid_overlay(NULL, fh, &fmt); + if (0 != err) { + saa7146_res_free(vv->video_fh, RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP); + return -EBUSY; + } + vv->ov.win = fmt.fmt.win; + + DEB_D("%dx%d+%d+%d 0x%08x field=%s\n", + vv->ov.win.w.width, vv->ov.win.w.height, + vv->ov.win.w.left, vv->ov.win.w.top, + vv->ov_fmt->pixelformat, v4l2_field_names[vv->ov.win.field]); + + if (0 != (ret = saa7146_enable_overlay(fh))) { + DEB_D("enabling overlay failed: %d\n", ret); + saa7146_res_free(vv->video_fh, RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP); + return ret; + } + + vv->video_status = STATUS_OVERLAY; + vv->video_fh = fh; + + return 0; +} +EXPORT_SYMBOL_GPL(saa7146_start_preview); + +int saa7146_stop_preview(struct saa7146_fh *fh) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + + DEB_EE("dev:%p, fh:%p\n", dev, fh); + + /* check if streaming capture is running */ + if (IS_CAPTURE_ACTIVE(fh) != 0) { + DEB_D("streaming capture is active\n"); + return -EBUSY; + } + + /* check if overlay is running at all */ + if ((vv->video_status & STATUS_OVERLAY) == 0) { + DEB_D("no active overlay\n"); + return 0; + } + + if (vv->video_fh != fh) { + DEB_D("overlay is active, but in another open\n"); + return -EBUSY; + } + + vv->video_status = 0; + vv->video_fh = NULL; + + saa7146_disable_overlay(fh); + + saa7146_res_free(fh, RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP); + + return 0; +} +EXPORT_SYMBOL_GPL(saa7146_stop_preview); + +/********************************************************************************/ +/* common pagetable functions */ + +static int saa7146_pgtable_build(struct saa7146_dev *dev, struct saa7146_buf *buf) +{ + struct pci_dev *pci = dev->pci; + struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb); + struct scatterlist *list = dma->sglist; + int length = dma->sglen; + struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev,buf->fmt->pixelformat); + + DEB_EE("dev:%p, buf:%p, sg_len:%d\n", dev, buf, length); + + if( 0 != IS_PLANAR(sfmt->trans)) { + struct saa7146_pgtable *pt1 = &buf->pt[0]; + struct saa7146_pgtable *pt2 = &buf->pt[1]; + struct saa7146_pgtable *pt3 = &buf->pt[2]; + __le32 *ptr1, *ptr2, *ptr3; + __le32 fill; + + int size = buf->fmt->width*buf->fmt->height; + int i,p,m1,m2,m3,o1,o2; + + switch( sfmt->depth ) { + case 12: { + /* create some offsets inside the page table */ + m1 = ((size+PAGE_SIZE)/PAGE_SIZE)-1; + m2 = ((size+(size/4)+PAGE_SIZE)/PAGE_SIZE)-1; + m3 = ((size+(size/2)+PAGE_SIZE)/PAGE_SIZE)-1; + o1 = size%PAGE_SIZE; + o2 = (size+(size/4))%PAGE_SIZE; + DEB_CAP("size:%d, m1:%d, m2:%d, m3:%d, o1:%d, o2:%d\n", + size, m1, m2, m3, o1, o2); + break; + } + case 16: { + /* create some offsets inside the page table */ + m1 = ((size+PAGE_SIZE)/PAGE_SIZE)-1; + m2 = ((size+(size/2)+PAGE_SIZE)/PAGE_SIZE)-1; + m3 = ((2*size+PAGE_SIZE)/PAGE_SIZE)-1; + o1 = size%PAGE_SIZE; + o2 = (size+(size/2))%PAGE_SIZE; + DEB_CAP("size:%d, m1:%d, m2:%d, m3:%d, o1:%d, o2:%d\n", + size, m1, m2, m3, o1, o2); + break; + } + default: { + return -1; + } + } + + ptr1 = pt1->cpu; + ptr2 = pt2->cpu; + ptr3 = pt3->cpu; + + /* walk all pages, copy all page addresses to ptr1 */ + for (i = 0; i < length; i++, list++) { + for (p = 0; p * 4096 < sg_dma_len(list); p++, ptr1++) + *ptr1 = cpu_to_le32(sg_dma_address(list) - list->offset); + } +/* + ptr1 = pt1->cpu; + for(j=0;j<40;j++) { + printk("ptr1 %d: 0x%08x\n",j,ptr1[j]); + } +*/ + + /* if we have a user buffer, the first page may not be + aligned to a page boundary. */ + pt1->offset = dma->sglist->offset; + pt2->offset = pt1->offset+o1; + pt3->offset = pt1->offset+o2; + + /* create video-dma2 page table */ + ptr1 = pt1->cpu; + for(i = m1; i <= m2 ; i++, ptr2++) { + *ptr2 = ptr1[i]; + } + fill = *(ptr2-1); + for(;i<1024;i++,ptr2++) { + *ptr2 = fill; + } + /* create video-dma3 page table */ + ptr1 = pt1->cpu; + for(i = m2; i <= m3; i++,ptr3++) { + *ptr3 = ptr1[i]; + } + fill = *(ptr3-1); + for(;i<1024;i++,ptr3++) { + *ptr3 = fill; + } + /* finally: finish up video-dma1 page table */ + ptr1 = pt1->cpu+m1; + fill = pt1->cpu[m1]; + for(i=m1;i<1024;i++,ptr1++) { + *ptr1 = fill; + } +/* + ptr1 = pt1->cpu; + ptr2 = pt2->cpu; + ptr3 = pt3->cpu; + for(j=0;j<40;j++) { + printk("ptr1 %d: 0x%08x\n",j,ptr1[j]); + } + for(j=0;j<40;j++) { + printk("ptr2 %d: 0x%08x\n",j,ptr2[j]); + } + for(j=0;j<40;j++) { + printk("ptr3 %d: 0x%08x\n",j,ptr3[j]); + } +*/ + } else { + struct saa7146_pgtable *pt = &buf->pt[0]; + return saa7146_pgtable_build_single(pci, pt, list, length); + } + + return 0; +} + + +/********************************************************************************/ +/* file operations */ + +static int video_begin(struct saa7146_fh *fh) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_format *fmt = NULL; + unsigned int resource; + int ret = 0, err = 0; + + DEB_EE("dev:%p, fh:%p\n", dev, fh); + + if ((vv->video_status & STATUS_CAPTURE) != 0) { + if (vv->video_fh == fh) { + DEB_S("already capturing\n"); + return 0; + } + DEB_S("already capturing in another open\n"); + return -EBUSY; + } + + if ((vv->video_status & STATUS_OVERLAY) != 0) { + DEB_S("warning: suspending overlay video for streaming capture\n"); + vv->ov_suspend = vv->video_fh; + err = saa7146_stop_preview(vv->video_fh); /* side effect: video_status is now 0, video_fh is NULL */ + if (0 != err) { + DEB_D("suspending video failed. aborting\n"); + return err; + } + } + + fmt = saa7146_format_by_fourcc(dev, vv->video_fmt.pixelformat); + /* we need to have a valid format set here */ + if (!fmt) + return -EINVAL; + + if (0 != (fmt->flags & FORMAT_IS_PLANAR)) { + resource = RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP|RESOURCE_DMA3_BRS; + } else { + resource = RESOURCE_DMA1_HPS; + } + + ret = saa7146_res_get(fh, resource); + if (0 == ret) { + DEB_S("cannot get capture resource %d\n", resource); + if (vv->ov_suspend != NULL) { + saa7146_start_preview(vv->ov_suspend); + vv->ov_suspend = NULL; + } + return -EBUSY; + } + + /* clear out beginning of streaming bit (rps register 0)*/ + saa7146_write(dev, MC2, MASK_27 ); + + /* enable rps0 irqs */ + SAA7146_IER_ENABLE(dev, MASK_27); + + vv->video_fh = fh; + vv->video_status = STATUS_CAPTURE; + + return 0; +} + +static int video_end(struct saa7146_fh *fh, struct file *file) +{ + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_dmaqueue *q = &vv->video_dmaq; + struct saa7146_format *fmt = NULL; + unsigned long flags; + unsigned int resource; + u32 dmas = 0; + DEB_EE("dev:%p, fh:%p\n", dev, fh); + + if ((vv->video_status & STATUS_CAPTURE) != STATUS_CAPTURE) { + DEB_S("not capturing\n"); + return 0; + } + + if (vv->video_fh != fh) { + DEB_S("capturing, but in another open\n"); + return -EBUSY; + } + + fmt = saa7146_format_by_fourcc(dev, vv->video_fmt.pixelformat); + /* we need to have a valid format set here */ + if (!fmt) + return -EINVAL; + + if (0 != (fmt->flags & FORMAT_IS_PLANAR)) { + resource = RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP|RESOURCE_DMA3_BRS; + dmas = MASK_22 | MASK_21 | MASK_20; + } else { + resource = RESOURCE_DMA1_HPS; + dmas = MASK_22; + } + spin_lock_irqsave(&dev->slock,flags); + + /* disable rps0 */ + saa7146_write(dev, MC1, MASK_28); + + /* disable rps0 irqs */ + SAA7146_IER_DISABLE(dev, MASK_27); + + /* shut down all used video dma transfers */ + saa7146_write(dev, MC1, dmas); + + if (q->curr) + saa7146_buffer_finish(dev, q, VIDEOBUF_DONE); + + spin_unlock_irqrestore(&dev->slock, flags); + + vv->video_fh = NULL; + vv->video_status = 0; + + saa7146_res_free(fh, resource); + + if (vv->ov_suspend != NULL) { + saa7146_start_preview(vv->ov_suspend); + vv->ov_suspend = NULL; + } + + return 0; +} + +static int vidioc_querycap(struct file *file, void *fh, struct v4l2_capability *cap) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + + strscpy((char *)cap->driver, "saa7146 v4l2", sizeof(cap->driver)); + strscpy((char *)cap->card, dev->ext->name, sizeof(cap->card)); + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_READWRITE | V4L2_CAP_STREAMING | + V4L2_CAP_DEVICE_CAPS; + cap->capabilities |= dev->ext_vv_data->capabilities; + return 0; +} + +static int vidioc_g_fbuf(struct file *file, void *fh, struct v4l2_framebuffer *fb) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + + *fb = vv->ov_fb; + fb->capability = V4L2_FBUF_CAP_LIST_CLIPPING; + fb->flags = V4L2_FBUF_FLAG_PRIMARY; + return 0; +} + +static int vidioc_s_fbuf(struct file *file, void *fh, const struct v4l2_framebuffer *fb) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_format *fmt; + + DEB_EE("VIDIOC_S_FBUF\n"); + + if (!capable(CAP_SYS_ADMIN) && !capable(CAP_SYS_RAWIO)) + return -EPERM; + + /* check args */ + fmt = saa7146_format_by_fourcc(dev, fb->fmt.pixelformat); + if (NULL == fmt) + return -EINVAL; + + /* planar formats are not allowed for overlay video, clipping and video dma would clash */ + if (fmt->flags & FORMAT_IS_PLANAR) + DEB_S("planar pixelformat '%4.4s' not allowed for overlay\n", + (char *)&fmt->pixelformat); + + /* check if overlay is running */ + if (IS_OVERLAY_ACTIVE(fh) != 0) { + if (vv->video_fh != fh) { + DEB_D("refusing to change framebuffer information while overlay is active in another open\n"); + return -EBUSY; + } + } + + /* ok, accept it */ + vv->ov_fb = *fb; + vv->ov_fmt = fmt; + + if (vv->ov_fb.fmt.bytesperline < vv->ov_fb.fmt.width) { + vv->ov_fb.fmt.bytesperline = vv->ov_fb.fmt.width * fmt->depth / 8; + DEB_D("setting bytesperline to %d\n", vv->ov_fb.fmt.bytesperline); + } + return 0; +} + +static int vidioc_enum_fmt_vid_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) +{ + if (f->index >= ARRAY_SIZE(formats)) + return -EINVAL; + f->pixelformat = formats[f->index].pixelformat; + return 0; +} + +int saa7146_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct saa7146_dev *dev = container_of(ctrl->handler, + struct saa7146_dev, ctrl_handler); + struct saa7146_vv *vv = dev->vv_data; + u32 val; + + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + val = saa7146_read(dev, BCS_CTRL); + val &= 0x00ffffff; + val |= (ctrl->val << 24); + saa7146_write(dev, BCS_CTRL, val); + saa7146_write(dev, MC2, MASK_22 | MASK_06); + break; + + case V4L2_CID_CONTRAST: + val = saa7146_read(dev, BCS_CTRL); + val &= 0xff00ffff; + val |= (ctrl->val << 16); + saa7146_write(dev, BCS_CTRL, val); + saa7146_write(dev, MC2, MASK_22 | MASK_06); + break; + + case V4L2_CID_SATURATION: + val = saa7146_read(dev, BCS_CTRL); + val &= 0xffffff00; + val |= (ctrl->val << 0); + saa7146_write(dev, BCS_CTRL, val); + saa7146_write(dev, MC2, MASK_22 | MASK_06); + break; + + case V4L2_CID_HFLIP: + /* fixme: we can support changing VFLIP and HFLIP here... */ + if ((vv->video_status & STATUS_CAPTURE)) + return -EBUSY; + vv->hflip = ctrl->val; + break; + + case V4L2_CID_VFLIP: + if ((vv->video_status & STATUS_CAPTURE)) + return -EBUSY; + vv->vflip = ctrl->val; + break; + + default: + return -EINVAL; + } + + if ((vv->video_status & STATUS_OVERLAY) != 0) { /* CHECK: && (vv->video_fh == fh)) */ + struct saa7146_fh *fh = vv->video_fh; + + saa7146_stop_preview(fh); + saa7146_start_preview(fh); + } + return 0; +} + +static int vidioc_g_parm(struct file *file, void *fh, + struct v4l2_streamparm *parm) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + parm->parm.capture.readbuffers = 1; + v4l2_video_std_frame_period(vv->standard->id, + &parm->parm.capture.timeperframe); + return 0; +} + +static int vidioc_g_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + + f->fmt.pix = vv->video_fmt; + return 0; +} + +static int vidioc_g_fmt_vid_overlay(struct file *file, void *fh, struct v4l2_format *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + + f->fmt.win = vv->ov.win; + return 0; +} + +static int vidioc_g_fmt_vbi_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + + f->fmt.vbi = vv->vbi_fmt; + return 0; +} + +static int vidioc_try_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_format *fmt; + enum v4l2_field field; + int maxw, maxh; + int calc_bpl; + + DEB_EE("V4L2_BUF_TYPE_VIDEO_CAPTURE: dev:%p, fh:%p\n", dev, fh); + + fmt = saa7146_format_by_fourcc(dev, f->fmt.pix.pixelformat); + if (NULL == fmt) + return -EINVAL; + + field = f->fmt.pix.field; + maxw = vv->standard->h_max_out; + maxh = vv->standard->v_max_out; + + if (V4L2_FIELD_ANY == field) { + field = (f->fmt.pix.height > maxh / 2) + ? V4L2_FIELD_INTERLACED + : V4L2_FIELD_BOTTOM; + } + switch (field) { + case V4L2_FIELD_ALTERNATE: + vv->last_field = V4L2_FIELD_TOP; + maxh = maxh / 2; + break; + case V4L2_FIELD_TOP: + case V4L2_FIELD_BOTTOM: + vv->last_field = V4L2_FIELD_INTERLACED; + maxh = maxh / 2; + break; + case V4L2_FIELD_INTERLACED: + vv->last_field = V4L2_FIELD_INTERLACED; + break; + default: + DEB_D("no known field mode '%d'\n", field); + return -EINVAL; + } + + f->fmt.pix.field = field; + f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; + if (f->fmt.pix.width > maxw) + f->fmt.pix.width = maxw; + if (f->fmt.pix.height > maxh) + f->fmt.pix.height = maxh; + + calc_bpl = (f->fmt.pix.width * fmt->depth) / 8; + + if (f->fmt.pix.bytesperline < calc_bpl) + f->fmt.pix.bytesperline = calc_bpl; + + if (f->fmt.pix.bytesperline > (2 * PAGE_SIZE * fmt->depth) / 8) /* arbitrary constraint */ + f->fmt.pix.bytesperline = calc_bpl; + + f->fmt.pix.sizeimage = f->fmt.pix.bytesperline * f->fmt.pix.height; + DEB_D("w:%d, h:%d, bytesperline:%d, sizeimage:%d\n", + f->fmt.pix.width, f->fmt.pix.height, + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage); + + return 0; +} + + +static int vidioc_try_fmt_vid_overlay(struct file *file, void *fh, struct v4l2_format *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + struct v4l2_window *win = &f->fmt.win; + enum v4l2_field field; + int maxw, maxh; + + DEB_EE("dev:%p\n", dev); + + if (NULL == vv->ov_fb.base) { + DEB_D("no fb base set\n"); + return -EINVAL; + } + if (NULL == vv->ov_fmt) { + DEB_D("no fb fmt set\n"); + return -EINVAL; + } + if (win->w.width < 48 || win->w.height < 32) { + DEB_D("min width/height. (%d,%d)\n", + win->w.width, win->w.height); + return -EINVAL; + } + if (win->clipcount > 16) { + DEB_D("clipcount too big\n"); + return -EINVAL; + } + + field = win->field; + maxw = vv->standard->h_max_out; + maxh = vv->standard->v_max_out; + + if (V4L2_FIELD_ANY == field) { + field = (win->w.height > maxh / 2) + ? V4L2_FIELD_INTERLACED + : V4L2_FIELD_TOP; + } + switch (field) { + case V4L2_FIELD_TOP: + case V4L2_FIELD_BOTTOM: + case V4L2_FIELD_ALTERNATE: + maxh = maxh / 2; + break; + case V4L2_FIELD_INTERLACED: + break; + default: + DEB_D("no known field mode '%d'\n", field); + return -EINVAL; + } + + win->field = field; + if (win->w.width > maxw) + win->w.width = maxw; + if (win->w.height > maxh) + win->w.height = maxh; + + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *__fh, struct v4l2_format *f) +{ + struct saa7146_fh *fh = __fh; + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + int err; + + DEB_EE("V4L2_BUF_TYPE_VIDEO_CAPTURE: dev:%p, fh:%p\n", dev, fh); + if (IS_CAPTURE_ACTIVE(fh) != 0) { + DEB_EE("streaming capture is active\n"); + return -EBUSY; + } + err = vidioc_try_fmt_vid_cap(file, fh, f); + if (0 != err) + return err; + vv->video_fmt = f->fmt.pix; + DEB_EE("set to pixelformat '%4.4s'\n", + (char *)&vv->video_fmt.pixelformat); + return 0; +} + +static int vidioc_s_fmt_vid_overlay(struct file *file, void *__fh, struct v4l2_format *f) +{ + struct saa7146_fh *fh = __fh; + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + int err; + + DEB_EE("V4L2_BUF_TYPE_VIDEO_OVERLAY: dev:%p, fh:%p\n", dev, fh); + err = vidioc_try_fmt_vid_overlay(file, fh, f); + if (0 != err) + return err; + vv->ov.win = f->fmt.win; + vv->ov.nclips = f->fmt.win.clipcount; + if (vv->ov.nclips > 16) + vv->ov.nclips = 16; + memcpy(vv->ov.clips, f->fmt.win.clips, + sizeof(struct v4l2_clip) * vv->ov.nclips); + + /* vv->ov.fh is used to indicate that we have valid overlay information, too */ + vv->ov.fh = fh; + + /* check if our current overlay is active */ + if (IS_OVERLAY_ACTIVE(fh) != 0) { + saa7146_stop_preview(fh); + saa7146_start_preview(fh); + } + return 0; +} + +static int vidioc_g_std(struct file *file, void *fh, v4l2_std_id *norm) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + + *norm = vv->standard->id; + return 0; +} + + /* the saa7146 supfhrts (used in conjunction with the saa7111a for example) + PAL / NTSC / SECAM. if your hardware does not (or does more) + -- override this function in your extension */ +/* + case VIDIOC_ENUMSTD: + { + struct v4l2_standard *e = arg; + if (e->index < 0 ) + return -EINVAL; + if( e->index < dev->ext_vv_data->num_stds ) { + DEB_EE("VIDIOC_ENUMSTD: index:%d\n", e->index); + v4l2_video_std_construct(e, dev->ext_vv_data->stds[e->index].id, dev->ext_vv_data->stds[e->index].name); + return 0; + } + return -EINVAL; + } + */ + +static int vidioc_s_std(struct file *file, void *fh, v4l2_std_id id) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct saa7146_vv *vv = dev->vv_data; + int found = 0; + int err, i; + + DEB_EE("VIDIOC_S_STD\n"); + + if ((vv->video_status & STATUS_CAPTURE) == STATUS_CAPTURE) { + DEB_D("cannot change video standard while streaming capture is active\n"); + return -EBUSY; + } + + if ((vv->video_status & STATUS_OVERLAY) != 0) { + vv->ov_suspend = vv->video_fh; + err = saa7146_stop_preview(vv->video_fh); /* side effect: video_status is now 0, video_fh is NULL */ + if (0 != err) { + DEB_D("suspending video failed. aborting\n"); + return err; + } + } + + for (i = 0; i < dev->ext_vv_data->num_stds; i++) + if (id & dev->ext_vv_data->stds[i].id) + break; + if (i != dev->ext_vv_data->num_stds) { + vv->standard = &dev->ext_vv_data->stds[i]; + if (NULL != dev->ext_vv_data->std_callback) + dev->ext_vv_data->std_callback(dev, vv->standard); + found = 1; + } + + if (vv->ov_suspend != NULL) { + saa7146_start_preview(vv->ov_suspend); + vv->ov_suspend = NULL; + } + + if (!found) { + DEB_EE("VIDIOC_S_STD: standard not found\n"); + return -EINVAL; + } + + DEB_EE("VIDIOC_S_STD: set to standard to '%s'\n", vv->standard->name); + return 0; +} + +static int vidioc_overlay(struct file *file, void *fh, unsigned int on) +{ + int err; + + DEB_D("VIDIOC_OVERLAY on:%d\n", on); + if (on) + err = saa7146_start_preview(fh); + else + err = saa7146_stop_preview(fh); + return err; +} + +static int vidioc_reqbufs(struct file *file, void *__fh, struct v4l2_requestbuffers *b) +{ + struct saa7146_fh *fh = __fh; + + if (b->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_reqbufs(&fh->video_q, b); + if (b->type == V4L2_BUF_TYPE_VBI_CAPTURE) + return videobuf_reqbufs(&fh->vbi_q, b); + return -EINVAL; +} + +static int vidioc_querybuf(struct file *file, void *__fh, struct v4l2_buffer *buf) +{ + struct saa7146_fh *fh = __fh; + + if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_querybuf(&fh->video_q, buf); + if (buf->type == V4L2_BUF_TYPE_VBI_CAPTURE) + return videobuf_querybuf(&fh->vbi_q, buf); + return -EINVAL; +} + +static int vidioc_qbuf(struct file *file, void *__fh, struct v4l2_buffer *buf) +{ + struct saa7146_fh *fh = __fh; + + if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_qbuf(&fh->video_q, buf); + if (buf->type == V4L2_BUF_TYPE_VBI_CAPTURE) + return videobuf_qbuf(&fh->vbi_q, buf); + return -EINVAL; +} + +static int vidioc_dqbuf(struct file *file, void *__fh, struct v4l2_buffer *buf) +{ + struct saa7146_fh *fh = __fh; + + if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_dqbuf(&fh->video_q, buf, file->f_flags & O_NONBLOCK); + if (buf->type == V4L2_BUF_TYPE_VBI_CAPTURE) + return videobuf_dqbuf(&fh->vbi_q, buf, file->f_flags & O_NONBLOCK); + return -EINVAL; +} + +static int vidioc_streamon(struct file *file, void *__fh, enum v4l2_buf_type type) +{ + struct saa7146_fh *fh = __fh; + int err; + + DEB_D("VIDIOC_STREAMON, type:%d\n", type); + + err = video_begin(fh); + if (err) + return err; + if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return videobuf_streamon(&fh->video_q); + if (type == V4L2_BUF_TYPE_VBI_CAPTURE) + return videobuf_streamon(&fh->vbi_q); + return -EINVAL; +} + +static int vidioc_streamoff(struct file *file, void *__fh, enum v4l2_buf_type type) +{ + struct saa7146_fh *fh = __fh; + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + int err; + + DEB_D("VIDIOC_STREAMOFF, type:%d\n", type); + + /* ugly: we need to copy some checks from video_end(), + because videobuf_streamoff() relies on the capture running. + check and fix this */ + if ((vv->video_status & STATUS_CAPTURE) != STATUS_CAPTURE) { + DEB_S("not capturing\n"); + return 0; + } + + if (vv->video_fh != fh) { + DEB_S("capturing, but in another open\n"); + return -EBUSY; + } + + err = -EINVAL; + if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + err = videobuf_streamoff(&fh->video_q); + else if (type == V4L2_BUF_TYPE_VBI_CAPTURE) + err = videobuf_streamoff(&fh->vbi_q); + if (0 != err) { + DEB_D("warning: videobuf_streamoff() failed\n"); + video_end(fh, file); + } else { + err = video_end(fh, file); + } + return err; +} + +const struct v4l2_ioctl_ops saa7146_video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay, + .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay, + .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay, + + .vidioc_overlay = vidioc_overlay, + .vidioc_g_fbuf = vidioc_g_fbuf, + .vidioc_s_fbuf = vidioc_s_fbuf, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_g_std = vidioc_g_std, + .vidioc_s_std = vidioc_s_std, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_g_parm = vidioc_g_parm, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +const struct v4l2_ioctl_ops saa7146_vbi_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_g_fmt_vbi_cap = vidioc_g_fmt_vbi_cap, + + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_g_std = vidioc_g_std, + .vidioc_s_std = vidioc_s_std, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_g_parm = vidioc_g_parm, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +/*********************************************************************************/ +/* buffer handling functions */ + +static int buffer_activate (struct saa7146_dev *dev, + struct saa7146_buf *buf, + struct saa7146_buf *next) +{ + struct saa7146_vv *vv = dev->vv_data; + + buf->vb.state = VIDEOBUF_ACTIVE; + saa7146_set_capture(dev,buf,next); + + mod_timer(&vv->video_dmaq.timeout, jiffies+BUFFER_TIMEOUT); + return 0; +} + +static void release_all_pagetables(struct saa7146_dev *dev, struct saa7146_buf *buf) +{ + saa7146_pgtable_free(dev->pci, &buf->pt[0]); + saa7146_pgtable_free(dev->pci, &buf->pt[1]); + saa7146_pgtable_free(dev->pci, &buf->pt[2]); +} + +static int buffer_prepare(struct videobuf_queue *q, + struct videobuf_buffer *vb, enum v4l2_field field) +{ + struct file *file = q->priv_data; + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_buf *buf = (struct saa7146_buf *)vb; + int size,err = 0; + + DEB_CAP("vbuf:%p\n", vb); + + /* sanity checks */ + if (vv->video_fmt.width < 48 || + vv->video_fmt.height < 32 || + vv->video_fmt.width > vv->standard->h_max_out || + vv->video_fmt.height > vv->standard->v_max_out) { + DEB_D("w (%d) / h (%d) out of bounds\n", + vv->video_fmt.width, vv->video_fmt.height); + return -EINVAL; + } + + size = vv->video_fmt.sizeimage; + if (0 != buf->vb.baddr && buf->vb.bsize < size) { + DEB_D("size mismatch\n"); + return -EINVAL; + } + + DEB_CAP("buffer_prepare [size=%dx%d,bytes=%d,fields=%s]\n", + vv->video_fmt.width, vv->video_fmt.height, + size, v4l2_field_names[vv->video_fmt.field]); + if (buf->vb.width != vv->video_fmt.width || + buf->vb.bytesperline != vv->video_fmt.bytesperline || + buf->vb.height != vv->video_fmt.height || + buf->vb.size != size || + buf->vb.field != field || + buf->vb.field != vv->video_fmt.field || + buf->fmt != &vv->video_fmt) { + saa7146_dma_free(dev,q,buf); + } + + if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { + struct saa7146_format *sfmt; + + buf->vb.bytesperline = vv->video_fmt.bytesperline; + buf->vb.width = vv->video_fmt.width; + buf->vb.height = vv->video_fmt.height; + buf->vb.size = size; + buf->vb.field = field; + buf->fmt = &vv->video_fmt; + buf->vb.field = vv->video_fmt.field; + + sfmt = saa7146_format_by_fourcc(dev,buf->fmt->pixelformat); + + release_all_pagetables(dev, buf); + if( 0 != IS_PLANAR(sfmt->trans)) { + saa7146_pgtable_alloc(dev->pci, &buf->pt[0]); + saa7146_pgtable_alloc(dev->pci, &buf->pt[1]); + saa7146_pgtable_alloc(dev->pci, &buf->pt[2]); + } else { + saa7146_pgtable_alloc(dev->pci, &buf->pt[0]); + } + + err = videobuf_iolock(q,&buf->vb, &vv->ov_fb); + if (err) + goto oops; + err = saa7146_pgtable_build(dev,buf); + if (err) + goto oops; + } + buf->vb.state = VIDEOBUF_PREPARED; + buf->activate = buffer_activate; + + return 0; + + oops: + DEB_D("error out\n"); + saa7146_dma_free(dev,q,buf); + + return err; +} + +static int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size) +{ + struct file *file = q->priv_data; + struct saa7146_fh *fh = file->private_data; + struct saa7146_vv *vv = fh->dev->vv_data; + + if (0 == *count || *count > MAX_SAA7146_CAPTURE_BUFFERS) + *count = MAX_SAA7146_CAPTURE_BUFFERS; + + *size = vv->video_fmt.sizeimage; + + /* check if we exceed the "max_memory" parameter */ + if( (*count * *size) > (max_memory*1048576) ) { + *count = (max_memory*1048576) / *size; + } + + DEB_CAP("%d buffers, %d bytes each\n", *count, *size); + + return 0; +} + +static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct file *file = q->priv_data; + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_buf *buf = (struct saa7146_buf *)vb; + + DEB_CAP("vbuf:%p\n", vb); + saa7146_buffer_queue(fh->dev, &vv->video_dmaq, buf); +} + +static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct file *file = q->priv_data; + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct saa7146_buf *buf = (struct saa7146_buf *)vb; + + DEB_CAP("vbuf:%p\n", vb); + + saa7146_dma_free(dev,q,buf); + + release_all_pagetables(dev, buf); +} + +static const struct videobuf_queue_ops video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +/********************************************************************************/ +/* file operations */ + +static void video_init(struct saa7146_dev *dev, struct saa7146_vv *vv) +{ + INIT_LIST_HEAD(&vv->video_dmaq.queue); + + timer_setup(&vv->video_dmaq.timeout, saa7146_buffer_timeout, 0); + vv->video_dmaq.dev = dev; + + /* set some default values */ + vv->standard = &dev->ext_vv_data->stds[0]; + + /* FIXME: what's this? */ + vv->current_hps_source = SAA7146_HPS_SOURCE_PORT_A; + vv->current_hps_sync = SAA7146_HPS_SYNC_PORT_A; +} + + +static int video_open(struct saa7146_dev *dev, struct file *file) +{ + struct saa7146_fh *fh = file->private_data; + + videobuf_queue_sg_init(&fh->video_q, &video_qops, + &dev->pci->dev, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct saa7146_buf), + file, &dev->v4l2_lock); + + return 0; +} + + +static void video_close(struct saa7146_dev *dev, struct file *file) +{ + struct saa7146_fh *fh = file->private_data; + struct saa7146_vv *vv = dev->vv_data; + struct videobuf_queue *q = &fh->video_q; + + if (IS_CAPTURE_ACTIVE(fh) != 0) + video_end(fh, file); + else if (IS_OVERLAY_ACTIVE(fh) != 0) + saa7146_stop_preview(fh); + + videobuf_stop(q); + /* hmm, why is this function declared void? */ +} + + +static void video_irq_done(struct saa7146_dev *dev, unsigned long st) +{ + struct saa7146_vv *vv = dev->vv_data; + struct saa7146_dmaqueue *q = &vv->video_dmaq; + + spin_lock(&dev->slock); + DEB_CAP("called\n"); + + /* only finish the buffer if we have one... */ + if( NULL != q->curr ) { + saa7146_buffer_finish(dev,q,VIDEOBUF_DONE); + } + saa7146_buffer_next(dev,q,0); + + spin_unlock(&dev->slock); +} + +static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) +{ + struct saa7146_fh *fh = file->private_data; + struct saa7146_dev *dev = fh->dev; + struct saa7146_vv *vv = dev->vv_data; + ssize_t ret = 0; + + DEB_EE("called\n"); + + if ((vv->video_status & STATUS_CAPTURE) != 0) { + /* fixme: should we allow read() captures while streaming capture? */ + if (vv->video_fh == fh) { + DEB_S("already capturing\n"); + return -EBUSY; + } + DEB_S("already capturing in another open\n"); + return -EBUSY; + } + + ret = video_begin(fh); + if( 0 != ret) { + goto out; + } + + ret = videobuf_read_one(&fh->video_q , data, count, ppos, + file->f_flags & O_NONBLOCK); + if (ret != 0) { + video_end(fh, file); + } else { + ret = video_end(fh, file); + } +out: + /* restart overlay if it was active before */ + if (vv->ov_suspend != NULL) { + saa7146_start_preview(vv->ov_suspend); + vv->ov_suspend = NULL; + } + + return ret; +} + +const struct saa7146_use_ops saa7146_video_uops = { + .init = video_init, + .open = video_open, + .release = video_close, + .irq_done = video_irq_done, + .read = video_read, +}; diff --git a/drivers/staging/media/deprecated/saa7146/common/saa7146_vv.h b/drivers/staging/media/deprecated/saa7146/common/saa7146_vv.h new file mode 100644 index 000000000..d7bd916fe --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/common/saa7146_vv.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SAA7146_VV__ +#define __SAA7146_VV__ + +#include +#include +#include +#include +#include "saa7146.h" + +#define MAX_SAA7146_CAPTURE_BUFFERS 32 /* arbitrary */ +#define BUFFER_TIMEOUT (HZ/2) /* 0.5 seconds */ + +#define WRITE_RPS0(x) do { \ + dev->d_rps0.cpu_addr[ count++ ] = cpu_to_le32(x); \ + } while (0); + +#define WRITE_RPS1(x) do { \ + dev->d_rps1.cpu_addr[ count++ ] = cpu_to_le32(x); \ + } while (0); + +struct saa7146_video_dma { + u32 base_odd; + u32 base_even; + u32 prot_addr; + u32 pitch; + u32 base_page; + u32 num_line_byte; +}; + +#define FORMAT_BYTE_SWAP 0x1 +#define FORMAT_IS_PLANAR 0x2 + +struct saa7146_format { + u32 pixelformat; + u32 trans; + u8 depth; + u8 flags; + u8 swap; +}; + +struct saa7146_standard +{ + char *name; + v4l2_std_id id; + + int v_offset; /* number of lines of vertical offset before processing */ + int v_field; /* number of lines in a field for HPS to process */ + + int h_offset; /* horizontal offset of processing window */ + int h_pixels; /* number of horizontal pixels to process */ + + int v_max_out; + int h_max_out; +}; + +/* buffer for one video/vbi frame */ +struct saa7146_buf { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + + /* saa7146 specific */ + struct v4l2_pix_format *fmt; + int (*activate)(struct saa7146_dev *dev, + struct saa7146_buf *buf, + struct saa7146_buf *next); + + /* page tables */ + struct saa7146_pgtable pt[3]; +}; + +struct saa7146_dmaqueue { + struct saa7146_dev *dev; + struct saa7146_buf *curr; + struct list_head queue; + struct timer_list timeout; +}; + +struct saa7146_overlay { + struct saa7146_fh *fh; + struct v4l2_window win; + struct v4l2_clip clips[16]; + int nclips; +}; + +/* per open data */ +struct saa7146_fh { + /* Must be the first field! */ + struct v4l2_fh fh; + struct saa7146_dev *dev; + + /* video capture */ + struct videobuf_queue video_q; + + /* vbi capture */ + struct videobuf_queue vbi_q; + + unsigned int resources; /* resource management for device open */ +}; + +#define STATUS_OVERLAY 0x01 +#define STATUS_CAPTURE 0x02 + +struct saa7146_vv +{ + /* vbi capture */ + struct saa7146_dmaqueue vbi_dmaq; + struct v4l2_vbi_format vbi_fmt; + struct timer_list vbi_read_timeout; + struct file *vbi_read_timeout_file; + /* vbi workaround interrupt queue */ + wait_queue_head_t vbi_wq; + int vbi_fieldcount; + struct saa7146_fh *vbi_streaming; + + int video_status; + struct saa7146_fh *video_fh; + + /* video overlay */ + struct saa7146_overlay ov; + struct v4l2_framebuffer ov_fb; + struct saa7146_format *ov_fmt; + struct saa7146_fh *ov_suspend; + + /* video capture */ + struct saa7146_dmaqueue video_dmaq; + struct v4l2_pix_format video_fmt; + enum v4l2_field last_field; + + /* common: fixme? shouldn't this be in saa7146_fh? + (this leads to a more complicated question: shall the driver + store the different settings (for example S_INPUT) for every open + and restore it appropriately, or should all settings be common for + all opens? currently, we do the latter, like all other + drivers do... */ + struct saa7146_standard *standard; + + int vflip; + int hflip; + int current_hps_source; + int current_hps_sync; + + struct saa7146_dma d_clipping; /* pointer to clipping memory */ + + unsigned int resources; /* resource management for device */ +}; + +/* flags */ +#define SAA7146_USE_PORT_B_FOR_VBI 0x2 /* use input port b for vbi hardware bug workaround */ + +struct saa7146_ext_vv +{ + /* information about the video capabilities of the device */ + int inputs; + int audios; + u32 capabilities; + int flags; + + /* additionally supported transmission standards */ + struct saa7146_standard *stds; + int num_stds; + int (*std_callback)(struct saa7146_dev*, struct saa7146_standard *); + + /* the extension can override this */ + struct v4l2_ioctl_ops vid_ops; + struct v4l2_ioctl_ops vbi_ops; + /* pointer to the saa7146 core ops */ + const struct v4l2_ioctl_ops *core_ops; + + struct v4l2_file_operations vbi_fops; +}; + +struct saa7146_use_ops { + void (*init)(struct saa7146_dev *, struct saa7146_vv *); + int(*open)(struct saa7146_dev *, struct file *); + void (*release)(struct saa7146_dev *, struct file *); + void (*irq_done)(struct saa7146_dev *, unsigned long status); + ssize_t (*read)(struct file *, char __user *, size_t, loff_t *); +}; + +/* from saa7146_fops.c */ +int saa7146_register_device(struct video_device *vid, struct saa7146_dev *dev, char *name, int type); +int saa7146_unregister_device(struct video_device *vid, struct saa7146_dev *dev); +void saa7146_buffer_finish(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, int state); +void saa7146_buffer_next(struct saa7146_dev *dev, struct saa7146_dmaqueue *q,int vbi); +int saa7146_buffer_queue(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, struct saa7146_buf *buf); +void saa7146_buffer_timeout(struct timer_list *t); +void saa7146_dma_free(struct saa7146_dev* dev,struct videobuf_queue *q, + struct saa7146_buf *buf); + +int saa7146_vv_init(struct saa7146_dev* dev, struct saa7146_ext_vv *ext_vv); +int saa7146_vv_release(struct saa7146_dev* dev); + +/* from saa7146_hlp.c */ +int saa7146_enable_overlay(struct saa7146_fh *fh); +void saa7146_disable_overlay(struct saa7146_fh *fh); + +void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next); +void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma) ; +void saa7146_set_hps_source_and_sync(struct saa7146_dev *saa, int source, int sync); +void saa7146_set_gpio(struct saa7146_dev *saa, u8 pin, u8 data); + +/* from saa7146_video.c */ +extern const struct v4l2_ioctl_ops saa7146_video_ioctl_ops; +extern const struct v4l2_ioctl_ops saa7146_vbi_ioctl_ops; +extern const struct saa7146_use_ops saa7146_video_uops; +int saa7146_start_preview(struct saa7146_fh *fh); +int saa7146_stop_preview(struct saa7146_fh *fh); +long saa7146_video_do_ioctl(struct file *file, unsigned int cmd, void *arg); +int saa7146_s_ctrl(struct v4l2_ctrl *ctrl); + +/* from saa7146_vbi.c */ +extern const struct saa7146_use_ops saa7146_vbi_uops; + +/* resource management functions */ +int saa7146_res_get(struct saa7146_fh *fh, unsigned int bit); +void saa7146_res_free(struct saa7146_fh *fh, unsigned int bits); + +#define RESOURCE_DMA1_HPS 0x1 +#define RESOURCE_DMA2_CLP 0x2 +#define RESOURCE_DMA3_BRS 0x4 + +/* saa7146 source inputs */ +#define SAA7146_HPS_SOURCE_PORT_A 0x00 +#define SAA7146_HPS_SOURCE_PORT_B 0x01 +#define SAA7146_HPS_SOURCE_YPB_CPA 0x02 +#define SAA7146_HPS_SOURCE_YPA_CPB 0x03 + +/* sync inputs */ +#define SAA7146_HPS_SYNC_PORT_A 0x00 +#define SAA7146_HPS_SYNC_PORT_B 0x01 + +/* some memory sizes */ +/* max. 16 clipping rectangles */ +#define SAA7146_CLIPPING_MEM (16 * 4 * sizeof(u32)) + +/* some defines for the various clipping-modes */ +#define SAA7146_CLIPPING_RECT 0x4 +#define SAA7146_CLIPPING_RECT_INVERTED 0x5 +#define SAA7146_CLIPPING_MASK 0x6 +#define SAA7146_CLIPPING_MASK_INVERTED 0x7 + +/* output formats: each entry holds four information */ +#define RGB08_COMPOSED 0x0217 /* composed is used in the sense of "not-planar" */ +/* this means: planar?=0, yuv2rgb-conversation-mode=2, dither=yes(=1), format-mode = 7 */ +#define RGB15_COMPOSED 0x0213 +#define RGB16_COMPOSED 0x0210 +#define RGB24_COMPOSED 0x0201 +#define RGB32_COMPOSED 0x0202 + +#define Y8 0x0006 +#define YUV411_COMPOSED 0x0003 +#define YUV422_COMPOSED 0x0000 +/* this means: planar?=1, yuv2rgb-conversion-mode=0, dither=no(=0), format-mode = b */ +#define YUV411_DECOMPOSED 0x100b +#define YUV422_DECOMPOSED 0x1009 +#define YUV420_DECOMPOSED 0x100a + +#define IS_PLANAR(x) (x & 0xf000) + +/* misc defines */ +#define SAA7146_NO_SWAP (0x0) +#define SAA7146_TWO_BYTE_SWAP (0x1) +#define SAA7146_FOUR_BYTE_SWAP (0x2) + +#endif diff --git a/drivers/staging/media/deprecated/saa7146/saa7146/Kconfig b/drivers/staging/media/deprecated/saa7146/saa7146/Kconfig new file mode 100644 index 000000000..228e8d3f8 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/saa7146/Kconfig @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_HEXIUM_GEMINI + tristate "Hexium Gemini frame grabber (DEPRECATED)" + depends on PCI && VIDEO_DEV && I2C + select VIDEO_SAA7146_VV + help + This is a video4linux driver for the Hexium Gemini frame + grabber card by Hexium. Please note that the Gemini Dual + card is *not* fully supported. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + To compile this driver as a module, choose M here: the + module will be called hexium_gemini. + +config VIDEO_HEXIUM_ORION + tristate "Hexium HV-PCI6 and Orion frame grabber (DEPRECATED)" + depends on PCI && VIDEO_DEV && I2C + select VIDEO_SAA7146_VV + help + This is a video4linux driver for the Hexium HV-PCI6 and + Orion frame grabber cards by Hexium. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + To compile this driver as a module, choose M here: the + module will be called hexium_orion. + +config VIDEO_MXB + tristate "Siemens-Nixdorf 'Multimedia eXtension Board' (DEPRECATED)" + depends on PCI && VIDEO_DEV && I2C + select VIDEO_SAA7146_VV + select VIDEO_TUNER + select VIDEO_SAA711X if MEDIA_SUBDRV_AUTOSELECT + select VIDEO_TDA9840 if MEDIA_SUBDRV_AUTOSELECT + select VIDEO_TEA6415C if MEDIA_SUBDRV_AUTOSELECT + select VIDEO_TEA6420 if MEDIA_SUBDRV_AUTOSELECT + help + This is a video4linux driver for the 'Multimedia eXtension Board' + TV card by Siemens-Nixdorf. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + To compile this driver as a module, choose M here: the + module will be called mxb. diff --git a/drivers/staging/media/deprecated/saa7146/saa7146/Makefile b/drivers/staging/media/deprecated/saa7146/saa7146/Makefile new file mode 100644 index 000000000..37c9336f8 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/saa7146/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_VIDEO_MXB) += mxb.o +obj-$(CONFIG_VIDEO_HEXIUM_ORION) += hexium_orion.o +obj-$(CONFIG_VIDEO_HEXIUM_GEMINI) += hexium_gemini.o + +ccflags-y += -I$(srctree)/drivers/media/i2c diff --git a/drivers/staging/media/deprecated/saa7146/saa7146/TODO b/drivers/staging/media/deprecated/saa7146/saa7146/TODO new file mode 100644 index 000000000..c9ae2ec79 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/saa7146/TODO @@ -0,0 +1,7 @@ +The saa7146-based drivers are one of the few drivers still not using +the vb2 framework, so these drivers are now deprecated with the intent of +removing them altogether by the beginning of 2023. + +In order to keep these drivers they have to be converted to vb2. +If someone is interested in doing this work, then contact the +linux-media mailinglist (https://linuxtv.org/lists.php). diff --git a/drivers/staging/media/deprecated/saa7146/saa7146/hexium_gemini.c b/drivers/staging/media/deprecated/saa7146/saa7146/hexium_gemini.c new file mode 100644 index 000000000..124e82bd4 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/saa7146/hexium_gemini.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + hexium_gemini.c - v4l2 driver for Hexium Gemini frame grabber cards + + Visit http://www.mihu.de/linux/saa7146/ and follow the link + to "hexium" for further details about this card. + + Copyright (C) 2003 Michael Hunold + +*/ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#define DEBUG_VARIABLE debug + +#include +#include +#include "../common/saa7146_vv.h" + +static int debug; +module_param(debug, int, 0); +MODULE_PARM_DESC(debug, "debug verbosity"); + +/* global variables */ +static int hexium_num; + +#define HEXIUM_GEMINI 4 +#define HEXIUM_GEMINI_DUAL 5 + +#define HEXIUM_INPUTS 9 +static struct v4l2_input hexium_inputs[HEXIUM_INPUTS] = { + { 0, "CVBS 1", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 1, "CVBS 2", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 2, "CVBS 3", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 3, "CVBS 4", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 4, "CVBS 5", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 5, "CVBS 6", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 6, "Y/C 1", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 7, "Y/C 2", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 8, "Y/C 3", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, +}; + +#define HEXIUM_AUDIOS 0 + +struct hexium_data +{ + s8 adr; + u8 byte; +}; + +#define HEXIUM_GEMINI_V_1_0 1 +#define HEXIUM_GEMINI_DUAL_V_1_0 2 + +struct hexium +{ + int type; + + struct video_device video_dev; + struct i2c_adapter i2c_adapter; + + int cur_input; /* current input */ + v4l2_std_id cur_std; /* current standard */ +}; + +/* Samsung KS0127B decoder default registers */ +static u8 hexium_ks0127b[0x100]={ +/*00*/ 0x00,0x52,0x30,0x40,0x01,0x0C,0x2A,0x10, +/*08*/ 0x00,0x00,0x00,0x60,0x00,0x00,0x0F,0x06, +/*10*/ 0x00,0x00,0xE4,0xC0,0x00,0x00,0x00,0x00, +/*18*/ 0x14,0x9B,0xFE,0xFF,0xFC,0xFF,0x03,0x22, +/*20*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*28*/ 0x00,0x00,0x00,0x00,0x00,0x2C,0x9B,0x00, +/*30*/ 0x00,0x00,0x10,0x80,0x80,0x10,0x80,0x80, +/*38*/ 0x01,0x04,0x00,0x00,0x00,0x29,0xC0,0x00, +/*40*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*48*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*50*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*58*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*60*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*68*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*70*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*78*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*80*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*88*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*90*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*98*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*A0*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*A8*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*B0*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*B8*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*C0*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*C8*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*D0*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*D8*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*E0*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*E8*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*F0*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/*F8*/ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; + +static struct hexium_data hexium_pal[] = { + { 0x01, 0x52 }, { 0x12, 0x64 }, { 0x2D, 0x2C }, { 0x2E, 0x9B }, { -1 , 0xFF } +}; + +static struct hexium_data hexium_ntsc[] = { + { 0x01, 0x53 }, { 0x12, 0x04 }, { 0x2D, 0x23 }, { 0x2E, 0x81 }, { -1 , 0xFF } +}; + +static struct hexium_data hexium_secam[] = { + { 0x01, 0x52 }, { 0x12, 0x64 }, { 0x2D, 0x2C }, { 0x2E, 0x9B }, { -1 , 0xFF } +}; + +static struct hexium_data hexium_input_select[] = { + { 0x02, 0x60 }, + { 0x02, 0x64 }, + { 0x02, 0x61 }, + { 0x02, 0x65 }, + { 0x02, 0x62 }, + { 0x02, 0x66 }, + { 0x02, 0x68 }, + { 0x02, 0x69 }, + { 0x02, 0x6A }, +}; + +/* fixme: h_offset = 0 for Hexium Gemini *Dual*, which + are currently *not* supported*/ +static struct saa7146_standard hexium_standards[] = { + { + .name = "PAL", .id = V4L2_STD_PAL, + .v_offset = 28, .v_field = 288, + .h_offset = 1, .h_pixels = 680, + .v_max_out = 576, .h_max_out = 768, + }, { + .name = "NTSC", .id = V4L2_STD_NTSC, + .v_offset = 28, .v_field = 240, + .h_offset = 1, .h_pixels = 640, + .v_max_out = 480, .h_max_out = 640, + }, { + .name = "SECAM", .id = V4L2_STD_SECAM, + .v_offset = 28, .v_field = 288, + .h_offset = 1, .h_pixels = 720, + .v_max_out = 576, .h_max_out = 768, + } +}; + +/* bring hardware to a sane state. this has to be done, just in case someone + wants to capture from this device before it has been properly initialized. + the capture engine would badly fail, because no valid signal arrives on the + saa7146, thus leading to timeouts and stuff. */ +static int hexium_init_done(struct saa7146_dev *dev) +{ + struct hexium *hexium = (struct hexium *) dev->ext_priv; + union i2c_smbus_data data; + int i = 0; + + DEB_D("hexium_init_done called\n"); + + /* initialize the helper ics to useful values */ + for (i = 0; i < sizeof(hexium_ks0127b); i++) { + data.byte = hexium_ks0127b[i]; + if (0 != i2c_smbus_xfer(&hexium->i2c_adapter, 0x6c, 0, I2C_SMBUS_WRITE, i, I2C_SMBUS_BYTE_DATA, &data)) { + pr_err("hexium_init_done() failed for address 0x%02x\n", + i); + } + } + + return 0; +} + +static int hexium_set_input(struct hexium *hexium, int input) +{ + union i2c_smbus_data data; + + DEB_D("\n"); + + data.byte = hexium_input_select[input].byte; + if (0 != i2c_smbus_xfer(&hexium->i2c_adapter, 0x6c, 0, I2C_SMBUS_WRITE, hexium_input_select[input].adr, I2C_SMBUS_BYTE_DATA, &data)) { + return -1; + } + + return 0; +} + +static int hexium_set_standard(struct hexium *hexium, struct hexium_data *vdec) +{ + union i2c_smbus_data data; + int i = 0; + + DEB_D("\n"); + + while (vdec[i].adr != -1) { + data.byte = vdec[i].byte; + if (0 != i2c_smbus_xfer(&hexium->i2c_adapter, 0x6c, 0, I2C_SMBUS_WRITE, vdec[i].adr, I2C_SMBUS_BYTE_DATA, &data)) { + pr_err("hexium_init_done: hexium_set_standard() failed for address 0x%02x\n", + i); + return -1; + } + i++; + } + return 0; +} + +static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i) +{ + DEB_EE("VIDIOC_ENUMINPUT %d\n", i->index); + + if (i->index >= HEXIUM_INPUTS) + return -EINVAL; + + memcpy(i, &hexium_inputs[i->index], sizeof(struct v4l2_input)); + + DEB_D("v4l2_ioctl: VIDIOC_ENUMINPUT %d\n", i->index); + return 0; +} + +static int vidioc_g_input(struct file *file, void *fh, unsigned int *input) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct hexium *hexium = (struct hexium *) dev->ext_priv; + + *input = hexium->cur_input; + + DEB_D("VIDIOC_G_INPUT: %d\n", *input); + return 0; +} + +static int vidioc_s_input(struct file *file, void *fh, unsigned int input) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct hexium *hexium = (struct hexium *) dev->ext_priv; + + DEB_EE("VIDIOC_S_INPUT %d\n", input); + + if (input >= HEXIUM_INPUTS) + return -EINVAL; + + hexium->cur_input = input; + hexium_set_input(hexium, input); + return 0; +} + +static struct saa7146_ext_vv vv_data; + +/* this function only gets called when the probing was successful */ +static int hexium_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info) +{ + struct hexium *hexium; + int ret; + + DEB_EE("\n"); + + hexium = kzalloc(sizeof(*hexium), GFP_KERNEL); + if (!hexium) + return -ENOMEM; + + dev->ext_priv = hexium; + + /* enable i2c-port pins */ + saa7146_write(dev, MC1, (MASK_08 | MASK_24 | MASK_10 | MASK_26)); + + strscpy(hexium->i2c_adapter.name, "hexium gemini", + sizeof(hexium->i2c_adapter.name)); + saa7146_i2c_adapter_prepare(dev, &hexium->i2c_adapter, SAA7146_I2C_BUS_BIT_RATE_480); + if (i2c_add_adapter(&hexium->i2c_adapter) < 0) { + DEB_S("cannot register i2c-device. skipping.\n"); + kfree(hexium); + return -EFAULT; + } + + /* set HWControl GPIO number 2 */ + saa7146_setgpio(dev, 2, SAA7146_GPIO_OUTHI); + + saa7146_write(dev, DD1_INIT, 0x07000700); + saa7146_write(dev, DD1_STREAM_B, 0x00000000); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + + /* the rest */ + hexium->cur_input = 0; + hexium_init_done(dev); + + hexium_set_standard(hexium, hexium_pal); + hexium->cur_std = V4L2_STD_PAL; + + hexium_set_input(hexium, 0); + hexium->cur_input = 0; + + ret = saa7146_vv_init(dev, &vv_data); + if (ret) { + i2c_del_adapter(&hexium->i2c_adapter); + kfree(hexium); + return ret; + } + + vv_data.vid_ops.vidioc_enum_input = vidioc_enum_input; + vv_data.vid_ops.vidioc_g_input = vidioc_g_input; + vv_data.vid_ops.vidioc_s_input = vidioc_s_input; + ret = saa7146_register_device(&hexium->video_dev, dev, "hexium gemini", VFL_TYPE_VIDEO); + if (ret < 0) { + pr_err("cannot register capture v4l2 device. skipping.\n"); + saa7146_vv_release(dev); + i2c_del_adapter(&hexium->i2c_adapter); + kfree(hexium); + return ret; + } + + pr_info("found 'hexium gemini' frame grabber-%d\n", hexium_num); + hexium_num++; + + return 0; +} + +static int hexium_detach(struct saa7146_dev *dev) +{ + struct hexium *hexium = (struct hexium *) dev->ext_priv; + + DEB_EE("dev:%p\n", dev); + + saa7146_unregister_device(&hexium->video_dev, dev); + saa7146_vv_release(dev); + + hexium_num--; + + i2c_del_adapter(&hexium->i2c_adapter); + kfree(hexium); + return 0; +} + +static int std_callback(struct saa7146_dev *dev, struct saa7146_standard *std) +{ + struct hexium *hexium = (struct hexium *) dev->ext_priv; + + if (V4L2_STD_PAL == std->id) { + hexium_set_standard(hexium, hexium_pal); + hexium->cur_std = V4L2_STD_PAL; + return 0; + } else if (V4L2_STD_NTSC == std->id) { + hexium_set_standard(hexium, hexium_ntsc); + hexium->cur_std = V4L2_STD_NTSC; + return 0; + } else if (V4L2_STD_SECAM == std->id) { + hexium_set_standard(hexium, hexium_secam); + hexium->cur_std = V4L2_STD_SECAM; + return 0; + } + + return -1; +} + +static struct saa7146_extension hexium_extension; + +static struct saa7146_pci_extension_data hexium_gemini_4bnc = { + .ext_priv = "Hexium Gemini (4 BNC)", + .ext = &hexium_extension, +}; + +static struct saa7146_pci_extension_data hexium_gemini_dual_4bnc = { + .ext_priv = "Hexium Gemini Dual (4 BNC)", + .ext = &hexium_extension, +}; + +static const struct pci_device_id pci_tbl[] = { + { + .vendor = PCI_VENDOR_ID_PHILIPS, + .device = PCI_DEVICE_ID_PHILIPS_SAA7146, + .subvendor = 0x17c8, + .subdevice = 0x2401, + .driver_data = (unsigned long) &hexium_gemini_4bnc, + }, + { + .vendor = PCI_VENDOR_ID_PHILIPS, + .device = PCI_DEVICE_ID_PHILIPS_SAA7146, + .subvendor = 0x17c8, + .subdevice = 0x2402, + .driver_data = (unsigned long) &hexium_gemini_dual_4bnc, + }, + { + .vendor = 0, + } +}; + +MODULE_DEVICE_TABLE(pci, pci_tbl); + +static struct saa7146_ext_vv vv_data = { + .inputs = HEXIUM_INPUTS, + .capabilities = 0, + .stds = &hexium_standards[0], + .num_stds = ARRAY_SIZE(hexium_standards), + .std_callback = &std_callback, +}; + +static struct saa7146_extension hexium_extension = { + .name = "hexium gemini", + .flags = SAA7146_USE_I2C_IRQ, + + .pci_tbl = &pci_tbl[0], + .module = THIS_MODULE, + + .attach = hexium_attach, + .detach = hexium_detach, + + .irq_mask = 0, + .irq_func = NULL, +}; + +static int __init hexium_init_module(void) +{ + if (0 != saa7146_register_extension(&hexium_extension)) { + DEB_S("failed to register extension\n"); + return -ENODEV; + } + + return 0; +} + +static void __exit hexium_cleanup_module(void) +{ + saa7146_unregister_extension(&hexium_extension); +} + +module_init(hexium_init_module); +module_exit(hexium_cleanup_module); + +MODULE_DESCRIPTION("video4linux-2 driver for Hexium Gemini frame grabber cards"); +MODULE_AUTHOR("Michael Hunold "); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/deprecated/saa7146/saa7146/hexium_orion.c b/drivers/staging/media/deprecated/saa7146/saa7146/hexium_orion.c new file mode 100644 index 000000000..ebd63998a --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/saa7146/hexium_orion.c @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + hexium_orion.c - v4l2 driver for the Hexium Orion frame grabber cards + + Visit http://www.mihu.de/linux/saa7146/ and follow the link + to "hexium" for further details about this card. + + Copyright (C) 2003 Michael Hunold + +*/ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#define DEBUG_VARIABLE debug + +#include +#include +#include "../common/saa7146_vv.h" + +static int debug; +module_param(debug, int, 0); +MODULE_PARM_DESC(debug, "debug verbosity"); + +/* global variables */ +static int hexium_num; + +#define HEXIUM_HV_PCI6_ORION 1 +#define HEXIUM_ORION_1SVHS_3BNC 2 +#define HEXIUM_ORION_4BNC 3 + +#define HEXIUM_INPUTS 9 +static struct v4l2_input hexium_inputs[HEXIUM_INPUTS] = { + { 0, "CVBS 1", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 1, "CVBS 2", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 2, "CVBS 3", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 3, "CVBS 4", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 4, "CVBS 5", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 5, "CVBS 6", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 6, "Y/C 1", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 7, "Y/C 2", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { 8, "Y/C 3", V4L2_INPUT_TYPE_CAMERA, 0, 0, V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, +}; + +#define HEXIUM_AUDIOS 0 + +struct hexium_data +{ + s8 adr; + u8 byte; +}; + +struct hexium +{ + int type; + struct video_device video_dev; + struct i2c_adapter i2c_adapter; + + int cur_input; /* current input */ +}; + +/* Philips SAA7110 decoder default registers */ +static u8 hexium_saa7110[53]={ +/*00*/ 0x4C,0x3C,0x0D,0xEF,0xBD,0xF0,0x00,0x00, +/*08*/ 0xF8,0xF8,0x60,0x60,0x40,0x86,0x18,0x90, +/*10*/ 0x00,0x2C,0x40,0x46,0x42,0x1A,0xFF,0xDA, +/*18*/ 0xF0,0x8B,0x00,0x00,0x00,0x00,0x00,0x00, +/*20*/ 0xD9,0x17,0x40,0x41,0x80,0x41,0x80,0x4F, +/*28*/ 0xFE,0x01,0x0F,0x0F,0x03,0x01,0x81,0x03, +/*30*/ 0x44,0x75,0x01,0x8C,0x03 +}; + +static struct { + struct hexium_data data[8]; +} hexium_input_select[] = { +{ + { /* cvbs 1 */ + { 0x06, 0x00 }, + { 0x20, 0xD9 }, + { 0x21, 0x17 }, // 0x16, + { 0x22, 0x40 }, + { 0x2C, 0x03 }, + { 0x30, 0x44 }, + { 0x31, 0x75 }, // ?? + { 0x21, 0x16 }, // 0x03, + } +}, { + { /* cvbs 2 */ + { 0x06, 0x00 }, + { 0x20, 0x78 }, + { 0x21, 0x07 }, // 0x03, + { 0x22, 0xD2 }, + { 0x2C, 0x83 }, + { 0x30, 0x60 }, + { 0x31, 0xB5 }, // ? + { 0x21, 0x03 }, + } +}, { + { /* cvbs 3 */ + { 0x06, 0x00 }, + { 0x20, 0xBA }, + { 0x21, 0x07 }, // 0x05, + { 0x22, 0x91 }, + { 0x2C, 0x03 }, + { 0x30, 0x60 }, + { 0x31, 0xB5 }, // ?? + { 0x21, 0x05 }, // 0x03, + } +}, { + { /* cvbs 4 */ + { 0x06, 0x00 }, + { 0x20, 0xD8 }, + { 0x21, 0x17 }, // 0x16, + { 0x22, 0x40 }, + { 0x2C, 0x03 }, + { 0x30, 0x44 }, + { 0x31, 0x75 }, // ?? + { 0x21, 0x16 }, // 0x03, + } +}, { + { /* cvbs 5 */ + { 0x06, 0x00 }, + { 0x20, 0xB8 }, + { 0x21, 0x07 }, // 0x05, + { 0x22, 0x91 }, + { 0x2C, 0x03 }, + { 0x30, 0x60 }, + { 0x31, 0xB5 }, // ?? + { 0x21, 0x05 }, // 0x03, + } +}, { + { /* cvbs 6 */ + { 0x06, 0x00 }, + { 0x20, 0x7C }, + { 0x21, 0x07 }, // 0x03 + { 0x22, 0xD2 }, + { 0x2C, 0x83 }, + { 0x30, 0x60 }, + { 0x31, 0xB5 }, // ?? + { 0x21, 0x03 }, + } +}, { + { /* y/c 1 */ + { 0x06, 0x80 }, + { 0x20, 0x59 }, + { 0x21, 0x17 }, + { 0x22, 0x42 }, + { 0x2C, 0xA3 }, + { 0x30, 0x44 }, + { 0x31, 0x75 }, + { 0x21, 0x12 }, + } +}, { + { /* y/c 2 */ + { 0x06, 0x80 }, + { 0x20, 0x9A }, + { 0x21, 0x17 }, + { 0x22, 0xB1 }, + { 0x2C, 0x13 }, + { 0x30, 0x60 }, + { 0x31, 0xB5 }, + { 0x21, 0x14 }, + } +}, { + { /* y/c 3 */ + { 0x06, 0x80 }, + { 0x20, 0x3C }, + { 0x21, 0x27 }, + { 0x22, 0xC1 }, + { 0x2C, 0x23 }, + { 0x30, 0x44 }, + { 0x31, 0x75 }, + { 0x21, 0x21 }, + } +} +}; + +static struct saa7146_standard hexium_standards[] = { + { + .name = "PAL", .id = V4L2_STD_PAL, + .v_offset = 16, .v_field = 288, + .h_offset = 1, .h_pixels = 680, + .v_max_out = 576, .h_max_out = 768, + }, { + .name = "NTSC", .id = V4L2_STD_NTSC, + .v_offset = 16, .v_field = 240, + .h_offset = 1, .h_pixels = 640, + .v_max_out = 480, .h_max_out = 640, + }, { + .name = "SECAM", .id = V4L2_STD_SECAM, + .v_offset = 16, .v_field = 288, + .h_offset = 1, .h_pixels = 720, + .v_max_out = 576, .h_max_out = 768, + } +}; + +/* this is only called for old HV-PCI6/Orion cards + without eeprom */ +static int hexium_probe(struct saa7146_dev *dev) +{ + struct hexium *hexium = NULL; + union i2c_smbus_data data; + int err = 0; + + DEB_EE("\n"); + + /* there are no hexium orion cards with revision 0 saa7146s */ + if (0 == dev->revision) { + return -EFAULT; + } + + hexium = kzalloc(sizeof(*hexium), GFP_KERNEL); + if (!hexium) + return -ENOMEM; + + /* enable i2c-port pins */ + saa7146_write(dev, MC1, (MASK_08 | MASK_24 | MASK_10 | MASK_26)); + + saa7146_write(dev, DD1_INIT, 0x01000100); + saa7146_write(dev, DD1_STREAM_B, 0x00000000); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + + strscpy(hexium->i2c_adapter.name, "hexium orion", + sizeof(hexium->i2c_adapter.name)); + saa7146_i2c_adapter_prepare(dev, &hexium->i2c_adapter, SAA7146_I2C_BUS_BIT_RATE_480); + if (i2c_add_adapter(&hexium->i2c_adapter) < 0) { + DEB_S("cannot register i2c-device. skipping.\n"); + kfree(hexium); + return -EFAULT; + } + + /* set SAA7110 control GPIO 0 */ + saa7146_setgpio(dev, 0, SAA7146_GPIO_OUTHI); + /* set HWControl GPIO number 2 */ + saa7146_setgpio(dev, 2, SAA7146_GPIO_OUTHI); + + mdelay(10); + + /* detect newer Hexium Orion cards by subsystem ids */ + if (0x17c8 == dev->pci->subsystem_vendor && 0x0101 == dev->pci->subsystem_device) { + pr_info("device is a Hexium Orion w/ 1 SVHS + 3 BNC inputs\n"); + /* we store the pointer in our private data field */ + dev->ext_priv = hexium; + hexium->type = HEXIUM_ORION_1SVHS_3BNC; + return 0; + } + + if (0x17c8 == dev->pci->subsystem_vendor && 0x2101 == dev->pci->subsystem_device) { + pr_info("device is a Hexium Orion w/ 4 BNC inputs\n"); + /* we store the pointer in our private data field */ + dev->ext_priv = hexium; + hexium->type = HEXIUM_ORION_4BNC; + return 0; + } + + /* check if this is an old hexium Orion card by looking at + a saa7110 at address 0x4e */ + err = i2c_smbus_xfer(&hexium->i2c_adapter, 0x4e, 0, I2C_SMBUS_READ, + 0x00, I2C_SMBUS_BYTE_DATA, &data); + if (err == 0) { + pr_info("device is a Hexium HV-PCI6/Orion (old)\n"); + /* we store the pointer in our private data field */ + dev->ext_priv = hexium; + hexium->type = HEXIUM_HV_PCI6_ORION; + return 0; + } + + i2c_del_adapter(&hexium->i2c_adapter); + kfree(hexium); + return -EFAULT; +} + +/* bring hardware to a sane state. this has to be done, just in case someone + wants to capture from this device before it has been properly initialized. + the capture engine would badly fail, because no valid signal arrives on the + saa7146, thus leading to timeouts and stuff. */ +static int hexium_init_done(struct saa7146_dev *dev) +{ + struct hexium *hexium = (struct hexium *) dev->ext_priv; + union i2c_smbus_data data; + int i = 0; + + DEB_D("hexium_init_done called\n"); + + /* initialize the helper ics to useful values */ + for (i = 0; i < sizeof(hexium_saa7110); i++) { + data.byte = hexium_saa7110[i]; + if (0 != i2c_smbus_xfer(&hexium->i2c_adapter, 0x4e, 0, I2C_SMBUS_WRITE, i, I2C_SMBUS_BYTE_DATA, &data)) { + pr_err("failed for address 0x%02x\n", i); + } + } + + return 0; +} + +static int hexium_set_input(struct hexium *hexium, int input) +{ + union i2c_smbus_data data; + int i = 0; + + DEB_D("\n"); + + for (i = 0; i < 8; i++) { + int adr = hexium_input_select[input].data[i].adr; + data.byte = hexium_input_select[input].data[i].byte; + if (0 != i2c_smbus_xfer(&hexium->i2c_adapter, 0x4e, 0, I2C_SMBUS_WRITE, adr, I2C_SMBUS_BYTE_DATA, &data)) { + return -1; + } + pr_debug("%d: 0x%02x => 0x%02x\n", input, adr, data.byte); + } + + return 0; +} + +static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i) +{ + DEB_EE("VIDIOC_ENUMINPUT %d\n", i->index); + + if (i->index >= HEXIUM_INPUTS) + return -EINVAL; + + memcpy(i, &hexium_inputs[i->index], sizeof(struct v4l2_input)); + + DEB_D("v4l2_ioctl: VIDIOC_ENUMINPUT %d\n", i->index); + return 0; +} + +static int vidioc_g_input(struct file *file, void *fh, unsigned int *input) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct hexium *hexium = (struct hexium *) dev->ext_priv; + + *input = hexium->cur_input; + + DEB_D("VIDIOC_G_INPUT: %d\n", *input); + return 0; +} + +static int vidioc_s_input(struct file *file, void *fh, unsigned int input) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct hexium *hexium = (struct hexium *) dev->ext_priv; + + if (input >= HEXIUM_INPUTS) + return -EINVAL; + + hexium->cur_input = input; + hexium_set_input(hexium, input); + + return 0; +} + +static struct saa7146_ext_vv vv_data; + +/* this function only gets called when the probing was successful */ +static int hexium_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info) +{ + struct hexium *hexium = (struct hexium *) dev->ext_priv; + int ret; + + DEB_EE("\n"); + + ret = saa7146_vv_init(dev, &vv_data); + if (ret) { + pr_err("Error in saa7146_vv_init()\n"); + return ret; + } + + vv_data.vid_ops.vidioc_enum_input = vidioc_enum_input; + vv_data.vid_ops.vidioc_g_input = vidioc_g_input; + vv_data.vid_ops.vidioc_s_input = vidioc_s_input; + if (0 != saa7146_register_device(&hexium->video_dev, dev, "hexium orion", VFL_TYPE_VIDEO)) { + pr_err("cannot register capture v4l2 device. skipping.\n"); + return -1; + } + + pr_err("found 'hexium orion' frame grabber-%d\n", hexium_num); + hexium_num++; + + /* the rest */ + hexium->cur_input = 0; + hexium_init_done(dev); + + return 0; +} + +static int hexium_detach(struct saa7146_dev *dev) +{ + struct hexium *hexium = (struct hexium *) dev->ext_priv; + + DEB_EE("dev:%p\n", dev); + + saa7146_unregister_device(&hexium->video_dev, dev); + saa7146_vv_release(dev); + + hexium_num--; + + i2c_del_adapter(&hexium->i2c_adapter); + kfree(hexium); + return 0; +} + +static int std_callback(struct saa7146_dev *dev, struct saa7146_standard *std) +{ + return 0; +} + +static struct saa7146_extension extension; + +static struct saa7146_pci_extension_data hexium_hv_pci6 = { + .ext_priv = "Hexium HV-PCI6 / Orion", + .ext = &extension, +}; + +static struct saa7146_pci_extension_data hexium_orion_1svhs_3bnc = { + .ext_priv = "Hexium HV-PCI6 / Orion (1 SVHS/3 BNC)", + .ext = &extension, +}; + +static struct saa7146_pci_extension_data hexium_orion_4bnc = { + .ext_priv = "Hexium HV-PCI6 / Orion (4 BNC)", + .ext = &extension, +}; + +static const struct pci_device_id pci_tbl[] = { + { + .vendor = PCI_VENDOR_ID_PHILIPS, + .device = PCI_DEVICE_ID_PHILIPS_SAA7146, + .subvendor = 0x0000, + .subdevice = 0x0000, + .driver_data = (unsigned long) &hexium_hv_pci6, + }, + { + .vendor = PCI_VENDOR_ID_PHILIPS, + .device = PCI_DEVICE_ID_PHILIPS_SAA7146, + .subvendor = 0x17c8, + .subdevice = 0x0101, + .driver_data = (unsigned long) &hexium_orion_1svhs_3bnc, + }, + { + .vendor = PCI_VENDOR_ID_PHILIPS, + .device = PCI_DEVICE_ID_PHILIPS_SAA7146, + .subvendor = 0x17c8, + .subdevice = 0x2101, + .driver_data = (unsigned long) &hexium_orion_4bnc, + }, + { + .vendor = 0, + } +}; + +MODULE_DEVICE_TABLE(pci, pci_tbl); + +static struct saa7146_ext_vv vv_data = { + .inputs = HEXIUM_INPUTS, + .capabilities = 0, + .stds = &hexium_standards[0], + .num_stds = ARRAY_SIZE(hexium_standards), + .std_callback = &std_callback, +}; + +static struct saa7146_extension extension = { + .name = "hexium HV-PCI6 Orion", + .flags = 0, // SAA7146_USE_I2C_IRQ, + + .pci_tbl = &pci_tbl[0], + .module = THIS_MODULE, + + .probe = hexium_probe, + .attach = hexium_attach, + .detach = hexium_detach, + + .irq_mask = 0, + .irq_func = NULL, +}; + +static int __init hexium_init_module(void) +{ + if (0 != saa7146_register_extension(&extension)) { + DEB_S("failed to register extension\n"); + return -ENODEV; + } + + return 0; +} + +static void __exit hexium_cleanup_module(void) +{ + saa7146_unregister_extension(&extension); +} + +module_init(hexium_init_module); +module_exit(hexium_cleanup_module); + +MODULE_DESCRIPTION("video4linux-2 driver for Hexium Orion frame grabber cards"); +MODULE_AUTHOR("Michael Hunold "); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/deprecated/saa7146/saa7146/mxb.c b/drivers/staging/media/deprecated/saa7146/saa7146/mxb.c new file mode 100644 index 000000000..3e568f952 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/saa7146/mxb.c @@ -0,0 +1,873 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + mxb - v4l2 driver for the Multimedia eXtension Board + + Copyright (C) 1998-2006 Michael Hunold + + Visit http://www.themm.net/~mihu/linux/saa7146/mxb.html + for further details about this card. + +*/ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#define DEBUG_VARIABLE debug + +#include +#include +#include +#include +#include + +#include "../common/saa7146_vv.h" +#include "tea6415c.h" +#include "tea6420.h" + +#define MXB_AUDIOS 6 + +#define I2C_SAA7111A 0x24 +#define I2C_TDA9840 0x42 +#define I2C_TEA6415C 0x43 +#define I2C_TEA6420_1 0x4c +#define I2C_TEA6420_2 0x4d +#define I2C_TUNER 0x60 + +#define MXB_BOARD_CAN_DO_VBI(dev) (dev->revision != 0) + +/* global variable */ +static int mxb_num; + +/* initial frequence the tuner will be tuned to. + in verden (lower saxony, germany) 4148 is a + channel called "phoenix" */ +static int freq = 4148; +module_param(freq, int, 0644); +MODULE_PARM_DESC(freq, "initial frequency the tuner will be tuned to while setup"); + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off device debugging (default:off)."); + +#define MXB_INPUTS 4 +enum { TUNER, AUX1, AUX3, AUX3_YC }; + +static struct v4l2_input mxb_inputs[MXB_INPUTS] = { + { TUNER, "Tuner", V4L2_INPUT_TYPE_TUNER, 0x3f, 0, + V4L2_STD_PAL_BG | V4L2_STD_PAL_I, 0, V4L2_IN_CAP_STD }, + { AUX1, "AUX1", V4L2_INPUT_TYPE_CAMERA, 0x3f, 0, + V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { AUX3, "AUX3 Composite", V4L2_INPUT_TYPE_CAMERA, 0x3f, 0, + V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, + { AUX3_YC, "AUX3 S-Video", V4L2_INPUT_TYPE_CAMERA, 0x3f, 0, + V4L2_STD_ALL, 0, V4L2_IN_CAP_STD }, +}; + +/* this array holds the information, which port of the saa7146 each + input actually uses. the mxb uses port 0 for every input */ +static struct { + int hps_source; + int hps_sync; +} input_port_selection[MXB_INPUTS] = { + { SAA7146_HPS_SOURCE_PORT_A, SAA7146_HPS_SYNC_PORT_A }, + { SAA7146_HPS_SOURCE_PORT_A, SAA7146_HPS_SYNC_PORT_A }, + { SAA7146_HPS_SOURCE_PORT_A, SAA7146_HPS_SYNC_PORT_A }, + { SAA7146_HPS_SOURCE_PORT_A, SAA7146_HPS_SYNC_PORT_A }, +}; + +/* this array holds the information of the audio source (mxb_audios), + which has to be switched corresponding to the video source (mxb_channels) */ +static int video_audio_connect[MXB_INPUTS] = + { 0, 1, 3, 3 }; + +struct mxb_routing { + u32 input; + u32 output; +}; + +/* these are the available audio sources, which can switched + to the line- and cd-output individually */ +static struct v4l2_audio mxb_audios[MXB_AUDIOS] = { + { + .index = 0, + .name = "Tuner", + .capability = V4L2_AUDCAP_STEREO, + } , { + .index = 1, + .name = "AUX1", + .capability = V4L2_AUDCAP_STEREO, + } , { + .index = 2, + .name = "AUX2", + .capability = V4L2_AUDCAP_STEREO, + } , { + .index = 3, + .name = "AUX3", + .capability = V4L2_AUDCAP_STEREO, + } , { + .index = 4, + .name = "Radio (X9)", + .capability = V4L2_AUDCAP_STEREO, + } , { + .index = 5, + .name = "CD-ROM (X10)", + .capability = V4L2_AUDCAP_STEREO, + } +}; + +/* These are the necessary input-output-pins for bringing one audio source + (see above) to the CD-output. Note that gain is set to 0 in this table. */ +static struct mxb_routing TEA6420_cd[MXB_AUDIOS + 1][2] = { + { { 1, 1 }, { 1, 1 } }, /* Tuner */ + { { 5, 1 }, { 6, 1 } }, /* AUX 1 */ + { { 4, 1 }, { 6, 1 } }, /* AUX 2 */ + { { 3, 1 }, { 6, 1 } }, /* AUX 3 */ + { { 1, 1 }, { 3, 1 } }, /* Radio */ + { { 1, 1 }, { 2, 1 } }, /* CD-Rom */ + { { 6, 1 }, { 6, 1 } } /* Mute */ +}; + +/* These are the necessary input-output-pins for bringing one audio source + (see above) to the line-output. Note that gain is set to 0 in this table. */ +static struct mxb_routing TEA6420_line[MXB_AUDIOS + 1][2] = { + { { 2, 3 }, { 1, 2 } }, + { { 5, 3 }, { 6, 2 } }, + { { 4, 3 }, { 6, 2 } }, + { { 3, 3 }, { 6, 2 } }, + { { 2, 3 }, { 3, 2 } }, + { { 2, 3 }, { 2, 2 } }, + { { 6, 3 }, { 6, 2 } } /* Mute */ +}; + +struct mxb +{ + struct video_device video_dev; + struct video_device vbi_dev; + + struct i2c_adapter i2c_adapter; + + struct v4l2_subdev *saa7111a; + struct v4l2_subdev *tda9840; + struct v4l2_subdev *tea6415c; + struct v4l2_subdev *tuner; + struct v4l2_subdev *tea6420_1; + struct v4l2_subdev *tea6420_2; + + int cur_mode; /* current audio mode (mono, stereo, ...) */ + int cur_input; /* current input */ + int cur_audinput; /* current audio input */ + int cur_mute; /* current mute status */ + struct v4l2_frequency cur_freq; /* current frequency the tuner is tuned to */ +}; + +#define saa7111a_call(mxb, o, f, args...) \ + v4l2_subdev_call(mxb->saa7111a, o, f, ##args) +#define tda9840_call(mxb, o, f, args...) \ + v4l2_subdev_call(mxb->tda9840, o, f, ##args) +#define tea6415c_call(mxb, o, f, args...) \ + v4l2_subdev_call(mxb->tea6415c, o, f, ##args) +#define tuner_call(mxb, o, f, args...) \ + v4l2_subdev_call(mxb->tuner, o, f, ##args) +#define call_all(dev, o, f, args...) \ + v4l2_device_call_until_err(&dev->v4l2_dev, 0, o, f, ##args) + +static void mxb_update_audmode(struct mxb *mxb) +{ + struct v4l2_tuner t = { + .audmode = mxb->cur_mode, + }; + + tda9840_call(mxb, tuner, s_tuner, &t); +} + +static inline void tea6420_route(struct mxb *mxb, int idx) +{ + v4l2_subdev_call(mxb->tea6420_1, audio, s_routing, + TEA6420_cd[idx][0].input, TEA6420_cd[idx][0].output, 0); + v4l2_subdev_call(mxb->tea6420_2, audio, s_routing, + TEA6420_cd[idx][1].input, TEA6420_cd[idx][1].output, 0); + v4l2_subdev_call(mxb->tea6420_1, audio, s_routing, + TEA6420_line[idx][0].input, TEA6420_line[idx][0].output, 0); + v4l2_subdev_call(mxb->tea6420_2, audio, s_routing, + TEA6420_line[idx][1].input, TEA6420_line[idx][1].output, 0); +} + +static struct saa7146_extension extension; + +static int mxb_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct saa7146_dev *dev = container_of(ctrl->handler, + struct saa7146_dev, ctrl_handler); + struct mxb *mxb = dev->ext_priv; + + switch (ctrl->id) { + case V4L2_CID_AUDIO_MUTE: + mxb->cur_mute = ctrl->val; + /* switch the audio-source */ + tea6420_route(mxb, ctrl->val ? 6 : + video_audio_connect[mxb->cur_input]); + break; + default: + return -EINVAL; + } + return 0; +} + +static const struct v4l2_ctrl_ops mxb_ctrl_ops = { + .s_ctrl = mxb_s_ctrl, +}; + +static int mxb_probe(struct saa7146_dev *dev) +{ + struct v4l2_ctrl_handler *hdl = &dev->ctrl_handler; + struct mxb *mxb = NULL; + + v4l2_ctrl_new_std(hdl, &mxb_ctrl_ops, + V4L2_CID_AUDIO_MUTE, 0, 1, 1, 1); + if (hdl->error) + return hdl->error; + mxb = kzalloc(sizeof(struct mxb), GFP_KERNEL); + if (mxb == NULL) { + DEB_D("not enough kernel memory\n"); + return -ENOMEM; + } + + + snprintf(mxb->i2c_adapter.name, sizeof(mxb->i2c_adapter.name), "mxb%d", mxb_num); + + saa7146_i2c_adapter_prepare(dev, &mxb->i2c_adapter, SAA7146_I2C_BUS_BIT_RATE_480); + if (i2c_add_adapter(&mxb->i2c_adapter) < 0) { + DEB_S("cannot register i2c-device. skipping.\n"); + kfree(mxb); + return -EFAULT; + } + + mxb->saa7111a = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, + "saa7111", I2C_SAA7111A, NULL); + mxb->tea6420_1 = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, + "tea6420", I2C_TEA6420_1, NULL); + mxb->tea6420_2 = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, + "tea6420", I2C_TEA6420_2, NULL); + mxb->tea6415c = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, + "tea6415c", I2C_TEA6415C, NULL); + mxb->tda9840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, + "tda9840", I2C_TDA9840, NULL); + mxb->tuner = v4l2_i2c_new_subdev(&dev->v4l2_dev, &mxb->i2c_adapter, + "tuner", I2C_TUNER, NULL); + + /* check if all devices are present */ + if (!mxb->tea6420_1 || !mxb->tea6420_2 || !mxb->tea6415c || + !mxb->tda9840 || !mxb->saa7111a || !mxb->tuner) { + pr_err("did not find all i2c devices. aborting\n"); + i2c_del_adapter(&mxb->i2c_adapter); + kfree(mxb); + return -ENODEV; + } + + /* all devices are present, probe was successful */ + + /* we store the pointer in our private data field */ + dev->ext_priv = mxb; + + v4l2_ctrl_handler_setup(hdl); + + return 0; +} + +/* some init data for the saa7740, the so-called 'sound arena module'. + there are no specs available, so we simply use some init values */ +static struct { + int length; + char data[9]; +} mxb_saa7740_init[] = { + { 3, { 0x80, 0x00, 0x00 } },{ 3, { 0x80, 0x89, 0x00 } }, + { 3, { 0x80, 0xb0, 0x0a } },{ 3, { 0x00, 0x00, 0x00 } }, + { 3, { 0x49, 0x00, 0x00 } },{ 3, { 0x4a, 0x00, 0x00 } }, + { 3, { 0x4b, 0x00, 0x00 } },{ 3, { 0x4c, 0x00, 0x00 } }, + { 3, { 0x4d, 0x00, 0x00 } },{ 3, { 0x4e, 0x00, 0x00 } }, + { 3, { 0x4f, 0x00, 0x00 } },{ 3, { 0x50, 0x00, 0x00 } }, + { 3, { 0x51, 0x00, 0x00 } },{ 3, { 0x52, 0x00, 0x00 } }, + { 3, { 0x53, 0x00, 0x00 } },{ 3, { 0x54, 0x00, 0x00 } }, + { 3, { 0x55, 0x00, 0x00 } },{ 3, { 0x56, 0x00, 0x00 } }, + { 3, { 0x57, 0x00, 0x00 } },{ 3, { 0x58, 0x00, 0x00 } }, + { 3, { 0x59, 0x00, 0x00 } },{ 3, { 0x5a, 0x00, 0x00 } }, + { 3, { 0x5b, 0x00, 0x00 } },{ 3, { 0x5c, 0x00, 0x00 } }, + { 3, { 0x5d, 0x00, 0x00 } },{ 3, { 0x5e, 0x00, 0x00 } }, + { 3, { 0x5f, 0x00, 0x00 } },{ 3, { 0x60, 0x00, 0x00 } }, + { 3, { 0x61, 0x00, 0x00 } },{ 3, { 0x62, 0x00, 0x00 } }, + { 3, { 0x63, 0x00, 0x00 } },{ 3, { 0x64, 0x00, 0x00 } }, + { 3, { 0x65, 0x00, 0x00 } },{ 3, { 0x66, 0x00, 0x00 } }, + { 3, { 0x67, 0x00, 0x00 } },{ 3, { 0x68, 0x00, 0x00 } }, + { 3, { 0x69, 0x00, 0x00 } },{ 3, { 0x6a, 0x00, 0x00 } }, + { 3, { 0x6b, 0x00, 0x00 } },{ 3, { 0x6c, 0x00, 0x00 } }, + { 3, { 0x6d, 0x00, 0x00 } },{ 3, { 0x6e, 0x00, 0x00 } }, + { 3, { 0x6f, 0x00, 0x00 } },{ 3, { 0x70, 0x00, 0x00 } }, + { 3, { 0x71, 0x00, 0x00 } },{ 3, { 0x72, 0x00, 0x00 } }, + { 3, { 0x73, 0x00, 0x00 } },{ 3, { 0x74, 0x00, 0x00 } }, + { 3, { 0x75, 0x00, 0x00 } },{ 3, { 0x76, 0x00, 0x00 } }, + { 3, { 0x77, 0x00, 0x00 } },{ 3, { 0x41, 0x00, 0x42 } }, + { 3, { 0x42, 0x10, 0x42 } },{ 3, { 0x43, 0x20, 0x42 } }, + { 3, { 0x44, 0x30, 0x42 } },{ 3, { 0x45, 0x00, 0x01 } }, + { 3, { 0x46, 0x00, 0x01 } },{ 3, { 0x47, 0x00, 0x01 } }, + { 3, { 0x48, 0x00, 0x01 } }, + { 9, { 0x01, 0x03, 0xc5, 0x5c, 0x7a, 0x85, 0x01, 0x00, 0x54 } }, + { 9, { 0x21, 0x03, 0xc5, 0x5c, 0x7a, 0x85, 0x01, 0x00, 0x54 } }, + { 9, { 0x09, 0x0b, 0xb4, 0x6b, 0x74, 0x85, 0x95, 0x00, 0x34 } }, + { 9, { 0x29, 0x0b, 0xb4, 0x6b, 0x74, 0x85, 0x95, 0x00, 0x34 } }, + { 9, { 0x11, 0x17, 0x43, 0x62, 0x68, 0x89, 0xd1, 0xff, 0xb0 } }, + { 9, { 0x31, 0x17, 0x43, 0x62, 0x68, 0x89, 0xd1, 0xff, 0xb0 } }, + { 9, { 0x19, 0x20, 0x62, 0x51, 0x5a, 0x95, 0x19, 0x01, 0x50 } }, + { 9, { 0x39, 0x20, 0x62, 0x51, 0x5a, 0x95, 0x19, 0x01, 0x50 } }, + { 9, { 0x05, 0x3e, 0xd2, 0x69, 0x4e, 0x9a, 0x51, 0x00, 0xf0 } }, + { 9, { 0x25, 0x3e, 0xd2, 0x69, 0x4e, 0x9a, 0x51, 0x00, 0xf0 } }, + { 9, { 0x0d, 0x3d, 0xa1, 0x40, 0x7d, 0x9f, 0x29, 0xfe, 0x14 } }, + { 9, { 0x2d, 0x3d, 0xa1, 0x40, 0x7d, 0x9f, 0x29, 0xfe, 0x14 } }, + { 9, { 0x15, 0x73, 0xa1, 0x50, 0x5d, 0xa6, 0xf5, 0xfe, 0x38 } }, + { 9, { 0x35, 0x73, 0xa1, 0x50, 0x5d, 0xa6, 0xf5, 0xfe, 0x38 } }, + { 9, { 0x1d, 0xed, 0xd0, 0x68, 0x29, 0xb4, 0xe1, 0x00, 0xb8 } }, + { 9, { 0x3d, 0xed, 0xd0, 0x68, 0x29, 0xb4, 0xe1, 0x00, 0xb8 } }, + { 3, { 0x80, 0xb3, 0x0a } }, + {-1, { 0 } } +}; + +/* bring hardware to a sane state. this has to be done, just in case someone + wants to capture from this device before it has been properly initialized. + the capture engine would badly fail, because no valid signal arrives on the + saa7146, thus leading to timeouts and stuff. */ +static int mxb_init_done(struct saa7146_dev* dev) +{ + struct mxb* mxb = (struct mxb*)dev->ext_priv; + struct i2c_msg msg; + struct tuner_setup tun_setup; + v4l2_std_id std = V4L2_STD_PAL_BG; + + int i, err = 0; + + /* mute audio on tea6420s */ + tea6420_route(mxb, 6); + + /* select video mode in saa7111a */ + saa7111a_call(mxb, video, s_std, std); + + /* select tuner-output on saa7111a */ + saa7111a_call(mxb, video, s_routing, SAA7115_COMPOSITE0, + SAA7111_FMT_CCIR, 0); + + /* select a tuner type */ + tun_setup.mode_mask = T_ANALOG_TV; + tun_setup.addr = ADDR_UNSET; + tun_setup.type = TUNER_PHILIPS_PAL; + tuner_call(mxb, tuner, s_type_addr, &tun_setup); + /* tune in some frequency on tuner */ + mxb->cur_freq.tuner = 0; + mxb->cur_freq.type = V4L2_TUNER_ANALOG_TV; + mxb->cur_freq.frequency = freq; + tuner_call(mxb, tuner, s_frequency, &mxb->cur_freq); + + /* set a default video standard */ + /* These two gpio calls set the GPIO pins that control the tda9820 */ + saa7146_write(dev, GPIO_CTRL, 0x00404050); + saa7111a_call(mxb, core, s_gpio, 1); + saa7111a_call(mxb, video, s_std, std); + tuner_call(mxb, video, s_std, std); + + /* switch to tuner-channel on tea6415c */ + tea6415c_call(mxb, video, s_routing, 3, 17, 0); + + /* select tuner-output on multicable on tea6415c */ + tea6415c_call(mxb, video, s_routing, 3, 13, 0); + + /* the rest for mxb */ + mxb->cur_input = 0; + mxb->cur_audinput = video_audio_connect[mxb->cur_input]; + mxb->cur_mute = 1; + + mxb->cur_mode = V4L2_TUNER_MODE_STEREO; + mxb_update_audmode(mxb); + + /* check if the saa7740 (aka 'sound arena module') is present + on the mxb. if so, we must initialize it. due to lack of + information about the saa7740, the values were reverse + engineered. */ + msg.addr = 0x1b; + msg.flags = 0; + msg.len = mxb_saa7740_init[0].length; + msg.buf = &mxb_saa7740_init[0].data[0]; + + err = i2c_transfer(&mxb->i2c_adapter, &msg, 1); + if (err == 1) { + /* the sound arena module is a pos, that's probably the reason + philips refuses to hand out a datasheet for the saa7740... + it seems to screw up the i2c bus, so we disable fast irq + based i2c transactions here and rely on the slow and safe + polling method ... */ + extension.flags &= ~SAA7146_USE_I2C_IRQ; + for (i = 1; ; i++) { + if (-1 == mxb_saa7740_init[i].length) + break; + + msg.len = mxb_saa7740_init[i].length; + msg.buf = &mxb_saa7740_init[i].data[0]; + err = i2c_transfer(&mxb->i2c_adapter, &msg, 1); + if (err != 1) { + DEB_D("failed to initialize 'sound arena module'\n"); + goto err; + } + } + pr_info("'sound arena module' detected\n"); + } +err: + /* the rest for saa7146: you should definitely set some basic values + for the input-port handling of the saa7146. */ + + /* ext->saa has been filled by the core driver */ + + /* some stuff is done via variables */ + saa7146_set_hps_source_and_sync(dev, input_port_selection[mxb->cur_input].hps_source, + input_port_selection[mxb->cur_input].hps_sync); + + /* some stuff is done via direct write to the registers */ + + /* this is ugly, but because of the fact that this is completely + hardware dependend, it should be done directly... */ + saa7146_write(dev, DD1_STREAM_B, 0x00000000); + saa7146_write(dev, DD1_INIT, 0x02000200); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + + return 0; +} + +/* interrupt-handler. this gets called when irq_mask is != 0. + it must clear the interrupt-bits in irq_mask it has handled */ +/* +void mxb_irq_bh(struct saa7146_dev* dev, u32* irq_mask) +{ + struct mxb* mxb = (struct mxb*)dev->ext_priv; +} +*/ + +static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i) +{ + DEB_EE("VIDIOC_ENUMINPUT %d\n", i->index); + if (i->index >= MXB_INPUTS) + return -EINVAL; + memcpy(i, &mxb_inputs[i->index], sizeof(struct v4l2_input)); + return 0; +} + +static int vidioc_g_input(struct file *file, void *fh, unsigned int *i) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct mxb *mxb = (struct mxb *)dev->ext_priv; + *i = mxb->cur_input; + + DEB_EE("VIDIOC_G_INPUT %d\n", *i); + return 0; +} + +static int vidioc_s_input(struct file *file, void *fh, unsigned int input) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct mxb *mxb = (struct mxb *)dev->ext_priv; + int err = 0; + int i = 0; + + DEB_EE("VIDIOC_S_INPUT %d\n", input); + + if (input >= MXB_INPUTS) + return -EINVAL; + + mxb->cur_input = input; + + saa7146_set_hps_source_and_sync(dev, input_port_selection[input].hps_source, + input_port_selection[input].hps_sync); + + /* prepare switching of tea6415c and saa7111a; + have a look at the 'background'-file for further information */ + switch (input) { + case TUNER: + i = SAA7115_COMPOSITE0; + + err = tea6415c_call(mxb, video, s_routing, 3, 17, 0); + + /* connect tuner-output always to multicable */ + if (!err) + err = tea6415c_call(mxb, video, s_routing, 3, 13, 0); + break; + case AUX3_YC: + /* nothing to be done here. aux3_yc is + directly connected to the saa711a */ + i = SAA7115_SVIDEO1; + break; + case AUX3: + /* nothing to be done here. aux3 is + directly connected to the saa711a */ + i = SAA7115_COMPOSITE1; + break; + case AUX1: + i = SAA7115_COMPOSITE0; + err = tea6415c_call(mxb, video, s_routing, 1, 17, 0); + break; + } + + if (err) + return err; + + /* switch video in saa7111a */ + if (saa7111a_call(mxb, video, s_routing, i, SAA7111_FMT_CCIR, 0)) + pr_err("VIDIOC_S_INPUT: could not address saa7111a\n"); + + mxb->cur_audinput = video_audio_connect[input]; + /* switch the audio-source only if necessary */ + if (0 == mxb->cur_mute) + tea6420_route(mxb, mxb->cur_audinput); + if (mxb->cur_audinput == 0) + mxb_update_audmode(mxb); + + return 0; +} + +static int vidioc_g_tuner(struct file *file, void *fh, struct v4l2_tuner *t) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct mxb *mxb = (struct mxb *)dev->ext_priv; + + if (t->index) { + DEB_D("VIDIOC_G_TUNER: channel %d does not have a tuner attached\n", + t->index); + return -EINVAL; + } + + DEB_EE("VIDIOC_G_TUNER: %d\n", t->index); + + memset(t, 0, sizeof(*t)); + strscpy(t->name, "TV Tuner", sizeof(t->name)); + t->type = V4L2_TUNER_ANALOG_TV; + t->capability = V4L2_TUNER_CAP_NORM | V4L2_TUNER_CAP_STEREO | + V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP; + t->audmode = mxb->cur_mode; + return call_all(dev, tuner, g_tuner, t); +} + +static int vidioc_s_tuner(struct file *file, void *fh, const struct v4l2_tuner *t) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct mxb *mxb = (struct mxb *)dev->ext_priv; + + if (t->index) { + DEB_D("VIDIOC_S_TUNER: channel %d does not have a tuner attached\n", + t->index); + return -EINVAL; + } + + mxb->cur_mode = t->audmode; + return call_all(dev, tuner, s_tuner, t); +} + +static int vidioc_querystd(struct file *file, void *fh, v4l2_std_id *norm) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + + return call_all(dev, video, querystd, norm); +} + +static int vidioc_g_frequency(struct file *file, void *fh, struct v4l2_frequency *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct mxb *mxb = (struct mxb *)dev->ext_priv; + + if (f->tuner) + return -EINVAL; + *f = mxb->cur_freq; + + DEB_EE("VIDIOC_G_FREQ: freq:0x%08x\n", mxb->cur_freq.frequency); + return 0; +} + +static int vidioc_s_frequency(struct file *file, void *fh, const struct v4l2_frequency *f) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct mxb *mxb = (struct mxb *)dev->ext_priv; + struct saa7146_vv *vv = dev->vv_data; + + if (f->tuner) + return -EINVAL; + + if (V4L2_TUNER_ANALOG_TV != f->type) + return -EINVAL; + + DEB_EE("VIDIOC_S_FREQUENCY: freq:0x%08x\n", mxb->cur_freq.frequency); + + /* tune in desired frequency */ + tuner_call(mxb, tuner, s_frequency, f); + /* let the tuner subdev clamp the frequency to the tuner range */ + mxb->cur_freq = *f; + tuner_call(mxb, tuner, g_frequency, &mxb->cur_freq); + if (mxb->cur_audinput == 0) + mxb_update_audmode(mxb); + + if (mxb->cur_input) + return 0; + + /* hack: changing the frequency should invalidate the vbi-counter (=> alevt) */ + spin_lock(&dev->slock); + vv->vbi_fieldcount = 0; + spin_unlock(&dev->slock); + + return 0; +} + +static int vidioc_enumaudio(struct file *file, void *fh, struct v4l2_audio *a) +{ + if (a->index >= MXB_AUDIOS) + return -EINVAL; + *a = mxb_audios[a->index]; + return 0; +} + +static int vidioc_g_audio(struct file *file, void *fh, struct v4l2_audio *a) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct mxb *mxb = (struct mxb *)dev->ext_priv; + + DEB_EE("VIDIOC_G_AUDIO\n"); + *a = mxb_audios[mxb->cur_audinput]; + return 0; +} + +static int vidioc_s_audio(struct file *file, void *fh, const struct v4l2_audio *a) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct mxb *mxb = (struct mxb *)dev->ext_priv; + + DEB_D("VIDIOC_S_AUDIO %d\n", a->index); + if (a->index >= 32 || + !(mxb_inputs[mxb->cur_input].audioset & (1 << a->index))) + return -EINVAL; + + if (mxb->cur_audinput != a->index) { + mxb->cur_audinput = a->index; + tea6420_route(mxb, a->index); + if (mxb->cur_audinput == 0) + mxb_update_audmode(mxb); + } + return 0; +} + +#ifdef CONFIG_VIDEO_ADV_DEBUG +static int vidioc_g_register(struct file *file, void *fh, struct v4l2_dbg_register *reg) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + + if (reg->reg > pci_resource_len(dev->pci, 0) - 4) + return -EINVAL; + reg->val = saa7146_read(dev, reg->reg); + reg->size = 4; + return 0; +} + +static int vidioc_s_register(struct file *file, void *fh, const struct v4l2_dbg_register *reg) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + + if (reg->reg > pci_resource_len(dev->pci, 0) - 4) + return -EINVAL; + saa7146_write(dev, reg->reg, reg->val); + return 0; +} +#endif + +static struct saa7146_ext_vv vv_data; + +/* this function only gets called when the probing was successful */ +static int mxb_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info) +{ + struct mxb *mxb; + int ret; + + DEB_EE("dev:%p\n", dev); + + ret = saa7146_vv_init(dev, &vv_data); + if (ret) { + ERR("Error in saa7146_vv_init()"); + return ret; + } + + if (mxb_probe(dev)) { + saa7146_vv_release(dev); + return -1; + } + mxb = (struct mxb *)dev->ext_priv; + + vv_data.vid_ops.vidioc_enum_input = vidioc_enum_input; + vv_data.vid_ops.vidioc_g_input = vidioc_g_input; + vv_data.vid_ops.vidioc_s_input = vidioc_s_input; + vv_data.vid_ops.vidioc_querystd = vidioc_querystd; + vv_data.vid_ops.vidioc_g_tuner = vidioc_g_tuner; + vv_data.vid_ops.vidioc_s_tuner = vidioc_s_tuner; + vv_data.vid_ops.vidioc_g_frequency = vidioc_g_frequency; + vv_data.vid_ops.vidioc_s_frequency = vidioc_s_frequency; + vv_data.vid_ops.vidioc_enumaudio = vidioc_enumaudio; + vv_data.vid_ops.vidioc_g_audio = vidioc_g_audio; + vv_data.vid_ops.vidioc_s_audio = vidioc_s_audio; +#ifdef CONFIG_VIDEO_ADV_DEBUG + vv_data.vid_ops.vidioc_g_register = vidioc_g_register; + vv_data.vid_ops.vidioc_s_register = vidioc_s_register; +#endif + if (saa7146_register_device(&mxb->video_dev, dev, "mxb", VFL_TYPE_VIDEO)) { + ERR("cannot register capture v4l2 device. skipping.\n"); + saa7146_vv_release(dev); + return -1; + } + + /* initialization stuff (vbi) (only for revision > 0 and for extensions which want it)*/ + if (MXB_BOARD_CAN_DO_VBI(dev)) { + if (saa7146_register_device(&mxb->vbi_dev, dev, "mxb", VFL_TYPE_VBI)) { + ERR("cannot register vbi v4l2 device. skipping.\n"); + } + } + + pr_info("found Multimedia eXtension Board #%d\n", mxb_num); + + mxb_num++; + mxb_init_done(dev); + return 0; +} + +static int mxb_detach(struct saa7146_dev *dev) +{ + struct mxb *mxb = (struct mxb *)dev->ext_priv; + + DEB_EE("dev:%p\n", dev); + + /* mute audio on tea6420s */ + tea6420_route(mxb, 6); + + saa7146_unregister_device(&mxb->video_dev,dev); + if (MXB_BOARD_CAN_DO_VBI(dev)) + saa7146_unregister_device(&mxb->vbi_dev, dev); + saa7146_vv_release(dev); + + mxb_num--; + + i2c_del_adapter(&mxb->i2c_adapter); + kfree(mxb); + + return 0; +} + +static int std_callback(struct saa7146_dev *dev, struct saa7146_standard *standard) +{ + struct mxb *mxb = (struct mxb *)dev->ext_priv; + + if (V4L2_STD_PAL_I == standard->id) { + v4l2_std_id std = V4L2_STD_PAL_I; + + DEB_D("VIDIOC_S_STD: setting mxb for PAL_I\n"); + /* These two gpio calls set the GPIO pins that control the tda9820 */ + saa7146_write(dev, GPIO_CTRL, 0x00404050); + saa7111a_call(mxb, core, s_gpio, 0); + saa7111a_call(mxb, video, s_std, std); + if (mxb->cur_input == 0) + tuner_call(mxb, video, s_std, std); + } else { + v4l2_std_id std = V4L2_STD_PAL_BG; + + if (mxb->cur_input) + std = standard->id; + DEB_D("VIDIOC_S_STD: setting mxb for PAL/NTSC/SECAM\n"); + /* These two gpio calls set the GPIO pins that control the tda9820 */ + saa7146_write(dev, GPIO_CTRL, 0x00404050); + saa7111a_call(mxb, core, s_gpio, 1); + saa7111a_call(mxb, video, s_std, std); + if (mxb->cur_input == 0) + tuner_call(mxb, video, s_std, std); + } + return 0; +} + +static struct saa7146_standard standard[] = { + { + .name = "PAL-BG", .id = V4L2_STD_PAL_BG, + .v_offset = 0x17, .v_field = 288, + .h_offset = 0x14, .h_pixels = 680, + .v_max_out = 576, .h_max_out = 768, + }, { + .name = "PAL-I", .id = V4L2_STD_PAL_I, + .v_offset = 0x17, .v_field = 288, + .h_offset = 0x14, .h_pixels = 680, + .v_max_out = 576, .h_max_out = 768, + }, { + .name = "NTSC", .id = V4L2_STD_NTSC, + .v_offset = 0x16, .v_field = 240, + .h_offset = 0x06, .h_pixels = 708, + .v_max_out = 480, .h_max_out = 640, + }, { + .name = "SECAM", .id = V4L2_STD_SECAM, + .v_offset = 0x14, .v_field = 288, + .h_offset = 0x14, .h_pixels = 720, + .v_max_out = 576, .h_max_out = 768, + } +}; + +static struct saa7146_pci_extension_data mxb = { + .ext_priv = "Multimedia eXtension Board", + .ext = &extension, +}; + +static const struct pci_device_id pci_tbl[] = { + { + .vendor = PCI_VENDOR_ID_PHILIPS, + .device = PCI_DEVICE_ID_PHILIPS_SAA7146, + .subvendor = 0x0000, + .subdevice = 0x0000, + .driver_data = (unsigned long)&mxb, + }, { + .vendor = 0, + } +}; + +MODULE_DEVICE_TABLE(pci, pci_tbl); + +static struct saa7146_ext_vv vv_data = { + .inputs = MXB_INPUTS, + .capabilities = V4L2_CAP_TUNER | V4L2_CAP_VBI_CAPTURE | V4L2_CAP_AUDIO, + .stds = &standard[0], + .num_stds = ARRAY_SIZE(standard), + .std_callback = &std_callback, +}; + +static struct saa7146_extension extension = { + .name = "Multimedia eXtension Board", + .flags = SAA7146_USE_I2C_IRQ, + + .pci_tbl = &pci_tbl[0], + .module = THIS_MODULE, + + .attach = mxb_attach, + .detach = mxb_detach, + + .irq_mask = 0, + .irq_func = NULL, +}; + +static int __init mxb_init_module(void) +{ + if (saa7146_register_extension(&extension)) { + DEB_S("failed to register extension\n"); + return -ENODEV; + } + + return 0; +} + +static void __exit mxb_cleanup_module(void) +{ + saa7146_unregister_extension(&extension); +} + +module_init(mxb_init_module); +module_exit(mxb_cleanup_module); + +MODULE_DESCRIPTION("video4linux-2 driver for the Siemens-Nixdorf 'Multimedia eXtension board'"); +MODULE_AUTHOR("Michael Hunold "); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/deprecated/saa7146/ttpci/Kconfig b/drivers/staging/media/deprecated/saa7146/ttpci/Kconfig new file mode 100644 index 000000000..8c85ed58e --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/ttpci/Kconfig @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DVB_BUDGET_CORE + tristate "SAA7146 DVB cards (aka Budget, Nova-PCI) (DEPRECATED)" + depends on DVB_CORE && PCI && I2C + select VIDEO_SAA7146 + select TTPCI_EEPROM + help + Support for simple SAA7146 based DVB cards + (so called Budget- or Nova-PCI cards) without onboard + MPEG2 decoder. + +config DVB_BUDGET + tristate "Budget cards (DEPRECATED)" + depends on DVB_BUDGET_CORE && I2C + select DVB_STV0299 if MEDIA_SUBDRV_AUTOSELECT + select DVB_VES1X93 if MEDIA_SUBDRV_AUTOSELECT + select DVB_VES1820 if MEDIA_SUBDRV_AUTOSELECT + select DVB_L64781 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA8083 if MEDIA_SUBDRV_AUTOSELECT + select DVB_S5H1420 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA10086 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA826X if MEDIA_SUBDRV_AUTOSELECT + select DVB_LNBP21 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA1004X if MEDIA_SUBDRV_AUTOSELECT + select DVB_ISL6423 if MEDIA_SUBDRV_AUTOSELECT + select DVB_STV090x if MEDIA_SUBDRV_AUTOSELECT + select DVB_STV6110x if MEDIA_SUBDRV_AUTOSELECT + help + Support for simple SAA7146 based DVB cards (so called Budget- + or Nova-PCI cards) without onboard MPEG2 decoder, and without + analog inputs or an onboard Common Interface connector. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + Say Y if you own such a card and want to use it. + + To compile this driver as a module, choose M here: the + module will be called budget. + +config DVB_BUDGET_CI + tristate "Budget cards with onboard CI connector (DEPRECATED)" + depends on DVB_BUDGET_CORE && I2C + select DVB_STV0297 if MEDIA_SUBDRV_AUTOSELECT + select DVB_STV0299 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA1004X if MEDIA_SUBDRV_AUTOSELECT + select DVB_STB0899 if MEDIA_SUBDRV_AUTOSELECT + select DVB_STB6100 if MEDIA_SUBDRV_AUTOSELECT + select DVB_LNBP21 if MEDIA_SUBDRV_AUTOSELECT + select DVB_STV0288 if MEDIA_SUBDRV_AUTOSELECT + select DVB_STB6000 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA10023 if MEDIA_SUBDRV_AUTOSELECT + select MEDIA_TUNER_TDA827X if MEDIA_SUBDRV_AUTOSELECT + depends on RC_CORE + help + Support for simple SAA7146 based DVB cards + (so called Budget- or Nova-PCI cards) without onboard + MPEG2 decoder, but with onboard Common Interface connector. + + Note: The Common Interface is not yet supported by this driver + due to lack of information from the vendor. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + Say Y if you own such a card and want to use it. + + To compile this driver as a module, choose M here: the + module will be called budget-ci. + +config DVB_BUDGET_AV + tristate "Budget cards with analog video inputs (DEPRECATED)" + depends on DVB_BUDGET_CORE && I2C + select VIDEO_SAA7146_VV + depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV + select DVB_PLL if MEDIA_SUBDRV_AUTOSELECT + select DVB_STV0299 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA1004X if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA10021 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA10023 if MEDIA_SUBDRV_AUTOSELECT + select DVB_STB0899 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TDA8261 if MEDIA_SUBDRV_AUTOSELECT + select DVB_TUA6100 if MEDIA_SUBDRV_AUTOSELECT + help + Support for simple SAA7146 based DVB cards + (so called Budget- or Nova-PCI cards) without onboard + MPEG2 decoder, but with one or more analog video inputs. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + Say Y if you own such a card and want to use it. + + To compile this driver as a module, choose M here: the + module will be called budget-av. diff --git a/drivers/staging/media/deprecated/saa7146/ttpci/Makefile b/drivers/staging/media/deprecated/saa7146/ttpci/Makefile new file mode 100644 index 000000000..b0708f6e4 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/ttpci/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the kernel SAA7146 FULL TS DVB device driver +# + +obj-$(CONFIG_DVB_BUDGET_CORE) += budget-core.o +obj-$(CONFIG_DVB_BUDGET) += budget.o +obj-$(CONFIG_DVB_BUDGET_AV) += budget-av.o +obj-$(CONFIG_DVB_BUDGET_CI) += budget-ci.o + +ccflags-y += -I $(srctree)/drivers/media/dvb-frontends/ +ccflags-y += -I $(srctree)/drivers/media/tuners +ccflags-y += -I $(srctree)/drivers/media/common diff --git a/drivers/staging/media/deprecated/saa7146/ttpci/TODO b/drivers/staging/media/deprecated/saa7146/ttpci/TODO new file mode 100644 index 000000000..c9ae2ec79 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/ttpci/TODO @@ -0,0 +1,7 @@ +The saa7146-based drivers are one of the few drivers still not using +the vb2 framework, so these drivers are now deprecated with the intent of +removing them altogether by the beginning of 2023. + +In order to keep these drivers they have to be converted to vb2. +If someone is interested in doing this work, then contact the +linux-media mailinglist (https://linuxtv.org/lists.php). diff --git a/drivers/staging/media/deprecated/saa7146/ttpci/budget-av.c b/drivers/staging/media/deprecated/saa7146/ttpci/budget-av.c new file mode 100644 index 000000000..0c61a2dec --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/ttpci/budget-av.c @@ -0,0 +1,1622 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * budget-av.c: driver for the SAA7146 based Budget DVB cards + * with analog video in + * + * Compiled from various sources by Michael Hunold + * + * CI interface support (c) 2004 Olivier Gournet & + * Andrew de Quincey + * + * Copyright (C) 2002 Ralph Metzler + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * the project's page is at https://linuxtv.org + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include "budget.h" +#include "stv0299.h" +#include "stb0899_drv.h" +#include "stb0899_reg.h" +#include "stb0899_cfg.h" +#include "tda8261.h" +#include "tda8261_cfg.h" +#include "tda1002x.h" +#include "tda1004x.h" +#include "tua6100.h" +#include "dvb-pll.h" +#include "../common/saa7146_vv.h" +#include +#include +#include +#include +#include +#include + +#include + +#define DEBICICAM 0x02420000 + +#define SLOTSTATUS_NONE 1 +#define SLOTSTATUS_PRESENT 2 +#define SLOTSTATUS_RESET 4 +#define SLOTSTATUS_READY 8 +#define SLOTSTATUS_OCCUPIED (SLOTSTATUS_PRESENT|SLOTSTATUS_RESET|SLOTSTATUS_READY) + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +struct budget_av { + struct budget budget; + struct video_device vd; + int cur_input; + int has_saa7113; + struct tasklet_struct ciintf_irq_tasklet; + int slot_status; + struct dvb_ca_en50221 ca; + u8 reinitialise_demod:1; +}; + +static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot); + + +/* GPIO Connections: + * 0 - Vcc/Reset (Reset is controlled by capacitor). Resets the frontend *AS WELL*! + * 1 - CI memory select 0=>IO memory, 1=>Attribute Memory + * 2 - CI Card Enable (Active Low) + * 3 - CI Card Detect + */ + +/**************************************************************************** + * INITIALIZATION + ****************************************************************************/ + +static u8 i2c_readreg(struct i2c_adapter *i2c, u8 id, u8 reg) +{ + u8 mm1[] = { 0x00 }; + u8 mm2[] = { 0x00 }; + struct i2c_msg msgs[2]; + + msgs[0].flags = 0; + msgs[1].flags = I2C_M_RD; + msgs[0].addr = msgs[1].addr = id / 2; + mm1[0] = reg; + msgs[0].len = 1; + msgs[1].len = 1; + msgs[0].buf = mm1; + msgs[1].buf = mm2; + + i2c_transfer(i2c, msgs, 2); + + return mm2[0]; +} + +static int i2c_readregs(struct i2c_adapter *i2c, u8 id, u8 reg, u8 * buf, u8 len) +{ + u8 mm1[] = { reg }; + struct i2c_msg msgs[2] = { + {.addr = id / 2,.flags = 0,.buf = mm1,.len = 1}, + {.addr = id / 2,.flags = I2C_M_RD,.buf = buf,.len = len} + }; + + if (i2c_transfer(i2c, msgs, 2) != 2) + return -EIO; + + return 0; +} + +static int i2c_writereg(struct i2c_adapter *i2c, u8 id, u8 reg, u8 val) +{ + u8 msg[2] = { reg, val }; + struct i2c_msg msgs; + + msgs.flags = 0; + msgs.addr = id / 2; + msgs.len = 2; + msgs.buf = msg; + return i2c_transfer(i2c, &msgs, 1); +} + +static int ciintf_read_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address) +{ + struct budget_av *budget_av = (struct budget_av *) ca->data; + int result; + + if (slot != 0) + return -EINVAL; + + saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTHI); + udelay(1); + + result = ttpci_budget_debiread(&budget_av->budget, DEBICICAM, address & 0xfff, 1, 0, 1); + if (result == -ETIMEDOUT) { + ciintf_slot_shutdown(ca, slot); + pr_info("cam ejected 1\n"); + } + return result; +} + +static int ciintf_write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address, u8 value) +{ + struct budget_av *budget_av = (struct budget_av *) ca->data; + int result; + + if (slot != 0) + return -EINVAL; + + saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTHI); + udelay(1); + + result = ttpci_budget_debiwrite(&budget_av->budget, DEBICICAM, address & 0xfff, 1, value, 0, 1); + if (result == -ETIMEDOUT) { + ciintf_slot_shutdown(ca, slot); + pr_info("cam ejected 2\n"); + } + return result; +} + +static int ciintf_read_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address) +{ + struct budget_av *budget_av = (struct budget_av *) ca->data; + int result; + + if (slot != 0) + return -EINVAL; + + saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTLO); + udelay(1); + + result = ttpci_budget_debiread(&budget_av->budget, DEBICICAM, address & 3, 1, 0, 0); + if (result == -ETIMEDOUT) { + ciintf_slot_shutdown(ca, slot); + pr_info("cam ejected 3\n"); + return -ETIMEDOUT; + } + return result; +} + +static int ciintf_write_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address, u8 value) +{ + struct budget_av *budget_av = (struct budget_av *) ca->data; + int result; + + if (slot != 0) + return -EINVAL; + + saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTLO); + udelay(1); + + result = ttpci_budget_debiwrite(&budget_av->budget, DEBICICAM, address & 3, 1, value, 0, 0); + if (result == -ETIMEDOUT) { + ciintf_slot_shutdown(ca, slot); + pr_info("cam ejected 5\n"); + } + return result; +} + +static int ciintf_slot_reset(struct dvb_ca_en50221 *ca, int slot) +{ + struct budget_av *budget_av = (struct budget_av *) ca->data; + struct saa7146_dev *saa = budget_av->budget.dev; + + if (slot != 0) + return -EINVAL; + + dprintk(1, "ciintf_slot_reset\n"); + budget_av->slot_status = SLOTSTATUS_RESET; + + saa7146_setgpio(saa, 2, SAA7146_GPIO_OUTHI); /* disable card */ + + saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTHI); /* Vcc off */ + msleep(2); + saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTLO); /* Vcc on */ + msleep(20); /* 20 ms Vcc settling time */ + + saa7146_setgpio(saa, 2, SAA7146_GPIO_OUTLO); /* enable card */ + ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB); + msleep(20); + + /* reinitialise the frontend if necessary */ + if (budget_av->reinitialise_demod) + dvb_frontend_reinitialise(budget_av->budget.dvb_frontend); + + return 0; +} + +static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot) +{ + struct budget_av *budget_av = (struct budget_av *) ca->data; + struct saa7146_dev *saa = budget_av->budget.dev; + + if (slot != 0) + return -EINVAL; + + dprintk(1, "ciintf_slot_shutdown\n"); + + ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB); + budget_av->slot_status = SLOTSTATUS_NONE; + + return 0; +} + +static int ciintf_slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) +{ + struct budget_av *budget_av = (struct budget_av *) ca->data; + struct saa7146_dev *saa = budget_av->budget.dev; + + if (slot != 0) + return -EINVAL; + + dprintk(1, "ciintf_slot_ts_enable: %d\n", budget_av->slot_status); + + ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTA); + + return 0; +} + +static int ciintf_poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) +{ + struct budget_av *budget_av = (struct budget_av *) ca->data; + struct saa7146_dev *saa = budget_av->budget.dev; + int result; + + if (slot != 0) + return -EINVAL; + + /* test the card detect line - needs to be done carefully + * since it never goes high for some CAMs on this interface (e.g. topuptv) */ + if (budget_av->slot_status == SLOTSTATUS_NONE) { + saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT); + udelay(1); + if (saa7146_read(saa, PSR) & MASK_06) { + if (budget_av->slot_status == SLOTSTATUS_NONE) { + budget_av->slot_status = SLOTSTATUS_PRESENT; + pr_info("cam inserted A\n"); + } + } + saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTLO); + } + + /* We also try and read from IO memory to work round the above detection bug. If + * there is no CAM, we will get a timeout. Only done if there is no cam + * present, since this test actually breaks some cams :( + * + * if the CI interface is not open, we also do the above test since we + * don't care if the cam has problems - we'll be resetting it on open() anyway */ + if ((budget_av->slot_status == SLOTSTATUS_NONE) || (!open)) { + saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTLO); + result = ttpci_budget_debiread(&budget_av->budget, DEBICICAM, 0, 1, 0, 1); + if ((result >= 0) && (budget_av->slot_status == SLOTSTATUS_NONE)) { + budget_av->slot_status = SLOTSTATUS_PRESENT; + pr_info("cam inserted B\n"); + } else if (result < 0) { + if (budget_av->slot_status != SLOTSTATUS_NONE) { + ciintf_slot_shutdown(ca, slot); + pr_info("cam ejected 5\n"); + return 0; + } + } + } + + /* read from attribute memory in reset/ready state to know when the CAM is ready */ + if (budget_av->slot_status == SLOTSTATUS_RESET) { + result = ciintf_read_attribute_mem(ca, slot, 0); + if (result == 0x1d) { + budget_av->slot_status = SLOTSTATUS_READY; + } + } + + /* work out correct return code */ + if (budget_av->slot_status != SLOTSTATUS_NONE) { + if (budget_av->slot_status & SLOTSTATUS_READY) { + return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY; + } + return DVB_CA_EN50221_POLL_CAM_PRESENT; + } + return 0; +} + +static int ciintf_init(struct budget_av *budget_av) +{ + struct saa7146_dev *saa = budget_av->budget.dev; + int result; + + memset(&budget_av->ca, 0, sizeof(struct dvb_ca_en50221)); + + saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTLO); + saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTLO); + saa7146_setgpio(saa, 2, SAA7146_GPIO_OUTLO); + saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTLO); + + /* Enable DEBI pins */ + saa7146_write(saa, MC1, MASK_27 | MASK_11); + + /* register CI interface */ + budget_av->ca.owner = THIS_MODULE; + budget_av->ca.read_attribute_mem = ciintf_read_attribute_mem; + budget_av->ca.write_attribute_mem = ciintf_write_attribute_mem; + budget_av->ca.read_cam_control = ciintf_read_cam_control; + budget_av->ca.write_cam_control = ciintf_write_cam_control; + budget_av->ca.slot_reset = ciintf_slot_reset; + budget_av->ca.slot_shutdown = ciintf_slot_shutdown; + budget_av->ca.slot_ts_enable = ciintf_slot_ts_enable; + budget_av->ca.poll_slot_status = ciintf_poll_slot_status; + budget_av->ca.data = budget_av; + budget_av->budget.ci_present = 1; + budget_av->slot_status = SLOTSTATUS_NONE; + + if ((result = dvb_ca_en50221_init(&budget_av->budget.dvb_adapter, + &budget_av->ca, 0, 1)) != 0) { + pr_err("ci initialisation failed\n"); + goto error; + } + + pr_info("ci interface initialised\n"); + return 0; + +error: + saa7146_write(saa, MC1, MASK_27); + return result; +} + +static void ciintf_deinit(struct budget_av *budget_av) +{ + struct saa7146_dev *saa = budget_av->budget.dev; + + saa7146_setgpio(saa, 0, SAA7146_GPIO_INPUT); + saa7146_setgpio(saa, 1, SAA7146_GPIO_INPUT); + saa7146_setgpio(saa, 2, SAA7146_GPIO_INPUT); + saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT); + + /* release the CA device */ + dvb_ca_en50221_release(&budget_av->ca); + + /* disable DEBI pins */ + saa7146_write(saa, MC1, MASK_27); +} + + +static const u8 saa7113_tab[] = { + 0x01, 0x08, + 0x02, 0xc0, + 0x03, 0x33, + 0x04, 0x00, + 0x05, 0x00, + 0x06, 0xeb, + 0x07, 0xe0, + 0x08, 0x28, + 0x09, 0x00, + 0x0a, 0x80, + 0x0b, 0x47, + 0x0c, 0x40, + 0x0d, 0x00, + 0x0e, 0x01, + 0x0f, 0x44, + + 0x10, 0x08, + 0x11, 0x0c, + 0x12, 0x7b, + 0x13, 0x00, + 0x15, 0x00, 0x16, 0x00, 0x17, 0x00, + + 0x57, 0xff, + 0x40, 0x82, 0x58, 0x00, 0x59, 0x54, 0x5a, 0x07, + 0x5b, 0x83, 0x5e, 0x00, + 0xff +}; + +static int saa7113_init(struct budget_av *budget_av) +{ + struct budget *budget = &budget_av->budget; + struct saa7146_dev *saa = budget->dev; + const u8 *data = saa7113_tab; + + saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTHI); + msleep(200); + + if (i2c_writereg(&budget->i2c_adap, 0x4a, 0x01, 0x08) != 1) { + dprintk(1, "saa7113 not found on KNC card\n"); + return -ENODEV; + } + + dprintk(1, "saa7113 detected and initializing\n"); + + while (*data != 0xff) { + i2c_writereg(&budget->i2c_adap, 0x4a, *data, *(data + 1)); + data += 2; + } + + dprintk(1, "saa7113 status=%02x\n", i2c_readreg(&budget->i2c_adap, 0x4a, 0x1f)); + + return 0; +} + +static int saa7113_setinput(struct budget_av *budget_av, int input) +{ + struct budget *budget = &budget_av->budget; + + if (1 != budget_av->has_saa7113) + return -ENODEV; + + if (input == 1) { + i2c_writereg(&budget->i2c_adap, 0x4a, 0x02, 0xc7); + i2c_writereg(&budget->i2c_adap, 0x4a, 0x09, 0x80); + } else if (input == 0) { + i2c_writereg(&budget->i2c_adap, 0x4a, 0x02, 0xc0); + i2c_writereg(&budget->i2c_adap, 0x4a, 0x09, 0x00); + } else + return -EINVAL; + + budget_av->cur_input = input; + return 0; +} + + +static int philips_su1278_ty_ci_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio) +{ + u8 aclk = 0; + u8 bclk = 0; + u8 m1; + + aclk = 0xb5; + if (srate < 2000000) + bclk = 0x86; + else if (srate < 5000000) + bclk = 0x89; + else if (srate < 15000000) + bclk = 0x8f; + else if (srate < 45000000) + bclk = 0x95; + + m1 = 0x14; + if (srate < 4000000) + m1 = 0x10; + + stv0299_writereg(fe, 0x13, aclk); + stv0299_writereg(fe, 0x14, bclk); + stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff); + stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff); + stv0299_writereg(fe, 0x21, (ratio) & 0xf0); + stv0299_writereg(fe, 0x0f, 0x80 | m1); + + return 0; +} + +static int philips_su1278_ty_ci_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + u32 div; + u8 buf[4]; + struct budget *budget = (struct budget *) fe->dvb->priv; + struct i2c_msg msg = {.addr = 0x61,.flags = 0,.buf = buf,.len = sizeof(buf) }; + + if ((c->frequency < 950000) || (c->frequency > 2150000)) + return -EINVAL; + + div = (c->frequency + (125 - 1)) / 125; /* round correctly */ + buf[0] = (div >> 8) & 0x7f; + buf[1] = div & 0xff; + buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4; + buf[3] = 0x20; + + if (c->symbol_rate < 4000000) + buf[3] |= 1; + + if (c->frequency < 1250000) + buf[3] |= 0; + else if (c->frequency < 1550000) + buf[3] |= 0x40; + else if (c->frequency < 2050000) + buf[3] |= 0x80; + else if (c->frequency < 2150000) + buf[3] |= 0xC0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget->i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static u8 typhoon_cinergy1200s_inittab[] = { + 0x01, 0x15, + 0x02, 0x30, + 0x03, 0x00, + 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */ + 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */ + 0x06, 0x40, /* DAC not used, set to high impendance mode */ + 0x07, 0x00, /* DAC LSB */ + 0x08, 0x40, /* DiSEqC off */ + 0x09, 0x00, /* FIFO */ + 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */ + 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */ + 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */ + 0x10, 0x3f, // AGC2 0x3d + 0x11, 0x84, + 0x12, 0xb9, + 0x15, 0xc9, // lock detector threshold + 0x16, 0x00, + 0x17, 0x00, + 0x18, 0x00, + 0x19, 0x00, + 0x1a, 0x00, + 0x1f, 0x50, + 0x20, 0x00, + 0x21, 0x00, + 0x22, 0x00, + 0x23, 0x00, + 0x28, 0x00, // out imp: normal out type: parallel FEC mode:0 + 0x29, 0x1e, // 1/2 threshold + 0x2a, 0x14, // 2/3 threshold + 0x2b, 0x0f, // 3/4 threshold + 0x2c, 0x09, // 5/6 threshold + 0x2d, 0x05, // 7/8 threshold + 0x2e, 0x01, + 0x31, 0x1f, // test all FECs + 0x32, 0x19, // viterbi and synchro search + 0x33, 0xfc, // rs control + 0x34, 0x93, // error control + 0x0f, 0x92, + 0xff, 0xff +}; + +static const struct stv0299_config typhoon_config = { + .demod_address = 0x68, + .inittab = typhoon_cinergy1200s_inittab, + .mclk = 88000000UL, + .invert = 0, + .skip_reinit = 0, + .lock_output = STV0299_LOCKOUTPUT_1, + .volt13_op0_op1 = STV0299_VOLT13_OP0, + .min_delay_ms = 100, + .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate, +}; + + +static const struct stv0299_config cinergy_1200s_config = { + .demod_address = 0x68, + .inittab = typhoon_cinergy1200s_inittab, + .mclk = 88000000UL, + .invert = 0, + .skip_reinit = 0, + .lock_output = STV0299_LOCKOUTPUT_0, + .volt13_op0_op1 = STV0299_VOLT13_OP0, + .min_delay_ms = 100, + .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate, +}; + +static const struct stv0299_config cinergy_1200s_1894_0010_config = { + .demod_address = 0x68, + .inittab = typhoon_cinergy1200s_inittab, + .mclk = 88000000UL, + .invert = 1, + .skip_reinit = 0, + .lock_output = STV0299_LOCKOUTPUT_1, + .volt13_op0_op1 = STV0299_VOLT13_OP0, + .min_delay_ms = 100, + .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate, +}; + +static int philips_cu1216_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct budget *budget = (struct budget *) fe->dvb->priv; + u8 buf[6]; + struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) }; + int i; + +#define CU1216_IF 36125000 +#define TUNER_MUL 62500 + + u32 div = (c->frequency + CU1216_IF + TUNER_MUL / 2) / TUNER_MUL; + + buf[0] = (div >> 8) & 0x7f; + buf[1] = div & 0xff; + buf[2] = 0xce; + buf[3] = (c->frequency < 150000000 ? 0x01 : + c->frequency < 445000000 ? 0x02 : 0x04); + buf[4] = 0xde; + buf[5] = 0x20; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget->i2c_adap, &msg, 1) != 1) + return -EIO; + + /* wait for the pll lock */ + msg.flags = I2C_M_RD; + msg.len = 1; + for (i = 0; i < 20; i++) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget->i2c_adap, &msg, 1) == 1 && (buf[0] & 0x40)) + break; + msleep(10); + } + + /* switch the charge pump to the lower current */ + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[2]; + buf[2] &= ~0x40; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget->i2c_adap, &msg, 1) != 1) + return -EIO; + + return 0; +} + +static struct tda1002x_config philips_cu1216_config = { + .demod_address = 0x0c, + .invert = 1, +}; + +static struct tda1002x_config philips_cu1216_config_altaddress = { + .demod_address = 0x0d, + .invert = 0, +}; + +static struct tda10023_config philips_cu1216_tda10023_config = { + .demod_address = 0x0c, + .invert = 1, +}; + +static int philips_tu1216_tuner_init(struct dvb_frontend *fe) +{ + struct budget *budget = (struct budget *) fe->dvb->priv; + static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab }; + struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) }; + + // setup PLL configuration + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget->i2c_adap, &tuner_msg, 1) != 1) + return -EIO; + msleep(1); + + return 0; +} + +static int philips_tu1216_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct budget *budget = (struct budget *) fe->dvb->priv; + u8 tuner_buf[4]; + struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tuner_buf,.len = + sizeof(tuner_buf) }; + int tuner_frequency = 0; + u8 band, cp, filter; + + // determine charge pump + tuner_frequency = c->frequency + 36166000; + if (tuner_frequency < 87000000) + return -EINVAL; + else if (tuner_frequency < 130000000) + cp = 3; + else if (tuner_frequency < 160000000) + cp = 5; + else if (tuner_frequency < 200000000) + cp = 6; + else if (tuner_frequency < 290000000) + cp = 3; + else if (tuner_frequency < 420000000) + cp = 5; + else if (tuner_frequency < 480000000) + cp = 6; + else if (tuner_frequency < 620000000) + cp = 3; + else if (tuner_frequency < 830000000) + cp = 5; + else if (tuner_frequency < 895000000) + cp = 7; + else + return -EINVAL; + + // determine band + if (c->frequency < 49000000) + return -EINVAL; + else if (c->frequency < 161000000) + band = 1; + else if (c->frequency < 444000000) + band = 2; + else if (c->frequency < 861000000) + band = 4; + else + return -EINVAL; + + // setup PLL filter + switch (c->bandwidth_hz) { + case 6000000: + filter = 0; + break; + + case 7000000: + filter = 0; + break; + + case 8000000: + filter = 1; + break; + + default: + return -EINVAL; + } + + // calculate divisor + // ((36166000+((1000000/6)/2)) + Finput)/(1000000/6) + tuner_frequency = (((c->frequency / 1000) * 6) + 217496) / 1000; + + // setup tuner buffer + tuner_buf[0] = (tuner_frequency >> 8) & 0x7f; + tuner_buf[1] = tuner_frequency & 0xff; + tuner_buf[2] = 0xca; + tuner_buf[3] = (cp << 5) | (filter << 3) | band; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget->i2c_adap, &tuner_msg, 1) != 1) + return -EIO; + + msleep(1); + return 0; +} + +static int philips_tu1216_request_firmware(struct dvb_frontend *fe, + const struct firmware **fw, char *name) +{ + struct budget *budget = (struct budget *) fe->dvb->priv; + + return request_firmware(fw, name, &budget->dev->pci->dev); +} + +static struct tda1004x_config philips_tu1216_config = { + + .demod_address = 0x8, + .invert = 1, + .invert_oclk = 1, + .xtal_freq = TDA10046_XTAL_4M, + .agc_config = TDA10046_AGC_DEFAULT, + .if_freq = TDA10046_FREQ_3617, + .request_firmware = philips_tu1216_request_firmware, +}; + +static u8 philips_sd1878_inittab[] = { + 0x01, 0x15, + 0x02, 0x30, + 0x03, 0x00, + 0x04, 0x7d, + 0x05, 0x35, + 0x06, 0x40, + 0x07, 0x00, + 0x08, 0x43, + 0x09, 0x02, + 0x0C, 0x51, + 0x0D, 0x82, + 0x0E, 0x23, + 0x10, 0x3f, + 0x11, 0x84, + 0x12, 0xb9, + 0x15, 0xc9, + 0x16, 0x19, + 0x17, 0x8c, + 0x18, 0x59, + 0x19, 0xf8, + 0x1a, 0xfe, + 0x1c, 0x7f, + 0x1d, 0x00, + 0x1e, 0x00, + 0x1f, 0x50, + 0x20, 0x00, + 0x21, 0x00, + 0x22, 0x00, + 0x23, 0x00, + 0x28, 0x00, + 0x29, 0x28, + 0x2a, 0x14, + 0x2b, 0x0f, + 0x2c, 0x09, + 0x2d, 0x09, + 0x31, 0x1f, + 0x32, 0x19, + 0x33, 0xfc, + 0x34, 0x93, + 0xff, 0xff +}; + +static int philips_sd1878_ci_set_symbol_rate(struct dvb_frontend *fe, + u32 srate, u32 ratio) +{ + u8 aclk = 0; + u8 bclk = 0; + u8 m1; + + aclk = 0xb5; + if (srate < 2000000) + bclk = 0x86; + else if (srate < 5000000) + bclk = 0x89; + else if (srate < 15000000) + bclk = 0x8f; + else if (srate < 45000000) + bclk = 0x95; + + m1 = 0x14; + if (srate < 4000000) + m1 = 0x10; + + stv0299_writereg(fe, 0x0e, 0x23); + stv0299_writereg(fe, 0x0f, 0x94); + stv0299_writereg(fe, 0x10, 0x39); + stv0299_writereg(fe, 0x13, aclk); + stv0299_writereg(fe, 0x14, bclk); + stv0299_writereg(fe, 0x15, 0xc9); + stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff); + stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff); + stv0299_writereg(fe, 0x21, (ratio) & 0xf0); + stv0299_writereg(fe, 0x0f, 0x80 | m1); + + return 0; +} + +static const struct stv0299_config philips_sd1878_config = { + .demod_address = 0x68, + .inittab = philips_sd1878_inittab, + .mclk = 88000000UL, + .invert = 0, + .skip_reinit = 0, + .lock_output = STV0299_LOCKOUTPUT_1, + .volt13_op0_op1 = STV0299_VOLT13_OP0, + .min_delay_ms = 100, + .set_symbol_rate = philips_sd1878_ci_set_symbol_rate, +}; + +/* KNC1 DVB-S (STB0899) Inittab */ +static const struct stb0899_s1_reg knc1_stb0899_s1_init_1[] = { + + { STB0899_DEV_ID , 0x81 }, + { STB0899_DISCNTRL1 , 0x32 }, + { STB0899_DISCNTRL2 , 0x80 }, + { STB0899_DISRX_ST0 , 0x04 }, + { STB0899_DISRX_ST1 , 0x00 }, + { STB0899_DISPARITY , 0x00 }, + { STB0899_DISSTATUS , 0x20 }, + { STB0899_DISF22 , 0x8c }, + { STB0899_DISF22RX , 0x9a }, + { STB0899_SYSREG , 0x0b }, + { STB0899_ACRPRESC , 0x11 }, + { STB0899_ACRDIV1 , 0x0a }, + { STB0899_ACRDIV2 , 0x05 }, + { STB0899_DACR1 , 0x00 }, + { STB0899_DACR2 , 0x00 }, + { STB0899_OUTCFG , 0x00 }, + { STB0899_MODECFG , 0x00 }, + { STB0899_IRQSTATUS_3 , 0x30 }, + { STB0899_IRQSTATUS_2 , 0x00 }, + { STB0899_IRQSTATUS_1 , 0x00 }, + { STB0899_IRQSTATUS_0 , 0x00 }, + { STB0899_IRQMSK_3 , 0xf3 }, + { STB0899_IRQMSK_2 , 0xfc }, + { STB0899_IRQMSK_1 , 0xff }, + { STB0899_IRQMSK_0 , 0xff }, + { STB0899_IRQCFG , 0x00 }, + { STB0899_I2CCFG , 0x88 }, + { STB0899_I2CRPT , 0x58 }, /* Repeater=8, Stop=disabled */ + { STB0899_IOPVALUE5 , 0x00 }, + { STB0899_IOPVALUE4 , 0x20 }, + { STB0899_IOPVALUE3 , 0xc9 }, + { STB0899_IOPVALUE2 , 0x90 }, + { STB0899_IOPVALUE1 , 0x40 }, + { STB0899_IOPVALUE0 , 0x00 }, + { STB0899_GPIO00CFG , 0x82 }, + { STB0899_GPIO01CFG , 0x82 }, + { STB0899_GPIO02CFG , 0x82 }, + { STB0899_GPIO03CFG , 0x82 }, + { STB0899_GPIO04CFG , 0x82 }, + { STB0899_GPIO05CFG , 0x82 }, + { STB0899_GPIO06CFG , 0x82 }, + { STB0899_GPIO07CFG , 0x82 }, + { STB0899_GPIO08CFG , 0x82 }, + { STB0899_GPIO09CFG , 0x82 }, + { STB0899_GPIO10CFG , 0x82 }, + { STB0899_GPIO11CFG , 0x82 }, + { STB0899_GPIO12CFG , 0x82 }, + { STB0899_GPIO13CFG , 0x82 }, + { STB0899_GPIO14CFG , 0x82 }, + { STB0899_GPIO15CFG , 0x82 }, + { STB0899_GPIO16CFG , 0x82 }, + { STB0899_GPIO17CFG , 0x82 }, + { STB0899_GPIO18CFG , 0x82 }, + { STB0899_GPIO19CFG , 0x82 }, + { STB0899_GPIO20CFG , 0x82 }, + { STB0899_SDATCFG , 0xb8 }, + { STB0899_SCLTCFG , 0xba }, + { STB0899_AGCRFCFG , 0x08 }, /* 0x1c */ + { STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */ + { STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */ + { STB0899_DIRCLKCFG , 0x82 }, + { STB0899_CLKOUT27CFG , 0x7e }, + { STB0899_STDBYCFG , 0x82 }, + { STB0899_CS0CFG , 0x82 }, + { STB0899_CS1CFG , 0x82 }, + { STB0899_DISEQCOCFG , 0x20 }, + { STB0899_GPIO32CFG , 0x82 }, + { STB0899_GPIO33CFG , 0x82 }, + { STB0899_GPIO34CFG , 0x82 }, + { STB0899_GPIO35CFG , 0x82 }, + { STB0899_GPIO36CFG , 0x82 }, + { STB0899_GPIO37CFG , 0x82 }, + { STB0899_GPIO38CFG , 0x82 }, + { STB0899_GPIO39CFG , 0x82 }, + { STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */ + { STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */ + { STB0899_FILTCTRL , 0x00 }, + { STB0899_SYSCTRL , 0x00 }, + { STB0899_STOPCLK1 , 0x20 }, + { STB0899_STOPCLK2 , 0x00 }, + { STB0899_INTBUFSTATUS , 0x00 }, + { STB0899_INTBUFCTRL , 0x0a }, + { 0xffff , 0xff }, +}; + +static const struct stb0899_s1_reg knc1_stb0899_s1_init_3[] = { + { STB0899_DEMOD , 0x00 }, + { STB0899_RCOMPC , 0xc9 }, + { STB0899_AGC1CN , 0x41 }, + { STB0899_AGC1REF , 0x08 }, + { STB0899_RTC , 0x7a }, + { STB0899_TMGCFG , 0x4e }, + { STB0899_AGC2REF , 0x33 }, + { STB0899_TLSR , 0x84 }, + { STB0899_CFD , 0xee }, + { STB0899_ACLC , 0x87 }, + { STB0899_BCLC , 0x94 }, + { STB0899_EQON , 0x41 }, + { STB0899_LDT , 0xdd }, + { STB0899_LDT2 , 0xc9 }, + { STB0899_EQUALREF , 0xb4 }, + { STB0899_TMGRAMP , 0x10 }, + { STB0899_TMGTHD , 0x30 }, + { STB0899_IDCCOMP , 0xfb }, + { STB0899_QDCCOMP , 0x03 }, + { STB0899_POWERI , 0x3b }, + { STB0899_POWERQ , 0x3d }, + { STB0899_RCOMP , 0x81 }, + { STB0899_AGCIQIN , 0x80 }, + { STB0899_AGC2I1 , 0x04 }, + { STB0899_AGC2I2 , 0xf5 }, + { STB0899_TLIR , 0x25 }, + { STB0899_RTF , 0x80 }, + { STB0899_DSTATUS , 0x00 }, + { STB0899_LDI , 0xca }, + { STB0899_CFRM , 0xf1 }, + { STB0899_CFRL , 0xf3 }, + { STB0899_NIRM , 0x2a }, + { STB0899_NIRL , 0x05 }, + { STB0899_ISYMB , 0x17 }, + { STB0899_QSYMB , 0xfa }, + { STB0899_SFRH , 0x2f }, + { STB0899_SFRM , 0x68 }, + { STB0899_SFRL , 0x40 }, + { STB0899_SFRUPH , 0x2f }, + { STB0899_SFRUPM , 0x68 }, + { STB0899_SFRUPL , 0x40 }, + { STB0899_EQUAI1 , 0xfd }, + { STB0899_EQUAQ1 , 0x04 }, + { STB0899_EQUAI2 , 0x0f }, + { STB0899_EQUAQ2 , 0xff }, + { STB0899_EQUAI3 , 0xdf }, + { STB0899_EQUAQ3 , 0xfa }, + { STB0899_EQUAI4 , 0x37 }, + { STB0899_EQUAQ4 , 0x0d }, + { STB0899_EQUAI5 , 0xbd }, + { STB0899_EQUAQ5 , 0xf7 }, + { STB0899_DSTATUS2 , 0x00 }, + { STB0899_VSTATUS , 0x00 }, + { STB0899_VERROR , 0xff }, + { STB0899_IQSWAP , 0x2a }, + { STB0899_ECNT1M , 0x00 }, + { STB0899_ECNT1L , 0x00 }, + { STB0899_ECNT2M , 0x00 }, + { STB0899_ECNT2L , 0x00 }, + { STB0899_ECNT3M , 0x00 }, + { STB0899_ECNT3L , 0x00 }, + { STB0899_FECAUTO1 , 0x06 }, + { STB0899_FECM , 0x01 }, + { STB0899_VTH12 , 0xf0 }, + { STB0899_VTH23 , 0xa0 }, + { STB0899_VTH34 , 0x78 }, + { STB0899_VTH56 , 0x4e }, + { STB0899_VTH67 , 0x48 }, + { STB0899_VTH78 , 0x38 }, + { STB0899_PRVIT , 0xff }, + { STB0899_VITSYNC , 0x19 }, + { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */ + { STB0899_TSULC , 0x42 }, + { STB0899_RSLLC , 0x40 }, + { STB0899_TSLPL , 0x12 }, + { STB0899_TSCFGH , 0x0c }, + { STB0899_TSCFGM , 0x00 }, + { STB0899_TSCFGL , 0x0c }, + { STB0899_TSOUT , 0x4d }, /* 0x0d for CAM */ + { STB0899_RSSYNCDEL , 0x00 }, + { STB0899_TSINHDELH , 0x02 }, + { STB0899_TSINHDELM , 0x00 }, + { STB0899_TSINHDELL , 0x00 }, + { STB0899_TSLLSTKM , 0x00 }, + { STB0899_TSLLSTKL , 0x00 }, + { STB0899_TSULSTKM , 0x00 }, + { STB0899_TSULSTKL , 0xab }, + { STB0899_PCKLENUL , 0x00 }, + { STB0899_PCKLENLL , 0xcc }, + { STB0899_RSPCKLEN , 0xcc }, + { STB0899_TSSTATUS , 0x80 }, + { STB0899_ERRCTRL1 , 0xb6 }, + { STB0899_ERRCTRL2 , 0x96 }, + { STB0899_ERRCTRL3 , 0x89 }, + { STB0899_DMONMSK1 , 0x27 }, + { STB0899_DMONMSK0 , 0x03 }, + { STB0899_DEMAPVIT , 0x5c }, + { STB0899_PLPARM , 0x1f }, + { STB0899_PDELCTRL , 0x48 }, + { STB0899_PDELCTRL2 , 0x00 }, + { STB0899_BBHCTRL1 , 0x00 }, + { STB0899_BBHCTRL2 , 0x00 }, + { STB0899_HYSTTHRESH , 0x77 }, + { STB0899_MATCSTM , 0x00 }, + { STB0899_MATCSTL , 0x00 }, + { STB0899_UPLCSTM , 0x00 }, + { STB0899_UPLCSTL , 0x00 }, + { STB0899_DFLCSTM , 0x00 }, + { STB0899_DFLCSTL , 0x00 }, + { STB0899_SYNCCST , 0x00 }, + { STB0899_SYNCDCSTM , 0x00 }, + { STB0899_SYNCDCSTL , 0x00 }, + { STB0899_ISI_ENTRY , 0x00 }, + { STB0899_ISI_BIT_EN , 0x00 }, + { STB0899_MATSTRM , 0x00 }, + { STB0899_MATSTRL , 0x00 }, + { STB0899_UPLSTRM , 0x00 }, + { STB0899_UPLSTRL , 0x00 }, + { STB0899_DFLSTRM , 0x00 }, + { STB0899_DFLSTRL , 0x00 }, + { STB0899_SYNCSTR , 0x00 }, + { STB0899_SYNCDSTRM , 0x00 }, + { STB0899_SYNCDSTRL , 0x00 }, + { STB0899_CFGPDELSTATUS1 , 0x10 }, + { STB0899_CFGPDELSTATUS2 , 0x00 }, + { STB0899_BBFERRORM , 0x00 }, + { STB0899_BBFERRORL , 0x00 }, + { STB0899_UPKTERRORM , 0x00 }, + { STB0899_UPKTERRORL , 0x00 }, + { 0xffff , 0xff }, +}; + +/* STB0899 demodulator config for the KNC1 and clones */ +static struct stb0899_config knc1_dvbs2_config = { + .init_dev = knc1_stb0899_s1_init_1, + .init_s2_demod = stb0899_s2_init_2, + .init_s1_demod = knc1_stb0899_s1_init_3, + .init_s2_fec = stb0899_s2_init_4, + .init_tst = stb0899_s1_init_5, + + .postproc = NULL, + + .demod_address = 0x68, +// .ts_output_mode = STB0899_OUT_PARALLEL, /* types = SERIAL/PARALLEL */ + .block_sync_mode = STB0899_SYNC_FORCED, /* DSS, SYNC_FORCED/UNSYNCED */ +// .ts_pfbit_toggle = STB0899_MPEG_NORMAL, /* DirecTV, MPEG toggling seq */ + + .xtal_freq = 27000000, + .inversion = IQ_SWAP_OFF, + + .lo_clk = 76500000, + .hi_clk = 90000000, + + .esno_ave = STB0899_DVBS2_ESNO_AVE, + .esno_quant = STB0899_DVBS2_ESNO_QUANT, + .avframes_coarse = STB0899_DVBS2_AVFRAMES_COARSE, + .avframes_fine = STB0899_DVBS2_AVFRAMES_FINE, + .miss_threshold = STB0899_DVBS2_MISS_THRESHOLD, + .uwp_threshold_acq = STB0899_DVBS2_UWP_THRESHOLD_ACQ, + .uwp_threshold_track = STB0899_DVBS2_UWP_THRESHOLD_TRACK, + .uwp_threshold_sof = STB0899_DVBS2_UWP_THRESHOLD_SOF, + .sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT, + + .btr_nco_bits = STB0899_DVBS2_BTR_NCO_BITS, + .btr_gain_shift_offset = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET, + .crl_nco_bits = STB0899_DVBS2_CRL_NCO_BITS, + .ldpc_max_iter = STB0899_DVBS2_LDPC_MAX_ITER, + + .tuner_get_frequency = tda8261_get_frequency, + .tuner_set_frequency = tda8261_set_frequency, + .tuner_set_bandwidth = NULL, + .tuner_get_bandwidth = tda8261_get_bandwidth, + .tuner_set_rfsiggain = NULL +}; + +/* + * SD1878/SHA tuner config + * 1F, Single I/P, Horizontal mount, High Sensitivity + */ +static const struct tda8261_config sd1878c_config = { +// .name = "SD1878/SHA", + .addr = 0x60, + .step_size = TDA8261_STEP_1000 /* kHz */ +}; + +static u8 read_pwm(struct budget_av *budget_av) +{ + u8 b = 0xff; + u8 pwm; + struct i2c_msg msg[] = { {.addr = 0x50,.flags = 0,.buf = &b,.len = 1}, + {.addr = 0x50,.flags = I2C_M_RD,.buf = &pwm,.len = 1} + }; + + if ((i2c_transfer(&budget_av->budget.i2c_adap, msg, 2) != 2) + || (pwm == 0xff)) + pwm = 0x48; + + return pwm; +} + +#define SUBID_DVBS_KNC1 0x0010 +#define SUBID_DVBS_KNC1_PLUS 0x0011 +#define SUBID_DVBS_TYPHOON 0x4f56 +#define SUBID_DVBS_CINERGY1200 0x1154 +#define SUBID_DVBS_CYNERGY1200N 0x1155 +#define SUBID_DVBS_TV_STAR 0x0014 +#define SUBID_DVBS_TV_STAR_PLUS_X4 0x0015 +#define SUBID_DVBS_TV_STAR_CI 0x0016 +#define SUBID_DVBS2_KNC1 0x0018 +#define SUBID_DVBS2_KNC1_OEM 0x0019 +#define SUBID_DVBS_EASYWATCH_1 0x001a +#define SUBID_DVBS_EASYWATCH_2 0x001b +#define SUBID_DVBS2_EASYWATCH 0x001d +#define SUBID_DVBS_EASYWATCH 0x001e + +#define SUBID_DVBC_EASYWATCH 0x002a +#define SUBID_DVBC_EASYWATCH_MK3 0x002c +#define SUBID_DVBC_KNC1 0x0020 +#define SUBID_DVBC_KNC1_PLUS 0x0021 +#define SUBID_DVBC_KNC1_MK3 0x0022 +#define SUBID_DVBC_KNC1_TDA10024 0x0028 +#define SUBID_DVBC_KNC1_PLUS_MK3 0x0023 +#define SUBID_DVBC_CINERGY1200 0x1156 +#define SUBID_DVBC_CINERGY1200_MK3 0x1176 + +#define SUBID_DVBT_EASYWATCH 0x003a +#define SUBID_DVBT_KNC1_PLUS 0x0031 +#define SUBID_DVBT_KNC1 0x0030 +#define SUBID_DVBT_CINERGY1200 0x1157 + +static void frontend_init(struct budget_av *budget_av) +{ + struct saa7146_dev * saa = budget_av->budget.dev; + struct dvb_frontend * fe = NULL; + + /* Enable / PowerON Frontend */ + saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTLO); + + /* Wait for PowerON */ + msleep(100); + + /* additional setup necessary for the PLUS cards */ + switch (saa->pci->subsystem_device) { + case SUBID_DVBS_KNC1_PLUS: + case SUBID_DVBC_KNC1_PLUS: + case SUBID_DVBT_KNC1_PLUS: + case SUBID_DVBC_EASYWATCH: + case SUBID_DVBC_KNC1_PLUS_MK3: + case SUBID_DVBS2_KNC1: + case SUBID_DVBS2_KNC1_OEM: + case SUBID_DVBS2_EASYWATCH: + saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTHI); + break; + } + + switch (saa->pci->subsystem_device) { + + case SUBID_DVBS_KNC1: + /* + * maybe that setting is needed for other dvb-s cards as well, + * but so far it has been only confirmed for this type + */ + budget_av->reinitialise_demod = 1; + fallthrough; + case SUBID_DVBS_KNC1_PLUS: + case SUBID_DVBS_EASYWATCH_1: + if (saa->pci->subsystem_vendor == 0x1894) { + fe = dvb_attach(stv0299_attach, &cinergy_1200s_1894_0010_config, + &budget_av->budget.i2c_adap); + if (fe) { + dvb_attach(tua6100_attach, fe, 0x60, &budget_av->budget.i2c_adap); + } + } else { + fe = dvb_attach(stv0299_attach, &typhoon_config, + &budget_av->budget.i2c_adap); + if (fe) { + fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params; + } + } + break; + + case SUBID_DVBS_TV_STAR: + case SUBID_DVBS_TV_STAR_PLUS_X4: + case SUBID_DVBS_TV_STAR_CI: + case SUBID_DVBS_CYNERGY1200N: + case SUBID_DVBS_EASYWATCH: + case SUBID_DVBS_EASYWATCH_2: + fe = dvb_attach(stv0299_attach, &philips_sd1878_config, + &budget_av->budget.i2c_adap); + if (fe) { + dvb_attach(dvb_pll_attach, fe, 0x60, + &budget_av->budget.i2c_adap, + DVB_PLL_PHILIPS_SD1878_TDA8261); + } + break; + + case SUBID_DVBS_TYPHOON: + fe = dvb_attach(stv0299_attach, &typhoon_config, + &budget_av->budget.i2c_adap); + if (fe) { + fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params; + } + break; + case SUBID_DVBS2_KNC1: + case SUBID_DVBS2_KNC1_OEM: + case SUBID_DVBS2_EASYWATCH: + budget_av->reinitialise_demod = 1; + if ((fe = dvb_attach(stb0899_attach, &knc1_dvbs2_config, &budget_av->budget.i2c_adap))) + dvb_attach(tda8261_attach, fe, &sd1878c_config, &budget_av->budget.i2c_adap); + + break; + case SUBID_DVBS_CINERGY1200: + fe = dvb_attach(stv0299_attach, &cinergy_1200s_config, + &budget_av->budget.i2c_adap); + if (fe) { + fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params; + } + break; + + case SUBID_DVBC_KNC1: + case SUBID_DVBC_KNC1_PLUS: + case SUBID_DVBC_CINERGY1200: + case SUBID_DVBC_EASYWATCH: + budget_av->reinitialise_demod = 1; + budget_av->budget.dev->i2c_bitrate = SAA7146_I2C_BUS_BIT_RATE_240; + fe = dvb_attach(tda10021_attach, &philips_cu1216_config, + &budget_av->budget.i2c_adap, + read_pwm(budget_av)); + if (fe == NULL) + fe = dvb_attach(tda10021_attach, &philips_cu1216_config_altaddress, + &budget_av->budget.i2c_adap, + read_pwm(budget_av)); + if (fe) { + fe->ops.tuner_ops.set_params = philips_cu1216_tuner_set_params; + } + break; + + case SUBID_DVBC_EASYWATCH_MK3: + case SUBID_DVBC_CINERGY1200_MK3: + case SUBID_DVBC_KNC1_MK3: + case SUBID_DVBC_KNC1_TDA10024: + case SUBID_DVBC_KNC1_PLUS_MK3: + budget_av->reinitialise_demod = 1; + budget_av->budget.dev->i2c_bitrate = SAA7146_I2C_BUS_BIT_RATE_240; + fe = dvb_attach(tda10023_attach, + &philips_cu1216_tda10023_config, + &budget_av->budget.i2c_adap, + read_pwm(budget_av)); + if (fe) { + fe->ops.tuner_ops.set_params = philips_cu1216_tuner_set_params; + } + break; + + case SUBID_DVBT_EASYWATCH: + case SUBID_DVBT_KNC1: + case SUBID_DVBT_KNC1_PLUS: + case SUBID_DVBT_CINERGY1200: + budget_av->reinitialise_demod = 1; + fe = dvb_attach(tda10046_attach, &philips_tu1216_config, + &budget_av->budget.i2c_adap); + if (fe) { + fe->ops.tuner_ops.init = philips_tu1216_tuner_init; + fe->ops.tuner_ops.set_params = philips_tu1216_tuner_set_params; + } + break; + } + + if (fe == NULL) { + pr_err("A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n", + saa->pci->vendor, + saa->pci->device, + saa->pci->subsystem_vendor, + saa->pci->subsystem_device); + return; + } + + budget_av->budget.dvb_frontend = fe; + + if (dvb_register_frontend(&budget_av->budget.dvb_adapter, + budget_av->budget.dvb_frontend)) { + pr_err("Frontend registration failed!\n"); + dvb_frontend_detach(budget_av->budget.dvb_frontend); + budget_av->budget.dvb_frontend = NULL; + } +} + + +static void budget_av_irq(struct saa7146_dev *dev, u32 * isr) +{ + struct budget_av *budget_av = (struct budget_av *) dev->ext_priv; + + dprintk(8, "dev: %p, budget_av: %p\n", dev, budget_av); + + if (*isr & MASK_10) + ttpci_budget_irq10_handler(dev, isr); +} + +static int budget_av_detach(struct saa7146_dev *dev) +{ + struct budget_av *budget_av = (struct budget_av *) dev->ext_priv; + int err; + + dprintk(2, "dev: %p\n", dev); + + if (1 == budget_av->has_saa7113) { + saa7146_setgpio(dev, 0, SAA7146_GPIO_OUTLO); + + msleep(200); + + saa7146_unregister_device(&budget_av->vd, dev); + + saa7146_vv_release(dev); + } + + if (budget_av->budget.ci_present) + ciintf_deinit(budget_av); + + if (budget_av->budget.dvb_frontend != NULL) { + dvb_unregister_frontend(budget_av->budget.dvb_frontend); + dvb_frontend_detach(budget_av->budget.dvb_frontend); + } + err = ttpci_budget_deinit(&budget_av->budget); + + kfree(budget_av); + + return err; +} + +#define KNC1_INPUTS 2 +static struct v4l2_input knc1_inputs[KNC1_INPUTS] = { + { 0, "Composite", V4L2_INPUT_TYPE_TUNER, 1, 0, + V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, 0, V4L2_IN_CAP_STD }, + { 1, "S-Video", V4L2_INPUT_TYPE_CAMERA, 2, 0, + V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, 0, V4L2_IN_CAP_STD }, +}; + +static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i) +{ + dprintk(1, "VIDIOC_ENUMINPUT %d\n", i->index); + if (i->index >= KNC1_INPUTS) + return -EINVAL; + memcpy(i, &knc1_inputs[i->index], sizeof(struct v4l2_input)); + return 0; +} + +static int vidioc_g_input(struct file *file, void *fh, unsigned int *i) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct budget_av *budget_av = (struct budget_av *)dev->ext_priv; + + *i = budget_av->cur_input; + + dprintk(1, "VIDIOC_G_INPUT %d\n", *i); + return 0; +} + +static int vidioc_s_input(struct file *file, void *fh, unsigned int input) +{ + struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev; + struct budget_av *budget_av = (struct budget_av *)dev->ext_priv; + + dprintk(1, "VIDIOC_S_INPUT %d\n", input); + return saa7113_setinput(budget_av, input); +} + +static struct saa7146_ext_vv vv_data; + +static int budget_av_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info) +{ + struct budget_av *budget_av; + u8 *mac; + int err; + + dprintk(2, "dev: %p\n", dev); + + if (!(budget_av = kzalloc(sizeof(struct budget_av), GFP_KERNEL))) + return -ENOMEM; + + budget_av->has_saa7113 = 0; + budget_av->budget.ci_present = 0; + + dev->ext_priv = budget_av; + + err = ttpci_budget_init(&budget_av->budget, dev, info, THIS_MODULE, + adapter_nr); + if (err) { + kfree(budget_av); + return err; + } + + /* knc1 initialization */ + saa7146_write(dev, DD1_STREAM_B, 0x04000000); + saa7146_write(dev, DD1_INIT, 0x07000600); + saa7146_write(dev, MC2, MASK_09 | MASK_25 | MASK_10 | MASK_26); + + if (saa7113_init(budget_av) == 0) { + budget_av->has_saa7113 = 1; + err = saa7146_vv_init(dev, &vv_data); + if (err != 0) { + /* fixme: proper cleanup here */ + ERR("cannot init vv subsystem\n"); + return err; + } + vv_data.vid_ops.vidioc_enum_input = vidioc_enum_input; + vv_data.vid_ops.vidioc_g_input = vidioc_g_input; + vv_data.vid_ops.vidioc_s_input = vidioc_s_input; + + if ((err = saa7146_register_device(&budget_av->vd, dev, "knc1", VFL_TYPE_VIDEO))) { + /* fixme: proper cleanup here */ + ERR("cannot register capture v4l2 device\n"); + saa7146_vv_release(dev); + return err; + } + + /* beware: this modifies dev->vv ... */ + saa7146_set_hps_source_and_sync(dev, SAA7146_HPS_SOURCE_PORT_A, + SAA7146_HPS_SYNC_PORT_A); + + saa7113_setinput(budget_av, 0); + } + + /* fixme: find some sane values here... */ + saa7146_write(dev, PCI_BT_V1, 0x1c00101f); + + mac = budget_av->budget.dvb_adapter.proposed_mac; + if (i2c_readregs(&budget_av->budget.i2c_adap, 0xa0, 0x30, mac, 6)) { + pr_err("KNC1-%d: Could not read MAC from KNC1 card\n", + budget_av->budget.dvb_adapter.num); + eth_zero_addr(mac); + } else { + pr_info("KNC1-%d: MAC addr = %pM\n", + budget_av->budget.dvb_adapter.num, mac); + } + + budget_av->budget.dvb_adapter.priv = budget_av; + frontend_init(budget_av); + ciintf_init(budget_av); + + ttpci_budget_init_hooks(&budget_av->budget); + + return 0; +} + +static struct saa7146_standard standard[] = { + {.name = "PAL",.id = V4L2_STD_PAL, + .v_offset = 0x17,.v_field = 288, + .h_offset = 0x14,.h_pixels = 680, + .v_max_out = 576,.h_max_out = 768 }, + + {.name = "NTSC",.id = V4L2_STD_NTSC, + .v_offset = 0x16,.v_field = 240, + .h_offset = 0x06,.h_pixels = 708, + .v_max_out = 480,.h_max_out = 640, }, +}; + +static struct saa7146_ext_vv vv_data = { + .inputs = 2, + .capabilities = 0, // perhaps later: V4L2_CAP_VBI_CAPTURE, but that need tweaking with the saa7113 + .flags = 0, + .stds = &standard[0], + .num_stds = ARRAY_SIZE(standard), +}; + +static struct saa7146_extension budget_extension; + +MAKE_BUDGET_INFO(knc1s, "KNC1 DVB-S", BUDGET_KNC1S); +MAKE_BUDGET_INFO(knc1s2,"KNC1 DVB-S2", BUDGET_KNC1S2); +MAKE_BUDGET_INFO(sates2,"Satelco EasyWatch DVB-S2", BUDGET_KNC1S2); +MAKE_BUDGET_INFO(knc1c, "KNC1 DVB-C", BUDGET_KNC1C); +MAKE_BUDGET_INFO(knc1t, "KNC1 DVB-T", BUDGET_KNC1T); +MAKE_BUDGET_INFO(kncxs, "KNC TV STAR DVB-S", BUDGET_TVSTAR); +MAKE_BUDGET_INFO(satewpls, "Satelco EasyWatch DVB-S light", BUDGET_TVSTAR); +MAKE_BUDGET_INFO(satewpls1, "Satelco EasyWatch DVB-S light", BUDGET_KNC1S); +MAKE_BUDGET_INFO(satewps, "Satelco EasyWatch DVB-S", BUDGET_KNC1S); +MAKE_BUDGET_INFO(satewplc, "Satelco EasyWatch DVB-C", BUDGET_KNC1CP); +MAKE_BUDGET_INFO(satewcmk3, "Satelco EasyWatch DVB-C MK3", BUDGET_KNC1C_MK3); +MAKE_BUDGET_INFO(satewt, "Satelco EasyWatch DVB-T", BUDGET_KNC1T); +MAKE_BUDGET_INFO(knc1sp, "KNC1 DVB-S Plus", BUDGET_KNC1SP); +MAKE_BUDGET_INFO(knc1spx4, "KNC1 DVB-S Plus X4", BUDGET_KNC1SP); +MAKE_BUDGET_INFO(knc1cp, "KNC1 DVB-C Plus", BUDGET_KNC1CP); +MAKE_BUDGET_INFO(knc1cmk3, "KNC1 DVB-C MK3", BUDGET_KNC1C_MK3); +MAKE_BUDGET_INFO(knc1ctda10024, "KNC1 DVB-C TDA10024", BUDGET_KNC1C_TDA10024); +MAKE_BUDGET_INFO(knc1cpmk3, "KNC1 DVB-C Plus MK3", BUDGET_KNC1CP_MK3); +MAKE_BUDGET_INFO(knc1tp, "KNC1 DVB-T Plus", BUDGET_KNC1TP); +MAKE_BUDGET_INFO(cin1200s, "TerraTec Cinergy 1200 DVB-S", BUDGET_CIN1200S); +MAKE_BUDGET_INFO(cin1200sn, "TerraTec Cinergy 1200 DVB-S", BUDGET_CIN1200S); +MAKE_BUDGET_INFO(cin1200c, "Terratec Cinergy 1200 DVB-C", BUDGET_CIN1200C); +MAKE_BUDGET_INFO(cin1200cmk3, "Terratec Cinergy 1200 DVB-C MK3", BUDGET_CIN1200C_MK3); +MAKE_BUDGET_INFO(cin1200t, "Terratec Cinergy 1200 DVB-T", BUDGET_CIN1200T); + +static const struct pci_device_id pci_tbl[] = { + MAKE_EXTENSION_PCI(knc1s, 0x1131, 0x4f56), + MAKE_EXTENSION_PCI(knc1s, 0x1131, 0x0010), + MAKE_EXTENSION_PCI(knc1s, 0x1894, 0x0010), + MAKE_EXTENSION_PCI(knc1sp, 0x1131, 0x0011), + MAKE_EXTENSION_PCI(knc1sp, 0x1894, 0x0011), + MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0014), + MAKE_EXTENSION_PCI(knc1spx4, 0x1894, 0x0015), + MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0016), + MAKE_EXTENSION_PCI(knc1s2, 0x1894, 0x0018), + MAKE_EXTENSION_PCI(knc1s2, 0x1894, 0x0019), + MAKE_EXTENSION_PCI(sates2, 0x1894, 0x001d), + MAKE_EXTENSION_PCI(satewpls, 0x1894, 0x001e), + MAKE_EXTENSION_PCI(satewpls1, 0x1894, 0x001a), + MAKE_EXTENSION_PCI(satewps, 0x1894, 0x001b), + MAKE_EXTENSION_PCI(satewplc, 0x1894, 0x002a), + MAKE_EXTENSION_PCI(satewcmk3, 0x1894, 0x002c), + MAKE_EXTENSION_PCI(satewt, 0x1894, 0x003a), + MAKE_EXTENSION_PCI(knc1c, 0x1894, 0x0020), + MAKE_EXTENSION_PCI(knc1cp, 0x1894, 0x0021), + MAKE_EXTENSION_PCI(knc1cmk3, 0x1894, 0x0022), + MAKE_EXTENSION_PCI(knc1ctda10024, 0x1894, 0x0028), + MAKE_EXTENSION_PCI(knc1cpmk3, 0x1894, 0x0023), + MAKE_EXTENSION_PCI(knc1t, 0x1894, 0x0030), + MAKE_EXTENSION_PCI(knc1tp, 0x1894, 0x0031), + MAKE_EXTENSION_PCI(cin1200s, 0x153b, 0x1154), + MAKE_EXTENSION_PCI(cin1200sn, 0x153b, 0x1155), + MAKE_EXTENSION_PCI(cin1200c, 0x153b, 0x1156), + MAKE_EXTENSION_PCI(cin1200cmk3, 0x153b, 0x1176), + MAKE_EXTENSION_PCI(cin1200t, 0x153b, 0x1157), + { + .vendor = 0, + } +}; + +MODULE_DEVICE_TABLE(pci, pci_tbl); + +static struct saa7146_extension budget_extension = { + .name = "budget_av", + .flags = SAA7146_USE_I2C_IRQ, + + .pci_tbl = pci_tbl, + + .module = THIS_MODULE, + .attach = budget_av_attach, + .detach = budget_av_detach, + + .irq_mask = MASK_10, + .irq_func = budget_av_irq, +}; + +static int __init budget_av_init(void) +{ + return saa7146_register_extension(&budget_extension); +} + +static void __exit budget_av_exit(void) +{ + saa7146_unregister_extension(&budget_extension); +} + +module_init(budget_av_init); +module_exit(budget_av_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ralph Metzler, Marcus Metzler, Michael Hunold, others"); +MODULE_DESCRIPTION("driver for the SAA7146 based so-called budget PCI DVB w/ analog input and CI-module (e.g. the KNC cards)"); diff --git a/drivers/staging/media/deprecated/saa7146/ttpci/budget-ci.c b/drivers/staging/media/deprecated/saa7146/ttpci/budget-ci.c new file mode 100644 index 000000000..d59d18647 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/ttpci/budget-ci.c @@ -0,0 +1,1574 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * budget-ci.c: driver for the SAA7146 based Budget DVB cards + * + * Compiled from various sources by Michael Hunold + * + * msp430 IR support contributed by Jack Thomasson + * partially based on the Siemens DVB driver by Ralph+Marcus Metzler + * + * CI interface support (c) 2004 Andrew de Quincey + * + * the project's page is at https://linuxtv.org + */ + +#include +#include +#include +#include +#include +#include + +#include "budget.h" + +#include +#include "stv0299.h" +#include "stv0297.h" +#include "tda1004x.h" +#include "stb0899_drv.h" +#include "stb0899_reg.h" +#include "stb0899_cfg.h" +#include "stb6100.h" +#include "stb6100_cfg.h" +#include "lnbp21.h" +#include "bsbe1.h" +#include "bsru6.h" +#include "tda1002x.h" +#include "tda827x.h" +#include "bsbe1-d01a.h" + +#define MODULE_NAME "budget_ci" + +/* + * Regarding DEBIADDR_IR: + * Some CI modules hang if random addresses are read. + * Using address 0x4000 for the IR read means that we + * use the same address as for CI version, which should + * be a safe default. + */ +#define DEBIADDR_IR 0x4000 +#define DEBIADDR_CICONTROL 0x0000 +#define DEBIADDR_CIVERSION 0x4000 +#define DEBIADDR_IO 0x1000 +#define DEBIADDR_ATTR 0x3000 + +#define CICONTROL_RESET 0x01 +#define CICONTROL_ENABLETS 0x02 +#define CICONTROL_CAMDETECT 0x08 + +#define DEBICICTL 0x00420000 +#define DEBICICAM 0x02420000 + +#define SLOTSTATUS_NONE 1 +#define SLOTSTATUS_PRESENT 2 +#define SLOTSTATUS_RESET 4 +#define SLOTSTATUS_READY 8 +#define SLOTSTATUS_OCCUPIED (SLOTSTATUS_PRESENT|SLOTSTATUS_RESET|SLOTSTATUS_READY) + +/* RC5 device wildcard */ +#define IR_DEVICE_ANY 255 + +static int rc5_device = -1; +module_param(rc5_device, int, 0644); +MODULE_PARM_DESC(rc5_device, "only IR commands to given RC5 device (device = 0 - 31, any device = 255, default: autodetect)"); + +static int ir_debug; +module_param(ir_debug, int, 0644); +MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding"); + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +struct budget_ci_ir { + struct rc_dev *dev; + struct tasklet_struct msp430_irq_tasklet; + char name[72]; /* 40 + 32 for (struct saa7146_dev).name */ + char phys[32]; + int rc5_device; + u32 ir_key; + bool have_command; + bool full_rc5; /* Outputs a full RC5 code */ +}; + +struct budget_ci { + struct budget budget; + struct tasklet_struct ciintf_irq_tasklet; + int slot_status; + int ci_irq; + struct dvb_ca_en50221 ca; + struct budget_ci_ir ir; + u8 tuner_pll_address; /* used for philips_tdm1316l configs */ +}; + +static void msp430_ir_interrupt(struct tasklet_struct *t) +{ + struct budget_ci_ir *ir = from_tasklet(ir, t, msp430_irq_tasklet); + struct budget_ci *budget_ci = container_of(ir, typeof(*budget_ci), ir); + struct rc_dev *dev = budget_ci->ir.dev; + u32 command = ttpci_budget_debiread(&budget_ci->budget, DEBINOSWAP, DEBIADDR_IR, 2, 1, 0) >> 8; + + /* + * The msp430 chip can generate two different bytes, command and device + * + * type1: X1CCCCCC, C = command bits (0 - 63) + * type2: X0TDDDDD, D = device bits (0 - 31), T = RC5 toggle bit + * + * Each signal from the remote control can generate one or more command + * bytes and one or more device bytes. For the repeated bytes, the + * highest bit (X) is set. The first command byte is always generated + * before the first device byte. Other than that, no specific order + * seems to apply. To make life interesting, bytes can also be lost. + * + * Only when we have a command and device byte, a keypress is + * generated. + */ + + if (ir_debug) + printk("budget_ci: received byte 0x%02x\n", command); + + /* Remove repeat bit, we use every command */ + command = command & 0x7f; + + /* Is this a RC5 command byte? */ + if (command & 0x40) { + budget_ci->ir.have_command = true; + budget_ci->ir.ir_key = command & 0x3f; + return; + } + + /* It's a RC5 device byte */ + if (!budget_ci->ir.have_command) + return; + budget_ci->ir.have_command = false; + + if (budget_ci->ir.rc5_device != IR_DEVICE_ANY && + budget_ci->ir.rc5_device != (command & 0x1f)) + return; + + if (budget_ci->ir.full_rc5) { + rc_keydown(dev, RC_PROTO_RC5, + RC_SCANCODE_RC5(budget_ci->ir.rc5_device, budget_ci->ir.ir_key), + !!(command & 0x20)); + return; + } + + /* FIXME: We should generate complete scancodes for all devices */ + rc_keydown(dev, RC_PROTO_UNKNOWN, budget_ci->ir.ir_key, + !!(command & 0x20)); +} + +static int msp430_ir_init(struct budget_ci *budget_ci) +{ + struct saa7146_dev *saa = budget_ci->budget.dev; + struct rc_dev *dev; + int error; + + dev = rc_allocate_device(RC_DRIVER_SCANCODE); + if (!dev) { + printk(KERN_ERR "budget_ci: IR interface initialisation failed\n"); + return -ENOMEM; + } + + snprintf(budget_ci->ir.name, sizeof(budget_ci->ir.name), + "Budget-CI dvb ir receiver %s", saa->name); + snprintf(budget_ci->ir.phys, sizeof(budget_ci->ir.phys), + "pci-%s/ir0", pci_name(saa->pci)); + + dev->driver_name = MODULE_NAME; + dev->device_name = budget_ci->ir.name; + dev->input_phys = budget_ci->ir.phys; + dev->input_id.bustype = BUS_PCI; + dev->input_id.version = 1; + if (saa->pci->subsystem_vendor) { + dev->input_id.vendor = saa->pci->subsystem_vendor; + dev->input_id.product = saa->pci->subsystem_device; + } else { + dev->input_id.vendor = saa->pci->vendor; + dev->input_id.product = saa->pci->device; + } + dev->dev.parent = &saa->pci->dev; + + if (rc5_device < 0) + budget_ci->ir.rc5_device = IR_DEVICE_ANY; + else + budget_ci->ir.rc5_device = rc5_device; + + /* Select keymap and address */ + switch (budget_ci->budget.dev->pci->subsystem_device) { + case 0x100c: + case 0x100f: + case 0x1011: + case 0x1012: + /* The hauppauge keymap is a superset of these remotes */ + dev->map_name = RC_MAP_HAUPPAUGE; + budget_ci->ir.full_rc5 = true; + + if (rc5_device < 0) + budget_ci->ir.rc5_device = 0x1f; + break; + case 0x1010: + case 0x1017: + case 0x1019: + case 0x101a: + case 0x101b: + /* for the Technotrend 1500 bundled remote */ + dev->map_name = RC_MAP_TT_1500; + break; + default: + /* unknown remote */ + dev->map_name = RC_MAP_BUDGET_CI_OLD; + break; + } + if (!budget_ci->ir.full_rc5) + dev->scancode_mask = 0xff; + + error = rc_register_device(dev); + if (error) { + printk(KERN_ERR "budget_ci: could not init driver for IR device (code %d)\n", error); + rc_free_device(dev); + return error; + } + + budget_ci->ir.dev = dev; + + tasklet_setup(&budget_ci->ir.msp430_irq_tasklet, msp430_ir_interrupt); + + SAA7146_IER_ENABLE(saa, MASK_06); + saa7146_setgpio(saa, 3, SAA7146_GPIO_IRQHI); + + return 0; +} + +static void msp430_ir_deinit(struct budget_ci *budget_ci) +{ + struct saa7146_dev *saa = budget_ci->budget.dev; + + SAA7146_IER_DISABLE(saa, MASK_06); + saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT); + tasklet_kill(&budget_ci->ir.msp430_irq_tasklet); + + rc_unregister_device(budget_ci->ir.dev); +} + +static int ciintf_read_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address) +{ + struct budget_ci *budget_ci = (struct budget_ci *) ca->data; + + if (slot != 0) + return -EINVAL; + + return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM, + DEBIADDR_ATTR | (address & 0xfff), 1, 1, 0); +} + +static int ciintf_write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address, u8 value) +{ + struct budget_ci *budget_ci = (struct budget_ci *) ca->data; + + if (slot != 0) + return -EINVAL; + + return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM, + DEBIADDR_ATTR | (address & 0xfff), 1, value, 1, 0); +} + +static int ciintf_read_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address) +{ + struct budget_ci *budget_ci = (struct budget_ci *) ca->data; + + if (slot != 0) + return -EINVAL; + + return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM, + DEBIADDR_IO | (address & 3), 1, 1, 0); +} + +static int ciintf_write_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address, u8 value) +{ + struct budget_ci *budget_ci = (struct budget_ci *) ca->data; + + if (slot != 0) + return -EINVAL; + + return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM, + DEBIADDR_IO | (address & 3), 1, value, 1, 0); +} + +static int ciintf_slot_reset(struct dvb_ca_en50221 *ca, int slot) +{ + struct budget_ci *budget_ci = (struct budget_ci *) ca->data; + struct saa7146_dev *saa = budget_ci->budget.dev; + + if (slot != 0) + return -EINVAL; + + if (budget_ci->ci_irq) { + // trigger on RISING edge during reset so we know when READY is re-asserted + saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI); + } + budget_ci->slot_status = SLOTSTATUS_RESET; + ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0); + msleep(1); + ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, + CICONTROL_RESET, 1, 0); + + saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI); + ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB); + return 0; +} + +static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot) +{ + struct budget_ci *budget_ci = (struct budget_ci *) ca->data; + struct saa7146_dev *saa = budget_ci->budget.dev; + + if (slot != 0) + return -EINVAL; + + saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI); + ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB); + return 0; +} + +static int ciintf_slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) +{ + struct budget_ci *budget_ci = (struct budget_ci *) ca->data; + struct saa7146_dev *saa = budget_ci->budget.dev; + int tmp; + + if (slot != 0) + return -EINVAL; + + saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTLO); + + tmp = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0); + ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, + tmp | CICONTROL_ENABLETS, 1, 0); + + ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTA); + return 0; +} + +static void ciintf_interrupt(struct tasklet_struct *t) +{ + struct budget_ci *budget_ci = from_tasklet(budget_ci, t, + ciintf_irq_tasklet); + struct saa7146_dev *saa = budget_ci->budget.dev; + unsigned int flags; + + // ensure we don't get spurious IRQs during initialisation + if (!budget_ci->budget.ci_present) + return; + + // read the CAM status + flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0); + if (flags & CICONTROL_CAMDETECT) { + + // GPIO should be set to trigger on falling edge if a CAM is present + saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO); + + if (budget_ci->slot_status & SLOTSTATUS_NONE) { + // CAM insertion IRQ + budget_ci->slot_status = SLOTSTATUS_PRESENT; + dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, + DVB_CA_EN50221_CAMCHANGE_INSERTED); + + } else if (budget_ci->slot_status & SLOTSTATUS_RESET) { + // CAM ready (reset completed) + budget_ci->slot_status = SLOTSTATUS_READY; + dvb_ca_en50221_camready_irq(&budget_ci->ca, 0); + + } else if (budget_ci->slot_status & SLOTSTATUS_READY) { + // FR/DA IRQ + dvb_ca_en50221_frda_irq(&budget_ci->ca, 0); + } + } else { + + // trigger on rising edge if a CAM is not present - when a CAM is inserted, we + // only want to get the IRQ when it sets READY. If we trigger on the falling edge, + // the CAM might not actually be ready yet. + saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI); + + // generate a CAM removal IRQ if we haven't already + if (budget_ci->slot_status & SLOTSTATUS_OCCUPIED) { + // CAM removal IRQ + budget_ci->slot_status = SLOTSTATUS_NONE; + dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, + DVB_CA_EN50221_CAMCHANGE_REMOVED); + } + } +} + +static int ciintf_poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) +{ + struct budget_ci *budget_ci = (struct budget_ci *) ca->data; + unsigned int flags; + + // ensure we don't get spurious IRQs during initialisation + if (!budget_ci->budget.ci_present) + return -EINVAL; + + // read the CAM status + flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0); + if (flags & CICONTROL_CAMDETECT) { + // mark it as present if it wasn't before + if (budget_ci->slot_status & SLOTSTATUS_NONE) { + budget_ci->slot_status = SLOTSTATUS_PRESENT; + } + + // during a RESET, we check if we can read from IO memory to see when CAM is ready + if (budget_ci->slot_status & SLOTSTATUS_RESET) { + if (ciintf_read_attribute_mem(ca, slot, 0) == 0x1d) { + budget_ci->slot_status = SLOTSTATUS_READY; + } + } + } else { + budget_ci->slot_status = SLOTSTATUS_NONE; + } + + if (budget_ci->slot_status != SLOTSTATUS_NONE) { + if (budget_ci->slot_status & SLOTSTATUS_READY) { + return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY; + } + return DVB_CA_EN50221_POLL_CAM_PRESENT; + } + + return 0; +} + +static int ciintf_init(struct budget_ci *budget_ci) +{ + struct saa7146_dev *saa = budget_ci->budget.dev; + int flags; + int result; + int ci_version; + int ca_flags; + + memset(&budget_ci->ca, 0, sizeof(struct dvb_ca_en50221)); + + // enable DEBI pins + saa7146_write(saa, MC1, MASK_27 | MASK_11); + + // test if it is there + ci_version = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CIVERSION, 1, 1, 0); + if ((ci_version & 0xa0) != 0xa0) { + result = -ENODEV; + goto error; + } + + // determine whether a CAM is present or not + flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0); + budget_ci->slot_status = SLOTSTATUS_NONE; + if (flags & CICONTROL_CAMDETECT) + budget_ci->slot_status = SLOTSTATUS_PRESENT; + + // version 0xa2 of the CI firmware doesn't generate interrupts + if (ci_version == 0xa2) { + ca_flags = 0; + budget_ci->ci_irq = 0; + } else { + ca_flags = DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE | + DVB_CA_EN50221_FLAG_IRQ_FR | + DVB_CA_EN50221_FLAG_IRQ_DA; + budget_ci->ci_irq = 1; + } + + // register CI interface + budget_ci->ca.owner = THIS_MODULE; + budget_ci->ca.read_attribute_mem = ciintf_read_attribute_mem; + budget_ci->ca.write_attribute_mem = ciintf_write_attribute_mem; + budget_ci->ca.read_cam_control = ciintf_read_cam_control; + budget_ci->ca.write_cam_control = ciintf_write_cam_control; + budget_ci->ca.slot_reset = ciintf_slot_reset; + budget_ci->ca.slot_shutdown = ciintf_slot_shutdown; + budget_ci->ca.slot_ts_enable = ciintf_slot_ts_enable; + budget_ci->ca.poll_slot_status = ciintf_poll_slot_status; + budget_ci->ca.data = budget_ci; + if ((result = dvb_ca_en50221_init(&budget_ci->budget.dvb_adapter, + &budget_ci->ca, + ca_flags, 1)) != 0) { + printk("budget_ci: CI interface detected, but initialisation failed.\n"); + goto error; + } + + // Setup CI slot IRQ + if (budget_ci->ci_irq) { + tasklet_setup(&budget_ci->ciintf_irq_tasklet, ciintf_interrupt); + if (budget_ci->slot_status != SLOTSTATUS_NONE) { + saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO); + } else { + saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI); + } + SAA7146_IER_ENABLE(saa, MASK_03); + } + + // enable interface + ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, + CICONTROL_RESET, 1, 0); + + // success! + printk("budget_ci: CI interface initialised\n"); + budget_ci->budget.ci_present = 1; + + // forge a fake CI IRQ so the CAM state is setup correctly + if (budget_ci->ci_irq) { + flags = DVB_CA_EN50221_CAMCHANGE_REMOVED; + if (budget_ci->slot_status != SLOTSTATUS_NONE) + flags = DVB_CA_EN50221_CAMCHANGE_INSERTED; + dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, flags); + } + + return 0; + +error: + saa7146_write(saa, MC1, MASK_27); + return result; +} + +static void ciintf_deinit(struct budget_ci *budget_ci) +{ + struct saa7146_dev *saa = budget_ci->budget.dev; + + // disable CI interrupts + if (budget_ci->ci_irq) { + SAA7146_IER_DISABLE(saa, MASK_03); + saa7146_setgpio(saa, 0, SAA7146_GPIO_INPUT); + tasklet_kill(&budget_ci->ciintf_irq_tasklet); + } + + // reset interface + ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0); + msleep(1); + ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, + CICONTROL_RESET, 1, 0); + + // disable TS data stream to CI interface + saa7146_setgpio(saa, 1, SAA7146_GPIO_INPUT); + + // release the CA device + dvb_ca_en50221_release(&budget_ci->ca); + + // disable DEBI pins + saa7146_write(saa, MC1, MASK_27); +} + +static void budget_ci_irq(struct saa7146_dev *dev, u32 * isr) +{ + struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv; + + dprintk(8, "dev: %p, budget_ci: %p\n", dev, budget_ci); + + if (*isr & MASK_06) + tasklet_schedule(&budget_ci->ir.msp430_irq_tasklet); + + if (*isr & MASK_10) + ttpci_budget_irq10_handler(dev, isr); + + if ((*isr & MASK_03) && (budget_ci->budget.ci_present) && (budget_ci->ci_irq)) + tasklet_schedule(&budget_ci->ciintf_irq_tasklet); +} + +static u8 philips_su1278_tt_inittab[] = { + 0x01, 0x0f, + 0x02, 0x30, + 0x03, 0x00, + 0x04, 0x5b, + 0x05, 0x85, + 0x06, 0x02, + 0x07, 0x00, + 0x08, 0x02, + 0x09, 0x00, + 0x0C, 0x01, + 0x0D, 0x81, + 0x0E, 0x44, + 0x0f, 0x14, + 0x10, 0x3c, + 0x11, 0x84, + 0x12, 0xda, + 0x13, 0x97, + 0x14, 0x95, + 0x15, 0xc9, + 0x16, 0x19, + 0x17, 0x8c, + 0x18, 0x59, + 0x19, 0xf8, + 0x1a, 0xfe, + 0x1c, 0x7f, + 0x1d, 0x00, + 0x1e, 0x00, + 0x1f, 0x50, + 0x20, 0x00, + 0x21, 0x00, + 0x22, 0x00, + 0x23, 0x00, + 0x28, 0x00, + 0x29, 0x28, + 0x2a, 0x14, + 0x2b, 0x0f, + 0x2c, 0x09, + 0x2d, 0x09, + 0x31, 0x1f, + 0x32, 0x19, + 0x33, 0xfc, + 0x34, 0x93, + 0xff, 0xff +}; + +static int philips_su1278_tt_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio) +{ + stv0299_writereg(fe, 0x0e, 0x44); + if (srate >= 10000000) { + stv0299_writereg(fe, 0x13, 0x97); + stv0299_writereg(fe, 0x14, 0x95); + stv0299_writereg(fe, 0x15, 0xc9); + stv0299_writereg(fe, 0x17, 0x8c); + stv0299_writereg(fe, 0x1a, 0xfe); + stv0299_writereg(fe, 0x1c, 0x7f); + stv0299_writereg(fe, 0x2d, 0x09); + } else { + stv0299_writereg(fe, 0x13, 0x99); + stv0299_writereg(fe, 0x14, 0x8d); + stv0299_writereg(fe, 0x15, 0xce); + stv0299_writereg(fe, 0x17, 0x43); + stv0299_writereg(fe, 0x1a, 0x1d); + stv0299_writereg(fe, 0x1c, 0x12); + stv0299_writereg(fe, 0x2d, 0x05); + } + stv0299_writereg(fe, 0x0e, 0x23); + stv0299_writereg(fe, 0x0f, 0x94); + stv0299_writereg(fe, 0x10, 0x39); + stv0299_writereg(fe, 0x15, 0xc9); + + stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff); + stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff); + stv0299_writereg(fe, 0x21, (ratio) & 0xf0); + + return 0; +} + +static int philips_su1278_tt_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; + u32 div; + u8 buf[4]; + struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) }; + + if ((p->frequency < 950000) || (p->frequency > 2150000)) + return -EINVAL; + + div = (p->frequency + (500 - 1)) / 500; /* round correctly */ + buf[0] = (div >> 8) & 0x7f; + buf[1] = div & 0xff; + buf[2] = 0x80 | ((div & 0x18000) >> 10) | 2; + buf[3] = 0x20; + + if (p->symbol_rate < 4000000) + buf[3] |= 1; + + if (p->frequency < 1250000) + buf[3] |= 0; + else if (p->frequency < 1550000) + buf[3] |= 0x40; + else if (p->frequency < 2050000) + buf[3] |= 0x80; + else if (p->frequency < 2150000) + buf[3] |= 0xC0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget_ci->budget.i2c_adap, &msg, 1) != 1) + return -EIO; + return 0; +} + +static const struct stv0299_config philips_su1278_tt_config = { + + .demod_address = 0x68, + .inittab = philips_su1278_tt_inittab, + .mclk = 64000000UL, + .invert = 0, + .skip_reinit = 1, + .lock_output = STV0299_LOCKOUTPUT_1, + .volt13_op0_op1 = STV0299_VOLT13_OP1, + .min_delay_ms = 50, + .set_symbol_rate = philips_su1278_tt_set_symbol_rate, +}; + + + +static int philips_tdm1316l_tuner_init(struct dvb_frontend *fe) +{ + struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; + static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab }; + static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 }; + struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = td1316_init,.len = + sizeof(td1316_init) }; + + // setup PLL configuration + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) + return -EIO; + msleep(1); + + // disable the mc44BC374c (do not check for errors) + tuner_msg.addr = 0x65; + tuner_msg.buf = disable_mc44BC374c; + tuner_msg.len = sizeof(disable_mc44BC374c); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1); + } + + return 0; +} + +static int philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; + u8 tuner_buf[4]; + struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = tuner_buf,.len = sizeof(tuner_buf) }; + int tuner_frequency = 0; + u8 band, cp, filter; + + // determine charge pump + tuner_frequency = p->frequency + 36130000; + if (tuner_frequency < 87000000) + return -EINVAL; + else if (tuner_frequency < 130000000) + cp = 3; + else if (tuner_frequency < 160000000) + cp = 5; + else if (tuner_frequency < 200000000) + cp = 6; + else if (tuner_frequency < 290000000) + cp = 3; + else if (tuner_frequency < 420000000) + cp = 5; + else if (tuner_frequency < 480000000) + cp = 6; + else if (tuner_frequency < 620000000) + cp = 3; + else if (tuner_frequency < 830000000) + cp = 5; + else if (tuner_frequency < 895000000) + cp = 7; + else + return -EINVAL; + + // determine band + if (p->frequency < 49000000) + return -EINVAL; + else if (p->frequency < 159000000) + band = 1; + else if (p->frequency < 444000000) + band = 2; + else if (p->frequency < 861000000) + band = 4; + else + return -EINVAL; + + // setup PLL filter and TDA9889 + switch (p->bandwidth_hz) { + case 6000000: + tda1004x_writereg(fe, 0x0C, 0x14); + filter = 0; + break; + + case 7000000: + tda1004x_writereg(fe, 0x0C, 0x80); + filter = 0; + break; + + case 8000000: + tda1004x_writereg(fe, 0x0C, 0x14); + filter = 1; + break; + + default: + return -EINVAL; + } + + // calculate divisor + // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6) + tuner_frequency = (((p->frequency / 1000) * 6) + 217280) / 1000; + + // setup tuner buffer + tuner_buf[0] = tuner_frequency >> 8; + tuner_buf[1] = tuner_frequency & 0xff; + tuner_buf[2] = 0xca; + tuner_buf[3] = (cp << 5) | (filter << 3) | band; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) + return -EIO; + + msleep(1); + return 0; +} + +static int philips_tdm1316l_request_firmware(struct dvb_frontend *fe, + const struct firmware **fw, char *name) +{ + struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; + + return request_firmware(fw, name, &budget_ci->budget.dev->pci->dev); +} + +static struct tda1004x_config philips_tdm1316l_config = { + + .demod_address = 0x8, + .invert = 0, + .invert_oclk = 0, + .xtal_freq = TDA10046_XTAL_4M, + .agc_config = TDA10046_AGC_DEFAULT, + .if_freq = TDA10046_FREQ_3617, + .request_firmware = philips_tdm1316l_request_firmware, +}; + +static struct tda1004x_config philips_tdm1316l_config_invert = { + + .demod_address = 0x8, + .invert = 1, + .invert_oclk = 0, + .xtal_freq = TDA10046_XTAL_4M, + .agc_config = TDA10046_AGC_DEFAULT, + .if_freq = TDA10046_FREQ_3617, + .request_firmware = philips_tdm1316l_request_firmware, +}; + +static int dvbc_philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; + u8 tuner_buf[5]; + struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address, + .flags = 0, + .buf = tuner_buf, + .len = sizeof(tuner_buf) }; + int tuner_frequency = 0; + u8 band, cp, filter; + + // determine charge pump + tuner_frequency = p->frequency + 36125000; + if (tuner_frequency < 87000000) + return -EINVAL; + else if (tuner_frequency < 130000000) { + cp = 3; + band = 1; + } else if (tuner_frequency < 160000000) { + cp = 5; + band = 1; + } else if (tuner_frequency < 200000000) { + cp = 6; + band = 1; + } else if (tuner_frequency < 290000000) { + cp = 3; + band = 2; + } else if (tuner_frequency < 420000000) { + cp = 5; + band = 2; + } else if (tuner_frequency < 480000000) { + cp = 6; + band = 2; + } else if (tuner_frequency < 620000000) { + cp = 3; + band = 4; + } else if (tuner_frequency < 830000000) { + cp = 5; + band = 4; + } else if (tuner_frequency < 895000000) { + cp = 7; + band = 4; + } else + return -EINVAL; + + // assume PLL filter should always be 8MHz for the moment. + filter = 1; + + // calculate divisor + tuner_frequency = (p->frequency + 36125000 + (62500/2)) / 62500; + + // setup tuner buffer + tuner_buf[0] = tuner_frequency >> 8; + tuner_buf[1] = tuner_frequency & 0xff; + tuner_buf[2] = 0xc8; + tuner_buf[3] = (cp << 5) | (filter << 3) | band; + tuner_buf[4] = 0x80; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) + return -EIO; + + msleep(50); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) + return -EIO; + + msleep(1); + + return 0; +} + +static u8 dvbc_philips_tdm1316l_inittab[] = { + 0x80, 0x01, + 0x80, 0x00, + 0x81, 0x01, + 0x81, 0x00, + 0x00, 0x09, + 0x01, 0x69, + 0x03, 0x00, + 0x04, 0x00, + 0x07, 0x00, + 0x08, 0x00, + 0x20, 0x00, + 0x21, 0x40, + 0x22, 0x00, + 0x23, 0x00, + 0x24, 0x40, + 0x25, 0x88, + 0x30, 0xff, + 0x31, 0x00, + 0x32, 0xff, + 0x33, 0x00, + 0x34, 0x50, + 0x35, 0x7f, + 0x36, 0x00, + 0x37, 0x20, + 0x38, 0x00, + 0x40, 0x1c, + 0x41, 0xff, + 0x42, 0x29, + 0x43, 0x20, + 0x44, 0xff, + 0x45, 0x00, + 0x46, 0x00, + 0x49, 0x04, + 0x4a, 0x00, + 0x4b, 0x7b, + 0x52, 0x30, + 0x55, 0xae, + 0x56, 0x47, + 0x57, 0xe1, + 0x58, 0x3a, + 0x5a, 0x1e, + 0x5b, 0x34, + 0x60, 0x00, + 0x63, 0x00, + 0x64, 0x00, + 0x65, 0x00, + 0x66, 0x00, + 0x67, 0x00, + 0x68, 0x00, + 0x69, 0x00, + 0x6a, 0x02, + 0x6b, 0x00, + 0x70, 0xff, + 0x71, 0x00, + 0x72, 0x00, + 0x73, 0x00, + 0x74, 0x0c, + 0x80, 0x00, + 0x81, 0x00, + 0x82, 0x00, + 0x83, 0x00, + 0x84, 0x04, + 0x85, 0x80, + 0x86, 0x24, + 0x87, 0x78, + 0x88, 0x10, + 0x89, 0x00, + 0x90, 0x01, + 0x91, 0x01, + 0xa0, 0x04, + 0xa1, 0x00, + 0xa2, 0x00, + 0xb0, 0x91, + 0xb1, 0x0b, + 0xc0, 0x53, + 0xc1, 0x70, + 0xc2, 0x12, + 0xd0, 0x00, + 0xd1, 0x00, + 0xd2, 0x00, + 0xd3, 0x00, + 0xd4, 0x00, + 0xd5, 0x00, + 0xde, 0x00, + 0xdf, 0x00, + 0x61, 0x38, + 0x62, 0x0a, + 0x53, 0x13, + 0x59, 0x08, + 0xff, 0xff, +}; + +static struct stv0297_config dvbc_philips_tdm1316l_config = { + .demod_address = 0x1c, + .inittab = dvbc_philips_tdm1316l_inittab, + .invert = 0, + .stop_during_read = 1, +}; + +static struct tda10023_config tda10023_config = { + .demod_address = 0xc, + .invert = 0, + .xtal = 16000000, + .pll_m = 11, + .pll_p = 3, + .pll_n = 1, + .deltaf = 0xa511, +}; + +static struct tda827x_config tda827x_config = { + .config = 0, +}; + +/* TT S2-3200 DVB-S (STB0899) Inittab */ +static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = { + + { STB0899_DEV_ID , 0x81 }, + { STB0899_DISCNTRL1 , 0x32 }, + { STB0899_DISCNTRL2 , 0x80 }, + { STB0899_DISRX_ST0 , 0x04 }, + { STB0899_DISRX_ST1 , 0x00 }, + { STB0899_DISPARITY , 0x00 }, + { STB0899_DISSTATUS , 0x20 }, + { STB0899_DISF22 , 0x8c }, + { STB0899_DISF22RX , 0x9a }, + { STB0899_SYSREG , 0x0b }, + { STB0899_ACRPRESC , 0x11 }, + { STB0899_ACRDIV1 , 0x0a }, + { STB0899_ACRDIV2 , 0x05 }, + { STB0899_DACR1 , 0x00 }, + { STB0899_DACR2 , 0x00 }, + { STB0899_OUTCFG , 0x00 }, + { STB0899_MODECFG , 0x00 }, + { STB0899_IRQSTATUS_3 , 0x30 }, + { STB0899_IRQSTATUS_2 , 0x00 }, + { STB0899_IRQSTATUS_1 , 0x00 }, + { STB0899_IRQSTATUS_0 , 0x00 }, + { STB0899_IRQMSK_3 , 0xf3 }, + { STB0899_IRQMSK_2 , 0xfc }, + { STB0899_IRQMSK_1 , 0xff }, + { STB0899_IRQMSK_0 , 0xff }, + { STB0899_IRQCFG , 0x00 }, + { STB0899_I2CCFG , 0x88 }, + { STB0899_I2CRPT , 0x48 }, /* 12k Pullup, Repeater=16, Stop=disabled */ + { STB0899_IOPVALUE5 , 0x00 }, + { STB0899_IOPVALUE4 , 0x20 }, + { STB0899_IOPVALUE3 , 0xc9 }, + { STB0899_IOPVALUE2 , 0x90 }, + { STB0899_IOPVALUE1 , 0x40 }, + { STB0899_IOPVALUE0 , 0x00 }, + { STB0899_GPIO00CFG , 0x82 }, + { STB0899_GPIO01CFG , 0x82 }, + { STB0899_GPIO02CFG , 0x82 }, + { STB0899_GPIO03CFG , 0x82 }, + { STB0899_GPIO04CFG , 0x82 }, + { STB0899_GPIO05CFG , 0x82 }, + { STB0899_GPIO06CFG , 0x82 }, + { STB0899_GPIO07CFG , 0x82 }, + { STB0899_GPIO08CFG , 0x82 }, + { STB0899_GPIO09CFG , 0x82 }, + { STB0899_GPIO10CFG , 0x82 }, + { STB0899_GPIO11CFG , 0x82 }, + { STB0899_GPIO12CFG , 0x82 }, + { STB0899_GPIO13CFG , 0x82 }, + { STB0899_GPIO14CFG , 0x82 }, + { STB0899_GPIO15CFG , 0x82 }, + { STB0899_GPIO16CFG , 0x82 }, + { STB0899_GPIO17CFG , 0x82 }, + { STB0899_GPIO18CFG , 0x82 }, + { STB0899_GPIO19CFG , 0x82 }, + { STB0899_GPIO20CFG , 0x82 }, + { STB0899_SDATCFG , 0xb8 }, + { STB0899_SCLTCFG , 0xba }, + { STB0899_AGCRFCFG , 0x1c }, /* 0x11 */ + { STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */ + { STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */ + { STB0899_DIRCLKCFG , 0x82 }, + { STB0899_CLKOUT27CFG , 0x7e }, + { STB0899_STDBYCFG , 0x82 }, + { STB0899_CS0CFG , 0x82 }, + { STB0899_CS1CFG , 0x82 }, + { STB0899_DISEQCOCFG , 0x20 }, + { STB0899_GPIO32CFG , 0x82 }, + { STB0899_GPIO33CFG , 0x82 }, + { STB0899_GPIO34CFG , 0x82 }, + { STB0899_GPIO35CFG , 0x82 }, + { STB0899_GPIO36CFG , 0x82 }, + { STB0899_GPIO37CFG , 0x82 }, + { STB0899_GPIO38CFG , 0x82 }, + { STB0899_GPIO39CFG , 0x82 }, + { STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */ + { STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */ + { STB0899_FILTCTRL , 0x00 }, + { STB0899_SYSCTRL , 0x00 }, + { STB0899_STOPCLK1 , 0x20 }, + { STB0899_STOPCLK2 , 0x00 }, + { STB0899_INTBUFSTATUS , 0x00 }, + { STB0899_INTBUFCTRL , 0x0a }, + { 0xffff , 0xff }, +}; + +static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = { + { STB0899_DEMOD , 0x00 }, + { STB0899_RCOMPC , 0xc9 }, + { STB0899_AGC1CN , 0x41 }, + { STB0899_AGC1REF , 0x10 }, + { STB0899_RTC , 0x7a }, + { STB0899_TMGCFG , 0x4e }, + { STB0899_AGC2REF , 0x34 }, + { STB0899_TLSR , 0x84 }, + { STB0899_CFD , 0xc7 }, + { STB0899_ACLC , 0x87 }, + { STB0899_BCLC , 0x94 }, + { STB0899_EQON , 0x41 }, + { STB0899_LDT , 0xdd }, + { STB0899_LDT2 , 0xc9 }, + { STB0899_EQUALREF , 0xb4 }, + { STB0899_TMGRAMP , 0x10 }, + { STB0899_TMGTHD , 0x30 }, + { STB0899_IDCCOMP , 0xfb }, + { STB0899_QDCCOMP , 0x03 }, + { STB0899_POWERI , 0x3b }, + { STB0899_POWERQ , 0x3d }, + { STB0899_RCOMP , 0x81 }, + { STB0899_AGCIQIN , 0x80 }, + { STB0899_AGC2I1 , 0x04 }, + { STB0899_AGC2I2 , 0xf5 }, + { STB0899_TLIR , 0x25 }, + { STB0899_RTF , 0x80 }, + { STB0899_DSTATUS , 0x00 }, + { STB0899_LDI , 0xca }, + { STB0899_CFRM , 0xf1 }, + { STB0899_CFRL , 0xf3 }, + { STB0899_NIRM , 0x2a }, + { STB0899_NIRL , 0x05 }, + { STB0899_ISYMB , 0x17 }, + { STB0899_QSYMB , 0xfa }, + { STB0899_SFRH , 0x2f }, + { STB0899_SFRM , 0x68 }, + { STB0899_SFRL , 0x40 }, + { STB0899_SFRUPH , 0x2f }, + { STB0899_SFRUPM , 0x68 }, + { STB0899_SFRUPL , 0x40 }, + { STB0899_EQUAI1 , 0xfd }, + { STB0899_EQUAQ1 , 0x04 }, + { STB0899_EQUAI2 , 0x0f }, + { STB0899_EQUAQ2 , 0xff }, + { STB0899_EQUAI3 , 0xdf }, + { STB0899_EQUAQ3 , 0xfa }, + { STB0899_EQUAI4 , 0x37 }, + { STB0899_EQUAQ4 , 0x0d }, + { STB0899_EQUAI5 , 0xbd }, + { STB0899_EQUAQ5 , 0xf7 }, + { STB0899_DSTATUS2 , 0x00 }, + { STB0899_VSTATUS , 0x00 }, + { STB0899_VERROR , 0xff }, + { STB0899_IQSWAP , 0x2a }, + { STB0899_ECNT1M , 0x00 }, + { STB0899_ECNT1L , 0x00 }, + { STB0899_ECNT2M , 0x00 }, + { STB0899_ECNT2L , 0x00 }, + { STB0899_ECNT3M , 0x00 }, + { STB0899_ECNT3L , 0x00 }, + { STB0899_FECAUTO1 , 0x06 }, + { STB0899_FECM , 0x01 }, + { STB0899_VTH12 , 0xf0 }, + { STB0899_VTH23 , 0xa0 }, + { STB0899_VTH34 , 0x78 }, + { STB0899_VTH56 , 0x4e }, + { STB0899_VTH67 , 0x48 }, + { STB0899_VTH78 , 0x38 }, + { STB0899_PRVIT , 0xff }, + { STB0899_VITSYNC , 0x19 }, + { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */ + { STB0899_TSULC , 0x42 }, + { STB0899_RSLLC , 0x40 }, + { STB0899_TSLPL , 0x12 }, + { STB0899_TSCFGH , 0x0c }, + { STB0899_TSCFGM , 0x00 }, + { STB0899_TSCFGL , 0x0c }, + { STB0899_TSOUT , 0x4d }, /* 0x0d for CAM */ + { STB0899_RSSYNCDEL , 0x00 }, + { STB0899_TSINHDELH , 0x02 }, + { STB0899_TSINHDELM , 0x00 }, + { STB0899_TSINHDELL , 0x00 }, + { STB0899_TSLLSTKM , 0x00 }, + { STB0899_TSLLSTKL , 0x00 }, + { STB0899_TSULSTKM , 0x00 }, + { STB0899_TSULSTKL , 0xab }, + { STB0899_PCKLENUL , 0x00 }, + { STB0899_PCKLENLL , 0xcc }, + { STB0899_RSPCKLEN , 0xcc }, + { STB0899_TSSTATUS , 0x80 }, + { STB0899_ERRCTRL1 , 0xb6 }, + { STB0899_ERRCTRL2 , 0x96 }, + { STB0899_ERRCTRL3 , 0x89 }, + { STB0899_DMONMSK1 , 0x27 }, + { STB0899_DMONMSK0 , 0x03 }, + { STB0899_DEMAPVIT , 0x5c }, + { STB0899_PLPARM , 0x1f }, + { STB0899_PDELCTRL , 0x48 }, + { STB0899_PDELCTRL2 , 0x00 }, + { STB0899_BBHCTRL1 , 0x00 }, + { STB0899_BBHCTRL2 , 0x00 }, + { STB0899_HYSTTHRESH , 0x77 }, + { STB0899_MATCSTM , 0x00 }, + { STB0899_MATCSTL , 0x00 }, + { STB0899_UPLCSTM , 0x00 }, + { STB0899_UPLCSTL , 0x00 }, + { STB0899_DFLCSTM , 0x00 }, + { STB0899_DFLCSTL , 0x00 }, + { STB0899_SYNCCST , 0x00 }, + { STB0899_SYNCDCSTM , 0x00 }, + { STB0899_SYNCDCSTL , 0x00 }, + { STB0899_ISI_ENTRY , 0x00 }, + { STB0899_ISI_BIT_EN , 0x00 }, + { STB0899_MATSTRM , 0x00 }, + { STB0899_MATSTRL , 0x00 }, + { STB0899_UPLSTRM , 0x00 }, + { STB0899_UPLSTRL , 0x00 }, + { STB0899_DFLSTRM , 0x00 }, + { STB0899_DFLSTRL , 0x00 }, + { STB0899_SYNCSTR , 0x00 }, + { STB0899_SYNCDSTRM , 0x00 }, + { STB0899_SYNCDSTRL , 0x00 }, + { STB0899_CFGPDELSTATUS1 , 0x10 }, + { STB0899_CFGPDELSTATUS2 , 0x00 }, + { STB0899_BBFERRORM , 0x00 }, + { STB0899_BBFERRORL , 0x00 }, + { STB0899_UPKTERRORM , 0x00 }, + { STB0899_UPKTERRORL , 0x00 }, + { 0xffff , 0xff }, +}; + +static struct stb0899_config tt3200_config = { + .init_dev = tt3200_stb0899_s1_init_1, + .init_s2_demod = stb0899_s2_init_2, + .init_s1_demod = tt3200_stb0899_s1_init_3, + .init_s2_fec = stb0899_s2_init_4, + .init_tst = stb0899_s1_init_5, + + .postproc = NULL, + + .demod_address = 0x68, + + .xtal_freq = 27000000, + .inversion = IQ_SWAP_ON, + + .lo_clk = 76500000, + .hi_clk = 99000000, + + .esno_ave = STB0899_DVBS2_ESNO_AVE, + .esno_quant = STB0899_DVBS2_ESNO_QUANT, + .avframes_coarse = STB0899_DVBS2_AVFRAMES_COARSE, + .avframes_fine = STB0899_DVBS2_AVFRAMES_FINE, + .miss_threshold = STB0899_DVBS2_MISS_THRESHOLD, + .uwp_threshold_acq = STB0899_DVBS2_UWP_THRESHOLD_ACQ, + .uwp_threshold_track = STB0899_DVBS2_UWP_THRESHOLD_TRACK, + .uwp_threshold_sof = STB0899_DVBS2_UWP_THRESHOLD_SOF, + .sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT, + + .btr_nco_bits = STB0899_DVBS2_BTR_NCO_BITS, + .btr_gain_shift_offset = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET, + .crl_nco_bits = STB0899_DVBS2_CRL_NCO_BITS, + .ldpc_max_iter = STB0899_DVBS2_LDPC_MAX_ITER, + + .tuner_get_frequency = stb6100_get_frequency, + .tuner_set_frequency = stb6100_set_frequency, + .tuner_set_bandwidth = stb6100_set_bandwidth, + .tuner_get_bandwidth = stb6100_get_bandwidth, + .tuner_set_rfsiggain = NULL +}; + +static struct stb6100_config tt3200_stb6100_config = { + .tuner_address = 0x60, + .refclock = 27000000, +}; + +static void frontend_init(struct budget_ci *budget_ci) +{ + switch (budget_ci->budget.dev->pci->subsystem_device) { + case 0x100c: // Hauppauge/TT Nova-CI budget (stv0299/ALPS BSRU6(tsa5059)) + budget_ci->budget.dvb_frontend = + dvb_attach(stv0299_attach, &alps_bsru6_config, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params; + budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap; + break; + } + break; + + case 0x100f: // Hauppauge/TT Nova-CI budget (stv0299b/Philips su1278(tsa5059)) + budget_ci->budget.dvb_frontend = + dvb_attach(stv0299_attach, &philips_su1278_tt_config, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_su1278_tt_tuner_set_params; + break; + } + break; + + case 0x1010: // TT DVB-C CI budget (stv0297/Philips tdm1316l(tda6651tt)) + budget_ci->tuner_pll_address = 0x61; + budget_ci->budget.dvb_frontend = + dvb_attach(stv0297_attach, &dvbc_philips_tdm1316l_config, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = dvbc_philips_tdm1316l_tuner_set_params; + break; + } + break; + + case 0x1011: // Hauppauge/TT Nova-T budget (tda10045/Philips tdm1316l(tda6651tt) + TDA9889) + budget_ci->tuner_pll_address = 0x63; + budget_ci->budget.dvb_frontend = + dvb_attach(tda10045_attach, &philips_tdm1316l_config, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init; + budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params; + break; + } + break; + + case 0x1012: // TT DVB-T CI budget (tda10046/Philips tdm1316l(tda6651tt)) + budget_ci->tuner_pll_address = 0x60; + budget_ci->budget.dvb_frontend = + dvb_attach(tda10046_attach, &philips_tdm1316l_config_invert, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init; + budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params; + break; + } + break; + + case 0x1017: // TT S-1500 PCI + budget_ci->budget.dvb_frontend = dvb_attach(stv0299_attach, &alps_bsbe1_config, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsbe1_tuner_set_params; + budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap; + + budget_ci->budget.dvb_frontend->ops.dishnetwork_send_legacy_command = NULL; + if (dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, LNBP21_LLC, 0) == NULL) { + printk("%s: No LNBP21 found!\n", __func__); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } + break; + + case 0x101a: /* TT Budget-C-1501 (philips tda10023/philips tda8274A) */ + budget_ci->budget.dvb_frontend = dvb_attach(tda10023_attach, &tda10023_config, &budget_ci->budget.i2c_adap, 0x48); + if (budget_ci->budget.dvb_frontend) { + if (dvb_attach(tda827x_attach, budget_ci->budget.dvb_frontend, 0x61, &budget_ci->budget.i2c_adap, &tda827x_config) == NULL) { + printk(KERN_ERR "%s: No tda827x found!\n", __func__); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } + break; + + case 0x101b: /* TT S-1500B (BSBE1-D01A - STV0288/STB6000/LNBP21) */ + budget_ci->budget.dvb_frontend = dvb_attach(stv0288_attach, &stv0288_bsbe1_d01a_config, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + if (dvb_attach(stb6000_attach, budget_ci->budget.dvb_frontend, 0x63, &budget_ci->budget.i2c_adap)) { + if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) { + printk(KERN_ERR "%s: No LNBP21 found!\n", __func__); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } else { + printk(KERN_ERR "%s: No STB6000 found!\n", __func__); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } + break; + + case 0x1019: // TT S2-3200 PCI + /* + * NOTE! on some STB0899 versions, the internal PLL takes a longer time + * to settle, aka LOCK. On the older revisions of the chip, we don't see + * this, as a result on the newer chips the entire clock tree, will not + * be stable after a freshly POWER 'ed up situation. + * In this case, we should RESET the STB0899 (Active LOW) and wait for + * PLL stabilization. + * + * On the TT S2 3200 and clones, the STB0899 demodulator's RESETB is + * connected to the SAA7146 GPIO, GPIO2, Pin 142 + */ + /* Reset Demodulator */ + saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO); + /* Wait for everything to die */ + msleep(50); + /* Pull it up out of Reset state */ + saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI); + /* Wait for PLL to stabilize */ + msleep(250); + /* + * PLL state should be stable now. Ideally, we should check + * for PLL LOCK status. But well, never mind! + */ + budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) { + if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) { + printk("%s: No LNBP21 found!\n", __func__); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } else { + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } + break; + + } + + if (budget_ci->budget.dvb_frontend == NULL) { + printk("budget-ci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n", + budget_ci->budget.dev->pci->vendor, + budget_ci->budget.dev->pci->device, + budget_ci->budget.dev->pci->subsystem_vendor, + budget_ci->budget.dev->pci->subsystem_device); + } else { + if (dvb_register_frontend + (&budget_ci->budget.dvb_adapter, budget_ci->budget.dvb_frontend)) { + printk("budget-ci: Frontend registration failed!\n"); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } +} + +static int budget_ci_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info) +{ + struct budget_ci *budget_ci; + int err; + + budget_ci = kzalloc(sizeof(struct budget_ci), GFP_KERNEL); + if (!budget_ci) { + err = -ENOMEM; + goto out1; + } + + dprintk(2, "budget_ci: %p\n", budget_ci); + + dev->ext_priv = budget_ci; + + err = ttpci_budget_init(&budget_ci->budget, dev, info, THIS_MODULE, + adapter_nr); + if (err) + goto out2; + + err = msp430_ir_init(budget_ci); + if (err) + goto out3; + + ciintf_init(budget_ci); + + budget_ci->budget.dvb_adapter.priv = budget_ci; + frontend_init(budget_ci); + + ttpci_budget_init_hooks(&budget_ci->budget); + + return 0; + +out3: + ttpci_budget_deinit(&budget_ci->budget); +out2: + kfree(budget_ci); +out1: + return err; +} + +static int budget_ci_detach(struct saa7146_dev *dev) +{ + struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv; + struct saa7146_dev *saa = budget_ci->budget.dev; + int err; + + if (budget_ci->budget.ci_present) + ciintf_deinit(budget_ci); + msp430_ir_deinit(budget_ci); + if (budget_ci->budget.dvb_frontend) { + dvb_unregister_frontend(budget_ci->budget.dvb_frontend); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + } + err = ttpci_budget_deinit(&budget_ci->budget); + + // disable frontend and CI interface + saa7146_setgpio(saa, 2, SAA7146_GPIO_INPUT); + + kfree(budget_ci); + + return err; +} + +static struct saa7146_extension budget_extension; + +MAKE_BUDGET_INFO(ttbs2, "TT-Budget/S-1500 PCI", BUDGET_TT); +MAKE_BUDGET_INFO(ttbci, "TT-Budget/WinTV-NOVA-CI PCI", BUDGET_TT_HW_DISEQC); +MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T PCI", BUDGET_TT); +MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT); +MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT); +MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT); +MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT); +MAKE_BUDGET_INFO(ttbs1500b, "TT-Budget S-1500B PCI", BUDGET_TT); + +static const struct pci_device_id pci_tbl[] = { + MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c), + MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100f), + MAKE_EXTENSION_PCI(ttbcci, 0x13c2, 0x1010), + MAKE_EXTENSION_PCI(ttbt2, 0x13c2, 0x1011), + MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012), + MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017), + MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a), + MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019), + MAKE_EXTENSION_PCI(ttbs1500b, 0x13c2, 0x101b), + { + .vendor = 0, + } +}; + +MODULE_DEVICE_TABLE(pci, pci_tbl); + +static struct saa7146_extension budget_extension = { + .name = "budget_ci dvb", + .flags = SAA7146_USE_I2C_IRQ, + + .module = THIS_MODULE, + .pci_tbl = &pci_tbl[0], + .attach = budget_ci_attach, + .detach = budget_ci_detach, + + .irq_mask = MASK_03 | MASK_06 | MASK_10, + .irq_func = budget_ci_irq, +}; + +static int __init budget_ci_init(void) +{ + return saa7146_register_extension(&budget_extension); +} + +static void __exit budget_ci_exit(void) +{ + saa7146_unregister_extension(&budget_extension); +} + +module_init(budget_ci_init); +module_exit(budget_ci_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Michael Hunold, Jack Thomasson, Andrew de Quincey, others"); +MODULE_DESCRIPTION("driver for the SAA7146 based so-called budget PCI DVB cards w/ CI-module produced by Siemens, Technotrend, Hauppauge"); diff --git a/drivers/staging/media/deprecated/saa7146/ttpci/budget-core.c b/drivers/staging/media/deprecated/saa7146/ttpci/budget-core.c new file mode 100644 index 000000000..5d5796f24 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/ttpci/budget-core.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * budget-core.c: driver for the SAA7146 based Budget DVB cards + * + * Compiled from various sources by Michael Hunold + * + * Copyright (C) 2002 Ralph Metzler + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * 26feb2004 Support for FS Activy Card (Grundig tuner) by + * Michael Dreher , + * Oliver Endriss , + * Andreas 'randy' Weinberger + * + * the project's page is at https://linuxtv.org + */ + + +#include "budget.h" +#include "ttpci-eeprom.h" + +#define TS_WIDTH (2 * TS_SIZE) +#define TS_WIDTH_ACTIVY TS_SIZE +#define TS_WIDTH_DVBC TS_SIZE +#define TS_HEIGHT_MASK 0xf00 +#define TS_HEIGHT_MASK_ACTIVY 0xc00 +#define TS_HEIGHT_MASK_DVBC 0xe00 +#define TS_MIN_BUFSIZE_K 188 +#define TS_MAX_BUFSIZE_K 1410 +#define TS_MAX_BUFSIZE_K_ACTIVY 564 +#define TS_MAX_BUFSIZE_K_DVBC 1316 +#define BUFFER_WARNING_WAIT (30*HZ) + +int budget_debug; +static int dma_buffer_size = TS_MIN_BUFSIZE_K; +module_param_named(debug, budget_debug, int, 0644); +module_param_named(bufsize, dma_buffer_size, int, 0444); +MODULE_PARM_DESC(debug, "Turn on/off budget debugging (default:off)."); +MODULE_PARM_DESC(bufsize, "DMA buffer size in KB, default: 188, min: 188, max: 1410 (Activy: 564)"); + +/**************************************************************************** + * TT budget / WinTV Nova + ****************************************************************************/ + +static int stop_ts_capture(struct budget *budget) +{ + dprintk(2, "budget: %p\n", budget); + + saa7146_write(budget->dev, MC1, MASK_20); // DMA3 off + SAA7146_IER_DISABLE(budget->dev, MASK_10); + return 0; +} + +static int start_ts_capture(struct budget *budget) +{ + struct saa7146_dev *dev = budget->dev; + + dprintk(2, "budget: %p\n", budget); + + if (!budget->feeding || !budget->fe_synced) + return 0; + + saa7146_write(dev, MC1, MASK_20); // DMA3 off + + memset(budget->grabbing, 0x00, budget->buffer_size); + + saa7146_write(dev, PCI_BT_V1, 0x001c0000 | (saa7146_read(dev, PCI_BT_V1) & ~0x001f0000)); + + budget->ttbp = 0; + + /* + * Signal path on the Activy: + * + * tuner -> SAA7146 port A -> SAA7146 BRS -> SAA7146 DMA3 -> memory + * + * Since the tuner feeds 204 bytes packets into the SAA7146, + * DMA3 is configured to strip the trailing 16 FEC bytes: + * Pitch: 188, NumBytes3: 188, NumLines3: 1024 + */ + + switch(budget->card->type) { + case BUDGET_FS_ACTIVY: + saa7146_write(dev, DD1_INIT, 0x04000000); + saa7146_write(dev, MC2, (MASK_09 | MASK_25)); + saa7146_write(dev, BRS_CTRL, 0x00000000); + break; + case BUDGET_PATCH: + saa7146_write(dev, DD1_INIT, 0x00000200); + saa7146_write(dev, MC2, (MASK_10 | MASK_26)); + saa7146_write(dev, BRS_CTRL, 0x60000000); + break; + case BUDGET_CIN1200C_MK3: + case BUDGET_KNC1C_MK3: + case BUDGET_KNC1C_TDA10024: + case BUDGET_KNC1CP_MK3: + if (budget->video_port == BUDGET_VIDEO_PORTA) { + saa7146_write(dev, DD1_INIT, 0x06000200); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + saa7146_write(dev, BRS_CTRL, 0x00000000); + } else { + saa7146_write(dev, DD1_INIT, 0x00000600); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + saa7146_write(dev, BRS_CTRL, 0x60000000); + } + break; + default: + if (budget->video_port == BUDGET_VIDEO_PORTA) { + saa7146_write(dev, DD1_INIT, 0x06000200); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + saa7146_write(dev, BRS_CTRL, 0x00000000); + } else { + saa7146_write(dev, DD1_INIT, 0x02000600); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + saa7146_write(dev, BRS_CTRL, 0x60000000); + } + } + + saa7146_write(dev, MC2, (MASK_08 | MASK_24)); + mdelay(10); + + saa7146_write(dev, BASE_ODD3, 0); + if (budget->buffer_size > budget->buffer_height * budget->buffer_width) { + // using odd/even buffers + saa7146_write(dev, BASE_EVEN3, budget->buffer_height * budget->buffer_width); + } else { + // using a single buffer + saa7146_write(dev, BASE_EVEN3, 0); + } + saa7146_write(dev, PROT_ADDR3, budget->buffer_size); + saa7146_write(dev, BASE_PAGE3, budget->pt.dma | ME1 | 0x90); + + saa7146_write(dev, PITCH3, budget->buffer_width); + saa7146_write(dev, NUM_LINE_BYTE3, + (budget->buffer_height << 16) | budget->buffer_width); + + saa7146_write(dev, MC2, (MASK_04 | MASK_20)); + + SAA7146_ISR_CLEAR(budget->dev, MASK_10); /* VPE */ + SAA7146_IER_ENABLE(budget->dev, MASK_10); /* VPE */ + saa7146_write(dev, MC1, (MASK_04 | MASK_20)); /* DMA3 on */ + + return 0; +} + +static int budget_read_fe_status(struct dvb_frontend *fe, + enum fe_status *status) +{ + struct budget *budget = (struct budget *) fe->dvb->priv; + int synced; + int ret; + + if (budget->read_fe_status) + ret = budget->read_fe_status(fe, status); + else + ret = -EINVAL; + + if (!ret) { + synced = (*status & FE_HAS_LOCK); + if (synced != budget->fe_synced) { + budget->fe_synced = synced; + spin_lock(&budget->feedlock); + if (synced) + start_ts_capture(budget); + else + stop_ts_capture(budget); + spin_unlock(&budget->feedlock); + } + } + return ret; +} + +static void vpeirq(struct tasklet_struct *t) +{ + struct budget *budget = from_tasklet(budget, t, vpe_tasklet); + u8 *mem = (u8 *) (budget->grabbing); + u32 olddma = budget->ttbp; + u32 newdma = saa7146_read(budget->dev, PCI_VDP3); + u32 count; + + /* Ensure streamed PCI data is synced to CPU */ + dma_sync_sg_for_cpu(&budget->dev->pci->dev, budget->pt.slist, + budget->pt.nents, DMA_FROM_DEVICE); + + /* nearest lower position divisible by 188 */ + newdma -= newdma % 188; + + if (newdma >= budget->buffer_size) + return; + + budget->ttbp = newdma; + + if (budget->feeding == 0 || newdma == olddma) + return; + + if (newdma > olddma) { /* no wraparound, dump olddma..newdma */ + count = newdma - olddma; + dvb_dmx_swfilter_packets(&budget->demux, mem + olddma, count / 188); + } else { /* wraparound, dump olddma..buflen and 0..newdma */ + count = budget->buffer_size - olddma; + dvb_dmx_swfilter_packets(&budget->demux, mem + olddma, count / 188); + count += newdma; + dvb_dmx_swfilter_packets(&budget->demux, mem, newdma / 188); + } + + if (count > budget->buffer_warning_threshold) + budget->buffer_warnings++; + + if (budget->buffer_warnings && time_after(jiffies, budget->buffer_warning_time)) { + printk("%s %s: used %d times >80%% of buffer (%u bytes now)\n", + budget->dev->name, __func__, budget->buffer_warnings, count); + budget->buffer_warning_time = jiffies + BUFFER_WARNING_WAIT; + budget->buffer_warnings = 0; + } +} + + +static int ttpci_budget_debiread_nolock(struct budget *budget, u32 config, + int addr, int count, int nobusyloop) +{ + struct saa7146_dev *saa = budget->dev; + int result; + + result = saa7146_wait_for_debi_done(saa, nobusyloop); + if (result < 0) + return result; + + saa7146_write(saa, DEBI_COMMAND, (count << 17) | 0x10000 | (addr & 0xffff)); + saa7146_write(saa, DEBI_CONFIG, config); + saa7146_write(saa, DEBI_PAGE, 0); + saa7146_write(saa, MC2, (2 << 16) | 2); + + result = saa7146_wait_for_debi_done(saa, nobusyloop); + if (result < 0) + return result; + + result = saa7146_read(saa, DEBI_AD); + result &= (0xffffffffUL >> ((4 - count) * 8)); + return result; +} + +int ttpci_budget_debiread(struct budget *budget, u32 config, int addr, int count, + int uselocks, int nobusyloop) +{ + if (count > 4 || count <= 0) + return 0; + + if (uselocks) { + unsigned long flags; + int result; + + spin_lock_irqsave(&budget->debilock, flags); + result = ttpci_budget_debiread_nolock(budget, config, addr, + count, nobusyloop); + spin_unlock_irqrestore(&budget->debilock, flags); + return result; + } + return ttpci_budget_debiread_nolock(budget, config, addr, + count, nobusyloop); +} + +static int ttpci_budget_debiwrite_nolock(struct budget *budget, u32 config, + int addr, int count, u32 value, int nobusyloop) +{ + struct saa7146_dev *saa = budget->dev; + int result; + + result = saa7146_wait_for_debi_done(saa, nobusyloop); + if (result < 0) + return result; + + saa7146_write(saa, DEBI_COMMAND, (count << 17) | 0x00000 | (addr & 0xffff)); + saa7146_write(saa, DEBI_CONFIG, config); + saa7146_write(saa, DEBI_PAGE, 0); + saa7146_write(saa, DEBI_AD, value); + saa7146_write(saa, MC2, (2 << 16) | 2); + + result = saa7146_wait_for_debi_done(saa, nobusyloop); + return result < 0 ? result : 0; +} + +int ttpci_budget_debiwrite(struct budget *budget, u32 config, int addr, + int count, u32 value, int uselocks, int nobusyloop) +{ + if (count > 4 || count <= 0) + return 0; + + if (uselocks) { + unsigned long flags; + int result; + + spin_lock_irqsave(&budget->debilock, flags); + result = ttpci_budget_debiwrite_nolock(budget, config, addr, + count, value, nobusyloop); + spin_unlock_irqrestore(&budget->debilock, flags); + return result; + } + return ttpci_budget_debiwrite_nolock(budget, config, addr, + count, value, nobusyloop); +} + + +/**************************************************************************** + * DVB API SECTION + ****************************************************************************/ + +static int budget_start_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct budget *budget = (struct budget *) demux->priv; + int status = 0; + + dprintk(2, "budget: %p\n", budget); + + if (!demux->dmx.frontend) + return -EINVAL; + + spin_lock(&budget->feedlock); + feed->pusi_seen = false; /* have a clean section start */ + if (budget->feeding++ == 0) + status = start_ts_capture(budget); + spin_unlock(&budget->feedlock); + return status; +} + +static int budget_stop_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct budget *budget = (struct budget *) demux->priv; + int status = 0; + + dprintk(2, "budget: %p\n", budget); + + spin_lock(&budget->feedlock); + if (--budget->feeding == 0) + status = stop_ts_capture(budget); + spin_unlock(&budget->feedlock); + return status; +} + +static int budget_register(struct budget *budget) +{ + struct dvb_demux *dvbdemux = &budget->demux; + int ret; + + dprintk(2, "budget: %p\n", budget); + + dvbdemux->priv = (void *) budget; + + dvbdemux->filternum = 256; + dvbdemux->feednum = 256; + dvbdemux->start_feed = budget_start_feed; + dvbdemux->stop_feed = budget_stop_feed; + dvbdemux->write_to_decoder = NULL; + + dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | DMX_SECTION_FILTERING | + DMX_MEMORY_BASED_FILTERING); + + dvb_dmx_init(&budget->demux); + + budget->dmxdev.filternum = 256; + budget->dmxdev.demux = &dvbdemux->dmx; + budget->dmxdev.capabilities = 0; + + dvb_dmxdev_init(&budget->dmxdev, &budget->dvb_adapter); + + budget->hw_frontend.source = DMX_FRONTEND_0; + + ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &budget->hw_frontend); + + if (ret < 0) + goto err_release_dmx; + + budget->mem_frontend.source = DMX_MEMORY_FE; + ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &budget->mem_frontend); + if (ret < 0) + goto err_release_dmx; + + ret = dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, &budget->hw_frontend); + if (ret < 0) + goto err_release_dmx; + + dvb_net_init(&budget->dvb_adapter, &budget->dvb_net, &dvbdemux->dmx); + + return 0; + +err_release_dmx: + dvb_dmxdev_release(&budget->dmxdev); + dvb_dmx_release(&budget->demux); + return ret; +} + +static void budget_unregister(struct budget *budget) +{ + struct dvb_demux *dvbdemux = &budget->demux; + + dprintk(2, "budget: %p\n", budget); + + dvb_net_release(&budget->dvb_net); + + dvbdemux->dmx.close(&dvbdemux->dmx); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &budget->hw_frontend); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &budget->mem_frontend); + + dvb_dmxdev_release(&budget->dmxdev); + dvb_dmx_release(&budget->demux); +} + +int ttpci_budget_init(struct budget *budget, struct saa7146_dev *dev, + struct saa7146_pci_extension_data *info, + struct module *owner, short *adapter_nums) +{ + int ret = 0; + struct budget_info *bi = info->ext_priv; + int max_bufsize; + int height_mask; + + memset(budget, 0, sizeof(struct budget)); + + dprintk(2, "dev: %p, budget: %p\n", dev, budget); + + budget->card = bi; + budget->dev = (struct saa7146_dev *) dev; + + switch(budget->card->type) { + case BUDGET_FS_ACTIVY: + budget->buffer_width = TS_WIDTH_ACTIVY; + max_bufsize = TS_MAX_BUFSIZE_K_ACTIVY; + height_mask = TS_HEIGHT_MASK_ACTIVY; + break; + + case BUDGET_KNC1C: + case BUDGET_KNC1CP: + case BUDGET_CIN1200C: + case BUDGET_KNC1C_MK3: + case BUDGET_KNC1C_TDA10024: + case BUDGET_KNC1CP_MK3: + case BUDGET_CIN1200C_MK3: + budget->buffer_width = TS_WIDTH_DVBC; + max_bufsize = TS_MAX_BUFSIZE_K_DVBC; + height_mask = TS_HEIGHT_MASK_DVBC; + break; + + default: + budget->buffer_width = TS_WIDTH; + max_bufsize = TS_MAX_BUFSIZE_K; + height_mask = TS_HEIGHT_MASK; + } + + if (dma_buffer_size < TS_MIN_BUFSIZE_K) + dma_buffer_size = TS_MIN_BUFSIZE_K; + else if (dma_buffer_size > max_bufsize) + dma_buffer_size = max_bufsize; + + budget->buffer_height = dma_buffer_size * 1024 / budget->buffer_width; + if (budget->buffer_height > 0xfff) { + budget->buffer_height /= 2; + budget->buffer_height &= height_mask; + budget->buffer_size = 2 * budget->buffer_height * budget->buffer_width; + } else { + budget->buffer_height &= height_mask; + budget->buffer_size = budget->buffer_height * budget->buffer_width; + } + budget->buffer_warning_threshold = budget->buffer_size * 80/100; + budget->buffer_warnings = 0; + budget->buffer_warning_time = jiffies; + + dprintk(2, "%s: buffer type = %s, width = %d, height = %d\n", + budget->dev->name, + budget->buffer_size > budget->buffer_width * budget->buffer_height ? "odd/even" : "single", + budget->buffer_width, budget->buffer_height); + printk("%s: dma buffer size %u\n", budget->dev->name, budget->buffer_size); + + ret = dvb_register_adapter(&budget->dvb_adapter, budget->card->name, + owner, &budget->dev->pci->dev, adapter_nums); + if (ret < 0) + return ret; + + /* set dd1 stream a & b */ + saa7146_write(dev, DD1_STREAM_B, 0x00000000); + saa7146_write(dev, MC2, (MASK_09 | MASK_25)); + saa7146_write(dev, MC2, (MASK_10 | MASK_26)); + saa7146_write(dev, DD1_INIT, 0x02000000); + saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26)); + + if (bi->type != BUDGET_FS_ACTIVY) + budget->video_port = BUDGET_VIDEO_PORTB; + else + budget->video_port = BUDGET_VIDEO_PORTA; + spin_lock_init(&budget->feedlock); + spin_lock_init(&budget->debilock); + + /* the Siemens DVB needs this if you want to have the i2c chips + get recognized before the main driver is loaded */ + if (bi->type != BUDGET_FS_ACTIVY) + saa7146_write(dev, GPIO_CTRL, 0x500000); /* GPIO 3 = 1 */ + + strscpy(budget->i2c_adap.name, budget->card->name, + sizeof(budget->i2c_adap.name)); + + saa7146_i2c_adapter_prepare(dev, &budget->i2c_adap, SAA7146_I2C_BUS_BIT_RATE_120); + strscpy(budget->i2c_adap.name, budget->card->name, + sizeof(budget->i2c_adap.name)); + + if (i2c_add_adapter(&budget->i2c_adap) < 0) { + ret = -ENOMEM; + goto err_dvb_unregister; + } + + ttpci_eeprom_parse_mac(&budget->i2c_adap, budget->dvb_adapter.proposed_mac); + + budget->grabbing = saa7146_vmalloc_build_pgtable(dev->pci, budget->buffer_size, &budget->pt); + if (NULL == budget->grabbing) { + ret = -ENOMEM; + goto err_del_i2c; + } + + saa7146_write(dev, PCI_BT_V1, 0x001c0000); + /* upload all */ + saa7146_write(dev, GPIO_CTRL, 0x000000); + + tasklet_setup(&budget->vpe_tasklet, vpeirq); + + /* frontend power on */ + if (bi->type != BUDGET_FS_ACTIVY) + saa7146_setgpio(dev, 2, SAA7146_GPIO_OUTHI); + + if ((ret = budget_register(budget)) == 0) + return 0; /* Everything OK */ + + /* An error occurred, cleanup resources */ + saa7146_vfree_destroy_pgtable(dev->pci, budget->grabbing, &budget->pt); + +err_del_i2c: + i2c_del_adapter(&budget->i2c_adap); + +err_dvb_unregister: + dvb_unregister_adapter(&budget->dvb_adapter); + + return ret; +} + +void ttpci_budget_init_hooks(struct budget *budget) +{ + if (budget->dvb_frontend && !budget->read_fe_status) { + budget->read_fe_status = budget->dvb_frontend->ops.read_status; + budget->dvb_frontend->ops.read_status = budget_read_fe_status; + } +} + +int ttpci_budget_deinit(struct budget *budget) +{ + struct saa7146_dev *dev = budget->dev; + + dprintk(2, "budget: %p\n", budget); + + budget_unregister(budget); + + tasklet_kill(&budget->vpe_tasklet); + + saa7146_vfree_destroy_pgtable(dev->pci, budget->grabbing, &budget->pt); + + i2c_del_adapter(&budget->i2c_adap); + + dvb_unregister_adapter(&budget->dvb_adapter); + + return 0; +} + +void ttpci_budget_irq10_handler(struct saa7146_dev *dev, u32 * isr) +{ + struct budget *budget = (struct budget *) dev->ext_priv; + + dprintk(8, "dev: %p, budget: %p\n", dev, budget); + + if (*isr & MASK_10) + tasklet_schedule(&budget->vpe_tasklet); +} + +void ttpci_budget_set_video_port(struct saa7146_dev *dev, int video_port) +{ + struct budget *budget = (struct budget *) dev->ext_priv; + + spin_lock(&budget->feedlock); + budget->video_port = video_port; + if (budget->feeding) { + stop_ts_capture(budget); + start_ts_capture(budget); + } + spin_unlock(&budget->feedlock); +} + +EXPORT_SYMBOL_GPL(ttpci_budget_debiread); +EXPORT_SYMBOL_GPL(ttpci_budget_debiwrite); +EXPORT_SYMBOL_GPL(ttpci_budget_init); +EXPORT_SYMBOL_GPL(ttpci_budget_init_hooks); +EXPORT_SYMBOL_GPL(ttpci_budget_deinit); +EXPORT_SYMBOL_GPL(ttpci_budget_irq10_handler); +EXPORT_SYMBOL_GPL(ttpci_budget_set_video_port); +EXPORT_SYMBOL_GPL(budget_debug); + +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/deprecated/saa7146/ttpci/budget.c b/drivers/staging/media/deprecated/saa7146/ttpci/budget.c new file mode 100644 index 000000000..a88711a3a --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/ttpci/budget.c @@ -0,0 +1,883 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * budget.c: driver for the SAA7146 based Budget DVB cards + * + * Compiled from various sources by Michael Hunold + * + * Copyright (C) 2002 Ralph Metzler + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * 26feb2004 Support for FS Activy Card (Grundig tuner) by + * Michael Dreher , + * Oliver Endriss and + * Andreas 'randy' Weinberger + * + * the project's page is at https://linuxtv.org + */ + +#include "budget.h" +#include "stv0299.h" +#include "ves1x93.h" +#include "ves1820.h" +#include "l64781.h" +#include "tda8083.h" +#include "s5h1420.h" +#include "tda10086.h" +#include "tda826x.h" +#include "lnbp21.h" +#include "bsru6.h" +#include "bsbe1.h" +#include "tdhd1.h" +#include "stv6110x.h" +#include "stv090x.h" +#include "isl6423.h" +#include "lnbh24.h" + + +static int diseqc_method; +module_param(diseqc_method, int, 0444); +MODULE_PARM_DESC(diseqc_method, "Select DiSEqC method for subsystem id 13c2:1003, 0: default, 1: more reliable (for newer revisions only)"); + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +static void Set22K (struct budget *budget, int state) +{ + struct saa7146_dev *dev=budget->dev; + dprintk(2, "budget: %p\n", budget); + saa7146_setgpio(dev, 3, (state ? SAA7146_GPIO_OUTHI : SAA7146_GPIO_OUTLO)); +} + +/* Diseqc functions only for TT Budget card */ +/* taken from the Skyvision DVB driver by + Ralph Metzler */ + +static void DiseqcSendBit (struct budget *budget, int data) +{ + struct saa7146_dev *dev=budget->dev; + dprintk(2, "budget: %p\n", budget); + + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI); + udelay(data ? 500 : 1000); + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); + udelay(data ? 1000 : 500); +} + +static void DiseqcSendByte (struct budget *budget, int data) +{ + int i, par=1, d; + + dprintk(2, "budget: %p\n", budget); + + for (i=7; i>=0; i--) { + d = (data>>i)&1; + par ^= d; + DiseqcSendBit(budget, d); + } + + DiseqcSendBit(budget, par); +} + +static int SendDiSEqCMsg (struct budget *budget, int len, u8 *msg, unsigned long burst) +{ + struct saa7146_dev *dev=budget->dev; + int i; + + dprintk(2, "budget: %p\n", budget); + + saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO); + mdelay(16); + + for (i=0; idev; + + dprintk(2, "budget: %p\n", budget); + + switch (voltage) { + case SEC_VOLTAGE_13: + saa7146_setgpio(dev, 1, SAA7146_GPIO_OUTHI); + saa7146_setgpio(dev, 2, SAA7146_GPIO_OUTLO); + break; + case SEC_VOLTAGE_18: + saa7146_setgpio(dev, 1, SAA7146_GPIO_OUTHI); + saa7146_setgpio(dev, 2, SAA7146_GPIO_OUTHI); + break; + case SEC_VOLTAGE_OFF: + saa7146_setgpio(dev, 1, SAA7146_GPIO_OUTLO); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int siemens_budget_set_voltage(struct dvb_frontend *fe, + enum fe_sec_voltage voltage) +{ + struct budget* budget = (struct budget*) fe->dvb->priv; + + return SetVoltage_Activy (budget, voltage); +} + +static int budget_set_tone(struct dvb_frontend *fe, + enum fe_sec_tone_mode tone) +{ + struct budget* budget = (struct budget*) fe->dvb->priv; + + switch (tone) { + case SEC_TONE_ON: + Set22K (budget, 1); + break; + + case SEC_TONE_OFF: + Set22K (budget, 0); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int budget_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd) +{ + struct budget* budget = (struct budget*) fe->dvb->priv; + + SendDiSEqCMsg (budget, cmd->msg_len, cmd->msg, 0); + + return 0; +} + +static int budget_diseqc_send_burst(struct dvb_frontend *fe, + enum fe_sec_mini_cmd minicmd) +{ + struct budget* budget = (struct budget*) fe->dvb->priv; + + SendDiSEqCMsg (budget, 0, NULL, minicmd); + + return 0; +} + +static int alps_bsrv2_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct budget* budget = (struct budget*) fe->dvb->priv; + u8 pwr = 0; + u8 buf[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) }; + u32 div = (c->frequency + 479500) / 125; + + if (c->frequency > 2000000) + pwr = 3; + else if (c->frequency > 1800000) + pwr = 2; + else if (c->frequency > 1600000) + pwr = 1; + else if (c->frequency > 1200000) + pwr = 0; + else if (c->frequency >= 1100000) + pwr = 1; + else pwr = 2; + + buf[0] = (div >> 8) & 0x7f; + buf[1] = div & 0xff; + buf[2] = ((div & 0x18000) >> 10) | 0x95; + buf[3] = (pwr << 6) | 0x30; + + // NOTE: since we're using a prescaler of 2, we set the + // divisor frequency to 62.5kHz and divide by 125 above + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1) return -EIO; + return 0; +} + +static struct ves1x93_config alps_bsrv2_config = +{ + .demod_address = 0x08, + .xin = 90100000UL, + .invert_pwm = 0, +}; + +static int alps_tdbe2_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct budget* budget = (struct budget*) fe->dvb->priv; + u32 div; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x62, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = (c->frequency + 35937500 + 31250) / 62500; + + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0x85 | ((div >> 10) & 0x60); + data[3] = (c->frequency < 174000000 ? 0x88 : c->frequency < 470000000 ? 0x84 : 0x81); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1) return -EIO; + return 0; +} + +static struct ves1820_config alps_tdbe2_config = { + .demod_address = 0x09, + .xin = 57840000UL, + .invert = 1, + .selagc = VES1820_SELAGC_SIGNAMPERR, +}; + +static int grundig_29504_401_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct budget *budget = fe->dvb->priv; + u8 *tuner_addr = fe->tuner_priv; + u32 div; + u8 cfg, cpump, band_select; + u8 data[4]; + struct i2c_msg msg = { .flags = 0, .buf = data, .len = sizeof(data) }; + + if (tuner_addr) + msg.addr = *tuner_addr; + else + msg.addr = 0x61; + + div = (36125000 + c->frequency) / 166666; + + cfg = 0x88; + + if (c->frequency < 175000000) + cpump = 2; + else if (c->frequency < 390000000) + cpump = 1; + else if (c->frequency < 470000000) + cpump = 2; + else if (c->frequency < 750000000) + cpump = 1; + else + cpump = 3; + + if (c->frequency < 175000000) + band_select = 0x0e; + else if (c->frequency < 470000000) + band_select = 0x05; + else + band_select = 0x03; + + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = ((div >> 10) & 0x60) | cfg; + data[3] = (cpump << 6) | band_select; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1) return -EIO; + return 0; +} + +static struct l64781_config grundig_29504_401_config = { + .demod_address = 0x55, +}; + +static struct l64781_config grundig_29504_401_config_activy = { + .demod_address = 0x54, +}; + +static u8 tuner_address_grundig_29504_401_activy = 0x60; + +static int grundig_29504_451_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct budget* budget = (struct budget*) fe->dvb->priv; + u32 div; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = c->frequency / 125; + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0x8e; + data[3] = 0x00; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1) return -EIO; + return 0; +} + +static struct tda8083_config grundig_29504_451_config = { + .demod_address = 0x68, +}; + +static int s5h1420_tuner_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct budget* budget = (struct budget*) fe->dvb->priv; + u32 div; + u8 data[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) }; + + div = c->frequency / 1000; + data[0] = (div >> 8) & 0x7f; + data[1] = div & 0xff; + data[2] = 0xc2; + + if (div < 1450) + data[3] = 0x00; + else if (div < 1850) + data[3] = 0x40; + else if (div < 2000) + data[3] = 0x80; + else + data[3] = 0xc0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1) return -EIO; + + return 0; +} + +static struct s5h1420_config s5h1420_config = { + .demod_address = 0x53, + .invert = 1, + .cdclk_polarity = 1, +}; + +static struct tda10086_config tda10086_config = { + .demod_address = 0x0e, + .invert = 0, + .diseqc_tone = 1, + .xtal_freq = TDA10086_XTAL_16M, +}; + +static const struct stv0299_config alps_bsru6_config_activy = { + .demod_address = 0x68, + .inittab = alps_bsru6_inittab, + .mclk = 88000000UL, + .invert = 1, + .op0_off = 1, + .min_delay_ms = 100, + .set_symbol_rate = alps_bsru6_set_symbol_rate, +}; + +static const struct stv0299_config alps_bsbe1_config_activy = { + .demod_address = 0x68, + .inittab = alps_bsbe1_inittab, + .mclk = 88000000UL, + .invert = 1, + .op0_off = 1, + .min_delay_ms = 100, + .set_symbol_rate = alps_bsbe1_set_symbol_rate, +}; + +static int alps_tdhd1_204_request_firmware(struct dvb_frontend *fe, const struct firmware **fw, char *name) +{ + struct budget *budget = (struct budget *)fe->dvb->priv; + + return request_firmware(fw, name, &budget->dev->pci->dev); +} + + +static int i2c_readreg(struct i2c_adapter *i2c, u8 adr, u8 reg) +{ + u8 val; + struct i2c_msg msg[] = { + { .addr = adr, .flags = 0, .buf = ®, .len = 1 }, + { .addr = adr, .flags = I2C_M_RD, .buf = &val, .len = 1 } + }; + + return (i2c_transfer(i2c, msg, 2) != 2) ? -EIO : val; +} + +static u8 read_pwm(struct budget* budget) +{ + u8 b = 0xff; + u8 pwm; + struct i2c_msg msg[] = { { .addr = 0x50,.flags = 0,.buf = &b,.len = 1 }, + { .addr = 0x50,.flags = I2C_M_RD,.buf = &pwm,.len = 1} }; + + if ((i2c_transfer(&budget->i2c_adap, msg, 2) != 2) || (pwm == 0xff)) + pwm = 0x48; + + return pwm; +} + +static struct stv090x_config tt1600_stv090x_config = { + .device = STV0903, + .demod_mode = STV090x_SINGLE, + .clk_mode = STV090x_CLK_EXT, + + .xtal = 13500000, + .address = 0x68, + + .ts1_mode = STV090x_TSMODE_DVBCI, + .ts2_mode = STV090x_TSMODE_SERIAL_CONTINUOUS, + + .repeater_level = STV090x_RPTLEVEL_16, + + .tuner_init = NULL, + .tuner_sleep = NULL, + .tuner_set_mode = NULL, + .tuner_set_frequency = NULL, + .tuner_get_frequency = NULL, + .tuner_set_bandwidth = NULL, + .tuner_get_bandwidth = NULL, + .tuner_set_bbgain = NULL, + .tuner_get_bbgain = NULL, + .tuner_set_refclk = NULL, + .tuner_get_status = NULL, +}; + +static struct stv6110x_config tt1600_stv6110x_config = { + .addr = 0x60, + .refclk = 27000000, + .clk_div = 2, +}; + +static struct isl6423_config tt1600_isl6423_config = { + .current_max = SEC_CURRENT_515m, + .curlim = SEC_CURRENT_LIM_ON, + .mod_extern = 1, + .addr = 0x08, +}; + +static void frontend_init(struct budget *budget) +{ + (void)alps_bsbe1_config; /* avoid warning */ + + switch(budget->dev->pci->subsystem_device) { + case 0x1003: // Hauppauge/TT Nova budget (stv0299/ALPS BSRU6(tsa5059) OR ves1893/ALPS BSRV2(sp5659)) + case 0x1013: + // try the ALPS BSRV2 first of all + budget->dvb_frontend = dvb_attach(ves1x93_attach, &alps_bsrv2_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsrv2_tuner_set_params; + budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd; + budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst; + budget->dvb_frontend->ops.set_tone = budget_set_tone; + break; + } + + // try the ALPS BSRU6 now + budget->dvb_frontend = dvb_attach(stv0299_attach, &alps_bsru6_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params; + budget->dvb_frontend->tuner_priv = &budget->i2c_adap; + if (budget->dev->pci->subsystem_device == 0x1003 && diseqc_method == 0) { + budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd; + budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst; + budget->dvb_frontend->ops.set_tone = budget_set_tone; + } + break; + } + break; + + case 0x1004: // Hauppauge/TT DVB-C budget (ves1820/ALPS TDBE2(sp5659)) + + budget->dvb_frontend = dvb_attach(ves1820_attach, &alps_tdbe2_config, &budget->i2c_adap, read_pwm(budget)); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = alps_tdbe2_tuner_set_params; + break; + } + break; + + case 0x1005: // Hauppauge/TT Nova-T budget (L64781/Grundig 29504-401(tsa5060)) + + budget->dvb_frontend = dvb_attach(l64781_attach, &grundig_29504_401_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = grundig_29504_401_tuner_set_params; + budget->dvb_frontend->tuner_priv = NULL; + break; + } + break; + + case 0x4f52: /* Cards based on Philips Semi Sylt PCI ref. design */ + budget->dvb_frontend = dvb_attach(stv0299_attach, &alps_bsru6_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + printk(KERN_INFO "budget: tuner ALPS BSRU6 in Philips Semi. Sylt detected\n"); + budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params; + budget->dvb_frontend->tuner_priv = &budget->i2c_adap; + break; + } + break; + + case 0x4f60: /* Fujitsu Siemens Activy Budget-S PCI rev AL (stv0299/tsa5059) */ + { + int subtype = i2c_readreg(&budget->i2c_adap, 0x50, 0x67); + + if (subtype < 0) + break; + /* fixme: find a better way to identify the card */ + if (subtype < 0x36) { + /* assume ALPS BSRU6 */ + budget->dvb_frontend = dvb_attach(stv0299_attach, &alps_bsru6_config_activy, &budget->i2c_adap); + if (budget->dvb_frontend) { + printk(KERN_INFO "budget: tuner ALPS BSRU6 detected\n"); + budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params; + budget->dvb_frontend->tuner_priv = &budget->i2c_adap; + budget->dvb_frontend->ops.set_voltage = siemens_budget_set_voltage; + budget->dvb_frontend->ops.dishnetwork_send_legacy_command = NULL; + break; + } + } else { + /* assume ALPS BSBE1 */ + /* reset tuner */ + saa7146_setgpio(budget->dev, 3, SAA7146_GPIO_OUTLO); + msleep(50); + saa7146_setgpio(budget->dev, 3, SAA7146_GPIO_OUTHI); + msleep(250); + budget->dvb_frontend = dvb_attach(stv0299_attach, &alps_bsbe1_config_activy, &budget->i2c_adap); + if (budget->dvb_frontend) { + printk(KERN_INFO "budget: tuner ALPS BSBE1 detected\n"); + budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsbe1_tuner_set_params; + budget->dvb_frontend->tuner_priv = &budget->i2c_adap; + budget->dvb_frontend->ops.set_voltage = siemens_budget_set_voltage; + budget->dvb_frontend->ops.dishnetwork_send_legacy_command = NULL; + break; + } + } + break; + } + + case 0x4f61: // Fujitsu Siemens Activy Budget-S PCI rev GR (tda8083/Grundig 29504-451(tsa5522)) + budget->dvb_frontend = dvb_attach(tda8083_attach, &grundig_29504_451_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = grundig_29504_451_tuner_set_params; + budget->dvb_frontend->ops.set_voltage = siemens_budget_set_voltage; + budget->dvb_frontend->ops.dishnetwork_send_legacy_command = NULL; + } + break; + + case 0x5f60: /* Fujitsu Siemens Activy Budget-T PCI rev AL (tda10046/ALPS TDHD1-204A) */ + budget->dvb_frontend = dvb_attach(tda10046_attach, &alps_tdhd1_204a_config, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->ops.tuner_ops.set_params = alps_tdhd1_204a_tuner_set_params; + budget->dvb_frontend->tuner_priv = &budget->i2c_adap; + } + break; + + case 0x5f61: /* Fujitsu Siemens Activy Budget-T PCI rev GR (L64781/Grundig 29504-401(tsa5060)) */ + budget->dvb_frontend = dvb_attach(l64781_attach, &grundig_29504_401_config_activy, &budget->i2c_adap); + if (budget->dvb_frontend) { + budget->dvb_frontend->tuner_priv = &tuner_address_grundig_29504_401_activy; + budget->dvb_frontend->ops.tuner_ops.set_params = grundig_29504_401_tuner_set_params; + } + break; + + case 0x1016: // Hauppauge/TT Nova-S SE (samsung s5h1420/????(tda8260)) + { + struct dvb_frontend *fe; + + fe = dvb_attach(s5h1420_attach, &s5h1420_config, &budget->i2c_adap); + if (fe) { + fe->ops.tuner_ops.set_params = s5h1420_tuner_set_params; + budget->dvb_frontend = fe; + if (dvb_attach(lnbp21_attach, fe, &budget->i2c_adap, + 0, 0) == NULL) { + printk("%s: No LNBP21 found!\n", __func__); + goto error_out; + } + break; + } + } + fallthrough; + case 0x1018: // TT Budget-S-1401 (philips tda10086/philips tda8262) + { + struct dvb_frontend *fe; + + // gpio2 is connected to CLB - reset it + leave it high + saa7146_setgpio(budget->dev, 2, SAA7146_GPIO_OUTLO); + msleep(1); + saa7146_setgpio(budget->dev, 2, SAA7146_GPIO_OUTHI); + msleep(1); + + fe = dvb_attach(tda10086_attach, &tda10086_config, &budget->i2c_adap); + if (fe) { + budget->dvb_frontend = fe; + if (dvb_attach(tda826x_attach, fe, 0x60, + &budget->i2c_adap, 0) == NULL) + printk("%s: No tda826x found!\n", __func__); + if (dvb_attach(lnbp21_attach, fe, + &budget->i2c_adap, 0, 0) == NULL) { + printk("%s: No LNBP21 found!\n", __func__); + goto error_out; + } + break; + } + } + fallthrough; + + case 0x101c: { /* TT S2-1600 */ + const struct stv6110x_devctl *ctl; + saa7146_setgpio(budget->dev, 2, SAA7146_GPIO_OUTLO); + msleep(50); + saa7146_setgpio(budget->dev, 2, SAA7146_GPIO_OUTHI); + msleep(250); + + budget->dvb_frontend = dvb_attach(stv090x_attach, + &tt1600_stv090x_config, + &budget->i2c_adap, + STV090x_DEMODULATOR_0); + + if (budget->dvb_frontend) { + + ctl = dvb_attach(stv6110x_attach, + budget->dvb_frontend, + &tt1600_stv6110x_config, + &budget->i2c_adap); + + if (ctl) { + tt1600_stv090x_config.tuner_init = ctl->tuner_init; + tt1600_stv090x_config.tuner_sleep = ctl->tuner_sleep; + tt1600_stv090x_config.tuner_set_mode = ctl->tuner_set_mode; + tt1600_stv090x_config.tuner_set_frequency = ctl->tuner_set_frequency; + tt1600_stv090x_config.tuner_get_frequency = ctl->tuner_get_frequency; + tt1600_stv090x_config.tuner_set_bandwidth = ctl->tuner_set_bandwidth; + tt1600_stv090x_config.tuner_get_bandwidth = ctl->tuner_get_bandwidth; + tt1600_stv090x_config.tuner_set_bbgain = ctl->tuner_set_bbgain; + tt1600_stv090x_config.tuner_get_bbgain = ctl->tuner_get_bbgain; + tt1600_stv090x_config.tuner_set_refclk = ctl->tuner_set_refclk; + tt1600_stv090x_config.tuner_get_status = ctl->tuner_get_status; + + /* call the init function once to initialize + tuner's clock output divider and demod's + master clock */ + if (budget->dvb_frontend->ops.init) + budget->dvb_frontend->ops.init(budget->dvb_frontend); + + if (dvb_attach(isl6423_attach, + budget->dvb_frontend, + &budget->i2c_adap, + &tt1600_isl6423_config) == NULL) { + printk(KERN_ERR "%s: No Intersil ISL6423 found!\n", __func__); + goto error_out; + } + } else { + printk(KERN_ERR "%s: No STV6110(A) Silicon Tuner found!\n", __func__); + goto error_out; + } + } + } + break; + + case 0x1020: { /* Omicom S2 */ + const struct stv6110x_devctl *ctl; + saa7146_setgpio(budget->dev, 2, SAA7146_GPIO_OUTLO); + msleep(50); + saa7146_setgpio(budget->dev, 2, SAA7146_GPIO_OUTHI); + msleep(250); + + budget->dvb_frontend = dvb_attach(stv090x_attach, + &tt1600_stv090x_config, + &budget->i2c_adap, + STV090x_DEMODULATOR_0); + + if (budget->dvb_frontend) { + printk(KERN_INFO "budget: Omicom S2 detected\n"); + + ctl = dvb_attach(stv6110x_attach, + budget->dvb_frontend, + &tt1600_stv6110x_config, + &budget->i2c_adap); + + if (ctl) { + tt1600_stv090x_config.tuner_init = ctl->tuner_init; + tt1600_stv090x_config.tuner_sleep = ctl->tuner_sleep; + tt1600_stv090x_config.tuner_set_mode = ctl->tuner_set_mode; + tt1600_stv090x_config.tuner_set_frequency = ctl->tuner_set_frequency; + tt1600_stv090x_config.tuner_get_frequency = ctl->tuner_get_frequency; + tt1600_stv090x_config.tuner_set_bandwidth = ctl->tuner_set_bandwidth; + tt1600_stv090x_config.tuner_get_bandwidth = ctl->tuner_get_bandwidth; + tt1600_stv090x_config.tuner_set_bbgain = ctl->tuner_set_bbgain; + tt1600_stv090x_config.tuner_get_bbgain = ctl->tuner_get_bbgain; + tt1600_stv090x_config.tuner_set_refclk = ctl->tuner_set_refclk; + tt1600_stv090x_config.tuner_get_status = ctl->tuner_get_status; + + /* call the init function once to initialize + tuner's clock output divider and demod's + master clock */ + if (budget->dvb_frontend->ops.init) + budget->dvb_frontend->ops.init(budget->dvb_frontend); + + if (dvb_attach(lnbh24_attach, + budget->dvb_frontend, + &budget->i2c_adap, + LNBH24_PCL | LNBH24_TTX, + LNBH24_TEN, 0x14>>1) == NULL) { + printk(KERN_ERR + "No LNBH24 found!\n"); + goto error_out; + } + } else { + printk(KERN_ERR "%s: No STV6110(A) Silicon Tuner found!\n", __func__); + goto error_out; + } + } + } + break; + } + + if (budget->dvb_frontend == NULL) { + printk("budget: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n", + budget->dev->pci->vendor, + budget->dev->pci->device, + budget->dev->pci->subsystem_vendor, + budget->dev->pci->subsystem_device); + } else { + if (dvb_register_frontend(&budget->dvb_adapter, budget->dvb_frontend)) + goto error_out; + } + return; + +error_out: + printk("budget: Frontend registration failed!\n"); + dvb_frontend_detach(budget->dvb_frontend); + budget->dvb_frontend = NULL; + return; +} + +static int budget_attach (struct saa7146_dev* dev, struct saa7146_pci_extension_data *info) +{ + struct budget *budget = NULL; + int err; + + budget = kmalloc(sizeof(struct budget), GFP_KERNEL); + if( NULL == budget ) { + return -ENOMEM; + } + + dprintk(2, "dev:%p, info:%p, budget:%p\n", dev, info, budget); + + dev->ext_priv = budget; + + err = ttpci_budget_init(budget, dev, info, THIS_MODULE, adapter_nr); + if (err) { + printk("==> failed\n"); + kfree (budget); + return err; + } + + budget->dvb_adapter.priv = budget; + frontend_init(budget); + + ttpci_budget_init_hooks(budget); + + return 0; +} + +static int budget_detach (struct saa7146_dev* dev) +{ + struct budget *budget = (struct budget*) dev->ext_priv; + int err; + + if (budget->dvb_frontend) { + dvb_unregister_frontend(budget->dvb_frontend); + dvb_frontend_detach(budget->dvb_frontend); + } + + err = ttpci_budget_deinit (budget); + + kfree (budget); + dev->ext_priv = NULL; + + return err; +} + +static struct saa7146_extension budget_extension; + +MAKE_BUDGET_INFO(ttbs, "TT-Budget/WinTV-NOVA-S PCI", BUDGET_TT); +MAKE_BUDGET_INFO(ttbc, "TT-Budget/WinTV-NOVA-C PCI", BUDGET_TT); +MAKE_BUDGET_INFO(ttbt, "TT-Budget/WinTV-NOVA-T PCI", BUDGET_TT); +MAKE_BUDGET_INFO(satel, "SATELCO Multimedia PCI", BUDGET_TT_HW_DISEQC); +MAKE_BUDGET_INFO(ttbs1401, "TT-Budget-S-1401 PCI", BUDGET_TT); +MAKE_BUDGET_INFO(tt1600, "TT-Budget S2-1600 PCI", BUDGET_TT); +MAKE_BUDGET_INFO(fsacs0, "Fujitsu Siemens Activy Budget-S PCI (rev GR/grundig frontend)", BUDGET_FS_ACTIVY); +MAKE_BUDGET_INFO(fsacs1, "Fujitsu Siemens Activy Budget-S PCI (rev AL/alps frontend)", BUDGET_FS_ACTIVY); +MAKE_BUDGET_INFO(fsact, "Fujitsu Siemens Activy Budget-T PCI (rev GR/Grundig frontend)", BUDGET_FS_ACTIVY); +MAKE_BUDGET_INFO(fsact1, "Fujitsu Siemens Activy Budget-T PCI (rev AL/ALPS TDHD1-204A)", BUDGET_FS_ACTIVY); +MAKE_BUDGET_INFO(omicom, "Omicom S2 PCI", BUDGET_TT); +MAKE_BUDGET_INFO(sylt, "Philips Semi Sylt PCI", BUDGET_TT_HW_DISEQC); + +static const struct pci_device_id pci_tbl[] = { + MAKE_EXTENSION_PCI(ttbs, 0x13c2, 0x1003), + MAKE_EXTENSION_PCI(ttbc, 0x13c2, 0x1004), + MAKE_EXTENSION_PCI(ttbt, 0x13c2, 0x1005), + MAKE_EXTENSION_PCI(satel, 0x13c2, 0x1013), + MAKE_EXTENSION_PCI(ttbs, 0x13c2, 0x1016), + MAKE_EXTENSION_PCI(ttbs1401, 0x13c2, 0x1018), + MAKE_EXTENSION_PCI(tt1600, 0x13c2, 0x101c), + MAKE_EXTENSION_PCI(fsacs1,0x1131, 0x4f60), + MAKE_EXTENSION_PCI(fsacs0,0x1131, 0x4f61), + MAKE_EXTENSION_PCI(fsact1, 0x1131, 0x5f60), + MAKE_EXTENSION_PCI(fsact, 0x1131, 0x5f61), + MAKE_EXTENSION_PCI(omicom, 0x14c4, 0x1020), + MAKE_EXTENSION_PCI(sylt, 0x1131, 0x4f52), + { + .vendor = 0, + } +}; + +MODULE_DEVICE_TABLE(pci, pci_tbl); + +static struct saa7146_extension budget_extension = { + .name = "budget dvb", + .flags = SAA7146_USE_I2C_IRQ, + + .module = THIS_MODULE, + .pci_tbl = pci_tbl, + .attach = budget_attach, + .detach = budget_detach, + + .irq_mask = MASK_10, + .irq_func = ttpci_budget_irq10_handler, +}; + +static int __init budget_init(void) +{ + return saa7146_register_extension(&budget_extension); +} + +static void __exit budget_exit(void) +{ + saa7146_unregister_extension(&budget_extension); +} + +module_init(budget_init); +module_exit(budget_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ralph Metzler, Marcus Metzler, Michael Hunold, others"); +MODULE_DESCRIPTION("driver for the SAA7146 based so-called budget PCI DVB cards by Siemens, Technotrend, Hauppauge"); diff --git a/drivers/staging/media/deprecated/saa7146/ttpci/budget.h b/drivers/staging/media/deprecated/saa7146/ttpci/budget.h new file mode 100644 index 000000000..82cc0df49 --- /dev/null +++ b/drivers/staging/media/deprecated/saa7146/ttpci/budget.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __BUDGET_DVB__ +#define __BUDGET_DVB__ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../common/saa7146.h" + +extern int budget_debug; + +#ifdef dprintk +#undef dprintk +#endif + +#define dprintk(level, fmt, arg...) do { \ + if (level & budget_debug) \ + printk(KERN_DEBUG KBUILD_MODNAME ": %s(): " fmt, \ + __func__, ##arg); \ +} while (0) + +#define TS_SIZE 188 + +struct budget_info { + char *name; + int type; +}; + +/* place to store all the necessary device information */ +struct budget { + + /* devices */ + struct dvb_device dvb_dev; + struct dvb_net dvb_net; + + struct saa7146_dev *dev; + + struct i2c_adapter i2c_adap; + struct budget_info *card; + + unsigned char *grabbing; + struct saa7146_pgtable pt; + + struct tasklet_struct fidb_tasklet; + struct tasklet_struct vpe_tasklet; + + struct dmxdev dmxdev; + struct dvb_demux demux; + + struct dmx_frontend hw_frontend; + struct dmx_frontend mem_frontend; + + int ci_present; + int video_port; + + u32 buffer_width; + u32 buffer_height; + u32 buffer_size; + u32 buffer_warning_threshold; + u32 buffer_warnings; + unsigned long buffer_warning_time; + + u32 ttbp; + int feeding; + + spinlock_t feedlock; + + spinlock_t debilock; + + struct dvb_adapter dvb_adapter; + struct dvb_frontend *dvb_frontend; + int (*read_fe_status)(struct dvb_frontend *fe, enum fe_status *status); + int fe_synced; + + void *priv; +}; + +#define MAKE_BUDGET_INFO(x_var,x_name,x_type) \ +static struct budget_info x_var ## _info = { \ + .name=x_name, \ + .type=x_type }; \ +static struct saa7146_pci_extension_data x_var = { \ + .ext_priv = &x_var ## _info, \ + .ext = &budget_extension }; + +#define BUDGET_TT 0 +#define BUDGET_TT_HW_DISEQC 1 +#define BUDGET_PATCH 3 +#define BUDGET_FS_ACTIVY 4 +#define BUDGET_CIN1200S 5 +#define BUDGET_CIN1200C 6 +#define BUDGET_CIN1200T 7 +#define BUDGET_KNC1S 8 +#define BUDGET_KNC1C 9 +#define BUDGET_KNC1T 10 +#define BUDGET_KNC1SP 11 +#define BUDGET_KNC1CP 12 +#define BUDGET_KNC1TP 13 +#define BUDGET_TVSTAR 14 +#define BUDGET_CIN1200C_MK3 15 +#define BUDGET_KNC1C_MK3 16 +#define BUDGET_KNC1CP_MK3 17 +#define BUDGET_KNC1S2 18 +#define BUDGET_KNC1C_TDA10024 19 + +#define BUDGET_VIDEO_PORTA 0 +#define BUDGET_VIDEO_PORTB 1 + +extern int ttpci_budget_init(struct budget *budget, struct saa7146_dev *dev, + struct saa7146_pci_extension_data *info, + struct module *owner, short *adapter_nums); +extern void ttpci_budget_init_hooks(struct budget *budget); +extern int ttpci_budget_deinit(struct budget *budget); +extern void ttpci_budget_irq10_handler(struct saa7146_dev *dev, u32 * isr); +extern void ttpci_budget_set_video_port(struct saa7146_dev *dev, int video_port); +extern int ttpci_budget_debiread(struct budget *budget, u32 config, int addr, int count, + int uselocks, int nobusyloop); +extern int ttpci_budget_debiwrite(struct budget *budget, u32 config, int addr, int count, u32 value, + int uselocks, int nobusyloop); + +#endif diff --git a/drivers/staging/media/deprecated/stkwebcam/Kconfig b/drivers/staging/media/deprecated/stkwebcam/Kconfig new file mode 100644 index 000000000..7234498e6 --- /dev/null +++ b/drivers/staging/media/deprecated/stkwebcam/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_STKWEBCAM + tristate "USB Syntek DC1125 Camera support (DEPRECATED)" + depends on VIDEO_DEV + depends on MEDIA_USB_SUPPORT && MEDIA_CAMERA_SUPPORT + help + Say Y here if you want to use this type of camera. + Supported devices are typically found in some Asus laptops, + with USB id 174f:a311 and 05e1:0501. Other Syntek cameras + may be supported by the stk11xx driver, from which this is + derived, see + + This driver is deprecated and is scheduled for removal by + the end of 2022. See the TODO file for more information. + + To compile this driver as a module, choose M here: the + module will be called stkwebcam. + diff --git a/drivers/staging/media/deprecated/stkwebcam/Makefile b/drivers/staging/media/deprecated/stkwebcam/Makefile new file mode 100644 index 000000000..17ad7b6f4 --- /dev/null +++ b/drivers/staging/media/deprecated/stkwebcam/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +stkwebcam-objs := stk-webcam.o stk-sensor.o + +obj-$(CONFIG_VIDEO_STKWEBCAM) += stkwebcam.o + diff --git a/drivers/staging/media/deprecated/stkwebcam/TODO b/drivers/staging/media/deprecated/stkwebcam/TODO new file mode 100644 index 000000000..735304a72 --- /dev/null +++ b/drivers/staging/media/deprecated/stkwebcam/TODO @@ -0,0 +1,12 @@ +This is a very old driver for very old hardware (specifically +laptops that use this sensor). In addition according to reports +the picture quality is quite bad. + +This is also one of the few drivers still not using the vb2 +framework (or even the old videobuf framework!), so this driver +is now deprecated with the intent of removing it altogether by +the end of 2022. + +In order to keep this driver it has to be converted to vb2. +If someone is interested in doing this work, then contact the +linux-media mailinglist (https://linuxtv.org/lists.php). diff --git a/drivers/staging/media/deprecated/stkwebcam/stk-sensor.c b/drivers/staging/media/deprecated/stkwebcam/stk-sensor.c new file mode 100644 index 000000000..94aa6a27f --- /dev/null +++ b/drivers/staging/media/deprecated/stkwebcam/stk-sensor.c @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* stk-sensor.c: Driver for ov96xx sensor (used in some Syntek webcams) + * + * Copyright 2007-2008 Jaime Velasco Juan + * + * Some parts derived from ov7670.c: + * Copyright 2006 One Laptop Per Child Association, Inc. Written + * by Jonathan Corbet with substantial inspiration from Mark + * McClelland's ovcamchip code. + * + * Copyright 2006-7 Jonathan Corbet + * + * This file may be distributed under the terms of the GNU General + */ + +/* Controlling the sensor via the STK1125 vendor specific control interface: + * The camera uses an OmniVision sensor and the stk1125 provides an + * SCCB(i2c)-USB bridge which let us program the sensor. + * In my case the sensor id is 0x9652, it can be read from sensor's register + * 0x0A and 0x0B as follows: + * - read register #R: + * output #R to index 0x0208 + * output 0x0070 to index 0x0200 + * input 1 byte from index 0x0201 (some kind of status register) + * until its value is 0x01 + * input 1 byte from index 0x0209. This is the value of #R + * - write value V to register #R + * output #R to index 0x0204 + * output V to index 0x0205 + * output 0x0005 to index 0x0200 + * input 1 byte from index 0x0201 until its value becomes 0x04 + */ + +/* It seems the i2c bus is controlled with these registers */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include "stk-webcam.h" + +#define STK_IIC_BASE (0x0200) +# define STK_IIC_OP (STK_IIC_BASE) +# define STK_IIC_OP_TX (0x05) +# define STK_IIC_OP_RX (0x70) +# define STK_IIC_STAT (STK_IIC_BASE+1) +# define STK_IIC_STAT_TX_OK (0x04) +# define STK_IIC_STAT_RX_OK (0x01) +/* I don't know what does this register. + * when it is 0x00 or 0x01, we cannot talk to the sensor, + * other values work */ +# define STK_IIC_ENABLE (STK_IIC_BASE+2) +# define STK_IIC_ENABLE_NO (0x00) +/* This is what the driver writes in windows */ +# define STK_IIC_ENABLE_YES (0x1e) +/* + * Address of the slave. Seems like the binary driver look for the + * sensor in multiple places, attempting a reset sequence. + * We only know about the ov9650 + */ +# define STK_IIC_ADDR (STK_IIC_BASE+3) +# define STK_IIC_TX_INDEX (STK_IIC_BASE+4) +# define STK_IIC_TX_VALUE (STK_IIC_BASE+5) +# define STK_IIC_RX_INDEX (STK_IIC_BASE+8) +# define STK_IIC_RX_VALUE (STK_IIC_BASE+9) + +#define MAX_RETRIES (50) + +#define SENSOR_ADDRESS (0x60) + +/* From ov7670.c (These registers aren't fully accurate) */ + +/* Registers */ +#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ +#define REG_BLUE 0x01 /* blue gain */ +#define REG_RED 0x02 /* red gain */ +#define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ +#define REG_COM1 0x04 /* Control 1 */ +#define COM1_CCIR656 0x40 /* CCIR656 enable */ +#define COM1_QFMT 0x20 /* QVGA/QCIF format */ +#define COM1_SKIP_0 0x00 /* Do not skip any row */ +#define COM1_SKIP_2 0x04 /* Skip 2 rows of 4 */ +#define COM1_SKIP_3 0x08 /* Skip 3 rows of 4 */ +#define REG_BAVE 0x05 /* U/B Average level */ +#define REG_GbAVE 0x06 /* Y/Gb Average level */ +#define REG_AECHH 0x07 /* AEC MS 5 bits */ +#define REG_RAVE 0x08 /* V/R Average level */ +#define REG_COM2 0x09 /* Control 2 */ +#define COM2_SSLEEP 0x10 /* Soft sleep mode */ +#define REG_PID 0x0a /* Product ID MSB */ +#define REG_VER 0x0b /* Product ID LSB */ +#define REG_COM3 0x0c /* Control 3 */ +#define COM3_SWAP 0x40 /* Byte swap */ +#define COM3_SCALEEN 0x08 /* Enable scaling */ +#define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ +#define REG_COM4 0x0d /* Control 4 */ +#define REG_COM5 0x0e /* All "reserved" */ +#define REG_COM6 0x0f /* Control 6 */ +#define REG_AECH 0x10 /* More bits of AEC value */ +#define REG_CLKRC 0x11 /* Clock control */ +#define CLK_PLL 0x80 /* Enable internal PLL */ +#define CLK_EXT 0x40 /* Use external clock directly */ +#define CLK_SCALE 0x3f /* Mask for internal clock scale */ +#define REG_COM7 0x12 /* Control 7 */ +#define COM7_RESET 0x80 /* Register reset */ +#define COM7_FMT_MASK 0x38 +#define COM7_FMT_SXGA 0x00 +#define COM7_FMT_VGA 0x40 +#define COM7_FMT_CIF 0x20 /* CIF format */ +#define COM7_FMT_QVGA 0x10 /* QVGA format */ +#define COM7_FMT_QCIF 0x08 /* QCIF format */ +#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ +#define COM7_YUV 0x00 /* YUV */ +#define COM7_BAYER 0x01 /* Bayer format */ +#define COM7_PBAYER 0x05 /* "Processed bayer" */ +#define REG_COM8 0x13 /* Control 8 */ +#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ +#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ +#define COM8_BFILT 0x20 /* Band filter enable */ +#define COM8_AGC 0x04 /* Auto gain enable */ +#define COM8_AWB 0x02 /* White balance enable */ +#define COM8_AEC 0x01 /* Auto exposure enable */ +#define REG_COM9 0x14 /* Control 9 - gain ceiling */ +#define REG_COM10 0x15 /* Control 10 */ +#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ +#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ +#define COM10_HREF_REV 0x08 /* Reverse HREF */ +#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ +#define COM10_VS_NEG 0x02 /* VSYNC negative */ +#define COM10_HS_NEG 0x01 /* HSYNC negative */ +#define REG_HSTART 0x17 /* Horiz start high bits */ +#define REG_HSTOP 0x18 /* Horiz stop high bits */ +#define REG_VSTART 0x19 /* Vert start high bits */ +#define REG_VSTOP 0x1a /* Vert stop high bits */ +#define REG_PSHFT 0x1b /* Pixel delay after HREF */ +#define REG_MIDH 0x1c /* Manuf. ID high */ +#define REG_MIDL 0x1d /* Manuf. ID low */ +#define REG_MVFP 0x1e /* Mirror / vflip */ +#define MVFP_MIRROR 0x20 /* Mirror image */ +#define MVFP_FLIP 0x10 /* Vertical flip */ + +#define REG_AEW 0x24 /* AGC upper limit */ +#define REG_AEB 0x25 /* AGC lower limit */ +#define REG_VPT 0x26 /* AGC/AEC fast mode op region */ +#define REG_ADVFL 0x2d /* Insert dummy lines (LSB) */ +#define REG_ADVFH 0x2e /* Insert dummy lines (MSB) */ +#define REG_HSYST 0x30 /* HSYNC rising edge delay */ +#define REG_HSYEN 0x31 /* HSYNC falling edge delay */ +#define REG_HREF 0x32 /* HREF pieces */ +#define REG_TSLB 0x3a /* lots of stuff */ +#define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ +#define TSLB_BYTEORD 0x08 /* swap bytes in 16bit mode? */ +#define REG_COM11 0x3b /* Control 11 */ +#define COM11_NIGHT 0x80 /* NIght mode enable */ +#define COM11_NMFR 0x60 /* Two bit NM frame rate */ +#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ +#define COM11_50HZ 0x08 /* Manual 50Hz select */ +#define COM11_EXP 0x02 +#define REG_COM12 0x3c /* Control 12 */ +#define COM12_HREF 0x80 /* HREF always */ +#define REG_COM13 0x3d /* Control 13 */ +#define COM13_GAMMA 0x80 /* Gamma enable */ +#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ +#define COM13_CMATRIX 0x10 /* Enable color matrix for RGB or YUV */ +#define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ +#define REG_COM14 0x3e /* Control 14 */ +#define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ +#define REG_EDGE 0x3f /* Edge enhancement factor */ +#define REG_COM15 0x40 /* Control 15 */ +#define COM15_R10F0 0x00 /* Data range 10 to F0 */ +#define COM15_R01FE 0x80 /* 01 to FE */ +#define COM15_R00FF 0xc0 /* 00 to FF */ +#define COM15_RGB565 0x10 /* RGB565 output */ +#define COM15_RGBFIXME 0x20 /* FIXME */ +#define COM15_RGB555 0x30 /* RGB555 output */ +#define REG_COM16 0x41 /* Control 16 */ +#define COM16_AWBGAIN 0x08 /* AWB gain enable */ +#define REG_COM17 0x42 /* Control 17 */ +#define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ +#define COM17_CBAR 0x08 /* DSP Color bar */ + +/* + * This matrix defines how the colors are generated, must be + * tweaked to adjust hue and saturation. + * + * Order: v-red, v-green, v-blue, u-red, u-green, u-blue + * + * They are nine-bit signed quantities, with the sign bit + * stored in 0x58. Sign for v-red is bit 0, and up from there. + */ +#define REG_CMATRIX_BASE 0x4f +#define CMATRIX_LEN 6 +#define REG_CMATRIX_SIGN 0x58 + + +#define REG_BRIGHT 0x55 /* Brightness */ +#define REG_CONTRAS 0x56 /* Contrast control */ + +#define REG_GFIX 0x69 /* Fix gain control */ + +#define REG_RGB444 0x8c /* RGB 444 control */ +#define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ +#define R444_RGBX 0x01 /* Empty nibble at end */ + +#define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ +#define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ + +#define REG_BD50MAX 0xa5 /* 50hz banding step limit */ +#define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ +#define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ +#define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ +#define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ +#define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ +#define REG_BD60MAX 0xab /* 60hz banding step limit */ + + + + +/* Returns 0 if OK */ +static int stk_sensor_outb(struct stk_camera *dev, u8 reg, u8 val) +{ + int i = 0; + u8 tmpval = 0; + + if (stk_camera_write_reg(dev, STK_IIC_TX_INDEX, reg)) + return 1; + if (stk_camera_write_reg(dev, STK_IIC_TX_VALUE, val)) + return 1; + if (stk_camera_write_reg(dev, STK_IIC_OP, STK_IIC_OP_TX)) + return 1; + do { + if (stk_camera_read_reg(dev, STK_IIC_STAT, &tmpval)) + return 1; + i++; + } while (tmpval == 0 && i < MAX_RETRIES); + if (tmpval != STK_IIC_STAT_TX_OK) { + if (tmpval) + pr_err("stk_sensor_outb failed, status=0x%02x\n", + tmpval); + return 1; + } else + return 0; +} + +static int stk_sensor_inb(struct stk_camera *dev, u8 reg, u8 *val) +{ + int i = 0; + u8 tmpval = 0; + + if (stk_camera_write_reg(dev, STK_IIC_RX_INDEX, reg)) + return 1; + if (stk_camera_write_reg(dev, STK_IIC_OP, STK_IIC_OP_RX)) + return 1; + do { + if (stk_camera_read_reg(dev, STK_IIC_STAT, &tmpval)) + return 1; + i++; + } while (tmpval == 0 && i < MAX_RETRIES); + if (tmpval != STK_IIC_STAT_RX_OK) { + if (tmpval) + pr_err("stk_sensor_inb failed, status=0x%02x\n", + tmpval); + return 1; + } + + if (stk_camera_read_reg(dev, STK_IIC_RX_VALUE, &tmpval)) + return 1; + + *val = tmpval; + return 0; +} + +static int stk_sensor_write_regvals(struct stk_camera *dev, + struct regval *rv) +{ + int ret; + if (rv == NULL) + return 0; + while (rv->reg != 0xff || rv->val != 0xff) { + ret = stk_sensor_outb(dev, rv->reg, rv->val); + if (ret != 0) + return ret; + rv++; + } + return 0; +} + +int stk_sensor_sleep(struct stk_camera *dev) +{ + u8 tmp; + return stk_sensor_inb(dev, REG_COM2, &tmp) + || stk_sensor_outb(dev, REG_COM2, tmp|COM2_SSLEEP); +} + +int stk_sensor_wakeup(struct stk_camera *dev) +{ + u8 tmp; + return stk_sensor_inb(dev, REG_COM2, &tmp) + || stk_sensor_outb(dev, REG_COM2, tmp&~COM2_SSLEEP); +} + +static struct regval ov_initvals[] = { + {REG_CLKRC, CLK_PLL}, + {REG_COM11, 0x01}, + {0x6a, 0x7d}, + {REG_AECH, 0x40}, + {REG_GAIN, 0x00}, + {REG_BLUE, 0x80}, + {REG_RED, 0x80}, + /* Do not enable fast AEC for now */ + /*{REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC},*/ + {REG_COM8, COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC}, + {0x39, 0x50}, {0x38, 0x93}, + {0x37, 0x00}, {0x35, 0x81}, + {REG_COM5, 0x20}, + {REG_COM1, 0x00}, + {REG_COM3, 0x00}, + {REG_COM4, 0x00}, + {REG_PSHFT, 0x00}, + {0x16, 0x07}, + {0x33, 0xe2}, {0x34, 0xbf}, + {REG_COM16, 0x00}, + {0x96, 0x04}, + /* Gamma curve values */ +/* { 0x7a, 0x20 }, { 0x7b, 0x10 }, + { 0x7c, 0x1e }, { 0x7d, 0x35 }, + { 0x7e, 0x5a }, { 0x7f, 0x69 }, + { 0x80, 0x76 }, { 0x81, 0x80 }, + { 0x82, 0x88 }, { 0x83, 0x8f }, + { 0x84, 0x96 }, { 0x85, 0xa3 }, + { 0x86, 0xaf }, { 0x87, 0xc4 }, + { 0x88, 0xd7 }, { 0x89, 0xe8 }, +*/ + {REG_GFIX, 0x40}, + {0x8e, 0x00}, + {REG_COM12, 0x73}, + {0x8f, 0xdf}, {0x8b, 0x06}, + {0x8c, 0x20}, + {0x94, 0x88}, {0x95, 0x88}, +/* {REG_COM15, 0xc1}, TODO */ + {0x29, 0x3f}, + {REG_COM6, 0x42}, + {REG_BD50MAX, 0x80}, + {REG_HAECC6, 0xb8}, {REG_HAECC7, 0x92}, + {REG_BD60MAX, 0x0a}, + {0x90, 0x00}, {0x91, 0x00}, + {REG_HAECC1, 0x00}, {REG_HAECC2, 0x00}, + {REG_AEW, 0x68}, {REG_AEB, 0x5c}, + {REG_VPT, 0xc3}, + {REG_COM9, 0x2e}, + {0x2a, 0x00}, {0x2b, 0x00}, + + {0xff, 0xff}, /* END MARKER */ +}; + +/* Probe the I2C bus and initialise the sensor chip */ +int stk_sensor_init(struct stk_camera *dev) +{ + u8 idl = 0; + u8 idh = 0; + + if (stk_camera_write_reg(dev, STK_IIC_ENABLE, STK_IIC_ENABLE_YES) + || stk_camera_write_reg(dev, STK_IIC_ADDR, SENSOR_ADDRESS) + || stk_sensor_outb(dev, REG_COM7, COM7_RESET)) { + pr_err("Sensor resetting failed\n"); + return -ENODEV; + } + msleep(10); + /* Read the manufacturer ID: ov = 0x7FA2 */ + if (stk_sensor_inb(dev, REG_MIDH, &idh) + || stk_sensor_inb(dev, REG_MIDL, &idl)) { + pr_err("Strange error reading sensor ID\n"); + return -ENODEV; + } + if (idh != 0x7f || idl != 0xa2) { + pr_err("Huh? you don't have a sensor from ovt\n"); + return -ENODEV; + } + if (stk_sensor_inb(dev, REG_PID, &idh) + || stk_sensor_inb(dev, REG_VER, &idl)) { + pr_err("Could not read sensor model\n"); + return -ENODEV; + } + stk_sensor_write_regvals(dev, ov_initvals); + msleep(10); + pr_info("OmniVision sensor detected, id %02X%02X at address %x\n", + idh, idl, SENSOR_ADDRESS); + return 0; +} + +/* V4L2_PIX_FMT_UYVY */ +static struct regval ov_fmt_uyvy[] = { + {REG_TSLB, TSLB_YLAST|0x08 }, + { 0x4f, 0x80 }, /* "matrix coefficient 1" */ + { 0x50, 0x80 }, /* "matrix coefficient 2" */ + { 0x51, 0 }, /* vb */ + { 0x52, 0x22 }, /* "matrix coefficient 4" */ + { 0x53, 0x5e }, /* "matrix coefficient 5" */ + { 0x54, 0x80 }, /* "matrix coefficient 6" */ + {REG_COM13, COM13_UVSAT|COM13_CMATRIX}, + {REG_COM15, COM15_R00FF }, + {0xff, 0xff}, /* END MARKER */ +}; +/* V4L2_PIX_FMT_YUYV */ +static struct regval ov_fmt_yuyv[] = { + {REG_TSLB, 0 }, + { 0x4f, 0x80 }, /* "matrix coefficient 1" */ + { 0x50, 0x80 }, /* "matrix coefficient 2" */ + { 0x51, 0 }, /* vb */ + { 0x52, 0x22 }, /* "matrix coefficient 4" */ + { 0x53, 0x5e }, /* "matrix coefficient 5" */ + { 0x54, 0x80 }, /* "matrix coefficient 6" */ + {REG_COM13, COM13_UVSAT|COM13_CMATRIX}, + {REG_COM15, COM15_R00FF }, + {0xff, 0xff}, /* END MARKER */ +}; + +/* V4L2_PIX_FMT_RGB565X rrrrrggg gggbbbbb */ +static struct regval ov_fmt_rgbr[] = { + { REG_RGB444, 0 }, /* No RGB444 please */ + {REG_TSLB, 0x00}, + { REG_COM1, 0x0 }, + { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ + { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ + { 0x50, 0xb3 }, /* "matrix coefficient 2" */ + { 0x51, 0 }, /* vb */ + { 0x52, 0x3d }, /* "matrix coefficient 4" */ + { 0x53, 0xa7 }, /* "matrix coefficient 5" */ + { 0x54, 0xe4 }, /* "matrix coefficient 6" */ + { REG_COM13, COM13_GAMMA }, + { REG_COM15, COM15_RGB565|COM15_R00FF }, + { 0xff, 0xff }, +}; + +/* V4L2_PIX_FMT_RGB565 gggbbbbb rrrrrggg */ +static struct regval ov_fmt_rgbp[] = { + { REG_RGB444, 0 }, /* No RGB444 please */ + {REG_TSLB, TSLB_BYTEORD }, + { REG_COM1, 0x0 }, + { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ + { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ + { 0x50, 0xb3 }, /* "matrix coefficient 2" */ + { 0x51, 0 }, /* vb */ + { 0x52, 0x3d }, /* "matrix coefficient 4" */ + { 0x53, 0xa7 }, /* "matrix coefficient 5" */ + { 0x54, 0xe4 }, /* "matrix coefficient 6" */ + { REG_COM13, COM13_GAMMA }, + { REG_COM15, COM15_RGB565|COM15_R00FF }, + { 0xff, 0xff }, +}; + +/* V4L2_PIX_FMT_SRGGB8 */ +static struct regval ov_fmt_bayer[] = { + /* This changes color order */ + {REG_TSLB, 0x40}, /* BGGR */ + /* {REG_TSLB, 0x08}, */ /* BGGR with vertical image flipping */ + {REG_COM15, COM15_R00FF }, + {0xff, 0xff}, /* END MARKER */ +}; +/* + * Store a set of start/stop values into the camera. + */ +static int stk_sensor_set_hw(struct stk_camera *dev, + int hstart, int hstop, int vstart, int vstop) +{ + int ret; + unsigned char v; +/* + * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of + * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is + * a mystery "edge offset" value in the top two bits of href. + */ + ret = stk_sensor_outb(dev, REG_HSTART, (hstart >> 3) & 0xff); + ret += stk_sensor_outb(dev, REG_HSTOP, (hstop >> 3) & 0xff); + ret += stk_sensor_inb(dev, REG_HREF, &v); + v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); + msleep(10); + ret += stk_sensor_outb(dev, REG_HREF, v); +/* + * Vertical: similar arrangement (note: this is different from ov7670.c) + */ + ret += stk_sensor_outb(dev, REG_VSTART, (vstart >> 3) & 0xff); + ret += stk_sensor_outb(dev, REG_VSTOP, (vstop >> 3) & 0xff); + ret += stk_sensor_inb(dev, REG_VREF, &v); + v = (v & 0xc0) | ((vstop & 0x7) << 3) | (vstart & 0x7); + msleep(10); + ret += stk_sensor_outb(dev, REG_VREF, v); + return ret; +} + + +int stk_sensor_configure(struct stk_camera *dev) +{ + int com7; + /* + * We setup the sensor to output dummy lines in low-res modes, + * so we don't get absurdly hight framerates. + */ + unsigned dummylines; + int flip; + struct regval *rv; + + switch (dev->vsettings.mode) { + case MODE_QCIF: com7 = COM7_FMT_QCIF; + dummylines = 604; + break; + case MODE_QVGA: com7 = COM7_FMT_QVGA; + dummylines = 267; + break; + case MODE_CIF: com7 = COM7_FMT_CIF; + dummylines = 412; + break; + case MODE_VGA: com7 = COM7_FMT_VGA; + dummylines = 11; + break; + case MODE_SXGA: com7 = COM7_FMT_SXGA; + dummylines = 0; + break; + default: + pr_err("Unsupported mode %d\n", dev->vsettings.mode); + return -EFAULT; + } + switch (dev->vsettings.palette) { + case V4L2_PIX_FMT_UYVY: + com7 |= COM7_YUV; + rv = ov_fmt_uyvy; + break; + case V4L2_PIX_FMT_YUYV: + com7 |= COM7_YUV; + rv = ov_fmt_yuyv; + break; + case V4L2_PIX_FMT_RGB565: + com7 |= COM7_RGB; + rv = ov_fmt_rgbp; + break; + case V4L2_PIX_FMT_RGB565X: + com7 |= COM7_RGB; + rv = ov_fmt_rgbr; + break; + case V4L2_PIX_FMT_SBGGR8: + com7 |= COM7_PBAYER; + rv = ov_fmt_bayer; + break; + default: + pr_err("Unsupported colorspace\n"); + return -EFAULT; + } + /*FIXME sometimes the sensor go to a bad state + stk_sensor_write_regvals(dev, ov_initvals); */ + stk_sensor_outb(dev, REG_COM7, com7); + msleep(50); + stk_sensor_write_regvals(dev, rv); + flip = (dev->vsettings.vflip?MVFP_FLIP:0) + | (dev->vsettings.hflip?MVFP_MIRROR:0); + stk_sensor_outb(dev, REG_MVFP, flip); + if (dev->vsettings.palette == V4L2_PIX_FMT_SBGGR8 + && !dev->vsettings.vflip) + stk_sensor_outb(dev, REG_TSLB, 0x08); + stk_sensor_outb(dev, REG_ADVFH, dummylines >> 8); + stk_sensor_outb(dev, REG_ADVFL, dummylines & 0xff); + msleep(50); + switch (dev->vsettings.mode) { + case MODE_VGA: + if (stk_sensor_set_hw(dev, 302, 1582, 6, 486)) + pr_err("stk_sensor_set_hw failed (VGA)\n"); + break; + case MODE_SXGA: + case MODE_CIF: + case MODE_QVGA: + case MODE_QCIF: + /*FIXME These settings seem ignored by the sensor + if (stk_sensor_set_hw(dev, 220, 1500, 10, 1034)) + pr_err("stk_sensor_set_hw failed (SXGA)\n"); + */ + break; + } + msleep(10); + return 0; +} + +int stk_sensor_set_brightness(struct stk_camera *dev, int br) +{ + if (br < 0 || br > 0xff) + return -EINVAL; + stk_sensor_outb(dev, REG_AEB, max(0x00, br - 6)); + stk_sensor_outb(dev, REG_AEW, min(0xff, br + 6)); + return 0; +} + diff --git a/drivers/staging/media/deprecated/stkwebcam/stk-webcam.c b/drivers/staging/media/deprecated/stkwebcam/stk-webcam.c new file mode 100644 index 000000000..787edb3d4 --- /dev/null +++ b/drivers/staging/media/deprecated/stkwebcam/stk-webcam.c @@ -0,0 +1,1434 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * stk-webcam.c : Driver for Syntek 1125 USB webcam controller + * + * Copyright (C) 2006 Nicolas VIVIEN + * Copyright 2007-2008 Jaime Velasco Juan + * + * Some parts are inspired from cafe_ccic.c + * Copyright 2006-2007 Jonathan Corbet + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stk-webcam.h" + + +static int hflip = -1; +module_param(hflip, int, 0444); +MODULE_PARM_DESC(hflip, "Horizontal image flip (mirror). Defaults to 0"); + +static int vflip = -1; +module_param(vflip, int, 0444); +MODULE_PARM_DESC(vflip, "Vertical image flip. Defaults to 0"); + +static int debug; +module_param(debug, int, 0444); +MODULE_PARM_DESC(debug, "Debug v4l ioctls. Defaults to 0"); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Jaime Velasco Juan and Nicolas VIVIEN"); +MODULE_DESCRIPTION("Syntek DC1125 webcam driver"); + +/* Some cameras have audio interfaces, we aren't interested in those */ +static const struct usb_device_id stkwebcam_table[] = { + { USB_DEVICE_AND_INTERFACE_INFO(0x174f, 0xa311, 0xff, 0xff, 0xff) }, + { USB_DEVICE_AND_INTERFACE_INFO(0x05e1, 0x0501, 0xff, 0xff, 0xff) }, + { } +}; +MODULE_DEVICE_TABLE(usb, stkwebcam_table); + +/* + * The stk webcam laptop module is mounted upside down in some laptops :( + * + * Some background information (thanks to Hans de Goede for providing this): + * + * 1) Once upon a time the stkwebcam driver was written + * + * 2) The webcam in question was used mostly in Asus laptop models, including + * the laptop of the original author of the driver, and in these models, in + * typical Asus fashion (see the long long list for uvc cams inside v4l-utils), + * they mounted the webcam-module the wrong way up. So the hflip and vflip + * module options were given a default value of 1 (the correct value for + * upside down mounted models) + * + * 3) Years later I got a bug report from a user with a laptop with stkwebcam, + * where the module was actually mounted the right way up, and thus showed + * upside down under Linux. So now I was facing the choice of 2 options: + * + * a) Add a not-upside-down list to stkwebcam, which overrules the default. + * + * b) Do it like all the other drivers do, and make the default right for + * cams mounted the proper way and add an upside-down model list, with + * models where we need to flip-by-default. + * + * Despite knowing that going b) would cause a period of pain where we were + * building the table I opted to go for option b), since a) is just too ugly, + * and worse different from how every other driver does it leading to + * confusion in the long run. This change was made in kernel 3.6. + * + * So for any user report about upside-down images since kernel 3.6 ask them + * to provide the output of 'sudo dmidecode' so the laptop can be added in + * the table below. + */ +static const struct dmi_system_id stk_upside_down_dmi_table[] = { + { + .ident = "ASUS G1", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "G1") + } + }, { + .ident = "ASUS F3JC", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "F3JC") + } + }, + { + .ident = "T12Rg-H", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "HCL Infosystems Limited"), + DMI_MATCH(DMI_PRODUCT_NAME, "T12Rg-H") + } + }, + { + .ident = "ASUS A6VM", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "A6VM") + } + }, + { + .ident = "ASUS A6JC", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "A6JC") + } + }, + {} +}; + + +/* + * Basic stuff + */ +int stk_camera_write_reg(struct stk_camera *dev, u16 index, u8 value) +{ + struct usb_device *udev = dev->udev; + int ret; + + ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + 0x01, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + value, + index, + NULL, + 0, + 500); + if (ret < 0) + return ret; + else + return 0; +} + +int stk_camera_read_reg(struct stk_camera *dev, u16 index, u8 *value) +{ + struct usb_device *udev = dev->udev; + int ret; + + ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + 0x00, + USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0x00, + index, + &dev->read_reg_scratch, + sizeof(u8), + 500); + if (ret >= 0) + *value = dev->read_reg_scratch; + + if (ret < 0) + return ret; + else + return 0; +} + +static int stk_start_stream(struct stk_camera *dev) +{ + u8 value; + int i, ret; + u8 value_116, value_117; + + + if (!is_present(dev)) + return -ENODEV; + if (!is_memallocd(dev) || !is_initialised(dev)) { + pr_err("FIXME: Buffers are not allocated\n"); + return -EFAULT; + } + ret = usb_set_interface(dev->udev, 0, 5); + + if (ret < 0) + pr_err("usb_set_interface failed !\n"); + if (stk_sensor_wakeup(dev)) + pr_err("error awaking the sensor\n"); + + stk_camera_read_reg(dev, 0x0116, &value_116); + stk_camera_read_reg(dev, 0x0117, &value_117); + + stk_camera_write_reg(dev, 0x0116, 0x0000); + stk_camera_write_reg(dev, 0x0117, 0x0000); + + stk_camera_read_reg(dev, 0x0100, &value); + stk_camera_write_reg(dev, 0x0100, value | 0x80); + + stk_camera_write_reg(dev, 0x0116, value_116); + stk_camera_write_reg(dev, 0x0117, value_117); + for (i = 0; i < MAX_ISO_BUFS; i++) { + if (dev->isobufs[i].urb) { + ret = usb_submit_urb(dev->isobufs[i].urb, GFP_KERNEL); + atomic_inc(&dev->urbs_used); + if (ret) + return ret; + } + } + set_streaming(dev); + return 0; +} + +static int stk_stop_stream(struct stk_camera *dev) +{ + u8 value; + int i; + if (is_present(dev)) { + stk_camera_read_reg(dev, 0x0100, &value); + stk_camera_write_reg(dev, 0x0100, value & ~0x80); + if (dev->isobufs != NULL) { + for (i = 0; i < MAX_ISO_BUFS; i++) { + if (dev->isobufs[i].urb) + usb_kill_urb(dev->isobufs[i].urb); + } + } + unset_streaming(dev); + + if (usb_set_interface(dev->udev, 0, 0)) + pr_err("usb_set_interface failed !\n"); + if (stk_sensor_sleep(dev)) + pr_err("error suspending the sensor\n"); + } + return 0; +} + +/* + * This seems to be the shortest init sequence we + * must do in order to find the sensor + * Bit 5 of reg. 0x0000 here is important, when reset to 0 the sensor + * is also reset. Maybe powers down it? + * Rest of values don't make a difference + */ + +static struct regval stk1125_initvals[] = { + /*TODO: What means this sequence? */ + {0x0000, 0x24}, + {0x0100, 0x21}, + {0x0002, 0x68}, + {0x0003, 0x80}, + {0x0005, 0x00}, + {0x0007, 0x03}, + {0x000d, 0x00}, + {0x000f, 0x02}, + {0x0300, 0x12}, + {0x0350, 0x41}, + {0x0351, 0x00}, + {0x0352, 0x00}, + {0x0353, 0x00}, + {0x0018, 0x10}, + {0x0019, 0x00}, + {0x001b, 0x0e}, + {0x001c, 0x46}, + {0x0300, 0x80}, + {0x001a, 0x04}, + {0x0110, 0x00}, + {0x0111, 0x00}, + {0x0112, 0x00}, + {0x0113, 0x00}, + + {0xffff, 0xff}, +}; + + +static int stk_initialise(struct stk_camera *dev) +{ + struct regval *rv; + int ret; + if (!is_present(dev)) + return -ENODEV; + if (is_initialised(dev)) + return 0; + rv = stk1125_initvals; + while (rv->reg != 0xffff) { + ret = stk_camera_write_reg(dev, rv->reg, rv->val); + if (ret) + return ret; + rv++; + } + if (stk_sensor_init(dev) == 0) { + set_initialised(dev); + return 0; + } else + return -1; +} + +/* *********************************************** */ +/* + * This function is called as an URB transfert is complete (Isochronous pipe). + * So, the traitement is done in interrupt time, so it has be fast, not crash, + * and not stall. Neat. + */ +static void stk_isoc_handler(struct urb *urb) +{ + int i; + int ret; + int framelen; + unsigned long flags; + + unsigned char *fill = NULL; + unsigned char *iso_buf = NULL; + + struct stk_camera *dev; + struct stk_sio_buffer *fb; + + dev = (struct stk_camera *) urb->context; + + if (dev == NULL) { + pr_err("isoc_handler called with NULL device !\n"); + return; + } + + if (urb->status == -ENOENT || urb->status == -ECONNRESET + || urb->status == -ESHUTDOWN) { + atomic_dec(&dev->urbs_used); + return; + } + + spin_lock_irqsave(&dev->spinlock, flags); + + if (urb->status != -EINPROGRESS && urb->status != 0) { + pr_err("isoc_handler: urb->status == %d\n", urb->status); + goto resubmit; + } + + if (list_empty(&dev->sio_avail)) { + /*FIXME Stop streaming after a while */ + pr_err_ratelimited("isoc_handler without available buffer!\n"); + goto resubmit; + } + fb = list_first_entry(&dev->sio_avail, + struct stk_sio_buffer, list); + fill = fb->buffer + fb->v4lbuf.bytesused; + + for (i = 0; i < urb->number_of_packets; i++) { + if (urb->iso_frame_desc[i].status != 0) { + if (urb->iso_frame_desc[i].status != -EXDEV) + pr_err("Frame %d has error %d\n", + i, urb->iso_frame_desc[i].status); + continue; + } + framelen = urb->iso_frame_desc[i].actual_length; + iso_buf = urb->transfer_buffer + urb->iso_frame_desc[i].offset; + + if (framelen <= 4) + continue; /* no data */ + + /* + * we found something informational from there + * the isoc frames have to type of headers + * type1: 00 xx 00 00 or 20 xx 00 00 + * type2: 80 xx 00 00 00 00 00 00 or a0 xx 00 00 00 00 00 00 + * xx is a sequencer which has never been seen over 0x3f + * imho data written down looks like bayer, i see similarities + * after every 640 bytes + */ + if (*iso_buf & 0x80) { + framelen -= 8; + iso_buf += 8; + /* This marks a new frame */ + if (fb->v4lbuf.bytesused != 0 + && fb->v4lbuf.bytesused != dev->frame_size) { + pr_err_ratelimited("frame %d, bytesused=%d, skipping\n", + i, fb->v4lbuf.bytesused); + fb->v4lbuf.bytesused = 0; + fill = fb->buffer; + } else if (fb->v4lbuf.bytesused == dev->frame_size) { + if (list_is_singular(&dev->sio_avail)) { + /* Always reuse the last buffer */ + fb->v4lbuf.bytesused = 0; + fill = fb->buffer; + } else { + list_move_tail(dev->sio_avail.next, + &dev->sio_full); + wake_up(&dev->wait_frame); + fb = list_first_entry(&dev->sio_avail, + struct stk_sio_buffer, list); + fb->v4lbuf.bytesused = 0; + fill = fb->buffer; + } + } + } else { + framelen -= 4; + iso_buf += 4; + } + + /* Our buffer is full !!! */ + if (framelen + fb->v4lbuf.bytesused > dev->frame_size) { + pr_err_ratelimited("Frame buffer overflow, lost sync\n"); + /*FIXME Do something here? */ + continue; + } + spin_unlock_irqrestore(&dev->spinlock, flags); + memcpy(fill, iso_buf, framelen); + spin_lock_irqsave(&dev->spinlock, flags); + fill += framelen; + + /* New size of our buffer */ + fb->v4lbuf.bytesused += framelen; + } + +resubmit: + spin_unlock_irqrestore(&dev->spinlock, flags); + urb->dev = dev->udev; + ret = usb_submit_urb(urb, GFP_ATOMIC); + if (ret != 0) { + pr_err("Error (%d) re-submitting urb in stk_isoc_handler\n", + ret); + } +} + +/* -------------------------------------------- */ + +static int stk_prepare_iso(struct stk_camera *dev) +{ + void *kbuf; + int i, j; + struct urb *urb; + struct usb_device *udev; + + if (dev == NULL) + return -ENXIO; + udev = dev->udev; + + if (dev->isobufs) + pr_err("isobufs already allocated. Bad\n"); + else + dev->isobufs = kcalloc(MAX_ISO_BUFS, sizeof(*dev->isobufs), + GFP_KERNEL); + if (dev->isobufs == NULL) { + pr_err("Unable to allocate iso buffers\n"); + return -ENOMEM; + } + for (i = 0; i < MAX_ISO_BUFS; i++) { + if (dev->isobufs[i].data == NULL) { + kbuf = kzalloc(ISO_BUFFER_SIZE, GFP_KERNEL); + if (kbuf == NULL) { + pr_err("Failed to allocate iso buffer %d\n", i); + goto isobufs_out; + } + dev->isobufs[i].data = kbuf; + } else + pr_err("isobuf data already allocated\n"); + if (dev->isobufs[i].urb == NULL) { + urb = usb_alloc_urb(ISO_FRAMES_PER_DESC, GFP_KERNEL); + if (urb == NULL) + goto isobufs_out; + dev->isobufs[i].urb = urb; + } else { + pr_err("Killing URB\n"); + usb_kill_urb(dev->isobufs[i].urb); + urb = dev->isobufs[i].urb; + } + urb->interval = 1; + urb->dev = udev; + urb->pipe = usb_rcvisocpipe(udev, dev->isoc_ep); + urb->transfer_flags = URB_ISO_ASAP; + urb->transfer_buffer = dev->isobufs[i].data; + urb->transfer_buffer_length = ISO_BUFFER_SIZE; + urb->complete = stk_isoc_handler; + urb->context = dev; + urb->start_frame = 0; + urb->number_of_packets = ISO_FRAMES_PER_DESC; + + for (j = 0; j < ISO_FRAMES_PER_DESC; j++) { + urb->iso_frame_desc[j].offset = j * ISO_MAX_FRAME_SIZE; + urb->iso_frame_desc[j].length = ISO_MAX_FRAME_SIZE; + } + } + set_memallocd(dev); + return 0; + +isobufs_out: + for (i = 0; i < MAX_ISO_BUFS && dev->isobufs[i].data; i++) + kfree(dev->isobufs[i].data); + for (i = 0; i < MAX_ISO_BUFS && dev->isobufs[i].urb; i++) + usb_free_urb(dev->isobufs[i].urb); + kfree(dev->isobufs); + dev->isobufs = NULL; + return -ENOMEM; +} + +static void stk_clean_iso(struct stk_camera *dev) +{ + int i; + + if (dev == NULL || dev->isobufs == NULL) + return; + + for (i = 0; i < MAX_ISO_BUFS; i++) { + struct urb *urb; + + urb = dev->isobufs[i].urb; + if (urb) { + if (atomic_read(&dev->urbs_used) && is_present(dev)) + usb_kill_urb(urb); + usb_free_urb(urb); + } + kfree(dev->isobufs[i].data); + } + kfree(dev->isobufs); + dev->isobufs = NULL; + unset_memallocd(dev); +} + +static int stk_setup_siobuf(struct stk_camera *dev, int index) +{ + struct stk_sio_buffer *buf = dev->sio_bufs + index; + INIT_LIST_HEAD(&buf->list); + buf->v4lbuf.length = PAGE_ALIGN(dev->frame_size); + buf->buffer = vmalloc_user(buf->v4lbuf.length); + if (buf->buffer == NULL) + return -ENOMEM; + buf->mapcount = 0; + buf->dev = dev; + buf->v4lbuf.index = index; + buf->v4lbuf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + buf->v4lbuf.flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + buf->v4lbuf.field = V4L2_FIELD_NONE; + buf->v4lbuf.memory = V4L2_MEMORY_MMAP; + buf->v4lbuf.m.offset = 2*index*buf->v4lbuf.length; + return 0; +} + +static int stk_free_sio_buffers(struct stk_camera *dev) +{ + int i; + int nbufs; + unsigned long flags; + if (dev->n_sbufs == 0 || dev->sio_bufs == NULL) + return 0; + /* + * If any buffers are mapped, we cannot free them at all. + */ + for (i = 0; i < dev->n_sbufs; i++) { + if (dev->sio_bufs[i].mapcount > 0) + return -EBUSY; + } + /* + * OK, let's do it. + */ + spin_lock_irqsave(&dev->spinlock, flags); + INIT_LIST_HEAD(&dev->sio_avail); + INIT_LIST_HEAD(&dev->sio_full); + nbufs = dev->n_sbufs; + dev->n_sbufs = 0; + spin_unlock_irqrestore(&dev->spinlock, flags); + for (i = 0; i < nbufs; i++) + vfree(dev->sio_bufs[i].buffer); + kfree(dev->sio_bufs); + dev->sio_bufs = NULL; + return 0; +} + +static int stk_prepare_sio_buffers(struct stk_camera *dev, unsigned n_sbufs) +{ + int i; + if (dev->sio_bufs != NULL) + pr_err("sio_bufs already allocated\n"); + else { + dev->sio_bufs = kcalloc(n_sbufs, + sizeof(struct stk_sio_buffer), + GFP_KERNEL); + if (dev->sio_bufs == NULL) + return -ENOMEM; + for (i = 0; i < n_sbufs; i++) { + if (stk_setup_siobuf(dev, i)) + return (dev->n_sbufs > 1 ? 0 : -ENOMEM); + dev->n_sbufs = i+1; + } + } + return 0; +} + +static int stk_allocate_buffers(struct stk_camera *dev, unsigned n_sbufs) +{ + int err; + err = stk_prepare_iso(dev); + if (err) { + stk_clean_iso(dev); + return err; + } + err = stk_prepare_sio_buffers(dev, n_sbufs); + if (err) { + stk_free_sio_buffers(dev); + return err; + } + return 0; +} + +static void stk_free_buffers(struct stk_camera *dev) +{ + stk_clean_iso(dev); + stk_free_sio_buffers(dev); +} +/* -------------------------------------------- */ + +/* v4l file operations */ + +static int v4l_stk_open(struct file *fp) +{ + struct stk_camera *dev = video_drvdata(fp); + int err; + + if (dev == NULL || !is_present(dev)) + return -ENXIO; + + if (mutex_lock_interruptible(&dev->lock)) + return -ERESTARTSYS; + if (!dev->first_init) + stk_camera_write_reg(dev, 0x0, 0x24); + else + dev->first_init = 0; + + err = v4l2_fh_open(fp); + if (!err) + usb_autopm_get_interface(dev->interface); + mutex_unlock(&dev->lock); + return err; +} + +static int v4l_stk_release(struct file *fp) +{ + struct stk_camera *dev = video_drvdata(fp); + + mutex_lock(&dev->lock); + if (dev->owner == fp) { + stk_stop_stream(dev); + stk_free_buffers(dev); + stk_camera_write_reg(dev, 0x0, 0x49); /* turn off the LED */ + unset_initialised(dev); + dev->owner = NULL; + } + + usb_autopm_put_interface(dev->interface); + mutex_unlock(&dev->lock); + return v4l2_fh_release(fp); +} + +static ssize_t stk_read(struct file *fp, char __user *buf, + size_t count, loff_t *f_pos) +{ + int i; + int ret; + unsigned long flags; + struct stk_sio_buffer *sbuf; + struct stk_camera *dev = video_drvdata(fp); + + if (!is_present(dev)) + return -EIO; + if (dev->owner && (!dev->reading || dev->owner != fp)) + return -EBUSY; + dev->owner = fp; + if (!is_streaming(dev)) { + if (stk_initialise(dev) + || stk_allocate_buffers(dev, 3) + || stk_start_stream(dev)) + return -ENOMEM; + dev->reading = 1; + spin_lock_irqsave(&dev->spinlock, flags); + for (i = 0; i < dev->n_sbufs; i++) { + list_add_tail(&dev->sio_bufs[i].list, &dev->sio_avail); + dev->sio_bufs[i].v4lbuf.flags = V4L2_BUF_FLAG_QUEUED; + } + spin_unlock_irqrestore(&dev->spinlock, flags); + } + if (*f_pos == 0) { + if (fp->f_flags & O_NONBLOCK && list_empty(&dev->sio_full)) + return -EWOULDBLOCK; + ret = wait_event_interruptible(dev->wait_frame, + !list_empty(&dev->sio_full) || !is_present(dev)); + if (ret) + return ret; + if (!is_present(dev)) + return -EIO; + } + if (count + *f_pos > dev->frame_size) + count = dev->frame_size - *f_pos; + spin_lock_irqsave(&dev->spinlock, flags); + if (list_empty(&dev->sio_full)) { + spin_unlock_irqrestore(&dev->spinlock, flags); + pr_err("BUG: No siobufs ready\n"); + return 0; + } + sbuf = list_first_entry(&dev->sio_full, struct stk_sio_buffer, list); + spin_unlock_irqrestore(&dev->spinlock, flags); + + if (copy_to_user(buf, sbuf->buffer + *f_pos, count)) + return -EFAULT; + + *f_pos += count; + + if (*f_pos >= dev->frame_size) { + *f_pos = 0; + spin_lock_irqsave(&dev->spinlock, flags); + list_move_tail(&sbuf->list, &dev->sio_avail); + spin_unlock_irqrestore(&dev->spinlock, flags); + } + return count; +} + +static ssize_t v4l_stk_read(struct file *fp, char __user *buf, + size_t count, loff_t *f_pos) +{ + struct stk_camera *dev = video_drvdata(fp); + int ret; + + if (mutex_lock_interruptible(&dev->lock)) + return -ERESTARTSYS; + ret = stk_read(fp, buf, count, f_pos); + mutex_unlock(&dev->lock); + return ret; +} + +static __poll_t v4l_stk_poll(struct file *fp, poll_table *wait) +{ + struct stk_camera *dev = video_drvdata(fp); + __poll_t res = v4l2_ctrl_poll(fp, wait); + + poll_wait(fp, &dev->wait_frame, wait); + + if (!is_present(dev)) + return EPOLLERR; + + if (!list_empty(&dev->sio_full)) + return res | EPOLLIN | EPOLLRDNORM; + + return res; +} + + +static void stk_v4l_vm_open(struct vm_area_struct *vma) +{ + struct stk_sio_buffer *sbuf = vma->vm_private_data; + sbuf->mapcount++; +} +static void stk_v4l_vm_close(struct vm_area_struct *vma) +{ + struct stk_sio_buffer *sbuf = vma->vm_private_data; + sbuf->mapcount--; + if (sbuf->mapcount == 0) + sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_MAPPED; +} +static const struct vm_operations_struct stk_v4l_vm_ops = { + .open = stk_v4l_vm_open, + .close = stk_v4l_vm_close +}; + +static int v4l_stk_mmap(struct file *fp, struct vm_area_struct *vma) +{ + unsigned int i; + int ret; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + struct stk_camera *dev = video_drvdata(fp); + struct stk_sio_buffer *sbuf = NULL; + + if (!(vma->vm_flags & VM_WRITE) || !(vma->vm_flags & VM_SHARED)) + return -EINVAL; + + for (i = 0; i < dev->n_sbufs; i++) { + if (dev->sio_bufs[i].v4lbuf.m.offset == offset) { + sbuf = dev->sio_bufs + i; + break; + } + } + if (sbuf == NULL) + return -EINVAL; + ret = remap_vmalloc_range(vma, sbuf->buffer, 0); + if (ret) + return ret; + vma->vm_flags |= VM_DONTEXPAND; + vma->vm_private_data = sbuf; + vma->vm_ops = &stk_v4l_vm_ops; + sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_MAPPED; + stk_v4l_vm_open(vma); + return 0; +} + +/* v4l ioctl handlers */ + +static int stk_vidioc_querycap(struct file *filp, + void *priv, struct v4l2_capability *cap) +{ + struct stk_camera *dev = video_drvdata(filp); + + strscpy(cap->driver, "stk", sizeof(cap->driver)); + strscpy(cap->card, "stk", sizeof(cap->card)); + usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info)); + return 0; +} + +static int stk_vidioc_enum_input(struct file *filp, + void *priv, struct v4l2_input *input) +{ + if (input->index != 0) + return -EINVAL; + + strscpy(input->name, "Syntek USB Camera", sizeof(input->name)); + input->type = V4L2_INPUT_TYPE_CAMERA; + return 0; +} + + +static int stk_vidioc_g_input(struct file *filp, void *priv, unsigned int *i) +{ + *i = 0; + return 0; +} + +static int stk_vidioc_s_input(struct file *filp, void *priv, unsigned int i) +{ + return i ? -EINVAL : 0; +} + +static int stk_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct stk_camera *dev = + container_of(ctrl->handler, struct stk_camera, hdl); + + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + return stk_sensor_set_brightness(dev, ctrl->val); + case V4L2_CID_HFLIP: + if (dmi_check_system(stk_upside_down_dmi_table)) + dev->vsettings.hflip = !ctrl->val; + else + dev->vsettings.hflip = ctrl->val; + return 0; + case V4L2_CID_VFLIP: + if (dmi_check_system(stk_upside_down_dmi_table)) + dev->vsettings.vflip = !ctrl->val; + else + dev->vsettings.vflip = ctrl->val; + return 0; + default: + return -EINVAL; + } + return 0; +} + + +static int stk_vidioc_enum_fmt_vid_cap(struct file *filp, + void *priv, struct v4l2_fmtdesc *fmtd) +{ + switch (fmtd->index) { + case 0: + fmtd->pixelformat = V4L2_PIX_FMT_RGB565; + break; + case 1: + fmtd->pixelformat = V4L2_PIX_FMT_RGB565X; + break; + case 2: + fmtd->pixelformat = V4L2_PIX_FMT_UYVY; + break; + case 3: + fmtd->pixelformat = V4L2_PIX_FMT_SBGGR8; + break; + case 4: + fmtd->pixelformat = V4L2_PIX_FMT_YUYV; + break; + default: + return -EINVAL; + } + return 0; +} + +static struct stk_size { + unsigned w; + unsigned h; + enum stk_mode m; +} stk_sizes[] = { + { .w = 1280, .h = 1024, .m = MODE_SXGA, }, + { .w = 640, .h = 480, .m = MODE_VGA, }, + { .w = 352, .h = 288, .m = MODE_CIF, }, + { .w = 320, .h = 240, .m = MODE_QVGA, }, + { .w = 176, .h = 144, .m = MODE_QCIF, }, +}; + +static int stk_vidioc_g_fmt_vid_cap(struct file *filp, + void *priv, struct v4l2_format *f) +{ + struct v4l2_pix_format *pix_format = &f->fmt.pix; + struct stk_camera *dev = video_drvdata(filp); + int i; + + for (i = 0; i < ARRAY_SIZE(stk_sizes) && + stk_sizes[i].m != dev->vsettings.mode; i++) + ; + if (i == ARRAY_SIZE(stk_sizes)) { + pr_err("ERROR: mode invalid\n"); + return -EINVAL; + } + pix_format->width = stk_sizes[i].w; + pix_format->height = stk_sizes[i].h; + pix_format->field = V4L2_FIELD_NONE; + pix_format->colorspace = V4L2_COLORSPACE_SRGB; + pix_format->pixelformat = dev->vsettings.palette; + if (dev->vsettings.palette == V4L2_PIX_FMT_SBGGR8) + pix_format->bytesperline = pix_format->width; + else + pix_format->bytesperline = 2 * pix_format->width; + pix_format->sizeimage = pix_format->bytesperline + * pix_format->height; + return 0; +} + +static int stk_try_fmt_vid_cap(struct file *filp, + struct v4l2_format *fmtd, int *idx) +{ + int i; + switch (fmtd->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_RGB565X: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_SBGGR8: + break; + default: + return -EINVAL; + } + for (i = 1; i < ARRAY_SIZE(stk_sizes); i++) { + if (fmtd->fmt.pix.width > stk_sizes[i].w) + break; + } + if (i == ARRAY_SIZE(stk_sizes) + || (abs(fmtd->fmt.pix.width - stk_sizes[i-1].w) + < abs(fmtd->fmt.pix.width - stk_sizes[i].w))) { + fmtd->fmt.pix.height = stk_sizes[i-1].h; + fmtd->fmt.pix.width = stk_sizes[i-1].w; + if (idx) + *idx = i - 1; + } else { + fmtd->fmt.pix.height = stk_sizes[i].h; + fmtd->fmt.pix.width = stk_sizes[i].w; + if (idx) + *idx = i; + } + + fmtd->fmt.pix.field = V4L2_FIELD_NONE; + fmtd->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB; + if (fmtd->fmt.pix.pixelformat == V4L2_PIX_FMT_SBGGR8) + fmtd->fmt.pix.bytesperline = fmtd->fmt.pix.width; + else + fmtd->fmt.pix.bytesperline = 2 * fmtd->fmt.pix.width; + fmtd->fmt.pix.sizeimage = fmtd->fmt.pix.bytesperline + * fmtd->fmt.pix.height; + return 0; +} + +static int stk_vidioc_try_fmt_vid_cap(struct file *filp, + void *priv, struct v4l2_format *fmtd) +{ + return stk_try_fmt_vid_cap(filp, fmtd, NULL); +} + +static int stk_setup_format(struct stk_camera *dev) +{ + int i = 0; + int depth; + if (dev->vsettings.palette == V4L2_PIX_FMT_SBGGR8) + depth = 1; + else + depth = 2; + while (i < ARRAY_SIZE(stk_sizes) && + stk_sizes[i].m != dev->vsettings.mode) + i++; + if (i == ARRAY_SIZE(stk_sizes)) { + pr_err("Something is broken in %s\n", __func__); + return -EFAULT; + } + /* This registers controls some timings, not sure of what. */ + stk_camera_write_reg(dev, 0x001b, 0x0e); + if (dev->vsettings.mode == MODE_SXGA) + stk_camera_write_reg(dev, 0x001c, 0x0e); + else + stk_camera_write_reg(dev, 0x001c, 0x46); + /* + * Registers 0x0115 0x0114 are the size of each line (bytes), + * regs 0x0117 0x0116 are the height of the image. + */ + stk_camera_write_reg(dev, 0x0115, + ((stk_sizes[i].w * depth) >> 8) & 0xff); + stk_camera_write_reg(dev, 0x0114, + (stk_sizes[i].w * depth) & 0xff); + stk_camera_write_reg(dev, 0x0117, + (stk_sizes[i].h >> 8) & 0xff); + stk_camera_write_reg(dev, 0x0116, + stk_sizes[i].h & 0xff); + return stk_sensor_configure(dev); +} + +static int stk_vidioc_s_fmt_vid_cap(struct file *filp, + void *priv, struct v4l2_format *fmtd) +{ + int ret; + int idx; + struct stk_camera *dev = video_drvdata(filp); + + if (dev == NULL) + return -ENODEV; + if (!is_present(dev)) + return -ENODEV; + if (is_streaming(dev)) + return -EBUSY; + if (dev->owner) + return -EBUSY; + ret = stk_try_fmt_vid_cap(filp, fmtd, &idx); + if (ret) + return ret; + + dev->vsettings.palette = fmtd->fmt.pix.pixelformat; + stk_free_buffers(dev); + dev->frame_size = fmtd->fmt.pix.sizeimage; + dev->vsettings.mode = stk_sizes[idx].m; + + stk_initialise(dev); + return stk_setup_format(dev); +} + +static int stk_vidioc_reqbufs(struct file *filp, + void *priv, struct v4l2_requestbuffers *rb) +{ + struct stk_camera *dev = video_drvdata(filp); + + if (dev == NULL) + return -ENODEV; + if (rb->memory != V4L2_MEMORY_MMAP) + return -EINVAL; + if (is_streaming(dev) + || (dev->owner && dev->owner != filp)) + return -EBUSY; + stk_free_buffers(dev); + if (rb->count == 0) { + stk_camera_write_reg(dev, 0x0, 0x49); /* turn off the LED */ + unset_initialised(dev); + dev->owner = NULL; + return 0; + } + dev->owner = filp; + + /*FIXME If they ask for zero, we must stop streaming and free */ + if (rb->count < 3) + rb->count = 3; + /* Arbitrary limit */ + else if (rb->count > 5) + rb->count = 5; + + stk_allocate_buffers(dev, rb->count); + rb->count = dev->n_sbufs; + return 0; +} + +static int stk_vidioc_querybuf(struct file *filp, + void *priv, struct v4l2_buffer *buf) +{ + struct stk_camera *dev = video_drvdata(filp); + struct stk_sio_buffer *sbuf; + + if (buf->index >= dev->n_sbufs) + return -EINVAL; + sbuf = dev->sio_bufs + buf->index; + *buf = sbuf->v4lbuf; + return 0; +} + +static int stk_vidioc_qbuf(struct file *filp, + void *priv, struct v4l2_buffer *buf) +{ + struct stk_camera *dev = video_drvdata(filp); + struct stk_sio_buffer *sbuf; + unsigned long flags; + + if (buf->memory != V4L2_MEMORY_MMAP) + return -EINVAL; + + if (buf->index >= dev->n_sbufs) + return -EINVAL; + sbuf = dev->sio_bufs + buf->index; + if (sbuf->v4lbuf.flags & V4L2_BUF_FLAG_QUEUED) + return 0; + sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_QUEUED; + sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_DONE; + spin_lock_irqsave(&dev->spinlock, flags); + list_add_tail(&sbuf->list, &dev->sio_avail); + *buf = sbuf->v4lbuf; + spin_unlock_irqrestore(&dev->spinlock, flags); + return 0; +} + +static int stk_vidioc_dqbuf(struct file *filp, + void *priv, struct v4l2_buffer *buf) +{ + struct stk_camera *dev = video_drvdata(filp); + struct stk_sio_buffer *sbuf; + unsigned long flags; + int ret; + + if (!is_streaming(dev)) + return -EINVAL; + + if (filp->f_flags & O_NONBLOCK && list_empty(&dev->sio_full)) + return -EWOULDBLOCK; + ret = wait_event_interruptible(dev->wait_frame, + !list_empty(&dev->sio_full) || !is_present(dev)); + if (ret) + return ret; + if (!is_present(dev)) + return -EIO; + + spin_lock_irqsave(&dev->spinlock, flags); + sbuf = list_first_entry(&dev->sio_full, struct stk_sio_buffer, list); + list_del_init(&sbuf->list); + spin_unlock_irqrestore(&dev->spinlock, flags); + sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_QUEUED; + sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_DONE; + sbuf->v4lbuf.sequence = ++dev->sequence; + v4l2_buffer_set_timestamp(&sbuf->v4lbuf, ktime_get_ns()); + + *buf = sbuf->v4lbuf; + return 0; +} + +static int stk_vidioc_streamon(struct file *filp, + void *priv, enum v4l2_buf_type type) +{ + struct stk_camera *dev = video_drvdata(filp); + if (is_streaming(dev)) + return 0; + if (dev->sio_bufs == NULL) + return -EINVAL; + dev->sequence = 0; + return stk_start_stream(dev); +} + +static int stk_vidioc_streamoff(struct file *filp, + void *priv, enum v4l2_buf_type type) +{ + struct stk_camera *dev = video_drvdata(filp); + unsigned long flags; + int i; + stk_stop_stream(dev); + spin_lock_irqsave(&dev->spinlock, flags); + INIT_LIST_HEAD(&dev->sio_avail); + INIT_LIST_HEAD(&dev->sio_full); + for (i = 0; i < dev->n_sbufs; i++) { + INIT_LIST_HEAD(&dev->sio_bufs[i].list); + dev->sio_bufs[i].v4lbuf.flags = 0; + } + spin_unlock_irqrestore(&dev->spinlock, flags); + return 0; +} + + +static int stk_vidioc_g_parm(struct file *filp, + void *priv, struct v4l2_streamparm *sp) +{ + /*FIXME This is not correct */ + sp->parm.capture.timeperframe.numerator = 1; + sp->parm.capture.timeperframe.denominator = 30; + sp->parm.capture.readbuffers = 2; + return 0; +} + +static int stk_vidioc_enum_framesizes(struct file *filp, + void *priv, struct v4l2_frmsizeenum *frms) +{ + if (frms->index >= ARRAY_SIZE(stk_sizes)) + return -EINVAL; + switch (frms->pixel_format) { + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_RGB565X: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_SBGGR8: + frms->type = V4L2_FRMSIZE_TYPE_DISCRETE; + frms->discrete.width = stk_sizes[frms->index].w; + frms->discrete.height = stk_sizes[frms->index].h; + return 0; + default: return -EINVAL; + } +} + +static const struct v4l2_ctrl_ops stk_ctrl_ops = { + .s_ctrl = stk_s_ctrl, +}; + +static const struct v4l2_file_operations v4l_stk_fops = { + .owner = THIS_MODULE, + .open = v4l_stk_open, + .release = v4l_stk_release, + .read = v4l_stk_read, + .poll = v4l_stk_poll, + .mmap = v4l_stk_mmap, + .unlocked_ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops v4l_stk_ioctl_ops = { + .vidioc_querycap = stk_vidioc_querycap, + .vidioc_enum_fmt_vid_cap = stk_vidioc_enum_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = stk_vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = stk_vidioc_s_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = stk_vidioc_g_fmt_vid_cap, + .vidioc_enum_input = stk_vidioc_enum_input, + .vidioc_s_input = stk_vidioc_s_input, + .vidioc_g_input = stk_vidioc_g_input, + .vidioc_reqbufs = stk_vidioc_reqbufs, + .vidioc_querybuf = stk_vidioc_querybuf, + .vidioc_qbuf = stk_vidioc_qbuf, + .vidioc_dqbuf = stk_vidioc_dqbuf, + .vidioc_streamon = stk_vidioc_streamon, + .vidioc_streamoff = stk_vidioc_streamoff, + .vidioc_g_parm = stk_vidioc_g_parm, + .vidioc_enum_framesizes = stk_vidioc_enum_framesizes, + .vidioc_log_status = v4l2_ctrl_log_status, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static void stk_v4l_dev_release(struct video_device *vd) +{ + struct stk_camera *dev = vdev_to_camera(vd); + + if (dev->sio_bufs != NULL || dev->isobufs != NULL) + pr_err("We are leaking memory\n"); + usb_put_intf(dev->interface); + usb_put_dev(dev->udev); + + v4l2_ctrl_handler_free(&dev->hdl); + v4l2_device_unregister(&dev->v4l2_dev); + kfree(dev); +} + +static const struct video_device stk_v4l_data = { + .name = "stkwebcam", + .fops = &v4l_stk_fops, + .ioctl_ops = &v4l_stk_ioctl_ops, + .release = stk_v4l_dev_release, +}; + + +static int stk_register_video_device(struct stk_camera *dev) +{ + int err; + + dev->vdev = stk_v4l_data; + dev->vdev.lock = &dev->lock; + dev->vdev.v4l2_dev = &dev->v4l2_dev; + dev->vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING; + video_set_drvdata(&dev->vdev, dev); + err = video_register_device(&dev->vdev, VFL_TYPE_VIDEO, -1); + if (err) + pr_err("v4l registration failed\n"); + else + pr_info("Syntek USB2.0 Camera is now controlling device %s\n", + video_device_node_name(&dev->vdev)); + return err; +} + + +/* USB Stuff */ + +static int stk_camera_probe(struct usb_interface *interface, + const struct usb_device_id *id) +{ + struct v4l2_ctrl_handler *hdl; + int err = 0; + int i; + + struct stk_camera *dev = NULL; + struct usb_device *udev = interface_to_usbdev(interface); + struct usb_host_interface *iface_desc; + struct usb_endpoint_descriptor *endpoint; + + dev = kzalloc(sizeof(struct stk_camera), GFP_KERNEL); + if (dev == NULL) { + pr_err("Out of memory !\n"); + return -ENOMEM; + } + err = v4l2_device_register(&interface->dev, &dev->v4l2_dev); + if (err < 0) { + dev_err(&udev->dev, "couldn't register v4l2_device\n"); + kfree(dev); + return err; + } + hdl = &dev->hdl; + v4l2_ctrl_handler_init(hdl, 3); + v4l2_ctrl_new_std(hdl, &stk_ctrl_ops, + V4L2_CID_BRIGHTNESS, 0, 0xff, 0x1, 0x60); + v4l2_ctrl_new_std(hdl, &stk_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 1); + v4l2_ctrl_new_std(hdl, &stk_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 1); + if (hdl->error) { + err = hdl->error; + dev_err(&udev->dev, "couldn't register control\n"); + goto error; + } + dev->v4l2_dev.ctrl_handler = hdl; + + spin_lock_init(&dev->spinlock); + mutex_init(&dev->lock); + init_waitqueue_head(&dev->wait_frame); + dev->first_init = 1; /* webcam LED management */ + + dev->udev = usb_get_dev(udev); + dev->interface = interface; + usb_get_intf(interface); + + if (hflip != -1) + dev->vsettings.hflip = hflip; + else if (dmi_check_system(stk_upside_down_dmi_table)) + dev->vsettings.hflip = 1; + else + dev->vsettings.hflip = 0; + if (vflip != -1) + dev->vsettings.vflip = vflip; + else if (dmi_check_system(stk_upside_down_dmi_table)) + dev->vsettings.vflip = 1; + else + dev->vsettings.vflip = 0; + dev->n_sbufs = 0; + set_present(dev); + + /* Set up the endpoint information + * use only the first isoc-in endpoint + * for the current alternate setting */ + iface_desc = interface->cur_altsetting; + + for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) { + endpoint = &iface_desc->endpoint[i].desc; + + if (!dev->isoc_ep + && usb_endpoint_is_isoc_in(endpoint)) { + /* we found an isoc in endpoint */ + dev->isoc_ep = usb_endpoint_num(endpoint); + break; + } + } + if (!dev->isoc_ep) { + pr_err("Could not find isoc-in endpoint\n"); + err = -ENODEV; + goto error_put; + } + dev->vsettings.palette = V4L2_PIX_FMT_RGB565; + dev->vsettings.mode = MODE_VGA; + dev->frame_size = 640 * 480 * 2; + + INIT_LIST_HEAD(&dev->sio_avail); + INIT_LIST_HEAD(&dev->sio_full); + + usb_set_intfdata(interface, dev); + + err = stk_register_video_device(dev); + if (err) + goto error_put; + + return 0; + +error_put: + usb_put_intf(interface); + usb_put_dev(dev->udev); +error: + v4l2_ctrl_handler_free(hdl); + v4l2_device_unregister(&dev->v4l2_dev); + kfree(dev); + return err; +} + +static void stk_camera_disconnect(struct usb_interface *interface) +{ + struct stk_camera *dev = usb_get_intfdata(interface); + + usb_set_intfdata(interface, NULL); + unset_present(dev); + + wake_up_interruptible(&dev->wait_frame); + + pr_info("Syntek USB2.0 Camera release resources device %s\n", + video_device_node_name(&dev->vdev)); + + video_unregister_device(&dev->vdev); +} + +#ifdef CONFIG_PM +static int stk_camera_suspend(struct usb_interface *intf, pm_message_t message) +{ + struct stk_camera *dev = usb_get_intfdata(intf); + if (is_streaming(dev)) { + stk_stop_stream(dev); + /* yes, this is ugly */ + set_streaming(dev); + } + return 0; +} + +static int stk_camera_resume(struct usb_interface *intf) +{ + struct stk_camera *dev = usb_get_intfdata(intf); + if (!is_initialised(dev)) + return 0; + unset_initialised(dev); + stk_initialise(dev); + stk_camera_write_reg(dev, 0x0, 0x49); + stk_setup_format(dev); + if (is_streaming(dev)) + stk_start_stream(dev); + return 0; +} +#endif + +static struct usb_driver stk_camera_driver = { + .name = "stkwebcam", + .probe = stk_camera_probe, + .disconnect = stk_camera_disconnect, + .id_table = stkwebcam_table, +#ifdef CONFIG_PM + .suspend = stk_camera_suspend, + .resume = stk_camera_resume, +#endif +}; + +module_usb_driver(stk_camera_driver); diff --git a/drivers/staging/media/deprecated/stkwebcam/stk-webcam.h b/drivers/staging/media/deprecated/stkwebcam/stk-webcam.h new file mode 100644 index 000000000..136decffe --- /dev/null +++ b/drivers/staging/media/deprecated/stkwebcam/stk-webcam.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * stk-webcam.h : Driver for Syntek 1125 USB webcam controller + * + * Copyright (C) 2006 Nicolas VIVIEN + * Copyright 2007-2008 Jaime Velasco Juan + */ + +#ifndef STKWEBCAM_H +#define STKWEBCAM_H + +#include +#include +#include +#include + +#define DRIVER_VERSION "v0.0.1" +#define DRIVER_VERSION_NUM 0x000001 + +#define MAX_ISO_BUFS 3 +#define ISO_FRAMES_PER_DESC 16 +#define ISO_MAX_FRAME_SIZE 3 * 1024 +#define ISO_BUFFER_SIZE (ISO_FRAMES_PER_DESC * ISO_MAX_FRAME_SIZE) + +struct stk_iso_buf { + void *data; + int length; + int read; + struct urb *urb; +}; + +/* Streaming IO buffers */ +struct stk_sio_buffer { + struct v4l2_buffer v4lbuf; + char *buffer; + int mapcount; + struct stk_camera *dev; + struct list_head list; +}; + +enum stk_mode {MODE_VGA, MODE_SXGA, MODE_CIF, MODE_QVGA, MODE_QCIF}; + +struct stk_video { + enum stk_mode mode; + __u32 palette; + int hflip; + int vflip; +}; + +enum stk_status { + S_PRESENT = 1, + S_INITIALISED = 2, + S_MEMALLOCD = 4, + S_STREAMING = 8, +}; +#define is_present(dev) ((dev)->status & S_PRESENT) +#define is_initialised(dev) ((dev)->status & S_INITIALISED) +#define is_streaming(dev) ((dev)->status & S_STREAMING) +#define is_memallocd(dev) ((dev)->status & S_MEMALLOCD) +#define set_present(dev) ((dev)->status = S_PRESENT) +#define unset_present(dev) ((dev)->status &= \ + ~(S_PRESENT|S_INITIALISED|S_STREAMING)) +#define set_initialised(dev) ((dev)->status |= S_INITIALISED) +#define unset_initialised(dev) ((dev)->status &= ~S_INITIALISED) +#define set_memallocd(dev) ((dev)->status |= S_MEMALLOCD) +#define unset_memallocd(dev) ((dev)->status &= ~S_MEMALLOCD) +#define set_streaming(dev) ((dev)->status |= S_STREAMING) +#define unset_streaming(dev) ((dev)->status &= ~S_STREAMING) + +struct regval { + unsigned reg; + unsigned val; +}; + +struct stk_camera { + struct v4l2_device v4l2_dev; + struct v4l2_ctrl_handler hdl; + struct video_device vdev; + struct usb_device *udev; + struct usb_interface *interface; + int webcam_model; + struct file *owner; + struct mutex lock; + int first_init; + + u8 isoc_ep; + + /* Not sure if this is right */ + atomic_t urbs_used; + + struct stk_video vsettings; + + enum stk_status status; + + spinlock_t spinlock; + wait_queue_head_t wait_frame; + + struct stk_iso_buf *isobufs; + + int frame_size; + /* Streaming buffers */ + int reading; + unsigned int n_sbufs; + struct stk_sio_buffer *sio_bufs; + struct list_head sio_avail; + struct list_head sio_full; + unsigned sequence; + + u8 read_reg_scratch; +}; + +#define vdev_to_camera(d) container_of(d, struct stk_camera, vdev) + +int stk_camera_write_reg(struct stk_camera *, u16, u8); +int stk_camera_read_reg(struct stk_camera *, u16, u8 *); + +int stk_sensor_init(struct stk_camera *); +int stk_sensor_configure(struct stk_camera *); +int stk_sensor_sleep(struct stk_camera *dev); +int stk_sensor_wakeup(struct stk_camera *dev); +int stk_sensor_set_brightness(struct stk_camera *dev, int br); + +#endif diff --git a/drivers/staging/media/deprecated/tm6000/Kconfig b/drivers/staging/media/deprecated/tm6000/Kconfig new file mode 100644 index 000000000..73d72e49e --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/Kconfig @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_TM6000 + tristate "TV Master TM5600/6000/6010 driver (DEPRECATED)" + depends on VIDEO_DEV && I2C && INPUT && RC_CORE && USB + select VIDEO_TUNER + select MEDIA_TUNER_XC2028 + select MEDIA_TUNER_XC5000 + select VIDEOBUF_VMALLOC + help + Support for TM5600/TM6000/TM6010 USB Device + + Since these cards have no MPEG decoder onboard, they transmit + only compressed MPEG data over the usb bus, so you need + an external software decoder to watch TV on your computer. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + Say Y if you own such a device and want to use it. + +config VIDEO_TM6000_ALSA + tristate "TV Master TM5600/6000/6010 audio support" + depends on VIDEO_TM6000 && SND + select SND_PCM + help + This is a video4linux driver for direct (DMA) audio for + TM5600/TM6000/TM6010 USB Devices. + + To compile this driver as a module, choose M here: the + module will be called tm6000-alsa. + +config VIDEO_TM6000_DVB + tristate "DVB Support for tm6000 based TV cards" + depends on VIDEO_TM6000 && DVB_CORE && USB + select DVB_ZL10353 + help + This adds support for DVB cards based on the tm5600/tm6000 chip. diff --git a/drivers/staging/media/deprecated/tm6000/Makefile b/drivers/staging/media/deprecated/tm6000/Makefile new file mode 100644 index 000000000..75247a02a --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 +tm6000-y := tm6000-cards.o \ + tm6000-core.o \ + tm6000-i2c.o \ + tm6000-video.o \ + tm6000-stds.o \ + tm6000-input.o + +obj-$(CONFIG_VIDEO_TM6000) += tm6000.o +obj-$(CONFIG_VIDEO_TM6000_ALSA) += tm6000-alsa.o +obj-$(CONFIG_VIDEO_TM6000_DVB) += tm6000-dvb.o + +ccflags-y += -I $(srctree)/drivers/media/tuners +ccflags-y += -I $(srctree)/drivers/media/dvb-frontends diff --git a/drivers/staging/media/deprecated/tm6000/TODO b/drivers/staging/media/deprecated/tm6000/TODO new file mode 100644 index 000000000..ecb30a429 --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/TODO @@ -0,0 +1,7 @@ +This is one of the few drivers still not using the vb2 +framework, so this driver is now deprecated with the intent of +removing it altogether by the beginning of 2023. + +In order to keep this driver it has to be converted to vb2. +If someone is interested in doing this work, then contact the +linux-media mailinglist (https://linuxtv.org/lists.php). diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-alsa.c b/drivers/staging/media/deprecated/tm6000/tm6000-alsa.c new file mode 100644 index 000000000..a19a46770 --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-alsa.c @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +// Support for audio capture for tm5600/6000/6010 +// Copyright (c) 2007-2008 Mauro Carvalho Chehab +// +// Based on cx88-alsa.c + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + + +#include "tm6000.h" +#include "tm6000-regs.h" + +#undef dprintk + +#define dprintk(level, fmt, arg...) do { \ + if (debug >= level) \ + printk(KERN_INFO "%s/1: " fmt, chip->core->name , ## arg); \ + } while (0) + +/**************************************************************************** + Module global static vars + ****************************************************************************/ + +static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ + +static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; + +module_param_array(enable, bool, NULL, 0444); +MODULE_PARM_DESC(enable, "Enable tm6000x soundcard. default enabled."); + +module_param_array(index, int, NULL, 0444); +MODULE_PARM_DESC(index, "Index value for tm6000x capture interface(s)."); + + +/**************************************************************************** + Module macros + ****************************************************************************/ + +MODULE_DESCRIPTION("ALSA driver module for tm5600/tm6000/tm6010 based TV cards"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); +MODULE_LICENSE("GPL v2"); +static unsigned int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable debug messages"); + +/**************************************************************************** + Module specific functions + ****************************************************************************/ + +/* + * BOARD Specific: Sets audio DMA + */ + +static int _tm6000_start_audio_dma(struct snd_tm6000_card *chip) +{ + struct tm6000_core *core = chip->core; + + dprintk(1, "Starting audio DMA\n"); + + /* Enables audio */ + tm6000_set_reg_mask(core, TM6010_REQ07_RCC_ACTIVE_IF, 0x40, 0x40); + + tm6000_set_audio_bitrate(core, 48000); + + return 0; +} + +/* + * BOARD Specific: Resets audio DMA + */ +static int _tm6000_stop_audio_dma(struct snd_tm6000_card *chip) +{ + struct tm6000_core *core = chip->core; + + dprintk(1, "Stopping audio DMA\n"); + + /* Disables audio */ + tm6000_set_reg_mask(core, TM6010_REQ07_RCC_ACTIVE_IF, 0x00, 0x40); + + return 0; +} + +/**************************************************************************** + ALSA PCM Interface + ****************************************************************************/ + +/* + * Digital hardware definition + */ +#define DEFAULT_FIFO_SIZE 4096 + +static const struct snd_pcm_hardware snd_tm6000_digital_hw = { + .info = SNDRV_PCM_INFO_BATCH | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP_VALID, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + + .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_KNOT, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + .period_bytes_min = 64, + .period_bytes_max = 12544, + .periods_min = 2, + .periods_max = 98, + .buffer_bytes_max = 62720 * 8, +}; + +/* + * audio pcm capture open callback + */ +static int snd_tm6000_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_tm6000_card *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + int err; + + err = snd_pcm_hw_constraint_pow2(runtime, 0, + SNDRV_PCM_HW_PARAM_PERIODS); + if (err < 0) + goto _error; + + chip->substream = substream; + + runtime->hw = snd_tm6000_digital_hw; + snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); + + return 0; +_error: + dprintk(1, "Error opening PCM!\n"); + return err; +} + +/* + * audio close callback + */ +static int snd_tm6000_close(struct snd_pcm_substream *substream) +{ + struct snd_tm6000_card *chip = snd_pcm_substream_chip(substream); + struct tm6000_core *core = chip->core; + + if (atomic_read(&core->stream_started) > 0) { + atomic_set(&core->stream_started, 0); + schedule_work(&core->wq_trigger); + } + + return 0; +} + +static int tm6000_fillbuf(struct tm6000_core *core, char *buf, int size) +{ + struct snd_tm6000_card *chip = core->adev; + struct snd_pcm_substream *substream = chip->substream; + struct snd_pcm_runtime *runtime; + int period_elapsed = 0; + unsigned int stride, buf_pos; + int length; + + if (atomic_read(&core->stream_started) == 0) + return 0; + + if (!size || !substream) { + dprintk(1, "substream was NULL\n"); + return -EINVAL; + } + + runtime = substream->runtime; + if (!runtime || !runtime->dma_area) { + dprintk(1, "runtime was NULL\n"); + return -EINVAL; + } + + buf_pos = chip->buf_pos; + stride = runtime->frame_bits >> 3; + + if (stride == 0) { + dprintk(1, "stride is zero\n"); + return -EINVAL; + } + + length = size / stride; + if (length == 0) { + dprintk(1, "%s: length was zero\n", __func__); + return -EINVAL; + } + + dprintk(1, "Copying %d bytes at %p[%d] - buf size=%d x %d\n", size, + runtime->dma_area, buf_pos, + (unsigned int)runtime->buffer_size, stride); + + if (buf_pos + length >= runtime->buffer_size) { + unsigned int cnt = runtime->buffer_size - buf_pos; + memcpy(runtime->dma_area + buf_pos * stride, buf, cnt * stride); + memcpy(runtime->dma_area, buf + cnt * stride, + length * stride - cnt * stride); + } else + memcpy(runtime->dma_area + buf_pos * stride, buf, + length * stride); + + snd_pcm_stream_lock(substream); + + chip->buf_pos += length; + if (chip->buf_pos >= runtime->buffer_size) + chip->buf_pos -= runtime->buffer_size; + + chip->period_pos += length; + if (chip->period_pos >= runtime->period_size) { + chip->period_pos -= runtime->period_size; + period_elapsed = 1; + } + + snd_pcm_stream_unlock(substream); + + if (period_elapsed) + snd_pcm_period_elapsed(substream); + + return 0; +} + +/* + * prepare callback + */ +static int snd_tm6000_prepare(struct snd_pcm_substream *substream) +{ + struct snd_tm6000_card *chip = snd_pcm_substream_chip(substream); + + chip->buf_pos = 0; + chip->period_pos = 0; + + return 0; +} + + +/* + * trigger callback + */ +static void audio_trigger(struct work_struct *work) +{ + struct tm6000_core *core = container_of(work, struct tm6000_core, + wq_trigger); + struct snd_tm6000_card *chip = core->adev; + + if (atomic_read(&core->stream_started)) { + dprintk(1, "starting capture"); + _tm6000_start_audio_dma(chip); + } else { + dprintk(1, "stopping capture"); + _tm6000_stop_audio_dma(chip); + } +} + +static int snd_tm6000_card_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_tm6000_card *chip = snd_pcm_substream_chip(substream); + struct tm6000_core *core = chip->core; + int err = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_START: + atomic_set(&core->stream_started, 1); + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: + atomic_set(&core->stream_started, 0); + break; + default: + err = -EINVAL; + break; + } + schedule_work(&core->wq_trigger); + + return err; +} +/* + * pointer callback + */ +static snd_pcm_uframes_t snd_tm6000_pointer(struct snd_pcm_substream *substream) +{ + struct snd_tm6000_card *chip = snd_pcm_substream_chip(substream); + + return chip->buf_pos; +} + +/* + * operators + */ +static const struct snd_pcm_ops snd_tm6000_pcm_ops = { + .open = snd_tm6000_pcm_open, + .close = snd_tm6000_close, + .prepare = snd_tm6000_prepare, + .trigger = snd_tm6000_card_trigger, + .pointer = snd_tm6000_pointer, +}; + +/* + * create a PCM device + */ + +/* FIXME: Control interface - How to control volume/mute? */ + +/**************************************************************************** + Basic Flow for Sound Devices + ****************************************************************************/ + +/* + * Alsa Constructor - Component probe + */ +static int tm6000_audio_init(struct tm6000_core *dev) +{ + struct snd_card *card; + struct snd_tm6000_card *chip; + int rc; + static int devnr; + char component[14]; + struct snd_pcm *pcm; + + if (!dev) + return 0; + + if (devnr >= SNDRV_CARDS) + return -ENODEV; + + if (!enable[devnr]) + return -ENOENT; + + rc = snd_card_new(&dev->udev->dev, index[devnr], "tm6000", + THIS_MODULE, 0, &card); + if (rc < 0) { + snd_printk(KERN_ERR "cannot create card instance %d\n", devnr); + return rc; + } + strscpy(card->driver, "tm6000-alsa", sizeof(card->driver)); + strscpy(card->shortname, "TM5600/60x0", sizeof(card->shortname)); + sprintf(card->longname, "TM5600/60x0 Audio at bus %d device %d", + dev->udev->bus->busnum, dev->udev->devnum); + + sprintf(component, "USB%04x:%04x", + le16_to_cpu(dev->udev->descriptor.idVendor), + le16_to_cpu(dev->udev->descriptor.idProduct)); + snd_component_add(card, component); + + chip = kzalloc(sizeof(struct snd_tm6000_card), GFP_KERNEL); + if (!chip) { + rc = -ENOMEM; + goto error; + } + + chip->core = dev; + chip->card = card; + dev->adev = chip; + spin_lock_init(&chip->reg_lock); + + rc = snd_pcm_new(card, "TM6000 Audio", 0, 0, 1, &pcm); + if (rc < 0) + goto error_chip; + + pcm->info_flags = 0; + pcm->private_data = chip; + strscpy(pcm->name, "Trident TM5600/60x0", sizeof(pcm->name)); + + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_tm6000_pcm_ops); + snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_VMALLOC, NULL, 0, 0); + + INIT_WORK(&dev->wq_trigger, audio_trigger); + rc = snd_card_register(card); + if (rc < 0) + goto error_chip; + + dprintk(1, "Registered audio driver for %s\n", card->longname); + + return 0; + +error_chip: + kfree(chip); + dev->adev = NULL; +error: + snd_card_free(card); + return rc; +} + +static int tm6000_audio_fini(struct tm6000_core *dev) +{ + struct snd_tm6000_card *chip; + + if (!dev) + return 0; + chip = dev->adev; + + if (!chip) + return 0; + + if (!chip->card) + return 0; + + snd_card_free(chip->card); + chip->card = NULL; + kfree(chip); + dev->adev = NULL; + + return 0; +} + +static struct tm6000_ops audio_ops = { + .type = TM6000_AUDIO, + .name = "TM6000 Audio Extension", + .init = tm6000_audio_init, + .fini = tm6000_audio_fini, + .fillbuf = tm6000_fillbuf, +}; + +static int __init tm6000_alsa_register(void) +{ + return tm6000_register_extension(&audio_ops); +} + +static void __exit tm6000_alsa_unregister(void) +{ + tm6000_unregister_extension(&audio_ops); +} + +module_init(tm6000_alsa_register); +module_exit(tm6000_alsa_unregister); diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-cards.c b/drivers/staging/media/deprecated/tm6000/tm6000-cards.c new file mode 100644 index 000000000..98f4a63ad --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-cards.c @@ -0,0 +1,1397 @@ +// SPDX-License-Identifier: GPL-2.0 +// tm6000-cards.c - driver for TM5600/TM6000/TM6010 USB video capture devices +// +// Copyright (c) 2006-2007 Mauro Carvalho Chehab + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tm6000.h" +#include "tm6000-regs.h" +#include "xc2028.h" +#include "xc5000.h" + +#define TM6000_BOARD_UNKNOWN 0 +#define TM5600_BOARD_GENERIC 1 +#define TM6000_BOARD_GENERIC 2 +#define TM6010_BOARD_GENERIC 3 +#define TM5600_BOARD_10MOONS_UT821 4 +#define TM5600_BOARD_10MOONS_UT330 5 +#define TM6000_BOARD_ADSTECH_DUAL_TV 6 +#define TM6000_BOARD_FREECOM_AND_SIMILAR 7 +#define TM6000_BOARD_ADSTECH_MINI_DUAL_TV 8 +#define TM6010_BOARD_HAUPPAUGE_900H 9 +#define TM6010_BOARD_BEHOLD_WANDER 10 +#define TM6010_BOARD_BEHOLD_VOYAGER 11 +#define TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE 12 +#define TM6010_BOARD_TWINHAN_TU501 13 +#define TM6010_BOARD_BEHOLD_WANDER_LITE 14 +#define TM6010_BOARD_BEHOLD_VOYAGER_LITE 15 +#define TM5600_BOARD_TERRATEC_GRABSTER 16 + +#define is_generic(model) ((model == TM6000_BOARD_UNKNOWN) || \ + (model == TM5600_BOARD_GENERIC) || \ + (model == TM6000_BOARD_GENERIC) || \ + (model == TM6010_BOARD_GENERIC)) + +#define TM6000_MAXBOARDS 16 +static unsigned int card[] = {[0 ... (TM6000_MAXBOARDS - 1)] = UNSET }; + +module_param_array(card, int, NULL, 0444); + +static unsigned long tm6000_devused; + + +struct tm6000_board { + char *name; + char eename[16]; /* EEPROM name */ + unsigned eename_size; /* size of EEPROM name */ + unsigned eename_pos; /* Position where it appears at ROM */ + + struct tm6000_capabilities caps; + + enum tm6000_devtype type; /* variant of the chipset */ + int tuner_type; /* type of the tuner */ + int tuner_addr; /* tuner address */ + int demod_addr; /* demodulator address */ + + struct tm6000_gpio gpio; + + struct tm6000_input vinput[3]; + struct tm6000_input rinput; + + char *ir_codes; +}; + +static struct tm6000_board tm6000_boards[] = { + [TM6000_BOARD_UNKNOWN] = { + .name = "Unknown tm6000 video grabber", + .caps = { + .has_tuner = 1, + .has_eeprom = 1, + }, + .gpio = { + .tuner_reset = TM6000_GPIO_1, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM5600_BOARD_GENERIC] = { + .name = "Generic tm5600 board", + .type = TM5600, + .tuner_type = TUNER_XC2028, + .tuner_addr = 0xc2 >> 1, + .caps = { + .has_tuner = 1, + .has_eeprom = 1, + }, + .gpio = { + .tuner_reset = TM6000_GPIO_1, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6000_BOARD_GENERIC] = { + .name = "Generic tm6000 board", + .tuner_type = TUNER_XC2028, + .tuner_addr = 0xc2 >> 1, + .caps = { + .has_tuner = 1, + .has_eeprom = 1, + }, + .gpio = { + .tuner_reset = TM6000_GPIO_1, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6010_BOARD_GENERIC] = { + .name = "Generic tm6010 board", + .type = TM6010, + .tuner_type = TUNER_XC2028, + .tuner_addr = 0xc2 >> 1, + .demod_addr = 0x1e >> 1, + .caps = { + .has_tuner = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 1, + .has_remote = 1, + }, + .gpio = { + .tuner_reset = TM6010_GPIO_2, + .tuner_on = TM6010_GPIO_3, + .demod_reset = TM6010_GPIO_1, + .demod_on = TM6010_GPIO_4, + .power_led = TM6010_GPIO_7, + .dvb_led = TM6010_GPIO_5, + .ir = TM6010_GPIO_0, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_SIF1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM5600_BOARD_10MOONS_UT821] = { + .name = "10Moons UT 821", + .tuner_type = TUNER_XC2028, + .eename = { '1', '0', 'M', 'O', 'O', 'N', 'S', '5', '6', '0', '0', 0xff, 0x45, 0x5b}, + .eename_size = 14, + .eename_pos = 0x14, + .type = TM5600, + .tuner_addr = 0xc2 >> 1, + .caps = { + .has_tuner = 1, + .has_eeprom = 1, + }, + .gpio = { + .tuner_reset = TM6000_GPIO_1, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM5600_BOARD_10MOONS_UT330] = { + .name = "10Moons UT 330", + .tuner_type = TUNER_PHILIPS_FQ1216AME_MK4, + .tuner_addr = 0xc8 >> 1, + .caps = { + .has_tuner = 1, + .has_dvb = 0, + .has_zl10353 = 0, + .has_eeprom = 1, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6000_BOARD_ADSTECH_DUAL_TV] = { + .name = "ADSTECH Dual TV USB", + .tuner_type = TUNER_XC2028, + .tuner_addr = 0xc8 >> 1, + .caps = { + .has_tuner = 1, + .has_tda9874 = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 1, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6000_BOARD_FREECOM_AND_SIMILAR] = { + .name = "Freecom Hybrid Stick / Moka DVB-T Receiver Dual", + .tuner_type = TUNER_XC2028, /* has a XC3028 */ + .tuner_addr = 0xc2 >> 1, + .demod_addr = 0x1e >> 1, + .caps = { + .has_tuner = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 0, + .has_remote = 1, + }, + .gpio = { + .tuner_reset = TM6000_GPIO_4, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6000_BOARD_ADSTECH_MINI_DUAL_TV] = { + .name = "ADSTECH Mini Dual TV USB", + .tuner_type = TUNER_XC2028, /* has a XC3028 */ + .tuner_addr = 0xc8 >> 1, + .demod_addr = 0x1e >> 1, + .caps = { + .has_tuner = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 0, + }, + .gpio = { + .tuner_reset = TM6000_GPIO_4, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6010_BOARD_HAUPPAUGE_900H] = { + .name = "Hauppauge WinTV HVR-900H / WinTV USB2-Stick", + .eename = { 'H', 0, 'V', 0, 'R', 0, '9', 0, '0', 0, '0', 0, 'H', 0 }, + .eename_size = 14, + .eename_pos = 0x42, + .tuner_type = TUNER_XC2028, /* has a XC3028 */ + .tuner_addr = 0xc2 >> 1, + .demod_addr = 0x1e >> 1, + .type = TM6010, + .ir_codes = RC_MAP_HAUPPAUGE, + .caps = { + .has_tuner = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 1, + .has_remote = 1, + }, + .gpio = { + .tuner_reset = TM6010_GPIO_2, + .tuner_on = TM6010_GPIO_3, + .demod_reset = TM6010_GPIO_1, + .demod_on = TM6010_GPIO_4, + .power_led = TM6010_GPIO_7, + .dvb_led = TM6010_GPIO_5, + .ir = TM6010_GPIO_0, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_SIF1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6010_BOARD_BEHOLD_WANDER] = { + .name = "Beholder Wander DVB-T/TV/FM USB2.0", + .tuner_type = TUNER_XC5000, + .tuner_addr = 0xc2 >> 1, + .demod_addr = 0x1e >> 1, + .type = TM6010, + .caps = { + .has_tuner = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 1, + .has_remote = 1, + .has_radio = 1, + }, + .gpio = { + .tuner_reset = TM6010_GPIO_0, + .demod_reset = TM6010_GPIO_1, + .power_led = TM6010_GPIO_6, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_SIF1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + .rinput = { + .type = TM6000_INPUT_RADIO, + .amux = TM6000_AMUX_ADC1, + }, + }, + [TM6010_BOARD_BEHOLD_VOYAGER] = { + .name = "Beholder Voyager TV/FM USB2.0", + .tuner_type = TUNER_XC5000, + .tuner_addr = 0xc2 >> 1, + .type = TM6010, + .caps = { + .has_tuner = 1, + .has_dvb = 0, + .has_zl10353 = 0, + .has_eeprom = 1, + .has_remote = 1, + .has_radio = 1, + }, + .gpio = { + .tuner_reset = TM6010_GPIO_0, + .power_led = TM6010_GPIO_6, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_SIF1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + .rinput = { + .type = TM6000_INPUT_RADIO, + .amux = TM6000_AMUX_ADC1, + }, + }, + [TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE] = { + .name = "Terratec Cinergy Hybrid XE / Cinergy Hybrid-Stick", + .tuner_type = TUNER_XC2028, /* has a XC3028 */ + .tuner_addr = 0xc2 >> 1, + .demod_addr = 0x1e >> 1, + .type = TM6010, + .caps = { + .has_tuner = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 1, + .has_remote = 1, + .has_radio = 1, + }, + .gpio = { + .tuner_reset = TM6010_GPIO_2, + .tuner_on = TM6010_GPIO_3, + .demod_reset = TM6010_GPIO_1, + .demod_on = TM6010_GPIO_4, + .power_led = TM6010_GPIO_7, + .dvb_led = TM6010_GPIO_5, + .ir = TM6010_GPIO_0, + }, + .ir_codes = RC_MAP_NEC_TERRATEC_CINERGY_XS, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_SIF1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + .rinput = { + .type = TM6000_INPUT_RADIO, + .amux = TM6000_AMUX_SIF1, + }, + }, + [TM5600_BOARD_TERRATEC_GRABSTER] = { + .name = "Terratec Grabster AV 150/250 MX", + .type = TM5600, + .tuner_type = TUNER_ABSENT, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_ADC1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6010_BOARD_TWINHAN_TU501] = { + .name = "Twinhan TU501(704D1)", + .tuner_type = TUNER_XC2028, /* has a XC3028 */ + .tuner_addr = 0xc2 >> 1, + .demod_addr = 0x1e >> 1, + .type = TM6010, + .caps = { + .has_tuner = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 1, + .has_remote = 1, + }, + .gpio = { + .tuner_reset = TM6010_GPIO_2, + .tuner_on = TM6010_GPIO_3, + .demod_reset = TM6010_GPIO_1, + .demod_on = TM6010_GPIO_4, + .power_led = TM6010_GPIO_7, + .dvb_led = TM6010_GPIO_5, + .ir = TM6010_GPIO_0, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_SIF1, + }, { + .type = TM6000_INPUT_COMPOSITE1, + .vmux = TM6000_VMUX_VIDEO_A, + .amux = TM6000_AMUX_ADC2, + }, { + .type = TM6000_INPUT_SVIDEO, + .vmux = TM6000_VMUX_VIDEO_AB, + .amux = TM6000_AMUX_ADC2, + }, + }, + }, + [TM6010_BOARD_BEHOLD_WANDER_LITE] = { + .name = "Beholder Wander Lite DVB-T/TV/FM USB2.0", + .tuner_type = TUNER_XC5000, + .tuner_addr = 0xc2 >> 1, + .demod_addr = 0x1e >> 1, + .type = TM6010, + .caps = { + .has_tuner = 1, + .has_dvb = 1, + .has_zl10353 = 1, + .has_eeprom = 1, + .has_remote = 0, + .has_radio = 1, + }, + .gpio = { + .tuner_reset = TM6010_GPIO_0, + .demod_reset = TM6010_GPIO_1, + .power_led = TM6010_GPIO_6, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_SIF1, + }, + }, + .rinput = { + .type = TM6000_INPUT_RADIO, + .amux = TM6000_AMUX_ADC1, + }, + }, + [TM6010_BOARD_BEHOLD_VOYAGER_LITE] = { + .name = "Beholder Voyager Lite TV/FM USB2.0", + .tuner_type = TUNER_XC5000, + .tuner_addr = 0xc2 >> 1, + .type = TM6010, + .caps = { + .has_tuner = 1, + .has_dvb = 0, + .has_zl10353 = 0, + .has_eeprom = 1, + .has_remote = 0, + .has_radio = 1, + }, + .gpio = { + .tuner_reset = TM6010_GPIO_0, + .power_led = TM6010_GPIO_6, + }, + .vinput = { { + .type = TM6000_INPUT_TV, + .vmux = TM6000_VMUX_VIDEO_B, + .amux = TM6000_AMUX_SIF1, + }, + }, + .rinput = { + .type = TM6000_INPUT_RADIO, + .amux = TM6000_AMUX_ADC1, + }, + }, +}; + +/* table of devices that work with this driver */ +static const struct usb_device_id tm6000_id_table[] = { + { USB_DEVICE(0x6000, 0x0001), .driver_info = TM5600_BOARD_GENERIC }, + { USB_DEVICE(0x6000, 0x0002), .driver_info = TM6010_BOARD_GENERIC }, + { USB_DEVICE(0x06e1, 0xf332), .driver_info = TM6000_BOARD_ADSTECH_DUAL_TV }, + { USB_DEVICE(0x14aa, 0x0620), .driver_info = TM6000_BOARD_FREECOM_AND_SIMILAR }, + { USB_DEVICE(0x06e1, 0xb339), .driver_info = TM6000_BOARD_ADSTECH_MINI_DUAL_TV }, + { USB_DEVICE(0x2040, 0x6600), .driver_info = TM6010_BOARD_HAUPPAUGE_900H }, + { USB_DEVICE(0x2040, 0x6601), .driver_info = TM6010_BOARD_HAUPPAUGE_900H }, + { USB_DEVICE(0x2040, 0x6610), .driver_info = TM6010_BOARD_HAUPPAUGE_900H }, + { USB_DEVICE(0x2040, 0x6611), .driver_info = TM6010_BOARD_HAUPPAUGE_900H }, + { USB_DEVICE(0x6000, 0xdec0), .driver_info = TM6010_BOARD_BEHOLD_WANDER }, + { USB_DEVICE(0x6000, 0xdec1), .driver_info = TM6010_BOARD_BEHOLD_VOYAGER }, + { USB_DEVICE(0x0ccd, 0x0086), .driver_info = TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE }, + { USB_DEVICE(0x0ccd, 0x00A5), .driver_info = TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE }, + { USB_DEVICE(0x0ccd, 0x0079), .driver_info = TM5600_BOARD_TERRATEC_GRABSTER }, + { USB_DEVICE(0x13d3, 0x3240), .driver_info = TM6010_BOARD_TWINHAN_TU501 }, + { USB_DEVICE(0x13d3, 0x3241), .driver_info = TM6010_BOARD_TWINHAN_TU501 }, + { USB_DEVICE(0x13d3, 0x3243), .driver_info = TM6010_BOARD_TWINHAN_TU501 }, + { USB_DEVICE(0x13d3, 0x3264), .driver_info = TM6010_BOARD_TWINHAN_TU501 }, + { USB_DEVICE(0x6000, 0xdec2), .driver_info = TM6010_BOARD_BEHOLD_WANDER_LITE }, + { USB_DEVICE(0x6000, 0xdec3), .driver_info = TM6010_BOARD_BEHOLD_VOYAGER_LITE }, + { } +}; +MODULE_DEVICE_TABLE(usb, tm6000_id_table); + +/* Control power led for show some activity */ +void tm6000_flash_led(struct tm6000_core *dev, u8 state) +{ + /* Power LED unconfigured */ + if (!dev->gpio.power_led) + return; + + /* ON Power LED */ + if (state) { + switch (dev->model) { + case TM6010_BOARD_HAUPPAUGE_900H: + case TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE: + case TM6010_BOARD_TWINHAN_TU501: + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.power_led, 0x00); + break; + case TM6010_BOARD_BEHOLD_WANDER: + case TM6010_BOARD_BEHOLD_VOYAGER: + case TM6010_BOARD_BEHOLD_WANDER_LITE: + case TM6010_BOARD_BEHOLD_VOYAGER_LITE: + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.power_led, 0x01); + break; + } + } + /* OFF Power LED */ + else { + switch (dev->model) { + case TM6010_BOARD_HAUPPAUGE_900H: + case TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE: + case TM6010_BOARD_TWINHAN_TU501: + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.power_led, 0x01); + break; + case TM6010_BOARD_BEHOLD_WANDER: + case TM6010_BOARD_BEHOLD_VOYAGER: + case TM6010_BOARD_BEHOLD_WANDER_LITE: + case TM6010_BOARD_BEHOLD_VOYAGER_LITE: + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.power_led, 0x00); + break; + } + } +} + +/* Tuner callback to provide the proper gpio changes needed for xc5000 */ +int tm6000_xc5000_callback(void *ptr, int component, int command, int arg) +{ + int rc = 0; + struct tm6000_core *dev = ptr; + + if (dev->tuner_type != TUNER_XC5000) + return 0; + + switch (command) { + case XC5000_TUNER_RESET: + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x01); + msleep(15); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x00); + msleep(15); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x01); + break; + } + return rc; +} +EXPORT_SYMBOL_GPL(tm6000_xc5000_callback); + +/* Tuner callback to provide the proper gpio changes needed for xc2028 */ + +int tm6000_tuner_callback(void *ptr, int component, int command, int arg) +{ + int rc = 0; + struct tm6000_core *dev = ptr; + + if (dev->tuner_type != TUNER_XC2028) + return 0; + + switch (command) { + case XC2028_RESET_CLK: + tm6000_ir_wait(dev, 0); + + tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, + 0x02, arg); + msleep(10); + rc = tm6000_i2c_reset(dev, 10); + break; + case XC2028_TUNER_RESET: + /* Reset codes during load firmware */ + switch (arg) { + case 0: + /* newer tuner can faster reset */ + switch (dev->model) { + case TM5600_BOARD_10MOONS_UT821: + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x01); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + 0x300, 0x01); + msleep(10); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x00); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + 0x300, 0x00); + msleep(10); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x01); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + 0x300, 0x01); + break; + case TM6010_BOARD_HAUPPAUGE_900H: + case TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE: + case TM6010_BOARD_TWINHAN_TU501: + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x01); + msleep(60); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x00); + msleep(75); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x01); + msleep(60); + break; + default: + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x00); + msleep(130); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x01); + msleep(130); + break; + } + + tm6000_ir_wait(dev, 1); + break; + case 1: + tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, + 0x02, 0x01); + msleep(10); + break; + case 2: + rc = tm6000_i2c_reset(dev, 100); + break; + } + break; + case XC2028_I2C_FLUSH: + tm6000_set_reg(dev, REQ_50_SET_START, 0, 0); + tm6000_set_reg(dev, REQ_51_SET_STOP, 0, 0); + break; + } + return rc; +} +EXPORT_SYMBOL_GPL(tm6000_tuner_callback); + +int tm6000_cards_setup(struct tm6000_core *dev) +{ + /* + * Board-specific initialization sequence. Handles all GPIO + * initialization sequences that are board-specific. + * Up to now, all found devices use GPIO1 and GPIO4 at the same way. + * Probably, they're all based on some reference device. Due to that, + * there's a common routine at the end to handle those GPIO's. Devices + * that use different pinups or init sequences can just return at + * the board-specific session. + */ + switch (dev->model) { + case TM6010_BOARD_HAUPPAUGE_900H: + case TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE: + case TM6010_BOARD_TWINHAN_TU501: + case TM6010_BOARD_GENERIC: + /* Turn xceive 3028 on */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.tuner_on, 0x01); + msleep(15); + /* Turn zarlink zl10353 on */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.demod_on, 0x00); + msleep(15); + /* Reset zarlink zl10353 */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.demod_reset, 0x00); + msleep(50); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.demod_reset, 0x01); + msleep(15); + /* Turn zarlink zl10353 off */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.demod_on, 0x01); + msleep(15); + /* ir ? */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.ir, 0x01); + msleep(15); + /* Power led on (blue) */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.power_led, 0x00); + msleep(15); + /* DVB led off (orange) */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.dvb_led, 0x01); + msleep(15); + /* Turn zarlink zl10353 on */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.demod_on, 0x00); + msleep(15); + break; + case TM6010_BOARD_BEHOLD_WANDER: + case TM6010_BOARD_BEHOLD_WANDER_LITE: + /* Power led on (blue) */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.power_led, 0x01); + msleep(15); + /* Reset zarlink zl10353 */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.demod_reset, 0x00); + msleep(50); + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.demod_reset, 0x01); + msleep(15); + break; + case TM6010_BOARD_BEHOLD_VOYAGER: + case TM6010_BOARD_BEHOLD_VOYAGER_LITE: + /* Power led on (blue) */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, dev->gpio.power_led, 0x01); + msleep(15); + break; + default: + break; + } + + /* + * Default initialization. Most of the devices seem to use GPIO1 + * and GPIO4.on the same way, so, this handles the common sequence + * used by most devices. + * If a device uses a different sequence or different GPIO pins for + * reset, just add the code at the board-specific part + */ + + if (dev->gpio.tuner_reset) { + int rc; + int i; + + for (i = 0; i < 2; i++) { + rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x00); + if (rc < 0) { + printk(KERN_ERR "Error %i doing tuner reset\n", rc); + return rc; + } + + msleep(10); /* Just to be conservative */ + rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.tuner_reset, 0x01); + if (rc < 0) { + printk(KERN_ERR "Error %i doing tuner reset\n", rc); + return rc; + } + } + } else { + printk(KERN_ERR "Tuner reset is not configured\n"); + return -1; + } + + msleep(50); + + return 0; +}; + +static void tm6000_config_tuner(struct tm6000_core *dev) +{ + struct tuner_setup tun_setup; + + /* Load tuner module */ + v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, + "tuner", dev->tuner_addr, NULL); + + memset(&tun_setup, 0, sizeof(tun_setup)); + tun_setup.type = dev->tuner_type; + tun_setup.addr = dev->tuner_addr; + + tun_setup.mode_mask = 0; + if (dev->caps.has_tuner) + tun_setup.mode_mask |= (T_ANALOG_TV | T_RADIO); + + switch (dev->tuner_type) { + case TUNER_XC2028: + tun_setup.tuner_callback = tm6000_tuner_callback; + break; + case TUNER_XC5000: + tun_setup.tuner_callback = tm6000_xc5000_callback; + break; + } + + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_type_addr, &tun_setup); + + switch (dev->tuner_type) { + case TUNER_XC2028: { + struct v4l2_priv_tun_config xc2028_cfg; + struct xc2028_ctrl ctl; + + memset(&xc2028_cfg, 0, sizeof(xc2028_cfg)); + memset(&ctl, 0, sizeof(ctl)); + + ctl.demod = XC3028_FE_ZARLINK456; + + xc2028_cfg.tuner = TUNER_XC2028; + xc2028_cfg.priv = &ctl; + + switch (dev->model) { + case TM6010_BOARD_HAUPPAUGE_900H: + case TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE: + case TM6010_BOARD_TWINHAN_TU501: + ctl.max_len = 80; + ctl.fname = "xc3028L-v36.fw"; + break; + default: + if (dev->dev_type == TM6010) + ctl.fname = "xc3028-v27.fw"; + else + ctl.fname = "xc3028-v24.fw"; + } + + printk(KERN_INFO "Setting firmware parameters for xc2028\n"); + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_config, + &xc2028_cfg); + + } + break; + case TUNER_XC5000: + { + struct v4l2_priv_tun_config xc5000_cfg; + struct xc5000_config ctl = { + .i2c_address = dev->tuner_addr, + .if_khz = 4570, + .radio_input = XC5000_RADIO_FM1_MONO, + }; + + xc5000_cfg.tuner = TUNER_XC5000; + xc5000_cfg.priv = &ctl; + + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_config, + &xc5000_cfg); + } + break; + default: + printk(KERN_INFO "Unknown tuner type. Tuner is not configured.\n"); + break; + } +} + +static int fill_board_specific_data(struct tm6000_core *dev) +{ + int rc; + + dev->dev_type = tm6000_boards[dev->model].type; + dev->tuner_type = tm6000_boards[dev->model].tuner_type; + dev->tuner_addr = tm6000_boards[dev->model].tuner_addr; + + dev->gpio = tm6000_boards[dev->model].gpio; + + dev->ir_codes = tm6000_boards[dev->model].ir_codes; + + dev->demod_addr = tm6000_boards[dev->model].demod_addr; + + dev->caps = tm6000_boards[dev->model].caps; + + dev->vinput[0] = tm6000_boards[dev->model].vinput[0]; + dev->vinput[1] = tm6000_boards[dev->model].vinput[1]; + dev->vinput[2] = tm6000_boards[dev->model].vinput[2]; + dev->rinput = tm6000_boards[dev->model].rinput; + + /* setup per-model quirks */ + switch (dev->model) { + case TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE: + case TM6010_BOARD_HAUPPAUGE_900H: + dev->quirks |= TM6000_QUIRK_NO_USB_DELAY; + break; + + default: + break; + } + + /* initialize hardware */ + rc = tm6000_init(dev); + if (rc < 0) + return rc; + + return v4l2_device_register(&dev->udev->dev, &dev->v4l2_dev); +} + + +static void use_alternative_detection_method(struct tm6000_core *dev) +{ + int i, model = -1; + + if (!dev->eedata_size) + return; + + for (i = 0; i < ARRAY_SIZE(tm6000_boards); i++) { + if (!tm6000_boards[i].eename_size) + continue; + if (dev->eedata_size < tm6000_boards[i].eename_pos + + tm6000_boards[i].eename_size) + continue; + + if (!memcmp(&dev->eedata[tm6000_boards[i].eename_pos], + tm6000_boards[i].eename, + tm6000_boards[i].eename_size)) { + model = i; + break; + } + } + if (model < 0) { + printk(KERN_INFO "Device has eeprom but is currently unknown\n"); + return; + } + + dev->model = model; + + printk(KERN_INFO "Device identified via eeprom as %s (type = %d)\n", + tm6000_boards[model].name, model); +} + +#if defined(CONFIG_MODULES) && defined(MODULE) +static void request_module_async(struct work_struct *work) +{ + struct tm6000_core *dev = container_of(work, struct tm6000_core, + request_module_wk); + + request_module("tm6000-alsa"); + + if (dev->caps.has_dvb) + request_module("tm6000-dvb"); +} + +static void request_modules(struct tm6000_core *dev) +{ + INIT_WORK(&dev->request_module_wk, request_module_async); + schedule_work(&dev->request_module_wk); +} + +static void flush_request_modules(struct tm6000_core *dev) +{ + flush_work(&dev->request_module_wk); +} +#else +#define request_modules(dev) +#define flush_request_modules(dev) +#endif /* CONFIG_MODULES */ + +static int tm6000_init_dev(struct tm6000_core *dev) +{ + struct v4l2_frequency f; + int rc = 0; + + mutex_init(&dev->lock); + mutex_lock(&dev->lock); + + if (!is_generic(dev->model)) { + rc = fill_board_specific_data(dev); + if (rc < 0) + goto err; + + /* register i2c bus */ + rc = tm6000_i2c_register(dev); + if (rc < 0) + goto err; + } else { + /* register i2c bus */ + rc = tm6000_i2c_register(dev); + if (rc < 0) + goto err; + + use_alternative_detection_method(dev); + + rc = fill_board_specific_data(dev); + if (rc < 0) + goto err; + } + + /* Default values for STD and resolutions */ + dev->width = 720; + dev->height = 480; + dev->norm = V4L2_STD_NTSC_M; + + /* Configure tuner */ + tm6000_config_tuner(dev); + + /* Set video standard */ + v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_std, dev->norm); + + /* Set tuner frequency - also loads firmware on xc2028/xc3028 */ + f.tuner = 0; + f.type = V4L2_TUNER_ANALOG_TV; + f.frequency = 3092; /* 193.25 MHz */ + dev->freq = f.frequency; + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f); + + if (dev->caps.has_tda9874) + v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap, + "tvaudio", I2C_ADDR_TDA9874, NULL); + + /* register and initialize V4L2 */ + rc = tm6000_v4l2_register(dev); + if (rc < 0) + goto err; + + tm6000_add_into_devlist(dev); + tm6000_init_extension(dev); + + tm6000_ir_init(dev); + + request_modules(dev); + + mutex_unlock(&dev->lock); + return 0; + +err: + mutex_unlock(&dev->lock); + return rc; +} + +/* high bandwidth multiplier, as encoded in highspeed endpoint descriptors */ +#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) + +static void get_max_endpoint(struct usb_device *udev, + struct usb_host_interface *alt, + char *msgtype, + struct usb_host_endpoint *curr_e, + struct tm6000_endpoint *tm_ep) +{ + u16 tmp = le16_to_cpu(curr_e->desc.wMaxPacketSize); + unsigned int size = tmp & 0x7ff; + + if (udev->speed == USB_SPEED_HIGH) + size = size * hb_mult(tmp); + + if (size > tm_ep->maxsize) { + tm_ep->endp = curr_e; + tm_ep->maxsize = size; + tm_ep->bInterfaceNumber = alt->desc.bInterfaceNumber; + tm_ep->bAlternateSetting = alt->desc.bAlternateSetting; + + printk(KERN_INFO "tm6000: %s endpoint: 0x%02x (max size=%u bytes)\n", + msgtype, curr_e->desc.bEndpointAddress, + size); + } +} + +/* + * tm6000_usb_probe() + * checks for supported devices + */ +static int tm6000_usb_probe(struct usb_interface *interface, + const struct usb_device_id *id) +{ + struct usb_device *usbdev; + struct tm6000_core *dev; + int i, rc; + int nr = 0; + char *speed; + + usbdev = usb_get_dev(interface_to_usbdev(interface)); + + /* Selects the proper interface */ + rc = usb_set_interface(usbdev, 0, 1); + if (rc < 0) + goto report_failure; + + /* Check to see next free device and mark as used */ + nr = find_first_zero_bit(&tm6000_devused, TM6000_MAXBOARDS); + if (nr >= TM6000_MAXBOARDS) { + printk(KERN_ERR "tm6000: Supports only %i tm60xx boards.\n", TM6000_MAXBOARDS); + rc = -ENOMEM; + goto put_device; + } + + /* Create and initialize dev struct */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + rc = -ENOMEM; + goto put_device; + } + spin_lock_init(&dev->slock); + mutex_init(&dev->usb_lock); + + /* Increment usage count */ + set_bit(nr, &tm6000_devused); + snprintf(dev->name, 29, "tm6000 #%d", nr); + + dev->model = id->driver_info; + if (card[nr] < ARRAY_SIZE(tm6000_boards)) + dev->model = card[nr]; + + dev->udev = usbdev; + dev->devno = nr; + + switch (usbdev->speed) { + case USB_SPEED_LOW: + speed = "1.5"; + break; + case USB_SPEED_UNKNOWN: + case USB_SPEED_FULL: + speed = "12"; + break; + case USB_SPEED_HIGH: + speed = "480"; + break; + default: + speed = "unknown"; + } + + /* Get endpoints */ + for (i = 0; i < interface->num_altsetting; i++) { + int ep; + + for (ep = 0; ep < interface->altsetting[i].desc.bNumEndpoints; ep++) { + struct usb_host_endpoint *e; + int dir_out; + + e = &interface->altsetting[i].endpoint[ep]; + + dir_out = ((e->desc.bEndpointAddress & + USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT); + + printk(KERN_INFO "tm6000: alt %d, interface %i, class %i\n", + i, + interface->altsetting[i].desc.bInterfaceNumber, + interface->altsetting[i].desc.bInterfaceClass); + + switch (e->desc.bmAttributes) { + case USB_ENDPOINT_XFER_BULK: + if (!dir_out) { + get_max_endpoint(usbdev, + &interface->altsetting[i], + "Bulk IN", e, + &dev->bulk_in); + } else { + get_max_endpoint(usbdev, + &interface->altsetting[i], + "Bulk OUT", e, + &dev->bulk_out); + } + break; + case USB_ENDPOINT_XFER_ISOC: + if (!dir_out) { + get_max_endpoint(usbdev, + &interface->altsetting[i], + "ISOC IN", e, + &dev->isoc_in); + } else { + get_max_endpoint(usbdev, + &interface->altsetting[i], + "ISOC OUT", e, + &dev->isoc_out); + } + break; + case USB_ENDPOINT_XFER_INT: + if (!dir_out) { + get_max_endpoint(usbdev, + &interface->altsetting[i], + "INT IN", e, + &dev->int_in); + } else { + get_max_endpoint(usbdev, + &interface->altsetting[i], + "INT OUT", e, + &dev->int_out); + } + break; + } + } + } + + + printk(KERN_INFO "tm6000: New video device @ %s Mbps (%04x:%04x, ifnum %d)\n", + speed, + le16_to_cpu(dev->udev->descriptor.idVendor), + le16_to_cpu(dev->udev->descriptor.idProduct), + interface->altsetting->desc.bInterfaceNumber); + +/* check if the the device has the iso in endpoint at the correct place */ + if (!dev->isoc_in.endp) { + printk(KERN_ERR "tm6000: probing error: no IN ISOC endpoint!\n"); + rc = -ENODEV; + goto free_device; + } + + /* save our data pointer in this interface device */ + usb_set_intfdata(interface, dev); + + printk(KERN_INFO "tm6000: Found %s\n", tm6000_boards[dev->model].name); + + rc = tm6000_init_dev(dev); + if (rc < 0) + goto free_device; + + return 0; + +free_device: + kfree(dev); +report_failure: + printk(KERN_ERR "tm6000: Error %d while registering\n", rc); + + clear_bit(nr, &tm6000_devused); +put_device: + usb_put_dev(usbdev); + return rc; +} + +/* + * tm6000_usb_disconnect() + * called when the device gets disconnected + * video device will be unregistered on v4l2_close in case it is still open + */ +static void tm6000_usb_disconnect(struct usb_interface *interface) +{ + struct tm6000_core *dev = usb_get_intfdata(interface); + usb_set_intfdata(interface, NULL); + + if (!dev) + return; + + printk(KERN_INFO "tm6000: disconnecting %s\n", dev->name); + + flush_request_modules(dev); + + tm6000_ir_fini(dev); + + if (dev->gpio.power_led) { + switch (dev->model) { + case TM6010_BOARD_HAUPPAUGE_900H: + case TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE: + case TM6010_BOARD_TWINHAN_TU501: + /* Power led off */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.power_led, 0x01); + msleep(15); + break; + case TM6010_BOARD_BEHOLD_WANDER: + case TM6010_BOARD_BEHOLD_VOYAGER: + case TM6010_BOARD_BEHOLD_WANDER_LITE: + case TM6010_BOARD_BEHOLD_VOYAGER_LITE: + /* Power led off */ + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.power_led, 0x00); + msleep(15); + break; + } + } + tm6000_v4l2_unregister(dev); + + tm6000_i2c_unregister(dev); + + v4l2_device_unregister(&dev->v4l2_dev); + + dev->state |= DEV_DISCONNECTED; + + usb_put_dev(dev->udev); + + tm6000_close_extension(dev); + tm6000_remove_from_devlist(dev); + + clear_bit(dev->devno, &tm6000_devused); + kfree(dev); +} + +static struct usb_driver tm6000_usb_driver = { + .name = "tm6000", + .probe = tm6000_usb_probe, + .disconnect = tm6000_usb_disconnect, + .id_table = tm6000_id_table, +}; + +module_usb_driver(tm6000_usb_driver); + +MODULE_DESCRIPTION("Trident TVMaster TM5600/TM6000/TM6010 USB2 adapter"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-core.c b/drivers/staging/media/deprecated/tm6000/tm6000-core.c new file mode 100644 index 000000000..5c8cbc5d6 --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-core.c @@ -0,0 +1,916 @@ +// SPDX-License-Identifier: GPL-2.0 +// tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices +// +// Copyright (c) 2006-2007 Mauro Carvalho Chehab +// +// Copyright (c) 2007 Michel Ludwig +// - DVB-T support + +#include +#include +#include +#include +#include +#include "tm6000.h" +#include "tm6000-regs.h" +#include +#include + +#define USB_TIMEOUT (5 * HZ) /* ms */ + +int tm6000_read_write_usb(struct tm6000_core *dev, u8 req_type, u8 req, + u16 value, u16 index, u8 *buf, u16 len) +{ + int ret, i; + unsigned int pipe; + u8 *data = NULL; + int delay = 5000; + + if (len) { + data = kzalloc(len, GFP_KERNEL); + if (!data) + return -ENOMEM; + } + + mutex_lock(&dev->usb_lock); + + if (req_type & USB_DIR_IN) + pipe = usb_rcvctrlpipe(dev->udev, 0); + else { + pipe = usb_sndctrlpipe(dev->udev, 0); + memcpy(data, buf, len); + } + + if (tm6000_debug & V4L2_DEBUG_I2C) { + printk(KERN_DEBUG "(dev %p, pipe %08x): ", dev->udev, pipe); + + printk(KERN_CONT "%s: %02x %02x %02x %02x %02x %02x %02x %02x ", + (req_type & USB_DIR_IN) ? " IN" : "OUT", + req_type, req, value&0xff, value>>8, index&0xff, + index>>8, len&0xff, len>>8); + + if (!(req_type & USB_DIR_IN)) { + printk(KERN_CONT ">>> "); + for (i = 0; i < len; i++) + printk(KERN_CONT " %02x", buf[i]); + printk(KERN_CONT "\n"); + } + } + + ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, + data, len, USB_TIMEOUT); + + if (req_type & USB_DIR_IN) + memcpy(buf, data, len); + + if (tm6000_debug & V4L2_DEBUG_I2C) { + if (ret < 0) { + if (req_type & USB_DIR_IN) + printk(KERN_DEBUG "<<< (len=%d)\n", len); + + printk(KERN_CONT "%s: Error #%d\n", __func__, ret); + } else if (req_type & USB_DIR_IN) { + printk(KERN_CONT "<<< "); + for (i = 0; i < len; i++) + printk(KERN_CONT " %02x", buf[i]); + printk(KERN_CONT "\n"); + } + } + + kfree(data); + + if (dev->quirks & TM6000_QUIRK_NO_USB_DELAY) + delay = 0; + + if (req == REQ_16_SET_GET_I2C_WR1_RDN && !(req_type & USB_DIR_IN)) { + unsigned int tsleep; + /* Calculate delay time, 14000us for 64 bytes */ + tsleep = (len * 200) + 200; + if (tsleep < delay) + tsleep = delay; + usleep_range(tsleep, tsleep + 1000); + } + else if (delay) + usleep_range(delay, delay + 1000); + + mutex_unlock(&dev->usb_lock); + return ret; +} + +int tm6000_set_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index) +{ + return + tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR, + req, value, index, NULL, 0); +} +EXPORT_SYMBOL_GPL(tm6000_set_reg); + +int tm6000_get_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index) +{ + int rc; + u8 buf[1]; + + rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req, + value, index, buf, 1); + + if (rc < 0) + return rc; + + return *buf; +} +EXPORT_SYMBOL_GPL(tm6000_get_reg); + +int tm6000_set_reg_mask(struct tm6000_core *dev, u8 req, u16 value, + u16 index, u16 mask) +{ + int rc; + u8 buf[1]; + u8 new_index; + + rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req, + value, 0, buf, 1); + + if (rc < 0) + return rc; + + new_index = (buf[0] & ~mask) | (index & mask); + + if (new_index == buf[0]) + return 0; + + return tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR, + req, value, new_index, NULL, 0); +} +EXPORT_SYMBOL_GPL(tm6000_set_reg_mask); + +int tm6000_get_reg16(struct tm6000_core *dev, u8 req, u16 value, u16 index) +{ + int rc; + u8 buf[2]; + + rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req, + value, index, buf, 2); + + if (rc < 0) + return rc; + + return buf[1]|buf[0]<<8; +} + +int tm6000_get_reg32(struct tm6000_core *dev, u8 req, u16 value, u16 index) +{ + int rc; + u8 buf[4]; + + rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req, + value, index, buf, 4); + + if (rc < 0) + return rc; + + return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24; +} + +int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep) +{ + int rc; + + rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0); + if (rc < 0) + return rc; + + msleep(tsleep); + + rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1); + msleep(tsleep); + + return rc; +} + +void tm6000_set_fourcc_format(struct tm6000_core *dev) +{ + if (dev->dev_type == TM6010) { + int val; + + val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, 0) & 0xfc; + if (dev->fourcc == V4L2_PIX_FMT_UYVY) + tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val); + else + tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val | 1); + } else { + if (dev->fourcc == V4L2_PIX_FMT_UYVY) + tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0); + else + tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90); + } +} + +static void tm6000_set_vbi(struct tm6000_core *dev) +{ + /* + * FIXME: + * VBI lines and start/end are different between 60Hz and 50Hz + * So, it is very likely that we need to change the config to + * something that takes it into account, doing something different + * if (dev->norm & V4L2_STD_525_60) + */ + + if (dev->dev_type == TM6010) { + tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01); + tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27); + tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55); + tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66); + tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66); + tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66); + tm6000_set_reg(dev, + TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00); + tm6000_set_reg(dev, + TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00); + tm6000_set_reg(dev, + TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01); + tm6000_set_reg(dev, + TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00); + tm6000_set_reg(dev, + TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02); + tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35); + tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0); + tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11); + tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c); + tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01); + tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00); + } +} + +int tm6000_init_analog_mode(struct tm6000_core *dev) +{ + struct v4l2_frequency f; + + if (dev->dev_type == TM6010) { + u8 active = TM6010_REQ07_RCC_ACTIVE_IF_AUDIO_ENABLE; + + if (!dev->radio) + active |= TM6010_REQ07_RCC_ACTIVE_IF_VIDEO_ENABLE; + + /* Enable video and audio */ + tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_IF, + active, 0x60); + /* Disable TS input */ + tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, + 0x00, 0x40); + } else { + /* Enables soft reset */ + tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01); + + if (dev->scaler) + /* Disable Hfilter and Enable TS Drop err */ + tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20); + else /* Enable Hfilter and disable TS Drop err */ + tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80); + + tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88); + tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x23); + tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0); + tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8); + tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06); + tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f); + + /* AP Software reset */ + tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08); + tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00); + + tm6000_set_fourcc_format(dev); + + /* Disables soft reset */ + tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00); + } + msleep(20); + + /* Tuner firmware can now be loaded */ + + /* + * FIXME: This is a hack! xc3028 "sleeps" when no channel is detected + * for more than a few seconds. Not sure why, as this behavior does + * not happen on other devices with xc3028. So, I suspect that it + * is yet another bug at tm6000. After start sleeping, decoding + * doesn't start automatically. Instead, it requires some + * I2C commands to wake it up. As we want to have image at the + * beginning, we needed to add this hack. The better would be to + * discover some way to make tm6000 to wake up without this hack. + */ + f.frequency = dev->freq; + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f); + + msleep(100); + tm6000_set_standard(dev); + tm6000_set_vbi(dev); + tm6000_set_audio_bitrate(dev, 48000); + + /* switch dvb led off */ + if (dev->gpio.dvb_led) { + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.dvb_led, 0x01); + } + + return 0; +} + +int tm6000_init_digital_mode(struct tm6000_core *dev) +{ + if (dev->dev_type == TM6010) { + /* Disable video and audio */ + tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_IF, + 0x00, 0x60); + /* Enable TS input */ + tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, + 0x40, 0x40); + /* all power down, but not the digital data port */ + tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28); + tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc); + tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff); + } else { + tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08); + tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00); + tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01); + tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x08); + tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c); + tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff); + tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0xd8); + tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40); + tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0); + tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09); + tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x37); + tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8); + tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0); + tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60); + + tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c); + tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff); + tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0x08); + msleep(50); + + tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00); + msleep(50); + tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01); + msleep(50); + tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00); + msleep(100); + } + + /* switch dvb led on */ + if (dev->gpio.dvb_led) { + tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, + dev->gpio.dvb_led, 0x00); + } + + return 0; +} +EXPORT_SYMBOL(tm6000_init_digital_mode); + +struct reg_init { + u8 req; + u8 reg; + u8 val; +}; + +/* The meaning of those initializations are unknown */ +static struct reg_init tm6000_init_tab[] = { + /* REG VALUE */ + { TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f }, + { TM6010_REQ07_RFF_SOFT_RESET, 0x08 }, + { TM6010_REQ07_RFF_SOFT_RESET, 0x00 }, + { TM6010_REQ07_RD5_POWERSAVE, 0x4f }, + { TM6000_REQ07_RDA_CLK_SEL, 0x23 }, + { TM6000_REQ07_RDB_OUT_SEL, 0x08 }, + { TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x00 }, + { TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10 }, + { TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00 }, + { TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00 }, + { TM6000_REQ07_REB_VADC_AADC_MODE, 0x64 }, /* 48000 bits/sample, external input */ + { TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL, 0xc2 }, + + { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */ + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 }, + { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 }, + { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 }, + { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 }, + { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 }, + { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a }, + { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 }, + { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 }, + { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b }, + { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 }, + { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f }, + { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c }, + { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c }, + { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, + { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c }, + { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a }, + { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 }, + { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 }, + { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a }, + { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 }, + { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 }, + { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 }, + { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 }, + { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 }, + { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 }, + { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, + { TM6010_REQ07_RC1_TRESHOLD, 0xd0 }, + { TM6010_REQ07_RC3_HSTART1, 0x88 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */ + { TM6010_REQ05_R18_IMASK7, 0x00 }, +}; + +static struct reg_init tm6010_init_tab[] = { + { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 }, + { TM6010_REQ07_RC4_HSTART0, 0xa0 }, + { TM6010_REQ07_RC6_HEND0, 0x40 }, + { TM6010_REQ07_RCA_VEND0, 0x31 }, + { TM6010_REQ07_RCC_ACTIVE_IF, 0xe1 }, + { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 }, + { TM6010_REQ07_RFE_POWER_DOWN, 0x7f }, + + { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 }, + { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 }, + { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 }, + { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 }, + { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 }, + { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 }, + { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 }, + { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 }, + { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc }, + + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 }, + { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 }, + { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 }, + { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 }, + { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 }, + { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a }, + { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 }, + { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 }, + { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b }, + { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 }, + { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f }, + { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c }, + { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c }, + { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, + { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c }, + { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a }, + { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 }, + { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 }, + { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a }, + { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 }, + { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 }, + { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 }, + { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 }, + { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 }, + { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 }, + { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, + { TM6010_REQ07_RC1_TRESHOLD, 0xd0 }, + { TM6010_REQ07_RC3_HSTART1, 0x88 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + + { TM6010_REQ05_R18_IMASK7, 0x00 }, + + { TM6010_REQ07_RDC_IR_LEADER1, 0xaa }, + { TM6010_REQ07_RDD_IR_LEADER0, 0x30 }, + { TM6010_REQ07_RDE_IR_PULSE_CNT1, 0x20 }, + { TM6010_REQ07_RDF_IR_PULSE_CNT0, 0xd0 }, + { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 }, + { TM6010_REQ07_RD8_IR, 0x0f }, + + /* set remote wakeup key:any key wakeup */ + { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe }, + { TM6010_REQ07_RDA_IR_WAKEUP_SEL, 0xff }, +}; + +int tm6000_init(struct tm6000_core *dev) +{ + int board, rc = 0, i, size; + struct reg_init *tab; + + /* Check board revision */ + board = tm6000_get_reg32(dev, REQ_40_GET_VERSION, 0, 0); + if (board >= 0) { + switch (board & 0xff) { + case 0xf3: + printk(KERN_INFO "Found tm6000\n"); + if (dev->dev_type != TM6000) + dev->dev_type = TM6000; + break; + case 0xf4: + printk(KERN_INFO "Found tm6010\n"); + if (dev->dev_type != TM6010) + dev->dev_type = TM6010; + break; + default: + printk(KERN_INFO "Unknown board version = 0x%08x\n", board); + } + } else + printk(KERN_ERR "Error %i while retrieving board version\n", board); + + if (dev->dev_type == TM6010) { + tab = tm6010_init_tab; + size = ARRAY_SIZE(tm6010_init_tab); + } else { + tab = tm6000_init_tab; + size = ARRAY_SIZE(tm6000_init_tab); + } + + /* Load board's initialization table */ + for (i = 0; i < size; i++) { + rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val); + if (rc < 0) { + printk(KERN_ERR "Error %i while setting req %d, reg %d to value %d\n", + rc, + tab[i].req, tab[i].reg, tab[i].val); + return rc; + } + } + + msleep(5); /* Just to be conservative */ + + rc = tm6000_cards_setup(dev); + + return rc; +} + + +int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate) +{ + int val = 0; + u8 areg_f0 = 0x60; /* ADC MCLK = 250 Fs */ + u8 areg_0a = 0x91; /* SIF 48KHz */ + + switch (bitrate) { + case 48000: + areg_f0 = 0x60; /* ADC MCLK = 250 Fs */ + areg_0a = 0x91; /* SIF 48KHz */ + dev->audio_bitrate = bitrate; + break; + case 32000: + areg_f0 = 0x00; /* ADC MCLK = 375 Fs */ + areg_0a = 0x90; /* SIF 32KHz */ + dev->audio_bitrate = bitrate; + break; + default: + return -EINVAL; + } + + + /* enable I2S, if we use sif or external I2S device */ + if (dev->dev_type == TM6010) { + val = tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, areg_0a); + if (val < 0) + return val; + + val = tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, + areg_f0, 0xf0); + if (val < 0) + return val; + } else { + val = tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE, + areg_f0, 0xf0); + if (val < 0) + return val; + } + return 0; +} +EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate); + +int tm6000_set_audio_rinput(struct tm6000_core *dev) +{ + if (dev->dev_type == TM6010) { + /* Audio crossbar setting, default SIF1 */ + u8 areg_f0; + u8 areg_07 = 0x10; + + switch (dev->rinput.amux) { + case TM6000_AMUX_SIF1: + case TM6000_AMUX_SIF2: + areg_f0 = 0x03; + areg_07 = 0x30; + break; + case TM6000_AMUX_ADC1: + areg_f0 = 0x00; + break; + case TM6000_AMUX_ADC2: + areg_f0 = 0x08; + break; + case TM6000_AMUX_I2S: + areg_f0 = 0x04; + break; + default: + printk(KERN_INFO "%s: audio input doesn't support\n", + dev->name); + return 0; + break; + } + /* Set audio input crossbar */ + tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, + areg_f0, 0x0f); + /* Mux overflow workaround */ + tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, + areg_07, 0xf0); + } else { + u8 areg_eb; + /* Audio setting, default LINE1 */ + switch (dev->rinput.amux) { + case TM6000_AMUX_ADC1: + areg_eb = 0x00; + break; + case TM6000_AMUX_ADC2: + areg_eb = 0x04; + break; + default: + printk(KERN_INFO "%s: audio input doesn't support\n", + dev->name); + return 0; + break; + } + /* Set audio input */ + tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE, + areg_eb, 0x0f); + } + return 0; +} + +static void tm6010_set_mute_sif(struct tm6000_core *dev, u8 mute) +{ + u8 mute_reg = 0; + + if (mute) + mute_reg = 0x08; + + tm6000_set_reg_mask(dev, TM6010_REQ08_R0A_A_I2S_MOD, mute_reg, 0x08); +} + +static void tm6010_set_mute_adc(struct tm6000_core *dev, u8 mute) +{ + u8 mute_reg = 0; + + if (mute) + mute_reg = 0x20; + + if (dev->dev_type == TM6010) { + tm6000_set_reg_mask(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL, + mute_reg, 0x20); + tm6000_set_reg_mask(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL, + mute_reg, 0x20); + } else { + tm6000_set_reg_mask(dev, TM6000_REQ07_REC_VADC_AADC_LVOL, + mute_reg, 0x20); + tm6000_set_reg_mask(dev, TM6000_REQ07_RED_VADC_AADC_RVOL, + mute_reg, 0x20); + } +} + +int tm6000_tvaudio_set_mute(struct tm6000_core *dev, u8 mute) +{ + enum tm6000_mux mux; + + if (dev->radio) + mux = dev->rinput.amux; + else + mux = dev->vinput[dev->input].amux; + + switch (mux) { + case TM6000_AMUX_SIF1: + case TM6000_AMUX_SIF2: + if (dev->dev_type == TM6010) + tm6010_set_mute_sif(dev, mute); + else { + printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has SIF audio inputs. Please check the %s configuration.\n", + dev->name); + return -EINVAL; + } + break; + case TM6000_AMUX_ADC1: + case TM6000_AMUX_ADC2: + tm6010_set_mute_adc(dev, mute); + break; + default: + return -EINVAL; + break; + } + return 0; +} + +static void tm6010_set_volume_sif(struct tm6000_core *dev, int vol) +{ + u8 vol_reg; + + vol_reg = vol & 0x0F; + + if (vol < 0) + vol_reg |= 0x40; + + tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, vol_reg); + tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, vol_reg); +} + +static void tm6010_set_volume_adc(struct tm6000_core *dev, int vol) +{ + u8 vol_reg; + + vol_reg = (vol + 0x10) & 0x1f; + + if (dev->dev_type == TM6010) { + tm6000_set_reg(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL, vol_reg); + tm6000_set_reg(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL, vol_reg); + } else { + tm6000_set_reg(dev, TM6000_REQ07_REC_VADC_AADC_LVOL, vol_reg); + tm6000_set_reg(dev, TM6000_REQ07_RED_VADC_AADC_RVOL, vol_reg); + } +} + +void tm6000_set_volume(struct tm6000_core *dev, int vol) +{ + enum tm6000_mux mux; + + if (dev->radio) { + mux = dev->rinput.amux; + vol += 8; /* Offset to 0 dB */ + } else + mux = dev->vinput[dev->input].amux; + + switch (mux) { + case TM6000_AMUX_SIF1: + case TM6000_AMUX_SIF2: + if (dev->dev_type == TM6010) + tm6010_set_volume_sif(dev, vol); + else + printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has SIF audio inputs. Please check the %s configuration.\n", + dev->name); + break; + case TM6000_AMUX_ADC1: + case TM6000_AMUX_ADC2: + tm6010_set_volume_adc(dev, vol); + break; + default: + break; + } +} + +static LIST_HEAD(tm6000_devlist); +static DEFINE_MUTEX(tm6000_devlist_mutex); + +/* + * tm6000_realease_resource() + */ + +void tm6000_remove_from_devlist(struct tm6000_core *dev) +{ + mutex_lock(&tm6000_devlist_mutex); + list_del(&dev->devlist); + mutex_unlock(&tm6000_devlist_mutex); +}; + +void tm6000_add_into_devlist(struct tm6000_core *dev) +{ + mutex_lock(&tm6000_devlist_mutex); + list_add_tail(&dev->devlist, &tm6000_devlist); + mutex_unlock(&tm6000_devlist_mutex); +}; + +/* + * Extension interface + */ + +static LIST_HEAD(tm6000_extension_devlist); + +int tm6000_call_fillbuf(struct tm6000_core *dev, enum tm6000_ops_type type, + char *buf, int size) +{ + struct tm6000_ops *ops = NULL; + + /* FIXME: tm6000_extension_devlist_lock should be a spinlock */ + + list_for_each_entry(ops, &tm6000_extension_devlist, next) { + if (ops->fillbuf && ops->type == type) + ops->fillbuf(dev, buf, size); + } + + return 0; +} + +int tm6000_register_extension(struct tm6000_ops *ops) +{ + struct tm6000_core *dev = NULL; + + mutex_lock(&tm6000_devlist_mutex); + list_add_tail(&ops->next, &tm6000_extension_devlist); + list_for_each_entry(dev, &tm6000_devlist, devlist) { + ops->init(dev); + printk(KERN_INFO "%s: Initialized (%s) extension\n", + dev->name, ops->name); + } + mutex_unlock(&tm6000_devlist_mutex); + return 0; +} +EXPORT_SYMBOL(tm6000_register_extension); + +void tm6000_unregister_extension(struct tm6000_ops *ops) +{ + struct tm6000_core *dev = NULL; + + mutex_lock(&tm6000_devlist_mutex); + list_for_each_entry(dev, &tm6000_devlist, devlist) + ops->fini(dev); + + printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name); + list_del(&ops->next); + mutex_unlock(&tm6000_devlist_mutex); +} +EXPORT_SYMBOL(tm6000_unregister_extension); + +void tm6000_init_extension(struct tm6000_core *dev) +{ + struct tm6000_ops *ops = NULL; + + mutex_lock(&tm6000_devlist_mutex); + list_for_each_entry(ops, &tm6000_extension_devlist, next) { + if (ops->init) + ops->init(dev); + } + mutex_unlock(&tm6000_devlist_mutex); +} + +void tm6000_close_extension(struct tm6000_core *dev) +{ + struct tm6000_ops *ops = NULL; + + mutex_lock(&tm6000_devlist_mutex); + list_for_each_entry(ops, &tm6000_extension_devlist, next) { + if (ops->fini) + ops->fini(dev); + } + mutex_unlock(&tm6000_devlist_mutex); +} diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-dvb.c b/drivers/staging/media/deprecated/tm6000/tm6000-dvb.c new file mode 100644 index 000000000..ee04973cb --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-dvb.c @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * tm6000-dvb.c - dvb-t support for TM5600/TM6000/TM6010 USB video capture devices + * + * Copyright (C) 2007 Michel Ludwig + */ + +#include +#include +#include + +#include "tm6000.h" +#include "tm6000-regs.h" + +#include "zl10353.h" + +#include + +#include "xc2028.h" +#include "xc5000.h" + +MODULE_DESCRIPTION("DVB driver extension module for tm5600/6000/6010 based TV cards"); +MODULE_AUTHOR("Mauro Carvalho Chehab"); +MODULE_LICENSE("GPL"); + +static int debug; + +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable debug message"); + +static inline void print_err_status(struct tm6000_core *dev, + int packet, int status) +{ + char *errmsg = "Unknown"; + + switch (status) { + case -ENOENT: + errmsg = "unlinked synchronously"; + break; + case -ECONNRESET: + errmsg = "unlinked asynchronously"; + break; + case -ENOSR: + errmsg = "Buffer error (overrun)"; + break; + case -EPIPE: + errmsg = "Stalled (device not responding)"; + break; + case -EOVERFLOW: + errmsg = "Babble (bad cable?)"; + break; + case -EPROTO: + errmsg = "Bit-stuff error (bad cable?)"; + break; + case -EILSEQ: + errmsg = "CRC/Timeout (could be anything)"; + break; + case -ETIME: + errmsg = "Device does not respond"; + break; + } + if (packet < 0) { + dprintk(dev, 1, "URB status %d [%s].\n", + status, errmsg); + } else { + dprintk(dev, 1, "URB packet %d, status %d [%s].\n", + packet, status, errmsg); + } +} + +static void tm6000_urb_received(struct urb *urb) +{ + int ret; + struct tm6000_core *dev = urb->context; + + switch (urb->status) { + case 0: + case -ETIMEDOUT: + break; + case -ENOENT: + case -ECONNRESET: + case -ESHUTDOWN: + return; + default: + print_err_status(dev, 0, urb->status); + } + + if (urb->actual_length > 0) + dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer, + urb->actual_length); + + if (dev->dvb->streams > 0) { + ret = usb_submit_urb(urb, GFP_ATOMIC); + if (ret < 0) { + printk(KERN_ERR "tm6000: error %s\n", __func__); + kfree(urb->transfer_buffer); + usb_free_urb(urb); + dev->dvb->bulk_urb = NULL; + } + } +} + +static int tm6000_start_stream(struct tm6000_core *dev) +{ + int ret; + unsigned int pipe, size; + struct tm6000_dvb *dvb = dev->dvb; + + printk(KERN_INFO "tm6000: got start stream request %s\n", __func__); + + if (dev->mode != TM6000_MODE_DIGITAL) { + tm6000_init_digital_mode(dev); + dev->mode = TM6000_MODE_DIGITAL; + } + + dvb->bulk_urb = usb_alloc_urb(0, GFP_KERNEL); + if (!dvb->bulk_urb) + return -ENOMEM; + + pipe = usb_rcvbulkpipe(dev->udev, dev->bulk_in.endp->desc.bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK); + + size = usb_maxpacket(dev->udev, pipe); + size = size * 15; /* 512 x 8 or 12 or 15 */ + + dvb->bulk_urb->transfer_buffer = kzalloc(size, GFP_KERNEL); + if (!dvb->bulk_urb->transfer_buffer) { + usb_free_urb(dvb->bulk_urb); + dvb->bulk_urb = NULL; + return -ENOMEM; + } + + usb_fill_bulk_urb(dvb->bulk_urb, dev->udev, pipe, + dvb->bulk_urb->transfer_buffer, + size, + tm6000_urb_received, dev); + + ret = usb_clear_halt(dev->udev, pipe); + if (ret < 0) { + printk(KERN_ERR "tm6000: error %i in %s during pipe reset\n", + ret, __func__); + + kfree(dvb->bulk_urb->transfer_buffer); + usb_free_urb(dvb->bulk_urb); + dvb->bulk_urb = NULL; + return ret; + } else + printk(KERN_ERR "tm6000: pipe reset\n"); + +/* mutex_lock(&tm6000_driver.open_close_mutex); */ + ret = usb_submit_urb(dvb->bulk_urb, GFP_ATOMIC); + +/* mutex_unlock(&tm6000_driver.open_close_mutex); */ + if (ret) { + printk(KERN_ERR "tm6000: submit of urb failed (error=%i)\n", + ret); + + kfree(dvb->bulk_urb->transfer_buffer); + usb_free_urb(dvb->bulk_urb); + dvb->bulk_urb = NULL; + return ret; + } + + return 0; +} + +static void tm6000_stop_stream(struct tm6000_core *dev) +{ + struct tm6000_dvb *dvb = dev->dvb; + + if (dvb->bulk_urb) { + printk(KERN_INFO "urb killing\n"); + usb_kill_urb(dvb->bulk_urb); + printk(KERN_INFO "urb buffer free\n"); + kfree(dvb->bulk_urb->transfer_buffer); + usb_free_urb(dvb->bulk_urb); + dvb->bulk_urb = NULL; + } +} + +static int tm6000_start_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct tm6000_core *dev = demux->priv; + struct tm6000_dvb *dvb = dev->dvb; + printk(KERN_INFO "tm6000: got start feed request %s\n", __func__); + + mutex_lock(&dvb->mutex); + if (dvb->streams == 0) { + dvb->streams = 1; +/* mutex_init(&tm6000_dev->streming_mutex); */ + tm6000_start_stream(dev); + } else + ++(dvb->streams); + mutex_unlock(&dvb->mutex); + + return 0; +} + +static int tm6000_stop_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct tm6000_core *dev = demux->priv; + struct tm6000_dvb *dvb = dev->dvb; + + printk(KERN_INFO "tm6000: got stop feed request %s\n", __func__); + + mutex_lock(&dvb->mutex); + + printk(KERN_INFO "stream %#x\n", dvb->streams); + --(dvb->streams); + if (dvb->streams == 0) { + printk(KERN_INFO "stop stream\n"); + tm6000_stop_stream(dev); +/* mutex_destroy(&tm6000_dev->streaming_mutex); */ + } + mutex_unlock(&dvb->mutex); +/* mutex_destroy(&tm6000_dev->streaming_mutex); */ + + return 0; +} + +static int tm6000_dvb_attach_frontend(struct tm6000_core *dev) +{ + struct tm6000_dvb *dvb = dev->dvb; + + if (dev->caps.has_zl10353) { + struct zl10353_config config = { + .demod_address = dev->demod_addr, + .no_tuner = 1, + .parallel_ts = 1, + .if2 = 45700, + .disable_i2c_gate_ctrl = 1, + }; + + dvb->frontend = dvb_attach(zl10353_attach, &config, + &dev->i2c_adap); + } else { + printk(KERN_ERR "tm6000: no frontend defined for the device!\n"); + return -1; + } + + return (!dvb->frontend) ? -1 : 0; +} + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +static int register_dvb(struct tm6000_core *dev) +{ + int ret = -1; + struct tm6000_dvb *dvb = dev->dvb; + + mutex_init(&dvb->mutex); + + dvb->streams = 0; + + /* attach the frontend */ + ret = tm6000_dvb_attach_frontend(dev); + if (ret < 0) { + printk(KERN_ERR "tm6000: couldn't attach the frontend!\n"); + goto err; + } + + ret = dvb_register_adapter(&dvb->adapter, "Trident TVMaster 6000 DVB-T", + THIS_MODULE, &dev->udev->dev, adapter_nr); + if (ret < 0) { + pr_err("tm6000: couldn't register the adapter!\n"); + goto err; + } + + dvb->adapter.priv = dev; + + if (dvb->frontend) { + switch (dev->tuner_type) { + case TUNER_XC2028: { + struct xc2028_config cfg = { + .i2c_adap = &dev->i2c_adap, + .i2c_addr = dev->tuner_addr, + }; + + dvb->frontend->callback = tm6000_tuner_callback; + ret = dvb_register_frontend(&dvb->adapter, dvb->frontend); + if (ret < 0) { + printk(KERN_ERR + "tm6000: couldn't register frontend\n"); + goto adapter_err; + } + + if (!dvb_attach(xc2028_attach, dvb->frontend, &cfg)) { + printk(KERN_ERR "tm6000: couldn't register frontend (xc3028)\n"); + ret = -EINVAL; + goto frontend_err; + } + printk(KERN_INFO "tm6000: XC2028/3028 asked to be attached to frontend!\n"); + break; + } + case TUNER_XC5000: { + struct xc5000_config cfg = { + .i2c_address = dev->tuner_addr, + }; + + dvb->frontend->callback = tm6000_xc5000_callback; + ret = dvb_register_frontend(&dvb->adapter, dvb->frontend); + if (ret < 0) { + printk(KERN_ERR + "tm6000: couldn't register frontend\n"); + goto adapter_err; + } + + if (!dvb_attach(xc5000_attach, dvb->frontend, &dev->i2c_adap, &cfg)) { + printk(KERN_ERR "tm6000: couldn't register frontend (xc5000)\n"); + ret = -EINVAL; + goto frontend_err; + } + printk(KERN_INFO "tm6000: XC5000 asked to be attached to frontend!\n"); + break; + } + } + } else + printk(KERN_ERR "tm6000: no frontend found\n"); + + dvb->demux.dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING + | DMX_MEMORY_BASED_FILTERING; + dvb->demux.priv = dev; + dvb->demux.filternum = 8; + dvb->demux.feednum = 8; + dvb->demux.start_feed = tm6000_start_feed; + dvb->demux.stop_feed = tm6000_stop_feed; + dvb->demux.write_to_decoder = NULL; + ret = dvb_dmx_init(&dvb->demux); + if (ret < 0) { + printk(KERN_ERR "tm6000: dvb_dmx_init failed (errno = %d)\n", ret); + goto frontend_err; + } + + dvb->dmxdev.filternum = dev->dvb->demux.filternum; + dvb->dmxdev.demux = &dev->dvb->demux.dmx; + dvb->dmxdev.capabilities = 0; + + ret = dvb_dmxdev_init(&dvb->dmxdev, &dvb->adapter); + if (ret < 0) { + printk(KERN_ERR "tm6000: dvb_dmxdev_init failed (errno = %d)\n", ret); + goto dvb_dmx_err; + } + + return 0; + +dvb_dmx_err: + dvb_dmx_release(&dvb->demux); +frontend_err: + if (dvb->frontend) { + dvb_unregister_frontend(dvb->frontend); + dvb_frontend_detach(dvb->frontend); + } +adapter_err: + dvb_unregister_adapter(&dvb->adapter); +err: + return ret; +} + +static void unregister_dvb(struct tm6000_core *dev) +{ + struct tm6000_dvb *dvb = dev->dvb; + + if (dvb->bulk_urb) { + struct urb *bulk_urb = dvb->bulk_urb; + + kfree(bulk_urb->transfer_buffer); + bulk_urb->transfer_buffer = NULL; + usb_unlink_urb(bulk_urb); + usb_free_urb(bulk_urb); + } + +/* mutex_lock(&tm6000_driver.open_close_mutex); */ + if (dvb->frontend) { + dvb_unregister_frontend(dvb->frontend); + dvb_frontend_detach(dvb->frontend); + } + + dvb_dmxdev_release(&dvb->dmxdev); + dvb_dmx_release(&dvb->demux); + dvb_unregister_adapter(&dvb->adapter); + mutex_destroy(&dvb->mutex); +/* mutex_unlock(&tm6000_driver.open_close_mutex); */ +} + +static int dvb_init(struct tm6000_core *dev) +{ + struct tm6000_dvb *dvb; + int rc; + + if (!dev) + return 0; + + if (!dev->caps.has_dvb) + return 0; + + if (dev->udev->speed == USB_SPEED_FULL) { + printk(KERN_INFO "This USB2.0 device cannot be run on a USB1.1 port. (it lacks a hardware PID filter)\n"); + return 0; + } + + dvb = kzalloc(sizeof(struct tm6000_dvb), GFP_KERNEL); + if (!dvb) + return -ENOMEM; + + dev->dvb = dvb; + + rc = register_dvb(dev); + if (rc < 0) { + kfree(dvb); + dev->dvb = NULL; + return 0; + } + + return 0; +} + +static int dvb_fini(struct tm6000_core *dev) +{ + if (!dev) + return 0; + + if (!dev->caps.has_dvb) + return 0; + + if (dev->dvb) { + unregister_dvb(dev); + kfree(dev->dvb); + dev->dvb = NULL; + } + + return 0; +} + +static struct tm6000_ops dvb_ops = { + .type = TM6000_DVB, + .name = "TM6000 dvb Extension", + .init = dvb_init, + .fini = dvb_fini, +}; + +static int __init tm6000_dvb_register(void) +{ + return tm6000_register_extension(&dvb_ops); +} + +static void __exit tm6000_dvb_unregister(void) +{ + tm6000_unregister_extension(&dvb_ops); +} + +module_init(tm6000_dvb_register); +module_exit(tm6000_dvb_unregister); diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-i2c.c b/drivers/staging/media/deprecated/tm6000/tm6000-i2c.c new file mode 100644 index 000000000..7554b93b8 --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-i2c.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +// tm6000-i2c.c - driver for TM5600/TM6000/TM6010 USB video capture devices +// +// Copyright (c) 2006-2007 Mauro Carvalho Chehab +// +// Copyright (c) 2007 Michel Ludwig +// - Fix SMBus Read Byte command + +#include +#include +#include +#include + +#include "tm6000.h" +#include "tm6000-regs.h" +#include +#include +#include "xc2028.h" + + +/* ----------------------------------------------------------- */ + +static unsigned int i2c_debug; +module_param(i2c_debug, int, 0644); +MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]"); + +#define i2c_dprintk(lvl, fmt, args...) if (i2c_debug >= lvl) do { \ + printk(KERN_DEBUG "%s at %s: " fmt, \ + dev->name, __func__, ##args); } while (0) + +static int tm6000_i2c_send_regs(struct tm6000_core *dev, unsigned char addr, + __u8 reg, char *buf, int len) +{ + int rc; + unsigned int i2c_packet_limit = 16; + + if (dev->dev_type == TM6010) + i2c_packet_limit = 80; + + if (!buf) + return -1; + + if (len < 1 || len > i2c_packet_limit) { + printk(KERN_ERR "Incorrect length of i2c packet = %d, limit set to %d\n", + len, i2c_packet_limit); + return -1; + } + + /* capture mutex */ + rc = tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR | + USB_RECIP_DEVICE, REQ_16_SET_GET_I2C_WR1_RDN, + addr | reg << 8, 0, buf, len); + + if (rc < 0) { + /* release mutex */ + return rc; + } + + /* release mutex */ + return rc; +} + +/* Generic read - doesn't work fine with 16bit registers */ +static int tm6000_i2c_recv_regs(struct tm6000_core *dev, unsigned char addr, + __u8 reg, char *buf, int len) +{ + int rc; + u8 b[2]; + unsigned int i2c_packet_limit = 16; + + if (dev->dev_type == TM6010) + i2c_packet_limit = 64; + + if (!buf) + return -1; + + if (len < 1 || len > i2c_packet_limit) { + printk(KERN_ERR "Incorrect length of i2c packet = %d, limit set to %d\n", + len, i2c_packet_limit); + return -1; + } + + /* capture mutex */ + if ((dev->caps.has_zl10353) && (dev->demod_addr << 1 == addr) && (reg % 2 == 0)) { + /* + * Workaround an I2C bug when reading from zl10353 + */ + reg -= 1; + len += 1; + + rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + REQ_16_SET_GET_I2C_WR1_RDN, addr | reg << 8, 0, b, len); + + *buf = b[1]; + } else { + rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + REQ_16_SET_GET_I2C_WR1_RDN, addr | reg << 8, 0, buf, len); + } + + /* release mutex */ + return rc; +} + +/* + * read from a 16bit register + * for example xc2028, xc3028 or xc3028L + */ +static int tm6000_i2c_recv_regs16(struct tm6000_core *dev, unsigned char addr, + __u16 reg, char *buf, int len) +{ + int rc; + unsigned char ureg; + + if (!buf || len != 2) + return -1; + + /* capture mutex */ + if (dev->dev_type == TM6010) { + ureg = reg & 0xFF; + rc = tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR | + USB_RECIP_DEVICE, REQ_16_SET_GET_I2C_WR1_RDN, + addr | (reg & 0xFF00), 0, &ureg, 1); + + if (rc < 0) { + /* release mutex */ + return rc; + } + + rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR | + USB_RECIP_DEVICE, REQ_35_AFTEK_TUNER_READ, + reg, 0, buf, len); + } else { + rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR | + USB_RECIP_DEVICE, REQ_14_SET_GET_I2C_WR2_RDN, + addr, reg, buf, len); + } + + /* release mutex */ + return rc; +} + +static int tm6000_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg msgs[], int num) +{ + struct tm6000_core *dev = i2c_adap->algo_data; + int addr, rc, i, byte; + + for (i = 0; i < num; i++) { + addr = (msgs[i].addr << 1) & 0xff; + i2c_dprintk(2, "%s %s addr=0x%x len=%d:", + (msgs[i].flags & I2C_M_RD) ? "read" : "write", + i == num - 1 ? "stop" : "nonstop", addr, msgs[i].len); + if (msgs[i].flags & I2C_M_RD) { + /* read request without preceding register selection */ + /* + * The TM6000 only supports a read transaction + * immediately after a 1 or 2 byte write to select + * a register. We cannot fulfill this request. + */ + i2c_dprintk(2, " read without preceding write not supported"); + rc = -EOPNOTSUPP; + goto err; + } else if (i + 1 < num && msgs[i].len <= 2 && + (msgs[i + 1].flags & I2C_M_RD) && + msgs[i].addr == msgs[i + 1].addr) { + /* 1 or 2 byte write followed by a read */ + if (i2c_debug >= 2) + for (byte = 0; byte < msgs[i].len; byte++) + printk(KERN_CONT " %02x", msgs[i].buf[byte]); + i2c_dprintk(2, "; joined to read %s len=%d:", + i == num - 2 ? "stop" : "nonstop", + msgs[i + 1].len); + + if (msgs[i].len == 2) { + rc = tm6000_i2c_recv_regs16(dev, addr, + msgs[i].buf[0] << 8 | msgs[i].buf[1], + msgs[i + 1].buf, msgs[i + 1].len); + } else { + rc = tm6000_i2c_recv_regs(dev, addr, msgs[i].buf[0], + msgs[i + 1].buf, msgs[i + 1].len); + } + + i++; + + if (addr == dev->tuner_addr << 1) { + tm6000_set_reg(dev, REQ_50_SET_START, 0, 0); + tm6000_set_reg(dev, REQ_51_SET_STOP, 0, 0); + } + if (i2c_debug >= 2) + for (byte = 0; byte < msgs[i].len; byte++) + printk(KERN_CONT " %02x", msgs[i].buf[byte]); + } else { + /* write bytes */ + if (i2c_debug >= 2) + for (byte = 0; byte < msgs[i].len; byte++) + printk(KERN_CONT " %02x", msgs[i].buf[byte]); + rc = tm6000_i2c_send_regs(dev, addr, msgs[i].buf[0], + msgs[i].buf + 1, msgs[i].len - 1); + } + if (i2c_debug >= 2) + printk(KERN_CONT "\n"); + if (rc < 0) + goto err; + } + + return num; +err: + i2c_dprintk(2, " ERROR: %i\n", rc); + return rc; +} + +static int tm6000_i2c_eeprom(struct tm6000_core *dev) +{ + int i, rc; + unsigned char *p = dev->eedata; + unsigned char bytes[17]; + + dev->i2c_client.addr = 0xa0 >> 1; + dev->eedata_size = 0; + + bytes[16] = '\0'; + for (i = 0; i < sizeof(dev->eedata); ) { + *p = i; + rc = tm6000_i2c_recv_regs(dev, 0xa0, i, p, 1); + if (rc < 1) { + if (p == dev->eedata) + goto noeeprom; + else { + printk(KERN_WARNING + "%s: i2c eeprom read error (err=%d)\n", + dev->name, rc); + } + return -EINVAL; + } + dev->eedata_size++; + p++; + if (0 == (i % 16)) + printk(KERN_INFO "%s: i2c eeprom %02x:", dev->name, i); + printk(KERN_CONT " %02x", dev->eedata[i]); + if ((dev->eedata[i] >= ' ') && (dev->eedata[i] <= 'z')) + bytes[i%16] = dev->eedata[i]; + else + bytes[i%16] = '.'; + + i++; + + if (0 == (i % 16)) { + bytes[16] = '\0'; + printk(KERN_CONT " %s\n", bytes); + } + } + if (0 != (i%16)) { + bytes[i%16] = '\0'; + for (i %= 16; i < 16; i++) + printk(KERN_CONT " "); + printk(KERN_CONT " %s\n", bytes); + } + + return 0; + +noeeprom: + printk(KERN_INFO "%s: Huh, no eeprom present (err=%d)?\n", + dev->name, rc); + return -EINVAL; +} + +/* ----------------------------------------------------------- */ + +/* + * functionality() + */ +static u32 functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm tm6000_algo = { + .master_xfer = tm6000_i2c_xfer, + .functionality = functionality, +}; + +/* ----------------------------------------------------------- */ + +/* + * tm6000_i2c_register() + * register i2c bus + */ +int tm6000_i2c_register(struct tm6000_core *dev) +{ + int rc; + + dev->i2c_adap.owner = THIS_MODULE; + dev->i2c_adap.algo = &tm6000_algo; + dev->i2c_adap.dev.parent = &dev->udev->dev; + strscpy(dev->i2c_adap.name, dev->name, sizeof(dev->i2c_adap.name)); + dev->i2c_adap.algo_data = dev; + i2c_set_adapdata(&dev->i2c_adap, &dev->v4l2_dev); + rc = i2c_add_adapter(&dev->i2c_adap); + if (rc) + return rc; + + dev->i2c_client.adapter = &dev->i2c_adap; + strscpy(dev->i2c_client.name, "tm6000 internal", I2C_NAME_SIZE); + tm6000_i2c_eeprom(dev); + + return 0; +} + +/* + * tm6000_i2c_unregister() + * unregister i2c_bus + */ +int tm6000_i2c_unregister(struct tm6000_core *dev) +{ + i2c_del_adapter(&dev->i2c_adap); + return 0; +} diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-input.c b/drivers/staging/media/deprecated/tm6000/tm6000-input.c new file mode 100644 index 000000000..5136e9e20 --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-input.c @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * tm6000-input.c - driver for TM5600/TM6000/TM6010 USB video capture devices + * + * Copyright (C) 2010 Stefan Ringel + */ + +#include +#include +#include + +#include +#include + +#include + +#include "tm6000.h" +#include "tm6000-regs.h" + +static unsigned int ir_debug; +module_param(ir_debug, int, 0644); +MODULE_PARM_DESC(ir_debug, "debug message level"); + +static unsigned int enable_ir = 1; +module_param(enable_ir, int, 0644); +MODULE_PARM_DESC(enable_ir, "enable ir (default is enable)"); + +static unsigned int ir_clock_mhz = 12; +module_param(ir_clock_mhz, int, 0644); +MODULE_PARM_DESC(ir_clock_mhz, "ir clock, in MHz"); + +#define URB_SUBMIT_DELAY 100 /* ms - Delay to submit an URB request on retrial and init */ +#define URB_INT_LED_DELAY 100 /* ms - Delay to turn led on again on int mode */ + +#undef dprintk + +#define dprintk(level, fmt, arg...) do {\ + if (ir_debug >= level) \ + printk(KERN_DEBUG "%s/ir: " fmt, ir->name , ## arg); \ + } while (0) + +struct tm6000_ir_poll_result { + u16 rc_data; +}; + +struct tm6000_IR { + struct tm6000_core *dev; + struct rc_dev *rc; + char name[32]; + char phys[32]; + + /* poll expernal decoder */ + int polling; + struct delayed_work work; + u8 wait:1; + u8 pwled:2; + u8 submit_urb:1; + struct urb *int_urb; + + /* IR device properties */ + u64 rc_proto; +}; + +void tm6000_ir_wait(struct tm6000_core *dev, u8 state) +{ + struct tm6000_IR *ir = dev->ir; + + if (!dev->ir) + return; + + dprintk(2, "%s: %i\n",__func__, ir->wait); + + if (state) + ir->wait = 1; + else + ir->wait = 0; +} + +static int tm6000_ir_config(struct tm6000_IR *ir) +{ + struct tm6000_core *dev = ir->dev; + u32 pulse = 0, leader = 0; + + dprintk(2, "%s\n",__func__); + + /* + * The IR decoder supports RC-5 or NEC, with a configurable timing. + * The timing configuration there is not that accurate, as it uses + * approximate values. The NEC spec mentions a 562.5 unit period, + * and RC-5 uses a 888.8 period. + * Currently, driver assumes a clock provided by a 12 MHz XTAL, but + * a modprobe parameter can adjust it. + * Adjustments are required for other timings. + * It seems that the 900ms timing for NEC is used to detect a RC-5 + * IR, in order to discard such decoding + */ + + switch (ir->rc_proto) { + case RC_PROTO_BIT_NEC: + leader = 900; /* ms */ + pulse = 700; /* ms - the actual value would be 562 */ + break; + default: + case RC_PROTO_BIT_RC5: + leader = 900; /* ms - from the NEC decoding */ + pulse = 1780; /* ms - The actual value would be 1776 */ + break; + } + + pulse = ir_clock_mhz * pulse; + leader = ir_clock_mhz * leader; + if (ir->rc_proto == RC_PROTO_BIT_NEC) + leader = leader | 0x8000; + + dprintk(2, "%s: %s, %d MHz, leader = 0x%04x, pulse = 0x%06x \n", + __func__, + (ir->rc_proto == RC_PROTO_BIT_NEC) ? "NEC" : "RC-5", + ir_clock_mhz, leader, pulse); + + /* Remote WAKEUP = enable, normal mode, from IR decoder output */ + tm6000_set_reg(dev, TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe); + + /* Enable IR reception on non-busrt mode */ + tm6000_set_reg(dev, TM6010_REQ07_RD8_IR, 0x2f); + + /* IR_WKUP_SEL = Low byte in decoded IR data */ + tm6000_set_reg(dev, TM6010_REQ07_RDA_IR_WAKEUP_SEL, 0xff); + /* IR_WKU_ADD code */ + tm6000_set_reg(dev, TM6010_REQ07_RDB_IR_WAKEUP_ADD, 0xff); + + tm6000_set_reg(dev, TM6010_REQ07_RDC_IR_LEADER1, leader >> 8); + tm6000_set_reg(dev, TM6010_REQ07_RDD_IR_LEADER0, leader); + + tm6000_set_reg(dev, TM6010_REQ07_RDE_IR_PULSE_CNT1, pulse >> 8); + tm6000_set_reg(dev, TM6010_REQ07_RDF_IR_PULSE_CNT0, pulse); + + if (!ir->polling) + tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 2, 0); + else + tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 2, 1); + msleep(10); + + /* Shows that IR is working via the LED */ + tm6000_flash_led(dev, 0); + msleep(100); + tm6000_flash_led(dev, 1); + ir->pwled = 1; + + return 0; +} + +static void tm6000_ir_keydown(struct tm6000_IR *ir, + const char *buf, unsigned int len) +{ + u8 device, command; + u32 scancode; + enum rc_proto protocol; + + if (len < 1) + return; + + command = buf[0]; + device = (len > 1 ? buf[1] : 0x0); + switch (ir->rc_proto) { + case RC_PROTO_BIT_RC5: + protocol = RC_PROTO_RC5; + scancode = RC_SCANCODE_RC5(device, command); + break; + case RC_PROTO_BIT_NEC: + protocol = RC_PROTO_NEC; + scancode = RC_SCANCODE_NEC(device, command); + break; + default: + protocol = RC_PROTO_OTHER; + scancode = RC_SCANCODE_OTHER(device << 8 | command); + break; + } + + dprintk(1, "%s, protocol: 0x%04x, scancode: 0x%08x\n", + __func__, protocol, scancode); + rc_keydown(ir->rc, protocol, scancode, 0); +} + +static void tm6000_ir_urb_received(struct urb *urb) +{ + struct tm6000_core *dev = urb->context; + struct tm6000_IR *ir = dev->ir; + char *buf; + + dprintk(2, "%s\n",__func__); + if (urb->status < 0 || urb->actual_length <= 0) { + printk(KERN_INFO "tm6000: IR URB failure: status: %i, length %i\n", + urb->status, urb->actual_length); + ir->submit_urb = 1; + schedule_delayed_work(&ir->work, msecs_to_jiffies(URB_SUBMIT_DELAY)); + return; + } + buf = urb->transfer_buffer; + + if (ir_debug) + print_hex_dump(KERN_DEBUG, "tm6000: IR data: ", + DUMP_PREFIX_OFFSET,16, 1, + buf, urb->actual_length, false); + + tm6000_ir_keydown(ir, urb->transfer_buffer, urb->actual_length); + + usb_submit_urb(urb, GFP_ATOMIC); + /* + * Flash the led. We can't do it here, as it is running on IRQ context. + * So, use the scheduler to do it, in a few ms. + */ + ir->pwled = 2; + schedule_delayed_work(&ir->work, msecs_to_jiffies(10)); +} + +static void tm6000_ir_handle_key(struct work_struct *work) +{ + struct tm6000_IR *ir = container_of(work, struct tm6000_IR, work.work); + struct tm6000_core *dev = ir->dev; + int rc; + u8 buf[2]; + + if (ir->wait) + return; + + dprintk(3, "%s\n",__func__); + + rc = tm6000_read_write_usb(dev, USB_DIR_IN | + USB_TYPE_VENDOR | USB_RECIP_DEVICE, + REQ_02_GET_IR_CODE, 0, 0, buf, 2); + if (rc < 0) + return; + + /* Check if something was read */ + if ((buf[0] & 0xff) == 0xff) { + if (!ir->pwled) { + tm6000_flash_led(dev, 1); + ir->pwled = 1; + } + return; + } + + tm6000_ir_keydown(ir, buf, rc); + tm6000_flash_led(dev, 0); + ir->pwled = 0; + + /* Re-schedule polling */ + schedule_delayed_work(&ir->work, msecs_to_jiffies(ir->polling)); +} + +static void tm6000_ir_int_work(struct work_struct *work) +{ + struct tm6000_IR *ir = container_of(work, struct tm6000_IR, work.work); + struct tm6000_core *dev = ir->dev; + int rc; + + dprintk(3, "%s, submit_urb = %d, pwled = %d\n",__func__, ir->submit_urb, + ir->pwled); + + if (ir->submit_urb) { + dprintk(3, "Resubmit urb\n"); + tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 2, 0); + + rc = usb_submit_urb(ir->int_urb, GFP_ATOMIC); + if (rc < 0) { + printk(KERN_ERR "tm6000: Can't submit an IR interrupt. Error %i\n", + rc); + /* Retry in 100 ms */ + schedule_delayed_work(&ir->work, msecs_to_jiffies(URB_SUBMIT_DELAY)); + return; + } + ir->submit_urb = 0; + } + + /* Led is enabled only if USB submit doesn't fail */ + if (ir->pwled == 2) { + tm6000_flash_led(dev, 0); + ir->pwled = 0; + schedule_delayed_work(&ir->work, msecs_to_jiffies(URB_INT_LED_DELAY)); + } else if (!ir->pwled) { + tm6000_flash_led(dev, 1); + ir->pwled = 1; + } +} + +static int tm6000_ir_start(struct rc_dev *rc) +{ + struct tm6000_IR *ir = rc->priv; + + dprintk(2, "%s\n",__func__); + + schedule_delayed_work(&ir->work, 0); + + return 0; +} + +static void tm6000_ir_stop(struct rc_dev *rc) +{ + struct tm6000_IR *ir = rc->priv; + + dprintk(2, "%s\n",__func__); + + cancel_delayed_work_sync(&ir->work); +} + +static int tm6000_ir_change_protocol(struct rc_dev *rc, u64 *rc_proto) +{ + struct tm6000_IR *ir = rc->priv; + + if (!ir) + return 0; + + dprintk(2, "%s\n",__func__); + + ir->rc_proto = *rc_proto; + + tm6000_ir_config(ir); + /* TODO */ + return 0; +} + +static int __tm6000_ir_int_start(struct rc_dev *rc) +{ + struct tm6000_IR *ir = rc->priv; + struct tm6000_core *dev; + int pipe, size; + int err = -ENOMEM; + + if (!ir) + return -ENODEV; + dev = ir->dev; + + dprintk(2, "%s\n",__func__); + + ir->int_urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!ir->int_urb) + return -ENOMEM; + + pipe = usb_rcvintpipe(dev->udev, + dev->int_in.endp->desc.bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK); + + size = usb_maxpacket(dev->udev, pipe); + dprintk(1, "IR max size: %d\n", size); + + ir->int_urb->transfer_buffer = kzalloc(size, GFP_ATOMIC); + if (!ir->int_urb->transfer_buffer) { + usb_free_urb(ir->int_urb); + return err; + } + dprintk(1, "int interval: %d\n", dev->int_in.endp->desc.bInterval); + + usb_fill_int_urb(ir->int_urb, dev->udev, pipe, + ir->int_urb->transfer_buffer, size, + tm6000_ir_urb_received, dev, + dev->int_in.endp->desc.bInterval); + + ir->submit_urb = 1; + schedule_delayed_work(&ir->work, msecs_to_jiffies(URB_SUBMIT_DELAY)); + + return 0; +} + +static void __tm6000_ir_int_stop(struct rc_dev *rc) +{ + struct tm6000_IR *ir = rc->priv; + + if (!ir || !ir->int_urb) + return; + + dprintk(2, "%s\n",__func__); + + usb_kill_urb(ir->int_urb); + kfree(ir->int_urb->transfer_buffer); + usb_free_urb(ir->int_urb); + ir->int_urb = NULL; +} + +int tm6000_ir_int_start(struct tm6000_core *dev) +{ + struct tm6000_IR *ir = dev->ir; + + if (!ir) + return 0; + + return __tm6000_ir_int_start(ir->rc); +} + +void tm6000_ir_int_stop(struct tm6000_core *dev) +{ + struct tm6000_IR *ir = dev->ir; + + if (!ir || !ir->rc) + return; + + __tm6000_ir_int_stop(ir->rc); +} + +int tm6000_ir_init(struct tm6000_core *dev) +{ + struct tm6000_IR *ir; + struct rc_dev *rc; + int err = -ENOMEM; + u64 rc_proto; + + if (!enable_ir) + return -ENODEV; + + if (!dev->caps.has_remote) + return 0; + + if (!dev->ir_codes) + return 0; + + ir = kzalloc(sizeof(*ir), GFP_ATOMIC); + rc = rc_allocate_device(RC_DRIVER_SCANCODE); + if (!ir || !rc) + goto out; + + dprintk(2, "%s\n", __func__); + + /* record handles to ourself */ + ir->dev = dev; + dev->ir = ir; + ir->rc = rc; + + /* input setup */ + rc->allowed_protocols = RC_PROTO_BIT_RC5 | RC_PROTO_BIT_NEC; + /* Needed, in order to support NEC remotes with 24 or 32 bits */ + rc->scancode_mask = 0xffff; + rc->priv = ir; + rc->change_protocol = tm6000_ir_change_protocol; + if (dev->int_in.endp) { + rc->open = __tm6000_ir_int_start; + rc->close = __tm6000_ir_int_stop; + INIT_DELAYED_WORK(&ir->work, tm6000_ir_int_work); + } else { + rc->open = tm6000_ir_start; + rc->close = tm6000_ir_stop; + ir->polling = 50; + INIT_DELAYED_WORK(&ir->work, tm6000_ir_handle_key); + } + + snprintf(ir->name, sizeof(ir->name), "tm5600/60x0 IR (%s)", + dev->name); + + usb_make_path(dev->udev, ir->phys, sizeof(ir->phys)); + strlcat(ir->phys, "/input0", sizeof(ir->phys)); + + rc_proto = RC_PROTO_BIT_UNKNOWN; + tm6000_ir_change_protocol(rc, &rc_proto); + + rc->device_name = ir->name; + rc->input_phys = ir->phys; + rc->input_id.bustype = BUS_USB; + rc->input_id.version = 1; + rc->input_id.vendor = le16_to_cpu(dev->udev->descriptor.idVendor); + rc->input_id.product = le16_to_cpu(dev->udev->descriptor.idProduct); + rc->map_name = dev->ir_codes; + rc->driver_name = "tm6000"; + rc->dev.parent = &dev->udev->dev; + + /* ir register */ + err = rc_register_device(rc); + if (err) + goto out; + + return 0; + +out: + dev->ir = NULL; + rc_free_device(rc); + kfree(ir); + return err; +} + +int tm6000_ir_fini(struct tm6000_core *dev) +{ + struct tm6000_IR *ir = dev->ir; + + /* skip detach on non attached board */ + + if (!ir) + return 0; + + dprintk(2, "%s\n",__func__); + + if (!ir->polling) + __tm6000_ir_int_stop(ir->rc); + + tm6000_ir_stop(ir->rc); + + /* Turn off the led */ + tm6000_flash_led(dev, 0); + ir->pwled = 0; + + rc_unregister_device(ir->rc); + + kfree(ir); + dev->ir = NULL; + + return 0; +} diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-regs.h b/drivers/staging/media/deprecated/tm6000/tm6000-regs.h new file mode 100644 index 000000000..6a181f2e7 --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-regs.h @@ -0,0 +1,588 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * tm6000-regs.h - driver for TM5600/TM6000/TM6010 USB video capture devices + * + * Copyright (c) 2006-2007 Mauro Carvalho Chehab + */ + +/* + * Define TV Master TM5600/TM6000/TM6010 Request codes + */ +#define REQ_00_SET_IR_VALUE 0 +#define REQ_01_SET_WAKEUP_IRCODE 1 +#define REQ_02_GET_IR_CODE 2 +#define REQ_03_SET_GET_MCU_PIN 3 +#define REQ_04_EN_DISABLE_MCU_INT 4 +#define REQ_05_SET_GET_USBREG 5 + /* Write: RegNum, Value, 0 */ + /* Read : RegNum, Value, 1, RegStatus */ +#define REQ_06_SET_GET_USBREG_BIT 6 +#define REQ_07_SET_GET_AVREG 7 + /* Write: RegNum, Value, 0 */ + /* Read : RegNum, Value, 1, RegStatus */ +#define REQ_08_SET_GET_AVREG_BIT 8 +#define REQ_09_SET_GET_TUNER_FQ 9 +#define REQ_10_SET_TUNER_SYSTEM 10 +#define REQ_11_SET_EEPROM_ADDR 11 +#define REQ_12_SET_GET_EEPROMBYTE 12 +#define REQ_13_GET_EEPROM_SEQREAD 13 +#define REQ_14_SET_GET_I2C_WR2_RDN 14 +#define REQ_15_SET_GET_I2CBYTE 15 + /* Write: Subaddr, Slave Addr, value, 0 */ + /* Read : Subaddr, Slave Addr, value, 1 */ +#define REQ_16_SET_GET_I2C_WR1_RDN 16 + /* Subaddr, Slave Addr, 0, length */ +#define REQ_17_SET_GET_I2CFP 17 + /* Write: Slave Addr, register, value */ + /* Read : Slave Addr, register, 2, data */ +#define REQ_20_DATA_TRANSFER 20 +#define REQ_30_I2C_WRITE 30 +#define REQ_31_I2C_READ 31 +#define REQ_35_AFTEK_TUNER_READ 35 +#define REQ_40_GET_VERSION 40 +#define REQ_50_SET_START 50 +#define REQ_51_SET_STOP 51 +#define REQ_52_TRANSMIT_DATA 52 +#define REQ_53_SPI_INITIAL 53 +#define REQ_54_SPI_SETSTART 54 +#define REQ_55_SPI_INOUTDATA 55 +#define REQ_56_SPI_SETSTOP 56 + +/* + * Define TV Master TM5600/TM6000/TM6010 GPIO lines + */ + +#define TM6000_GPIO_CLK 0x101 +#define TM6000_GPIO_DATA 0x100 + +#define TM6000_GPIO_1 0x102 +#define TM6000_GPIO_2 0x103 +#define TM6000_GPIO_3 0x104 +#define TM6000_GPIO_4 0x300 +#define TM6000_GPIO_5 0x301 +#define TM6000_GPIO_6 0x304 +#define TM6000_GPIO_7 0x305 + +/* tm6010 defines GPIO with different values */ +#define TM6010_GPIO_0 0x0102 +#define TM6010_GPIO_1 0x0103 +#define TM6010_GPIO_2 0x0104 +#define TM6010_GPIO_3 0x0105 +#define TM6010_GPIO_4 0x0106 +#define TM6010_GPIO_5 0x0107 +#define TM6010_GPIO_6 0x0300 +#define TM6010_GPIO_7 0x0301 +#define TM6010_GPIO_9 0x0305 +/* + * Define TV Master TM5600/TM6000/TM6010 URB message codes and length + */ + +enum { + TM6000_URB_MSG_VIDEO = 1, + TM6000_URB_MSG_AUDIO, + TM6000_URB_MSG_VBI, + TM6000_URB_MSG_PTS, + TM6000_URB_MSG_ERR, +}; + +/* Define specific TM6000 Video decoder registers */ +#define TM6000_REQ07_RD8_TEST_SEL 0x07, 0xd8 +#define TM6000_REQ07_RD9_A_SIM_SEL 0x07, 0xd9 +#define TM6000_REQ07_RDA_CLK_SEL 0x07, 0xda +#define TM6000_REQ07_RDB_OUT_SEL 0x07, 0xdb +#define TM6000_REQ07_RDC_NSEL_I2S 0x07, 0xdc +#define TM6000_REQ07_RDD_GPIO2_MDRV 0x07, 0xdd +#define TM6000_REQ07_RDE_GPIO1_MDRV 0x07, 0xde +#define TM6000_REQ07_RDF_PWDOWN_ACLK 0x07, 0xdf +#define TM6000_REQ07_RE0_VADC_REF_CTL 0x07, 0xe0 +#define TM6000_REQ07_RE1_VADC_DACLIMP 0x07, 0xe1 +#define TM6000_REQ07_RE2_VADC_STATUS_CTL 0x07, 0xe2 +#define TM6000_REQ07_RE3_VADC_INP_LPF_SEL1 0x07, 0xe3 +#define TM6000_REQ07_RE4_VADC_TARGET1 0x07, 0xe4 +#define TM6000_REQ07_RE5_VADC_INP_LPF_SEL2 0x07, 0xe5 +#define TM6000_REQ07_RE6_VADC_TARGET2 0x07, 0xe6 +#define TM6000_REQ07_RE7_VADC_AGAIN_CTL 0x07, 0xe7 +#define TM6000_REQ07_RE8_VADC_PWDOWN_CTL 0x07, 0xe8 +#define TM6000_REQ07_RE9_VADC_INPUT_CTL1 0x07, 0xe9 +#define TM6000_REQ07_REA_VADC_INPUT_CTL2 0x07, 0xea +#define TM6000_REQ07_REB_VADC_AADC_MODE 0x07, 0xeb +#define TM6000_REQ07_REC_VADC_AADC_LVOL 0x07, 0xec +#define TM6000_REQ07_RED_VADC_AADC_RVOL 0x07, 0xed +#define TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL 0x07, 0xee +#define TM6000_REQ07_REF_VADC_GAIN_MAP_CTL 0x07, 0xef +#define TM6000_REQ07_RFD_BIST_ERR_VST_LOW 0x07, 0xfd +#define TM6000_REQ07_RFE_BIST_ERR_VST_HIGH 0x07, 0xfe + +/* Define TM6000/TM6010 Video decoder registers */ +#define TM6010_REQ07_R00_VIDEO_CONTROL0 0x07, 0x00 +#define TM6010_REQ07_R01_VIDEO_CONTROL1 0x07, 0x01 +#define TM6010_REQ07_R02_VIDEO_CONTROL2 0x07, 0x02 +#define TM6010_REQ07_R03_YC_SEP_CONTROL 0x07, 0x03 +#define TM6010_REQ07_R04_LUMA_HAGC_CONTROL 0x07, 0x04 +#define TM6010_REQ07_R05_NOISE_THRESHOLD 0x07, 0x05 +#define TM6010_REQ07_R06_AGC_GATE_THRESHOLD 0x07, 0x06 +#define TM6010_REQ07_R07_OUTPUT_CONTROL 0x07, 0x07 +#define TM6010_REQ07_R08_LUMA_CONTRAST_ADJ 0x07, 0x08 +#define TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ 0x07, 0x09 +#define TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ 0x07, 0x0a +#define TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ 0x07, 0x0b +#define TM6010_REQ07_R0C_CHROMA_AGC_CONTROL 0x07, 0x0c +#define TM6010_REQ07_R0D_CHROMA_KILL_LEVEL 0x07, 0x0d +#define TM6010_REQ07_R0F_CHROMA_AUTO_POSITION 0x07, 0x0f +#define TM6010_REQ07_R10_AGC_PEAK_NOMINAL 0x07, 0x10 +#define TM6010_REQ07_R11_AGC_PEAK_CONTROL 0x07, 0x11 +#define TM6010_REQ07_R12_AGC_GATE_STARTH 0x07, 0x12 +#define TM6010_REQ07_R13_AGC_GATE_STARTL 0x07, 0x13 +#define TM6010_REQ07_R14_AGC_GATE_WIDTH 0x07, 0x14 +#define TM6010_REQ07_R15_AGC_BP_DELAY 0x07, 0x15 +#define TM6010_REQ07_R16_LOCK_COUNT 0x07, 0x16 +#define TM6010_REQ07_R17_HLOOP_MAXSTATE 0x07, 0x17 +#define TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3 0x07, 0x18 +#define TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2 0x07, 0x19 +#define TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1 0x07, 0x1a +#define TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0 0x07, 0x1b +#define TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3 0x07, 0x1c +#define TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2 0x07, 0x1d +#define TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1 0x07, 0x1e +#define TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0 0x07, 0x1f +#define TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME 0x07, 0x20 +#define TM6010_REQ07_R21_HSYNC_PHASE_OFFSET 0x07, 0x21 +#define TM6010_REQ07_R22_HSYNC_PLL_START_TIME 0x07, 0x22 +#define TM6010_REQ07_R23_HSYNC_PLL_END_TIME 0x07, 0x23 +#define TM6010_REQ07_R24_HSYNC_TIP_START_TIME 0x07, 0x24 +#define TM6010_REQ07_R25_HSYNC_TIP_END_TIME 0x07, 0x25 +#define TM6010_REQ07_R26_HSYNC_RISING_EDGE_START 0x07, 0x26 +#define TM6010_REQ07_R27_HSYNC_RISING_EDGE_END 0x07, 0x27 +#define TM6010_REQ07_R28_BACKPORCH_START 0x07, 0x28 +#define TM6010_REQ07_R29_BACKPORCH_END 0x07, 0x29 +#define TM6010_REQ07_R2A_HSYNC_FILTER_START 0x07, 0x2a +#define TM6010_REQ07_R2B_HSYNC_FILTER_END 0x07, 0x2b +#define TM6010_REQ07_R2C_CHROMA_BURST_START 0x07, 0x2c +#define TM6010_REQ07_R2D_CHROMA_BURST_END 0x07, 0x2d +#define TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART 0x07, 0x2e +#define TM6010_REQ07_R2F_ACTIVE_VIDEO_HWIDTH 0x07, 0x2f +#define TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART 0x07, 0x30 +#define TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT 0x07, 0x31 +#define TM6010_REQ07_R32_VSYNC_HLOCK_MIN 0x07, 0x32 +#define TM6010_REQ07_R33_VSYNC_HLOCK_MAX 0x07, 0x33 +#define TM6010_REQ07_R34_VSYNC_AGC_MIN 0x07, 0x34 +#define TM6010_REQ07_R35_VSYNC_AGC_MAX 0x07, 0x35 +#define TM6010_REQ07_R36_VSYNC_VBI_MIN 0x07, 0x36 +#define TM6010_REQ07_R37_VSYNC_VBI_MAX 0x07, 0x37 +#define TM6010_REQ07_R38_VSYNC_THRESHOLD 0x07, 0x38 +#define TM6010_REQ07_R39_VSYNC_TIME_CONSTANT 0x07, 0x39 +#define TM6010_REQ07_R3A_STATUS1 0x07, 0x3a +#define TM6010_REQ07_R3B_STATUS2 0x07, 0x3b +#define TM6010_REQ07_R3C_STATUS3 0x07, 0x3c +#define TM6010_REQ07_R3F_RESET 0x07, 0x3f +#define TM6010_REQ07_R40_TELETEXT_VBI_CODE0 0x07, 0x40 +#define TM6010_REQ07_R41_TELETEXT_VBI_CODE1 0x07, 0x41 +#define TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL 0x07, 0x42 +#define TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7 0x07, 0x43 +#define TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8 0x07, 0x44 +#define TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9 0x07, 0x45 +#define TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10 0x07, 0x46 +#define TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11 0x07, 0x47 +#define TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12 0x07, 0x48 +#define TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13 0x07, 0x49 +#define TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14 0x07, 0x4a +#define TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15 0x07, 0x4b +#define TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16 0x07, 0x4c +#define TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17 0x07, 0x4d +#define TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18 0x07, 0x4e +#define TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19 0x07, 0x4f +#define TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20 0x07, 0x50 +#define TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21 0x07, 0x51 +#define TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22 0x07, 0x52 +#define TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23 0x07, 0x53 +#define TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES 0x07, 0x54 +#define TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN 0x07, 0x55 +#define TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN 0x07, 0x56 +#define TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN 0x07, 0x57 +#define TM6010_REQ07_R58_VBI_CAPTION_DTO1 0x07, 0x58 +#define TM6010_REQ07_R59_VBI_CAPTION_DTO0 0x07, 0x59 +#define TM6010_REQ07_R5A_VBI_TELETEXT_DTO1 0x07, 0x5a +#define TM6010_REQ07_R5B_VBI_TELETEXT_DTO0 0x07, 0x5b +#define TM6010_REQ07_R5C_VBI_WSS625_DTO1 0x07, 0x5c +#define TM6010_REQ07_R5D_VBI_WSS625_DTO0 0x07, 0x5d +#define TM6010_REQ07_R5E_VBI_CAPTION_FRAME_START 0x07, 0x5e +#define TM6010_REQ07_R5F_VBI_WSS625_FRAME_START 0x07, 0x5f +#define TM6010_REQ07_R60_TELETEXT_FRAME_START 0x07, 0x60 +#define TM6010_REQ07_R61_VBI_CCDATA1 0x07, 0x61 +#define TM6010_REQ07_R62_VBI_CCDATA2 0x07, 0x62 +#define TM6010_REQ07_R63_VBI_WSS625_DATA1 0x07, 0x63 +#define TM6010_REQ07_R64_VBI_WSS625_DATA2 0x07, 0x64 +#define TM6010_REQ07_R65_VBI_DATA_STATUS 0x07, 0x65 +#define TM6010_REQ07_R66_VBI_CAPTION_START 0x07, 0x66 +#define TM6010_REQ07_R67_VBI_WSS625_START 0x07, 0x67 +#define TM6010_REQ07_R68_VBI_TELETEXT_START 0x07, 0x68 +#define TM6010_REQ07_R70_HSYNC_DTO_INC_STATUS3 0x07, 0x70 +#define TM6010_REQ07_R71_HSYNC_DTO_INC_STATUS2 0x07, 0x71 +#define TM6010_REQ07_R72_HSYNC_DTO_INC_STATUS1 0x07, 0x72 +#define TM6010_REQ07_R73_HSYNC_DTO_INC_STATUS0 0x07, 0x73 +#define TM6010_REQ07_R74_CHROMA_DTO_INC_STATUS3 0x07, 0x74 +#define TM6010_REQ07_R75_CHROMA_DTO_INC_STATUS2 0x07, 0x75 +#define TM6010_REQ07_R76_CHROMA_DTO_INC_STATUS1 0x07, 0x76 +#define TM6010_REQ07_R77_CHROMA_DTO_INC_STATUS0 0x07, 0x77 +#define TM6010_REQ07_R78_AGC_AGAIN_STATUS 0x07, 0x78 +#define TM6010_REQ07_R79_AGC_DGAIN_STATUS 0x07, 0x79 +#define TM6010_REQ07_R7A_CHROMA_MAG_STATUS 0x07, 0x7a +#define TM6010_REQ07_R7B_CHROMA_GAIN_STATUS1 0x07, 0x7b +#define TM6010_REQ07_R7C_CHROMA_GAIN_STATUS0 0x07, 0x7c +#define TM6010_REQ07_R7D_CORDIC_FREQ_STATUS 0x07, 0x7d +#define TM6010_REQ07_R7F_STATUS_NOISE 0x07, 0x7f +#define TM6010_REQ07_R80_COMB_FILTER_TRESHOLD 0x07, 0x80 +#define TM6010_REQ07_R82_COMB_FILTER_CONFIG 0x07, 0x82 +#define TM6010_REQ07_R83_CHROMA_LOCK_CONFIG 0x07, 0x83 +#define TM6010_REQ07_R84_NOISE_NTSC_C 0x07, 0x84 +#define TM6010_REQ07_R85_NOISE_PAL_C 0x07, 0x85 +#define TM6010_REQ07_R86_NOISE_PHASE_C 0x07, 0x86 +#define TM6010_REQ07_R87_NOISE_PHASE_Y 0x07, 0x87 +#define TM6010_REQ07_R8A_CHROMA_LOOPFILTER_STATE 0x07, 0x8a +#define TM6010_REQ07_R8B_CHROMA_HRESAMPLER 0x07, 0x8b +#define TM6010_REQ07_R8D_CPUMP_DELAY_ADJ 0x07, 0x8d +#define TM6010_REQ07_R8E_CPUMP_ADJ 0x07, 0x8e +#define TM6010_REQ07_R8F_CPUMP_DELAY 0x07, 0x8f + +/* Define TM6000/TM6010 Miscellaneous registers */ +#define TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE 0x07, 0xc0 +#define TM6010_REQ07_RC1_TRESHOLD 0x07, 0xc1 +#define TM6010_REQ07_RC2_HSYNC_WIDTH 0x07, 0xc2 +#define TM6010_REQ07_RC3_HSTART1 0x07, 0xc3 +#define TM6010_REQ07_RC4_HSTART0 0x07, 0xc4 +#define TM6010_REQ07_RC5_HEND1 0x07, 0xc5 +#define TM6010_REQ07_RC6_HEND0 0x07, 0xc6 +#define TM6010_REQ07_RC7_VSTART1 0x07, 0xc7 +#define TM6010_REQ07_RC8_VSTART0 0x07, 0xc8 +#define TM6010_REQ07_RC9_VEND1 0x07, 0xc9 +#define TM6010_REQ07_RCA_VEND0 0x07, 0xca +#define TM6010_REQ07_RCB_DELAY 0x07, 0xcb +/* ONLY for TM6010 */ +#define TM6010_REQ07_RCC_ACTIVE_IF 0x07, 0xcc +#define TM6010_REQ07_RCC_ACTIVE_IF_VIDEO_ENABLE (1 << 5) +#define TM6010_REQ07_RCC_ACTIVE_IF_AUDIO_ENABLE (1 << 6) +#define TM6010_REQ07_RD0_USB_PERIPHERY_CONTROL 0x07, 0xd0 +#define TM6010_REQ07_RD1_ADDR_FOR_REQ1 0x07, 0xd1 +#define TM6010_REQ07_RD2_ADDR_FOR_REQ2 0x07, 0xd2 +#define TM6010_REQ07_RD3_ADDR_FOR_REQ3 0x07, 0xd3 +#define TM6010_REQ07_RD4_ADDR_FOR_REQ4 0x07, 0xd4 +#define TM6010_REQ07_RD5_POWERSAVE 0x07, 0xd5 +#define TM6010_REQ07_RD6_ENDP_REQ1_REQ2 0x07, 0xd6 +#define TM6010_REQ07_RD7_ENDP_REQ3_REQ4 0x07, 0xd7 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RD8_IR 0x07, 0xd8 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RD9_IR_BSIZE 0x07, 0xd9 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RDA_IR_WAKEUP_SEL 0x07, 0xda +/* ONLY for TM6010 */ +#define TM6010_REQ07_RDB_IR_WAKEUP_ADD 0x07, 0xdb +/* ONLY for TM6010 */ +#define TM6010_REQ07_RDC_IR_LEADER1 0x07, 0xdc +/* ONLY for TM6010 */ +#define TM6010_REQ07_RDD_IR_LEADER0 0x07, 0xdd +/* ONLY for TM6010 */ +#define TM6010_REQ07_RDE_IR_PULSE_CNT1 0x07, 0xde +/* ONLY for TM6010 */ +#define TM6010_REQ07_RDF_IR_PULSE_CNT0 0x07, 0xdf +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE0_DVIDEO_SOURCE 0x07, 0xe0 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE0_DVIDEO_SOURCE_IF 0x07, 0xe1 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE2_OUT_SEL2 0x07, 0xe2 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE3_OUT_SEL1 0x07, 0xe3 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE4_OUT_SEL0 0x07, 0xe4 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE5_REMOTE_WAKEUP 0x07, 0xe5 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE7_PUB_GPIO 0x07, 0xe7 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE8_TYPESEL_MOS_I2S 0x07, 0xe8 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RE9_TYPESEL_MOS_TS 0x07, 0xe9 +/* ONLY for TM6010 */ +#define TM6010_REQ07_REA_TYPESEL_MOS_CCIR 0x07, 0xea +/* ONLY for TM6010 */ +#define TM6010_REQ07_RF0_BIST_CRC_RESULT0 0x07, 0xf0 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RF1_BIST_CRC_RESULT1 0x07, 0xf1 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RF2_BIST_CRC_RESULT2 0x07, 0xf2 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RF3_BIST_CRC_RESULT3 0x07, 0xf3 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RF4_BIST_ERR_VST2 0x07, 0xf4 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RF5_BIST_ERR_VST1 0x07, 0xf5 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RF6_BIST_ERR_VST0 0x07, 0xf6 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RF7_BIST 0x07, 0xf7 +/* ONLY for TM6010 */ +#define TM6010_REQ07_RFE_POWER_DOWN 0x07, 0xfe +#define TM6010_REQ07_RFF_SOFT_RESET 0x07, 0xff + +/* Define TM6000/TM6010 USB registers */ +#define TM6010_REQ05_R00_MAIN_CTRL 0x05, 0x00 +#define TM6010_REQ05_R01_DEVADDR 0x05, 0x01 +#define TM6010_REQ05_R02_TEST 0x05, 0x02 +#define TM6010_REQ05_R04_SOFN0 0x05, 0x04 +#define TM6010_REQ05_R05_SOFN1 0x05, 0x05 +#define TM6010_REQ05_R06_SOFTM0 0x05, 0x06 +#define TM6010_REQ05_R07_SOFTM1 0x05, 0x07 +#define TM6010_REQ05_R08_PHY_TEST 0x05, 0x08 +#define TM6010_REQ05_R09_VCTL 0x05, 0x09 +#define TM6010_REQ05_R0A_VSTA 0x05, 0x0a +#define TM6010_REQ05_R0B_CX_CFG 0x05, 0x0b +#define TM6010_REQ05_R0C_ENDP0_REG0 0x05, 0x0c +#define TM6010_REQ05_R10_GMASK 0x05, 0x10 +#define TM6010_REQ05_R11_IMASK0 0x05, 0x11 +#define TM6010_REQ05_R12_IMASK1 0x05, 0x12 +#define TM6010_REQ05_R13_IMASK2 0x05, 0x13 +#define TM6010_REQ05_R14_IMASK3 0x05, 0x14 +#define TM6010_REQ05_R15_IMASK4 0x05, 0x15 +#define TM6010_REQ05_R16_IMASK5 0x05, 0x16 +#define TM6010_REQ05_R17_IMASK6 0x05, 0x17 +#define TM6010_REQ05_R18_IMASK7 0x05, 0x18 +#define TM6010_REQ05_R19_ZEROP0 0x05, 0x19 +#define TM6010_REQ05_R1A_ZEROP1 0x05, 0x1a +#define TM6010_REQ05_R1C_FIFO_EMP0 0x05, 0x1c +#define TM6010_REQ05_R1D_FIFO_EMP1 0x05, 0x1d +#define TM6010_REQ05_R20_IRQ_GROUP 0x05, 0x20 +#define TM6010_REQ05_R21_IRQ_SOURCE0 0x05, 0x21 +#define TM6010_REQ05_R22_IRQ_SOURCE1 0x05, 0x22 +#define TM6010_REQ05_R23_IRQ_SOURCE2 0x05, 0x23 +#define TM6010_REQ05_R24_IRQ_SOURCE3 0x05, 0x24 +#define TM6010_REQ05_R25_IRQ_SOURCE4 0x05, 0x25 +#define TM6010_REQ05_R26_IRQ_SOURCE5 0x05, 0x26 +#define TM6010_REQ05_R27_IRQ_SOURCE6 0x05, 0x27 +#define TM6010_REQ05_R28_IRQ_SOURCE7 0x05, 0x28 +#define TM6010_REQ05_R29_SEQ_ERR0 0x05, 0x29 +#define TM6010_REQ05_R2A_SEQ_ERR1 0x05, 0x2a +#define TM6010_REQ05_R2B_SEQ_ABORT0 0x05, 0x2b +#define TM6010_REQ05_R2C_SEQ_ABORT1 0x05, 0x2c +#define TM6010_REQ05_R2D_TX_ZERO0 0x05, 0x2d +#define TM6010_REQ05_R2E_TX_ZERO1 0x05, 0x2e +#define TM6010_REQ05_R2F_IDLE_CNT 0x05, 0x2f +#define TM6010_REQ05_R30_FNO_P1 0x05, 0x30 +#define TM6010_REQ05_R31_FNO_P2 0x05, 0x31 +#define TM6010_REQ05_R32_FNO_P3 0x05, 0x32 +#define TM6010_REQ05_R33_FNO_P4 0x05, 0x33 +#define TM6010_REQ05_R34_FNO_P5 0x05, 0x34 +#define TM6010_REQ05_R35_FNO_P6 0x05, 0x35 +#define TM6010_REQ05_R36_FNO_P7 0x05, 0x36 +#define TM6010_REQ05_R37_FNO_P8 0x05, 0x37 +#define TM6010_REQ05_R38_FNO_P9 0x05, 0x38 +#define TM6010_REQ05_R30_FNO_P10 0x05, 0x39 +#define TM6010_REQ05_R30_FNO_P11 0x05, 0x3a +#define TM6010_REQ05_R30_FNO_P12 0x05, 0x3b +#define TM6010_REQ05_R30_FNO_P13 0x05, 0x3c +#define TM6010_REQ05_R30_FNO_P14 0x05, 0x3d +#define TM6010_REQ05_R30_FNO_P15 0x05, 0x3e +#define TM6010_REQ05_R40_IN_MAXPS_LOW1 0x05, 0x40 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH1 0x05, 0x41 +#define TM6010_REQ05_R42_IN_MAXPS_LOW2 0x05, 0x42 +#define TM6010_REQ05_R43_IN_MAXPS_HIGH2 0x05, 0x43 +#define TM6010_REQ05_R44_IN_MAXPS_LOW3 0x05, 0x44 +#define TM6010_REQ05_R45_IN_MAXPS_HIGH3 0x05, 0x45 +#define TM6010_REQ05_R46_IN_MAXPS_LOW4 0x05, 0x46 +#define TM6010_REQ05_R47_IN_MAXPS_HIGH4 0x05, 0x47 +#define TM6010_REQ05_R48_IN_MAXPS_LOW5 0x05, 0x48 +#define TM6010_REQ05_R49_IN_MAXPS_HIGH5 0x05, 0x49 +#define TM6010_REQ05_R4A_IN_MAXPS_LOW6 0x05, 0x4a +#define TM6010_REQ05_R4B_IN_MAXPS_HIGH6 0x05, 0x4b +#define TM6010_REQ05_R4C_IN_MAXPS_LOW7 0x05, 0x4c +#define TM6010_REQ05_R4D_IN_MAXPS_HIGH7 0x05, 0x4d +#define TM6010_REQ05_R4E_IN_MAXPS_LOW8 0x05, 0x4e +#define TM6010_REQ05_R4F_IN_MAXPS_HIGH8 0x05, 0x4f +#define TM6010_REQ05_R50_IN_MAXPS_LOW9 0x05, 0x50 +#define TM6010_REQ05_R51_IN_MAXPS_HIGH9 0x05, 0x51 +#define TM6010_REQ05_R40_IN_MAXPS_LOW10 0x05, 0x52 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH10 0x05, 0x53 +#define TM6010_REQ05_R40_IN_MAXPS_LOW11 0x05, 0x54 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH11 0x05, 0x55 +#define TM6010_REQ05_R40_IN_MAXPS_LOW12 0x05, 0x56 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH12 0x05, 0x57 +#define TM6010_REQ05_R40_IN_MAXPS_LOW13 0x05, 0x58 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH13 0x05, 0x59 +#define TM6010_REQ05_R40_IN_MAXPS_LOW14 0x05, 0x5a +#define TM6010_REQ05_R41_IN_MAXPS_HIGH14 0x05, 0x5b +#define TM6010_REQ05_R40_IN_MAXPS_LOW15 0x05, 0x5c +#define TM6010_REQ05_R41_IN_MAXPS_HIGH15 0x05, 0x5d +#define TM6010_REQ05_R60_OUT_MAXPS_LOW1 0x05, 0x60 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH1 0x05, 0x61 +#define TM6010_REQ05_R62_OUT_MAXPS_LOW2 0x05, 0x62 +#define TM6010_REQ05_R63_OUT_MAXPS_HIGH2 0x05, 0x63 +#define TM6010_REQ05_R64_OUT_MAXPS_LOW3 0x05, 0x64 +#define TM6010_REQ05_R65_OUT_MAXPS_HIGH3 0x05, 0x65 +#define TM6010_REQ05_R66_OUT_MAXPS_LOW4 0x05, 0x66 +#define TM6010_REQ05_R67_OUT_MAXPS_HIGH4 0x05, 0x67 +#define TM6010_REQ05_R68_OUT_MAXPS_LOW5 0x05, 0x68 +#define TM6010_REQ05_R69_OUT_MAXPS_HIGH5 0x05, 0x69 +#define TM6010_REQ05_R6A_OUT_MAXPS_LOW6 0x05, 0x6a +#define TM6010_REQ05_R6B_OUT_MAXPS_HIGH6 0x05, 0x6b +#define TM6010_REQ05_R6C_OUT_MAXPS_LOW7 0x05, 0x6c +#define TM6010_REQ05_R6D_OUT_MAXPS_HIGH7 0x05, 0x6d +#define TM6010_REQ05_R6E_OUT_MAXPS_LOW8 0x05, 0x6e +#define TM6010_REQ05_R6F_OUT_MAXPS_HIGH8 0x05, 0x6f +#define TM6010_REQ05_R70_OUT_MAXPS_LOW9 0x05, 0x70 +#define TM6010_REQ05_R71_OUT_MAXPS_HIGH9 0x05, 0x71 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW10 0x05, 0x72 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH10 0x05, 0x73 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW11 0x05, 0x74 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH11 0x05, 0x75 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW12 0x05, 0x76 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH12 0x05, 0x77 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW13 0x05, 0x78 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH13 0x05, 0x79 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW14 0x05, 0x7a +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH14 0x05, 0x7b +#define TM6010_REQ05_R60_OUT_MAXPS_LOW15 0x05, 0x7c +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH15 0x05, 0x7d +#define TM6010_REQ05_R80_FIFO0 0x05, 0x80 +#define TM6010_REQ05_R81_FIFO1 0x05, 0x81 +#define TM6010_REQ05_R82_FIFO2 0x05, 0x82 +#define TM6010_REQ05_R83_FIFO3 0x05, 0x83 +#define TM6010_REQ05_R84_FIFO4 0x05, 0x84 +#define TM6010_REQ05_R85_FIFO5 0x05, 0x85 +#define TM6010_REQ05_R86_FIFO6 0x05, 0x86 +#define TM6010_REQ05_R87_FIFO7 0x05, 0x87 +#define TM6010_REQ05_R88_FIFO8 0x05, 0x88 +#define TM6010_REQ05_R89_FIFO9 0x05, 0x89 +#define TM6010_REQ05_R81_FIFO10 0x05, 0x8a +#define TM6010_REQ05_R81_FIFO11 0x05, 0x8b +#define TM6010_REQ05_R81_FIFO12 0x05, 0x8c +#define TM6010_REQ05_R81_FIFO13 0x05, 0x8d +#define TM6010_REQ05_R81_FIFO14 0x05, 0x8e +#define TM6010_REQ05_R81_FIFO15 0x05, 0x8f +#define TM6010_REQ05_R90_CFG_FIFO0 0x05, 0x90 +#define TM6010_REQ05_R91_CFG_FIFO1 0x05, 0x91 +#define TM6010_REQ05_R92_CFG_FIFO2 0x05, 0x92 +#define TM6010_REQ05_R93_CFG_FIFO3 0x05, 0x93 +#define TM6010_REQ05_R94_CFG_FIFO4 0x05, 0x94 +#define TM6010_REQ05_R95_CFG_FIFO5 0x05, 0x95 +#define TM6010_REQ05_R96_CFG_FIFO6 0x05, 0x96 +#define TM6010_REQ05_R97_CFG_FIFO7 0x05, 0x97 +#define TM6010_REQ05_R98_CFG_FIFO8 0x05, 0x98 +#define TM6010_REQ05_R99_CFG_FIFO9 0x05, 0x99 +#define TM6010_REQ05_R91_CFG_FIFO10 0x05, 0x9a +#define TM6010_REQ05_R91_CFG_FIFO11 0x05, 0x9b +#define TM6010_REQ05_R91_CFG_FIFO12 0x05, 0x9c +#define TM6010_REQ05_R91_CFG_FIFO13 0x05, 0x9d +#define TM6010_REQ05_R91_CFG_FIFO14 0x05, 0x9e +#define TM6010_REQ05_R91_CFG_FIFO15 0x05, 0x9f +#define TM6010_REQ05_RA0_CTL_FIFO0 0x05, 0xa0 +#define TM6010_REQ05_RA1_CTL_FIFO1 0x05, 0xa1 +#define TM6010_REQ05_RA2_CTL_FIFO2 0x05, 0xa2 +#define TM6010_REQ05_RA3_CTL_FIFO3 0x05, 0xa3 +#define TM6010_REQ05_RA4_CTL_FIFO4 0x05, 0xa4 +#define TM6010_REQ05_RA5_CTL_FIFO5 0x05, 0xa5 +#define TM6010_REQ05_RA6_CTL_FIFO6 0x05, 0xa6 +#define TM6010_REQ05_RA7_CTL_FIFO7 0x05, 0xa7 +#define TM6010_REQ05_RA8_CTL_FIFO8 0x05, 0xa8 +#define TM6010_REQ05_RA9_CTL_FIFO9 0x05, 0xa9 +#define TM6010_REQ05_RA1_CTL_FIFO10 0x05, 0xaa +#define TM6010_REQ05_RA1_CTL_FIFO11 0x05, 0xab +#define TM6010_REQ05_RA1_CTL_FIFO12 0x05, 0xac +#define TM6010_REQ05_RA1_CTL_FIFO13 0x05, 0xad +#define TM6010_REQ05_RA1_CTL_FIFO14 0x05, 0xae +#define TM6010_REQ05_RA1_CTL_FIFO15 0x05, 0xaf +#define TM6010_REQ05_RB0_BC_LOW_FIFO0 0x05, 0xb0 +#define TM6010_REQ05_RB1_BC_LOW_FIFO1 0x05, 0xb1 +#define TM6010_REQ05_RB2_BC_LOW_FIFO2 0x05, 0xb2 +#define TM6010_REQ05_RB3_BC_LOW_FIFO3 0x05, 0xb3 +#define TM6010_REQ05_RB4_BC_LOW_FIFO4 0x05, 0xb4 +#define TM6010_REQ05_RB5_BC_LOW_FIFO5 0x05, 0xb5 +#define TM6010_REQ05_RB6_BC_LOW_FIFO6 0x05, 0xb6 +#define TM6010_REQ05_RB7_BC_LOW_FIFO7 0x05, 0xb7 +#define TM6010_REQ05_RB8_BC_LOW_FIFO8 0x05, 0xb8 +#define TM6010_REQ05_RB9_BC_LOW_FIFO9 0x05, 0xb9 +#define TM6010_REQ05_RB1_BC_LOW_FIFO10 0x05, 0xba +#define TM6010_REQ05_RB1_BC_LOW_FIFO11 0x05, 0xbb +#define TM6010_REQ05_RB1_BC_LOW_FIFO12 0x05, 0xbc +#define TM6010_REQ05_RB1_BC_LOW_FIFO13 0x05, 0xbd +#define TM6010_REQ05_RB1_BC_LOW_FIFO14 0x05, 0xbe +#define TM6010_REQ05_RB1_BC_LOW_FIFO15 0x05, 0xbf +#define TM6010_REQ05_RC0_DATA_FIFO0 0x05, 0xc0 +#define TM6010_REQ05_RC4_DATA_FIFO1 0x05, 0xc4 +#define TM6010_REQ05_RC8_DATA_FIFO2 0x05, 0xc8 +#define TM6010_REQ05_RCC_DATA_FIFO3 0x05, 0xcc +#define TM6010_REQ05_RD0_DATA_FIFO4 0x05, 0xd0 +#define TM6010_REQ05_RD4_DATA_FIFO5 0x05, 0xd4 +#define TM6010_REQ05_RD8_DATA_FIFO6 0x05, 0xd8 +#define TM6010_REQ05_RDC_DATA_FIFO7 0x05, 0xdc +#define TM6010_REQ05_RE0_DATA_FIFO8 0x05, 0xe0 +#define TM6010_REQ05_RE4_DATA_FIFO9 0x05, 0xe4 +#define TM6010_REQ05_RC4_DATA_FIFO10 0x05, 0xe8 +#define TM6010_REQ05_RC4_DATA_FIFO11 0x05, 0xec +#define TM6010_REQ05_RC4_DATA_FIFO12 0x05, 0xf0 +#define TM6010_REQ05_RC4_DATA_FIFO13 0x05, 0xf4 +#define TM6010_REQ05_RC4_DATA_FIFO14 0x05, 0xf8 +#define TM6010_REQ05_RC4_DATA_FIFO15 0x05, 0xfc + +/* Define TM6010 Audio decoder registers */ +/* This core available only in TM6010 */ +#define TM6010_REQ08_R00_A_VERSION 0x08, 0x00 +#define TM6010_REQ08_R01_A_INIT 0x08, 0x01 +#define TM6010_REQ08_R02_A_FIX_GAIN_CTRL 0x08, 0x02 +#define TM6010_REQ08_R03_A_AUTO_GAIN_CTRL 0x08, 0x03 +#define TM6010_REQ08_R04_A_SIF_AMP_CTRL 0x08, 0x04 +#define TM6010_REQ08_R05_A_STANDARD_MOD 0x08, 0x05 +#define TM6010_REQ08_R06_A_SOUND_MOD 0x08, 0x06 +#define TM6010_REQ08_R07_A_LEFT_VOL 0x08, 0x07 +#define TM6010_REQ08_R08_A_RIGHT_VOL 0x08, 0x08 +#define TM6010_REQ08_R09_A_MAIN_VOL 0x08, 0x09 +#define TM6010_REQ08_R0A_A_I2S_MOD 0x08, 0x0a +#define TM6010_REQ08_R0B_A_ASD_THRES1 0x08, 0x0b +#define TM6010_REQ08_R0C_A_ASD_THRES2 0x08, 0x0c +#define TM6010_REQ08_R0D_A_AMD_THRES 0x08, 0x0d +#define TM6010_REQ08_R0E_A_MONO_THRES1 0x08, 0x0e +#define TM6010_REQ08_R0F_A_MONO_THRES2 0x08, 0x0f +#define TM6010_REQ08_R10_A_MUTE_THRES1 0x08, 0x10 +#define TM6010_REQ08_R11_A_MUTE_THRES2 0x08, 0x11 +#define TM6010_REQ08_R12_A_AGC_U 0x08, 0x12 +#define TM6010_REQ08_R13_A_AGC_ERR_T 0x08, 0x13 +#define TM6010_REQ08_R14_A_AGC_GAIN_INIT 0x08, 0x14 +#define TM6010_REQ08_R15_A_AGC_STEP_THR 0x08, 0x15 +#define TM6010_REQ08_R16_A_AGC_GAIN_MAX 0x08, 0x16 +#define TM6010_REQ08_R17_A_AGC_GAIN_MIN 0x08, 0x17 +#define TM6010_REQ08_R18_A_TR_CTRL 0x08, 0x18 +#define TM6010_REQ08_R19_A_FH_2FH_GAIN 0x08, 0x19 +#define TM6010_REQ08_R1A_A_NICAM_SER_MAX 0x08, 0x1a +#define TM6010_REQ08_R1B_A_NICAM_SER_MIN 0x08, 0x1b +#define TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT 0x08, 0x1e +#define TM6010_REQ08_R1F_A_TEST_INTF_SEL 0x08, 0x1f +#define TM6010_REQ08_R20_A_TEST_PIN_SEL 0x08, 0x20 +#define TM6010_REQ08_R21_A_AGC_ERR 0x08, 0x21 +#define TM6010_REQ08_R22_A_AGC_GAIN 0x08, 0x22 +#define TM6010_REQ08_R23_A_NICAM_INFO 0x08, 0x23 +#define TM6010_REQ08_R24_A_SER 0x08, 0x24 +#define TM6010_REQ08_R25_A_C1_AMP 0x08, 0x25 +#define TM6010_REQ08_R26_A_C2_AMP 0x08, 0x26 +#define TM6010_REQ08_R27_A_NOISE_AMP 0x08, 0x27 +#define TM6010_REQ08_R28_A_AUDIO_MODE_RES 0x08, 0x28 + +/* Define TM6010 Video ADC registers */ +#define TM6010_REQ08_RE0_ADC_REF 0x08, 0xe0 +#define TM6010_REQ08_RE1_DAC_CLMP 0x08, 0xe1 +#define TM6010_REQ08_RE2_POWER_DOWN_CTRL1 0x08, 0xe2 +#define TM6010_REQ08_RE3_ADC_IN1_SEL 0x08, 0xe3 +#define TM6010_REQ08_RE4_ADC_IN2_SEL 0x08, 0xe4 +#define TM6010_REQ08_RE5_GAIN_PARAM 0x08, 0xe5 +#define TM6010_REQ08_RE6_POWER_DOWN_CTRL2 0x08, 0xe6 +#define TM6010_REQ08_RE7_REG_GAIN_Y 0x08, 0xe7 +#define TM6010_REQ08_RE8_REG_GAIN_C 0x08, 0xe8 +#define TM6010_REQ08_RE9_BIAS_CTRL 0x08, 0xe9 +#define TM6010_REQ08_REA_BUFF_DRV_CTRL 0x08, 0xea +#define TM6010_REQ08_REB_SIF_GAIN_CTRL 0x08, 0xeb +#define TM6010_REQ08_REC_REVERSE_YC_CTRL 0x08, 0xec +#define TM6010_REQ08_RED_GAIN_SEL 0x08, 0xed + +/* Define TM6010 Audio ADC registers */ +#define TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG 0x08, 0xf0 +#define TM6010_REQ08_RF1_AADC_POWER_DOWN 0x08, 0xf1 +#define TM6010_REQ08_RF2_LEFT_CHANNEL_VOL 0x08, 0xf2 +#define TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL 0x08, 0xf3 diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-stds.c b/drivers/staging/media/deprecated/tm6000/tm6000-stds.c new file mode 100644 index 000000000..858cb4f3a --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-stds.c @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0 +// tm6000-stds.c - driver for TM5600/TM6000/TM6010 USB video capture devices +// +// Copyright (c) 2007 Mauro Carvalho Chehab + +#include +#include +#include "tm6000.h" +#include "tm6000-regs.h" + +static unsigned int tm6010_a_mode; +module_param(tm6010_a_mode, int, 0644); +MODULE_PARM_DESC(tm6010_a_mode, "set tm6010 sif audio mode"); + +struct tm6000_reg_settings { + unsigned char req; + unsigned char reg; + unsigned char value; +}; + + +struct tm6000_std_settings { + v4l2_std_id id; + struct tm6000_reg_settings *common; +}; + +static struct tm6000_reg_settings composite_pal_m[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83 }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, + { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_reg_settings composite_pal_nc[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91 }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, + { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_reg_settings composite_pal[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25 }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5 }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, + { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_reg_settings composite_secam[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24 }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92 }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18 }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xff }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_reg_settings composite_ntsc[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, + { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_std_settings composite_stds[] = { + { .id = V4L2_STD_PAL_M, .common = composite_pal_m, }, + { .id = V4L2_STD_PAL_Nc, .common = composite_pal_nc, }, + { .id = V4L2_STD_PAL, .common = composite_pal, }, + { .id = V4L2_STD_SECAM, .common = composite_secam, }, + { .id = V4L2_STD_NTSC, .common = composite_ntsc, }, +}; + +static struct tm6000_reg_settings svideo_pal_m[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x05 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83 }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, + { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_reg_settings svideo_pal_nc[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x37 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91 }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, + { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_reg_settings svideo_pal[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x33 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x30 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25 }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5 }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, + { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_reg_settings svideo_secam[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24 }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92 }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18 }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xff }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_reg_settings svideo_ntsc[] = { + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x01 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x30 }, + { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0x8b }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, + { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f }, + { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd }, + { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, + { 0, 0, 0 } +}; + +static struct tm6000_std_settings svideo_stds[] = { + { .id = V4L2_STD_PAL_M, .common = svideo_pal_m, }, + { .id = V4L2_STD_PAL_Nc, .common = svideo_pal_nc, }, + { .id = V4L2_STD_PAL, .common = svideo_pal, }, + { .id = V4L2_STD_SECAM, .common = svideo_secam, }, + { .id = V4L2_STD_NTSC, .common = svideo_ntsc, }, +}; + +static int tm6000_set_audio_std(struct tm6000_core *dev) +{ + uint8_t areg_02 = 0x04; /* GC1 Fixed gain 0dB */ + uint8_t areg_05 = 0x01; /* Auto 4.5 = M Japan, Auto 6.5 = DK */ + uint8_t areg_06 = 0x02; /* Auto de-emphasis, manual channel mode */ + + if (dev->radio) { + tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, 0x04); + tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0x80); + tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x0c); + /* set mono or stereo */ + if (dev->amode == V4L2_TUNER_MODE_MONO) + tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00); + else if (dev->amode == V4L2_TUNER_MODE_STEREO) + tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x02); + tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x18); + tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x0a); + tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x40); + tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe); + tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13); + tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80); + tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0xff); + return 0; + } + + /* + * STD/MN shouldn't be affected by tm6010_a_mode, as there's just one + * audio standard for each V4L2_STD type. + */ + if ((dev->norm & V4L2_STD_NTSC) == V4L2_STD_NTSC_M_KR) { + areg_05 |= 0x04; + } else if ((dev->norm & V4L2_STD_NTSC) == V4L2_STD_NTSC_M_JP) { + areg_05 |= 0x43; + } else if (dev->norm & V4L2_STD_MN) { + areg_05 |= 0x22; + } else switch (tm6010_a_mode) { + /* auto */ + case 0: + if ((dev->norm & V4L2_STD_SECAM) == V4L2_STD_SECAM_L) + areg_05 |= 0x00; + else /* Other PAL/SECAM standards */ + areg_05 |= 0x10; + break; + /* A2 */ + case 1: + if (dev->norm & V4L2_STD_DK) + areg_05 = 0x09; + else + areg_05 = 0x05; + break; + /* NICAM */ + case 2: + if (dev->norm & V4L2_STD_DK) { + areg_05 = 0x06; + } else if (dev->norm & V4L2_STD_PAL_I) { + areg_05 = 0x08; + } else if (dev->norm & V4L2_STD_SECAM_L) { + areg_05 = 0x0a; + areg_02 = 0x02; + } else { + areg_05 = 0x07; + } + break; + /* other */ + case 3: + if (dev->norm & V4L2_STD_DK) { + areg_05 = 0x0b; + } else { + areg_05 = 0x02; + } + break; + } + + tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, areg_02); + tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0xa0); + tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, areg_05); + tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, areg_06); + tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x08); + tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0x91); + tm6000_set_reg(dev, TM6010_REQ08_R0B_A_ASD_THRES1, 0x20); + tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x12); + tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x20); + tm6000_set_reg(dev, TM6010_REQ08_R0E_A_MONO_THRES1, 0xf0); + tm6000_set_reg(dev, TM6010_REQ08_R0F_A_MONO_THRES2, 0x80); + tm6000_set_reg(dev, TM6010_REQ08_R10_A_MUTE_THRES1, 0xc0); + tm6000_set_reg(dev, TM6010_REQ08_R11_A_MUTE_THRES2, 0x80); + tm6000_set_reg(dev, TM6010_REQ08_R12_A_AGC_U, 0x12); + tm6000_set_reg(dev, TM6010_REQ08_R13_A_AGC_ERR_T, 0xfe); + tm6000_set_reg(dev, TM6010_REQ08_R14_A_AGC_GAIN_INIT, 0x20); + tm6000_set_reg(dev, TM6010_REQ08_R15_A_AGC_STEP_THR, 0x14); + tm6000_set_reg(dev, TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe); + tm6000_set_reg(dev, TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01); + tm6000_set_reg(dev, TM6010_REQ08_R18_A_TR_CTRL, 0xa0); + tm6000_set_reg(dev, TM6010_REQ08_R19_A_FH_2FH_GAIN, 0x32); + tm6000_set_reg(dev, TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64); + tm6000_set_reg(dev, TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20); + tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1c, 0x00); + tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1d, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13); + tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00); + tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80); + + return 0; +} + +void tm6000_get_std_res(struct tm6000_core *dev) +{ + /* Currently, those are the only supported resoltions */ + if (dev->norm & V4L2_STD_525_60) + dev->height = 480; + else + dev->height = 576; + + dev->width = 720; +} + +static int tm6000_load_std(struct tm6000_core *dev, struct tm6000_reg_settings *set) +{ + int i, rc; + + /* Load board's initialization table */ + for (i = 0; set[i].req; i++) { + rc = tm6000_set_reg(dev, set[i].req, set[i].reg, set[i].value); + if (rc < 0) { + printk(KERN_ERR "Error %i while setting req %d, reg %d to value %d\n", + rc, set[i].req, set[i].reg, set[i].value); + return rc; + } + } + + return 0; +} + +int tm6000_set_standard(struct tm6000_core *dev) +{ + struct tm6000_input *input; + int i, rc = 0; + u8 reg_07_fe = 0x8a; + u8 reg_08_f1 = 0xfc; + u8 reg_08_e2 = 0xf0; + u8 reg_08_e6 = 0x0f; + + tm6000_get_std_res(dev); + + if (!dev->radio) + input = &dev->vinput[dev->input]; + else + input = &dev->rinput; + + if (dev->dev_type == TM6010) { + switch (input->vmux) { + case TM6000_VMUX_VIDEO_A: + tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4); + tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1); + tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0); + tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2); + tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8); + reg_07_fe |= 0x01; + break; + case TM6000_VMUX_VIDEO_B: + tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8); + tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1); + tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0); + tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2); + tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8); + reg_07_fe |= 0x01; + break; + case TM6000_VMUX_VIDEO_AB: + tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc); + tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8); + reg_08_e6 = 0x00; + tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2); + tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0); + tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2); + tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe0); + break; + default: + break; + } + switch (input->amux) { + case TM6000_AMUX_ADC1: + tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, + 0x00, 0x0f); + /* Mux overflow workaround */ + tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, + 0x10, 0xf0); + break; + case TM6000_AMUX_ADC2: + tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, + 0x08, 0x0f); + /* Mux overflow workaround */ + tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, + 0x10, 0xf0); + break; + case TM6000_AMUX_SIF1: + reg_08_e2 |= 0x02; + reg_08_e6 = 0x08; + reg_07_fe |= 0x40; + reg_08_f1 |= 0x02; + tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3); + tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, + 0x02, 0x0f); + /* Mux overflow workaround */ + tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, + 0x30, 0xf0); + break; + case TM6000_AMUX_SIF2: + reg_08_e2 |= 0x02; + reg_08_e6 = 0x08; + reg_07_fe |= 0x40; + reg_08_f1 |= 0x02; + tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf7); + tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, + 0x02, 0x0f); + /* Mux overflow workaround */ + tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL, + 0x30, 0xf0); + break; + default: + break; + } + tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, reg_08_e2); + tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, reg_08_e6); + tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, reg_08_f1); + tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, reg_07_fe); + } else { + switch (input->vmux) { + case TM6000_VMUX_VIDEO_A: + tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10); + tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00); + tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f); + tm6000_set_reg(dev, + REQ_03_SET_GET_MCU_PIN, input->v_gpio, 0); + break; + case TM6000_VMUX_VIDEO_B: + tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x00); + tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00); + tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f); + tm6000_set_reg(dev, + REQ_03_SET_GET_MCU_PIN, input->v_gpio, 0); + break; + case TM6000_VMUX_VIDEO_AB: + tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10); + tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x10); + tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00); + tm6000_set_reg(dev, + REQ_03_SET_GET_MCU_PIN, input->v_gpio, 1); + break; + default: + break; + } + switch (input->amux) { + case TM6000_AMUX_ADC1: + tm6000_set_reg_mask(dev, + TM6000_REQ07_REB_VADC_AADC_MODE, 0x00, 0x0f); + break; + case TM6000_AMUX_ADC2: + tm6000_set_reg_mask(dev, + TM6000_REQ07_REB_VADC_AADC_MODE, 0x04, 0x0f); + break; + default: + break; + } + } + if (input->type == TM6000_INPUT_SVIDEO) { + for (i = 0; i < ARRAY_SIZE(svideo_stds); i++) { + if (dev->norm & svideo_stds[i].id) { + rc = tm6000_load_std(dev, svideo_stds[i].common); + goto ret; + } + } + return -EINVAL; + } else { + for (i = 0; i < ARRAY_SIZE(composite_stds); i++) { + if (dev->norm & composite_stds[i].id) { + rc = tm6000_load_std(dev, composite_stds[i].common); + goto ret; + } + } + return -EINVAL; + } + +ret: + if (rc < 0) + return rc; + + if ((dev->dev_type == TM6010) && + ((input->amux == TM6000_AMUX_SIF1) || + (input->amux == TM6000_AMUX_SIF2))) + tm6000_set_audio_std(dev); + + msleep(40); + + return 0; +} diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-usb-isoc.h b/drivers/staging/media/deprecated/tm6000/tm6000-usb-isoc.h new file mode 100644 index 000000000..e3c6933f8 --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-usb-isoc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * tm6000-buf.c - driver for TM5600/TM6000/TM6010 USB video capture devices + * + * Copyright (c) 2006-2007 Mauro Carvalho Chehab + */ + +#include + +#define TM6000_URB_MSG_LEN 180 + +struct usb_isoc_ctl { + /* max packet size of isoc transaction */ + int max_pkt_size; + + /* number of allocated urbs */ + int num_bufs; + + /* urb for isoc transfers */ + struct urb **urb; + + /* transfer buffers for isoc transfer */ + char **transfer_buffer; + + /* Last buffer command and region */ + u8 cmd; + int pos, size, pktsize; + + /* Last field: ODD or EVEN? */ + int vfield, field; + + /* Stores incomplete commands */ + u32 tmp_buf; + int tmp_buf_len; + + /* Stores already requested buffers */ + struct tm6000_buffer *buf; +}; diff --git a/drivers/staging/media/deprecated/tm6000/tm6000-video.c b/drivers/staging/media/deprecated/tm6000/tm6000-video.c new file mode 100644 index 000000000..e06ed21ed --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000-video.c @@ -0,0 +1,1703 @@ +// SPDX-License-Identifier: GPL-2.0 +// tm6000-video.c - driver for TM5600/TM6000/TM6010 USB video capture devices +// +// Copyright (c) 2006-2007 Mauro Carvalho Chehab +// +// Copyright (c) 2007 Michel Ludwig +// - Fixed module load/unload + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tm6000-regs.h" +#include "tm6000.h" + +#define BUFFER_TIMEOUT msecs_to_jiffies(2000) /* 2 seconds */ + +/* Limits minimum and default number of buffers */ +#define TM6000_MIN_BUF 4 +#define TM6000_DEF_BUF 8 + +#define TM6000_NUM_URB_BUF 8 + +#define TM6000_MAX_ISO_PACKETS 46 /* Max number of ISO packets */ + +/* Declare static vars that will be used as parameters */ +static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ +static int video_nr = -1; /* /dev/videoN, -1 for autodetect */ +static int radio_nr = -1; /* /dev/radioN, -1 for autodetect */ +static bool keep_urb; /* keep urb buffers allocated */ + +/* Debug level */ +int tm6000_debug; +EXPORT_SYMBOL_GPL(tm6000_debug); + +static struct tm6000_fmt format[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .depth = 16, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + .depth = 16, + }, { + .fourcc = V4L2_PIX_FMT_TM6000, + .depth = 16, + } +}; + +/* ------------------------------------------------------------------ + * DMA and thread functions + * ------------------------------------------------------------------ + */ + +#define norm_maxw(a) 720 +#define norm_maxh(a) 576 + +#define norm_minw(a) norm_maxw(a) +#define norm_minh(a) norm_maxh(a) + +/* + * video-buf generic routine to get the next available buffer + */ +static inline void get_next_buf(struct tm6000_dmaqueue *dma_q, + struct tm6000_buffer **buf) +{ + struct tm6000_core *dev = container_of(dma_q, struct tm6000_core, vidq); + + if (list_empty(&dma_q->active)) { + dprintk(dev, V4L2_DEBUG_QUEUE, "No active queue to serve\n"); + *buf = NULL; + return; + } + + *buf = list_entry(dma_q->active.next, + struct tm6000_buffer, vb.queue); +} + +/* + * Announces that a buffer were filled and request the next + */ +static inline void buffer_filled(struct tm6000_core *dev, + struct tm6000_dmaqueue *dma_q, + struct tm6000_buffer *buf) +{ + /* Advice that buffer was filled */ + dprintk(dev, V4L2_DEBUG_ISOC, "[%p/%d] wakeup\n", buf, buf->vb.i); + buf->vb.state = VIDEOBUF_DONE; + buf->vb.field_count++; + buf->vb.ts = ktime_get_ns(); + + list_del(&buf->vb.queue); + wake_up(&buf->vb.done); +} + +/* + * Identify the tm5600/6000 buffer header type and properly handles + */ +static int copy_streams(u8 *data, unsigned long len, + struct urb *urb) +{ + struct tm6000_dmaqueue *dma_q = urb->context; + struct tm6000_core *dev = container_of(dma_q, struct tm6000_core, vidq); + u8 *ptr = data, *endp = data+len; + unsigned long header = 0; + int rc = 0; + unsigned int cmd, cpysize, pktsize, size, field, block, line, pos = 0; + struct tm6000_buffer *vbuf = NULL; + char *voutp = NULL; + unsigned int linewidth; + + if (!dev->radio) { + /* get video buffer */ + get_next_buf(dma_q, &vbuf); + + if (!vbuf) + return rc; + voutp = videobuf_to_vmalloc(&vbuf->vb); + + if (!voutp) + return 0; + } + + for (ptr = data; ptr < endp;) { + if (!dev->isoc_ctl.cmd) { + /* Header */ + if (dev->isoc_ctl.tmp_buf_len > 0) { + /* from last urb or packet */ + header = dev->isoc_ctl.tmp_buf; + if (4 - dev->isoc_ctl.tmp_buf_len > 0) { + memcpy((u8 *)&header + + dev->isoc_ctl.tmp_buf_len, + ptr, + 4 - dev->isoc_ctl.tmp_buf_len); + ptr += 4 - dev->isoc_ctl.tmp_buf_len; + } + dev->isoc_ctl.tmp_buf_len = 0; + } else { + if (ptr + 3 >= endp) { + /* have incomplete header */ + dev->isoc_ctl.tmp_buf_len = endp - ptr; + memcpy(&dev->isoc_ctl.tmp_buf, ptr, + dev->isoc_ctl.tmp_buf_len); + return rc; + } + /* Seek for sync */ + for (; ptr < endp - 3; ptr++) { + if (*(ptr + 3) == 0x47) + break; + } + /* Get message header */ + header = *(unsigned long *)ptr; + ptr += 4; + } + + /* split the header fields */ + size = ((header & 0x7e) << 1); + if (size > 0) + size -= 4; + block = (header >> 7) & 0xf; + field = (header >> 11) & 0x1; + line = (header >> 12) & 0x1ff; + cmd = (header >> 21) & 0x7; + /* Validates header fields */ + if (size > TM6000_URB_MSG_LEN) + size = TM6000_URB_MSG_LEN; + pktsize = TM6000_URB_MSG_LEN; + /* + * calculate position in buffer and change the buffer + */ + switch (cmd) { + case TM6000_URB_MSG_VIDEO: + if (!dev->radio) { + if ((dev->isoc_ctl.vfield != field) && + (field == 1)) { + /* + * Announces that a new buffer + * were filled + */ + buffer_filled(dev, dma_q, vbuf); + dprintk(dev, V4L2_DEBUG_ISOC, + "new buffer filled\n"); + get_next_buf(dma_q, &vbuf); + if (!vbuf) + return rc; + voutp = videobuf_to_vmalloc(&vbuf->vb); + if (!voutp) + return rc; + memset(voutp, 0, vbuf->vb.size); + } + linewidth = vbuf->vb.width << 1; + pos = ((line << 1) - field - 1) * + linewidth + block * TM6000_URB_MSG_LEN; + /* Don't allow to write out of the buffer */ + if (pos + size > vbuf->vb.size) + cmd = TM6000_URB_MSG_ERR; + dev->isoc_ctl.vfield = field; + } + break; + case TM6000_URB_MSG_VBI: + break; + case TM6000_URB_MSG_AUDIO: + case TM6000_URB_MSG_PTS: + size = pktsize; /* Size is always 180 bytes */ + break; + } + } else { + /* Continue the last copy */ + cmd = dev->isoc_ctl.cmd; + size = dev->isoc_ctl.size; + pos = dev->isoc_ctl.pos; + pktsize = dev->isoc_ctl.pktsize; + field = dev->isoc_ctl.field; + } + cpysize = (endp - ptr > size) ? size : endp - ptr; + if (cpysize) { + /* copy data in different buffers */ + switch (cmd) { + case TM6000_URB_MSG_VIDEO: + /* Fills video buffer */ + if (vbuf) + memcpy(&voutp[pos], ptr, cpysize); + break; + case TM6000_URB_MSG_AUDIO: { + int i; + for (i = 0; i < cpysize; i += 2) + swab16s((u16 *)(ptr + i)); + + tm6000_call_fillbuf(dev, TM6000_AUDIO, ptr, cpysize); + break; + } + case TM6000_URB_MSG_VBI: + /* Need some code to copy vbi buffer */ + break; + case TM6000_URB_MSG_PTS: { + /* Need some code to copy pts */ + u32 pts; + pts = *(u32 *)ptr; + dprintk(dev, V4L2_DEBUG_ISOC, "field %d, PTS %x", + field, pts); + break; + } + } + } + if (ptr + pktsize > endp) { + /* + * End of URB packet, but cmd processing is not + * complete. Preserve the state for a next packet + */ + dev->isoc_ctl.pos = pos + cpysize; + dev->isoc_ctl.size = size - cpysize; + dev->isoc_ctl.cmd = cmd; + dev->isoc_ctl.field = field; + dev->isoc_ctl.pktsize = pktsize - (endp - ptr); + ptr += endp - ptr; + } else { + dev->isoc_ctl.cmd = 0; + ptr += pktsize; + } + } + return 0; +} + +/* + * Identify the tm5600/6000 buffer header type and properly handles + */ +static int copy_multiplexed(u8 *ptr, unsigned long len, + struct urb *urb) +{ + struct tm6000_dmaqueue *dma_q = urb->context; + struct tm6000_core *dev = container_of(dma_q, struct tm6000_core, vidq); + unsigned int pos = dev->isoc_ctl.pos, cpysize; + int rc = 1; + struct tm6000_buffer *buf; + char *outp = NULL; + + get_next_buf(dma_q, &buf); + if (buf) + outp = videobuf_to_vmalloc(&buf->vb); + + if (!outp) + return 0; + + while (len > 0) { + cpysize = min(len, buf->vb.size-pos); + memcpy(&outp[pos], ptr, cpysize); + pos += cpysize; + ptr += cpysize; + len -= cpysize; + if (pos >= buf->vb.size) { + pos = 0; + /* Announces that a new buffer were filled */ + buffer_filled(dev, dma_q, buf); + dprintk(dev, V4L2_DEBUG_ISOC, "new buffer filled\n"); + get_next_buf(dma_q, &buf); + if (!buf) + break; + outp = videobuf_to_vmalloc(&(buf->vb)); + if (!outp) + return rc; + pos = 0; + } + } + + dev->isoc_ctl.pos = pos; + return rc; +} + +static inline void print_err_status(struct tm6000_core *dev, + int packet, int status) +{ + char *errmsg = "Unknown"; + + switch (status) { + case -ENOENT: + errmsg = "unlinked synchronously"; + break; + case -ECONNRESET: + errmsg = "unlinked asynchronously"; + break; + case -ENOSR: + errmsg = "Buffer error (overrun)"; + break; + case -EPIPE: + errmsg = "Stalled (device not responding)"; + break; + case -EOVERFLOW: + errmsg = "Babble (bad cable?)"; + break; + case -EPROTO: + errmsg = "Bit-stuff error (bad cable?)"; + break; + case -EILSEQ: + errmsg = "CRC/Timeout (could be anything)"; + break; + case -ETIME: + errmsg = "Device does not respond"; + break; + } + if (packet < 0) { + dprintk(dev, V4L2_DEBUG_QUEUE, "URB status %d [%s].\n", + status, errmsg); + } else { + dprintk(dev, V4L2_DEBUG_QUEUE, "URB packet %d, status %d [%s].\n", + packet, status, errmsg); + } +} + + +/* + * Controls the isoc copy of each urb packet + */ +static inline int tm6000_isoc_copy(struct urb *urb) +{ + struct tm6000_dmaqueue *dma_q = urb->context; + struct tm6000_core *dev = container_of(dma_q, struct tm6000_core, vidq); + int i, len = 0, rc = 1, status; + char *p; + + if (urb->status < 0) { + print_err_status(dev, -1, urb->status); + return 0; + } + + for (i = 0; i < urb->number_of_packets; i++) { + status = urb->iso_frame_desc[i].status; + + if (status < 0) { + print_err_status(dev, i, status); + continue; + } + + len = urb->iso_frame_desc[i].actual_length; + + if (len > 0) { + p = urb->transfer_buffer + urb->iso_frame_desc[i].offset; + if (!urb->iso_frame_desc[i].status) { + if ((dev->fourcc) == V4L2_PIX_FMT_TM6000) { + rc = copy_multiplexed(p, len, urb); + if (rc <= 0) + return rc; + } else { + copy_streams(p, len, urb); + } + } + } + } + return rc; +} + +/* ------------------------------------------------------------------ + * URB control + * ------------------------------------------------------------------ + */ + +/* + * IRQ callback, called by URB callback + */ +static void tm6000_irq_callback(struct urb *urb) +{ + struct tm6000_dmaqueue *dma_q = urb->context; + struct tm6000_core *dev = container_of(dma_q, struct tm6000_core, vidq); + unsigned long flags; + int i; + + switch (urb->status) { + case 0: + case -ETIMEDOUT: + break; + + case -ECONNRESET: + case -ENOENT: + case -ESHUTDOWN: + return; + + default: + tm6000_err("urb completion error %d.\n", urb->status); + break; + } + + spin_lock_irqsave(&dev->slock, flags); + tm6000_isoc_copy(urb); + spin_unlock_irqrestore(&dev->slock, flags); + + /* Reset urb buffers */ + for (i = 0; i < urb->number_of_packets; i++) { + urb->iso_frame_desc[i].status = 0; + urb->iso_frame_desc[i].actual_length = 0; + } + + urb->status = usb_submit_urb(urb, GFP_ATOMIC); + if (urb->status) + tm6000_err("urb resubmit failed (error=%i)\n", + urb->status); +} + +/* + * Allocate URB buffers + */ +static int tm6000_alloc_urb_buffers(struct tm6000_core *dev) +{ + int num_bufs = TM6000_NUM_URB_BUF; + int i; + + if (dev->urb_buffer) + return 0; + + dev->urb_buffer = kmalloc_array(num_bufs, sizeof(*dev->urb_buffer), + GFP_KERNEL); + if (!dev->urb_buffer) + return -ENOMEM; + + dev->urb_dma = kmalloc_array(num_bufs, sizeof(*dev->urb_dma), + GFP_KERNEL); + if (!dev->urb_dma) + return -ENOMEM; + + for (i = 0; i < num_bufs; i++) { + dev->urb_buffer[i] = usb_alloc_coherent( + dev->udev, dev->urb_size, + GFP_KERNEL, &dev->urb_dma[i]); + if (!dev->urb_buffer[i]) { + tm6000_err("unable to allocate %i bytes for transfer buffer %i\n", + dev->urb_size, i); + return -ENOMEM; + } + memset(dev->urb_buffer[i], 0, dev->urb_size); + } + + return 0; +} + +/* + * Free URB buffers + */ +static int tm6000_free_urb_buffers(struct tm6000_core *dev) +{ + int i; + + if (!dev->urb_buffer) + return 0; + + for (i = 0; i < TM6000_NUM_URB_BUF; i++) { + if (dev->urb_buffer[i]) { + usb_free_coherent(dev->udev, + dev->urb_size, + dev->urb_buffer[i], + dev->urb_dma[i]); + dev->urb_buffer[i] = NULL; + } + } + kfree(dev->urb_buffer); + kfree(dev->urb_dma); + dev->urb_buffer = NULL; + dev->urb_dma = NULL; + + return 0; +} + +/* + * Stop and Deallocate URBs + */ +static void tm6000_uninit_isoc(struct tm6000_core *dev) +{ + struct urb *urb; + int i; + + dev->isoc_ctl.buf = NULL; + for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { + urb = dev->isoc_ctl.urb[i]; + if (urb) { + usb_kill_urb(urb); + usb_unlink_urb(urb); + usb_free_urb(urb); + dev->isoc_ctl.urb[i] = NULL; + } + dev->isoc_ctl.transfer_buffer[i] = NULL; + } + + if (!keep_urb) + tm6000_free_urb_buffers(dev); + + kfree(dev->isoc_ctl.urb); + kfree(dev->isoc_ctl.transfer_buffer); + + dev->isoc_ctl.urb = NULL; + dev->isoc_ctl.transfer_buffer = NULL; + dev->isoc_ctl.num_bufs = 0; +} + +/* + * Assign URBs and start IRQ + */ +static int tm6000_prepare_isoc(struct tm6000_core *dev) +{ + struct tm6000_dmaqueue *dma_q = &dev->vidq; + int i, j, sb_size, pipe, size, max_packets; + int num_bufs = TM6000_NUM_URB_BUF; + struct urb *urb; + + /* De-allocates all pending stuff */ + tm6000_uninit_isoc(dev); + /* Stop interrupt USB pipe */ + tm6000_ir_int_stop(dev); + + usb_set_interface(dev->udev, + dev->isoc_in.bInterfaceNumber, + dev->isoc_in.bAlternateSetting); + + /* Start interrupt USB pipe */ + tm6000_ir_int_start(dev); + + pipe = usb_rcvisocpipe(dev->udev, + dev->isoc_in.endp->desc.bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK); + + size = usb_maxpacket(dev->udev, pipe); + + if (size > dev->isoc_in.maxsize) + size = dev->isoc_in.maxsize; + + dev->isoc_ctl.max_pkt_size = size; + + max_packets = TM6000_MAX_ISO_PACKETS; + sb_size = max_packets * size; + dev->urb_size = sb_size; + + dev->isoc_ctl.num_bufs = num_bufs; + + dev->isoc_ctl.urb = kmalloc_array(num_bufs, sizeof(void *), + GFP_KERNEL); + if (!dev->isoc_ctl.urb) + return -ENOMEM; + + dev->isoc_ctl.transfer_buffer = kmalloc_array(num_bufs, + sizeof(void *), + GFP_KERNEL); + if (!dev->isoc_ctl.transfer_buffer) { + kfree(dev->isoc_ctl.urb); + return -ENOMEM; + } + + dprintk(dev, V4L2_DEBUG_QUEUE, "Allocating %d x %d packets (%d bytes) of %d bytes each to handle %u size\n", + max_packets, num_bufs, sb_size, + dev->isoc_in.maxsize, size); + + + if (tm6000_alloc_urb_buffers(dev) < 0) { + tm6000_err("cannot allocate memory for urb buffers\n"); + + /* call free, as some buffers might have been allocated */ + tm6000_free_urb_buffers(dev); + kfree(dev->isoc_ctl.urb); + kfree(dev->isoc_ctl.transfer_buffer); + return -ENOMEM; + } + + /* allocate urbs and transfer buffers */ + for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { + urb = usb_alloc_urb(max_packets, GFP_KERNEL); + if (!urb) { + tm6000_uninit_isoc(dev); + tm6000_free_urb_buffers(dev); + return -ENOMEM; + } + dev->isoc_ctl.urb[i] = urb; + + urb->transfer_dma = dev->urb_dma[i]; + dev->isoc_ctl.transfer_buffer[i] = dev->urb_buffer[i]; + + usb_fill_bulk_urb(urb, dev->udev, pipe, + dev->isoc_ctl.transfer_buffer[i], sb_size, + tm6000_irq_callback, dma_q); + urb->interval = dev->isoc_in.endp->desc.bInterval; + urb->number_of_packets = max_packets; + urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP; + + for (j = 0; j < max_packets; j++) { + urb->iso_frame_desc[j].offset = size * j; + urb->iso_frame_desc[j].length = size; + } + } + + return 0; +} + +static int tm6000_start_thread(struct tm6000_core *dev) +{ + struct tm6000_dmaqueue *dma_q = &dev->vidq; + int i; + + dma_q->frame = 0; + dma_q->ini_jiffies = jiffies; + + init_waitqueue_head(&dma_q->wq); + + /* submit urbs and enables IRQ */ + for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { + int rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC); + if (rc) { + tm6000_err("submit of urb %i failed (error=%i)\n", i, + rc); + tm6000_uninit_isoc(dev); + return rc; + } + } + + return 0; +} + +/* ------------------------------------------------------------------ + * Videobuf operations + * ------------------------------------------------------------------ + */ + +static int +buffer_setup(struct videobuf_queue *vq, unsigned int *count, unsigned int *size) +{ + struct tm6000_fh *fh = vq->priv_data; + + *size = fh->fmt->depth * fh->width * fh->height >> 3; + if (0 == *count) + *count = TM6000_DEF_BUF; + + if (*count < TM6000_MIN_BUF) + *count = TM6000_MIN_BUF; + + while (*size * *count > vid_limit * 1024 * 1024) + (*count)--; + + return 0; +} + +static void free_buffer(struct videobuf_queue *vq, struct tm6000_buffer *buf) +{ + struct tm6000_fh *fh = vq->priv_data; + struct tm6000_core *dev = fh->dev; + unsigned long flags; + + /* We used to wait for the buffer to finish here, but this didn't work + because, as we were keeping the state as VIDEOBUF_QUEUED, + videobuf_queue_cancel marked it as finished for us. + (Also, it could wedge forever if the hardware was misconfigured.) + + This should be safe; by the time we get here, the buffer isn't + queued anymore. If we ever start marking the buffers as + VIDEOBUF_ACTIVE, it won't be, though. + */ + spin_lock_irqsave(&dev->slock, flags); + if (dev->isoc_ctl.buf == buf) + dev->isoc_ctl.buf = NULL; + spin_unlock_irqrestore(&dev->slock, flags); + + videobuf_vmalloc_free(&buf->vb); + buf->vb.state = VIDEOBUF_NEEDS_INIT; +} + +static int +buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct tm6000_fh *fh = vq->priv_data; + struct tm6000_buffer *buf = container_of(vb, struct tm6000_buffer, vb); + struct tm6000_core *dev = fh->dev; + int rc = 0; + + BUG_ON(NULL == fh->fmt); + + + /* FIXME: It assumes depth=2 */ + /* The only currently supported format is 16 bits/pixel */ + buf->vb.size = fh->fmt->depth*fh->width*fh->height >> 3; + if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) + return -EINVAL; + + if (buf->fmt != fh->fmt || + buf->vb.width != fh->width || + buf->vb.height != fh->height || + buf->vb.field != field) { + buf->fmt = fh->fmt; + buf->vb.width = fh->width; + buf->vb.height = fh->height; + buf->vb.field = field; + buf->vb.state = VIDEOBUF_NEEDS_INIT; + } + + if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { + rc = videobuf_iolock(vq, &buf->vb, NULL); + if (rc != 0) + goto fail; + } + + if (!dev->isoc_ctl.num_bufs) { + rc = tm6000_prepare_isoc(dev); + if (rc < 0) + goto fail; + + rc = tm6000_start_thread(dev); + if (rc < 0) + goto fail; + + } + + buf->vb.state = VIDEOBUF_PREPARED; + return 0; + +fail: + free_buffer(vq, buf); + return rc; +} + +static void +buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct tm6000_buffer *buf = container_of(vb, struct tm6000_buffer, vb); + struct tm6000_fh *fh = vq->priv_data; + struct tm6000_core *dev = fh->dev; + struct tm6000_dmaqueue *vidq = &dev->vidq; + + buf->vb.state = VIDEOBUF_QUEUED; + list_add_tail(&buf->vb.queue, &vidq->active); +} + +static void buffer_release(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct tm6000_buffer *buf = container_of(vb, struct tm6000_buffer, vb); + + free_buffer(vq, buf); +} + +static const struct videobuf_queue_ops tm6000_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +/* ------------------------------------------------------------------ + * IOCTL handling + * ------------------------------------------------------------------ + */ + +static bool is_res_read(struct tm6000_core *dev, struct tm6000_fh *fh) +{ + /* Is the current fh handling it? if so, that's OK */ + if (dev->resources == fh && dev->is_res_read) + return true; + + return false; +} + +static bool is_res_streaming(struct tm6000_core *dev, struct tm6000_fh *fh) +{ + /* Is the current fh handling it? if so, that's OK */ + if (dev->resources == fh) + return true; + + return false; +} + +static bool res_get(struct tm6000_core *dev, struct tm6000_fh *fh, + bool is_res_read) +{ + /* Is the current fh handling it? if so, that's OK */ + if (dev->resources == fh && dev->is_res_read == is_res_read) + return true; + + /* is it free? */ + if (dev->resources) + return false; + + /* grab it */ + dev->resources = fh; + dev->is_res_read = is_res_read; + dprintk(dev, V4L2_DEBUG_RES_LOCK, "res: get\n"); + return true; +} + +static void res_free(struct tm6000_core *dev, struct tm6000_fh *fh) +{ + /* Is the current fh handling it? if so, that's OK */ + if (dev->resources != fh) + return; + + dev->resources = NULL; + dprintk(dev, V4L2_DEBUG_RES_LOCK, "res: put\n"); +} + +/* ------------------------------------------------------------------ + * IOCTL vidioc handling + * ------------------------------------------------------------------ + */ +static int vidioc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct tm6000_core *dev = ((struct tm6000_fh *)priv)->dev; + + strscpy(cap->driver, "tm6000", sizeof(cap->driver)); + strscpy(cap->card, "Trident TM5600/6000/6010", sizeof(cap->card)); + usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info)); + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_DEVICE_CAPS; + if (dev->tuner_type != TUNER_ABSENT) + cap->capabilities |= V4L2_CAP_TUNER; + if (dev->caps.has_radio) + cap->capabilities |= V4L2_CAP_RADIO; + + return 0; +} + +static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + if (f->index >= ARRAY_SIZE(format)) + return -EINVAL; + + f->pixelformat = format[f->index].fourcc; + return 0; +} + +static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct tm6000_fh *fh = priv; + + f->fmt.pix.width = fh->width; + f->fmt.pix.height = fh->height; + f->fmt.pix.field = fh->vb_vidq.field; + f->fmt.pix.pixelformat = fh->fmt->fourcc; + f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; + f->fmt.pix.bytesperline = + (f->fmt.pix.width * fh->fmt->depth) >> 3; + f->fmt.pix.sizeimage = + f->fmt.pix.height * f->fmt.pix.bytesperline; + + return 0; +} + +static struct tm6000_fmt *format_by_fourcc(unsigned int fourcc) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(format); i++) + if (format[i].fourcc == fourcc) + return format+i; + return NULL; +} + +static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct tm6000_core *dev = ((struct tm6000_fh *)priv)->dev; + struct tm6000_fmt *fmt; + enum v4l2_field field; + + fmt = format_by_fourcc(f->fmt.pix.pixelformat); + if (NULL == fmt) { + dprintk(dev, 2, "Fourcc format (0x%08x) invalid.\n", + f->fmt.pix.pixelformat); + return -EINVAL; + } + + field = V4L2_FIELD_INTERLACED; + + tm6000_get_std_res(dev); + + f->fmt.pix.width = dev->width; + f->fmt.pix.height = dev->height; + + f->fmt.pix.width &= ~0x01; + + f->fmt.pix.field = field; + + f->fmt.pix.bytesperline = + (f->fmt.pix.width * fmt->depth) >> 3; + f->fmt.pix.sizeimage = + f->fmt.pix.height * f->fmt.pix.bytesperline; + f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; + + return 0; +} + +/*FIXME: This seems to be generic enough to be at videodev2 */ +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + int ret = vidioc_try_fmt_vid_cap(file, fh, f); + if (ret < 0) + return ret; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->width = f->fmt.pix.width; + fh->height = f->fmt.pix.height; + fh->vb_vidq.field = f->fmt.pix.field; + fh->type = f->type; + + dev->fourcc = f->fmt.pix.pixelformat; + + tm6000_set_fourcc_format(dev); + + return 0; +} + +static int vidioc_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *p) +{ + struct tm6000_fh *fh = priv; + + return videobuf_reqbufs(&fh->vb_vidq, p); +} + +static int vidioc_querybuf(struct file *file, void *priv, + struct v4l2_buffer *p) +{ + struct tm6000_fh *fh = priv; + + return videobuf_querybuf(&fh->vb_vidq, p); +} + +static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct tm6000_fh *fh = priv; + + return videobuf_qbuf(&fh->vb_vidq, p); +} + +static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) +{ + struct tm6000_fh *fh = priv; + + return videobuf_dqbuf(&fh->vb_vidq, p, + file->f_flags & O_NONBLOCK); +} + +static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (i != fh->type) + return -EINVAL; + + if (!res_get(dev, fh, false)) + return -EBUSY; + return videobuf_streamon(&fh->vb_vidq); +} + +static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (i != fh->type) + return -EINVAL; + + videobuf_streamoff(&fh->vb_vidq); + res_free(dev, fh); + + return 0; +} + +static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id norm) +{ + int rc = 0; + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + dev->norm = norm; + rc = tm6000_init_analog_mode(dev); + + fh->width = dev->width; + fh->height = dev->height; + + if (rc < 0) + return rc; + + v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_std, dev->norm); + + return 0; +} + +static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *norm) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + *norm = dev->norm; + return 0; +} + +static const char *iname[] = { + [TM6000_INPUT_TV] = "Television", + [TM6000_INPUT_COMPOSITE1] = "Composite 1", + [TM6000_INPUT_COMPOSITE2] = "Composite 2", + [TM6000_INPUT_SVIDEO] = "S-Video", +}; + +static int vidioc_enum_input(struct file *file, void *priv, + struct v4l2_input *i) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + unsigned int n; + + n = i->index; + if (n >= 3) + return -EINVAL; + + if (!dev->vinput[n].type) + return -EINVAL; + + i->index = n; + + if (dev->vinput[n].type == TM6000_INPUT_TV) + i->type = V4L2_INPUT_TYPE_TUNER; + else + i->type = V4L2_INPUT_TYPE_CAMERA; + + strscpy(i->name, iname[dev->vinput[n].type], sizeof(i->name)); + + i->std = TM6000_STD; + + return 0; +} + +static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + *i = dev->input; + + return 0; +} + +static int vidioc_s_input(struct file *file, void *priv, unsigned int i) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + int rc = 0; + + if (i >= 3) + return -EINVAL; + if (!dev->vinput[i].type) + return -EINVAL; + + dev->input = i; + + rc = vidioc_s_std(file, priv, dev->norm); + + return rc; +} + +/* --- controls ---------------------------------------------- */ + +static int tm6000_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct tm6000_core *dev = container_of(ctrl->handler, struct tm6000_core, ctrl_handler); + u8 val = ctrl->val; + + switch (ctrl->id) { + case V4L2_CID_CONTRAST: + tm6000_set_reg(dev, TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, val); + return 0; + case V4L2_CID_BRIGHTNESS: + tm6000_set_reg(dev, TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, val); + return 0; + case V4L2_CID_SATURATION: + tm6000_set_reg(dev, TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, val); + return 0; + case V4L2_CID_HUE: + tm6000_set_reg(dev, TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ, val); + return 0; + } + return -EINVAL; +} + +static const struct v4l2_ctrl_ops tm6000_ctrl_ops = { + .s_ctrl = tm6000_s_ctrl, +}; + +static int tm6000_radio_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct tm6000_core *dev = container_of(ctrl->handler, + struct tm6000_core, radio_ctrl_handler); + u8 val = ctrl->val; + + switch (ctrl->id) { + case V4L2_CID_AUDIO_MUTE: + dev->ctl_mute = val; + tm6000_tvaudio_set_mute(dev, val); + return 0; + case V4L2_CID_AUDIO_VOLUME: + dev->ctl_volume = val; + tm6000_set_volume(dev, val); + return 0; + } + return -EINVAL; +} + +static const struct v4l2_ctrl_ops tm6000_radio_ctrl_ops = { + .s_ctrl = tm6000_radio_s_ctrl, +}; + +static int vidioc_g_tuner(struct file *file, void *priv, + struct v4l2_tuner *t) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + if (UNSET == dev->tuner_type) + return -ENOTTY; + if (0 != t->index) + return -EINVAL; + + strscpy(t->name, "Television", sizeof(t->name)); + t->type = V4L2_TUNER_ANALOG_TV; + t->capability = V4L2_TUNER_CAP_NORM | V4L2_TUNER_CAP_STEREO; + t->rangehigh = 0xffffffffUL; + t->rxsubchans = V4L2_TUNER_SUB_STEREO; + + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, g_tuner, t); + + t->audmode = dev->amode; + + return 0; +} + +static int vidioc_s_tuner(struct file *file, void *priv, + const struct v4l2_tuner *t) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + if (UNSET == dev->tuner_type) + return -ENOTTY; + if (0 != t->index) + return -EINVAL; + + if (t->audmode > V4L2_TUNER_MODE_STEREO) + dev->amode = V4L2_TUNER_MODE_STEREO; + else + dev->amode = t->audmode; + dprintk(dev, 3, "audio mode: %x\n", t->audmode); + + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_tuner, t); + + return 0; +} + +static int vidioc_g_frequency(struct file *file, void *priv, + struct v4l2_frequency *f) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + if (UNSET == dev->tuner_type) + return -ENOTTY; + if (f->tuner) + return -EINVAL; + + f->frequency = dev->freq; + + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, g_frequency, f); + + return 0; +} + +static int vidioc_s_frequency(struct file *file, void *priv, + const struct v4l2_frequency *f) +{ + struct tm6000_fh *fh = priv; + struct tm6000_core *dev = fh->dev; + + if (UNSET == dev->tuner_type) + return -ENOTTY; + if (f->tuner != 0) + return -EINVAL; + + dev->freq = f->frequency; + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, f); + + return 0; +} + +static int radio_g_tuner(struct file *file, void *priv, + struct v4l2_tuner *t) +{ + struct tm6000_fh *fh = file->private_data; + struct tm6000_core *dev = fh->dev; + + if (0 != t->index) + return -EINVAL; + + memset(t, 0, sizeof(*t)); + strscpy(t->name, "Radio", sizeof(t->name)); + t->type = V4L2_TUNER_RADIO; + t->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO; + t->rxsubchans = V4L2_TUNER_SUB_STEREO; + t->audmode = V4L2_TUNER_MODE_STEREO; + + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, g_tuner, t); + + return 0; +} + +static int radio_s_tuner(struct file *file, void *priv, + const struct v4l2_tuner *t) +{ + struct tm6000_fh *fh = file->private_data; + struct tm6000_core *dev = fh->dev; + + if (0 != t->index) + return -EINVAL; + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_tuner, t); + return 0; +} + +/* ------------------------------------------------------------------ + File operations for the device + ------------------------------------------------------------------*/ + +static int __tm6000_open(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct tm6000_core *dev = video_drvdata(file); + struct tm6000_fh *fh; + enum v4l2_buf_type type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + int rc; + int radio = 0; + + dprintk(dev, V4L2_DEBUG_OPEN, "tm6000: open called (dev=%s)\n", + video_device_node_name(vdev)); + + switch (vdev->vfl_type) { + case VFL_TYPE_VIDEO: + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + break; + case VFL_TYPE_VBI: + type = V4L2_BUF_TYPE_VBI_CAPTURE; + break; + case VFL_TYPE_RADIO: + radio = 1; + break; + default: + return -EINVAL; + } + + /* If more than one user, mutex should be added */ + dev->users++; + + dprintk(dev, V4L2_DEBUG_OPEN, "open dev=%s type=%s users=%d\n", + video_device_node_name(vdev), v4l2_type_names[type], + dev->users); + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh), GFP_KERNEL); + if (NULL == fh) { + dev->users--; + return -ENOMEM; + } + + v4l2_fh_init(&fh->fh, vdev); + file->private_data = fh; + fh->dev = dev; + fh->radio = radio; + dev->radio = radio; + fh->type = type; + dev->fourcc = format[0].fourcc; + + fh->fmt = format_by_fourcc(dev->fourcc); + + tm6000_get_std_res(dev); + + fh->width = dev->width; + fh->height = dev->height; + + dprintk(dev, V4L2_DEBUG_OPEN, "Open: fh=%p, dev=%p, dev->vidq=%p\n", + fh, dev, &dev->vidq); + dprintk(dev, V4L2_DEBUG_OPEN, "Open: list_empty queued=%d\n", + list_empty(&dev->vidq.queued)); + dprintk(dev, V4L2_DEBUG_OPEN, "Open: list_empty active=%d\n", + list_empty(&dev->vidq.active)); + + /* initialize hardware on analog mode */ + rc = tm6000_init_analog_mode(dev); + if (rc < 0) { + v4l2_fh_exit(&fh->fh); + kfree(fh); + return rc; + } + + dev->mode = TM6000_MODE_ANALOG; + + if (!fh->radio) { + videobuf_queue_vmalloc_init(&fh->vb_vidq, &tm6000_video_qops, + NULL, &dev->slock, + fh->type, + V4L2_FIELD_INTERLACED, + sizeof(struct tm6000_buffer), fh, &dev->lock); + } else { + dprintk(dev, V4L2_DEBUG_OPEN, "video_open: setting radio device\n"); + tm6000_set_audio_rinput(dev); + v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_radio); + tm6000_prepare_isoc(dev); + tm6000_start_thread(dev); + } + v4l2_fh_add(&fh->fh); + + return 0; +} + +static int tm6000_open(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + int res; + + mutex_lock(vdev->lock); + res = __tm6000_open(file); + mutex_unlock(vdev->lock); + return res; +} + +static ssize_t +tm6000_read(struct file *file, char __user *data, size_t count, loff_t *pos) +{ + struct tm6000_fh *fh = file->private_data; + struct tm6000_core *dev = fh->dev; + + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + int res; + + if (!res_get(fh->dev, fh, true)) + return -EBUSY; + + if (mutex_lock_interruptible(&dev->lock)) + return -ERESTARTSYS; + res = videobuf_read_stream(&fh->vb_vidq, data, count, pos, 0, + file->f_flags & O_NONBLOCK); + mutex_unlock(&dev->lock); + return res; + } + return 0; +} + +static __poll_t +__tm6000_poll(struct file *file, struct poll_table_struct *wait) +{ + __poll_t req_events = poll_requested_events(wait); + struct tm6000_fh *fh = file->private_data; + struct tm6000_buffer *buf; + __poll_t res = 0; + + if (v4l2_event_pending(&fh->fh)) + res = EPOLLPRI; + else if (req_events & EPOLLPRI) + poll_wait(file, &fh->fh.wait, wait); + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != fh->type) + return res | EPOLLERR; + + if (!!is_res_streaming(fh->dev, fh)) + return res | EPOLLERR; + + if (!is_res_read(fh->dev, fh)) { + /* streaming capture */ + if (list_empty(&fh->vb_vidq.stream)) + return res | EPOLLERR; + buf = list_entry(fh->vb_vidq.stream.next, struct tm6000_buffer, vb.stream); + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == VIDEOBUF_DONE || + buf->vb.state == VIDEOBUF_ERROR) + return res | EPOLLIN | EPOLLRDNORM; + } else if (req_events & (EPOLLIN | EPOLLRDNORM)) { + /* read() capture */ + return res | videobuf_poll_stream(file, &fh->vb_vidq, wait); + } + return res; +} + +static __poll_t tm6000_poll(struct file *file, struct poll_table_struct *wait) +{ + struct tm6000_fh *fh = file->private_data; + struct tm6000_core *dev = fh->dev; + __poll_t res; + + mutex_lock(&dev->lock); + res = __tm6000_poll(file, wait); + mutex_unlock(&dev->lock); + return res; +} + +static int tm6000_release(struct file *file) +{ + struct tm6000_fh *fh = file->private_data; + struct tm6000_core *dev = fh->dev; + struct video_device *vdev = video_devdata(file); + + dprintk(dev, V4L2_DEBUG_OPEN, "tm6000: close called (dev=%s, users=%d)\n", + video_device_node_name(vdev), dev->users); + + mutex_lock(&dev->lock); + dev->users--; + + res_free(dev, fh); + + if (!dev->users) { + tm6000_uninit_isoc(dev); + + /* Stop interrupt USB pipe */ + tm6000_ir_int_stop(dev); + + usb_reset_configuration(dev->udev); + + if (dev->int_in.endp) + usb_set_interface(dev->udev, + dev->isoc_in.bInterfaceNumber, 2); + else + usb_set_interface(dev->udev, + dev->isoc_in.bInterfaceNumber, 0); + + /* Start interrupt USB pipe */ + tm6000_ir_int_start(dev); + + if (!fh->radio) + videobuf_mmap_free(&fh->vb_vidq); + } + v4l2_fh_del(&fh->fh); + v4l2_fh_exit(&fh->fh); + kfree(fh); + mutex_unlock(&dev->lock); + + return 0; +} + +static int tm6000_mmap(struct file *file, struct vm_area_struct * vma) +{ + struct tm6000_fh *fh = file->private_data; + struct tm6000_core *dev = fh->dev; + int res; + + if (mutex_lock_interruptible(&dev->lock)) + return -ERESTARTSYS; + res = videobuf_mmap_mapper(&fh->vb_vidq, vma); + mutex_unlock(&dev->lock); + return res; +} + +static const struct v4l2_file_operations tm6000_fops = { + .owner = THIS_MODULE, + .open = tm6000_open, + .release = tm6000_release, + .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ + .read = tm6000_read, + .poll = tm6000_poll, + .mmap = tm6000_mmap, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_s_std = vidioc_s_std, + .vidioc_g_std = vidioc_g_std, + .vidioc_enum_input = vidioc_enum_input, + .vidioc_g_input = vidioc_g_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_tuner = vidioc_g_tuner, + .vidioc_s_tuner = vidioc_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, + .vidioc_streamon = vidioc_streamon, + .vidioc_streamoff = vidioc_streamoff, + .vidioc_reqbufs = vidioc_reqbufs, + .vidioc_querybuf = vidioc_querybuf, + .vidioc_qbuf = vidioc_qbuf, + .vidioc_dqbuf = vidioc_dqbuf, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static struct video_device tm6000_template = { + .name = "tm6000", + .fops = &tm6000_fops, + .ioctl_ops = &video_ioctl_ops, + .release = video_device_release_empty, + .tvnorms = TM6000_STD, +}; + +static const struct v4l2_file_operations radio_fops = { + .owner = THIS_MODULE, + .open = tm6000_open, + .poll = v4l2_ctrl_poll, + .release = tm6000_release, + .unlocked_ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops radio_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_g_tuner = radio_g_tuner, + .vidioc_s_tuner = radio_s_tuner, + .vidioc_g_frequency = vidioc_g_frequency, + .vidioc_s_frequency = vidioc_s_frequency, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static struct video_device tm6000_radio_template = { + .name = "tm6000", + .fops = &radio_fops, + .ioctl_ops = &radio_ioctl_ops, +}; + +/* ----------------------------------------------------------------- + * Initialization and module stuff + * ------------------------------------------------------------------ + */ + +static void vdev_init(struct tm6000_core *dev, + struct video_device *vfd, + const struct video_device + *template, const char *type_name) +{ + *vfd = *template; + vfd->v4l2_dev = &dev->v4l2_dev; + vfd->release = video_device_release_empty; + vfd->lock = &dev->lock; + + snprintf(vfd->name, sizeof(vfd->name), "%s %s", dev->name, type_name); + + video_set_drvdata(vfd, dev); +} + +int tm6000_v4l2_register(struct tm6000_core *dev) +{ + int ret = 0; + + v4l2_ctrl_handler_init(&dev->ctrl_handler, 6); + v4l2_ctrl_handler_init(&dev->radio_ctrl_handler, 2); + v4l2_ctrl_new_std(&dev->radio_ctrl_handler, &tm6000_radio_ctrl_ops, + V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0); + v4l2_ctrl_new_std(&dev->radio_ctrl_handler, &tm6000_radio_ctrl_ops, + V4L2_CID_AUDIO_VOLUME, -15, 15, 1, 0); + v4l2_ctrl_new_std(&dev->ctrl_handler, &tm6000_ctrl_ops, + V4L2_CID_BRIGHTNESS, 0, 255, 1, 54); + v4l2_ctrl_new_std(&dev->ctrl_handler, &tm6000_ctrl_ops, + V4L2_CID_CONTRAST, 0, 255, 1, 119); + v4l2_ctrl_new_std(&dev->ctrl_handler, &tm6000_ctrl_ops, + V4L2_CID_SATURATION, 0, 255, 1, 112); + v4l2_ctrl_new_std(&dev->ctrl_handler, &tm6000_ctrl_ops, + V4L2_CID_HUE, -128, 127, 1, 0); + v4l2_ctrl_add_handler(&dev->ctrl_handler, + &dev->radio_ctrl_handler, NULL, false); + + if (dev->radio_ctrl_handler.error) + ret = dev->radio_ctrl_handler.error; + if (!ret && dev->ctrl_handler.error) + ret = dev->ctrl_handler.error; + if (ret) + goto free_ctrl; + + vdev_init(dev, &dev->vfd, &tm6000_template, "video"); + + dev->vfd.ctrl_handler = &dev->ctrl_handler; + dev->vfd.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | + V4L2_CAP_READWRITE; + if (dev->tuner_type != TUNER_ABSENT) + dev->vfd.device_caps |= V4L2_CAP_TUNER; + + /* init video dma queues */ + INIT_LIST_HEAD(&dev->vidq.active); + INIT_LIST_HEAD(&dev->vidq.queued); + + ret = video_register_device(&dev->vfd, VFL_TYPE_VIDEO, video_nr); + + if (ret < 0) { + printk(KERN_INFO "%s: can't register video device\n", + dev->name); + goto free_ctrl; + } + + printk(KERN_INFO "%s: registered device %s\n", + dev->name, video_device_node_name(&dev->vfd)); + + if (dev->caps.has_radio) { + vdev_init(dev, &dev->radio_dev, &tm6000_radio_template, + "radio"); + dev->radio_dev.ctrl_handler = &dev->radio_ctrl_handler; + dev->radio_dev.device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER; + ret = video_register_device(&dev->radio_dev, VFL_TYPE_RADIO, + radio_nr); + if (ret < 0) { + printk(KERN_INFO "%s: can't register radio device\n", + dev->name); + goto unreg_video; + } + + printk(KERN_INFO "%s: registered device %s\n", + dev->name, video_device_node_name(&dev->radio_dev)); + } + + printk(KERN_INFO "Trident TVMaster TM5600/TM6000/TM6010 USB2 board (Load status: %d)\n", ret); + return ret; + +unreg_video: + video_unregister_device(&dev->vfd); +free_ctrl: + v4l2_ctrl_handler_free(&dev->ctrl_handler); + v4l2_ctrl_handler_free(&dev->radio_ctrl_handler); + return ret; +} + +int tm6000_v4l2_unregister(struct tm6000_core *dev) +{ + video_unregister_device(&dev->vfd); + + /* if URB buffers are still allocated free them now */ + tm6000_free_urb_buffers(dev); + + video_unregister_device(&dev->radio_dev); + return 0; +} + +int tm6000_v4l2_exit(void) +{ + return 0; +} + +module_param(video_nr, int, 0); +MODULE_PARM_DESC(video_nr, "Allow changing video device number"); + +module_param_named(debug, tm6000_debug, int, 0444); +MODULE_PARM_DESC(debug, "activates debug info"); + +module_param(vid_limit, int, 0644); +MODULE_PARM_DESC(vid_limit, "capture memory limit in megabytes"); + +module_param(keep_urb, bool, 0); +MODULE_PARM_DESC(keep_urb, "Keep urb buffers allocated even when the device is closed by the user"); diff --git a/drivers/staging/media/deprecated/tm6000/tm6000.h b/drivers/staging/media/deprecated/tm6000/tm6000.h new file mode 100644 index 000000000..c08c95312 --- /dev/null +++ b/drivers/staging/media/deprecated/tm6000/tm6000.h @@ -0,0 +1,396 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * tm6000.h - driver for TM5600/TM6000/TM6010 USB video capture devices + * + * Copyright (c) 2006-2007 Mauro Carvalho Chehab + * + * Copyright (c) 2007 Michel Ludwig + * - DVB-T support + */ + +#include +#include +#include +#include "tm6000-usb-isoc.h" +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Inputs */ +enum tm6000_itype { + TM6000_INPUT_TV = 1, + TM6000_INPUT_COMPOSITE1, + TM6000_INPUT_COMPOSITE2, + TM6000_INPUT_SVIDEO, + TM6000_INPUT_DVB, + TM6000_INPUT_RADIO, +}; + +enum tm6000_mux { + TM6000_VMUX_VIDEO_A = 1, + TM6000_VMUX_VIDEO_B, + TM6000_VMUX_VIDEO_AB, + TM6000_AMUX_ADC1, + TM6000_AMUX_ADC2, + TM6000_AMUX_SIF1, + TM6000_AMUX_SIF2, + TM6000_AMUX_I2S, +}; + +enum tm6000_devtype { + TM6000 = 0, + TM5600, + TM6010, +}; + +struct tm6000_input { + enum tm6000_itype type; + enum tm6000_mux vmux; + enum tm6000_mux amux; + unsigned int v_gpio; + unsigned int a_gpio; +}; + +/* ------------------------------------------------------------------ + * Basic structures + * ------------------------------------------------------------------ + */ + +struct tm6000_fmt { + u32 fourcc; /* v4l2 format id */ + int depth; +}; + +/* buffer for one video frame */ +struct tm6000_buffer { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + + struct tm6000_fmt *fmt; +}; + +struct tm6000_dmaqueue { + struct list_head active; + struct list_head queued; + + /* thread for generating video stream*/ + struct task_struct *kthread; + wait_queue_head_t wq; + /* Counters to control fps rate */ + int frame; + int ini_jiffies; +}; + +/* device states */ +enum tm6000_core_state { + DEV_INITIALIZED = 0x01, + DEV_DISCONNECTED = 0x02, + DEV_MISCONFIGURED = 0x04, +}; + +/* io methods */ +enum tm6000_io_method { + IO_NONE, + IO_READ, + IO_MMAP, +}; + +enum tm6000_mode { + TM6000_MODE_UNKNOWN = 0, + TM6000_MODE_ANALOG, + TM6000_MODE_DIGITAL, +}; + +struct tm6000_gpio { + int tuner_reset; + int tuner_on; + int demod_reset; + int demod_on; + int power_led; + int dvb_led; + int ir; +}; + +struct tm6000_capabilities { + unsigned int has_tuner:1; + unsigned int has_tda9874:1; + unsigned int has_dvb:1; + unsigned int has_zl10353:1; + unsigned int has_eeprom:1; + unsigned int has_remote:1; + unsigned int has_radio:1; +}; + +struct tm6000_dvb { + struct dvb_adapter adapter; + struct dvb_demux demux; + struct dvb_frontend *frontend; + struct dmxdev dmxdev; + unsigned int streams; + struct urb *bulk_urb; + struct mutex mutex; +}; + +struct snd_tm6000_card { + struct snd_card *card; + spinlock_t reg_lock; + struct tm6000_core *core; + struct snd_pcm_substream *substream; + + /* temporary data for buffer fill processing */ + unsigned buf_pos; + unsigned period_pos; +}; + +struct tm6000_endpoint { + struct usb_host_endpoint *endp; + __u8 bInterfaceNumber; + __u8 bAlternateSetting; + unsigned maxsize; +}; + +#define TM6000_QUIRK_NO_USB_DELAY (1 << 0) + +struct tm6000_core { + /* generic device properties */ + char name[30]; /* name (including minor) of the device */ + int model; /* index in the device_data struct */ + int devno; /* marks the number of this device */ + enum tm6000_devtype dev_type; /* type of device */ + unsigned char eedata[256]; /* Eeprom data */ + unsigned eedata_size; /* Size of the eeprom info */ + + v4l2_std_id norm; /* Current norm */ + int width, height; /* Selected resolution */ + + enum tm6000_core_state state; + + /* Device Capabilities*/ + struct tm6000_capabilities caps; + + /* Used to load alsa/dvb */ + struct work_struct request_module_wk; + + /* Tuner configuration */ + int tuner_type; /* type of the tuner */ + int tuner_addr; /* tuner address */ + + struct tm6000_gpio gpio; + + char *ir_codes; + + __u8 radio; + + /* Demodulator configuration */ + int demod_addr; /* demodulator address */ + + int audio_bitrate; + /* i2c i/o */ + struct i2c_adapter i2c_adap; + struct i2c_client i2c_client; + + + /* extension */ + struct list_head devlist; + + /* video for linux */ + int users; + + /* various device info */ + struct tm6000_fh *resources; /* Points to fh that is streaming */ + bool is_res_read; + + struct video_device vfd; + struct video_device radio_dev; + struct tm6000_dmaqueue vidq; + struct v4l2_device v4l2_dev; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl_handler radio_ctrl_handler; + + int input; + struct tm6000_input vinput[3]; /* video input */ + struct tm6000_input rinput; /* radio input */ + + int freq; + unsigned int fourcc; + + enum tm6000_mode mode; + + int ctl_mute; /* audio */ + int ctl_volume; + int amode; + + /* DVB-T support */ + struct tm6000_dvb *dvb; + + /* audio support */ + struct snd_tm6000_card *adev; + struct work_struct wq_trigger; /* Trigger to start/stop audio for alsa module */ + atomic_t stream_started; /* stream should be running if true */ + + struct tm6000_IR *ir; + + /* locks */ + struct mutex lock; + struct mutex usb_lock; + + /* usb transfer */ + struct usb_device *udev; /* the usb device */ + + struct tm6000_endpoint bulk_in, bulk_out, isoc_in, isoc_out; + struct tm6000_endpoint int_in, int_out; + + /* scaler!=0 if scaler is active*/ + int scaler; + + /* Isoc control struct */ + struct usb_isoc_ctl isoc_ctl; + + spinlock_t slock; + + /* urb dma buffers */ + char **urb_buffer; + dma_addr_t *urb_dma; + unsigned int urb_size; + + unsigned long quirks; +}; + +enum tm6000_ops_type { + TM6000_AUDIO = 0x10, + TM6000_DVB = 0x20, +}; + +struct tm6000_ops { + struct list_head next; + char *name; + enum tm6000_ops_type type; + int (*init)(struct tm6000_core *); + int (*fini)(struct tm6000_core *); + int (*fillbuf)(struct tm6000_core *, char *buf, int size); +}; + +struct tm6000_fh { + struct v4l2_fh fh; + struct tm6000_core *dev; + unsigned int radio; + + /* video capture */ + struct tm6000_fmt *fmt; + unsigned int width, height; + struct videobuf_queue vb_vidq; + + enum v4l2_buf_type type; +}; + +#define TM6000_STD (V4L2_STD_PAL|V4L2_STD_PAL_N|V4L2_STD_PAL_Nc| \ + V4L2_STD_PAL_M|V4L2_STD_PAL_60|V4L2_STD_NTSC_M| \ + V4L2_STD_NTSC_M_JP|V4L2_STD_SECAM) + +/* In tm6000-cards.c */ + +int tm6000_tuner_callback(void *ptr, int component, int command, int arg); +int tm6000_xc5000_callback(void *ptr, int component, int command, int arg); +int tm6000_cards_setup(struct tm6000_core *dev); +void tm6000_flash_led(struct tm6000_core *dev, u8 state); + +/* In tm6000-core.c */ + +int tm6000_read_write_usb(struct tm6000_core *dev, u8 reqtype, u8 req, + u16 value, u16 index, u8 *buf, u16 len); +int tm6000_get_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index); +int tm6000_get_reg16(struct tm6000_core *dev, u8 req, u16 value, u16 index); +int tm6000_get_reg32(struct tm6000_core *dev, u8 req, u16 value, u16 index); +int tm6000_set_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index); +int tm6000_set_reg_mask(struct tm6000_core *dev, u8 req, u16 value, + u16 index, u16 mask); +int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep); +int tm6000_init(struct tm6000_core *dev); +int tm6000_reset(struct tm6000_core *dev); + +int tm6000_init_analog_mode(struct tm6000_core *dev); +int tm6000_init_digital_mode(struct tm6000_core *dev); +int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate); +int tm6000_set_audio_rinput(struct tm6000_core *dev); +int tm6000_tvaudio_set_mute(struct tm6000_core *dev, u8 mute); +void tm6000_set_volume(struct tm6000_core *dev, int vol); + +int tm6000_v4l2_register(struct tm6000_core *dev); +int tm6000_v4l2_unregister(struct tm6000_core *dev); +int tm6000_v4l2_exit(void); +void tm6000_set_fourcc_format(struct tm6000_core *dev); + +void tm6000_remove_from_devlist(struct tm6000_core *dev); +void tm6000_add_into_devlist(struct tm6000_core *dev); +int tm6000_register_extension(struct tm6000_ops *ops); +void tm6000_unregister_extension(struct tm6000_ops *ops); +void tm6000_init_extension(struct tm6000_core *dev); +void tm6000_close_extension(struct tm6000_core *dev); +int tm6000_call_fillbuf(struct tm6000_core *dev, enum tm6000_ops_type type, + char *buf, int size); + + +/* In tm6000-stds.c */ +void tm6000_get_std_res(struct tm6000_core *dev); +int tm6000_set_standard(struct tm6000_core *dev); + +/* In tm6000-i2c.c */ +int tm6000_i2c_register(struct tm6000_core *dev); +int tm6000_i2c_unregister(struct tm6000_core *dev); + +/* In tm6000-queue.c */ + +int tm6000_v4l2_mmap(struct file *filp, struct vm_area_struct *vma); + +int tm6000_vidioc_streamon(struct file *file, void *priv, + enum v4l2_buf_type i); +int tm6000_vidioc_streamoff(struct file *file, void *priv, + enum v4l2_buf_type i); +int tm6000_vidioc_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *rb); +int tm6000_vidioc_querybuf(struct file *file, void *priv, + struct v4l2_buffer *b); +int tm6000_vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *b); +int tm6000_vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b); +ssize_t tm6000_v4l2_read(struct file *filp, char __user * buf, size_t count, + loff_t *f_pos); +unsigned int tm6000_v4l2_poll(struct file *file, + struct poll_table_struct *wait); +int tm6000_queue_init(struct tm6000_core *dev); + +/* In tm6000-alsa.c */ +/*int tm6000_audio_init(struct tm6000_core *dev, int idx);*/ + +/* In tm6000-input.c */ +int tm6000_ir_init(struct tm6000_core *dev); +int tm6000_ir_fini(struct tm6000_core *dev); +void tm6000_ir_wait(struct tm6000_core *dev, u8 state); +int tm6000_ir_int_start(struct tm6000_core *dev); +void tm6000_ir_int_stop(struct tm6000_core *dev); + +/* Debug stuff */ + +extern int tm6000_debug; + +#define dprintk(dev, level, fmt, arg...) do {\ + if (tm6000_debug & level) \ + printk(KERN_INFO "(%lu) %s %s :"fmt, jiffies, \ + dev->name, __func__ , ##arg); } while (0) + +#define V4L2_DEBUG_REG 0x0004 +#define V4L2_DEBUG_I2C 0x0008 +#define V4L2_DEBUG_QUEUE 0x0010 +#define V4L2_DEBUG_ISOC 0x0020 +#define V4L2_DEBUG_RES_LOCK 0x0040 /* Resource locking */ +#define V4L2_DEBUG_OPEN 0x0080 /* video open/close debug */ + +#define tm6000_err(fmt, arg...) do {\ + printk(KERN_ERR "tm6000 %s :"fmt, \ + __func__ , ##arg); } while (0) diff --git a/drivers/staging/media/deprecated/zr364xx/Kconfig b/drivers/staging/media/deprecated/zr364xx/Kconfig new file mode 100644 index 000000000..ea29c9d8d --- /dev/null +++ b/drivers/staging/media/deprecated/zr364xx/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +config USB_ZR364XX + tristate "USB ZR364XX Camera support (DEPRECATED)" + depends on USB && VIDEO_DEV + select VIDEOBUF_GEN + select VIDEOBUF_VMALLOC + help + Say Y here if you want to connect this type of camera to your + computer's USB port. + See for more info + and list of supported cameras. + + This driver is deprecated and is scheduled for removal by + the beginning of 2023. See the TODO file for more information. + + To compile this driver as a module, choose M here: the + module will be called zr364xx. + diff --git a/drivers/staging/media/deprecated/zr364xx/Makefile b/drivers/staging/media/deprecated/zr364xx/Makefile new file mode 100644 index 000000000..edab017d4 --- /dev/null +++ b/drivers/staging/media/deprecated/zr364xx/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_USB_ZR364XX) += zr364xx.o + diff --git a/drivers/staging/media/deprecated/zr364xx/TODO b/drivers/staging/media/deprecated/zr364xx/TODO new file mode 100644 index 000000000..ecb30a429 --- /dev/null +++ b/drivers/staging/media/deprecated/zr364xx/TODO @@ -0,0 +1,7 @@ +This is one of the few drivers still not using the vb2 +framework, so this driver is now deprecated with the intent of +removing it altogether by the beginning of 2023. + +In order to keep this driver it has to be converted to vb2. +If someone is interested in doing this work, then contact the +linux-media mailinglist (https://linuxtv.org/lists.php). diff --git a/drivers/staging/media/deprecated/zr364xx/zr364xx.c b/drivers/staging/media/deprecated/zr364xx/zr364xx.c new file mode 100644 index 000000000..538a33004 --- /dev/null +++ b/drivers/staging/media/deprecated/zr364xx/zr364xx.c @@ -0,0 +1,1635 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Zoran 364xx based USB webcam module version 0.73 + * + * Allows you to use your USB webcam with V4L2 applications + * This is still in heavy development ! + * + * Copyright (C) 2004 Antoine Jacquet + * http://royale.zerezo.com/zr364xx/ + * + * Heavily inspired by usb-skeleton.c, vicam.c, cpia.c and spca50x.c drivers + * V4L2 version inspired by meye.c driver + * + * Some video buffer code by Lamarque based on s2255drv.c and vivi.c drivers. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Version Information */ +#define DRIVER_VERSION "0.7.4" +#define DRIVER_AUTHOR "Antoine Jacquet, http://royale.zerezo.com/" +#define DRIVER_DESC "Zoran 364xx" + + +/* Camera */ +#define FRAMES 1 +#define MAX_FRAME_SIZE 200000 +#define BUFFER_SIZE 0x1000 +#define CTRL_TIMEOUT 500 + +#define ZR364XX_DEF_BUFS 4 +#define ZR364XX_READ_IDLE 0 +#define ZR364XX_READ_FRAME 1 + +/* Debug macro */ +#define DBG(fmt, args...) \ + do { \ + if (debug) { \ + printk(KERN_INFO KBUILD_MODNAME " " fmt, ##args); \ + } \ + } while (0) + +/*#define FULL_DEBUG 1*/ +#ifdef FULL_DEBUG +#define _DBG DBG +#else +#define _DBG(fmt, args...) +#endif + +/* Init methods, need to find nicer names for these + * the exact names of the chipsets would be the best if someone finds it */ +#define METHOD0 0 +#define METHOD1 1 +#define METHOD2 2 +#define METHOD3 3 + + +/* Module parameters */ +static int debug; +static int mode; + + +/* Module parameters interface */ +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level"); +module_param(mode, int, 0644); +MODULE_PARM_DESC(mode, "0 = 320x240, 1 = 160x120, 2 = 640x480"); + + +/* Devices supported by this driver + * .driver_info contains the init method used by the camera */ +static const struct usb_device_id device_table[] = { + {USB_DEVICE(0x08ca, 0x0109), .driver_info = METHOD0 }, + {USB_DEVICE(0x041e, 0x4024), .driver_info = METHOD0 }, + {USB_DEVICE(0x0d64, 0x0108), .driver_info = METHOD0 }, + {USB_DEVICE(0x0546, 0x3187), .driver_info = METHOD0 }, + {USB_DEVICE(0x0d64, 0x3108), .driver_info = METHOD0 }, + {USB_DEVICE(0x0595, 0x4343), .driver_info = METHOD0 }, + {USB_DEVICE(0x0bb0, 0x500d), .driver_info = METHOD0 }, + {USB_DEVICE(0x0feb, 0x2004), .driver_info = METHOD0 }, + {USB_DEVICE(0x055f, 0xb500), .driver_info = METHOD0 }, + {USB_DEVICE(0x08ca, 0x2062), .driver_info = METHOD2 }, + {USB_DEVICE(0x052b, 0x1a18), .driver_info = METHOD1 }, + {USB_DEVICE(0x04c8, 0x0729), .driver_info = METHOD0 }, + {USB_DEVICE(0x04f2, 0xa208), .driver_info = METHOD0 }, + {USB_DEVICE(0x0784, 0x0040), .driver_info = METHOD1 }, + {USB_DEVICE(0x06d6, 0x0034), .driver_info = METHOD0 }, + {USB_DEVICE(0x0a17, 0x0062), .driver_info = METHOD2 }, + {USB_DEVICE(0x06d6, 0x003b), .driver_info = METHOD0 }, + {USB_DEVICE(0x0a17, 0x004e), .driver_info = METHOD2 }, + {USB_DEVICE(0x041e, 0x405d), .driver_info = METHOD2 }, + {USB_DEVICE(0x08ca, 0x2102), .driver_info = METHOD3 }, + {USB_DEVICE(0x06d6, 0x003d), .driver_info = METHOD0 }, + {} /* Terminating entry */ +}; + +MODULE_DEVICE_TABLE(usb, device_table); + +/* frame structure */ +struct zr364xx_framei { + unsigned long ulState; /* ulState:ZR364XX_READ_IDLE, + ZR364XX_READ_FRAME */ + void *lpvbits; /* image data */ + unsigned long cur_size; /* current data copied to it */ +}; + +/* image buffer structure */ +struct zr364xx_bufferi { + unsigned long dwFrames; /* number of frames in buffer */ + struct zr364xx_framei frame[FRAMES]; /* array of FRAME structures */ +}; + +struct zr364xx_dmaqueue { + struct list_head active; + struct zr364xx_camera *cam; +}; + +struct zr364xx_pipeinfo { + u32 transfer_size; + u8 *transfer_buffer; + u32 state; + void *stream_urb; + void *cam; /* back pointer to zr364xx_camera struct */ + u32 err_count; + u32 idx; +}; + +struct zr364xx_fmt { + u32 fourcc; + int depth; +}; + +/* image formats. */ +static const struct zr364xx_fmt formats[] = { + { + .fourcc = V4L2_PIX_FMT_JPEG, + .depth = 24 + } +}; + +/* Camera stuff */ +struct zr364xx_camera { + struct usb_device *udev; /* save off the usb device pointer */ + struct usb_interface *interface;/* the interface for this device */ + struct v4l2_device v4l2_dev; + struct v4l2_ctrl_handler ctrl_handler; + struct video_device vdev; /* v4l video device */ + struct v4l2_fh *owner; /* owns the streaming */ + int nb; + struct zr364xx_bufferi buffer; + int skip; + int width; + int height; + int method; + struct mutex lock; + + spinlock_t slock; + struct zr364xx_dmaqueue vidq; + int last_frame; + int cur_frame; + unsigned long frame_count; + int b_acquire; + struct zr364xx_pipeinfo pipe[1]; + + u8 read_endpoint; + + const struct zr364xx_fmt *fmt; + struct videobuf_queue vb_vidq; + bool was_streaming; +}; + +/* buffer for one video frame */ +struct zr364xx_buffer { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + const struct zr364xx_fmt *fmt; +}; + +/* function used to send initialisation commands to the camera */ +static int send_control_msg(struct usb_device *udev, u8 request, u16 value, + u16 index, unsigned char *cp, u16 size) +{ + int status; + + unsigned char *transfer_buffer = kmemdup(cp, size, GFP_KERNEL); + if (!transfer_buffer) + return -ENOMEM; + + status = usb_control_msg(udev, + usb_sndctrlpipe(udev, 0), + request, + USB_DIR_OUT | USB_TYPE_VENDOR | + USB_RECIP_DEVICE, value, index, + transfer_buffer, size, CTRL_TIMEOUT); + + kfree(transfer_buffer); + return status; +} + + +/* Control messages sent to the camera to initialize it + * and launch the capture */ +typedef struct { + unsigned int value; + unsigned int size; + unsigned char *bytes; +} message; + +/* method 0 */ +static unsigned char m0d1[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +static unsigned char m0d2[] = { 0, 0, 0, 0, 0, 0 }; +static unsigned char m0d3[] = { 0, 0 }; +static message m0[] = { + {0x1f30, 0, NULL}, + {0xd000, 0, NULL}, + {0x3370, sizeof(m0d1), m0d1}, + {0x2000, 0, NULL}, + {0x2f0f, 0, NULL}, + {0x2610, sizeof(m0d2), m0d2}, + {0xe107, 0, NULL}, + {0x2502, 0, NULL}, + {0x1f70, 0, NULL}, + {0xd000, 0, NULL}, + {0x9a01, sizeof(m0d3), m0d3}, + {-1, -1, NULL} +}; + +/* method 1 */ +static unsigned char m1d1[] = { 0xff, 0xff }; +static unsigned char m1d2[] = { 0x00, 0x00 }; +static message m1[] = { + {0x1f30, 0, NULL}, + {0xd000, 0, NULL}, + {0xf000, 0, NULL}, + {0x2000, 0, NULL}, + {0x2f0f, 0, NULL}, + {0x2650, 0, NULL}, + {0xe107, 0, NULL}, + {0x2502, sizeof(m1d1), m1d1}, + {0x1f70, 0, NULL}, + {0xd000, 0, NULL}, + {0xd000, 0, NULL}, + {0xd000, 0, NULL}, + {0x9a01, sizeof(m1d2), m1d2}, + {-1, -1, NULL} +}; + +/* method 2 */ +static unsigned char m2d1[] = { 0xff, 0xff }; +static message m2[] = { + {0x1f30, 0, NULL}, + {0xf000, 0, NULL}, + {0x2000, 0, NULL}, + {0x2f0f, 0, NULL}, + {0x2650, 0, NULL}, + {0xe107, 0, NULL}, + {0x2502, sizeof(m2d1), m2d1}, + {0x1f70, 0, NULL}, + {-1, -1, NULL} +}; + +/* init table */ +static message *init[4] = { m0, m1, m2, m2 }; + + +/* JPEG static data in header (Huffman table, etc) */ +static unsigned char header1[] = { + 0xFF, 0xD8, + /* + 0xFF, 0xE0, 0x00, 0x10, 'J', 'F', 'I', 'F', + 0x00, 0x01, 0x01, 0x00, 0x33, 0x8A, 0x00, 0x00, 0x33, 0x88, + */ + 0xFF, 0xDB, 0x00, 0x84 +}; +static unsigned char header2[] = { + 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, + 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, + 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, + 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, + 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, + 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, + 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, + 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, + 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, + 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, + 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, + 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, + 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, + 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, + 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, + 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, + 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00, 0x1F, + 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, + 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, + 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, + 0x04, 0x04, 0x00, 0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, + 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, + 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, + 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, + 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, + 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, + 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, + 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, + 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, + 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, + 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, + 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, + 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, + 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, + 0xF8, 0xF9, 0xFA, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0xF0, 0x01, + 0x40, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, + 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, + 0x00, 0x3F, 0x00 +}; +static unsigned char header3; + +/* ------------------------------------------------------------------ + Videobuf operations + ------------------------------------------------------------------*/ + +static int buffer_setup(struct videobuf_queue *vq, unsigned int *count, + unsigned int *size) +{ + struct zr364xx_camera *cam = vq->priv_data; + + *size = cam->width * cam->height * (cam->fmt->depth >> 3); + + if (*count == 0) + *count = ZR364XX_DEF_BUFS; + + if (*size * *count > ZR364XX_DEF_BUFS * 1024 * 1024) + *count = (ZR364XX_DEF_BUFS * 1024 * 1024) / *size; + + return 0; +} + +static void free_buffer(struct videobuf_queue *vq, struct zr364xx_buffer *buf) +{ + _DBG("%s\n", __func__); + + videobuf_vmalloc_free(&buf->vb); + buf->vb.state = VIDEOBUF_NEEDS_INIT; +} + +static int buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct zr364xx_camera *cam = vq->priv_data; + struct zr364xx_buffer *buf = container_of(vb, struct zr364xx_buffer, + vb); + int rc; + + DBG("%s, field=%d\n", __func__, field); + if (!cam->fmt) + return -EINVAL; + + buf->vb.size = cam->width * cam->height * (cam->fmt->depth >> 3); + + if (buf->vb.baddr != 0 && buf->vb.bsize < buf->vb.size) { + DBG("invalid buffer prepare\n"); + return -EINVAL; + } + + buf->fmt = cam->fmt; + buf->vb.width = cam->width; + buf->vb.height = cam->height; + buf->vb.field = field; + + if (buf->vb.state == VIDEOBUF_NEEDS_INIT) { + rc = videobuf_iolock(vq, &buf->vb, NULL); + if (rc < 0) + goto fail; + } + + buf->vb.state = VIDEOBUF_PREPARED; + return 0; +fail: + free_buffer(vq, buf); + return rc; +} + +static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) +{ + struct zr364xx_buffer *buf = container_of(vb, struct zr364xx_buffer, + vb); + struct zr364xx_camera *cam = vq->priv_data; + + _DBG("%s\n", __func__); + + buf->vb.state = VIDEOBUF_QUEUED; + list_add_tail(&buf->vb.queue, &cam->vidq.active); +} + +static void buffer_release(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct zr364xx_buffer *buf = container_of(vb, struct zr364xx_buffer, + vb); + + _DBG("%s\n", __func__); + free_buffer(vq, buf); +} + +static const struct videobuf_queue_ops zr364xx_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +/********************/ +/* V4L2 integration */ +/********************/ +static int zr364xx_vidioc_streamon(struct file *file, void *priv, + enum v4l2_buf_type type); + +static ssize_t zr364xx_read(struct file *file, char __user *buf, size_t count, + loff_t * ppos) +{ + struct zr364xx_camera *cam = video_drvdata(file); + int err = 0; + + _DBG("%s\n", __func__); + + if (!buf) + return -EINVAL; + + if (!count) + return -EINVAL; + + if (mutex_lock_interruptible(&cam->lock)) + return -ERESTARTSYS; + + err = zr364xx_vidioc_streamon(file, file->private_data, + V4L2_BUF_TYPE_VIDEO_CAPTURE); + if (err == 0) { + DBG("%s: reading %d bytes at pos %d.\n", __func__, + (int) count, (int) *ppos); + + /* NoMan Sux ! */ + err = videobuf_read_one(&cam->vb_vidq, buf, count, ppos, + file->f_flags & O_NONBLOCK); + } + mutex_unlock(&cam->lock); + return err; +} + +/* video buffer vmalloc implementation based partly on VIVI driver which is + * Copyright (c) 2006 by + * Mauro Carvalho Chehab + * Ted Walther + * John Sokol + * http://v4l.videotechnology.com/ + * + */ +static void zr364xx_fillbuff(struct zr364xx_camera *cam, + struct zr364xx_buffer *buf, + int jpgsize) +{ + int pos = 0; + const char *tmpbuf; + char *vbuf = videobuf_to_vmalloc(&buf->vb); + unsigned long last_frame; + + if (!vbuf) + return; + + last_frame = cam->last_frame; + if (last_frame != -1) { + tmpbuf = (const char *)cam->buffer.frame[last_frame].lpvbits; + switch (buf->fmt->fourcc) { + case V4L2_PIX_FMT_JPEG: + buf->vb.size = jpgsize; + memcpy(vbuf, tmpbuf, buf->vb.size); + break; + default: + printk(KERN_DEBUG KBUILD_MODNAME ": unknown format?\n"); + } + cam->last_frame = -1; + } else { + printk(KERN_ERR KBUILD_MODNAME ": =======no frame\n"); + return; + } + DBG("%s: Buffer %p size= %d\n", __func__, vbuf, pos); + /* tell v4l buffer was filled */ + + buf->vb.field_count = cam->frame_count * 2; + buf->vb.ts = ktime_get_ns(); + buf->vb.state = VIDEOBUF_DONE; +} + +static int zr364xx_got_frame(struct zr364xx_camera *cam, int jpgsize) +{ + struct zr364xx_dmaqueue *dma_q = &cam->vidq; + struct zr364xx_buffer *buf; + unsigned long flags = 0; + int rc = 0; + + DBG("wakeup: %p\n", &dma_q); + spin_lock_irqsave(&cam->slock, flags); + + if (list_empty(&dma_q->active)) { + DBG("No active queue to serve\n"); + rc = -1; + goto unlock; + } + buf = list_entry(dma_q->active.next, + struct zr364xx_buffer, vb.queue); + + if (!waitqueue_active(&buf->vb.done)) { + /* no one active */ + rc = -1; + goto unlock; + } + list_del(&buf->vb.queue); + buf->vb.ts = ktime_get_ns(); + DBG("[%p/%d] wakeup\n", buf, buf->vb.i); + zr364xx_fillbuff(cam, buf, jpgsize); + wake_up(&buf->vb.done); + DBG("wakeup [buf/i] [%p/%d]\n", buf, buf->vb.i); +unlock: + spin_unlock_irqrestore(&cam->slock, flags); + return rc; +} + +/* this function moves the usb stream read pipe data + * into the system buffers. + * returns 0 on success, EAGAIN if more data to process (call this + * function again). + */ +static int zr364xx_read_video_callback(struct zr364xx_camera *cam, + struct zr364xx_pipeinfo *pipe_info, + struct urb *purb) +{ + unsigned char *pdest; + unsigned char *psrc; + s32 idx = cam->cur_frame; + struct zr364xx_framei *frm = &cam->buffer.frame[idx]; + int i = 0; + unsigned char *ptr = NULL; + + _DBG("buffer to user\n"); + + /* swap bytes if camera needs it */ + if (cam->method == METHOD0) { + u16 *buf = (u16 *)pipe_info->transfer_buffer; + for (i = 0; i < purb->actual_length/2; i++) + swab16s(buf + i); + } + + /* search done. now find out if should be acquiring */ + if (!cam->b_acquire) { + /* we found a frame, but this channel is turned off */ + frm->ulState = ZR364XX_READ_IDLE; + return -EINVAL; + } + + psrc = (u8 *)pipe_info->transfer_buffer; + ptr = pdest = frm->lpvbits; + + if (frm->ulState == ZR364XX_READ_IDLE) { + if (purb->actual_length < 128) { + /* header incomplete */ + dev_info(&cam->udev->dev, + "%s: buffer (%d bytes) too small to hold jpeg header. Discarding.\n", + __func__, purb->actual_length); + return -EINVAL; + } + + frm->ulState = ZR364XX_READ_FRAME; + frm->cur_size = 0; + + _DBG("jpeg header, "); + memcpy(ptr, header1, sizeof(header1)); + ptr += sizeof(header1); + header3 = 0; + memcpy(ptr, &header3, 1); + ptr++; + memcpy(ptr, psrc, 64); + ptr += 64; + header3 = 1; + memcpy(ptr, &header3, 1); + ptr++; + memcpy(ptr, psrc + 64, 64); + ptr += 64; + memcpy(ptr, header2, sizeof(header2)); + ptr += sizeof(header2); + memcpy(ptr, psrc + 128, + purb->actual_length - 128); + ptr += purb->actual_length - 128; + _DBG("header : %d %d %d %d %d %d %d %d %d\n", + psrc[0], psrc[1], psrc[2], + psrc[3], psrc[4], psrc[5], + psrc[6], psrc[7], psrc[8]); + frm->cur_size = ptr - pdest; + } else { + if (frm->cur_size + purb->actual_length > MAX_FRAME_SIZE) { + dev_info(&cam->udev->dev, + "%s: buffer (%d bytes) too small to hold frame data. Discarding frame data.\n", + __func__, MAX_FRAME_SIZE); + } else { + pdest += frm->cur_size; + memcpy(pdest, psrc, purb->actual_length); + frm->cur_size += purb->actual_length; + } + } + /*_DBG("cur_size %lu urb size %d\n", frm->cur_size, + purb->actual_length);*/ + + if (purb->actual_length < pipe_info->transfer_size) { + _DBG("****************Buffer[%d]full*************\n", idx); + cam->last_frame = cam->cur_frame; + cam->cur_frame++; + /* end of system frame ring buffer, start at zero */ + if (cam->cur_frame == cam->buffer.dwFrames) + cam->cur_frame = 0; + + /* frame ready */ + /* go back to find the JPEG EOI marker */ + ptr = pdest = frm->lpvbits; + ptr += frm->cur_size - 2; + while (ptr > pdest) { + if (*ptr == 0xFF && *(ptr + 1) == 0xD9 + && *(ptr + 2) == 0xFF) + break; + ptr--; + } + if (ptr == pdest) + DBG("No EOI marker\n"); + + /* Sometimes there is junk data in the middle of the picture, + * we want to skip this bogus frames */ + while (ptr > pdest) { + if (*ptr == 0xFF && *(ptr + 1) == 0xFF + && *(ptr + 2) == 0xFF) + break; + ptr--; + } + if (ptr != pdest) { + DBG("Bogus frame ? %d\n", ++(cam->nb)); + } else if (cam->b_acquire) { + /* we skip the 2 first frames which are usually buggy */ + if (cam->skip) + cam->skip--; + else { + _DBG("jpeg(%lu): %d %d %d %d %d %d %d %d\n", + frm->cur_size, + pdest[0], pdest[1], pdest[2], pdest[3], + pdest[4], pdest[5], pdest[6], pdest[7]); + + zr364xx_got_frame(cam, frm->cur_size); + } + } + cam->frame_count++; + frm->ulState = ZR364XX_READ_IDLE; + frm->cur_size = 0; + } + /* done successfully */ + return 0; +} + +static int zr364xx_vidioc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct zr364xx_camera *cam = video_drvdata(file); + + strscpy(cap->driver, DRIVER_DESC, sizeof(cap->driver)); + if (cam->udev->product) + strscpy(cap->card, cam->udev->product, sizeof(cap->card)); + strscpy(cap->bus_info, dev_name(&cam->udev->dev), + sizeof(cap->bus_info)); + return 0; +} + +static int zr364xx_vidioc_enum_input(struct file *file, void *priv, + struct v4l2_input *i) +{ + if (i->index != 0) + return -EINVAL; + strscpy(i->name, DRIVER_DESC " Camera", sizeof(i->name)); + i->type = V4L2_INPUT_TYPE_CAMERA; + return 0; +} + +static int zr364xx_vidioc_g_input(struct file *file, void *priv, + unsigned int *i) +{ + *i = 0; + return 0; +} + +static int zr364xx_vidioc_s_input(struct file *file, void *priv, + unsigned int i) +{ + if (i != 0) + return -EINVAL; + return 0; +} + +static int zr364xx_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct zr364xx_camera *cam = + container_of(ctrl->handler, struct zr364xx_camera, ctrl_handler); + int temp; + + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + /* hardware brightness */ + send_control_msg(cam->udev, 1, 0x2001, 0, NULL, 0); + temp = (0x60 << 8) + 127 - ctrl->val; + send_control_msg(cam->udev, 1, temp, 0, NULL, 0); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int zr364xx_vidioc_enum_fmt_vid_cap(struct file *file, + void *priv, struct v4l2_fmtdesc *f) +{ + if (f->index > 0) + return -EINVAL; + f->pixelformat = formats[0].fourcc; + return 0; +} + +static char *decode_fourcc(__u32 pixelformat, char *buf) +{ + buf[0] = pixelformat & 0xff; + buf[1] = (pixelformat >> 8) & 0xff; + buf[2] = (pixelformat >> 16) & 0xff; + buf[3] = (pixelformat >> 24) & 0xff; + buf[4] = '\0'; + return buf; +} + +static int zr364xx_vidioc_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct zr364xx_camera *cam = video_drvdata(file); + char pixelformat_name[5]; + + if (!cam) + return -ENODEV; + + if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_JPEG) { + DBG("%s: unsupported pixelformat V4L2_PIX_FMT_%s\n", __func__, + decode_fourcc(f->fmt.pix.pixelformat, pixelformat_name)); + return -EINVAL; + } + + if (!(f->fmt.pix.width == 160 && f->fmt.pix.height == 120) && + !(f->fmt.pix.width == 640 && f->fmt.pix.height == 480)) { + f->fmt.pix.width = 320; + f->fmt.pix.height = 240; + } + + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.bytesperline = f->fmt.pix.width * 2; + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; + DBG("%s: V4L2_PIX_FMT_%s (%d) ok!\n", __func__, + decode_fourcc(f->fmt.pix.pixelformat, pixelformat_name), + f->fmt.pix.field); + return 0; +} + +static int zr364xx_vidioc_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct zr364xx_camera *cam; + + if (!file) + return -ENODEV; + cam = video_drvdata(file); + + f->fmt.pix.pixelformat = formats[0].fourcc; + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.width = cam->width; + f->fmt.pix.height = cam->height; + f->fmt.pix.bytesperline = f->fmt.pix.width * 2; + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; + return 0; +} + +static int zr364xx_vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct zr364xx_camera *cam = video_drvdata(file); + struct videobuf_queue *q = &cam->vb_vidq; + char pixelformat_name[5]; + int ret = zr364xx_vidioc_try_fmt_vid_cap(file, cam, f); + int i; + + if (ret < 0) + return ret; + + mutex_lock(&q->vb_lock); + + if (videobuf_queue_is_busy(&cam->vb_vidq)) { + DBG("%s queue busy\n", __func__); + ret = -EBUSY; + goto out; + } + + if (cam->owner) { + DBG("%s can't change format after started\n", __func__); + ret = -EBUSY; + goto out; + } + + cam->width = f->fmt.pix.width; + cam->height = f->fmt.pix.height; + DBG("%s: %dx%d mode selected\n", __func__, + cam->width, cam->height); + f->fmt.pix.bytesperline = f->fmt.pix.width * 2; + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; + cam->vb_vidq.field = f->fmt.pix.field; + + if (f->fmt.pix.width == 160 && f->fmt.pix.height == 120) + mode = 1; + else if (f->fmt.pix.width == 640 && f->fmt.pix.height == 480) + mode = 2; + else + mode = 0; + + m0d1[0] = mode; + m1[2].value = 0xf000 + mode; + m2[1].value = 0xf000 + mode; + + /* special case for METHOD3, the modes are different */ + if (cam->method == METHOD3) { + switch (mode) { + case 1: + m2[1].value = 0xf000 + 4; + break; + case 2: + m2[1].value = 0xf000 + 0; + break; + default: + m2[1].value = 0xf000 + 1; + break; + } + } + + header2[437] = cam->height / 256; + header2[438] = cam->height % 256; + header2[439] = cam->width / 256; + header2[440] = cam->width % 256; + + for (i = 0; init[cam->method][i].size != -1; i++) { + ret = + send_control_msg(cam->udev, 1, init[cam->method][i].value, + 0, init[cam->method][i].bytes, + init[cam->method][i].size); + if (ret < 0) { + dev_err(&cam->udev->dev, + "error during resolution change sequence: %d\n", i); + goto out; + } + } + + /* Added some delay here, since opening/closing the camera quickly, + * like Ekiga does during its startup, can crash the webcam + */ + mdelay(100); + cam->skip = 2; + ret = 0; + +out: + mutex_unlock(&q->vb_lock); + + DBG("%s: V4L2_PIX_FMT_%s (%d) ok!\n", __func__, + decode_fourcc(f->fmt.pix.pixelformat, pixelformat_name), + f->fmt.pix.field); + return ret; +} + +static int zr364xx_vidioc_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *p) +{ + struct zr364xx_camera *cam = video_drvdata(file); + + if (cam->owner && cam->owner != priv) + return -EBUSY; + return videobuf_reqbufs(&cam->vb_vidq, p); +} + +static int zr364xx_vidioc_querybuf(struct file *file, + void *priv, + struct v4l2_buffer *p) +{ + int rc; + struct zr364xx_camera *cam = video_drvdata(file); + rc = videobuf_querybuf(&cam->vb_vidq, p); + return rc; +} + +static int zr364xx_vidioc_qbuf(struct file *file, + void *priv, + struct v4l2_buffer *p) +{ + int rc; + struct zr364xx_camera *cam = video_drvdata(file); + _DBG("%s\n", __func__); + if (cam->owner && cam->owner != priv) + return -EBUSY; + rc = videobuf_qbuf(&cam->vb_vidq, p); + return rc; +} + +static int zr364xx_vidioc_dqbuf(struct file *file, + void *priv, + struct v4l2_buffer *p) +{ + int rc; + struct zr364xx_camera *cam = video_drvdata(file); + _DBG("%s\n", __func__); + if (cam->owner && cam->owner != priv) + return -EBUSY; + rc = videobuf_dqbuf(&cam->vb_vidq, p, file->f_flags & O_NONBLOCK); + return rc; +} + +static void read_pipe_completion(struct urb *purb) +{ + struct zr364xx_pipeinfo *pipe_info; + struct zr364xx_camera *cam; + int pipe; + + pipe_info = purb->context; + _DBG("%s %p, status %d\n", __func__, purb, purb->status); + if (!pipe_info) { + printk(KERN_ERR KBUILD_MODNAME ": no context!\n"); + return; + } + + cam = pipe_info->cam; + if (!cam) { + printk(KERN_ERR KBUILD_MODNAME ": no context!\n"); + return; + } + + /* if shutting down, do not resubmit, exit immediately */ + if (purb->status == -ESHUTDOWN) { + DBG("%s, err shutdown\n", __func__); + pipe_info->err_count++; + return; + } + + if (pipe_info->state == 0) { + DBG("exiting USB pipe\n"); + return; + } + + if (purb->actual_length > pipe_info->transfer_size) { + dev_err(&cam->udev->dev, "wrong number of bytes\n"); + return; + } + + if (purb->status == 0) + zr364xx_read_video_callback(cam, pipe_info, purb); + else { + pipe_info->err_count++; + DBG("%s: failed URB %d\n", __func__, purb->status); + } + + pipe = usb_rcvbulkpipe(cam->udev, cam->read_endpoint); + + /* reuse urb */ + usb_fill_bulk_urb(pipe_info->stream_urb, cam->udev, + pipe, + pipe_info->transfer_buffer, + pipe_info->transfer_size, + read_pipe_completion, pipe_info); + + if (pipe_info->state != 0) { + purb->status = usb_submit_urb(pipe_info->stream_urb, + GFP_ATOMIC); + + if (purb->status) + dev_err(&cam->udev->dev, + "error submitting urb (error=%i)\n", + purb->status); + } else + DBG("read pipe complete state 0\n"); +} + +static int zr364xx_start_readpipe(struct zr364xx_camera *cam) +{ + int pipe; + int retval; + struct zr364xx_pipeinfo *pipe_info = cam->pipe; + pipe = usb_rcvbulkpipe(cam->udev, cam->read_endpoint); + DBG("%s: start pipe IN x%x\n", __func__, cam->read_endpoint); + + pipe_info->state = 1; + pipe_info->err_count = 0; + pipe_info->stream_urb = usb_alloc_urb(0, GFP_KERNEL); + if (!pipe_info->stream_urb) + return -ENOMEM; + /* transfer buffer allocated in board_init */ + usb_fill_bulk_urb(pipe_info->stream_urb, cam->udev, + pipe, + pipe_info->transfer_buffer, + pipe_info->transfer_size, + read_pipe_completion, pipe_info); + + DBG("submitting URB %p\n", pipe_info->stream_urb); + retval = usb_submit_urb(pipe_info->stream_urb, GFP_KERNEL); + if (retval) { + usb_free_urb(pipe_info->stream_urb); + printk(KERN_ERR KBUILD_MODNAME ": start read pipe failed\n"); + return retval; + } + + return 0; +} + +static void zr364xx_stop_readpipe(struct zr364xx_camera *cam) +{ + struct zr364xx_pipeinfo *pipe_info; + + if (!cam) { + printk(KERN_ERR KBUILD_MODNAME ": invalid device\n"); + return; + } + DBG("stop read pipe\n"); + pipe_info = cam->pipe; + if (pipe_info) { + if (pipe_info->state != 0) + pipe_info->state = 0; + + if (pipe_info->stream_urb) { + /* cancel urb */ + usb_kill_urb(pipe_info->stream_urb); + usb_free_urb(pipe_info->stream_urb); + pipe_info->stream_urb = NULL; + } + } + return; +} + +/* starts acquisition process */ +static int zr364xx_start_acquire(struct zr364xx_camera *cam) +{ + int j; + + DBG("start acquire\n"); + + cam->last_frame = -1; + cam->cur_frame = 0; + for (j = 0; j < FRAMES; j++) { + cam->buffer.frame[j].ulState = ZR364XX_READ_IDLE; + cam->buffer.frame[j].cur_size = 0; + } + cam->b_acquire = 1; + return 0; +} + +static inline int zr364xx_stop_acquire(struct zr364xx_camera *cam) +{ + cam->b_acquire = 0; + return 0; +} + +static int zr364xx_prepare(struct zr364xx_camera *cam) +{ + int res; + int i, j; + + for (i = 0; init[cam->method][i].size != -1; i++) { + res = send_control_msg(cam->udev, 1, init[cam->method][i].value, + 0, init[cam->method][i].bytes, + init[cam->method][i].size); + if (res < 0) { + dev_err(&cam->udev->dev, + "error during open sequence: %d\n", i); + return res; + } + } + + cam->skip = 2; + cam->last_frame = -1; + cam->cur_frame = 0; + cam->frame_count = 0; + for (j = 0; j < FRAMES; j++) { + cam->buffer.frame[j].ulState = ZR364XX_READ_IDLE; + cam->buffer.frame[j].cur_size = 0; + } + v4l2_ctrl_handler_setup(&cam->ctrl_handler); + return 0; +} + +static int zr364xx_vidioc_streamon(struct file *file, void *priv, + enum v4l2_buf_type type) +{ + struct zr364xx_camera *cam = video_drvdata(file); + int res; + + DBG("%s\n", __func__); + + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (cam->owner && cam->owner != priv) + return -EBUSY; + + res = zr364xx_prepare(cam); + if (res) + return res; + res = videobuf_streamon(&cam->vb_vidq); + if (res == 0) { + zr364xx_start_acquire(cam); + cam->owner = file->private_data; + } + return res; +} + +static int zr364xx_vidioc_streamoff(struct file *file, void *priv, + enum v4l2_buf_type type) +{ + struct zr364xx_camera *cam = video_drvdata(file); + + DBG("%s\n", __func__); + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + if (cam->owner && cam->owner != priv) + return -EBUSY; + zr364xx_stop_acquire(cam); + return videobuf_streamoff(&cam->vb_vidq); +} + + +/* open the camera */ +static int zr364xx_open(struct file *file) +{ + struct zr364xx_camera *cam = video_drvdata(file); + int err; + + DBG("%s\n", __func__); + + if (mutex_lock_interruptible(&cam->lock)) + return -ERESTARTSYS; + + err = v4l2_fh_open(file); + if (err) + goto out; + + /* Added some delay here, since opening/closing the camera quickly, + * like Ekiga does during its startup, can crash the webcam + */ + mdelay(100); + err = 0; + +out: + mutex_unlock(&cam->lock); + DBG("%s: %d\n", __func__, err); + return err; +} + +static void zr364xx_board_uninit(struct zr364xx_camera *cam) +{ + unsigned long i; + + zr364xx_stop_readpipe(cam); + + /* release sys buffers */ + for (i = 0; i < FRAMES; i++) { + if (cam->buffer.frame[i].lpvbits) { + DBG("vfree %p\n", cam->buffer.frame[i].lpvbits); + vfree(cam->buffer.frame[i].lpvbits); + } + cam->buffer.frame[i].lpvbits = NULL; + } + + /* release transfer buffer */ + kfree(cam->pipe->transfer_buffer); +} + +static void zr364xx_release(struct v4l2_device *v4l2_dev) +{ + struct zr364xx_camera *cam = + container_of(v4l2_dev, struct zr364xx_camera, v4l2_dev); + + videobuf_mmap_free(&cam->vb_vidq); + v4l2_ctrl_handler_free(&cam->ctrl_handler); + zr364xx_board_uninit(cam); + v4l2_device_unregister(&cam->v4l2_dev); + kfree(cam); +} + +/* release the camera */ +static int zr364xx_close(struct file *file) +{ + struct zr364xx_camera *cam; + struct usb_device *udev; + int i; + + DBG("%s\n", __func__); + cam = video_drvdata(file); + + mutex_lock(&cam->lock); + udev = cam->udev; + + if (file->private_data == cam->owner) { + /* turn off stream */ + if (cam->b_acquire) + zr364xx_stop_acquire(cam); + videobuf_streamoff(&cam->vb_vidq); + + for (i = 0; i < 2; i++) { + send_control_msg(udev, 1, init[cam->method][i].value, + 0, init[cam->method][i].bytes, + init[cam->method][i].size); + } + cam->owner = NULL; + } + + /* Added some delay here, since opening/closing the camera quickly, + * like Ekiga does during its startup, can crash the webcam + */ + mdelay(100); + mutex_unlock(&cam->lock); + return v4l2_fh_release(file); +} + + +static int zr364xx_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct zr364xx_camera *cam = video_drvdata(file); + int ret; + + if (!cam) { + DBG("%s: cam == NULL\n", __func__); + return -ENODEV; + } + DBG("mmap called, vma=%p\n", vma); + + ret = videobuf_mmap_mapper(&cam->vb_vidq, vma); + + DBG("vma start=0x%08lx, size=%ld, ret=%d\n", + (unsigned long)vma->vm_start, + (unsigned long)vma->vm_end - (unsigned long)vma->vm_start, ret); + return ret; +} + +static __poll_t zr364xx_poll(struct file *file, + struct poll_table_struct *wait) +{ + struct zr364xx_camera *cam = video_drvdata(file); + struct videobuf_queue *q = &cam->vb_vidq; + __poll_t res = v4l2_ctrl_poll(file, wait); + + _DBG("%s\n", __func__); + + return res | videobuf_poll_stream(file, q, wait); +} + +static const struct v4l2_ctrl_ops zr364xx_ctrl_ops = { + .s_ctrl = zr364xx_s_ctrl, +}; + +static const struct v4l2_file_operations zr364xx_fops = { + .owner = THIS_MODULE, + .open = zr364xx_open, + .release = zr364xx_close, + .read = zr364xx_read, + .mmap = zr364xx_mmap, + .unlocked_ioctl = video_ioctl2, + .poll = zr364xx_poll, +}; + +static const struct v4l2_ioctl_ops zr364xx_ioctl_ops = { + .vidioc_querycap = zr364xx_vidioc_querycap, + .vidioc_enum_fmt_vid_cap = zr364xx_vidioc_enum_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = zr364xx_vidioc_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = zr364xx_vidioc_s_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = zr364xx_vidioc_g_fmt_vid_cap, + .vidioc_enum_input = zr364xx_vidioc_enum_input, + .vidioc_g_input = zr364xx_vidioc_g_input, + .vidioc_s_input = zr364xx_vidioc_s_input, + .vidioc_streamon = zr364xx_vidioc_streamon, + .vidioc_streamoff = zr364xx_vidioc_streamoff, + .vidioc_reqbufs = zr364xx_vidioc_reqbufs, + .vidioc_querybuf = zr364xx_vidioc_querybuf, + .vidioc_qbuf = zr364xx_vidioc_qbuf, + .vidioc_dqbuf = zr364xx_vidioc_dqbuf, + .vidioc_log_status = v4l2_ctrl_log_status, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static const struct video_device zr364xx_template = { + .name = DRIVER_DESC, + .fops = &zr364xx_fops, + .ioctl_ops = &zr364xx_ioctl_ops, + .release = video_device_release_empty, + .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING, +}; + + + +/*******************/ +/* USB integration */ +/*******************/ +static int zr364xx_board_init(struct zr364xx_camera *cam) +{ + struct zr364xx_pipeinfo *pipe = cam->pipe; + unsigned long i; + int err; + + DBG("board init: %p\n", cam); + memset(pipe, 0, sizeof(*pipe)); + pipe->cam = cam; + pipe->transfer_size = BUFFER_SIZE; + + pipe->transfer_buffer = kzalloc(pipe->transfer_size, + GFP_KERNEL); + if (!pipe->transfer_buffer) { + DBG("out of memory!\n"); + return -ENOMEM; + } + + cam->b_acquire = 0; + cam->frame_count = 0; + + /*** start create system buffers ***/ + for (i = 0; i < FRAMES; i++) { + /* always allocate maximum size for system buffers */ + cam->buffer.frame[i].lpvbits = vmalloc(MAX_FRAME_SIZE); + + DBG("valloc %p, idx %lu, pdata %p\n", + &cam->buffer.frame[i], i, + cam->buffer.frame[i].lpvbits); + if (!cam->buffer.frame[i].lpvbits) { + printk(KERN_INFO KBUILD_MODNAME ": out of memory. Using less frames\n"); + break; + } + } + + if (i == 0) { + printk(KERN_INFO KBUILD_MODNAME ": out of memory. Aborting\n"); + err = -ENOMEM; + goto err_free; + } else + cam->buffer.dwFrames = i; + + /* make sure internal states are set */ + for (i = 0; i < FRAMES; i++) { + cam->buffer.frame[i].ulState = ZR364XX_READ_IDLE; + cam->buffer.frame[i].cur_size = 0; + } + + cam->cur_frame = 0; + cam->last_frame = -1; + /*** end create system buffers ***/ + + /* start read pipe */ + err = zr364xx_start_readpipe(cam); + if (err) + goto err_free_frames; + + DBG(": board initialized\n"); + return 0; + +err_free_frames: + for (i = 0; i < FRAMES; i++) + vfree(cam->buffer.frame[i].lpvbits); +err_free: + kfree(cam->pipe->transfer_buffer); + cam->pipe->transfer_buffer = NULL; + return err; +} + +static int zr364xx_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + struct usb_device *udev = interface_to_usbdev(intf); + struct zr364xx_camera *cam = NULL; + struct usb_host_interface *iface_desc; + struct usb_endpoint_descriptor *endpoint; + struct v4l2_ctrl_handler *hdl; + int err; + int i; + + DBG("probing...\n"); + + dev_info(&intf->dev, DRIVER_DESC " compatible webcam plugged\n"); + dev_info(&intf->dev, "model %04x:%04x detected\n", + le16_to_cpu(udev->descriptor.idVendor), + le16_to_cpu(udev->descriptor.idProduct)); + + cam = kzalloc(sizeof(*cam), GFP_KERNEL); + if (!cam) + return -ENOMEM; + + err = v4l2_device_register(&intf->dev, &cam->v4l2_dev); + if (err < 0) { + dev_err(&udev->dev, "couldn't register v4l2_device\n"); + goto free_cam; + } + hdl = &cam->ctrl_handler; + v4l2_ctrl_handler_init(hdl, 1); + v4l2_ctrl_new_std(hdl, &zr364xx_ctrl_ops, + V4L2_CID_BRIGHTNESS, 0, 127, 1, 64); + if (hdl->error) { + err = hdl->error; + dev_err(&udev->dev, "couldn't register control\n"); + goto free_hdlr_and_unreg_dev; + } + /* save the init method used by this camera */ + cam->method = id->driver_info; + mutex_init(&cam->lock); + cam->vdev = zr364xx_template; + cam->vdev.lock = &cam->lock; + cam->vdev.v4l2_dev = &cam->v4l2_dev; + cam->vdev.ctrl_handler = &cam->ctrl_handler; + video_set_drvdata(&cam->vdev, cam); + + cam->udev = udev; + + switch (mode) { + case 1: + dev_info(&udev->dev, "160x120 mode selected\n"); + cam->width = 160; + cam->height = 120; + break; + case 2: + dev_info(&udev->dev, "640x480 mode selected\n"); + cam->width = 640; + cam->height = 480; + break; + default: + dev_info(&udev->dev, "320x240 mode selected\n"); + cam->width = 320; + cam->height = 240; + break; + } + + m0d1[0] = mode; + m1[2].value = 0xf000 + mode; + m2[1].value = 0xf000 + mode; + + /* special case for METHOD3, the modes are different */ + if (cam->method == METHOD3) { + switch (mode) { + case 1: + m2[1].value = 0xf000 + 4; + break; + case 2: + m2[1].value = 0xf000 + 0; + break; + default: + m2[1].value = 0xf000 + 1; + break; + } + } + + header2[437] = cam->height / 256; + header2[438] = cam->height % 256; + header2[439] = cam->width / 256; + header2[440] = cam->width % 256; + + cam->nb = 0; + + DBG("dev: %p, udev %p interface %p\n", cam, cam->udev, intf); + + /* set up the endpoint information */ + iface_desc = intf->cur_altsetting; + DBG("num endpoints %d\n", iface_desc->desc.bNumEndpoints); + for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) { + endpoint = &iface_desc->endpoint[i].desc; + if (!cam->read_endpoint && usb_endpoint_is_bulk_in(endpoint)) { + /* we found the bulk in endpoint */ + cam->read_endpoint = endpoint->bEndpointAddress; + } + } + + if (!cam->read_endpoint) { + err = -ENOMEM; + dev_err(&intf->dev, "Could not find bulk-in endpoint\n"); + goto free_hdlr_and_unreg_dev; + } + + /* v4l */ + INIT_LIST_HEAD(&cam->vidq.active); + cam->vidq.cam = cam; + + usb_set_intfdata(intf, cam); + + /* load zr364xx board specific */ + err = zr364xx_board_init(cam); + if (err) + goto free_hdlr_and_unreg_dev; + err = v4l2_ctrl_handler_setup(hdl); + if (err) + goto board_uninit; + + spin_lock_init(&cam->slock); + + cam->fmt = formats; + + videobuf_queue_vmalloc_init(&cam->vb_vidq, &zr364xx_video_qops, + NULL, &cam->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_NONE, + sizeof(struct zr364xx_buffer), cam, &cam->lock); + + err = video_register_device(&cam->vdev, VFL_TYPE_VIDEO, -1); + if (err) { + dev_err(&udev->dev, "video_register_device failed\n"); + goto board_uninit; + } + cam->v4l2_dev.release = zr364xx_release; + + dev_info(&udev->dev, DRIVER_DESC " controlling device %s\n", + video_device_node_name(&cam->vdev)); + return 0; + +board_uninit: + zr364xx_board_uninit(cam); +free_hdlr_and_unreg_dev: + v4l2_ctrl_handler_free(hdl); + v4l2_device_unregister(&cam->v4l2_dev); +free_cam: + kfree(cam); + return err; +} + + +static void zr364xx_disconnect(struct usb_interface *intf) +{ + struct zr364xx_camera *cam = usb_get_intfdata(intf); + + mutex_lock(&cam->lock); + usb_set_intfdata(intf, NULL); + dev_info(&intf->dev, DRIVER_DESC " webcam unplugged\n"); + video_unregister_device(&cam->vdev); + v4l2_device_disconnect(&cam->v4l2_dev); + + /* stops the read pipe if it is running */ + if (cam->b_acquire) + zr364xx_stop_acquire(cam); + + zr364xx_stop_readpipe(cam); + mutex_unlock(&cam->lock); + v4l2_device_put(&cam->v4l2_dev); +} + + +#ifdef CONFIG_PM +static int zr364xx_suspend(struct usb_interface *intf, pm_message_t message) +{ + struct zr364xx_camera *cam = usb_get_intfdata(intf); + + cam->was_streaming = cam->b_acquire; + if (!cam->was_streaming) + return 0; + zr364xx_stop_acquire(cam); + zr364xx_stop_readpipe(cam); + return 0; +} + +static int zr364xx_resume(struct usb_interface *intf) +{ + struct zr364xx_camera *cam = usb_get_intfdata(intf); + int res; + + if (!cam->was_streaming) + return 0; + + res = zr364xx_start_readpipe(cam); + if (res) + return res; + + res = zr364xx_prepare(cam); + if (res) + goto err_prepare; + + zr364xx_start_acquire(cam); + return 0; + +err_prepare: + zr364xx_stop_readpipe(cam); + return res; +} +#endif + +/**********************/ +/* Module integration */ +/**********************/ + +static struct usb_driver zr364xx_driver = { + .name = "zr364xx", + .probe = zr364xx_probe, + .disconnect = zr364xx_disconnect, +#ifdef CONFIG_PM + .suspend = zr364xx_suspend, + .resume = zr364xx_resume, + .reset_resume = zr364xx_resume, +#endif + .id_table = device_table +}; + +module_usb_driver(zr364xx_driver); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRIVER_VERSION); diff --git a/drivers/staging/media/imx/Kconfig b/drivers/staging/media/imx/Kconfig new file mode 100644 index 000000000..21fd79515 --- /dev/null +++ b/drivers/staging/media/imx/Kconfig @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0 +config VIDEO_IMX_MEDIA + tristate "i.MX5/6 V4L2 media core driver" + depends on ARCH_MXC || COMPILE_TEST + depends on HAS_DMA + depends on VIDEO_DEV + depends on VIDEO_DEV + select MEDIA_CONTROLLER + select V4L2_FWNODE + select V4L2_MEM2MEM_DEV + select VIDEOBUF2_DMA_CONTIG + select VIDEO_V4L2_SUBDEV_API + help + Say yes here to enable support for video4linux media controller + driver for the i.MX5/6 SOC. + +if VIDEO_IMX_MEDIA +menu "i.MX5/6/7/8 Media Sub devices" + +config VIDEO_IMX_CSI + tristate "i.MX5/6 Camera Sensor Interface driver" + depends on IMX_IPUV3_CORE + default y + help + A video4linux camera sensor interface driver for i.MX5/6. +endmenu +endif + +config VIDEO_IMX8MQ_MIPI_CSI2 + tristate "NXP i.MX8MQ MIPI CSI-2 receiver" + depends on ARCH_MXC || COMPILE_TEST + depends on VIDEO_DEV + select MEDIA_CONTROLLER + select V4L2_FWNODE + select VIDEO_V4L2_SUBDEV_API + help + V4L2 driver for the MIPI CSI-2 receiver found in the i.MX8MQ SoC. diff --git a/drivers/staging/media/imx/Makefile b/drivers/staging/media/imx/Makefile new file mode 100644 index 000000000..906a422aa --- /dev/null +++ b/drivers/staging/media/imx/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +imx-media-common-objs := imx-media-capture.o imx-media-dev-common.o \ + imx-media-of.o imx-media-utils.o + +imx6-media-objs := imx-media-dev.o imx-media-internal-sd.o \ + imx-ic-common.o imx-ic-prp.o imx-ic-prpencvf.o imx-media-vdic.o \ + imx-media-csc-scaler.o + +imx6-media-csi-objs := imx-media-csi.o imx-media-fim.o + +obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx-media-common.o + +obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-media.o +obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-media-csi.o +obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-mipi-csi2.o + +obj-$(CONFIG_VIDEO_IMX8MQ_MIPI_CSI2) += imx8mq-mipi-csi2.o diff --git a/drivers/staging/media/imx/TODO b/drivers/staging/media/imx/TODO new file mode 100644 index 000000000..11c9e10d3 --- /dev/null +++ b/drivers/staging/media/imx/TODO @@ -0,0 +1,13 @@ + +- The Frame Interval Monitor could be exported to v4l2-core for + general use. + +- This media driver supports inheriting V4L2 controls to the + video capture devices, from the subdevices in the capture device's + pipeline. The controls for each capture device are updated in the + link_notify callback when the pipeline is modified. This feature should be + removed, userspace should use the subdev-based userspace API instead. + +- Similarly to the legacy control handling, legacy format handling where + formats on the video nodes are influenced by the active format of the + connected subdev should be removed. diff --git a/drivers/staging/media/imx/imx-ic-common.c b/drivers/staging/media/imx/imx-ic-common.c new file mode 100644 index 000000000..6df1ffb53 --- /dev/null +++ b/drivers/staging/media/imx/imx-ic-common.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * V4L2 Image Converter Subdev for Freescale i.MX5/6 SOC + * + * Copyright (c) 2014-2016 Mentor Graphics Inc. + */ +#include +#include +#include "imx-media.h" +#include "imx-ic.h" + +#define IC_TASK_PRP IC_NUM_TASKS +#define IC_NUM_OPS (IC_NUM_TASKS + 1) + +static struct imx_ic_ops *ic_ops[IC_NUM_OPS] = { + [IC_TASK_PRP] = &imx_ic_prp_ops, + [IC_TASK_ENCODER] = &imx_ic_prpencvf_ops, + [IC_TASK_VIEWFINDER] = &imx_ic_prpencvf_ops, +}; + +struct v4l2_subdev *imx_media_ic_register(struct v4l2_device *v4l2_dev, + struct device *ipu_dev, + struct ipu_soc *ipu, + u32 grp_id) +{ + struct imx_ic_priv *priv; + int ret; + + priv = devm_kzalloc(ipu_dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return ERR_PTR(-ENOMEM); + + priv->ipu_dev = ipu_dev; + priv->ipu = ipu; + + /* get our IC task id */ + switch (grp_id) { + case IMX_MEDIA_GRP_ID_IPU_IC_PRP: + priv->task_id = IC_TASK_PRP; + break; + case IMX_MEDIA_GRP_ID_IPU_IC_PRPENC: + priv->task_id = IC_TASK_ENCODER; + break; + case IMX_MEDIA_GRP_ID_IPU_IC_PRPVF: + priv->task_id = IC_TASK_VIEWFINDER; + break; + default: + return ERR_PTR(-EINVAL); + } + + v4l2_subdev_init(&priv->sd, ic_ops[priv->task_id]->subdev_ops); + v4l2_set_subdevdata(&priv->sd, priv); + priv->sd.internal_ops = ic_ops[priv->task_id]->internal_ops; + priv->sd.entity.ops = ic_ops[priv->task_id]->entity_ops; + priv->sd.entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER; + priv->sd.owner = ipu_dev->driver->owner; + priv->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; + priv->sd.grp_id = grp_id; + imx_media_grp_id_to_sd_name(priv->sd.name, sizeof(priv->sd.name), + priv->sd.grp_id, ipu_get_num(ipu)); + + ret = ic_ops[priv->task_id]->init(priv); + if (ret) + return ERR_PTR(ret); + + ret = v4l2_device_register_subdev(v4l2_dev, &priv->sd); + if (ret) { + ic_ops[priv->task_id]->remove(priv); + return ERR_PTR(ret); + } + + return &priv->sd; +} + +int imx_media_ic_unregister(struct v4l2_subdev *sd) +{ + struct imx_ic_priv *priv = container_of(sd, struct imx_ic_priv, sd); + + v4l2_info(sd, "Removing\n"); + + ic_ops[priv->task_id]->remove(priv); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + + return 0; +} diff --git a/drivers/staging/media/imx/imx-ic-prp.c b/drivers/staging/media/imx/imx-ic-prp.c new file mode 100644 index 000000000..ac5fb3320 --- /dev/null +++ b/drivers/staging/media/imx/imx-ic-prp.c @@ -0,0 +1,514 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * V4L2 Capture IC Preprocess Subdev for Freescale i.MX5/6 SOC + * + * This subdevice handles capture of video frames from the CSI or VDIC, + * which are routed directly to the Image Converter preprocess tasks, + * for resizing, colorspace conversion, and rotation. + * + * Copyright (c) 2012-2017 Mentor Graphics Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "imx-media.h" +#include "imx-ic.h" + +/* + * Min/Max supported width and heights. + */ +#define MIN_W 32 +#define MIN_H 32 +#define MAX_W 4096 +#define MAX_H 4096 +#define W_ALIGN 4 /* multiple of 16 pixels */ +#define H_ALIGN 1 /* multiple of 2 lines */ +#define S_ALIGN 1 /* multiple of 2 */ + +struct prp_priv { + struct imx_ic_priv *ic_priv; + struct media_pad pad[PRP_NUM_PADS]; + + /* lock to protect all members below */ + struct mutex lock; + + struct v4l2_subdev *src_sd; + struct v4l2_subdev *sink_sd_prpenc; + struct v4l2_subdev *sink_sd_prpvf; + + /* the CSI id at link validate */ + int csi_id; + + struct v4l2_mbus_framefmt format_mbus; + struct v4l2_fract frame_interval; + + int stream_count; +}; + +static inline struct prp_priv *sd_to_priv(struct v4l2_subdev *sd) +{ + struct imx_ic_priv *ic_priv = v4l2_get_subdevdata(sd); + + return ic_priv->task_priv; +} + +static int prp_start(struct prp_priv *priv) +{ + struct imx_ic_priv *ic_priv = priv->ic_priv; + bool src_is_vdic; + + /* set IC to receive from CSI or VDI depending on source */ + src_is_vdic = !!(priv->src_sd->grp_id & IMX_MEDIA_GRP_ID_IPU_VDIC); + + ipu_set_ic_src_mux(ic_priv->ipu, priv->csi_id, src_is_vdic); + + return 0; +} + +static void prp_stop(struct prp_priv *priv) +{ +} + +static struct v4l2_mbus_framefmt * +__prp_get_fmt(struct prp_priv *priv, struct v4l2_subdev_state *sd_state, + unsigned int pad, enum v4l2_subdev_format_whence which) +{ + struct imx_ic_priv *ic_priv = priv->ic_priv; + + if (which == V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_get_try_format(&ic_priv->sd, sd_state, pad); + else + return &priv->format_mbus; +} + +/* + * V4L2 subdev operations. + */ + +static int prp_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct prp_priv *priv = sd_to_priv(sd); + struct v4l2_mbus_framefmt *infmt; + int ret = 0; + + mutex_lock(&priv->lock); + + switch (code->pad) { + case PRP_SINK_PAD: + ret = imx_media_enum_ipu_formats(&code->code, code->index, + PIXFMT_SEL_YUV_RGB); + break; + case PRP_SRC_PAD_PRPENC: + case PRP_SRC_PAD_PRPVF: + if (code->index != 0) { + ret = -EINVAL; + goto out; + } + infmt = __prp_get_fmt(priv, sd_state, PRP_SINK_PAD, + code->which); + code->code = infmt->code; + break; + default: + ret = -EINVAL; + } +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *sdformat) +{ + struct prp_priv *priv = sd_to_priv(sd); + struct v4l2_mbus_framefmt *fmt; + int ret = 0; + + if (sdformat->pad >= PRP_NUM_PADS) + return -EINVAL; + + mutex_lock(&priv->lock); + + fmt = __prp_get_fmt(priv, sd_state, sdformat->pad, sdformat->which); + if (!fmt) { + ret = -EINVAL; + goto out; + } + + sdformat->format = *fmt; +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *sdformat) +{ + struct prp_priv *priv = sd_to_priv(sd); + struct v4l2_mbus_framefmt *fmt, *infmt; + const struct imx_media_pixfmt *cc; + int ret = 0; + u32 code; + + if (sdformat->pad >= PRP_NUM_PADS) + return -EINVAL; + + mutex_lock(&priv->lock); + + if (priv->stream_count > 0) { + ret = -EBUSY; + goto out; + } + + infmt = __prp_get_fmt(priv, sd_state, PRP_SINK_PAD, sdformat->which); + + switch (sdformat->pad) { + case PRP_SINK_PAD: + v4l_bound_align_image(&sdformat->format.width, MIN_W, MAX_W, + W_ALIGN, &sdformat->format.height, + MIN_H, MAX_H, H_ALIGN, S_ALIGN); + + cc = imx_media_find_ipu_format(sdformat->format.code, + PIXFMT_SEL_YUV_RGB); + if (!cc) { + imx_media_enum_ipu_formats(&code, 0, + PIXFMT_SEL_YUV_RGB); + cc = imx_media_find_ipu_format(code, + PIXFMT_SEL_YUV_RGB); + sdformat->format.code = cc->codes[0]; + } + + if (sdformat->format.field == V4L2_FIELD_ANY) + sdformat->format.field = V4L2_FIELD_NONE; + break; + case PRP_SRC_PAD_PRPENC: + case PRP_SRC_PAD_PRPVF: + /* Output pads mirror input pad */ + sdformat->format = *infmt; + break; + } + + imx_media_try_colorimetry(&sdformat->format, true); + + fmt = __prp_get_fmt(priv, sd_state, sdformat->pad, sdformat->which); + *fmt = sdformat->format; +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); + struct imx_ic_priv *ic_priv = v4l2_get_subdevdata(sd); + struct prp_priv *priv = ic_priv->task_priv; + struct v4l2_subdev *remote_sd; + int ret = 0; + + dev_dbg(ic_priv->ipu_dev, "%s: link setup %s -> %s", + ic_priv->sd.name, remote->entity->name, local->entity->name); + + remote_sd = media_entity_to_v4l2_subdev(remote->entity); + + mutex_lock(&priv->lock); + + if (local->flags & MEDIA_PAD_FL_SINK) { + if (flags & MEDIA_LNK_FL_ENABLED) { + if (priv->src_sd) { + ret = -EBUSY; + goto out; + } + if (priv->sink_sd_prpenc && + (remote_sd->grp_id & IMX_MEDIA_GRP_ID_IPU_VDIC)) { + ret = -EINVAL; + goto out; + } + priv->src_sd = remote_sd; + } else { + priv->src_sd = NULL; + } + + goto out; + } + + /* this is a source pad */ + if (flags & MEDIA_LNK_FL_ENABLED) { + switch (local->index) { + case PRP_SRC_PAD_PRPENC: + if (priv->sink_sd_prpenc) { + ret = -EBUSY; + goto out; + } + if (priv->src_sd && (priv->src_sd->grp_id & + IMX_MEDIA_GRP_ID_IPU_VDIC)) { + ret = -EINVAL; + goto out; + } + priv->sink_sd_prpenc = remote_sd; + break; + case PRP_SRC_PAD_PRPVF: + if (priv->sink_sd_prpvf) { + ret = -EBUSY; + goto out; + } + priv->sink_sd_prpvf = remote_sd; + break; + default: + ret = -EINVAL; + } + } else { + switch (local->index) { + case PRP_SRC_PAD_PRPENC: + priv->sink_sd_prpenc = NULL; + break; + case PRP_SRC_PAD_PRPVF: + priv->sink_sd_prpvf = NULL; + break; + default: + ret = -EINVAL; + } + } + +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_link_validate(struct v4l2_subdev *sd, + struct media_link *link, + struct v4l2_subdev_format *source_fmt, + struct v4l2_subdev_format *sink_fmt) +{ + struct imx_ic_priv *ic_priv = v4l2_get_subdevdata(sd); + struct prp_priv *priv = ic_priv->task_priv; + struct v4l2_subdev *csi; + int ret; + + ret = v4l2_subdev_link_validate_default(sd, link, + source_fmt, sink_fmt); + if (ret) + return ret; + + csi = imx_media_pipeline_subdev(&ic_priv->sd.entity, + IMX_MEDIA_GRP_ID_IPU_CSI, true); + if (IS_ERR(csi)) + csi = NULL; + + mutex_lock(&priv->lock); + + if (priv->src_sd->grp_id & IMX_MEDIA_GRP_ID_IPU_VDIC) { + /* + * the ->PRPENC link cannot be enabled if the source + * is the VDIC + */ + if (priv->sink_sd_prpenc) { + ret = -EINVAL; + goto out; + } + } else { + /* the source is a CSI */ + if (!csi) { + ret = -EINVAL; + goto out; + } + } + + if (csi) { + switch (csi->grp_id) { + case IMX_MEDIA_GRP_ID_IPU_CSI0: + priv->csi_id = 0; + break; + case IMX_MEDIA_GRP_ID_IPU_CSI1: + priv->csi_id = 1; + break; + default: + ret = -EINVAL; + } + } else { + priv->csi_id = 0; + } + +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct imx_ic_priv *ic_priv = v4l2_get_subdevdata(sd); + struct prp_priv *priv = ic_priv->task_priv; + int ret = 0; + + mutex_lock(&priv->lock); + + if (!priv->src_sd || (!priv->sink_sd_prpenc && !priv->sink_sd_prpvf)) { + ret = -EPIPE; + goto out; + } + + /* + * enable/disable streaming only if stream_count is + * going from 0 to 1 / 1 to 0. + */ + if (priv->stream_count != !enable) + goto update_count; + + dev_dbg(ic_priv->ipu_dev, "%s: stream %s\n", sd->name, + enable ? "ON" : "OFF"); + + if (enable) + ret = prp_start(priv); + else + prp_stop(priv); + if (ret) + goto out; + + /* start/stop upstream */ + ret = v4l2_subdev_call(priv->src_sd, video, s_stream, enable); + ret = (ret && ret != -ENOIOCTLCMD) ? ret : 0; + if (ret) { + if (enable) + prp_stop(priv); + goto out; + } + +update_count: + priv->stream_count += enable ? 1 : -1; + if (priv->stream_count < 0) + priv->stream_count = 0; +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct prp_priv *priv = sd_to_priv(sd); + + if (fi->pad >= PRP_NUM_PADS) + return -EINVAL; + + mutex_lock(&priv->lock); + fi->interval = priv->frame_interval; + mutex_unlock(&priv->lock); + + return 0; +} + +static int prp_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct prp_priv *priv = sd_to_priv(sd); + + if (fi->pad >= PRP_NUM_PADS) + return -EINVAL; + + mutex_lock(&priv->lock); + + /* No limits on valid frame intervals */ + if (fi->interval.numerator == 0 || fi->interval.denominator == 0) + fi->interval = priv->frame_interval; + else + priv->frame_interval = fi->interval; + + mutex_unlock(&priv->lock); + + return 0; +} + +static int prp_registered(struct v4l2_subdev *sd) +{ + struct prp_priv *priv = sd_to_priv(sd); + u32 code; + + /* init default frame interval */ + priv->frame_interval.numerator = 1; + priv->frame_interval.denominator = 30; + + /* set a default mbus format */ + imx_media_enum_ipu_formats(&code, 0, PIXFMT_SEL_YUV); + + return imx_media_init_mbus_fmt(&priv->format_mbus, + IMX_MEDIA_DEF_PIX_WIDTH, + IMX_MEDIA_DEF_PIX_HEIGHT, code, + V4L2_FIELD_NONE, NULL); +} + +static const struct v4l2_subdev_pad_ops prp_pad_ops = { + .init_cfg = imx_media_init_cfg, + .enum_mbus_code = prp_enum_mbus_code, + .get_fmt = prp_get_fmt, + .set_fmt = prp_set_fmt, + .link_validate = prp_link_validate, +}; + +static const struct v4l2_subdev_video_ops prp_video_ops = { + .g_frame_interval = prp_g_frame_interval, + .s_frame_interval = prp_s_frame_interval, + .s_stream = prp_s_stream, +}; + +static const struct media_entity_operations prp_entity_ops = { + .link_setup = prp_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_subdev_ops prp_subdev_ops = { + .video = &prp_video_ops, + .pad = &prp_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops prp_internal_ops = { + .registered = prp_registered, +}; + +static int prp_init(struct imx_ic_priv *ic_priv) +{ + struct prp_priv *priv; + int i; + + priv = devm_kzalloc(ic_priv->ipu_dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->lock); + ic_priv->task_priv = priv; + priv->ic_priv = ic_priv; + + for (i = 0; i < PRP_NUM_PADS; i++) + priv->pad[i].flags = (i == PRP_SINK_PAD) ? + MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE; + + return media_entity_pads_init(&ic_priv->sd.entity, PRP_NUM_PADS, + priv->pad); +} + +static void prp_remove(struct imx_ic_priv *ic_priv) +{ + struct prp_priv *priv = ic_priv->task_priv; + + mutex_destroy(&priv->lock); +} + +struct imx_ic_ops imx_ic_prp_ops = { + .subdev_ops = &prp_subdev_ops, + .internal_ops = &prp_internal_ops, + .entity_ops = &prp_entity_ops, + .init = prp_init, + .remove = prp_remove, +}; diff --git a/drivers/staging/media/imx/imx-ic-prpencvf.c b/drivers/staging/media/imx/imx-ic-prpencvf.c new file mode 100644 index 000000000..9b81cfbcd --- /dev/null +++ b/drivers/staging/media/imx/imx-ic-prpencvf.c @@ -0,0 +1,1372 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * V4L2 Capture IC Preprocess Subdev for Freescale i.MX5/6 SOC + * + * This subdevice handles capture of video frames from the CSI or VDIC, + * which are routed directly to the Image Converter preprocess tasks, + * for resizing, colorspace conversion, and rotation. + * + * Copyright (c) 2012-2017 Mentor Graphics Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "imx-media.h" +#include "imx-ic.h" + +/* + * Min/Max supported width and heights. + * + * We allow planar output, so we have to align width at the source pad + * by 16 pixels to meet IDMAC alignment requirements for possible planar + * output. + * + * TODO: move this into pad format negotiation, if capture device + * has not requested a planar format, we should allow 8 pixel + * alignment at the source pad. + */ +#define MIN_W_SINK 32 +#define MIN_H_SINK 32 +#define MAX_W_SINK 4096 +#define MAX_H_SINK 4096 +#define W_ALIGN_SINK 3 /* multiple of 8 pixels */ +#define H_ALIGN_SINK 1 /* multiple of 2 lines */ + +#define MAX_W_SRC 1024 +#define MAX_H_SRC 1024 +#define W_ALIGN_SRC 1 /* multiple of 2 pixels */ +#define H_ALIGN_SRC 1 /* multiple of 2 lines */ + +#define S_ALIGN 1 /* multiple of 2 */ + +struct prp_priv { + struct imx_ic_priv *ic_priv; + struct media_pad pad[PRPENCVF_NUM_PADS]; + /* the video device at output pad */ + struct imx_media_video_dev *vdev; + + /* lock to protect all members below */ + struct mutex lock; + + /* IPU units we require */ + struct ipu_ic *ic; + struct ipuv3_channel *out_ch; + struct ipuv3_channel *rot_in_ch; + struct ipuv3_channel *rot_out_ch; + + /* active vb2 buffers to send to video dev sink */ + struct imx_media_buffer *active_vb2_buf[2]; + struct imx_media_dma_buf underrun_buf; + + int ipu_buf_num; /* ipu double buffer index: 0-1 */ + + /* the sink for the captured frames */ + struct media_entity *sink; + /* the source subdev */ + struct v4l2_subdev *src_sd; + + struct v4l2_mbus_framefmt format_mbus[PRPENCVF_NUM_PADS]; + const struct imx_media_pixfmt *cc[PRPENCVF_NUM_PADS]; + struct v4l2_fract frame_interval; + + struct imx_media_dma_buf rot_buf[2]; + + /* controls */ + struct v4l2_ctrl_handler ctrl_hdlr; + int rotation; /* degrees */ + bool hflip; + bool vflip; + + /* derived from rotation, hflip, vflip controls */ + enum ipu_rotate_mode rot_mode; + + spinlock_t irqlock; /* protect eof_irq handler */ + + struct timer_list eof_timeout_timer; + int eof_irq; + int nfb4eof_irq; + + int stream_count; + u32 frame_sequence; /* frame sequence counter */ + bool last_eof; /* waiting for last EOF at stream off */ + bool nfb4eof; /* NFB4EOF encountered during streaming */ + bool interweave_swap; /* swap top/bottom lines when interweaving */ + struct completion last_eof_comp; +}; + +static const struct prp_channels { + u32 out_ch; + u32 rot_in_ch; + u32 rot_out_ch; +} prp_channel[] = { + [IC_TASK_ENCODER] = { + .out_ch = IPUV3_CHANNEL_IC_PRP_ENC_MEM, + .rot_in_ch = IPUV3_CHANNEL_MEM_ROT_ENC, + .rot_out_ch = IPUV3_CHANNEL_ROT_ENC_MEM, + }, + [IC_TASK_VIEWFINDER] = { + .out_ch = IPUV3_CHANNEL_IC_PRP_VF_MEM, + .rot_in_ch = IPUV3_CHANNEL_MEM_ROT_VF, + .rot_out_ch = IPUV3_CHANNEL_ROT_VF_MEM, + }, +}; + +static inline struct prp_priv *sd_to_priv(struct v4l2_subdev *sd) +{ + struct imx_ic_priv *ic_priv = v4l2_get_subdevdata(sd); + + return ic_priv->task_priv; +} + +static void prp_put_ipu_resources(struct prp_priv *priv) +{ + if (priv->ic) + ipu_ic_put(priv->ic); + priv->ic = NULL; + + if (priv->out_ch) + ipu_idmac_put(priv->out_ch); + priv->out_ch = NULL; + + if (priv->rot_in_ch) + ipu_idmac_put(priv->rot_in_ch); + priv->rot_in_ch = NULL; + + if (priv->rot_out_ch) + ipu_idmac_put(priv->rot_out_ch); + priv->rot_out_ch = NULL; +} + +static int prp_get_ipu_resources(struct prp_priv *priv) +{ + struct imx_ic_priv *ic_priv = priv->ic_priv; + struct ipu_ic *ic; + struct ipuv3_channel *out_ch, *rot_in_ch, *rot_out_ch; + int ret, task = ic_priv->task_id; + + ic = ipu_ic_get(ic_priv->ipu, task); + if (IS_ERR(ic)) { + v4l2_err(&ic_priv->sd, "failed to get IC\n"); + ret = PTR_ERR(ic); + goto out; + } + priv->ic = ic; + + out_ch = ipu_idmac_get(ic_priv->ipu, prp_channel[task].out_ch); + if (IS_ERR(out_ch)) { + v4l2_err(&ic_priv->sd, "could not get IDMAC channel %u\n", + prp_channel[task].out_ch); + ret = PTR_ERR(out_ch); + goto out; + } + priv->out_ch = out_ch; + + rot_in_ch = ipu_idmac_get(ic_priv->ipu, prp_channel[task].rot_in_ch); + if (IS_ERR(rot_in_ch)) { + v4l2_err(&ic_priv->sd, "could not get IDMAC channel %u\n", + prp_channel[task].rot_in_ch); + ret = PTR_ERR(rot_in_ch); + goto out; + } + priv->rot_in_ch = rot_in_ch; + + rot_out_ch = ipu_idmac_get(ic_priv->ipu, prp_channel[task].rot_out_ch); + if (IS_ERR(rot_out_ch)) { + v4l2_err(&ic_priv->sd, "could not get IDMAC channel %u\n", + prp_channel[task].rot_out_ch); + ret = PTR_ERR(rot_out_ch); + goto out; + } + priv->rot_out_ch = rot_out_ch; + + return 0; +out: + prp_put_ipu_resources(priv); + return ret; +} + +static void prp_vb2_buf_done(struct prp_priv *priv, struct ipuv3_channel *ch) +{ + struct imx_media_video_dev *vdev = priv->vdev; + struct imx_media_buffer *done, *next; + struct vb2_buffer *vb; + dma_addr_t phys; + + done = priv->active_vb2_buf[priv->ipu_buf_num]; + if (done) { + done->vbuf.field = vdev->fmt.field; + done->vbuf.sequence = priv->frame_sequence; + vb = &done->vbuf.vb2_buf; + vb->timestamp = ktime_get_ns(); + vb2_buffer_done(vb, priv->nfb4eof ? + VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); + } + + priv->frame_sequence++; + priv->nfb4eof = false; + + /* get next queued buffer */ + next = imx_media_capture_device_next_buf(vdev); + if (next) { + phys = vb2_dma_contig_plane_dma_addr(&next->vbuf.vb2_buf, 0); + priv->active_vb2_buf[priv->ipu_buf_num] = next; + } else { + phys = priv->underrun_buf.phys; + priv->active_vb2_buf[priv->ipu_buf_num] = NULL; + } + + if (ipu_idmac_buffer_is_ready(ch, priv->ipu_buf_num)) + ipu_idmac_clear_buffer(ch, priv->ipu_buf_num); + + if (priv->interweave_swap && ch == priv->out_ch) + phys += vdev->fmt.bytesperline; + + ipu_cpmem_set_buffer(ch, priv->ipu_buf_num, phys); +} + +static irqreturn_t prp_eof_interrupt(int irq, void *dev_id) +{ + struct prp_priv *priv = dev_id; + struct ipuv3_channel *channel; + + spin_lock(&priv->irqlock); + + if (priv->last_eof) { + complete(&priv->last_eof_comp); + priv->last_eof = false; + goto unlock; + } + + channel = (ipu_rot_mode_is_irt(priv->rot_mode)) ? + priv->rot_out_ch : priv->out_ch; + + prp_vb2_buf_done(priv, channel); + + /* select new IPU buf */ + ipu_idmac_select_buffer(channel, priv->ipu_buf_num); + /* toggle IPU double-buffer index */ + priv->ipu_buf_num ^= 1; + + /* bump the EOF timeout timer */ + mod_timer(&priv->eof_timeout_timer, + jiffies + msecs_to_jiffies(IMX_MEDIA_EOF_TIMEOUT)); + +unlock: + spin_unlock(&priv->irqlock); + return IRQ_HANDLED; +} + +static irqreturn_t prp_nfb4eof_interrupt(int irq, void *dev_id) +{ + struct prp_priv *priv = dev_id; + struct imx_ic_priv *ic_priv = priv->ic_priv; + + spin_lock(&priv->irqlock); + + /* + * this is not an unrecoverable error, just mark + * the next captured frame with vb2 error flag. + */ + priv->nfb4eof = true; + + v4l2_err(&ic_priv->sd, "NFB4EOF\n"); + + spin_unlock(&priv->irqlock); + + return IRQ_HANDLED; +} + +/* + * EOF timeout timer function. + */ +/* + * EOF timeout timer function. This is an unrecoverable condition + * without a stream restart. + */ +static void prp_eof_timeout(struct timer_list *t) +{ + struct prp_priv *priv = from_timer(priv, t, eof_timeout_timer); + struct imx_media_video_dev *vdev = priv->vdev; + struct imx_ic_priv *ic_priv = priv->ic_priv; + + v4l2_err(&ic_priv->sd, "EOF timeout\n"); + + /* signal a fatal error to capture device */ + imx_media_capture_device_error(vdev); +} + +static void prp_setup_vb2_buf(struct prp_priv *priv, dma_addr_t *phys) +{ + struct imx_media_video_dev *vdev = priv->vdev; + struct imx_media_buffer *buf; + int i; + + for (i = 0; i < 2; i++) { + buf = imx_media_capture_device_next_buf(vdev); + if (buf) { + priv->active_vb2_buf[i] = buf; + phys[i] = vb2_dma_contig_plane_dma_addr( + &buf->vbuf.vb2_buf, 0); + } else { + priv->active_vb2_buf[i] = NULL; + phys[i] = priv->underrun_buf.phys; + } + } +} + +static void prp_unsetup_vb2_buf(struct prp_priv *priv, + enum vb2_buffer_state return_status) +{ + struct imx_media_buffer *buf; + int i; + + /* return any remaining active frames with return_status */ + for (i = 0; i < 2; i++) { + buf = priv->active_vb2_buf[i]; + if (buf) { + struct vb2_buffer *vb = &buf->vbuf.vb2_buf; + + vb->timestamp = ktime_get_ns(); + vb2_buffer_done(vb, return_status); + } + } +} + +static int prp_setup_channel(struct prp_priv *priv, + struct ipuv3_channel *channel, + enum ipu_rotate_mode rot_mode, + dma_addr_t addr0, dma_addr_t addr1, + bool rot_swap_width_height) +{ + struct imx_media_video_dev *vdev = priv->vdev; + const struct imx_media_pixfmt *outcc; + struct v4l2_mbus_framefmt *outfmt; + unsigned int burst_size; + struct ipu_image image; + bool interweave; + int ret; + + outfmt = &priv->format_mbus[PRPENCVF_SRC_PAD]; + outcc = vdev->cc; + + ipu_cpmem_zero(channel); + + memset(&image, 0, sizeof(image)); + image.pix = vdev->fmt; + image.rect = vdev->compose; + + /* + * If the field type at capture interface is interlaced, and + * the output IDMAC pad is sequential, enable interweave at + * the IDMAC output channel. + */ + interweave = V4L2_FIELD_IS_INTERLACED(image.pix.field) && + V4L2_FIELD_IS_SEQUENTIAL(outfmt->field); + priv->interweave_swap = interweave && + image.pix.field == V4L2_FIELD_INTERLACED_BT; + + if (rot_swap_width_height) { + swap(image.pix.width, image.pix.height); + swap(image.rect.width, image.rect.height); + /* recalc stride using swapped width */ + image.pix.bytesperline = outcc->planar ? + image.pix.width : + (image.pix.width * outcc->bpp) >> 3; + } + + if (priv->interweave_swap && channel == priv->out_ch) { + /* start interweave scan at 1st top line (2nd line) */ + image.rect.top = 1; + } + + image.phys0 = addr0; + image.phys1 = addr1; + + /* + * Skip writing U and V components to odd rows in the output + * channels for planar 4:2:0 (but not when enabling IDMAC + * interweaving, they are incompatible). + */ + if ((channel == priv->out_ch && !interweave) || + channel == priv->rot_out_ch) { + switch (image.pix.pixelformat) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YVU420: + case V4L2_PIX_FMT_NV12: + ipu_cpmem_skip_odd_chroma_rows(channel); + break; + } + } + + ret = ipu_cpmem_set_image(channel, &image); + if (ret) + return ret; + + if (channel == priv->rot_in_ch || + channel == priv->rot_out_ch) { + burst_size = 8; + ipu_cpmem_set_block_mode(channel); + } else { + burst_size = (image.pix.width & 0xf) ? 8 : 16; + } + + ipu_cpmem_set_burstsize(channel, burst_size); + + if (rot_mode) + ipu_cpmem_set_rotation(channel, rot_mode); + + if (interweave && channel == priv->out_ch) + ipu_cpmem_interlaced_scan(channel, + priv->interweave_swap ? + -image.pix.bytesperline : + image.pix.bytesperline, + image.pix.pixelformat); + + ret = ipu_ic_task_idma_init(priv->ic, channel, + image.pix.width, image.pix.height, + burst_size, rot_mode); + if (ret) + return ret; + + ipu_cpmem_set_axi_id(channel, 1); + + ipu_idmac_set_double_buffer(channel, true); + + return 0; +} + +static int prp_setup_rotation(struct prp_priv *priv) +{ + struct imx_media_video_dev *vdev = priv->vdev; + struct imx_ic_priv *ic_priv = priv->ic_priv; + const struct imx_media_pixfmt *outcc, *incc; + struct v4l2_mbus_framefmt *infmt; + struct v4l2_pix_format *outfmt; + struct ipu_ic_csc csc; + dma_addr_t phys[2]; + int ret; + + infmt = &priv->format_mbus[PRPENCVF_SINK_PAD]; + outfmt = &vdev->fmt; + incc = priv->cc[PRPENCVF_SINK_PAD]; + outcc = vdev->cc; + + ret = ipu_ic_calc_csc(&csc, + infmt->ycbcr_enc, infmt->quantization, + incc->cs, + outfmt->ycbcr_enc, outfmt->quantization, + outcc->cs); + if (ret) { + v4l2_err(&ic_priv->sd, "ipu_ic_calc_csc failed, %d\n", + ret); + return ret; + } + + ret = imx_media_alloc_dma_buf(ic_priv->ipu_dev, &priv->rot_buf[0], + outfmt->sizeimage); + if (ret) { + v4l2_err(&ic_priv->sd, "failed to alloc rot_buf[0], %d\n", ret); + return ret; + } + ret = imx_media_alloc_dma_buf(ic_priv->ipu_dev, &priv->rot_buf[1], + outfmt->sizeimage); + if (ret) { + v4l2_err(&ic_priv->sd, "failed to alloc rot_buf[1], %d\n", ret); + goto free_rot0; + } + + ret = ipu_ic_task_init(priv->ic, &csc, + infmt->width, infmt->height, + outfmt->height, outfmt->width); + if (ret) { + v4l2_err(&ic_priv->sd, "ipu_ic_task_init failed, %d\n", ret); + goto free_rot1; + } + + /* init the IC-PRP-->MEM IDMAC channel */ + ret = prp_setup_channel(priv, priv->out_ch, IPU_ROTATE_NONE, + priv->rot_buf[0].phys, priv->rot_buf[1].phys, + true); + if (ret) { + v4l2_err(&ic_priv->sd, + "prp_setup_channel(out_ch) failed, %d\n", ret); + goto free_rot1; + } + + /* init the MEM-->IC-PRP ROT IDMAC channel */ + ret = prp_setup_channel(priv, priv->rot_in_ch, priv->rot_mode, + priv->rot_buf[0].phys, priv->rot_buf[1].phys, + true); + if (ret) { + v4l2_err(&ic_priv->sd, + "prp_setup_channel(rot_in_ch) failed, %d\n", ret); + goto free_rot1; + } + + prp_setup_vb2_buf(priv, phys); + + /* init the destination IC-PRP ROT-->MEM IDMAC channel */ + ret = prp_setup_channel(priv, priv->rot_out_ch, IPU_ROTATE_NONE, + phys[0], phys[1], + false); + if (ret) { + v4l2_err(&ic_priv->sd, + "prp_setup_channel(rot_out_ch) failed, %d\n", ret); + goto unsetup_vb2; + } + + /* now link IC-PRP-->MEM to MEM-->IC-PRP ROT */ + ipu_idmac_link(priv->out_ch, priv->rot_in_ch); + + /* enable the IC */ + ipu_ic_enable(priv->ic); + + /* set buffers ready */ + ipu_idmac_select_buffer(priv->out_ch, 0); + ipu_idmac_select_buffer(priv->out_ch, 1); + ipu_idmac_select_buffer(priv->rot_out_ch, 0); + ipu_idmac_select_buffer(priv->rot_out_ch, 1); + + /* enable the channels */ + ipu_idmac_enable_channel(priv->out_ch); + ipu_idmac_enable_channel(priv->rot_in_ch); + ipu_idmac_enable_channel(priv->rot_out_ch); + + /* and finally enable the IC PRP task */ + ipu_ic_task_enable(priv->ic); + + return 0; + +unsetup_vb2: + prp_unsetup_vb2_buf(priv, VB2_BUF_STATE_QUEUED); +free_rot1: + imx_media_free_dma_buf(ic_priv->ipu_dev, &priv->rot_buf[1]); +free_rot0: + imx_media_free_dma_buf(ic_priv->ipu_dev, &priv->rot_buf[0]); + return ret; +} + +static void prp_unsetup_rotation(struct prp_priv *priv) +{ + struct imx_ic_priv *ic_priv = priv->ic_priv; + + ipu_ic_task_disable(priv->ic); + + ipu_idmac_disable_channel(priv->out_ch); + ipu_idmac_disable_channel(priv->rot_in_ch); + ipu_idmac_disable_channel(priv->rot_out_ch); + + ipu_idmac_unlink(priv->out_ch, priv->rot_in_ch); + + ipu_ic_disable(priv->ic); + + imx_media_free_dma_buf(ic_priv->ipu_dev, &priv->rot_buf[0]); + imx_media_free_dma_buf(ic_priv->ipu_dev, &priv->rot_buf[1]); +} + +static int prp_setup_norotation(struct prp_priv *priv) +{ + struct imx_media_video_dev *vdev = priv->vdev; + struct imx_ic_priv *ic_priv = priv->ic_priv; + const struct imx_media_pixfmt *outcc, *incc; + struct v4l2_mbus_framefmt *infmt; + struct v4l2_pix_format *outfmt; + struct ipu_ic_csc csc; + dma_addr_t phys[2]; + int ret; + + infmt = &priv->format_mbus[PRPENCVF_SINK_PAD]; + outfmt = &vdev->fmt; + incc = priv->cc[PRPENCVF_SINK_PAD]; + outcc = vdev->cc; + + ret = ipu_ic_calc_csc(&csc, + infmt->ycbcr_enc, infmt->quantization, + incc->cs, + outfmt->ycbcr_enc, outfmt->quantization, + outcc->cs); + if (ret) { + v4l2_err(&ic_priv->sd, "ipu_ic_calc_csc failed, %d\n", + ret); + return ret; + } + + ret = ipu_ic_task_init(priv->ic, &csc, + infmt->width, infmt->height, + outfmt->width, outfmt->height); + if (ret) { + v4l2_err(&ic_priv->sd, "ipu_ic_task_init failed, %d\n", ret); + return ret; + } + + prp_setup_vb2_buf(priv, phys); + + /* init the IC PRP-->MEM IDMAC channel */ + ret = prp_setup_channel(priv, priv->out_ch, priv->rot_mode, + phys[0], phys[1], false); + if (ret) { + v4l2_err(&ic_priv->sd, + "prp_setup_channel(out_ch) failed, %d\n", ret); + goto unsetup_vb2; + } + + ipu_cpmem_dump(priv->out_ch); + ipu_ic_dump(priv->ic); + ipu_dump(ic_priv->ipu); + + ipu_ic_enable(priv->ic); + + /* set buffers ready */ + ipu_idmac_select_buffer(priv->out_ch, 0); + ipu_idmac_select_buffer(priv->out_ch, 1); + + /* enable the channels */ + ipu_idmac_enable_channel(priv->out_ch); + + /* enable the IC task */ + ipu_ic_task_enable(priv->ic); + + return 0; + +unsetup_vb2: + prp_unsetup_vb2_buf(priv, VB2_BUF_STATE_QUEUED); + return ret; +} + +static void prp_unsetup_norotation(struct prp_priv *priv) +{ + ipu_ic_task_disable(priv->ic); + ipu_idmac_disable_channel(priv->out_ch); + ipu_ic_disable(priv->ic); +} + +static void prp_unsetup(struct prp_priv *priv, + enum vb2_buffer_state state) +{ + if (ipu_rot_mode_is_irt(priv->rot_mode)) + prp_unsetup_rotation(priv); + else + prp_unsetup_norotation(priv); + + prp_unsetup_vb2_buf(priv, state); +} + +static int prp_start(struct prp_priv *priv) +{ + struct imx_ic_priv *ic_priv = priv->ic_priv; + struct imx_media_video_dev *vdev = priv->vdev; + int ret; + + ret = prp_get_ipu_resources(priv); + if (ret) + return ret; + + ret = imx_media_alloc_dma_buf(ic_priv->ipu_dev, &priv->underrun_buf, + vdev->fmt.sizeimage); + if (ret) + goto out_put_ipu; + + priv->ipu_buf_num = 0; + + /* init EOF completion waitq */ + init_completion(&priv->last_eof_comp); + priv->frame_sequence = 0; + priv->last_eof = false; + priv->nfb4eof = false; + + if (ipu_rot_mode_is_irt(priv->rot_mode)) + ret = prp_setup_rotation(priv); + else + ret = prp_setup_norotation(priv); + if (ret) + goto out_free_underrun; + + priv->nfb4eof_irq = ipu_idmac_channel_irq(ic_priv->ipu, + priv->out_ch, + IPU_IRQ_NFB4EOF); + ret = devm_request_irq(ic_priv->ipu_dev, priv->nfb4eof_irq, + prp_nfb4eof_interrupt, 0, + "imx-ic-prp-nfb4eof", priv); + if (ret) { + v4l2_err(&ic_priv->sd, + "Error registering NFB4EOF irq: %d\n", ret); + goto out_unsetup; + } + + if (ipu_rot_mode_is_irt(priv->rot_mode)) + priv->eof_irq = ipu_idmac_channel_irq( + ic_priv->ipu, priv->rot_out_ch, IPU_IRQ_EOF); + else + priv->eof_irq = ipu_idmac_channel_irq( + ic_priv->ipu, priv->out_ch, IPU_IRQ_EOF); + + ret = devm_request_irq(ic_priv->ipu_dev, priv->eof_irq, + prp_eof_interrupt, 0, + "imx-ic-prp-eof", priv); + if (ret) { + v4l2_err(&ic_priv->sd, + "Error registering eof irq: %d\n", ret); + goto out_free_nfb4eof_irq; + } + + /* start upstream */ + ret = v4l2_subdev_call(priv->src_sd, video, s_stream, 1); + ret = (ret && ret != -ENOIOCTLCMD) ? ret : 0; + if (ret) { + v4l2_err(&ic_priv->sd, + "upstream stream on failed: %d\n", ret); + goto out_free_eof_irq; + } + + /* start the EOF timeout timer */ + mod_timer(&priv->eof_timeout_timer, + jiffies + msecs_to_jiffies(IMX_MEDIA_EOF_TIMEOUT)); + + return 0; + +out_free_eof_irq: + devm_free_irq(ic_priv->ipu_dev, priv->eof_irq, priv); +out_free_nfb4eof_irq: + devm_free_irq(ic_priv->ipu_dev, priv->nfb4eof_irq, priv); +out_unsetup: + prp_unsetup(priv, VB2_BUF_STATE_QUEUED); +out_free_underrun: + imx_media_free_dma_buf(ic_priv->ipu_dev, &priv->underrun_buf); +out_put_ipu: + prp_put_ipu_resources(priv); + return ret; +} + +static void prp_stop(struct prp_priv *priv) +{ + struct imx_ic_priv *ic_priv = priv->ic_priv; + unsigned long flags; + int ret; + + /* mark next EOF interrupt as the last before stream off */ + spin_lock_irqsave(&priv->irqlock, flags); + priv->last_eof = true; + spin_unlock_irqrestore(&priv->irqlock, flags); + + /* + * and then wait for interrupt handler to mark completion. + */ + ret = wait_for_completion_timeout( + &priv->last_eof_comp, + msecs_to_jiffies(IMX_MEDIA_EOF_TIMEOUT)); + if (ret == 0) + v4l2_warn(&ic_priv->sd, "wait last EOF timeout\n"); + + /* stop upstream */ + ret = v4l2_subdev_call(priv->src_sd, video, s_stream, 0); + if (ret && ret != -ENOIOCTLCMD) + v4l2_warn(&ic_priv->sd, + "upstream stream off failed: %d\n", ret); + + devm_free_irq(ic_priv->ipu_dev, priv->eof_irq, priv); + devm_free_irq(ic_priv->ipu_dev, priv->nfb4eof_irq, priv); + + prp_unsetup(priv, VB2_BUF_STATE_ERROR); + + imx_media_free_dma_buf(ic_priv->ipu_dev, &priv->underrun_buf); + + /* cancel the EOF timeout timer */ + del_timer_sync(&priv->eof_timeout_timer); + + prp_put_ipu_resources(priv); +} + +static struct v4l2_mbus_framefmt * +__prp_get_fmt(struct prp_priv *priv, struct v4l2_subdev_state *sd_state, + unsigned int pad, enum v4l2_subdev_format_whence which) +{ + struct imx_ic_priv *ic_priv = priv->ic_priv; + + if (which == V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_get_try_format(&ic_priv->sd, sd_state, pad); + else + return &priv->format_mbus[pad]; +} + +/* + * Applies IC resizer and IDMAC alignment restrictions to output + * rectangle given the input rectangle, and depending on given + * rotation mode. + * + * The IC resizer cannot downsize more than 4:1. Note also that + * for 90 or 270 rotation, _both_ output width and height must + * be aligned by W_ALIGN_SRC, because the intermediate rotation + * buffer swaps output width/height, and the final output buffer + * does not. + * + * Returns true if the output rectangle was modified. + */ +static bool prp_bound_align_output(struct v4l2_mbus_framefmt *outfmt, + struct v4l2_mbus_framefmt *infmt, + enum ipu_rotate_mode rot_mode) +{ + u32 orig_width = outfmt->width; + u32 orig_height = outfmt->height; + + if (ipu_rot_mode_is_irt(rot_mode)) + v4l_bound_align_image(&outfmt->width, + infmt->height / 4, MAX_H_SRC, + W_ALIGN_SRC, + &outfmt->height, + infmt->width / 4, MAX_W_SRC, + W_ALIGN_SRC, S_ALIGN); + else + v4l_bound_align_image(&outfmt->width, + infmt->width / 4, MAX_W_SRC, + W_ALIGN_SRC, + &outfmt->height, + infmt->height / 4, MAX_H_SRC, + H_ALIGN_SRC, S_ALIGN); + + return outfmt->width != orig_width || outfmt->height != orig_height; +} + +/* + * V4L2 subdev operations. + */ + +static int prp_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->pad >= PRPENCVF_NUM_PADS) + return -EINVAL; + + return imx_media_enum_ipu_formats(&code->code, code->index, + PIXFMT_SEL_YUV_RGB); +} + +static int prp_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *sdformat) +{ + struct prp_priv *priv = sd_to_priv(sd); + struct v4l2_mbus_framefmt *fmt; + int ret = 0; + + if (sdformat->pad >= PRPENCVF_NUM_PADS) + return -EINVAL; + + mutex_lock(&priv->lock); + + fmt = __prp_get_fmt(priv, sd_state, sdformat->pad, sdformat->which); + if (!fmt) { + ret = -EINVAL; + goto out; + } + + sdformat->format = *fmt; +out: + mutex_unlock(&priv->lock); + return ret; +} + +static void prp_try_fmt(struct prp_priv *priv, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *sdformat, + const struct imx_media_pixfmt **cc) +{ + struct v4l2_mbus_framefmt *infmt; + + *cc = imx_media_find_ipu_format(sdformat->format.code, + PIXFMT_SEL_YUV_RGB); + if (!*cc) { + u32 code; + + imx_media_enum_ipu_formats(&code, 0, PIXFMT_SEL_YUV_RGB); + *cc = imx_media_find_ipu_format(code, PIXFMT_SEL_YUV_RGB); + + sdformat->format.code = (*cc)->codes[0]; + } + + infmt = __prp_get_fmt(priv, sd_state, PRPENCVF_SINK_PAD, + sdformat->which); + + if (sdformat->pad == PRPENCVF_SRC_PAD) { + sdformat->format.field = infmt->field; + + prp_bound_align_output(&sdformat->format, infmt, + priv->rot_mode); + + /* propagate colorimetry from sink */ + sdformat->format.colorspace = infmt->colorspace; + sdformat->format.xfer_func = infmt->xfer_func; + } else { + v4l_bound_align_image(&sdformat->format.width, + MIN_W_SINK, MAX_W_SINK, W_ALIGN_SINK, + &sdformat->format.height, + MIN_H_SINK, MAX_H_SINK, H_ALIGN_SINK, + S_ALIGN); + + if (sdformat->format.field == V4L2_FIELD_ANY) + sdformat->format.field = V4L2_FIELD_NONE; + } + + imx_media_try_colorimetry(&sdformat->format, true); +} + +static int prp_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *sdformat) +{ + struct prp_priv *priv = sd_to_priv(sd); + const struct imx_media_pixfmt *cc; + struct v4l2_mbus_framefmt *fmt; + int ret = 0; + + if (sdformat->pad >= PRPENCVF_NUM_PADS) + return -EINVAL; + + mutex_lock(&priv->lock); + + if (priv->stream_count > 0) { + ret = -EBUSY; + goto out; + } + + prp_try_fmt(priv, sd_state, sdformat, &cc); + + fmt = __prp_get_fmt(priv, sd_state, sdformat->pad, sdformat->which); + *fmt = sdformat->format; + + /* propagate a default format to source pad */ + if (sdformat->pad == PRPENCVF_SINK_PAD) { + const struct imx_media_pixfmt *outcc; + struct v4l2_mbus_framefmt *outfmt; + struct v4l2_subdev_format format; + + format.pad = PRPENCVF_SRC_PAD; + format.which = sdformat->which; + format.format = sdformat->format; + prp_try_fmt(priv, sd_state, &format, &outcc); + + outfmt = __prp_get_fmt(priv, sd_state, PRPENCVF_SRC_PAD, + sdformat->which); + *outfmt = format.format; + if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) + priv->cc[PRPENCVF_SRC_PAD] = outcc; + } + + if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) + priv->cc[sdformat->pad] = cc; + +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct prp_priv *priv = sd_to_priv(sd); + struct v4l2_subdev_format format = {}; + const struct imx_media_pixfmt *cc; + int ret = 0; + + if (fse->pad >= PRPENCVF_NUM_PADS || fse->index != 0) + return -EINVAL; + + mutex_lock(&priv->lock); + + format.pad = fse->pad; + format.which = fse->which; + format.format.code = fse->code; + format.format.width = 1; + format.format.height = 1; + prp_try_fmt(priv, sd_state, &format, &cc); + fse->min_width = format.format.width; + fse->min_height = format.format.height; + + if (format.format.code != fse->code) { + ret = -EINVAL; + goto out; + } + + format.format.code = fse->code; + format.format.width = -1; + format.format.height = -1; + prp_try_fmt(priv, sd_state, &format, &cc); + fse->max_width = format.format.width; + fse->max_height = format.format.height; +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); + struct imx_ic_priv *ic_priv = v4l2_get_subdevdata(sd); + struct prp_priv *priv = ic_priv->task_priv; + struct v4l2_subdev *remote_sd; + int ret = 0; + + dev_dbg(ic_priv->ipu_dev, "%s: link setup %s -> %s", + ic_priv->sd.name, remote->entity->name, local->entity->name); + + mutex_lock(&priv->lock); + + if (local->flags & MEDIA_PAD_FL_SINK) { + if (!is_media_entity_v4l2_subdev(remote->entity)) { + ret = -EINVAL; + goto out; + } + + remote_sd = media_entity_to_v4l2_subdev(remote->entity); + + if (flags & MEDIA_LNK_FL_ENABLED) { + if (priv->src_sd) { + ret = -EBUSY; + goto out; + } + priv->src_sd = remote_sd; + } else { + priv->src_sd = NULL; + } + + goto out; + } + + /* this is the source pad */ + + /* the remote must be the device node */ + if (!is_media_entity_v4l2_video_device(remote->entity)) { + ret = -EINVAL; + goto out; + } + + if (flags & MEDIA_LNK_FL_ENABLED) { + if (priv->sink) { + ret = -EBUSY; + goto out; + } + } else { + priv->sink = NULL; + goto out; + } + + priv->sink = remote->entity; +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct prp_priv *priv = container_of(ctrl->handler, + struct prp_priv, ctrl_hdlr); + struct imx_ic_priv *ic_priv = priv->ic_priv; + enum ipu_rotate_mode rot_mode; + int rotation, ret = 0; + bool hflip, vflip; + + mutex_lock(&priv->lock); + + rotation = priv->rotation; + hflip = priv->hflip; + vflip = priv->vflip; + + switch (ctrl->id) { + case V4L2_CID_HFLIP: + hflip = (ctrl->val == 1); + break; + case V4L2_CID_VFLIP: + vflip = (ctrl->val == 1); + break; + case V4L2_CID_ROTATE: + rotation = ctrl->val; + break; + default: + v4l2_err(&ic_priv->sd, "Invalid control\n"); + ret = -EINVAL; + goto out; + } + + ret = ipu_degrees_to_rot_mode(&rot_mode, rotation, hflip, vflip); + if (ret) + goto out; + + if (rot_mode != priv->rot_mode) { + struct v4l2_mbus_framefmt outfmt, infmt; + + /* can't change rotation mid-streaming */ + if (priv->stream_count > 0) { + ret = -EBUSY; + goto out; + } + + outfmt = priv->format_mbus[PRPENCVF_SRC_PAD]; + infmt = priv->format_mbus[PRPENCVF_SINK_PAD]; + + if (prp_bound_align_output(&outfmt, &infmt, rot_mode)) { + ret = -EINVAL; + goto out; + } + + priv->rot_mode = rot_mode; + priv->rotation = rotation; + priv->hflip = hflip; + priv->vflip = vflip; + } + +out: + mutex_unlock(&priv->lock); + return ret; +} + +static const struct v4l2_ctrl_ops prp_ctrl_ops = { + .s_ctrl = prp_s_ctrl, +}; + +static int prp_init_controls(struct prp_priv *priv) +{ + struct imx_ic_priv *ic_priv = priv->ic_priv; + struct v4l2_ctrl_handler *hdlr = &priv->ctrl_hdlr; + int ret; + + v4l2_ctrl_handler_init(hdlr, 3); + + v4l2_ctrl_new_std(hdlr, &prp_ctrl_ops, V4L2_CID_HFLIP, + 0, 1, 1, 0); + v4l2_ctrl_new_std(hdlr, &prp_ctrl_ops, V4L2_CID_VFLIP, + 0, 1, 1, 0); + v4l2_ctrl_new_std(hdlr, &prp_ctrl_ops, V4L2_CID_ROTATE, + 0, 270, 90, 0); + + ic_priv->sd.ctrl_handler = hdlr; + + if (hdlr->error) { + ret = hdlr->error; + goto out_free; + } + + v4l2_ctrl_handler_setup(hdlr); + return 0; + +out_free: + v4l2_ctrl_handler_free(hdlr); + return ret; +} + +static int prp_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct imx_ic_priv *ic_priv = v4l2_get_subdevdata(sd); + struct prp_priv *priv = ic_priv->task_priv; + int ret = 0; + + mutex_lock(&priv->lock); + + if (!priv->src_sd || !priv->sink) { + ret = -EPIPE; + goto out; + } + + /* + * enable/disable streaming only if stream_count is + * going from 0 to 1 / 1 to 0. + */ + if (priv->stream_count != !enable) + goto update_count; + + dev_dbg(ic_priv->ipu_dev, "%s: stream %s\n", sd->name, + enable ? "ON" : "OFF"); + + if (enable) + ret = prp_start(priv); + else + prp_stop(priv); + if (ret) + goto out; + +update_count: + priv->stream_count += enable ? 1 : -1; + if (priv->stream_count < 0) + priv->stream_count = 0; +out: + mutex_unlock(&priv->lock); + return ret; +} + +static int prp_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct prp_priv *priv = sd_to_priv(sd); + + if (fi->pad >= PRPENCVF_NUM_PADS) + return -EINVAL; + + mutex_lock(&priv->lock); + fi->interval = priv->frame_interval; + mutex_unlock(&priv->lock); + + return 0; +} + +static int prp_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct prp_priv *priv = sd_to_priv(sd); + + if (fi->pad >= PRPENCVF_NUM_PADS) + return -EINVAL; + + mutex_lock(&priv->lock); + + /* No limits on valid frame intervals */ + if (fi->interval.numerator == 0 || fi->interval.denominator == 0) + fi->interval = priv->frame_interval; + else + priv->frame_interval = fi->interval; + + mutex_unlock(&priv->lock); + + return 0; +} + +static int prp_registered(struct v4l2_subdev *sd) +{ + struct prp_priv *priv = sd_to_priv(sd); + struct imx_ic_priv *ic_priv = priv->ic_priv; + int i, ret; + u32 code; + + /* set a default mbus format */ + imx_media_enum_ipu_formats(&code, 0, PIXFMT_SEL_YUV); + + for (i = 0; i < PRPENCVF_NUM_PADS; i++) { + ret = imx_media_init_mbus_fmt(&priv->format_mbus[i], + IMX_MEDIA_DEF_PIX_WIDTH, + IMX_MEDIA_DEF_PIX_HEIGHT, code, + V4L2_FIELD_NONE, &priv->cc[i]); + if (ret) + return ret; + } + + /* init default frame interval */ + priv->frame_interval.numerator = 1; + priv->frame_interval.denominator = 30; + + priv->vdev = imx_media_capture_device_init(ic_priv->ipu_dev, + &ic_priv->sd, + PRPENCVF_SRC_PAD, true); + if (IS_ERR(priv->vdev)) + return PTR_ERR(priv->vdev); + + ret = imx_media_capture_device_register(priv->vdev, 0); + if (ret) + goto remove_vdev; + + ret = prp_init_controls(priv); + if (ret) + goto unreg_vdev; + + return 0; + +unreg_vdev: + imx_media_capture_device_unregister(priv->vdev); +remove_vdev: + imx_media_capture_device_remove(priv->vdev); + return ret; +} + +static void prp_unregistered(struct v4l2_subdev *sd) +{ + struct prp_priv *priv = sd_to_priv(sd); + + imx_media_capture_device_unregister(priv->vdev); + imx_media_capture_device_remove(priv->vdev); + + v4l2_ctrl_handler_free(&priv->ctrl_hdlr); +} + +static const struct v4l2_subdev_pad_ops prp_pad_ops = { + .init_cfg = imx_media_init_cfg, + .enum_mbus_code = prp_enum_mbus_code, + .enum_frame_size = prp_enum_frame_size, + .get_fmt = prp_get_fmt, + .set_fmt = prp_set_fmt, +}; + +static const struct v4l2_subdev_video_ops prp_video_ops = { + .g_frame_interval = prp_g_frame_interval, + .s_frame_interval = prp_s_frame_interval, + .s_stream = prp_s_stream, +}; + +static const struct media_entity_operations prp_entity_ops = { + .link_setup = prp_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_subdev_ops prp_subdev_ops = { + .video = &prp_video_ops, + .pad = &prp_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops prp_internal_ops = { + .registered = prp_registered, + .unregistered = prp_unregistered, +}; + +static int prp_init(struct imx_ic_priv *ic_priv) +{ + struct prp_priv *priv; + int i, ret; + + priv = devm_kzalloc(ic_priv->ipu_dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ic_priv->task_priv = priv; + priv->ic_priv = ic_priv; + + spin_lock_init(&priv->irqlock); + timer_setup(&priv->eof_timeout_timer, prp_eof_timeout, 0); + + mutex_init(&priv->lock); + + for (i = 0; i < PRPENCVF_NUM_PADS; i++) { + priv->pad[i].flags = (i == PRPENCVF_SINK_PAD) ? + MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE; + } + + ret = media_entity_pads_init(&ic_priv->sd.entity, PRPENCVF_NUM_PADS, + priv->pad); + if (ret) + mutex_destroy(&priv->lock); + + return ret; +} + +static void prp_remove(struct imx_ic_priv *ic_priv) +{ + struct prp_priv *priv = ic_priv->task_priv; + + mutex_destroy(&priv->lock); +} + +struct imx_ic_ops imx_ic_prpencvf_ops = { + .subdev_ops = &prp_subdev_ops, + .internal_ops = &prp_internal_ops, + .entity_ops = &prp_entity_ops, + .init = prp_init, + .remove = prp_remove, +}; diff --git a/drivers/staging/media/imx/imx-ic.h b/drivers/staging/media/imx/imx-ic.h new file mode 100644 index 000000000..587c191c3 --- /dev/null +++ b/drivers/staging/media/imx/imx-ic.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * V4L2 Image Converter Subdev for Freescale i.MX5/6 SOC + * + * Copyright (c) 2016 Mentor Graphics Inc. + */ +#ifndef _IMX_IC_H +#define _IMX_IC_H + +#include + +struct imx_ic_priv { + struct device *ipu_dev; + struct ipu_soc *ipu; + struct v4l2_subdev sd; + int task_id; + void *task_priv; +}; + +struct imx_ic_ops { + const struct v4l2_subdev_ops *subdev_ops; + const struct v4l2_subdev_internal_ops *internal_ops; + const struct media_entity_operations *entity_ops; + + int (*init)(struct imx_ic_priv *ic_priv); + void (*remove)(struct imx_ic_priv *ic_priv); +}; + +extern struct imx_ic_ops imx_ic_prp_ops; +extern struct imx_ic_ops imx_ic_prpencvf_ops; + +#endif diff --git a/drivers/staging/media/imx/imx-media-capture.c b/drivers/staging/media/imx/imx-media-capture.c new file mode 100644 index 000000000..93ba09236 --- /dev/null +++ b/drivers/staging/media/imx/imx-media-capture.c @@ -0,0 +1,1051 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Video Capture Subdev for Freescale i.MX5/6 SOC + * + * Copyright (c) 2012-2016 Mentor Graphics Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include