From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- include/video/s1d13xxxfb.h | 174 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) create mode 100644 include/video/s1d13xxxfb.h (limited to 'include/video/s1d13xxxfb.h') diff --git a/include/video/s1d13xxxfb.h b/include/video/s1d13xxxfb.h new file mode 100644 index 000000000..55f534491 --- /dev/null +++ b/include/video/s1d13xxxfb.h @@ -0,0 +1,174 @@ +/* include/video/s1d13xxxfb.h + * + * (c) 2004 Simtec Electronics + * (c) 2005 Thibaut VARENE + * + * Header file for Epson S1D13XXX driver code + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef S1D13XXXFB_H +#define S1D13XXXFB_H + +#define S1D_PALETTE_SIZE 256 +#define S1D_FBID "S1D13xxx" +#define S1D_DEVICENAME "s1d13xxxfb" + +/* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */ +#define S1D13505_PROD_ID 0x3 /* 000011 */ +#define S1D13506_PROD_ID 0x4 /* 000100 */ +#define S1D13806_PROD_ID 0x7 /* 000111 */ + +/* register definitions (tested on s1d13896) */ +#define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */ +#define S1DREG_MISC 0x0001 /* Miscellaneous Register */ +#define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */ +#define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */ +#define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */ +#define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */ +#define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */ +#define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */ +#define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */ +#define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */ +#define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */ +#define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */ +#define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */ +#define S1DREG_SDRAM_REF_RATE 0x0021 /* SDRAM Refresh Rate Register */ +#define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */ +#define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */ +#define S1DREG_PANEL_TYPE 0x0030 /* Panel Type Register */ +#define S1DREG_MOD_RATE 0x0031 /* MOD Rate Register */ +#define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */ +#define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */ +#define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */ +#define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */ +#define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */ +#define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */ +#define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines */ +#define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */ +#define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */ +#define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */ +#define S1DREG_LCD_MISC 0x0041 /* LCD Miscellaneous Register */ +#define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */ +#define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */ +#define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */ +#define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */ +#define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */ +#define S1DREG_LCD_PIX_PAN 0x0048 /* LCD Pixel Panning Register */ +#define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */ +#define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */ +#define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */ +#define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */ +#define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */ +#define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */ +#define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */ +#define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */ +#define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */ +#define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */ +#define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */ +#define S1DREG_TV_OUT_CTL 0x005B /* TV Output Control Register */ +#define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */ +#define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */ +#define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */ +#define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */ +#define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */ +#define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */ +#define S1DREG_CRT_PIX_PAN 0x0068 /* CRT/TV Pixel Panning Register */ +#define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */ +#define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */ +#define S1DREG_LCD_CUR_CTL 0x0070 /* LCD Ink/Cursor Control Register */ +#define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */ +#define S1DREG_LCD_CUR_XPOS0 0x0072 /* LCD Cursor X Position Register 0 */ +#define S1DREG_LCD_CUR_XPOS1 0x0073 /* LCD Cursor X Position Register 1 */ +#define S1DREG_LCD_CUR_YPOS0 0x0074 /* LCD Cursor Y Position Register 0 */ +#define S1DREG_LCD_CUR_YPOS1 0x0075 /* LCD Cursor Y Position Register 1 */ +#define S1DREG_LCD_CUR_BCTL0 0x0076 /* LCD Ink/Cursor Blue Color 0 Register */ +#define S1DREG_LCD_CUR_GCTL0 0x0077 /* LCD Ink/Cursor Green Color 0 Register */ +#define S1DREG_LCD_CUR_RCTL0 0x0078 /* LCD Ink/Cursor Red Color 0 Register */ +#define S1DREG_LCD_CUR_BCTL1 0x007A /* LCD Ink/Cursor Blue Color 1 Register */ +#define S1DREG_LCD_CUR_GCTL1 0x007B /* LCD Ink/Cursor Green Color 1 Register */ +#define S1DREG_LCD_CUR_RCTL1 0x007C /* LCD Ink/Cursor Red Color 1 Register */ +#define S1DREG_LCD_CUR_FIFO_HTC 0x007E /* LCD Ink/Cursor FIFO High Threshold Register */ +#define S1DREG_CRT_CUR_CTL 0x0080 /* CRT/TV Ink/Cursor Control Register */ +#define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */ +#define S1DREG_CRT_CUR_XPOS0 0x0082 /* CRT/TV Cursor X Position Register 0 */ +#define S1DREG_CRT_CUR_XPOS1 0x0083 /* CRT/TV Cursor X Position Register 1 */ +#define S1DREG_CRT_CUR_YPOS0 0x0084 /* CRT/TV Cursor Y Position Register 0 */ +#define S1DREG_CRT_CUR_YPOS1 0x0085 /* CRT/TV Cursor Y Position Register 1 */ +#define S1DREG_CRT_CUR_BCTL0 0x0086 /* CRT/TV Ink/Cursor Blue Color 0 Register */ +#define S1DREG_CRT_CUR_GCTL0 0x0087 /* CRT/TV Ink/Cursor Green Color 0 Register */ +#define S1DREG_CRT_CUR_RCTL0 0x0088 /* CRT/TV Ink/Cursor Red Color 0 Register */ +#define S1DREG_CRT_CUR_BCTL1 0x008A /* CRT/TV Ink/Cursor Blue Color 1 Register */ +#define S1DREG_CRT_CUR_GCTL1 0x008B /* CRT/TV Ink/Cursor Green Color 1 Register */ +#define S1DREG_CRT_CUR_RCTL1 0x008C /* CRT/TV Ink/Cursor Red Color 1 Register */ +#define S1DREG_CRT_CUR_FIFO_HTC 0x008E /* CRT/TV Ink/Cursor FIFO High Threshold Register */ +#define S1DREG_BBLT_CTL0 0x0100 /* BitBLT Control Register 0 */ +#define S1DREG_BBLT_CTL1 0x0101 /* BitBLT Control Register 1 */ +#define S1DREG_BBLT_CC_EXP 0x0102 /* BitBLT Code/Color Expansion Register */ +#define S1DREG_BBLT_OP 0x0103 /* BitBLT Operation Register */ +#define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */ +#define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */ +#define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */ +#define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */ +#define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */ +#define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */ +#define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */ +#define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */ +#define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */ +#define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */ +#define S1DREG_BBLT_HEIGHT0 0x0112 /* BitBLT Height Register 0 */ +#define S1DREG_BBLT_HEIGHT1 0x0113 /* BitBLT Height Register 1 */ +#define S1DREG_BBLT_BGC0 0x0114 /* BitBLT Background Color Register 0 */ +#define S1DREG_BBLT_BGC1 0x0115 /* BitBLT Background Color Register 1 */ +#define S1DREG_BBLT_FGC0 0x0118 /* BitBLT Foreground Color Register 0 */ +#define S1DREG_BBLT_FGC1 0x0119 /* BitBLT Foreground Color Register 1 */ +#define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */ +#define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */ +#define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */ +#define S1DREG_PS_CNF 0x01F0 /* Power Save Configuration Register */ +#define S1DREG_PS_STATUS 0x01F1 /* Power Save Status Register */ +#define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */ +#define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */ + +#define S1DREG_DELAYOFF 0xFFFE +#define S1DREG_DELAYON 0xFFFF + +#define BBLT_SOLID_FILL 0x0c + + +/* Note: all above defines should go in separate header files + when implementing other S1D13xxx chip support. */ + +struct s1d13xxxfb_regval { + u16 addr; + u8 value; +}; + +struct s1d13xxxfb_par { + void __iomem *regs; + unsigned char display; + unsigned char prod_id; + unsigned char revision; + + unsigned int pseudo_palette[16]; +#ifdef CONFIG_PM + void *regs_save; /* pm saves all registers here */ + void *disp_save; /* pm saves entire screen here */ +#endif +}; + +struct s1d13xxxfb_pdata { + const struct s1d13xxxfb_regval *initregs; + const unsigned int initregssize; + void (*platform_init_video)(void); +#ifdef CONFIG_PM + int (*platform_suspend_video)(void); + int (*platform_resume_video)(void); +#endif +}; + +#endif + -- cgit v1.2.3