From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- sound/pci/ice1712/envy24ht.h | 206 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 206 insertions(+) create mode 100644 sound/pci/ice1712/envy24ht.h (limited to 'sound/pci/ice1712/envy24ht.h') diff --git a/sound/pci/ice1712/envy24ht.h b/sound/pci/ice1712/envy24ht.h new file mode 100644 index 000000000..10e79c82f --- /dev/null +++ b/sound/pci/ice1712/envy24ht.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_VT1724_H +#define __SOUND_VT1724_H + +/* + * ALSA driver for ICEnsemble VT1724 (Envy24) + * + * Copyright (c) 2000 Jaroslav Kysela + */ + +#include +#include +#include +#include +#include + +#include "ice1712.h" + +enum { + ICE_EEP2_SYSCONF = 0, /* 06 */ + ICE_EEP2_ACLINK, /* 07 */ + ICE_EEP2_I2S, /* 08 */ + ICE_EEP2_SPDIF, /* 09 */ + ICE_EEP2_GPIO_DIR, /* 0a */ + ICE_EEP2_GPIO_DIR1, /* 0b */ + ICE_EEP2_GPIO_DIR2, /* 0c */ + ICE_EEP2_GPIO_MASK, /* 0d */ + ICE_EEP2_GPIO_MASK1, /* 0e */ + ICE_EEP2_GPIO_MASK2, /* 0f */ + ICE_EEP2_GPIO_STATE, /* 10 */ + ICE_EEP2_GPIO_STATE1, /* 11 */ + ICE_EEP2_GPIO_STATE2 /* 12 */ +}; + +/* + * Direct registers + */ + +#define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x) + +#define VT1724_REG_CONTROL 0x00 /* byte */ +#define VT1724_RESET 0x80 /* reset whole chip */ +#define VT1724_REG_IRQMASK 0x01 /* byte */ +#define VT1724_IRQ_MPU_RX 0x80 +#define VT1724_IRQ_MPU_TX 0x20 +#define VT1724_IRQ_MTPCM 0x10 +#define VT1724_REG_IRQSTAT 0x02 /* byte */ +/* look to VT1724_IRQ_* */ +#define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/ +#define VT1724_CFG_CLOCK 0xc0 +#define VT1724_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */ +#define VT1724_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */ +#define VT1724_CFG_MPU401 0x20 /* MPU401 UARTs */ +#define VT1724_CFG_ADC_MASK 0x0c /* one, two or one and S/PDIF, stereo ADCs */ +#define VT1724_CFG_ADC_NONE 0x0c /* no ADCs */ +#define VT1724_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */ + +#define VT1724_REG_AC97_CFG 0x05 /* byte */ +#define VT1724_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */ +#define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */ + +#define VT1724_REG_I2S_FEATURES 0x06 /* byte */ +#define VT1724_CFG_I2S_VOLUME 0x80 /* volume/mute capability */ +#define VT1724_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */ +#define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */ +#define VT1724_CFG_I2S_192KHZ 0x08 /* supports 192kHz sampling */ +#define VT1724_CFG_I2S_OTHER 0x07 /* other I2S IDs */ + +#define VT1724_REG_SPDIF_CFG 0x07 /* byte */ +#define VT1724_CFG_SPDIF_OUT_EN 0x80 /*Internal S/PDIF output is enabled*/ +#define VT1724_CFG_SPDIF_OUT_INT 0x40 /*Internal S/PDIF output is implemented*/ +#define VT1724_CFG_I2S_CHIPID 0x3c /* I2S chip ID */ +#define VT1724_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */ +#define VT1724_CFG_SPDIF_OUT 0x01 /* External S/PDIF output is present */ + +/*there is no consumer AC97 codec with the VT1724*/ +//#define VT1724_REG_AC97_INDEX 0x08 /* byte */ +//#define VT1724_REG_AC97_CMD 0x09 /* byte */ + +#define VT1724_REG_MPU_TXFIFO 0x0a /*byte ro. number of bytes in TX fifo*/ +#define VT1724_REG_MPU_RXFIFO 0x0b /*byte ro. number of bytes in RX fifo*/ + +#define VT1724_REG_MPU_DATA 0x0c /* byte */ +#define VT1724_REG_MPU_CTRL 0x0d /* byte */ +#define VT1724_MPU_UART 0x01 +#define VT1724_MPU_TX_EMPTY 0x02 +#define VT1724_MPU_TX_FULL 0x04 +#define VT1724_MPU_RX_EMPTY 0x08 +#define VT1724_MPU_RX_FULL 0x10 + +#define VT1724_REG_MPU_FIFO_WM 0x0e /*byte set the high/low watermarks for RX/TX fifos*/ +#define VT1724_MPU_RX_FIFO 0x20 //1=rx fifo watermark 0=tx fifo watermark +#define VT1724_MPU_FIFO_MASK 0x1f + +#define VT1724_REG_I2C_DEV_ADDR 0x10 /* byte */ +#define VT1724_I2C_WRITE 0x01 /* write direction */ +#define VT1724_REG_I2C_BYTE_ADDR 0x11 /* byte */ +#define VT1724_REG_I2C_DATA 0x12 /* byte */ +#define VT1724_REG_I2C_CTRL 0x13 /* byte */ +#define VT1724_I2C_EEPROM 0x80 /* 1 = EEPROM exists */ +#define VT1724_I2C_BUSY 0x01 /* busy bit */ + +#define VT1724_REG_GPIO_DATA 0x14 /* word */ +#define VT1724_REG_GPIO_WRITE_MASK 0x16 /* word */ +#define VT1724_REG_GPIO_DIRECTION 0x18 /* dword? (3 bytes) 0=input 1=output. + bit3 - during reset used for Eeprom power-on strapping + if TESTEN# pin active, bit 2 always input*/ +#define VT1724_REG_POWERDOWN 0x1c +#define VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */ +#define VT1724_REG_GPIO_WRITE_MASK_22 0x1f /* byte write mask for GPIO 16:22 */ + + +/* + * Professional multi-track direct control registers + */ + +#define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x) + +#define VT1724_MT_IRQ 0x00 /* byte - interrupt mask */ +#define VT1724_MULTI_PDMA4 0x80 /* SPDIF Out / PDMA4 */ +#define VT1724_MULTI_PDMA3 0x40 /* PDMA3 */ +#define VT1724_MULTI_PDMA2 0x20 /* PDMA2 */ +#define VT1724_MULTI_PDMA1 0x10 /* PDMA1 */ +#define VT1724_MULTI_FIFO_ERR 0x08 /* DMA FIFO underrun/overrun. */ +#define VT1724_MULTI_RDMA1 0x04 /* RDMA1 (S/PDIF input) */ +#define VT1724_MULTI_RDMA0 0x02 /* RMDA0 */ +#define VT1724_MULTI_PDMA0 0x01 /* MC Interleave/PDMA0 */ + +#define VT1724_MT_RATE 0x01 /* byte - sampling rate select */ +#define VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */ +#define VT1724_MT_I2S_FORMAT 0x02 /* byte - I2S data format */ +#define VT1724_MT_I2S_MCLK_128X 0x08 +#define VT1724_MT_I2S_FORMAT_MASK 0x03 +#define VT1724_MT_I2S_FORMAT_I2S 0x00 +#define VT1724_MT_DMA_INT_MASK 0x03 /* byte -DMA Interrupt Mask */ +/* lool to VT1724_MULTI_* */ +#define VT1724_MT_AC97_INDEX 0x04 /* byte - AC'97 index */ +#define VT1724_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */ +#define VT1724_AC97_COLD 0x80 /* cold reset */ +#define VT1724_AC97_WARM 0x40 /* warm reset */ +#define VT1724_AC97_WRITE 0x20 /* W: write, R: write in progress */ +#define VT1724_AC97_READ 0x10 /* W: read, R: read in progress */ +#define VT1724_AC97_READY 0x08 /* codec ready status bit */ +#define VT1724_AC97_ID_MASK 0x03 /* codec id mask */ +#define VT1724_MT_AC97_DATA 0x06 /* word - AC'97 data */ +#define VT1724_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */ +#define VT1724_MT_PLAYBACK_SIZE 0x14 /* dword - playback size */ +#define VT1724_MT_DMA_CONTROL 0x18 /* byte - control */ +#define VT1724_PDMA4_START 0x80 /* SPDIF out / PDMA4 start */ +#define VT1724_PDMA3_START 0x40 /* PDMA3 start */ +#define VT1724_PDMA2_START 0x20 /* PDMA2 start */ +#define VT1724_PDMA1_START 0x10 /* PDMA1 start */ +#define VT1724_RDMA1_START 0x04 /* RDMA1 start */ +#define VT1724_RDMA0_START 0x02 /* RMDA0 start */ +#define VT1724_PDMA0_START 0x01 /* MC Interleave / PDMA0 start */ +#define VT1724_MT_BURST 0x19 /* Interleaved playback DMA Active streams / PCI burst size */ +#define VT1724_MT_DMA_FIFO_ERR 0x1a /*Global playback and record DMA FIFO Underrun/Overrun */ +#define VT1724_PDMA4_UNDERRUN 0x80 +#define VT1724_PDMA2_UNDERRUN 0x40 +#define VT1724_PDMA3_UNDERRUN 0x20 +#define VT1724_PDMA1_UNDERRUN 0x10 +#define VT1724_RDMA1_UNDERRUN 0x04 +#define VT1724_RDMA0_UNDERRUN 0x02 +#define VT1724_PDMA0_UNDERRUN 0x01 +#define VT1724_MT_DMA_PAUSE 0x1b /*Global playback and record DMA FIFO pause/resume */ +#define VT1724_PDMA4_PAUSE 0x80 +#define VT1724_PDMA3_PAUSE 0x40 +#define VT1724_PDMA2_PAUSE 0x20 +#define VT1724_PDMA1_PAUSE 0x10 +#define VT1724_RDMA1_PAUSE 0x04 +#define VT1724_RDMA0_PAUSE 0x02 +#define VT1724_PDMA0_PAUSE 0x01 +#define VT1724_MT_PLAYBACK_COUNT 0x1c /* word - playback count */ +#define VT1724_MT_CAPTURE_ADDR 0x20 /* dword - capture address */ +#define VT1724_MT_CAPTURE_SIZE 0x24 /* word - capture size */ +#define VT1724_MT_CAPTURE_COUNT 0x26 /* word - capture count */ + +#define VT1724_MT_ROUTE_PLAYBACK 0x2c /* word */ + +#define VT1724_MT_RDMA1_ADDR 0x30 /* dword - RDMA1 capture address */ +#define VT1724_MT_RDMA1_SIZE 0x34 /* word - RDMA1 capture size */ +#define VT1724_MT_RDMA1_COUNT 0x36 /* word - RDMA1 capture count */ + +#define VT1724_MT_SPDIF_CTRL 0x3c /* word */ +#define VT1724_MT_MONITOR_PEAKINDEX 0x3e /* byte */ +#define VT1724_MT_MONITOR_PEAKDATA 0x3f /* byte */ + +/* concurrent stereo channels */ +#define VT1724_MT_PDMA4_ADDR 0x40 /* dword */ +#define VT1724_MT_PDMA4_SIZE 0x44 /* word */ +#define VT1724_MT_PDMA4_COUNT 0x46 /* word */ +#define VT1724_MT_PDMA3_ADDR 0x50 /* dword */ +#define VT1724_MT_PDMA3_SIZE 0x54 /* word */ +#define VT1724_MT_PDMA3_COUNT 0x56 /* word */ +#define VT1724_MT_PDMA2_ADDR 0x60 /* dword */ +#define VT1724_MT_PDMA2_SIZE 0x64 /* word */ +#define VT1724_MT_PDMA2_COUNT 0x66 /* word */ +#define VT1724_MT_PDMA1_ADDR 0x70 /* dword */ +#define VT1724_MT_PDMA1_SIZE 0x74 /* word */ +#define VT1724_MT_PDMA1_COUNT 0x76 /* word */ + + +unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr); +void snd_vt1724_write_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr, unsigned char data); + +#endif /* __SOUND_VT1724_H */ -- cgit v1.2.3