From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- sound/soc/codecs/rk817_codec.c | 543 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 543 insertions(+) create mode 100644 sound/soc/codecs/rk817_codec.c (limited to 'sound/soc/codecs/rk817_codec.c') diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c new file mode 100644 index 000000000..2a5b274bf --- /dev/null +++ b/sound/soc/codecs/rk817_codec.c @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// rk817 ALSA SoC Audio driver +// +// Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct rk817_codec_priv { + struct snd_soc_component *component; + struct rk808 *rk808; + struct clk *mclk; + unsigned int stereo_sysclk; + bool mic_in_differential; +}; + +/* + * This sets the codec up with the values defined in the default implementation including the APLL + * from the Rockchip vendor kernel. I do not know if these values are universal despite differing + * from the default values defined above and taken from the datasheet, or implementation specific. + * I don't have another implementation to compare from the Rockchip sources. Hard-coding for now. + * Additionally, I do not know according to the documentation the units accepted for the clock + * values, so for the moment those are left unvalidated. + */ + +static int rk817_init(struct snd_soc_component *component) +{ + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + + snd_soc_component_write(component, RK817_CODEC_DDAC_POPD_DACST, 0x02); + snd_soc_component_write(component, RK817_CODEC_DDAC_SR_LMT0, 0x02); + snd_soc_component_write(component, RK817_CODEC_DADC_SR_ACL0, 0x02); + snd_soc_component_write(component, RK817_CODEC_DTOP_VUCTIME, 0xf4); + if (rk817->mic_in_differential) { + snd_soc_component_update_bits(component, RK817_CODEC_AMIC_CFG0, MIC_DIFF_MASK, + MIC_DIFF_EN); + } + + return 0; +} + +static int rk817_set_component_pll(struct snd_soc_component *component, + int pll_id, int source, unsigned int freq_in, + unsigned int freq_out) +{ + /* Set resistor value and charge pump current for PLL. */ + snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58); + /* Set the PLL feedback clock divide value (values not documented). */ + snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d); + /* Set the PLL pre-divide value (values not documented). */ + snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, 0x0c); + /* Set the PLL VCO output clock divide and PLL divided ratio of PLL High Clk (values not + * documented). + */ + snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5); + + return 0; +} + +/* + * DDAC/DADC L/R volume setting + * 0db~-95db, 0.375db/step, for example: + * 0x00: 0dB + * 0xff: -95dB + */ + +static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0); + +/* + * PGA GAIN L/R volume setting + * 27db~-18db, 3db/step, for example: + * 0x0: -18dB + * 0xf: 27dB + */ + +static const DECLARE_TLV_DB_MINMAX(rk817_gain_tlv, -1800, 2700); + +static const struct snd_kcontrol_new rk817_volume_controls[] = { + SOC_DOUBLE_R_RANGE_TLV("Master Playback Volume", RK817_CODEC_DDAC_VOLL, + RK817_CODEC_DDAC_VOLR, 0, 0x00, 0xff, 1, rk817_vol_tlv), + SOC_DOUBLE_R_RANGE_TLV("Master Capture Volume", RK817_CODEC_DADC_VOLL, + RK817_CODEC_DADC_VOLR, 0, 0x00, 0xff, 1, rk817_vol_tlv), + SOC_DOUBLE_TLV("Mic Capture Gain", RK817_CODEC_DMIC_PGA_GAIN, 4, 0, 0xf, 0, + rk817_gain_tlv), +}; + +/* Since the speaker output and L headphone pin are internally the same, make audio path mutually + * exclusive with a mux. + */ + +static const char *dac_mux_text[] = { + "HP", + "SPK", +}; + +static SOC_ENUM_SINGLE_VIRT_DECL(dac_enum, dac_mux_text); + +static const struct snd_kcontrol_new dac_mux = + SOC_DAPM_ENUM("Playback Mux", dac_enum); + +static const struct snd_soc_dapm_widget rk817_dapm_widgets[] = { + + /* capture/playback common */ + SND_SOC_DAPM_SUPPLY("LDO Regulator", RK817_CODEC_AREF_RTCFG1, 6, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("IBIAS Block", RK817_CODEC_AREF_RTCFG1, 2, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("VAvg Buffer", RK817_CODEC_AREF_RTCFG1, 1, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL Power", RK817_CODEC_APLL_CFG5, 0, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("I2S TX1 Transfer Start", RK817_CODEC_DI2S_RXCMD_TSD, 5, 0, NULL, 0), + + /* capture path common */ + SND_SOC_DAPM_SUPPLY("ADC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 7, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("I2S TX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 6, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 5, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("I2S TX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 4, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIC Power On", RK817_CODEC_AMIC_CFG0, 6, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("I2S TX3 Transfer Start", RK817_CODEC_DI2S_TXCR3_TXCMD, 7, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("I2S TX3 Right Justified", RK817_CODEC_DI2S_TXCR3_TXCMD, 3, 0, NULL, 0), + + /* capture path L */ + SND_SOC_DAPM_ADC("ADC L", "Capture", RK817_CODEC_AADC_CFG0, 7, 1), + SND_SOC_DAPM_SUPPLY("PGA L Power On", RK817_CODEC_AMIC_CFG0, 5, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("Mic Boost L1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Mic Boost L2", RK817_CODEC_AMIC_CFG0, 2, 0, NULL, 0), + + /* capture path R */ + SND_SOC_DAPM_ADC("ADC R", "Capture", RK817_CODEC_AADC_CFG0, 6, 1), + SND_SOC_DAPM_SUPPLY("PGA R Power On", RK817_CODEC_AMIC_CFG0, 4, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("Mic Boost R1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Mic Boost R2", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0), + + /* playback path common */ + SND_SOC_DAPM_SUPPLY("DAC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 3, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("I2S RX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("I2S RX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC Bias", RK817_CODEC_ADAC_CFG1, 3, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC Mute Off", RK817_CODEC_DDAC_MUTE_MIXCTL, 0, 1, NULL, 0), + + /* playback path speaker */ + SND_SOC_DAPM_SUPPLY("Class D Mode", RK817_CODEC_DDAC_MUTE_MIXCTL, 4, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("High Pass Filter", RK817_CODEC_DDAC_MUTE_MIXCTL, 7, 0, NULL, 0), + SND_SOC_DAPM_DAC("SPK DAC", "Playback", RK817_CODEC_ADAC_CFG1, 2, 1), + SND_SOC_DAPM_SUPPLY("Enable Class D", RK817_CODEC_ACLASSD_CFG1, 7, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Disable Class D Mute Ramp", RK817_CODEC_ACLASSD_CFG1, 6, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("Class D Mute Rate 1", RK817_CODEC_ACLASSD_CFG1, 3, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Class D Mute Rate 2", RK817_CODEC_ACLASSD_CFG1, 2, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("Class D OCPP 2", RK817_CODEC_ACLASSD_CFG2, 5, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Class D OCPP 3", RK817_CODEC_ACLASSD_CFG2, 4, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Class D OCPN 2", RK817_CODEC_ACLASSD_CFG2, 1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Class D OCPN 3", RK817_CODEC_ACLASSD_CFG2, 0, 0, NULL, 0), + + /* playback path headphones */ + SND_SOC_DAPM_SUPPLY("Headphone Charge Pump", RK817_CODEC_AHP_CP, 4, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Headphone CP Discharge LDO", RK817_CODEC_AHP_CP, 3, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("Headphone OStage", RK817_CODEC_AHP_CFG0, 6, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("Headphone Pre Amp", RK817_CODEC_AHP_CFG0, 5, 1, NULL, 0), + SND_SOC_DAPM_DAC("DAC L", "Playback", RK817_CODEC_ADAC_CFG1, 1, 1), + SND_SOC_DAPM_DAC("DAC R", "Playback", RK817_CODEC_ADAC_CFG1, 0, 1), + + /* Mux for input/output path selection */ + SND_SOC_DAPM_MUX("Playback Mux", SND_SOC_NOPM, 1, 0, &dac_mux), + + /* Pins for Simple Card Bindings */ + SND_SOC_DAPM_INPUT("MICL"), + SND_SOC_DAPM_INPUT("MICR"), + SND_SOC_DAPM_OUTPUT("HPOL"), + SND_SOC_DAPM_OUTPUT("HPOR"), + SND_SOC_DAPM_OUTPUT("SPKO"), +}; + +static const struct snd_soc_dapm_route rk817_dapm_routes[] = { + + /* capture path */ + /* left mic */ + {"ADC L", NULL, "LDO Regulator"}, + {"ADC L", NULL, "IBIAS Block"}, + {"ADC L", NULL, "VAvg Buffer"}, + {"ADC L", NULL, "PLL Power"}, + {"ADC L", NULL, "ADC Clock"}, + {"ADC L", NULL, "I2S TX Clock"}, + {"ADC L", NULL, "ADC Channel Enable"}, + {"ADC L", NULL, "I2S TX Channel Enable"}, + {"ADC L", NULL, "I2S TX1 Transfer Start"}, + {"MICL", NULL, "MIC Power On"}, + {"MICL", NULL, "PGA L Power On"}, + {"MICL", NULL, "Mic Boost L1"}, + {"MICL", NULL, "Mic Boost L2"}, + {"MICL", NULL, "I2S TX3 Transfer Start"}, + {"MICL", NULL, "I2S TX3 Right Justified"}, + {"ADC L", NULL, "MICL"}, + + /* right mic */ + {"ADC R", NULL, "LDO Regulator"}, + {"ADC R", NULL, "IBIAS Block"}, + {"ADC R", NULL, "VAvg Buffer"}, + {"ADC R", NULL, "PLL Power"}, + {"ADC R", NULL, "ADC Clock"}, + {"ADC R", NULL, "I2S TX Clock"}, + {"ADC R", NULL, "ADC Channel Enable"}, + {"ADC R", NULL, "I2S TX Channel Enable"}, + {"ADC R", NULL, "I2S TX1 Transfer Start"}, + {"MICR", NULL, "MIC Power On"}, + {"MICR", NULL, "PGA R Power On"}, + {"MICR", NULL, "Mic Boost R1"}, + {"MICR", NULL, "Mic Boost R2"}, + {"MICR", NULL, "I2S TX3 Transfer Start"}, + {"MICR", NULL, "I2S TX3 Right Justified"}, + {"ADC R", NULL, "MICR"}, + + /* playback path */ + /* speaker path */ + {"SPK DAC", NULL, "LDO Regulator"}, + {"SPK DAC", NULL, "IBIAS Block"}, + {"SPK DAC", NULL, "VAvg Buffer"}, + {"SPK DAC", NULL, "PLL Power"}, + {"SPK DAC", NULL, "I2S TX1 Transfer Start"}, + {"SPK DAC", NULL, "DAC Clock"}, + {"SPK DAC", NULL, "I2S RX Clock"}, + {"SPK DAC", NULL, "DAC Channel Enable"}, + {"SPK DAC", NULL, "I2S RX Channel Enable"}, + {"SPK DAC", NULL, "Class D Mode"}, + {"SPK DAC", NULL, "DAC Bias"}, + {"SPK DAC", NULL, "DAC Mute Off"}, + {"SPK DAC", NULL, "Enable Class D"}, + {"SPK DAC", NULL, "Disable Class D Mute Ramp"}, + {"SPK DAC", NULL, "Class D Mute Rate 1"}, + {"SPK DAC", NULL, "Class D Mute Rate 2"}, + {"SPK DAC", NULL, "Class D OCPP 2"}, + {"SPK DAC", NULL, "Class D OCPP 3"}, + {"SPK DAC", NULL, "Class D OCPN 2"}, + {"SPK DAC", NULL, "Class D OCPN 3"}, + {"SPK DAC", NULL, "High Pass Filter"}, + + /* headphone path L */ + {"DAC L", NULL, "LDO Regulator"}, + {"DAC L", NULL, "IBIAS Block"}, + {"DAC L", NULL, "VAvg Buffer"}, + {"DAC L", NULL, "PLL Power"}, + {"DAC L", NULL, "I2S TX1 Transfer Start"}, + {"DAC L", NULL, "DAC Clock"}, + {"DAC L", NULL, "I2S RX Clock"}, + {"DAC L", NULL, "DAC Channel Enable"}, + {"DAC L", NULL, "I2S RX Channel Enable"}, + {"DAC L", NULL, "DAC Bias"}, + {"DAC L", NULL, "DAC Mute Off"}, + {"DAC L", NULL, "Headphone Charge Pump"}, + {"DAC L", NULL, "Headphone CP Discharge LDO"}, + {"DAC L", NULL, "Headphone OStage"}, + {"DAC L", NULL, "Headphone Pre Amp"}, + + /* headphone path R */ + {"DAC R", NULL, "LDO Regulator"}, + {"DAC R", NULL, "IBIAS Block"}, + {"DAC R", NULL, "VAvg Buffer"}, + {"DAC R", NULL, "PLL Power"}, + {"DAC R", NULL, "I2S TX1 Transfer Start"}, + {"DAC R", NULL, "DAC Clock"}, + {"DAC R", NULL, "I2S RX Clock"}, + {"DAC R", NULL, "DAC Channel Enable"}, + {"DAC R", NULL, "I2S RX Channel Enable"}, + {"DAC R", NULL, "DAC Bias"}, + {"DAC R", NULL, "DAC Mute Off"}, + {"DAC R", NULL, "Headphone Charge Pump"}, + {"DAC R", NULL, "Headphone CP Discharge LDO"}, + {"DAC R", NULL, "Headphone OStage"}, + {"DAC R", NULL, "Headphone Pre Amp"}, + + /* mux path for output selection */ + {"Playback Mux", "HP", "DAC L"}, + {"Playback Mux", "HP", "DAC R"}, + {"Playback Mux", "SPK", "SPK DAC"}, + {"SPKO", NULL, "Playback Mux"}, + {"HPOL", NULL, "Playback Mux"}, + {"HPOR", NULL, "Playback Mux"}, +}; + +static int rk817_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_component *component = codec_dai->component; + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + + rk817->stereo_sysclk = freq; + + return 0; +} + +static int rk817_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_component *component = codec_dai->component; + unsigned int i2s_mst = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + i2s_mst |= RK817_I2S_MODE_SLV; + break; + case SND_SOC_DAIFMT_CBM_CFM: + i2s_mst |= RK817_I2S_MODE_MST; + break; + default: + dev_err(component->dev, "%s : set master mask failed!\n", __func__); + return -EINVAL; + } + + snd_soc_component_update_bits(component, RK817_CODEC_DI2S_CKM, + RK817_I2S_MODE_MASK, i2s_mst); + + return 0; +} + +static int rk817_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2, + VDW_RX_16BITS); + snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2, + VDW_TX_16BITS); + break; + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S32_LE: + snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2, + VDW_RX_24BITS); + snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2, + VDW_TX_24BITS); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk817_digital_mute(struct snd_soc_dai *dai, int mute, int stream) +{ + struct snd_soc_component *component = dai->component; + + if (mute) + snd_soc_component_update_bits(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + DACMT_MASK, DACMT_ENABLE); + else + snd_soc_component_update_bits(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + DACMT_MASK, DACMT_DISABLE); + + return 0; +} + +#define RK817_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ + SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_96000) + +#define RK817_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ + SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_96000) + +#define RK817_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dai_ops rk817_dai_ops = { + .hw_params = rk817_hw_params, + .set_fmt = rk817_set_dai_fmt, + .set_sysclk = rk817_set_dai_sysclk, + .mute_stream = rk817_digital_mute, + .no_capture_mute = 1, +}; + +static struct snd_soc_dai_driver rk817_dai[] = { + { + .name = "rk817-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 8, + .rates = RK817_PLAYBACK_RATES, + .formats = RK817_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RK817_CAPTURE_RATES, + .formats = RK817_FORMATS, + }, + .ops = &rk817_dai_ops, + }, +}; + +static int rk817_probe(struct snd_soc_component *component) +{ + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + struct rk808 *rk808 = dev_get_drvdata(component->dev->parent); + + snd_soc_component_init_regmap(component, rk808->regmap); + rk817->component = component; + + snd_soc_component_write(component, RK817_CODEC_DTOP_LPT_SRST, 0x40); + + rk817_init(component); + + /* setting initial pll values so that we can continue to leverage simple-audio-card. + * The values aren't important since no parameters are used. + */ + + snd_soc_component_set_pll(component, 0, 0, 0, 0); + + return 0; +} + +static void rk817_remove(struct snd_soc_component *component) +{ + snd_soc_component_exit_regmap(component); +} + +static const struct snd_soc_component_driver soc_codec_dev_rk817 = { + .probe = rk817_probe, + .remove = rk817_remove, + .idle_bias_on = 1, + .use_pmdown_time = 1, + .endianness = 1, + .controls = rk817_volume_controls, + .num_controls = ARRAY_SIZE(rk817_volume_controls), + .dapm_routes = rk817_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rk817_dapm_routes), + .dapm_widgets = rk817_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rk817_dapm_widgets), + .set_pll = rk817_set_component_pll, +}; + +static void rk817_codec_parse_dt_property(struct device *dev, + struct rk817_codec_priv *rk817) +{ + struct device_node *node; + + node = of_get_child_by_name(dev->parent->of_node, "codec"); + if (!node) { + dev_dbg(dev, "%s() Can not get child: codec\n", + __func__); + } + + rk817->mic_in_differential = + of_property_read_bool(node, "rockchip,mic-in-differential"); + + of_node_put(node); +} + +static int rk817_platform_probe(struct platform_device *pdev) +{ + struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent); + struct rk817_codec_priv *rk817_codec_data; + int ret; + + rk817_codec_data = devm_kzalloc(&pdev->dev, + sizeof(struct rk817_codec_priv), + GFP_KERNEL); + if (!rk817_codec_data) + return -ENOMEM; + + platform_set_drvdata(pdev, rk817_codec_data); + + rk817_codec_data->rk808 = rk808; + + rk817_codec_parse_dt_property(&pdev->dev, rk817_codec_data); + + rk817_codec_data->mclk = devm_clk_get(pdev->dev.parent, "mclk"); + if (IS_ERR(rk817_codec_data->mclk)) { + dev_dbg(&pdev->dev, "Unable to get mclk\n"); + ret = -ENXIO; + goto err_; + } + + ret = clk_prepare_enable(rk817_codec_data->mclk); + if (ret < 0) { + dev_err(&pdev->dev, "%s() clock prepare error %d\n", + __func__, ret); + goto err_; + } + + ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk817, + rk817_dai, ARRAY_SIZE(rk817_dai)); + if (ret < 0) { + dev_err(&pdev->dev, "%s() register codec error %d\n", + __func__, ret); + goto err_clk; + } + + return 0; + +err_clk: + clk_disable_unprepare(rk817_codec_data->mclk); +err_: + return ret; +} + +static int rk817_platform_remove(struct platform_device *pdev) +{ + struct rk817_codec_priv *rk817 = platform_get_drvdata(pdev); + + clk_disable_unprepare(rk817->mclk); + + return 0; +} + +static struct platform_driver rk817_codec_driver = { + .driver = { + .name = "rk817-codec", + }, + .probe = rk817_platform_probe, + .remove = rk817_platform_remove, +}; + +module_platform_driver(rk817_codec_driver); + +MODULE_DESCRIPTION("ASoC RK817 codec driver"); +MODULE_AUTHOR("binyuan "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:rk817-codec"); -- cgit v1.2.3