From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- sound/soc/codecs/rt1015.h | 449 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 449 insertions(+) create mode 100644 sound/soc/codecs/rt1015.h (limited to 'sound/soc/codecs/rt1015.h') diff --git a/sound/soc/codecs/rt1015.h b/sound/soc/codecs/rt1015.h new file mode 100644 index 000000000..c9f636af7 --- /dev/null +++ b/sound/soc/codecs/rt1015.h @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// rt1015.h -- RT1015 ALSA SoC audio amplifier driver +// +// Copyright 2019 Realtek Semiconductor Corp. +// Author: Jack Yu +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation. +// + +#ifndef __RT1015_H__ +#define __RT1015_H__ +#include + +#define RT1015_DEVICE_ID_VAL 0x1011 +#define RT1015_DEVICE_ID_VAL2 0x1015 + +#define RT1015_RESET 0x0000 +#define RT1015_CLK2 0x0004 +#define RT1015_CLK3 0x0006 +#define RT1015_PLL1 0x000a +#define RT1015_PLL2 0x000c +#define RT1015_DUM_RW1 0x000e +#define RT1015_DUM_RW2 0x0010 +#define RT1015_DUM_RW3 0x0012 +#define RT1015_DUM_RW4 0x0014 +#define RT1015_DUM_RW5 0x0016 +#define RT1015_DUM_RW6 0x0018 +#define RT1015_CLK_DET 0x0020 +#define RT1015_SIL_DET 0x0022 +#define RT1015_CUSTOMER_ID 0x0076 +#define RT1015_PCODE_FWVER 0x0078 +#define RT1015_VER_ID 0x007a +#define RT1015_VENDOR_ID 0x007c +#define RT1015_DEVICE_ID 0x007d +#define RT1015_PAD_DRV1 0x00f0 +#define RT1015_PAD_DRV2 0x00f2 +#define RT1015_GAT_BOOST 0x00f3 +#define RT1015_PRO_ALT 0x00f4 +#define RT1015_OSCK_STA 0x00f6 +#define RT1015_MAN_I2C 0x0100 +#define RT1015_DAC1 0x0102 +#define RT1015_DAC2 0x0104 +#define RT1015_DAC3 0x0106 +#define RT1015_ADC1 0x010c +#define RT1015_ADC2 0x010e +#define RT1015_TDM_MASTER 0x0111 +#define RT1015_TDM_TCON 0x0112 +#define RT1015_TDM1_1 0x0114 +#define RT1015_TDM1_2 0x0116 +#define RT1015_TDM1_3 0x0118 +#define RT1015_TDM1_4 0x011a +#define RT1015_TDM1_5 0x011c +#define RT1015_MIXER1 0x0300 +#define RT1015_MIXER2 0x0302 +#define RT1015_ANA_PROTECT1 0x0311 +#define RT1015_ANA_CTRL_SEQ1 0x0313 +#define RT1015_ANA_CTRL_SEQ2 0x0314 +#define RT1015_VBAT_DET_DEB 0x031a +#define RT1015_VBAT_VOLT_DET1 0x031c +#define RT1015_VBAT_VOLT_DET2 0x031d +#define RT1015_VBAT_TEST_OUT1 0x031e +#define RT1015_VBAT_TEST_OUT2 0x031f +#define RT1015_VBAT_PROT_ATT 0x0320 +#define RT1015_VBAT_DET_CODE 0x0321 +#define RT1015_PWR1 0x0322 +#define RT1015_PWR4 0x0328 +#define RT1015_PWR5 0x0329 +#define RT1015_PWR6 0x032a +#define RT1015_PWR7 0x032b +#define RT1015_PWR8 0x032c +#define RT1015_PWR9 0x032d +#define RT1015_CLASSD_SEQ 0x032e +#define RT1015_SMART_BST_CTRL1 0x0330 +#define RT1015_SMART_BST_CTRL2 0x0332 +#define RT1015_ANA_CTRL1 0x0334 +#define RT1015_ANA_CTRL2 0x0336 +#define RT1015_PWR_STATE_CTRL 0x0338 +#define RT1015_MONO_DYNA_CTRL 0x04fa +#define RT1015_MONO_DYNA_CTRL1 0x04fc +#define RT1015_MONO_DYNA_CTRL2 0x04fe +#define RT1015_MONO_DYNA_CTRL3 0x0500 +#define RT1015_MONO_DYNA_CTRL4 0x0502 +#define RT1015_MONO_DYNA_CTRL5 0x0504 +#define RT1015_SPK_VOL 0x0506 +#define RT1015_SHORT_DETTOP1 0x0508 +#define RT1015_SHORT_DETTOP2 0x050a +#define RT1015_SPK_DC_DETECT1 0x0519 +#define RT1015_SPK_DC_DETECT2 0x051a +#define RT1015_SPK_DC_DETECT3 0x051b +#define RT1015_SPK_DC_DETECT4 0x051d +#define RT1015_SPK_DC_DETECT5 0x051f +#define RT1015_BAT_RPO_STEP1 0x0536 +#define RT1015_BAT_RPO_STEP2 0x0538 +#define RT1015_BAT_RPO_STEP3 0x053a +#define RT1015_BAT_RPO_STEP4 0x053c +#define RT1015_BAT_RPO_STEP5 0x053d +#define RT1015_BAT_RPO_STEP6 0x053e +#define RT1015_BAT_RPO_STEP7 0x053f +#define RT1015_BAT_RPO_STEP8 0x0540 +#define RT1015_BAT_RPO_STEP9 0x0541 +#define RT1015_BAT_RPO_STEP10 0x0542 +#define RT1015_BAT_RPO_STEP11 0x0543 +#define RT1015_BAT_RPO_STEP12 0x0544 +#define RT1015_SPREAD_SPEC1 0x0568 +#define RT1015_SPREAD_SPEC2 0x056a +#define RT1015_PAD_STATUS 0x1000 +#define RT1015_PADS_PULLING_CTRL1 0x1002 +#define RT1015_PADS_DRIVING 0x1006 +#define RT1015_SYS_RST1 0x1007 +#define RT1015_SYS_RST2 0x1009 +#define RT1015_SYS_GATING1 0x100a +#define RT1015_TEST_MODE1 0x100c +#define RT1015_TEST_MODE2 0x100d +#define RT1015_TIMING_CTRL1 0x100e +#define RT1015_PLL_INT 0x1010 +#define RT1015_TEST_OUT1 0x1020 +#define RT1015_DC_CALIB_CLSD1 0x1200 +#define RT1015_DC_CALIB_CLSD2 0x1202 +#define RT1015_DC_CALIB_CLSD3 0x1204 +#define RT1015_DC_CALIB_CLSD4 0x1206 +#define RT1015_DC_CALIB_CLSD5 0x1208 +#define RT1015_DC_CALIB_CLSD6 0x120a +#define RT1015_DC_CALIB_CLSD7 0x120c +#define RT1015_DC_CALIB_CLSD8 0x120e +#define RT1015_DC_CALIB_CLSD9 0x1210 +#define RT1015_DC_CALIB_CLSD10 0x1212 +#define RT1015_CLSD_INTERNAL1 0x1300 +#define RT1015_CLSD_INTERNAL2 0x1302 +#define RT1015_CLSD_INTERNAL3 0x1304 +#define RT1015_CLSD_INTERNAL4 0x1305 +#define RT1015_CLSD_INTERNAL5 0x1306 +#define RT1015_CLSD_INTERNAL6 0x1308 +#define RT1015_CLSD_INTERNAL7 0x130a +#define RT1015_CLSD_INTERNAL8 0x130c +#define RT1015_CLSD_INTERNAL9 0x130e +#define RT1015_CLSD_OCP_CTRL 0x130f +#define RT1015_VREF_LV 0x1310 +#define RT1015_MBIAS1 0x1312 +#define RT1015_MBIAS2 0x1314 +#define RT1015_MBIAS3 0x1316 +#define RT1015_MBIAS4 0x1318 +#define RT1015_VREF_LV1 0x131a +#define RT1015_S_BST_TIMING_INTER1 0x1322 +#define RT1015_S_BST_TIMING_INTER2 0x1323 +#define RT1015_S_BST_TIMING_INTER3 0x1324 +#define RT1015_S_BST_TIMING_INTER4 0x1325 +#define RT1015_S_BST_TIMING_INTER5 0x1326 +#define RT1015_S_BST_TIMING_INTER6 0x1327 +#define RT1015_S_BST_TIMING_INTER7 0x1328 +#define RT1015_S_BST_TIMING_INTER8 0x1329 +#define RT1015_S_BST_TIMING_INTER9 0x132a +#define RT1015_S_BST_TIMING_INTER10 0x132b +#define RT1015_S_BST_TIMING_INTER11 0x1330 +#define RT1015_S_BST_TIMING_INTER12 0x1331 +#define RT1015_S_BST_TIMING_INTER13 0x1332 +#define RT1015_S_BST_TIMING_INTER14 0x1333 +#define RT1015_S_BST_TIMING_INTER15 0x1334 +#define RT1015_S_BST_TIMING_INTER16 0x1335 +#define RT1015_S_BST_TIMING_INTER17 0x1336 +#define RT1015_S_BST_TIMING_INTER18 0x1337 +#define RT1015_S_BST_TIMING_INTER19 0x1338 +#define RT1015_S_BST_TIMING_INTER20 0x1339 +#define RT1015_S_BST_TIMING_INTER21 0x133a +#define RT1015_S_BST_TIMING_INTER22 0x133b +#define RT1015_S_BST_TIMING_INTER23 0x133c +#define RT1015_S_BST_TIMING_INTER24 0x133d +#define RT1015_S_BST_TIMING_INTER25 0x133e +#define RT1015_S_BST_TIMING_INTER26 0x133f +#define RT1015_S_BST_TIMING_INTER27 0x1340 +#define RT1015_S_BST_TIMING_INTER28 0x1341 +#define RT1015_S_BST_TIMING_INTER29 0x1342 +#define RT1015_S_BST_TIMING_INTER30 0x1343 +#define RT1015_S_BST_TIMING_INTER31 0x1344 +#define RT1015_S_BST_TIMING_INTER32 0x1345 +#define RT1015_S_BST_TIMING_INTER33 0x1346 +#define RT1015_S_BST_TIMING_INTER34 0x1347 +#define RT1015_S_BST_TIMING_INTER35 0x1348 +#define RT1015_S_BST_TIMING_INTER36 0x1349 + +/* 0x0004 */ +#define RT1015_CLK_SYS_PRE_SEL_MASK (0x3 << 14) +#define RT1015_CLK_SYS_PRE_SEL_SFT 14 +#define RT1015_CLK_SYS_PRE_SEL_MCLK (0x0 << 14) +#define RT1015_CLK_SYS_PRE_SEL_PLL (0x2 << 14) +#define RT1015_PLL_SEL_MASK (0x1 << 13) +#define RT1015_PLL_SEL_SFT 13 +#define RT1015_PLL_SEL_PLL_SRC2 (0x0 << 13) +#define RT1015_PLL_SEL_BCLK (0x1 << 13) +#define RT1015_FS_PD_MASK (0x7 << 4) +#define RT1015_FS_PD_SFT 4 + +/* 0x000a */ +#define RT1015_PLL_M_MAX 0xf +#define RT1015_PLL_M_MASK (RT1015_PLL_M_MAX << 12) +#define RT1015_PLL_M_SFT 12 +#define RT1015_PLL_M_BP (0x1 << 11) +#define RT1015_PLL_M_BP_SFT 11 +#define RT1015_PLL_N_MAX 0x1ff +#define RT1015_PLL_N_MASK (RT1015_PLL_N_MAX << 0) +#define RT1015_PLL_N_SFT 0 + +/* 0x000c */ +#define RT1015_PLL_BPK_MASK (0x1 << 5) +#define RT1015_PLL_BPK (0x0 << 5) +#define RT1015_PLL_K_MAX 0x1f +#define RT1015_PLL_K_MASK (RT1015_PLL_K_MAX) +#define RT1015_PLL_K_SFT 0 + +/* 0x0020 */ +#define RT1015_EN_BCLK_DET_MASK (0x1 << 15) +#define RT1015_EN_BCLK_DET (0x1 << 15) +#define RT1015_DIS_BCLK_DET (0x0 << 15) + +/* 0x007a */ +#define RT1015_ID_MASK 0xff +#define RT1015_ID_VERA 0x0 +#define RT1015_ID_VERB 0x1 + +/* 0x00f2 */ +#define RT1015_MONO_LR_SEL_MASK (0x3 << 4) +#define RT1015_MONO_L_CHANNEL (0x0 << 4) +#define RT1015_MONO_R_CHANNEL (0x1 << 4) +#define RT1015_MONO_LR_MIX_CHANNEL (0x2 << 4) + +/* 0x0102 */ +#define RT1015_DAC_VOL_MASK (0x7f << 9) +#define RT1015_DAC_VOL_SFT 9 + +/* 0x0104 */ +#define RT1015_DAC_CLK (0x1 << 13) +#define RT1015_DAC_CLK_BIT 13 + +/* 0x0106 */ +#define RT1015_DAC_MUTE_MASK (0x1 << 15) +#define RT1015_DA_MUTE_SFT 15 +#define RT1015_DVOL_MUTE_FLAG_SFT 12 + +/* 0x0111 */ +#define RT1015_TCON_TDM_MS_MASK (0x1 << 14) +#define RT1015_TCON_TDM_MS_SFT 14 +#define RT1015_TCON_TDM_MS_S (0x0 << 14) +#define RT1015_TCON_TDM_MS_M (0x1 << 14) +#define RT1015_I2S_DL_MASK (0x7 << 8) +#define RT1015_I2S_DL_SFT 8 +#define RT1015_I2S_DL_16 (0x0 << 8) +#define RT1015_I2S_DL_20 (0x1 << 8) +#define RT1015_I2S_DL_24 (0x2 << 8) +#define RT1015_I2S_DL_8 (0x3 << 8) +#define RT1015_I2S_M_DF_MASK (0x7 << 0) +#define RT1015_I2S_M_DF_SFT 0 +#define RT1015_I2S_M_DF_I2S (0x0) +#define RT1015_I2S_M_DF_LEFT (0x1) +#define RT1015_I2S_M_DF_PCM_A (0x2) +#define RT1015_I2S_M_DF_PCM_B (0x3) +#define RT1015_I2S_M_DF_PCM_A_N (0x6) +#define RT1015_I2S_M_DF_PCM_B_N (0x7) + +/* TDM_tcon Setting (0x0112) */ +#define RT1015_I2S_TCON_DF_MASK (0x7 << 13) +#define RT1015_I2S_TCON_DF_SFT 13 +#define RT1015_I2S_TCON_DF_I2S (0x0 << 13) +#define RT1015_I2S_TCON_DF_LEFT (0x1 << 13) +#define RT1015_I2S_TCON_DF_PCM_A (0x2 << 13) +#define RT1015_I2S_TCON_DF_PCM_B (0x3 << 13) +#define RT1015_I2S_TCON_DF_PCM_A_N (0x6 << 13) +#define RT1015_I2S_TCON_DF_PCM_B_N (0x7 << 13) +#define RT1015_TCON_BCLK_SEL_MASK (0x3 << 10) +#define RT1015_TCON_BCLK_SEL_SFT 10 +#define RT1015_TCON_BCLK_SEL_32FS (0x0 << 10) +#define RT1015_TCON_BCLK_SEL_64FS (0x1 << 10) +#define RT1015_TCON_BCLK_SEL_128FS (0x2 << 10) +#define RT1015_TCON_BCLK_SEL_256FS (0x3 << 10) +#define RT1015_TCON_CH_LEN_MASK (0x3 << 5) +#define RT1015_TCON_CH_LEN_SFT 5 +#define RT1015_TCON_CH_LEN_16B (0x0 << 5) +#define RT1015_TCON_CH_LEN_20B (0x1 << 5) +#define RT1015_TCON_CH_LEN_24B (0x2 << 5) +#define RT1015_TCON_CH_LEN_32B (0x3 << 5) +#define RT1015_TCON_BCLK_MST_MASK (0x1 << 4) +#define RT1015_TCON_BCLK_MST_SFT 4 +#define RT1015_TCON_BCLK_MST_INV (0x1 << 4) + +/* TDM1 Setting-1 (0x0114) */ +#define RT1015_TDM_INV_BCLK_MASK (0x1 << 15) +#define RT1015_TDM_INV_BCLK_SFT 15 +#define RT1015_TDM_INV_BCLK (0x1 << 15) +#define RT1015_I2S_CH_TX_MASK (0x3 << 10) +#define RT1015_I2S_CH_TX_SFT 10 +#define RT1015_I2S_TX_2CH (0x0 << 10) +#define RT1015_I2S_TX_4CH (0x1 << 10) +#define RT1015_I2S_TX_6CH (0x2 << 10) +#define RT1015_I2S_TX_8CH (0x3 << 10) +#define RT1015_I2S_CH_RX_MASK (0x3 << 8) +#define RT1015_I2S_CH_RX_SFT 8 +#define RT1015_I2S_RX_2CH (0x0 << 8) +#define RT1015_I2S_RX_4CH (0x1 << 8) +#define RT1015_I2S_RX_6CH (0x2 << 8) +#define RT1015_I2S_RX_8CH (0x3 << 8) +#define RT1015_I2S_LR_CH_SEL_MASK (0x1 << 7) +#define RT1015_I2S_LR_CH_SEL_SFT 7 +#define RT1015_I2S_LEFT_CH_SEL (0x0 << 7) +#define RT1015_I2S_RIGHT_CH_SEL (0x1 << 7) +#define RT1015_I2S_CH_TX_LEN_MASK (0x7 << 4) +#define RT1015_I2S_CH_TX_LEN_SFT 4 +#define RT1015_I2S_CH_TX_LEN_16B (0x0 << 4) +#define RT1015_I2S_CH_TX_LEN_20B (0x1 << 4) +#define RT1015_I2S_CH_TX_LEN_24B (0x2 << 4) +#define RT1015_I2S_CH_TX_LEN_32B (0x3 << 4) +#define RT1015_I2S_CH_TX_LEN_8B (0x4 << 4) +#define RT1015_I2S_CH_RX_LEN_MASK (0x7 << 0) +#define RT1015_I2S_CH_RX_LEN_SFT 0 +#define RT1015_I2S_CH_RX_LEN_16B (0x0 << 0) +#define RT1015_I2S_CH_RX_LEN_20B (0x1 << 0) +#define RT1015_I2S_CH_RX_LEN_24B (0x2 << 0) +#define RT1015_I2S_CH_RX_LEN_32B (0x3 << 0) +#define RT1015_I2S_CH_RX_LEN_8B (0x4 << 0) + +/* TDM1 Setting-4 (0x011a) */ +#define RT1015_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 12) +#define RT1015_TDM_I2S_TX_R_DAC1_1_MASK (0x7 << 8) +#define RT1015_TDM_I2S_TX_L_DAC1_1_SFT 12 +#define RT1015_TDM_I2S_TX_R_DAC1_1_SFT 8 + +/* 0x0330 */ +#define RT1015_ABST_AUTO_EN_MASK (0x1 << 13) +#define RT1015_ABST_AUTO_MODE (0x1 << 13) +#define RT1015_ABST_REG_MODE (0x0 << 13) +#define RT1015_ABST_FIX_TGT_MASK (0x1 << 12) +#define RT1015_ABST_FIX_TGT_EN (0x1 << 12) +#define RT1015_ABST_FIX_TGT_DIS (0x0 << 12) +#define RT1015_BYPASS_SWR_REG_MASK (0x1 << 7) +#define RT1015_BYPASS_SWRREG_BYPASS (0x1 << 7) +#define RT1015_BYPASS_SWRREG_PASS (0x0 << 7) + +/* 0x0322 */ +#define RT1015_PWR_LDO2 (0x1 << 15) +#define RT1015_PWR_LDO2_BIT 15 +#define RT1015_PWR_DAC (0x1 << 14) +#define RT1015_PWR_DAC_BIT 14 +#define RT1015_PWR_INTCLK (0x1 << 13) +#define RT1015_PWR_INTCLK_BIT 13 +#define RT1015_PWR_ISENSE (0x1 << 12) +#define RT1015_PWR_ISENSE_BIT 12 +#define RT1015_PWR_VSENSE (0x1 << 10) +#define RT1015_PWR_VSENSE_BIT 10 +#define RT1015_PWR_PLL (0x1 << 9) +#define RT1015_PWR_PLL_BIT 9 +#define RT1015_PWR_BG_1_2 (0x1 << 8) +#define RT1015_PWR_BG_1_2_BIT 8 +#define RT1015_PWR_MBIAS_BG (0x1 << 7) +#define RT1015_PWR_MBIAS_BG_BIT 7 +#define RT1015_PWR_VBAT (0x1 << 6) +#define RT1015_PWR_VBAT_BIT 6 +#define RT1015_PWR_MBIAS (0x1 << 4) +#define RT1015_PWR_MBIAS_BIT 4 +#define RT1015_PWR_ADCV (0x1 << 3) +#define RT1015_PWR_ADCV_BIT 3 +#define RT1015_PWR_MIXERV (0x1 << 2) +#define RT1015_PWR_MIXERV_BIT 2 +#define RT1015_PWR_SUMV (0x1 << 1) +#define RT1015_PWR_SUMV_BIT 1 +#define RT1015_PWR_VREFLV (0x1 << 0) +#define RT1015_PWR_VREFLV_BIT 0 + +/* 0x0324 */ +#define RT1015_PWR_BASIC (0x1 << 15) +#define RT1015_PWR_BASIC_BIT 15 +#define RT1015_PWR_SD (0x1 << 14) +#define RT1015_PWR_SD_BIT 14 +#define RT1015_PWR_IBIAS (0x1 << 13) +#define RT1015_PWR_IBIAS_BIT 13 +#define RT1015_PWR_VCM (0x1 << 11) +#define RT1015_PWR_VCM_BIT 11 + +/* 0x0328 */ +#define RT1015_PWR_SWR (0x1 << 12) +#define RT1015_PWR_SWR_BIT 12 + +/* 0x0519 */ +#define RT1015_EN_CLA_D_DC_DET_MASK (0x1 << 12) +#define RT1015_EN_CLA_D_DC_DET (0x1 << 12) +#define RT1015_DIS_CLA_D_DC_DET (0x0 << 12) + +/* 0x1300 */ +#define RT1015_PWR_CLSD (0x1 << 12) +#define RT1015_PWR_CLSD_BIT 12 + +/* 0x007a */ +#define RT1015_ID_MASK 0xff +#define RT1015_ID_VERA 0x0 +#define RT1015_ID_VERB 0x1 + +/* System Clock Source */ +enum { + RT1015_SCLK_S_MCLK, + RT1015_SCLK_S_PLL, +}; + +/* PLL1 Source */ +enum { + RT1015_PLL_S_MCLK, + RT1015_PLL_S_BCLK, +}; + +enum { + RT1015_AIF1, + RT1015_AIFS, +}; + +enum { + RT1015_VERA, + RT1015_VERB, +}; + +enum { + BYPASS, + ADAPTIVE, + FIXED_ADAPTIVE, +}; + +enum { + RT1015_Enable_Boost = 0, + RT1015_Bypass_Boost, +}; + +enum { + RT1015_HW_28 = 0, + RT1015_HW_29, +}; + +struct rt1015_priv { + struct snd_soc_component *component; + struct rt1015_platform_data pdata; + struct regmap *regmap; + int sysclk; + int sysclk_src; + int pll_src; + int pll_in; + int pll_out; + int boost_mode; + int bypass_boost; + int dac_is_used; + int cali_done; +}; + +#endif /* __RT1015_H__ */ -- cgit v1.2.3