From 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 21 Feb 2023 18:24:12 -0800 Subject: Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ... --- sound/soc/xilinx/xlnx_formatter_pcm.c | 726 ++++++++++++++++++++++++++++++++++ 1 file changed, 726 insertions(+) create mode 100644 sound/soc/xilinx/xlnx_formatter_pcm.c (limited to 'sound/soc/xilinx/xlnx_formatter_pcm.c') diff --git a/sound/soc/xilinx/xlnx_formatter_pcm.c b/sound/soc/xilinx/xlnx_formatter_pcm.c new file mode 100644 index 000000000..ff1fe62fe --- /dev/null +++ b/sound/soc/xilinx/xlnx_formatter_pcm.c @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Xilinx ASoC audio formatter support +// +// Copyright (C) 2018 Xilinx, Inc. +// +// Author: Maruthi Srinivas Bayyavarapu + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DRV_NAME "xlnx_formatter_pcm" + +#define XLNX_S2MM_OFFSET 0 +#define XLNX_MM2S_OFFSET 0x100 + +#define XLNX_AUD_CORE_CONFIG 0x4 +#define XLNX_AUD_CTRL 0x10 +#define XLNX_AUD_STS 0x14 + +#define AUD_CTRL_RESET_MASK BIT(1) +#define AUD_CFG_MM2S_MASK BIT(15) +#define AUD_CFG_S2MM_MASK BIT(31) + +#define XLNX_AUD_FS_MULTIPLIER 0x18 +#define XLNX_AUD_PERIOD_CONFIG 0x1C +#define XLNX_AUD_BUFF_ADDR_LSB 0x20 +#define XLNX_AUD_BUFF_ADDR_MSB 0x24 +#define XLNX_AUD_XFER_COUNT 0x28 +#define XLNX_AUD_CH_STS_START 0x2C +#define XLNX_BYTES_PER_CH 0x44 +#define XLNX_AUD_ALIGN_BYTES 64 + +#define AUD_STS_IOC_IRQ_MASK BIT(31) +#define AUD_STS_CH_STS_MASK BIT(29) +#define AUD_CTRL_IOC_IRQ_MASK BIT(13) +#define AUD_CTRL_TOUT_IRQ_MASK BIT(14) +#define AUD_CTRL_DMA_EN_MASK BIT(0) + +#define CFG_MM2S_CH_MASK GENMASK(11, 8) +#define CFG_MM2S_CH_SHIFT 8 +#define CFG_MM2S_XFER_MASK GENMASK(14, 13) +#define CFG_MM2S_XFER_SHIFT 13 +#define CFG_MM2S_PKG_MASK BIT(12) + +#define CFG_S2MM_CH_MASK GENMASK(27, 24) +#define CFG_S2MM_CH_SHIFT 24 +#define CFG_S2MM_XFER_MASK GENMASK(30, 29) +#define CFG_S2MM_XFER_SHIFT 29 +#define CFG_S2MM_PKG_MASK BIT(28) + +#define AUD_CTRL_DATA_WIDTH_SHIFT 16 +#define AUD_CTRL_ACTIVE_CH_SHIFT 19 +#define PERIOD_CFG_PERIODS_SHIFT 16 + +#define PERIODS_MIN 2 +#define PERIODS_MAX 6 +#define PERIOD_BYTES_MIN 192 +#define PERIOD_BYTES_MAX (50 * 1024) +#define XLNX_PARAM_UNKNOWN 0 + +enum bit_depth { + BIT_DEPTH_8, + BIT_DEPTH_16, + BIT_DEPTH_20, + BIT_DEPTH_24, + BIT_DEPTH_32, +}; + +struct xlnx_pcm_drv_data { + void __iomem *mmio; + bool s2mm_presence; + bool mm2s_presence; + int s2mm_irq; + int mm2s_irq; + struct snd_pcm_substream *play_stream; + struct snd_pcm_substream *capture_stream; + struct clk *axi_clk; + unsigned int sysclk; +}; + +/* + * struct xlnx_pcm_stream_param - stream configuration + * @mmio: base address offset + * @interleaved: audio channels arrangement in buffer + * @xfer_mode: data formatting mode during transfer + * @ch_limit: Maximum channels supported + * @buffer_size: stream ring buffer size + */ +struct xlnx_pcm_stream_param { + void __iomem *mmio; + bool interleaved; + u32 xfer_mode; + u32 ch_limit; + u64 buffer_size; +}; + +static const struct snd_pcm_hardware xlnx_pcm_hardware = { + .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_BATCH | SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .rate_min = 8000, + .rate_max = 192000, + .buffer_bytes_max = PERIODS_MAX * PERIOD_BYTES_MAX, + .period_bytes_min = PERIOD_BYTES_MIN, + .period_bytes_max = PERIOD_BYTES_MAX, + .periods_min = PERIODS_MIN, + .periods_max = PERIODS_MAX, +}; + +enum { + AES_TO_AES, + AES_TO_PCM, + PCM_TO_PCM, + PCM_TO_AES +}; + +static void xlnx_parse_aes_params(u32 chsts_reg1_val, u32 chsts_reg2_val, + struct device *dev) +{ + u32 padded, srate, bit_depth, status[2]; + + if (chsts_reg1_val & IEC958_AES0_PROFESSIONAL) { + status[0] = chsts_reg1_val & 0xff; + status[1] = (chsts_reg1_val >> 16) & 0xff; + + switch (status[0] & IEC958_AES0_PRO_FS) { + case IEC958_AES0_PRO_FS_44100: + srate = 44100; + break; + case IEC958_AES0_PRO_FS_48000: + srate = 48000; + break; + case IEC958_AES0_PRO_FS_32000: + srate = 32000; + break; + case IEC958_AES0_PRO_FS_NOTID: + default: + srate = XLNX_PARAM_UNKNOWN; + break; + } + + switch (status[1] & IEC958_AES2_PRO_SBITS) { + case IEC958_AES2_PRO_WORDLEN_NOTID: + case IEC958_AES2_PRO_SBITS_20: + padded = 0; + break; + case IEC958_AES2_PRO_SBITS_24: + padded = 4; + break; + default: + bit_depth = XLNX_PARAM_UNKNOWN; + goto log_params; + } + + switch (status[1] & IEC958_AES2_PRO_WORDLEN) { + case IEC958_AES2_PRO_WORDLEN_20_16: + bit_depth = 16 + padded; + break; + case IEC958_AES2_PRO_WORDLEN_22_18: + bit_depth = 18 + padded; + break; + case IEC958_AES2_PRO_WORDLEN_23_19: + bit_depth = 19 + padded; + break; + case IEC958_AES2_PRO_WORDLEN_24_20: + bit_depth = 20 + padded; + break; + case IEC958_AES2_PRO_WORDLEN_NOTID: + default: + bit_depth = XLNX_PARAM_UNKNOWN; + break; + } + + } else { + status[0] = (chsts_reg1_val >> 24) & 0xff; + status[1] = chsts_reg2_val & 0xff; + + switch (status[0] & IEC958_AES3_CON_FS) { + case IEC958_AES3_CON_FS_44100: + srate = 44100; + break; + case IEC958_AES3_CON_FS_48000: + srate = 48000; + break; + case IEC958_AES3_CON_FS_32000: + srate = 32000; + break; + default: + srate = XLNX_PARAM_UNKNOWN; + break; + } + + if (status[1] & IEC958_AES4_CON_MAX_WORDLEN_24) + padded = 4; + else + padded = 0; + + switch (status[1] & IEC958_AES4_CON_WORDLEN) { + case IEC958_AES4_CON_WORDLEN_20_16: + bit_depth = 16 + padded; + break; + case IEC958_AES4_CON_WORDLEN_22_18: + bit_depth = 18 + padded; + break; + case IEC958_AES4_CON_WORDLEN_23_19: + bit_depth = 19 + padded; + break; + case IEC958_AES4_CON_WORDLEN_24_20: + bit_depth = 20 + padded; + break; + case IEC958_AES4_CON_WORDLEN_21_17: + bit_depth = 17 + padded; + break; + case IEC958_AES4_CON_WORDLEN_NOTID: + default: + bit_depth = XLNX_PARAM_UNKNOWN; + break; + } + } + +log_params: + if (srate != XLNX_PARAM_UNKNOWN) + dev_info(dev, "sample rate = %d\n", srate); + else + dev_info(dev, "sample rate = unknown\n"); + + if (bit_depth != XLNX_PARAM_UNKNOWN) + dev_info(dev, "bit_depth = %d\n", bit_depth); + else + dev_info(dev, "bit_depth = unknown\n"); +} + +static int xlnx_formatter_pcm_reset(void __iomem *mmio_base) +{ + u32 val, retries = 0; + + val = readl(mmio_base + XLNX_AUD_CTRL); + val |= AUD_CTRL_RESET_MASK; + writel(val, mmio_base + XLNX_AUD_CTRL); + + val = readl(mmio_base + XLNX_AUD_CTRL); + /* Poll for maximum timeout of approximately 100ms (1 * 100)*/ + while ((val & AUD_CTRL_RESET_MASK) && (retries < 100)) { + mdelay(1); + retries++; + val = readl(mmio_base + XLNX_AUD_CTRL); + } + if (val & AUD_CTRL_RESET_MASK) + return -ENODEV; + + return 0; +} + +static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream) +{ + u32 val; + + val = readl(mmio_base + XLNX_AUD_CTRL); + val &= ~AUD_CTRL_IOC_IRQ_MASK; + if (stream == SNDRV_PCM_STREAM_CAPTURE) + val &= ~AUD_CTRL_TOUT_IRQ_MASK; + + writel(val, mmio_base + XLNX_AUD_CTRL); +} + +static irqreturn_t xlnx_mm2s_irq_handler(int irq, void *arg) +{ + u32 val; + void __iomem *reg; + struct device *dev = arg; + struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev); + + reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS; + val = readl(reg); + if (val & AUD_STS_IOC_IRQ_MASK) { + writel(val & AUD_STS_IOC_IRQ_MASK, reg); + if (adata->play_stream) + snd_pcm_period_elapsed(adata->play_stream); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static irqreturn_t xlnx_s2mm_irq_handler(int irq, void *arg) +{ + u32 val; + void __iomem *reg; + struct device *dev = arg; + struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev); + + reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS; + val = readl(reg); + if (val & AUD_STS_IOC_IRQ_MASK) { + writel(val & AUD_STS_IOC_IRQ_MASK, reg); + if (adata->capture_stream) + snd_pcm_period_elapsed(adata->capture_stream); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int xlnx_formatter_set_sysclk(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir) +{ + struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev); + + adata->sysclk = freq; + return 0; +} + +static int xlnx_formatter_pcm_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + int err; + u32 val, data_format_mode; + u32 ch_count_mask, ch_count_shift, data_xfer_mode, data_xfer_shift; + struct xlnx_pcm_stream_param *stream_data; + struct snd_pcm_runtime *runtime = substream->runtime; + struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && + !adata->mm2s_presence) + return -ENODEV; + else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && + !adata->s2mm_presence) + return -ENODEV; + + stream_data = kzalloc(sizeof(*stream_data), GFP_KERNEL); + if (!stream_data) + return -ENOMEM; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ch_count_mask = CFG_MM2S_CH_MASK; + ch_count_shift = CFG_MM2S_CH_SHIFT; + data_xfer_mode = CFG_MM2S_XFER_MASK; + data_xfer_shift = CFG_MM2S_XFER_SHIFT; + data_format_mode = CFG_MM2S_PKG_MASK; + stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET; + adata->play_stream = substream; + + } else { + ch_count_mask = CFG_S2MM_CH_MASK; + ch_count_shift = CFG_S2MM_CH_SHIFT; + data_xfer_mode = CFG_S2MM_XFER_MASK; + data_xfer_shift = CFG_S2MM_XFER_SHIFT; + data_format_mode = CFG_S2MM_PKG_MASK; + stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET; + adata->capture_stream = substream; + } + + val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG); + + if (!(val & data_format_mode)) + stream_data->interleaved = true; + + stream_data->xfer_mode = (val & data_xfer_mode) >> data_xfer_shift; + stream_data->ch_limit = (val & ch_count_mask) >> ch_count_shift; + dev_info(component->dev, + "stream %d : format = %d mode = %d ch_limit = %d\n", + substream->stream, stream_data->interleaved, + stream_data->xfer_mode, stream_data->ch_limit); + + snd_soc_set_runtime_hwparams(substream, &xlnx_pcm_hardware); + runtime->private_data = stream_data; + + /* Resize the period bytes as divisible by 64 */ + err = snd_pcm_hw_constraint_step(runtime, 0, + SNDRV_PCM_HW_PARAM_PERIOD_BYTES, + XLNX_AUD_ALIGN_BYTES); + if (err) { + dev_err(component->dev, + "Unable to set constraint on period bytes\n"); + return err; + } + + /* Resize the buffer bytes as divisible by 64 */ + err = snd_pcm_hw_constraint_step(runtime, 0, + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, + XLNX_AUD_ALIGN_BYTES); + if (err) { + dev_err(component->dev, + "Unable to set constraint on buffer bytes\n"); + return err; + } + + /* Set periods as integer multiple */ + err = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (err < 0) { + dev_err(component->dev, + "Unable to set constraint on periods to be integer\n"); + return err; + } + + /* enable DMA IOC irq */ + val = readl(stream_data->mmio + XLNX_AUD_CTRL); + val |= AUD_CTRL_IOC_IRQ_MASK; + writel(val, stream_data->mmio + XLNX_AUD_CTRL); + + return 0; +} + +static int xlnx_formatter_pcm_close(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + int ret; + struct xlnx_pcm_stream_param *stream_data = + substream->runtime->private_data; + + ret = xlnx_formatter_pcm_reset(stream_data->mmio); + if (ret) { + dev_err(component->dev, "audio formatter reset failed\n"); + goto err_reset; + } + xlnx_formatter_disable_irqs(stream_data->mmio, substream->stream); + +err_reset: + kfree(stream_data); + return 0; +} + +static snd_pcm_uframes_t +xlnx_formatter_pcm_pointer(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + u32 pos; + struct snd_pcm_runtime *runtime = substream->runtime; + struct xlnx_pcm_stream_param *stream_data = runtime->private_data; + + pos = readl(stream_data->mmio + XLNX_AUD_XFER_COUNT); + + if (pos >= stream_data->buffer_size) + pos = 0; + + return bytes_to_frames(runtime, pos); +} + +static int xlnx_formatter_pcm_hw_params(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + u32 low, high, active_ch, val, bytes_per_ch, bits_per_sample; + u32 aes_reg1_val, aes_reg2_val; + u64 size; + struct snd_pcm_runtime *runtime = substream->runtime; + struct xlnx_pcm_stream_param *stream_data = runtime->private_data; + struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev); + + active_ch = params_channels(params); + if (active_ch > stream_data->ch_limit) + return -EINVAL; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && + adata->sysclk) { + unsigned int mclk_fs = adata->sysclk / params_rate(params); + + if (adata->sysclk % params_rate(params) != 0) { + dev_warn(component->dev, "sysclk %u not divisible by rate %u\n", + adata->sysclk, params_rate(params)); + return -EINVAL; + } + + writel(mclk_fs, stream_data->mmio + XLNX_AUD_FS_MULTIPLIER); + } + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && + stream_data->xfer_mode == AES_TO_PCM) { + val = readl(stream_data->mmio + XLNX_AUD_STS); + if (val & AUD_STS_CH_STS_MASK) { + aes_reg1_val = readl(stream_data->mmio + + XLNX_AUD_CH_STS_START); + aes_reg2_val = readl(stream_data->mmio + + XLNX_AUD_CH_STS_START + 0x4); + + xlnx_parse_aes_params(aes_reg1_val, aes_reg2_val, + component->dev); + } + } + + size = params_buffer_bytes(params); + + stream_data->buffer_size = size; + + low = lower_32_bits(runtime->dma_addr); + high = upper_32_bits(runtime->dma_addr); + writel(low, stream_data->mmio + XLNX_AUD_BUFF_ADDR_LSB); + writel(high, stream_data->mmio + XLNX_AUD_BUFF_ADDR_MSB); + + val = readl(stream_data->mmio + XLNX_AUD_CTRL); + bits_per_sample = params_width(params); + switch (bits_per_sample) { + case 8: + val |= (BIT_DEPTH_8 << AUD_CTRL_DATA_WIDTH_SHIFT); + break; + case 16: + val |= (BIT_DEPTH_16 << AUD_CTRL_DATA_WIDTH_SHIFT); + break; + case 20: + val |= (BIT_DEPTH_20 << AUD_CTRL_DATA_WIDTH_SHIFT); + break; + case 24: + val |= (BIT_DEPTH_24 << AUD_CTRL_DATA_WIDTH_SHIFT); + break; + case 32: + val |= (BIT_DEPTH_32 << AUD_CTRL_DATA_WIDTH_SHIFT); + break; + default: + return -EINVAL; + } + + val |= active_ch << AUD_CTRL_ACTIVE_CH_SHIFT; + writel(val, stream_data->mmio + XLNX_AUD_CTRL); + + val = (params_periods(params) << PERIOD_CFG_PERIODS_SHIFT) + | params_period_bytes(params); + writel(val, stream_data->mmio + XLNX_AUD_PERIOD_CONFIG); + bytes_per_ch = DIV_ROUND_UP(params_period_bytes(params), active_ch); + writel(bytes_per_ch, stream_data->mmio + XLNX_BYTES_PER_CH); + + return 0; +} + +static int xlnx_formatter_pcm_trigger(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + int cmd) +{ + u32 val; + struct xlnx_pcm_stream_param *stream_data = + substream->runtime->private_data; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_RESUME: + val = readl(stream_data->mmio + XLNX_AUD_CTRL); + val |= AUD_CTRL_DMA_EN_MASK; + writel(val, stream_data->mmio + XLNX_AUD_CTRL); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + case SNDRV_PCM_TRIGGER_SUSPEND: + val = readl(stream_data->mmio + XLNX_AUD_CTRL); + val &= ~AUD_CTRL_DMA_EN_MASK; + writel(val, stream_data->mmio + XLNX_AUD_CTRL); + break; + } + + return 0; +} + +static int xlnx_formatter_pcm_new(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd) +{ + snd_pcm_set_managed_buffer_all(rtd->pcm, + SNDRV_DMA_TYPE_DEV, component->dev, + xlnx_pcm_hardware.buffer_bytes_max, + xlnx_pcm_hardware.buffer_bytes_max); + return 0; +} + +static const struct snd_soc_component_driver xlnx_asoc_component = { + .name = DRV_NAME, + .set_sysclk = xlnx_formatter_set_sysclk, + .open = xlnx_formatter_pcm_open, + .close = xlnx_formatter_pcm_close, + .hw_params = xlnx_formatter_pcm_hw_params, + .trigger = xlnx_formatter_pcm_trigger, + .pointer = xlnx_formatter_pcm_pointer, + .pcm_construct = xlnx_formatter_pcm_new, +}; + +static int xlnx_formatter_pcm_probe(struct platform_device *pdev) +{ + int ret; + u32 val; + struct xlnx_pcm_drv_data *aud_drv_data; + struct device *dev = &pdev->dev; + + aud_drv_data = devm_kzalloc(dev, sizeof(*aud_drv_data), GFP_KERNEL); + if (!aud_drv_data) + return -ENOMEM; + + aud_drv_data->axi_clk = devm_clk_get(dev, "s_axi_lite_aclk"); + if (IS_ERR(aud_drv_data->axi_clk)) { + ret = PTR_ERR(aud_drv_data->axi_clk); + dev_err(dev, "failed to get s_axi_lite_aclk(%d)\n", ret); + return ret; + } + ret = clk_prepare_enable(aud_drv_data->axi_clk); + if (ret) { + dev_err(dev, + "failed to enable s_axi_lite_aclk(%d)\n", ret); + return ret; + } + + aud_drv_data->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(aud_drv_data->mmio)) { + dev_err(dev, "audio formatter ioremap failed\n"); + ret = PTR_ERR(aud_drv_data->mmio); + goto clk_err; + } + + val = readl(aud_drv_data->mmio + XLNX_AUD_CORE_CONFIG); + if (val & AUD_CFG_MM2S_MASK) { + aud_drv_data->mm2s_presence = true; + ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio + + XLNX_MM2S_OFFSET); + if (ret) { + dev_err(dev, "audio formatter reset failed\n"); + goto clk_err; + } + xlnx_formatter_disable_irqs(aud_drv_data->mmio + + XLNX_MM2S_OFFSET, + SNDRV_PCM_STREAM_PLAYBACK); + + aud_drv_data->mm2s_irq = platform_get_irq_byname(pdev, + "irq_mm2s"); + if (aud_drv_data->mm2s_irq < 0) { + ret = aud_drv_data->mm2s_irq; + goto clk_err; + } + ret = devm_request_irq(dev, aud_drv_data->mm2s_irq, + xlnx_mm2s_irq_handler, 0, + "xlnx_formatter_pcm_mm2s_irq", dev); + if (ret) { + dev_err(dev, "xlnx audio mm2s irq request failed\n"); + goto clk_err; + } + } + if (val & AUD_CFG_S2MM_MASK) { + aud_drv_data->s2mm_presence = true; + ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio + + XLNX_S2MM_OFFSET); + if (ret) { + dev_err(dev, "audio formatter reset failed\n"); + goto clk_err; + } + xlnx_formatter_disable_irqs(aud_drv_data->mmio + + XLNX_S2MM_OFFSET, + SNDRV_PCM_STREAM_CAPTURE); + + aud_drv_data->s2mm_irq = platform_get_irq_byname(pdev, + "irq_s2mm"); + if (aud_drv_data->s2mm_irq < 0) { + ret = aud_drv_data->s2mm_irq; + goto clk_err; + } + ret = devm_request_irq(dev, aud_drv_data->s2mm_irq, + xlnx_s2mm_irq_handler, 0, + "xlnx_formatter_pcm_s2mm_irq", + dev); + if (ret) { + dev_err(dev, "xlnx audio s2mm irq request failed\n"); + goto clk_err; + } + } + + dev_set_drvdata(dev, aud_drv_data); + + ret = devm_snd_soc_register_component(dev, &xlnx_asoc_component, + NULL, 0); + if (ret) { + dev_err(dev, "pcm platform device register failed\n"); + goto clk_err; + } + + return 0; + +clk_err: + clk_disable_unprepare(aud_drv_data->axi_clk); + return ret; +} + +static int xlnx_formatter_pcm_remove(struct platform_device *pdev) +{ + int ret = 0; + struct xlnx_pcm_drv_data *adata = dev_get_drvdata(&pdev->dev); + + if (adata->s2mm_presence) + ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_S2MM_OFFSET); + + /* Try MM2S reset, even if S2MM reset fails */ + if (adata->mm2s_presence) + ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_MM2S_OFFSET); + + if (ret) + dev_err(&pdev->dev, "audio formatter reset failed\n"); + + clk_disable_unprepare(adata->axi_clk); + return 0; +} + +static const struct of_device_id xlnx_formatter_pcm_of_match[] = { + { .compatible = "xlnx,audio-formatter-1.0"}, + {}, +}; +MODULE_DEVICE_TABLE(of, xlnx_formatter_pcm_of_match); + +static struct platform_driver xlnx_formatter_pcm_driver = { + .probe = xlnx_formatter_pcm_probe, + .remove = xlnx_formatter_pcm_remove, + .driver = { + .name = DRV_NAME, + .of_match_table = xlnx_formatter_pcm_of_match, + }, +}; + +module_platform_driver(xlnx_formatter_pcm_driver); +MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu "); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3