diff options
| author |  Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 18:24:12 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 18:24:12 -0800 |
| commit | 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 (patch) | |
| tree | cc5c2d0a898769fd59549594fedb3ee6f84e59a0 /arch/m68k/ifpsp060/src/ftest.S | |
| download | linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.tar.gz linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.zip | |
Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted
Pull networking updates from Jakub Kicinski:
"Core:
- Add dedicated kmem_cache for typical/small skb->head, avoid having
to access struct page at kfree time, and improve memory use.
- Introduce sysctl to set default RPS configuration for new netdevs.
- Define Netlink protocol specification format which can be used to
describe messages used by each family and auto-generate parsers.
Add tools for generating kernel data structures and uAPI headers.
- Expose all net/core sysctls inside netns.
- Remove 4s sleep in netpoll if carrier is instantly detected on
boot.
- Add configurable limit of MDB entries per port, and port-vlan.
- Continue populating drop reasons throughout the stack.
- Retire a handful of legacy Qdiscs and classifiers.
Protocols:
- Support IPv4 big TCP (TSO frames larger than 64kB).
- Add IP_LOCAL_PORT_RANGE socket option, to control local port range
on socket by socket basis.
- Track and report in procfs number of MPTCP sockets used.
- Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
manager.
- IPv6: don't check net.ipv6.route.max_size and rely on garbage
collection to free memory (similarly to IPv4).
- Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).
- ICMP: add per-rate limit counters.
- Add support for user scanning requests in ieee802154.
- Remove static WEP support.
- Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
reporting.
- WiFi 7 EHT channel puncturing support (client & AP).
BPF:
- Add a rbtree data structure following the "next-gen data structure"
precedent set by recently added linked list, that is, by using
kfunc + kptr instead of adding a new BPF map type.
- Expose XDP hints via kfuncs with initial support for RX hash and
timestamp metadata.
- Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
better support decap on GRE tunnel devices not operating in collect
metadata.
- Improve x86 JIT's codegen for PROBE_MEM runtime error checks.
- Remove the need for trace_printk_lock for bpf_trace_printk and
bpf_trace_vprintk helpers.
- Extend libbpf's bpf_tracing.h support for tracing arguments of
kprobes/uprobes and syscall as a special case.
- Significantly reduce the search time for module symbols by
livepatch and BPF.
- Enable cpumasks to be used as kptrs, which is useful for tracing
programs tracking which tasks end up running on which CPUs in
different time intervals.
- Add support for BPF trampoline on s390x and riscv64.
- Add capability to export the XDP features supported by the NIC.
- Add __bpf_kfunc tag for marking kernel functions as kfuncs.
- Add cgroup.memory=nobpf kernel parameter option to disable BPF
memory accounting for container environments.
Netfilter:
- Remove the CLUSTERIP target. It has been marked as obsolete for
years, and we still have WARN splats wrt races of the out-of-band
/proc interface installed by this target.
- Add 'destroy' commands to nf_tables. They are identical to the
existing 'delete' commands, but do not return an error if the
referenced object (set, chain, rule...) did not exist.
Driver API:
- Improve cpumask_local_spread() locality to help NICs set the right
IRQ affinity on AMD platforms.
- Separate C22 and C45 MDIO bus transactions more clearly.
- Introduce new DCB table to control DSCP rewrite on egress.
- Support configuration of Physical Layer Collision Avoidance (PLCA)
Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
shared medium Ethernet.
- Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
preemption of low priority frames by high priority frames.
- Add support for controlling MACSec offload using netlink SET.
- Rework devlink instance refcounts to allow registration and
de-registration under the instance lock. Split the code into
multiple files, drop some of the unnecessarily granular locks and
factor out common parts of netlink operation handling.
- Add TX frame aggregation parameters (for USB drivers).
- Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
messages with notifications for debug.
- Allow offloading of UDP NEW connections via act_ct.
- Add support for per action HW stats in TC.
- Support hardware miss to TC action (continue processing in SW from
a specific point in the action chain).
- Warn if old Wireless Extension user space interface is used with
modern cfg80211/mac80211 drivers. Do not support Wireless
Extensions for Wi-Fi 7 devices at all. Everyone should switch to
using nl80211 interface instead.
- Improve the CAN bit timing configuration. Use extack to return
error messages directly to user space, update the SJW handling,
including the definition of a new default value that will benefit
CAN-FD controllers, by increasing their oscillator tolerance.
New hardware / drivers:
- Ethernet:
- nVidia BlueField-3 support (control traffic driver)
- Ethernet support for imx93 SoCs
- Motorcomm yt8531 gigabit Ethernet PHY
- onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
- Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
- Amlogic gxl MDIO mux
- WiFi:
- RealTek RTL8188EU (rtl8xxxu)
- Qualcomm Wi-Fi 7 devices (ath12k)
- CAN:
- Renesas R-Car V4H
Drivers:
- Bluetooth:
- Set Per Platform Antenna Gain (PPAG) for Intel controllers.
- Ethernet NICs:
- Intel (1G, igc):
- support TSN / Qbv / packet scheduling features of i226 model
- Intel (100G, ice):
- use GNSS subsystem instead of TTY
- multi-buffer XDP support
- extend support for GPIO pins to E823 devices
- nVidia/Mellanox:
- update the shared buffer configuration on PFC commands
- implement PTP adjphase function for HW offset control
- TC support for Geneve and GRE with VF tunnel offload
- more efficient crypto key management method
- multi-port eswitch support
- Netronome/Corigine:
- add DCB IEEE support
- support IPsec offloading for NFP3800
- Freescale/NXP (enetc):
- support XDP_REDIRECT for XDP non-linear buffers
- improve reconfig, avoid link flap and waiting for idle
- support MAC Merge layer
- Other NICs:
- sfc/ef100: add basic devlink support for ef100
- ionic: rx_push mode operation (writing descriptors via MMIO)
- bnxt: use the auxiliary bus abstraction for RDMA
- r8169: disable ASPM and reset bus in case of tx timeout
- cpsw: support QSGMII mode for J721e CPSW9G
- cpts: support pulse-per-second output
- ngbe: add an mdio bus driver
- usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
- r8152: handle devices with FW with NCM support
- amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
- virtio-net: support multi buffer XDP
- virtio/vsock: replace virtio_vsock_pkt with sk_buff
- tsnep: XDP support
- Ethernet high-speed switches:
- nVidia/Mellanox (mlxsw):
- add support for latency TLV (in FW control messages)
- Microchip (sparx5):
- separate explicit and implicit traffic forwarding rules, make
the implicit rules always active
- add support for egress DSCP rewrite
- IS0 VCAP support (Ingress Classification)
- IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
etc.)
- ES2 VCAP support (Egress Access Control)
- support for Per-Stream Filtering and Policing (802.1Q,
8.6.5.1)
- Ethernet embedded switches:
- Marvell (mv88e6xxx):
- add MAB (port auth) offload support
- enable PTP receive for mv88e6390
- NXP (ocelot):
- support MAC Merge layer
- support for the the vsc7512 internal copper phys
- Microchip:
- lan9303: convert to PHYLINK
- lan966x: support TC flower filter statistics
- lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
- lan937x: support Credit Based Shaper configuration
- ksz9477: support Energy Efficient Ethernet
- other:
- qca8k: convert to regmap read/write API, use bulk operations
- rswitch: Improve TX timestamp accuracy
- Intel WiFi (iwlwifi):
- EHT (Wi-Fi 7) rate reporting
- STEP equalizer support: transfer some STEP (connection to radio
on platforms with integrated wifi) related parameters from the
BIOS to the firmware.
- Qualcomm 802.11ax WiFi (ath11k):
- IPQ5018 support
- Fine Timing Measurement (FTM) responder role support
- channel 177 support
- MediaTek WiFi (mt76):
- per-PHY LED support
- mt7996: EHT (Wi-Fi 7) support
- Wireless Ethernet Dispatch (WED) reset support
- switch to using page pool allocator
- RealTek WiFi (rtw89):
- support new version of Bluetooth co-existance
- Mobile:
- rmnet: support TX aggregation"
* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
page_pool: add a comment explaining the fragment counter usage
net: ethtool: fix __ethtool_dev_mm_supported() implementation
ethtool: pse-pd: Fix double word in comments
xsk: add linux/vmalloc.h to xsk.c
sefltests: netdevsim: wait for devlink instance after netns removal
selftest: fib_tests: Always cleanup before exit
net/mlx5e: Align IPsec ASO result memory to be as required by hardware
net/mlx5e: TC, Set CT miss to the specific ct action instance
net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
net/mlx5: Refactor tc miss handling to a single function
net/mlx5: Kconfig: Make tc offload depend on tc skb extension
net/sched: flower: Support hardware miss to tc action
net/sched: flower: Move filter handle initialization earlier
net/sched: cls_api: Support hardware miss to tc action
net/sched: Rename user cookie and act cookie
sfc: fix builds without CONFIG_RTC_LIB
sfc: clean up some inconsistent indentings
net/mlx4_en: Introduce flexible array to silence overflow warning
net: lan966x: Fix possible deadlock inside PTP
net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
...
Diffstat (limited to 'arch/m68k/ifpsp060/src/ftest.S')
| -rw-r--r-- | arch/m68k/ifpsp060/src/ftest.S | 1456 |
1 files changed, 1456 insertions, 0 deletions
diff --git a/arch/m68k/ifpsp060/src/ftest.S b/arch/m68k/ifpsp060/src/ftest.S new file mode 100644 index 000000000..1f947915d --- /dev/null +++ b/arch/m68k/ifpsp060/src/ftest.S @@ -0,0 +1,1456 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +############################################# +set SREGS, -64 +set IREGS, -128 +set IFPREGS, -224 +set SFPREGS, -320 +set IFPCREGS, -332 +set SFPCREGS, -344 +set ICCR, -346 +set SCCR, -348 +set TESTCTR, -352 +set DATA, -384 + +############################################# +TESTTOP: + bra.l _060TESTS_ + short 0x0000 + + bra.l _060TESTS_unimp + short 0x0000 + + bra.l _060TESTS_enable + short 0x0000 + +start_str: + string "Testing 68060 FPSP started:\n" + +start_str_unimp: + string "Testing 68060 FPSP unimplemented instruction started:\n" + +start_str_enable: + string "Testing 68060 FPSP exception enabled started:\n" + +pass_str: + string "passed\n" + +fail_str: + string " failed\n" + + align 0x4 +chk_test: + tst.l %d0 + bne.b test_fail +test_pass: + pea pass_str(%pc) + bsr.l _print_str + addq.l &0x4,%sp + rts +test_fail: + mov.l %d1,-(%sp) + bsr.l _print_num + addq.l &0x4,%sp + + pea fail_str(%pc) + bsr.l _print_str + addq.l &0x4,%sp + rts + +############################################# +_060TESTS_: + link %a6,&-384 + + movm.l &0x3f3c,-(%sp) + fmovm.x &0xff,-(%sp) + + pea start_str(%pc) + bsr.l _print_str + addq.l &0x4,%sp + +### effadd + clr.l TESTCTR(%a6) + pea effadd_str(%pc) + bsr.l _print_str + addq.l &0x4,%sp + + bsr.l effadd_0 + + bsr.l chk_test + +### unsupp + clr.l TESTCTR(%a6) + pea unsupp_str(%pc) + bsr.l _print_str + addq.l &0x4,%sp + + bsr.l unsupp_0 + + bsr.l chk_test + +### ovfl non-maskable + clr.l TESTCTR(%a6) + pea ovfl_nm_str(%pc) + bsr.l _print_str + bsr.l ovfl_nm_0 + + bsr.l chk_test + +### unfl non-maskable + clr.l TESTCTR(%a6) + pea unfl_nm_str(%pc) + bsr.l _print_str + bsr.l unfl_nm_0 + + bsr.l chk_test + + movm.l (%sp)+,&0x3cfc + fmovm.x (%sp)+,&0xff + + unlk %a6 + rts + +_060TESTS_unimp: + link %a6,&-384 + + movm.l &0x3f3c,-(%sp) + fmovm.x &0xff,-(%sp) + + pea start_str_unimp(%pc) + bsr.l _print_str + addq.l &0x4,%sp + +### unimp + clr.l TESTCTR(%a6) + pea unimp_str(%pc) + bsr.l _print_str + addq.l &0x4,%sp + + bsr.l unimp_0 + + bsr.l chk_test + + movm.l (%sp)+,&0x3cfc + fmovm.x (%sp)+,&0xff + + unlk %a6 + rts + +_060TESTS_enable: + link %a6,&-384 + + movm.l &0x3f3c,-(%sp) + fmovm.x &0xff,-(%sp) + + pea start_str_enable(%pc) + bsr.l _print_str + addq.l &0x4,%sp + +### snan + clr.l TESTCTR(%a6) + pea snan_str(%pc) + bsr.l _print_str + bsr.l snan_0 + + bsr.l chk_test + +### operr + clr.l TESTCTR(%a6) + pea operr_str(%pc) + bsr.l _print_str + bsr.l operr_0 + + bsr.l chk_test + +### ovfl + clr.l TESTCTR(%a6) + pea ovfl_str(%pc) + bsr.l _print_str + bsr.l ovfl_0 + + bsr.l chk_test + +### unfl + clr.l TESTCTR(%a6) + pea unfl_str(%pc) + bsr.l _print_str + bsr.l unfl_0 + + bsr.l chk_test + +### dz + clr.l TESTCTR(%a6) + pea dz_str(%pc) + bsr.l _print_str + bsr.l dz_0 + + bsr.l chk_test + +### inexact + clr.l TESTCTR(%a6) + pea inex_str(%pc) + bsr.l _print_str + bsr.l inex_0 + + bsr.l chk_test + + movm.l (%sp)+,&0x3cfc + fmovm.x (%sp)+,&0xff + + unlk %a6 + rts + +############################################# +############################################# + +unimp_str: + string "\tUnimplemented FP instructions..." + + align 0x4 +unimp_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0x40000000,DATA+0x0(%a6) + mov.l &0xc90fdaa2,DATA+0x4(%a6) + mov.l &0x2168c235,DATA+0x8(%a6) + + mov.w &0x0000,%cc +unimp_0_pc: + fsin.x DATA(%a6),%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0xbfbf0000,IFPREGS+0x0(%a6) + mov.l &0x80000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x08000208,IFPCREGS+0x4(%a6) + lea unimp_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +unimp_1: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0x3ffe0000,DATA+0x0(%a6) + mov.l &0xc90fdaa2,DATA+0x4(%a6) + mov.l &0x2168c235,DATA+0x8(%a6) + + mov.w &0x0000,%cc +unimp_1_pc: + ftan.x DATA(%a6),%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x3fff0000,IFPREGS+0x0(%a6) + mov.l &0x80000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x00000208,IFPCREGS+0x4(%a6) + lea unimp_1_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +# fmovecr +unimp_2: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.w &0x0000,%cc +unimp_2_pc: + fmovcr.x &0x31,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x40000000,IFPREGS+0x0(%a6) + mov.l &0x935d8ddd,IFPREGS+0x4(%a6) + mov.l &0xaaa8ac17,IFPREGS+0x8(%a6) + mov.l &0x00000208,IFPCREGS+0x4(%a6) + lea unimp_2_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +# fscc +unimp_3: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + fmov.l &0x0f000000,%fpsr + mov.l &0x00,%d7 + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.w &0x0000,%cc +unimp_3_pc: + fsgt %d7 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + mov.l &0x0f008080,IFPCREGS+0x4(%a6) + lea unimp_3_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +# fdbcc +unimp_4: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + fmov.l &0x0f000000,%fpsr + mov.l &0x2,%d7 + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.w &0x0000,%cc +unimp_4_pc: + fdbgt.w %d7,unimp_4_pc + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + mov.w &0xffff,IREGS+28+2(%a6) + mov.l &0x0f008080,IFPCREGS+0x4(%a6) + lea unimp_4_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +# ftrapcc +unimp_5: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + fmov.l &0x0f000000,%fpsr + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.w &0x0000,%cc +unimp_5_pc: + ftpgt.l &0xabcdef01 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + mov.l &0x0f008080,IFPCREGS+0x4(%a6) + lea unimp_5_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +############################################# + +effadd_str: + string "\tUnimplemented <ea>..." + + align 0x4 +effadd_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + fmov.b &0x2,%fp0 + + mov.w &0x0000,%cc +effadd_0_pc: + fmul.x &0xc00000008000000000000000,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0xc0010000,IFPREGS+0x0(%a6) + mov.l &0x80000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x08000000,IFPCREGS+0x4(%a6) + lea effadd_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +effadd_1: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.w &0x0000,%cc +effadd_1_pc: + fabs.p &0xc12300012345678912345678,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x3e660000,IFPREGS+0x0(%a6) + mov.l &0xd0ed23e8,IFPREGS+0x4(%a6) + mov.l &0xd14035bc,IFPREGS+0x8(%a6) + mov.l &0x00000108,IFPCREGS+0x4(%a6) + lea effadd_1_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +fmovml_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + mov.w &0x0000,%cc + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + fmovm.l &0xffffffffffffffff,%fpcr,%fpsr + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + mov.l &0x0000fff0,IFPCREGS+0x0(%a6) + mov.l &0x0ffffff8,IFPCREGS+0x4(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +fmovml_1: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + mov.w &0x0000,%cc + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + fmovm.l &0xffffffffffffffff,%fpcr,%fpiar + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + mov.l &0x0000fff0,IFPCREGS+0x0(%a6) + mov.l &0xffffffff,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +fmovml_2: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + mov.w &0x0000,%cc + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + fmovm.l &0xffffffffffffffff,%fpsr,%fpiar + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + mov.l &0x0ffffff8,IFPCREGS+0x4(%a6) + mov.l &0xffffffff,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +fmovml_3: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + mov.w &0x0000,%cc + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + fmovm.l &0xffffffffffffffffffffffff,%fpcr,%fpsr,%fpiar + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + mov.l &0x0000fff0,IFPCREGS+0x0(%a6) + mov.l &0x0ffffff8,IFPCREGS+0x4(%a6) + mov.l &0xffffffff,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +# fmovmx dynamic +fmovmx_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + fmov.b &0x1,%fp0 + fmov.b &0x2,%fp1 + fmov.b &0x3,%fp2 + fmov.b &0x4,%fp3 + fmov.b &0x5,%fp4 + fmov.b &0x6,%fp5 + fmov.b &0x7,%fp6 + fmov.b &0x8,%fp7 + + fmov.l &0x0,%fpiar + mov.l &0xffffffaa,%d0 + + mov.w &0x0000,ICCR(%a6) + movm.l &0xffff,IREGS(%a6) + + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + + mov.w &0x0000,%cc + + fmovm.x %d0,-(%sp) + + mov.w %cc,SCCR(%a6) + + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + fmov.s &0x7f800000,%fp1 + fmov.s &0x7f800000,%fp3 + fmov.s &0x7f800000,%fp5 + fmov.s &0x7f800000,%fp7 + + fmov.x (%sp)+,%fp1 + fmov.x (%sp)+,%fp3 + fmov.x (%sp)+,%fp5 + fmov.x (%sp)+,%fp7 + + movm.l &0xffff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +fmovmx_1: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + fmov.b &0x1,%fp0 + fmov.b &0x2,%fp1 + fmov.b &0x3,%fp2 + fmov.b &0x4,%fp3 + fmov.b &0x5,%fp4 + fmov.b &0x6,%fp5 + fmov.b &0x7,%fp6 + fmov.b &0x8,%fp7 + + fmov.x %fp6,-(%sp) + fmov.x %fp4,-(%sp) + fmov.x %fp2,-(%sp) + fmov.x %fp0,-(%sp) + + fmovm.x &0xff,IFPREGS(%a6) + + fmov.s &0x7f800000,%fp6 + fmov.s &0x7f800000,%fp4 + fmov.s &0x7f800000,%fp2 + fmov.s &0x7f800000,%fp0 + + fmov.l &0x0,%fpiar + fmov.l &0x0,%fpsr + mov.l &0xffffffaa,%d0 + + mov.w &0x0000,ICCR(%a6) + movm.l &0xffff,IREGS(%a6) + + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.w &0x0000,%cc + + fmovm.x (%sp)+,%d0 + + mov.w %cc,SCCR(%a6) + + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + movm.l &0xffff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +fmovmx_2: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + fmov.b &0x1,%fp0 + fmov.b &0x2,%fp1 + fmov.b &0x3,%fp2 + fmov.b &0x4,%fp3 + fmov.b &0x5,%fp4 + fmov.b &0x6,%fp5 + fmov.b &0x7,%fp6 + fmov.b &0x8,%fp7 + + fmov.l &0x0,%fpiar + mov.l &0xffffff00,%d0 + + mov.w &0x0000,ICCR(%a6) + movm.l &0xffff,IREGS(%a6) + + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + + mov.w &0x0000,%cc + + fmovm.x %d0,-(%sp) + + mov.w %cc,SCCR(%a6) + + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + movm.l &0xffff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +########################################################### + +# This test will take a non-maskable overflow directly. +ovfl_nm_str: + string "\tNon-maskable overflow..." + + align 0x4 +ovfl_nm_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + fmov.b &0x2,%fp0 + mov.l &0x7ffe0000,DATA+0x0(%a6) + mov.l &0x80000000,DATA+0x4(%a6) + mov.l &0x00000000,DATA+0x8(%a6) + + mov.w &0x0000,%cc +ovfl_nm_0_pc: + fmul.x DATA(%a6),%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x7fff0000,IFPREGS+0x0(%a6) + mov.l &0x00000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x02001048,IFPCREGS+0x4(%a6) + lea ovfl_nm_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +########################################################### + +# This test will take an overflow directly. +ovfl_str: + string "\tEnabled overflow..." + + align 0x4 +ovfl_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmov.l &0x00001000,%fpcr + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + fmov.b &0x2,%fp0 + mov.l &0x7ffe0000,DATA+0x0(%a6) + mov.l &0x80000000,DATA+0x4(%a6) + mov.l &0x00000000,DATA+0x8(%a6) + + mov.w &0x0000,%cc +ovfl_0_pc: + fmul.x DATA(%a6),%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x7fff0000,IFPREGS+0x0(%a6) + mov.l &0x00000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x02001048,IFPCREGS+0x4(%a6) + lea ovfl_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +##################################################################### + +# This test will take an underflow directly. +unfl_str: + string "\tEnabled underflow..." + + align 0x4 +unfl_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmov.l &0x00000800,%fpcr + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0x00000000,DATA+0x0(%a6) + mov.l &0x80000000,DATA+0x4(%a6) + mov.l &0x00000000,DATA+0x8(%a6) + fmovm.x DATA(%a6),&0x80 + + mov.w &0x0000,%cc +unfl_0_pc: + fdiv.b &0x2,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x00000000,IFPREGS+0x0(%a6) + mov.l &0x40000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x00000800,IFPCREGS+0x4(%a6) + lea unfl_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +##################################################################### + +# This test will take a non-maskable underflow directly. +unfl_nm_str: + string "\tNon-maskable underflow..." + + align 0x4 +unfl_nm_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0x00000000,DATA+0x0(%a6) + mov.l &0x80000000,DATA+0x4(%a6) + mov.l &0x00000000,DATA+0x8(%a6) + fmovm.x DATA(%a6),&0x80 + + mov.w &0x0000,%cc +unfl_nm_0_pc: + fdiv.b &0x2,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x00000000,IFPREGS+0x0(%a6) + mov.l &0x40000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x00000800,IFPCREGS+0x4(%a6) + lea unfl_nm_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +##################################################################### + +inex_str: + string "\tEnabled inexact..." + + align 0x4 +inex_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmov.l &0x00000200,%fpcr # enable inexact + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0x50000000,DATA+0x0(%a6) + mov.l &0x80000000,DATA+0x4(%a6) + mov.l &0x00000000,DATA+0x8(%a6) + fmovm.x DATA(%a6),&0x80 + + mov.w &0x0000,%cc +inex_0_pc: + fadd.b &0x2,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x50000000,IFPREGS+0x0(%a6) + mov.l &0x80000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x00000208,IFPCREGS+0x4(%a6) + lea inex_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +##################################################################### + +snan_str: + string "\tEnabled SNAN..." + + align 0x4 +snan_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmov.l &0x00004000,%fpcr # enable SNAN + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0xffff0000,DATA+0x0(%a6) + mov.l &0x00000000,DATA+0x4(%a6) + mov.l &0x00000001,DATA+0x8(%a6) + fmovm.x DATA(%a6),&0x80 + + mov.w &0x0000,%cc +snan_0_pc: + fadd.b &0x2,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0xffff0000,IFPREGS+0x0(%a6) + mov.l &0x00000000,IFPREGS+0x4(%a6) + mov.l &0x00000001,IFPREGS+0x8(%a6) + mov.l &0x09004080,IFPCREGS+0x4(%a6) + lea snan_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +##################################################################### + +operr_str: + string "\tEnabled OPERR..." + + align 0x4 +operr_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmov.l &0x00002000,%fpcr # enable OPERR + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0xffff0000,DATA+0x0(%a6) + mov.l &0x00000000,DATA+0x4(%a6) + mov.l &0x00000000,DATA+0x8(%a6) + fmovm.x DATA(%a6),&0x80 + + mov.w &0x0000,%cc +operr_0_pc: + fadd.s &0x7f800000,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0xffff0000,IFPREGS+0x0(%a6) + mov.l &0x00000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x01002080,IFPCREGS+0x4(%a6) + lea operr_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +##################################################################### + +dz_str: + string "\tEnabled DZ..." + + align 0x4 +dz_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmov.l &0x00000400,%fpcr # enable DZ + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0x40000000,DATA+0x0(%a6) + mov.l &0x80000000,DATA+0x4(%a6) + mov.l &0x00000000,DATA+0x8(%a6) + fmovm.x DATA(%a6),&0x80 + + mov.w &0x0000,%cc +dz_0_pc: + fdiv.b &0x0,%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x40000000,IFPREGS+0x0(%a6) + mov.l &0x80000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x02000410,IFPCREGS+0x4(%a6) + lea dz_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +##################################################################### + +unsupp_str: + string "\tUnimplemented data type/format..." + +# an unnormalized number + align 0x4 +unsupp_0: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0xc03f0000,DATA+0x0(%a6) + mov.l &0x00000000,DATA+0x4(%a6) + mov.l &0x00000001,DATA+0x8(%a6) + fmov.b &0x2,%fp0 + mov.w &0x0000,%cc +unsupp_0_pc: + fmul.x DATA(%a6),%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0xc0010000,IFPREGS+0x0(%a6) + mov.l &0x80000000,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x08000000,IFPCREGS+0x4(%a6) + lea unsupp_0_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +# a denormalized number +unsupp_1: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0x80000000,DATA+0x0(%a6) + mov.l &0x01000000,DATA+0x4(%a6) + mov.l &0x00000000,DATA+0x8(%a6) + fmov.l &0x7fffffff,%fp0 + + mov.w &0x0000,%cc +unsupp_1_pc: + fmul.x DATA(%a6),%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x80170000,IFPREGS+0x0(%a6) + mov.l &0xfffffffe,IFPREGS+0x4(%a6) + mov.l &0x00000000,IFPREGS+0x8(%a6) + mov.l &0x08000000,IFPCREGS+0x4(%a6) + lea unsupp_1_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + +# packed +unsupp_2: + addq.l &0x1,TESTCTR(%a6) + + movm.l DEF_REGS(%pc),&0x3fff + fmovm.x DEF_FPREGS(%pc),&0xff + fmovm.l DEF_FPCREGS(%pc),%fpcr,%fpsr,%fpiar + + mov.w &0x0000,ICCR(%a6) + movm.l &0x7fff,IREGS(%a6) + fmovm.x &0xff,IFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6) + + mov.l &0xc1230001,DATA+0x0(%a6) + mov.l &0x23456789,DATA+0x4(%a6) + mov.l &0x12345678,DATA+0x8(%a6) + + mov.w &0x0000,%cc +unsupp_2_pc: + fabs.p DATA(%a6),%fp0 + + mov.w %cc,SCCR(%a6) + movm.l &0x7fff,SREGS(%a6) + fmovm.x &0xff,SFPREGS(%a6) + fmovm.l %fpcr,%fpsr,%fpiar,SFPCREGS(%a6) + + mov.l &0x3e660000,IFPREGS+0x0(%a6) + mov.l &0xd0ed23e8,IFPREGS+0x4(%a6) + mov.l &0xd14035bc,IFPREGS+0x8(%a6) + mov.l &0x00000108,IFPCREGS+0x4(%a6) + lea unsupp_2_pc(%pc),%a0 + mov.l %a0,IFPCREGS+0x8(%a6) + + bsr.l chkregs + tst.b %d0 + bne.l error + + bsr.l chkfpregs + tst.b %d0 + bne.l error + + clr.l %d0 + rts + +########################################################### +########################################################### + +chkregs: + lea IREGS(%a6),%a0 + lea SREGS(%a6),%a1 + mov.l &14,%d0 +chkregs_loop: + cmp.l (%a0)+,(%a1)+ + bne.l chkregs_error + dbra.w %d0,chkregs_loop + + mov.w ICCR(%a6),%d0 + mov.w SCCR(%a6),%d1 + cmp.w %d0,%d1 + bne.l chkregs_error + + clr.l %d0 + rts + +chkregs_error: + movq.l &0x1,%d0 + rts + +error: + mov.l TESTCTR(%a6),%d1 + movq.l &0x1,%d0 + rts + +chkfpregs: + lea IFPREGS(%a6),%a0 + lea SFPREGS(%a6),%a1 + mov.l &23,%d0 +chkfpregs_loop: + cmp.l (%a0)+,(%a1)+ + bne.l chkfpregs_error + dbra.w %d0,chkfpregs_loop + + lea IFPCREGS(%a6),%a0 + lea SFPCREGS(%a6),%a1 + cmp.l (%a0)+,(%a1)+ + bne.l chkfpregs_error + cmp.l (%a0)+,(%a1)+ + bne.l chkfpregs_error + cmp.l (%a0)+,(%a1)+ + bne.l chkfpregs_error + + clr.l %d0 + rts + +chkfpregs_error: + movq.l &0x1,%d0 + rts + +DEF_REGS: + long 0xacacacac, 0xacacacac, 0xacacacac, 0xacacacac + long 0xacacacac, 0xacacacac, 0xacacacac, 0xacacacac + + long 0xacacacac, 0xacacacac, 0xacacacac, 0xacacacac + long 0xacacacac, 0xacacacac, 0xacacacac, 0xacacacac + +DEF_FPREGS: + long 0x7fff0000, 0xffffffff, 0xffffffff + long 0x7fff0000, 0xffffffff, 0xffffffff + long 0x7fff0000, 0xffffffff, 0xffffffff + long 0x7fff0000, 0xffffffff, 0xffffffff + long 0x7fff0000, 0xffffffff, 0xffffffff + long 0x7fff0000, 0xffffffff, 0xffffffff + long 0x7fff0000, 0xffffffff, 0xffffffff + long 0x7fff0000, 0xffffffff, 0xffffffff + +DEF_FPCREGS: + long 0x00000000, 0x00000000, 0x00000000 + +############################################################ + +_print_str: + mov.l %d0,-(%sp) + mov.l (TESTTOP-0x80+0x0,%pc),%d0 + pea (TESTTOP-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + +_print_num: + mov.l %d0,-(%sp) + mov.l (TESTTOP-0x80+0x4,%pc),%d0 + pea (TESTTOP-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + +############################################################ |