Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted

Pull networking updates from Jakub Kicinski:
 "Core:

   - Add dedicated kmem_cache for typical/small skb->head, avoid having
     to access struct page at kfree time, and improve memory use.

   - Introduce sysctl to set default RPS configuration for new netdevs.

   - Define Netlink protocol specification format which can be used to
     describe messages used by each family and auto-generate parsers.
     Add tools for generating kernel data structures and uAPI headers.

   - Expose all net/core sysctls inside netns.

   - Remove 4s sleep in netpoll if carrier is instantly detected on
     boot.

   - Add configurable limit of MDB entries per port, and port-vlan.

   - Continue populating drop reasons throughout the stack.

   - Retire a handful of legacy Qdiscs and classifiers.

  Protocols:

   - Support IPv4 big TCP (TSO frames larger than 64kB).

   - Add IP_LOCAL_PORT_RANGE socket option, to control local port range
     on socket by socket basis.

   - Track and report in procfs number of MPTCP sockets used.

   - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
     manager.

   - IPv6: don't check net.ipv6.route.max_size and rely on garbage
     collection to free memory (similarly to IPv4).

   - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).

   - ICMP: add per-rate limit counters.

   - Add support for user scanning requests in ieee802154.

   - Remove static WEP support.

   - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
     reporting.

   - WiFi 7 EHT channel puncturing support (client & AP).

  BPF:

   - Add a rbtree data structure following the "next-gen data structure"
     precedent set by recently added linked list, that is, by using
     kfunc + kptr instead of adding a new BPF map type.

   - Expose XDP hints via kfuncs with initial support for RX hash and
     timestamp metadata.

   - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
     better support decap on GRE tunnel devices not operating in collect
     metadata.

   - Improve x86 JIT's codegen for PROBE_MEM runtime error checks.

   - Remove the need for trace_printk_lock for bpf_trace_printk and
     bpf_trace_vprintk helpers.

   - Extend libbpf's bpf_tracing.h support for tracing arguments of
     kprobes/uprobes and syscall as a special case.

   - Significantly reduce the search time for module symbols by
     livepatch and BPF.

   - Enable cpumasks to be used as kptrs, which is useful for tracing
     programs tracking which tasks end up running on which CPUs in
     different time intervals.

   - Add support for BPF trampoline on s390x and riscv64.

   - Add capability to export the XDP features supported by the NIC.

   - Add __bpf_kfunc tag for marking kernel functions as kfuncs.

   - Add cgroup.memory=nobpf kernel parameter option to disable BPF
     memory accounting for container environments.

  Netfilter:

   - Remove the CLUSTERIP target. It has been marked as obsolete for
     years, and we still have WARN splats wrt races of the out-of-band
     /proc interface installed by this target.

   - Add 'destroy' commands to nf_tables. They are identical to the
     existing 'delete' commands, but do not return an error if the
     referenced object (set, chain, rule...) did not exist.

  Driver API:

   - Improve cpumask_local_spread() locality to help NICs set the right
     IRQ affinity on AMD platforms.

   - Separate C22 and C45 MDIO bus transactions more clearly.

   - Introduce new DCB table to control DSCP rewrite on egress.

   - Support configuration of Physical Layer Collision Avoidance (PLCA)
     Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
     shared medium Ethernet.

   - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
     preemption of low priority frames by high priority frames.

   - Add support for controlling MACSec offload using netlink SET.

   - Rework devlink instance refcounts to allow registration and
     de-registration under the instance lock. Split the code into
     multiple files, drop some of the unnecessarily granular locks and
     factor out common parts of netlink operation handling.

   - Add TX frame aggregation parameters (for USB drivers).

   - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
     messages with notifications for debug.

   - Allow offloading of UDP NEW connections via act_ct.

   - Add support for per action HW stats in TC.

   - Support hardware miss to TC action (continue processing in SW from
     a specific point in the action chain).

   - Warn if old Wireless Extension user space interface is used with
     modern cfg80211/mac80211 drivers. Do not support Wireless
     Extensions for Wi-Fi 7 devices at all. Everyone should switch to
     using nl80211 interface instead.

   - Improve the CAN bit timing configuration. Use extack to return
     error messages directly to user space, update the SJW handling,
     including the definition of a new default value that will benefit
     CAN-FD controllers, by increasing their oscillator tolerance.

  New hardware / drivers:

   - Ethernet:
      - nVidia BlueField-3 support (control traffic driver)
      - Ethernet support for imx93 SoCs
      - Motorcomm yt8531 gigabit Ethernet PHY
      - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
      - Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
      - Amlogic gxl MDIO mux

   - WiFi:
      - RealTek RTL8188EU (rtl8xxxu)
      - Qualcomm Wi-Fi 7 devices (ath12k)

   - CAN:
      - Renesas R-Car V4H

  Drivers:

   - Bluetooth:
      - Set Per Platform Antenna Gain (PPAG) for Intel controllers.

   - Ethernet NICs:
      - Intel (1G, igc):
         - support TSN / Qbv / packet scheduling features of i226 model
      - Intel (100G, ice):
         - use GNSS subsystem instead of TTY
         - multi-buffer XDP support
         - extend support for GPIO pins to E823 devices
      - nVidia/Mellanox:
         - update the shared buffer configuration on PFC commands
         - implement PTP adjphase function for HW offset control
         - TC support for Geneve and GRE with VF tunnel offload
         - more efficient crypto key management method
         - multi-port eswitch support
      - Netronome/Corigine:
         - add DCB IEEE support
         - support IPsec offloading for NFP3800
      - Freescale/NXP (enetc):
         - support XDP_REDIRECT for XDP non-linear buffers
         - improve reconfig, avoid link flap and waiting for idle
         - support MAC Merge layer
      - Other NICs:
         - sfc/ef100: add basic devlink support for ef100
         - ionic: rx_push mode operation (writing descriptors via MMIO)
         - bnxt: use the auxiliary bus abstraction for RDMA
         - r8169: disable ASPM and reset bus in case of tx timeout
         - cpsw: support QSGMII mode for J721e CPSW9G
         - cpts: support pulse-per-second output
         - ngbe: add an mdio bus driver
         - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
         - r8152: handle devices with FW with NCM support
         - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
         - virtio-net: support multi buffer XDP
         - virtio/vsock: replace virtio_vsock_pkt with sk_buff
         - tsnep: XDP support

   - Ethernet high-speed switches:
      - nVidia/Mellanox (mlxsw):
         - add support for latency TLV (in FW control messages)
      - Microchip (sparx5):
         - separate explicit and implicit traffic forwarding rules, make
           the implicit rules always active
         - add support for egress DSCP rewrite
         - IS0 VCAP support (Ingress Classification)
         - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
           etc.)
         - ES2 VCAP support (Egress Access Control)
         - support for Per-Stream Filtering and Policing (802.1Q,
           8.6.5.1)

   - Ethernet embedded switches:
      - Marvell (mv88e6xxx):
         - add MAB (port auth) offload support
         - enable PTP receive for mv88e6390
      - NXP (ocelot):
         - support MAC Merge layer
         - support for the the vsc7512 internal copper phys
      - Microchip:
         - lan9303: convert to PHYLINK
         - lan966x: support TC flower filter statistics
         - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
         - lan937x: support Credit Based Shaper configuration
         - ksz9477: support Energy Efficient Ethernet
      - other:
         - qca8k: convert to regmap read/write API, use bulk operations
         - rswitch: Improve TX timestamp accuracy

   - Intel WiFi (iwlwifi):
      - EHT (Wi-Fi 7) rate reporting
      - STEP equalizer support: transfer some STEP (connection to radio
        on platforms with integrated wifi) related parameters from the
        BIOS to the firmware.

   - Qualcomm 802.11ax WiFi (ath11k):
      - IPQ5018 support
      - Fine Timing Measurement (FTM) responder role support
      - channel 177 support

   - MediaTek WiFi (mt76):
      - per-PHY LED support
      - mt7996: EHT (Wi-Fi 7) support
      - Wireless Ethernet Dispatch (WED) reset support
      - switch to using page pool allocator

   - RealTek WiFi (rtw89):
      - support new version of Bluetooth co-existance

   - Mobile:
      - rmnet: support TX aggregation"

* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
  page_pool: add a comment explaining the fragment counter usage
  net: ethtool: fix __ethtool_dev_mm_supported() implementation
  ethtool: pse-pd: Fix double word in comments
  xsk: add linux/vmalloc.h to xsk.c
  sefltests: netdevsim: wait for devlink instance after netns removal
  selftest: fib_tests: Always cleanup before exit
  net/mlx5e: Align IPsec ASO result memory to be as required by hardware
  net/mlx5e: TC, Set CT miss to the specific ct action instance
  net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
  net/mlx5: Refactor tc miss handling to a single function
  net/mlx5: Kconfig: Make tc offload depend on tc skb extension
  net/sched: flower: Support hardware miss to tc action
  net/sched: flower: Move filter handle initialization earlier
  net/sched: cls_api: Support hardware miss to tc action
  net/sched: Rename user cookie and act cookie
  sfc: fix builds without CONFIG_RTC_LIB
  sfc: clean up some inconsistent indentings
  net/mlx4_en: Introduce flexible array to silence overflow warning
  net: lan966x: Fix possible deadlock inside PTP
  net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
  ...

1 files changed, 1063 insertions, 0 deletions

diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2_coresight_regs.h b/drivers/misc/habanalabs/gaudi2/gaudi2_coresight_regs.h
new file mode 100644
index 000000000..df8729286
--- /dev/null
+++ b/drivers/misc/habanalabs/gaudi2/gaudi2_coresight_regs.h
@@ -0,0 +1,1063 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+#ifndef GAUDI2_CORESIGHT_REGS_DRV_H_
+#define GAUDI2_CORESIGHT_REGS_DRV_H_
+
+#include "gaudi2_masks.h"
+#include "../include/gaudi2/gaudi2_coresight.h"
+#include "gaudi2P.h"
+
+/* FUNNEL Offsets - same offsets for all funnels*/
+#define mmFUNNEL_CTRL_REG_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PRIORITY_CTRL_REG_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITATBDATA0_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITATBCTR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITATBCTR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITATBCTR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITCTRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITCTRL -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CLAIMSET_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CLAIMCLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_LOCKACCESS_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_LOCKSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_AUTHSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_DEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_DEVID -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_DEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR4 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PERIPHID5_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PERIPHID6_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PERIPHID7_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR0 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR1 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR2 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR3 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CID0_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CID0 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CID1 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CID2 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CID3_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CID3 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+/* ETF Offsets - same offsets for all etfs */
+#define mmETF_RSZ_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RSZ -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_STS_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_STS -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_RRD_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RRD -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_RRP_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RRP -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_RWP_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RWP -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_TRG_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_TRG -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_CTL_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_CTL -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_RWD_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RWD -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_MODE_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_MODE -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_LBUFLEVEL_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_LBUFLEVEL -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_CBUFLEVEL_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_CBUFLEVEL -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_BUFWM_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_BUFWM -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_FFSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_FFSR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_FFCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_FFCR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PSCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PSCR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBMDATA0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBMCTR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBMCTR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBMCTR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITMISCOP0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITMISCOP0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITTRFLIN_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITTRFLIN -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBDATA0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBDATA0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBCTR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBCTR2 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBCTR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBCTR1 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBCTR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBCTR0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITCTRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITCTRL -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_CLAIMSET_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_CLAIMSET -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_CLAIMCLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_CLAIMCLR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_LAR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_LAR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_LSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_LSR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_AUTHSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_AUTHSTATUS -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_DEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_DEVID -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_DEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_DEVTYPE -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID4_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID4 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID5_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID5 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID6_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID6 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID7_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID7 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID1 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID2 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID3_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID3 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_COMPID0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_COMPID0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_COMPID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_COMPID1 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_COMPID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_COMPID2 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_COMPID3_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_COMPID3 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+
+/* STM OFFSETS - same offsets for all stms */
+#define mmSTM_STMDMASTARTR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMASTARTR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDMASTOPR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMASTOPR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDMASTATR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMASTATR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDMACTLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMACTLR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDMAIDR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMAIDR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHETER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHETER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEBSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEBSR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEMCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEMCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEEXTMUXR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEMASTR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEMASTR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEFEAT1R_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEFEAT1R -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEIDR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEIDR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPTER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPTER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPSCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPSCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPMSCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPMSCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPOVERRIDER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPMOVERRIDER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPTRIGCSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMTCSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMTCSR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMTSSTIMR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMTSSTIMR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMTSFREQR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMTSFREQR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSYNCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSYNCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMAUXCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMAUXCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMFEAT1R_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMFEAT1R -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMFEAT2R_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMFEAT2R -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMFEAT3R_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMFEAT3R -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITTRIGGER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITTRIGGER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITATBDATA0_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITATBDATA0 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITATBCTR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITATBCTR2 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITATBID_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITATBID -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITATBCTR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITATBCTR0 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITCTRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITCTRL -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCLAIMSET_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCLAIMSET -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCLAIMCLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCLAIMCLR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMLAR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMLAR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMLSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMLSR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMAUTHSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDEVARCH_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDEVARCH -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDEVID -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDEVTYPE -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR4 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR5_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR5 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR6_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR6 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR7_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR7 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR0 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR1 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR2 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR3 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCIDR0 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCIDR1 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCIDR2 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCIDR3 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+
+/* SPMU OFFSETS - same offsets for all SPMUs */
+#define mmSPMU_PMEVCNTR0_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR1_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR2_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR3_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR4_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR5_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCCNTR_L_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCCNTR_H_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMTRC_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMTRC -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_TRC_CTRL_HOST_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_TRC_STAT_HOST_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_TRC_EN_HOST_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER0_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER1_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER2_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER3_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER4_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER5_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMSSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMSSR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMOVSSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMOVSSR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCCNTSR_L_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCCNTSR_H_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR5_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMSCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMSCR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMSRR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMSRR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCNTENSET_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCNTENCLR_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMINTENSET_EL1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMINTENCLR_EL1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMOVSCLR_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMSWINC_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMOVSSET_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCFGR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCFGR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCR_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMITCTRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMITCTRL -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCLAIMSET_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCLAIMCLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVAFF0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVAFF1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMLAR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMLAR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMLSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMLSR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMAUTHSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVARCH_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVARCH -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVID2 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVID1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVID -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR4 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR5_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR5 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR6_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR6 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR7_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR7 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR2 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR3 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCIDR0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCIDR1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCIDR2 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCIDR3 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+
+/* BMON OFFSETS - same offsets for all BMONs*/
+#define mmBMON_CR_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CR -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_RESET_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_INT_CLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_TRIG_TH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_S0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_S0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_E0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_E0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_S1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_S1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_E1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_E1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_S2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_S2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_E2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_E2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_S3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_S3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_E3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_E3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_REDUCTION_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDL_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDL -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDENL_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDENL -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDENH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDENH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_LATENCY_SMP_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ATTR_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ATTR -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ATTREN_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ATTREN -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_USRENL_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_USRENL -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_USRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_USRL -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_USRENH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_USRENH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_USRH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_USRH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CAPTURE_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_RELEASE_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_RELEASE -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_WIN_CAPTURE_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_BW_WIN_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MATCH_CNT_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MATCH_CNT_WIN_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CYCCNT_L_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CYCCNT_H_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MAXLAT_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MINLAT_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MAXBW_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MINBW_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MAXOS_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MINOS_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDL_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDH_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ATTR_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_STM_TRC_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_STM_TRC_DROP_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_DEVARCH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PMDEVID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PMDEVID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PMDEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_DEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR5_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR6_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR7_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+
+/* Coresight unlock offset */
+#define  mmCORESIGHT_UNLOCK_REGISTER_OFFSET mmSTM_STMLAR_OFFSET
+#define  mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET mmSTM_STMLSR_OFFSET
+
+#endif /* GAUDI2_CORESIGHT_REGS_DRV_H_ */