diff options
| author |  Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 18:24:12 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 18:24:12 -0800 |
| commit | 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 (patch) | |
| tree | cc5c2d0a898769fd59549594fedb3ee6f84e59a0 /drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h | |
| download | linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.tar.gz linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.zip | |
Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted
Pull networking updates from Jakub Kicinski:
"Core:
- Add dedicated kmem_cache for typical/small skb->head, avoid having
to access struct page at kfree time, and improve memory use.
- Introduce sysctl to set default RPS configuration for new netdevs.
- Define Netlink protocol specification format which can be used to
describe messages used by each family and auto-generate parsers.
Add tools for generating kernel data structures and uAPI headers.
- Expose all net/core sysctls inside netns.
- Remove 4s sleep in netpoll if carrier is instantly detected on
boot.
- Add configurable limit of MDB entries per port, and port-vlan.
- Continue populating drop reasons throughout the stack.
- Retire a handful of legacy Qdiscs and classifiers.
Protocols:
- Support IPv4 big TCP (TSO frames larger than 64kB).
- Add IP_LOCAL_PORT_RANGE socket option, to control local port range
on socket by socket basis.
- Track and report in procfs number of MPTCP sockets used.
- Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
manager.
- IPv6: don't check net.ipv6.route.max_size and rely on garbage
collection to free memory (similarly to IPv4).
- Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).
- ICMP: add per-rate limit counters.
- Add support for user scanning requests in ieee802154.
- Remove static WEP support.
- Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
reporting.
- WiFi 7 EHT channel puncturing support (client & AP).
BPF:
- Add a rbtree data structure following the "next-gen data structure"
precedent set by recently added linked list, that is, by using
kfunc + kptr instead of adding a new BPF map type.
- Expose XDP hints via kfuncs with initial support for RX hash and
timestamp metadata.
- Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
better support decap on GRE tunnel devices not operating in collect
metadata.
- Improve x86 JIT's codegen for PROBE_MEM runtime error checks.
- Remove the need for trace_printk_lock for bpf_trace_printk and
bpf_trace_vprintk helpers.
- Extend libbpf's bpf_tracing.h support for tracing arguments of
kprobes/uprobes and syscall as a special case.
- Significantly reduce the search time for module symbols by
livepatch and BPF.
- Enable cpumasks to be used as kptrs, which is useful for tracing
programs tracking which tasks end up running on which CPUs in
different time intervals.
- Add support for BPF trampoline on s390x and riscv64.
- Add capability to export the XDP features supported by the NIC.
- Add __bpf_kfunc tag for marking kernel functions as kfuncs.
- Add cgroup.memory=nobpf kernel parameter option to disable BPF
memory accounting for container environments.
Netfilter:
- Remove the CLUSTERIP target. It has been marked as obsolete for
years, and we still have WARN splats wrt races of the out-of-band
/proc interface installed by this target.
- Add 'destroy' commands to nf_tables. They are identical to the
existing 'delete' commands, but do not return an error if the
referenced object (set, chain, rule...) did not exist.
Driver API:
- Improve cpumask_local_spread() locality to help NICs set the right
IRQ affinity on AMD platforms.
- Separate C22 and C45 MDIO bus transactions more clearly.
- Introduce new DCB table to control DSCP rewrite on egress.
- Support configuration of Physical Layer Collision Avoidance (PLCA)
Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
shared medium Ethernet.
- Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
preemption of low priority frames by high priority frames.
- Add support for controlling MACSec offload using netlink SET.
- Rework devlink instance refcounts to allow registration and
de-registration under the instance lock. Split the code into
multiple files, drop some of the unnecessarily granular locks and
factor out common parts of netlink operation handling.
- Add TX frame aggregation parameters (for USB drivers).
- Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
messages with notifications for debug.
- Allow offloading of UDP NEW connections via act_ct.
- Add support for per action HW stats in TC.
- Support hardware miss to TC action (continue processing in SW from
a specific point in the action chain).
- Warn if old Wireless Extension user space interface is used with
modern cfg80211/mac80211 drivers. Do not support Wireless
Extensions for Wi-Fi 7 devices at all. Everyone should switch to
using nl80211 interface instead.
- Improve the CAN bit timing configuration. Use extack to return
error messages directly to user space, update the SJW handling,
including the definition of a new default value that will benefit
CAN-FD controllers, by increasing their oscillator tolerance.
New hardware / drivers:
- Ethernet:
- nVidia BlueField-3 support (control traffic driver)
- Ethernet support for imx93 SoCs
- Motorcomm yt8531 gigabit Ethernet PHY
- onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
- Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
- Amlogic gxl MDIO mux
- WiFi:
- RealTek RTL8188EU (rtl8xxxu)
- Qualcomm Wi-Fi 7 devices (ath12k)
- CAN:
- Renesas R-Car V4H
Drivers:
- Bluetooth:
- Set Per Platform Antenna Gain (PPAG) for Intel controllers.
- Ethernet NICs:
- Intel (1G, igc):
- support TSN / Qbv / packet scheduling features of i226 model
- Intel (100G, ice):
- use GNSS subsystem instead of TTY
- multi-buffer XDP support
- extend support for GPIO pins to E823 devices
- nVidia/Mellanox:
- update the shared buffer configuration on PFC commands
- implement PTP adjphase function for HW offset control
- TC support for Geneve and GRE with VF tunnel offload
- more efficient crypto key management method
- multi-port eswitch support
- Netronome/Corigine:
- add DCB IEEE support
- support IPsec offloading for NFP3800
- Freescale/NXP (enetc):
- support XDP_REDIRECT for XDP non-linear buffers
- improve reconfig, avoid link flap and waiting for idle
- support MAC Merge layer
- Other NICs:
- sfc/ef100: add basic devlink support for ef100
- ionic: rx_push mode operation (writing descriptors via MMIO)
- bnxt: use the auxiliary bus abstraction for RDMA
- r8169: disable ASPM and reset bus in case of tx timeout
- cpsw: support QSGMII mode for J721e CPSW9G
- cpts: support pulse-per-second output
- ngbe: add an mdio bus driver
- usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
- r8152: handle devices with FW with NCM support
- amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
- virtio-net: support multi buffer XDP
- virtio/vsock: replace virtio_vsock_pkt with sk_buff
- tsnep: XDP support
- Ethernet high-speed switches:
- nVidia/Mellanox (mlxsw):
- add support for latency TLV (in FW control messages)
- Microchip (sparx5):
- separate explicit and implicit traffic forwarding rules, make
the implicit rules always active
- add support for egress DSCP rewrite
- IS0 VCAP support (Ingress Classification)
- IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
etc.)
- ES2 VCAP support (Egress Access Control)
- support for Per-Stream Filtering and Policing (802.1Q,
8.6.5.1)
- Ethernet embedded switches:
- Marvell (mv88e6xxx):
- add MAB (port auth) offload support
- enable PTP receive for mv88e6390
- NXP (ocelot):
- support MAC Merge layer
- support for the the vsc7512 internal copper phys
- Microchip:
- lan9303: convert to PHYLINK
- lan966x: support TC flower filter statistics
- lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
- lan937x: support Credit Based Shaper configuration
- ksz9477: support Energy Efficient Ethernet
- other:
- qca8k: convert to regmap read/write API, use bulk operations
- rswitch: Improve TX timestamp accuracy
- Intel WiFi (iwlwifi):
- EHT (Wi-Fi 7) rate reporting
- STEP equalizer support: transfer some STEP (connection to radio
on platforms with integrated wifi) related parameters from the
BIOS to the firmware.
- Qualcomm 802.11ax WiFi (ath11k):
- IPQ5018 support
- Fine Timing Measurement (FTM) responder role support
- channel 177 support
- MediaTek WiFi (mt76):
- per-PHY LED support
- mt7996: EHT (Wi-Fi 7) support
- Wireless Ethernet Dispatch (WED) reset support
- switch to using page pool allocator
- RealTek WiFi (rtw89):
- support new version of Bluetooth co-existance
- Mobile:
- rmnet: support TX aggregation"
* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
page_pool: add a comment explaining the fragment counter usage
net: ethtool: fix __ethtool_dev_mm_supported() implementation
ethtool: pse-pd: Fix double word in comments
xsk: add linux/vmalloc.h to xsk.c
sefltests: netdevsim: wait for devlink instance after netns removal
selftest: fib_tests: Always cleanup before exit
net/mlx5e: Align IPsec ASO result memory to be as required by hardware
net/mlx5e: TC, Set CT miss to the specific ct action instance
net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
net/mlx5: Refactor tc miss handling to a single function
net/mlx5: Kconfig: Make tc offload depend on tc skb extension
net/sched: flower: Support hardware miss to tc action
net/sched: flower: Move filter handle initialization earlier
net/sched: cls_api: Support hardware miss to tc action
net/sched: Rename user cookie and act cookie
sfc: fix builds without CONFIG_RTC_LIB
sfc: clean up some inconsistent indentings
net/mlx4_en: Introduce flexible array to silence overflow warning
net: lan966x: Fix possible deadlock inside PTP
net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
...
Diffstat (limited to 'drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h')
| -rw-r--r-- | drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h | 834 |
1 files changed, 834 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h new file mode 100644 index 000000000..f9e310ab6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_REGS_H_ +#define ASIC_REG_TPC0_QM_REGS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC0_QM_GLBL_CFG0 0xE08000 + +#define mmTPC0_QM_GLBL_CFG1 0xE08004 + +#define mmTPC0_QM_GLBL_PROT 0xE08008 + +#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C + +#define mmTPC0_QM_GLBL_SECURE_PROPS_0 0xE08010 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_1 0xE08014 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_2 0xE08018 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_3 0xE0801C + +#define mmTPC0_QM_GLBL_SECURE_PROPS_4 0xE08020 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 0xE08024 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 0xE08028 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 0xE0802C + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 0xE08030 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 0xE08034 + +#define mmTPC0_QM_GLBL_STS0 0xE08038 + +#define mmTPC0_QM_GLBL_STS1_0 0xE08040 + +#define mmTPC0_QM_GLBL_STS1_1 0xE08044 + +#define mmTPC0_QM_GLBL_STS1_2 0xE08048 + +#define mmTPC0_QM_GLBL_STS1_3 0xE0804C + +#define mmTPC0_QM_GLBL_STS1_4 0xE08050 + +#define mmTPC0_QM_GLBL_MSG_EN_0 0xE08054 + +#define mmTPC0_QM_GLBL_MSG_EN_1 0xE08058 + +#define mmTPC0_QM_GLBL_MSG_EN_2 0xE0805C + +#define mmTPC0_QM_GLBL_MSG_EN_3 0xE08060 + +#define mmTPC0_QM_GLBL_MSG_EN_4 0xE08068 + +#define mmTPC0_QM_PQ_BASE_LO_0 0xE08070 + +#define mmTPC0_QM_PQ_BASE_LO_1 0xE08074 + +#define mmTPC0_QM_PQ_BASE_LO_2 0xE08078 + +#define mmTPC0_QM_PQ_BASE_LO_3 0xE0807C + +#define mmTPC0_QM_PQ_BASE_HI_0 0xE08080 + +#define mmTPC0_QM_PQ_BASE_HI_1 0xE08084 + +#define mmTPC0_QM_PQ_BASE_HI_2 0xE08088 + +#define mmTPC0_QM_PQ_BASE_HI_3 0xE0808C + +#define mmTPC0_QM_PQ_SIZE_0 0xE08090 + +#define mmTPC0_QM_PQ_SIZE_1 0xE08094 + +#define mmTPC0_QM_PQ_SIZE_2 0xE08098 + +#define mmTPC0_QM_PQ_SIZE_3 0xE0809C + +#define mmTPC0_QM_PQ_PI_0 0xE080A0 + +#define mmTPC0_QM_PQ_PI_1 0xE080A4 + +#define mmTPC0_QM_PQ_PI_2 0xE080A8 + +#define mmTPC0_QM_PQ_PI_3 0xE080AC + +#define mmTPC0_QM_PQ_CI_0 0xE080B0 + +#define mmTPC0_QM_PQ_CI_1 0xE080B4 + +#define mmTPC0_QM_PQ_CI_2 0xE080B8 + +#define mmTPC0_QM_PQ_CI_3 0xE080BC + +#define mmTPC0_QM_PQ_CFG0_0 0xE080C0 + +#define mmTPC0_QM_PQ_CFG0_1 0xE080C4 + +#define mmTPC0_QM_PQ_CFG0_2 0xE080C8 + +#define mmTPC0_QM_PQ_CFG0_3 0xE080CC + +#define mmTPC0_QM_PQ_CFG1_0 0xE080D0 + +#define mmTPC0_QM_PQ_CFG1_1 0xE080D4 + +#define mmTPC0_QM_PQ_CFG1_2 0xE080D8 + +#define mmTPC0_QM_PQ_CFG1_3 0xE080DC + +#define mmTPC0_QM_PQ_ARUSER_31_11_0 0xE080E0 + +#define mmTPC0_QM_PQ_ARUSER_31_11_1 0xE080E4 + +#define mmTPC0_QM_PQ_ARUSER_31_11_2 0xE080E8 + +#define mmTPC0_QM_PQ_ARUSER_31_11_3 0xE080EC + +#define mmTPC0_QM_PQ_STS0_0 0xE080F0 + +#define mmTPC0_QM_PQ_STS0_1 0xE080F4 + +#define mmTPC0_QM_PQ_STS0_2 0xE080F8 + +#define mmTPC0_QM_PQ_STS0_3 0xE080FC + +#define mmTPC0_QM_PQ_STS1_0 0xE08100 + +#define mmTPC0_QM_PQ_STS1_1 0xE08104 + +#define mmTPC0_QM_PQ_STS1_2 0xE08108 + +#define mmTPC0_QM_PQ_STS1_3 0xE0810C + +#define mmTPC0_QM_CQ_CFG0_0 0xE08110 + +#define mmTPC0_QM_CQ_CFG0_1 0xE08114 + +#define mmTPC0_QM_CQ_CFG0_2 0xE08118 + +#define mmTPC0_QM_CQ_CFG0_3 0xE0811C + +#define mmTPC0_QM_CQ_CFG0_4 0xE08120 + +#define mmTPC0_QM_CQ_CFG1_0 0xE08124 + +#define mmTPC0_QM_CQ_CFG1_1 0xE08128 + +#define mmTPC0_QM_CQ_CFG1_2 0xE0812C + +#define mmTPC0_QM_CQ_CFG1_3 0xE08130 + +#define mmTPC0_QM_CQ_CFG1_4 0xE08134 + +#define mmTPC0_QM_CQ_ARUSER_31_11_0 0xE08138 + +#define mmTPC0_QM_CQ_ARUSER_31_11_1 0xE0813C + +#define mmTPC0_QM_CQ_ARUSER_31_11_2 0xE08140 + +#define mmTPC0_QM_CQ_ARUSER_31_11_3 0xE08144 + +#define mmTPC0_QM_CQ_ARUSER_31_11_4 0xE08148 + +#define mmTPC0_QM_CQ_STS0_0 0xE0814C + +#define mmTPC0_QM_CQ_STS0_1 0xE08150 + +#define mmTPC0_QM_CQ_STS0_2 0xE08154 + +#define mmTPC0_QM_CQ_STS0_3 0xE08158 + +#define mmTPC0_QM_CQ_STS0_4 0xE0815C + +#define mmTPC0_QM_CQ_STS1_0 0xE08160 + +#define mmTPC0_QM_CQ_STS1_1 0xE08164 + +#define mmTPC0_QM_CQ_STS1_2 0xE08168 + +#define mmTPC0_QM_CQ_STS1_3 0xE0816C + +#define mmTPC0_QM_CQ_STS1_4 0xE08170 + +#define mmTPC0_QM_CQ_PTR_LO_0 0xE08174 + +#define mmTPC0_QM_CQ_PTR_HI_0 0xE08178 + +#define mmTPC0_QM_CQ_TSIZE_0 0xE0817C + +#define mmTPC0_QM_CQ_CTL_0 0xE08180 + +#define mmTPC0_QM_CQ_PTR_LO_1 0xE08184 + +#define mmTPC0_QM_CQ_PTR_HI_1 0xE08188 + +#define mmTPC0_QM_CQ_TSIZE_1 0xE0818C + +#define mmTPC0_QM_CQ_CTL_1 0xE08190 + +#define mmTPC0_QM_CQ_PTR_LO_2 0xE08194 + +#define mmTPC0_QM_CQ_PTR_HI_2 0xE08198 + +#define mmTPC0_QM_CQ_TSIZE_2 0xE0819C + +#define mmTPC0_QM_CQ_CTL_2 0xE081A0 + +#define mmTPC0_QM_CQ_PTR_LO_3 0xE081A4 + +#define mmTPC0_QM_CQ_PTR_HI_3 0xE081A8 + +#define mmTPC0_QM_CQ_TSIZE_3 0xE081AC + +#define mmTPC0_QM_CQ_CTL_3 0xE081B0 + +#define mmTPC0_QM_CQ_PTR_LO_4 0xE081B4 + +#define mmTPC0_QM_CQ_PTR_HI_4 0xE081B8 + +#define mmTPC0_QM_CQ_TSIZE_4 0xE081BC + +#define mmTPC0_QM_CQ_CTL_4 0xE081C0 + +#define mmTPC0_QM_CQ_PTR_LO_STS_0 0xE081C4 + +#define mmTPC0_QM_CQ_PTR_LO_STS_1 0xE081C8 + +#define mmTPC0_QM_CQ_PTR_LO_STS_2 0xE081CC + +#define mmTPC0_QM_CQ_PTR_LO_STS_3 0xE081D0 + +#define mmTPC0_QM_CQ_PTR_LO_STS_4 0xE081D4 + +#define mmTPC0_QM_CQ_PTR_HI_STS_0 0xE081D8 + +#define mmTPC0_QM_CQ_PTR_HI_STS_1 0xE081DC + +#define mmTPC0_QM_CQ_PTR_HI_STS_2 0xE081E0 + +#define mmTPC0_QM_CQ_PTR_HI_STS_3 0xE081E4 + +#define mmTPC0_QM_CQ_PTR_HI_STS_4 0xE081E8 + +#define mmTPC0_QM_CQ_TSIZE_STS_0 0xE081EC + +#define mmTPC0_QM_CQ_TSIZE_STS_1 0xE081F0 + +#define mmTPC0_QM_CQ_TSIZE_STS_2 0xE081F4 + +#define mmTPC0_QM_CQ_TSIZE_STS_3 0xE081F8 + +#define mmTPC0_QM_CQ_TSIZE_STS_4 0xE081FC + +#define mmTPC0_QM_CQ_CTL_STS_0 0xE08200 + +#define mmTPC0_QM_CQ_CTL_STS_1 0xE08204 + +#define mmTPC0_QM_CQ_CTL_STS_2 0xE08208 + +#define mmTPC0_QM_CQ_CTL_STS_3 0xE0820C + +#define mmTPC0_QM_CQ_CTL_STS_4 0xE08210 + +#define mmTPC0_QM_CQ_IFIFO_CNT_0 0xE08214 + +#define mmTPC0_QM_CQ_IFIFO_CNT_1 0xE08218 + +#define mmTPC0_QM_CQ_IFIFO_CNT_2 0xE0821C + +#define mmTPC0_QM_CQ_IFIFO_CNT_3 0xE08220 + +#define mmTPC0_QM_CQ_IFIFO_CNT_4 0xE08224 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0xE08228 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0xE0822C + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0xE08230 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0xE08234 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0xE08238 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0xE0823C + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0xE08240 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0xE08244 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0xE08248 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0xE0824C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0xE08250 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0xE08254 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0xE08258 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0xE0825C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0xE08260 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0xE08264 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0xE08268 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0xE0826C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0xE08270 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0xE08274 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0xE08278 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0xE0827C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0xE08280 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0xE08284 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0xE08288 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0xE0828C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0xE08290 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0xE08294 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0xE08298 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0xE0829C + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0xE082A0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0xE082A4 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0xE082A8 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0xE082AC + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0xE082B0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0xE082B4 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0xE082B8 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0xE082BC + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0xE082C0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0xE082C4 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 0xE082C8 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 0xE082CC + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 0xE082D0 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 0xE082D4 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 0xE082D8 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE082E0 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE082E4 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE082E8 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE082EC + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE082F0 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE082F4 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE082F8 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE082FC + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE08300 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE08304 + +#define mmTPC0_QM_CP_FENCE0_RDATA_0 0xE08308 + +#define mmTPC0_QM_CP_FENCE0_RDATA_1 0xE0830C + +#define mmTPC0_QM_CP_FENCE0_RDATA_2 0xE08310 + +#define mmTPC0_QM_CP_FENCE0_RDATA_3 0xE08314 + +#define mmTPC0_QM_CP_FENCE0_RDATA_4 0xE08318 + +#define mmTPC0_QM_CP_FENCE1_RDATA_0 0xE0831C + +#define mmTPC0_QM_CP_FENCE1_RDATA_1 0xE08320 + +#define mmTPC0_QM_CP_FENCE1_RDATA_2 0xE08324 + +#define mmTPC0_QM_CP_FENCE1_RDATA_3 0xE08328 + +#define mmTPC0_QM_CP_FENCE1_RDATA_4 0xE0832C + +#define mmTPC0_QM_CP_FENCE2_RDATA_0 0xE08330 + +#define mmTPC0_QM_CP_FENCE2_RDATA_1 0xE08334 + +#define mmTPC0_QM_CP_FENCE2_RDATA_2 0xE08338 + +#define mmTPC0_QM_CP_FENCE2_RDATA_3 0xE0833C + +#define mmTPC0_QM_CP_FENCE2_RDATA_4 0xE08340 + +#define mmTPC0_QM_CP_FENCE3_RDATA_0 0xE08344 + +#define mmTPC0_QM_CP_FENCE3_RDATA_1 0xE08348 + +#define mmTPC0_QM_CP_FENCE3_RDATA_2 0xE0834C + +#define mmTPC0_QM_CP_FENCE3_RDATA_3 0xE08350 + +#define mmTPC0_QM_CP_FENCE3_RDATA_4 0xE08354 + +#define mmTPC0_QM_CP_FENCE0_CNT_0 0xE08358 + +#define mmTPC0_QM_CP_FENCE0_CNT_1 0xE0835C + +#define mmTPC0_QM_CP_FENCE0_CNT_2 0xE08360 + +#define mmTPC0_QM_CP_FENCE0_CNT_3 0xE08364 + +#define mmTPC0_QM_CP_FENCE0_CNT_4 0xE08368 + +#define mmTPC0_QM_CP_FENCE1_CNT_0 0xE0836C + +#define mmTPC0_QM_CP_FENCE1_CNT_1 0xE08370 + +#define mmTPC0_QM_CP_FENCE1_CNT_2 0xE08374 + +#define mmTPC0_QM_CP_FENCE1_CNT_3 0xE08378 + +#define mmTPC0_QM_CP_FENCE1_CNT_4 0xE0837C + +#define mmTPC0_QM_CP_FENCE2_CNT_0 0xE08380 + +#define mmTPC0_QM_CP_FENCE2_CNT_1 0xE08384 + +#define mmTPC0_QM_CP_FENCE2_CNT_2 0xE08388 + +#define mmTPC0_QM_CP_FENCE2_CNT_3 0xE0838C + +#define mmTPC0_QM_CP_FENCE2_CNT_4 0xE08390 + +#define mmTPC0_QM_CP_FENCE3_CNT_0 0xE08394 + +#define mmTPC0_QM_CP_FENCE3_CNT_1 0xE08398 + +#define mmTPC0_QM_CP_FENCE3_CNT_2 0xE0839C + +#define mmTPC0_QM_CP_FENCE3_CNT_3 0xE083A0 + +#define mmTPC0_QM_CP_FENCE3_CNT_4 0xE083A4 + +#define mmTPC0_QM_CP_STS_0 0xE083A8 + +#define mmTPC0_QM_CP_STS_1 0xE083AC + +#define mmTPC0_QM_CP_STS_2 0xE083B0 + +#define mmTPC0_QM_CP_STS_3 0xE083B4 + +#define mmTPC0_QM_CP_STS_4 0xE083B8 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_0 0xE083BC + +#define mmTPC0_QM_CP_CURRENT_INST_LO_1 0xE083C0 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_2 0xE083C4 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_3 0xE083C8 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_4 0xE083CC + +#define mmTPC0_QM_CP_CURRENT_INST_HI_0 0xE083D0 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_1 0xE083D4 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_2 0xE083D8 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_3 0xE083DC + +#define mmTPC0_QM_CP_CURRENT_INST_HI_4 0xE083E0 + +#define mmTPC0_QM_CP_BARRIER_CFG_0 0xE083F4 + +#define mmTPC0_QM_CP_BARRIER_CFG_1 0xE083F8 + +#define mmTPC0_QM_CP_BARRIER_CFG_2 0xE083FC + +#define mmTPC0_QM_CP_BARRIER_CFG_3 0xE08400 + +#define mmTPC0_QM_CP_BARRIER_CFG_4 0xE08404 + +#define mmTPC0_QM_CP_DBG_0_0 0xE08408 + +#define mmTPC0_QM_CP_DBG_0_1 0xE0840C + +#define mmTPC0_QM_CP_DBG_0_2 0xE08410 + +#define mmTPC0_QM_CP_DBG_0_3 0xE08414 + +#define mmTPC0_QM_CP_DBG_0_4 0xE08418 + +#define mmTPC0_QM_CP_ARUSER_31_11_0 0xE0841C + +#define mmTPC0_QM_CP_ARUSER_31_11_1 0xE08420 + +#define mmTPC0_QM_CP_ARUSER_31_11_2 0xE08424 + +#define mmTPC0_QM_CP_ARUSER_31_11_3 0xE08428 + +#define mmTPC0_QM_CP_ARUSER_31_11_4 0xE0842C + +#define mmTPC0_QM_CP_AWUSER_31_11_0 0xE08430 + +#define mmTPC0_QM_CP_AWUSER_31_11_1 0xE08434 + +#define mmTPC0_QM_CP_AWUSER_31_11_2 0xE08438 + +#define mmTPC0_QM_CP_AWUSER_31_11_3 0xE0843C + +#define mmTPC0_QM_CP_AWUSER_31_11_4 0xE08440 + +#define mmTPC0_QM_ARB_CFG_0 0xE08A00 + +#define mmTPC0_QM_ARB_CHOISE_Q_PUSH 0xE08A04 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_0 0xE08A08 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_1 0xE08A0C + +#define mmTPC0_QM_ARB_WRR_WEIGHT_2 0xE08A10 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_3 0xE08A14 + +#define mmTPC0_QM_ARB_CFG_1 0xE08A18 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_0 0xE08A20 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_1 0xE08A24 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_2 0xE08A28 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_3 0xE08A2C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_4 0xE08A30 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_5 0xE08A34 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_6 0xE08A38 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_7 0xE08A3C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_8 0xE08A40 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_9 0xE08A44 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_10 0xE08A48 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_11 0xE08A4C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_12 0xE08A50 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_13 0xE08A54 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_14 0xE08A58 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_15 0xE08A5C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_16 0xE08A60 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_17 0xE08A64 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_18 0xE08A68 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_19 0xE08A6C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_20 0xE08A70 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_21 0xE08A74 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_22 0xE08A78 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_23 0xE08A7C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_24 0xE08A80 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_25 0xE08A84 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_26 0xE08A88 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_27 0xE08A8C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_28 0xE08A90 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_29 0xE08A94 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_30 0xE08A98 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_31 0xE08A9C + +#define mmTPC0_QM_ARB_MST_CRED_INC 0xE08AA0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE08AA4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE08AA8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE08AAC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE08AB0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE08AB4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE08AB8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE08ABC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE08AC0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE08AC4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE08AC8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE08ACC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE08AD0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE08AD4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE08AD8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE08ADC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE08AE0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE08AE4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE08AE8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE08AEC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE08AF0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE08AF4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE08AF8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE08AFC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE08B00 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE08B04 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE08B08 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE08B0C + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE08B10 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE08B14 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE08B18 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE08B1C + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE08B20 + +#define mmTPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE08B28 + +#define mmTPC0_QM_ARB_MST_SLAVE_EN 0xE08B2C + +#define mmTPC0_QM_ARB_MST_QUIET_PER 0xE08B34 + +#define mmTPC0_QM_ARB_SLV_CHOISE_WDT 0xE08B38 + +#define mmTPC0_QM_ARB_SLV_ID 0xE08B3C + +#define mmTPC0_QM_ARB_MSG_MAX_INFLIGHT 0xE08B44 + +#define mmTPC0_QM_ARB_MSG_AWUSER_31_11 0xE08B48 + +#define mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP 0xE08B4C + +#define mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE08B50 + +#define mmTPC0_QM_ARB_BASE_LO 0xE08B54 + +#define mmTPC0_QM_ARB_BASE_HI 0xE08B58 + +#define mmTPC0_QM_ARB_STATE_STS 0xE08B80 + +#define mmTPC0_QM_ARB_CHOISE_FULLNESS_STS 0xE08B84 + +#define mmTPC0_QM_ARB_MSG_STS 0xE08B88 + +#define mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD 0xE08B8C + +#define mmTPC0_QM_ARB_ERR_CAUSE 0xE08B9C + +#define mmTPC0_QM_ARB_ERR_MSG_EN 0xE08BA0 + +#define mmTPC0_QM_ARB_ERR_STS_DRP 0xE08BA8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_0 0xE08BB0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_1 0xE08BB4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_2 0xE08BB8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_3 0xE08BBC + +#define mmTPC0_QM_ARB_MST_CRED_STS_4 0xE08BC0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_5 0xE08BC4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_6 0xE08BC8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_7 0xE08BCC + +#define mmTPC0_QM_ARB_MST_CRED_STS_8 0xE08BD0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_9 0xE08BD4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_10 0xE08BD8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_11 0xE08BDC + +#define mmTPC0_QM_ARB_MST_CRED_STS_12 0xE08BE0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_13 0xE08BE4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_14 0xE08BE8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_15 0xE08BEC + +#define mmTPC0_QM_ARB_MST_CRED_STS_16 0xE08BF0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_17 0xE08BF4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_18 0xE08BF8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_19 0xE08BFC + +#define mmTPC0_QM_ARB_MST_CRED_STS_20 0xE08C00 + +#define mmTPC0_QM_ARB_MST_CRED_STS_21 0xE08C04 + +#define mmTPC0_QM_ARB_MST_CRED_STS_22 0xE08C08 + +#define mmTPC0_QM_ARB_MST_CRED_STS_23 0xE08C0C + +#define mmTPC0_QM_ARB_MST_CRED_STS_24 0xE08C10 + +#define mmTPC0_QM_ARB_MST_CRED_STS_25 0xE08C14 + +#define mmTPC0_QM_ARB_MST_CRED_STS_26 0xE08C18 + +#define mmTPC0_QM_ARB_MST_CRED_STS_27 0xE08C1C + +#define mmTPC0_QM_ARB_MST_CRED_STS_28 0xE08C20 + +#define mmTPC0_QM_ARB_MST_CRED_STS_29 0xE08C24 + +#define mmTPC0_QM_ARB_MST_CRED_STS_30 0xE08C28 + +#define mmTPC0_QM_ARB_MST_CRED_STS_31 0xE08C2C + +#define mmTPC0_QM_CGM_CFG 0xE08C70 + +#define mmTPC0_QM_CGM_STS 0xE08C74 + +#define mmTPC0_QM_CGM_CFG1 0xE08C78 + +#define mmTPC0_QM_LOCAL_RANGE_BASE 0xE08C80 + +#define mmTPC0_QM_LOCAL_RANGE_SIZE 0xE08C84 + +#define mmTPC0_QM_CSMR_STRICT_PRIO_CFG 0xE08C90 + +#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 0xE08C94 + +#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 0xE08C98 + +#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 0xE08C9C + +#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 0xE08CA0 + +#define mmTPC0_QM_GLBL_AXCACHE 0xE08CA4 + +#define mmTPC0_QM_IND_GW_APB_CFG 0xE08CB0 + +#define mmTPC0_QM_IND_GW_APB_WDATA 0xE08CB4 + +#define mmTPC0_QM_IND_GW_APB_RDATA 0xE08CB8 + +#define mmTPC0_QM_IND_GW_APB_STATUS 0xE08CBC + +#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08CD0 + +#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08CD4 + +#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08CD8 + +#define mmTPC0_QM_GLBL_MEM_INIT_BUSY 0xE08D00 + +#endif /* ASIC_REG_TPC0_QM_REGS_H_ */ |