diff options
| author |  Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 18:24:12 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 18:24:12 -0800 |
| commit | 5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 (patch) | |
| tree | cc5c2d0a898769fd59549594fedb3ee6f84e59a0 /drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h | |
| download | linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.tar.gz linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.zip | |
Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted
Pull networking updates from Jakub Kicinski:
"Core:
- Add dedicated kmem_cache for typical/small skb->head, avoid having
to access struct page at kfree time, and improve memory use.
- Introduce sysctl to set default RPS configuration for new netdevs.
- Define Netlink protocol specification format which can be used to
describe messages used by each family and auto-generate parsers.
Add tools for generating kernel data structures and uAPI headers.
- Expose all net/core sysctls inside netns.
- Remove 4s sleep in netpoll if carrier is instantly detected on
boot.
- Add configurable limit of MDB entries per port, and port-vlan.
- Continue populating drop reasons throughout the stack.
- Retire a handful of legacy Qdiscs and classifiers.
Protocols:
- Support IPv4 big TCP (TSO frames larger than 64kB).
- Add IP_LOCAL_PORT_RANGE socket option, to control local port range
on socket by socket basis.
- Track and report in procfs number of MPTCP sockets used.
- Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
manager.
- IPv6: don't check net.ipv6.route.max_size and rely on garbage
collection to free memory (similarly to IPv4).
- Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).
- ICMP: add per-rate limit counters.
- Add support for user scanning requests in ieee802154.
- Remove static WEP support.
- Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
reporting.
- WiFi 7 EHT channel puncturing support (client & AP).
BPF:
- Add a rbtree data structure following the "next-gen data structure"
precedent set by recently added linked list, that is, by using
kfunc + kptr instead of adding a new BPF map type.
- Expose XDP hints via kfuncs with initial support for RX hash and
timestamp metadata.
- Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
better support decap on GRE tunnel devices not operating in collect
metadata.
- Improve x86 JIT's codegen for PROBE_MEM runtime error checks.
- Remove the need for trace_printk_lock for bpf_trace_printk and
bpf_trace_vprintk helpers.
- Extend libbpf's bpf_tracing.h support for tracing arguments of
kprobes/uprobes and syscall as a special case.
- Significantly reduce the search time for module symbols by
livepatch and BPF.
- Enable cpumasks to be used as kptrs, which is useful for tracing
programs tracking which tasks end up running on which CPUs in
different time intervals.
- Add support for BPF trampoline on s390x and riscv64.
- Add capability to export the XDP features supported by the NIC.
- Add __bpf_kfunc tag for marking kernel functions as kfuncs.
- Add cgroup.memory=nobpf kernel parameter option to disable BPF
memory accounting for container environments.
Netfilter:
- Remove the CLUSTERIP target. It has been marked as obsolete for
years, and we still have WARN splats wrt races of the out-of-band
/proc interface installed by this target.
- Add 'destroy' commands to nf_tables. They are identical to the
existing 'delete' commands, but do not return an error if the
referenced object (set, chain, rule...) did not exist.
Driver API:
- Improve cpumask_local_spread() locality to help NICs set the right
IRQ affinity on AMD platforms.
- Separate C22 and C45 MDIO bus transactions more clearly.
- Introduce new DCB table to control DSCP rewrite on egress.
- Support configuration of Physical Layer Collision Avoidance (PLCA)
Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
shared medium Ethernet.
- Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
preemption of low priority frames by high priority frames.
- Add support for controlling MACSec offload using netlink SET.
- Rework devlink instance refcounts to allow registration and
de-registration under the instance lock. Split the code into
multiple files, drop some of the unnecessarily granular locks and
factor out common parts of netlink operation handling.
- Add TX frame aggregation parameters (for USB drivers).
- Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
messages with notifications for debug.
- Allow offloading of UDP NEW connections via act_ct.
- Add support for per action HW stats in TC.
- Support hardware miss to TC action (continue processing in SW from
a specific point in the action chain).
- Warn if old Wireless Extension user space interface is used with
modern cfg80211/mac80211 drivers. Do not support Wireless
Extensions for Wi-Fi 7 devices at all. Everyone should switch to
using nl80211 interface instead.
- Improve the CAN bit timing configuration. Use extack to return
error messages directly to user space, update the SJW handling,
including the definition of a new default value that will benefit
CAN-FD controllers, by increasing their oscillator tolerance.
New hardware / drivers:
- Ethernet:
- nVidia BlueField-3 support (control traffic driver)
- Ethernet support for imx93 SoCs
- Motorcomm yt8531 gigabit Ethernet PHY
- onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
- Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
- Amlogic gxl MDIO mux
- WiFi:
- RealTek RTL8188EU (rtl8xxxu)
- Qualcomm Wi-Fi 7 devices (ath12k)
- CAN:
- Renesas R-Car V4H
Drivers:
- Bluetooth:
- Set Per Platform Antenna Gain (PPAG) for Intel controllers.
- Ethernet NICs:
- Intel (1G, igc):
- support TSN / Qbv / packet scheduling features of i226 model
- Intel (100G, ice):
- use GNSS subsystem instead of TTY
- multi-buffer XDP support
- extend support for GPIO pins to E823 devices
- nVidia/Mellanox:
- update the shared buffer configuration on PFC commands
- implement PTP adjphase function for HW offset control
- TC support for Geneve and GRE with VF tunnel offload
- more efficient crypto key management method
- multi-port eswitch support
- Netronome/Corigine:
- add DCB IEEE support
- support IPsec offloading for NFP3800
- Freescale/NXP (enetc):
- support XDP_REDIRECT for XDP non-linear buffers
- improve reconfig, avoid link flap and waiting for idle
- support MAC Merge layer
- Other NICs:
- sfc/ef100: add basic devlink support for ef100
- ionic: rx_push mode operation (writing descriptors via MMIO)
- bnxt: use the auxiliary bus abstraction for RDMA
- r8169: disable ASPM and reset bus in case of tx timeout
- cpsw: support QSGMII mode for J721e CPSW9G
- cpts: support pulse-per-second output
- ngbe: add an mdio bus driver
- usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
- r8152: handle devices with FW with NCM support
- amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
- virtio-net: support multi buffer XDP
- virtio/vsock: replace virtio_vsock_pkt with sk_buff
- tsnep: XDP support
- Ethernet high-speed switches:
- nVidia/Mellanox (mlxsw):
- add support for latency TLV (in FW control messages)
- Microchip (sparx5):
- separate explicit and implicit traffic forwarding rules, make
the implicit rules always active
- add support for egress DSCP rewrite
- IS0 VCAP support (Ingress Classification)
- IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
etc.)
- ES2 VCAP support (Egress Access Control)
- support for Per-Stream Filtering and Policing (802.1Q,
8.6.5.1)
- Ethernet embedded switches:
- Marvell (mv88e6xxx):
- add MAB (port auth) offload support
- enable PTP receive for mv88e6390
- NXP (ocelot):
- support MAC Merge layer
- support for the the vsc7512 internal copper phys
- Microchip:
- lan9303: convert to PHYLINK
- lan966x: support TC flower filter statistics
- lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
- lan937x: support Credit Based Shaper configuration
- ksz9477: support Energy Efficient Ethernet
- other:
- qca8k: convert to regmap read/write API, use bulk operations
- rswitch: Improve TX timestamp accuracy
- Intel WiFi (iwlwifi):
- EHT (Wi-Fi 7) rate reporting
- STEP equalizer support: transfer some STEP (connection to radio
on platforms with integrated wifi) related parameters from the
BIOS to the firmware.
- Qualcomm 802.11ax WiFi (ath11k):
- IPQ5018 support
- Fine Timing Measurement (FTM) responder role support
- channel 177 support
- MediaTek WiFi (mt76):
- per-PHY LED support
- mt7996: EHT (Wi-Fi 7) support
- Wireless Ethernet Dispatch (WED) reset support
- switch to using page pool allocator
- RealTek WiFi (rtw89):
- support new version of Bluetooth co-existance
- Mobile:
- rmnet: support TX aggregation"
* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
page_pool: add a comment explaining the fragment counter usage
net: ethtool: fix __ethtool_dev_mm_supported() implementation
ethtool: pse-pd: Fix double word in comments
xsk: add linux/vmalloc.h to xsk.c
sefltests: netdevsim: wait for devlink instance after netns removal
selftest: fib_tests: Always cleanup before exit
net/mlx5e: Align IPsec ASO result memory to be as required by hardware
net/mlx5e: TC, Set CT miss to the specific ct action instance
net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
net/mlx5: Refactor tc miss handling to a single function
net/mlx5: Kconfig: Make tc offload depend on tc skb extension
net/sched: flower: Support hardware miss to tc action
net/sched: flower: Move filter handle initialization earlier
net/sched: cls_api: Support hardware miss to tc action
net/sched: Rename user cookie and act cookie
sfc: fix builds without CONFIG_RTC_LIB
sfc: clean up some inconsistent indentings
net/mlx4_en: Introduce flexible array to silence overflow warning
net: lan966x: Fix possible deadlock inside PTP
net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
...
Diffstat (limited to 'drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h')
| -rw-r--r-- | drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h | 1226 |
1 files changed, 1226 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h new file mode 100644 index 000000000..3e77c3795 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_CFG_REGS_H_ +#define ASIC_REG_TPC2_CFG_REGS_H_ + +/* + ***************************************** + * TPC2_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE86418 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8641C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86420 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE86424 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86428 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8642C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86430 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86434 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE86438 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8643C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86440 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86444 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE86448 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8644C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86450 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE86454 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86458 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8645C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86460 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86464 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE86468 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8646C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86470 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE86474 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE86478 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE8647C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE86480 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE86484 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE86488 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE8648C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE86490 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE86494 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE86498 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE8649C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864AC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864BC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE864C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE864C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE864C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE864CC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE864D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE864D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE864D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE864DC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE864E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE864E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE864E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE864EC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE864F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE864F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE864F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE864FC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86500 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE86504 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86508 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE8650C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86510 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86514 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE86518 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE8651C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86520 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86524 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE86528 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE8652C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86530 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE86534 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE86538 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE8653C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE86540 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE86544 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE86548 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE8654C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE86550 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE86554 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE86558 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE8655C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE86560 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE86564 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE86568 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE8656C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE86570 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE86574 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE86578 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE8657C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86580 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE86584 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86588 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE8658C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE86590 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86594 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86598 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE8659C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE865A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE865A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE865A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE865AC + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE865B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE865B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE865B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE865BC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE865C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE865C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE865C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE865CC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE865D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE865D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE865D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE865DC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE865E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE865E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE865E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE865EC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE865F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE865F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE865F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE865FC + +#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE86600 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE86604 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE86608 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE8660C + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE86610 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE86614 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE86618 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE8661C + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE86620 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE86624 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE86628 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE8662C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE86630 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE86634 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE86638 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE8663C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE86640 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE86644 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE86648 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE8664C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE86650 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE86654 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE86658 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE8665C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE86660 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE86664 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE86668 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE8666C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE86670 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE86674 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE86678 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE8667C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE86680 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE86684 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE86688 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE8668C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE86690 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE86694 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE86698 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE8669C + +#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE866A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE866A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE866A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE866AC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE866B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE866B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE866B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE866BC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE866C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE866C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE866C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE866CC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE866D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE866D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE866D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE866DC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE866E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE866E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE866E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE866EC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE866F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE866F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE866F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE866FC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE86700 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE86704 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE86708 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE8670C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE86710 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE86714 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE86718 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE8671C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE86720 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE86724 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE86728 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE8672C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE86730 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE86734 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE86738 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE8673C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE86740 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE86744 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE86748 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE8674C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE86750 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE86754 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE86758 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE8675C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE86760 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE86764 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE86768 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE8676C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE86770 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE86774 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE86778 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE8677C + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86780 + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE86784 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86788 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE8678C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86790 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE86794 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86798 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE8679C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE867A0 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE867A4 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE867A8 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE867AC + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE867B0 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE867B4 + +#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE867B8 + +#define mmTPC2_CFG_KERNEL_KERNEL_ID 0xE867BC + +#define mmTPC2_CFG_KERNEL_SRF_0 0xE867C0 + +#define mmTPC2_CFG_KERNEL_SRF_1 0xE867C4 + +#define mmTPC2_CFG_KERNEL_SRF_2 0xE867C8 + +#define mmTPC2_CFG_KERNEL_SRF_3 0xE867CC + +#define mmTPC2_CFG_KERNEL_SRF_4 0xE867D0 + +#define mmTPC2_CFG_KERNEL_SRF_5 0xE867D4 + +#define mmTPC2_CFG_KERNEL_SRF_6 0xE867D8 + +#define mmTPC2_CFG_KERNEL_SRF_7 0xE867DC + +#define mmTPC2_CFG_KERNEL_SRF_8 0xE867E0 + +#define mmTPC2_CFG_KERNEL_SRF_9 0xE867E4 + +#define mmTPC2_CFG_KERNEL_SRF_10 0xE867E8 + +#define mmTPC2_CFG_KERNEL_SRF_11 0xE867EC + +#define mmTPC2_CFG_KERNEL_SRF_12 0xE867F0 + +#define mmTPC2_CFG_KERNEL_SRF_13 0xE867F4 + +#define mmTPC2_CFG_KERNEL_SRF_14 0xE867F8 + +#define mmTPC2_CFG_KERNEL_SRF_15 0xE867FC + +#define mmTPC2_CFG_KERNEL_SRF_16 0xE86800 + +#define mmTPC2_CFG_KERNEL_SRF_17 0xE86804 + +#define mmTPC2_CFG_KERNEL_SRF_18 0xE86808 + +#define mmTPC2_CFG_KERNEL_SRF_19 0xE8680C + +#define mmTPC2_CFG_KERNEL_SRF_20 0xE86810 + +#define mmTPC2_CFG_KERNEL_SRF_21 0xE86814 + +#define mmTPC2_CFG_KERNEL_SRF_22 0xE86818 + +#define mmTPC2_CFG_KERNEL_SRF_23 0xE8681C + +#define mmTPC2_CFG_KERNEL_SRF_24 0xE86820 + +#define mmTPC2_CFG_KERNEL_SRF_25 0xE86824 + +#define mmTPC2_CFG_KERNEL_SRF_26 0xE86828 + +#define mmTPC2_CFG_KERNEL_SRF_27 0xE8682C + +#define mmTPC2_CFG_KERNEL_SRF_28 0xE86830 + +#define mmTPC2_CFG_KERNEL_SRF_29 0xE86834 + +#define mmTPC2_CFG_KERNEL_SRF_30 0xE86838 + +#define mmTPC2_CFG_KERNEL_SRF_31 0xE8683C + +#define mmTPC2_CFG_ROUND_CSR 0xE868FC + +#define mmTPC2_CFG_PROT 0xE86900 + +#define mmTPC2_CFG_SEMAPHORE 0xE86908 + +#define mmTPC2_CFG_VFLAGS 0xE8690C + +#define mmTPC2_CFG_SFLAGS 0xE86910 + +#define mmTPC2_CFG_LFSR_POLYNOM 0xE86918 + +#define mmTPC2_CFG_STATUS 0xE8691C + +#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86920 + +#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86924 + +#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8692C + +#define mmTPC2_CFG_TPC_CMD 0xE86930 + +#define mmTPC2_CFG_TPC_EXECUTE 0xE86938 + +#define mmTPC2_CFG_TPC_STALL 0xE8693C + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86940 + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86944 + +#define mmTPC2_CFG_RD_RATE_LIMIT 0xE86948 + +#define mmTPC2_CFG_WR_RATE_LIMIT 0xE86950 + +#define mmTPC2_CFG_MSS_CONFIG 0xE86954 + +#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86958 + +#define mmTPC2_CFG_TPC_INTR_MASK 0xE8695C + +#define mmTPC2_CFG_WQ_CREDITS 0xE86960 + +#define mmTPC2_CFG_ARUSER_LO 0xE86964 + +#define mmTPC2_CFG_ARUSER_HI 0xE86968 + +#define mmTPC2_CFG_AWUSER_LO 0xE8696C + +#define mmTPC2_CFG_AWUSER_HI 0xE86970 + +#define mmTPC2_CFG_OPCODE_EXEC 0xE86974 + +#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE86978 + +#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE8697C + +#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE86980 + +#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE86984 + +#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE86988 + +#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE8698C + +#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE86990 + +#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE86994 + +#define mmTPC2_CFG_TSB_CFG_MAX_SIZE 0xE86998 + +#define mmTPC2_CFG_TSB_CFG 0xE8699C + +#define mmTPC2_CFG_DBGMEM_ADD 0xE869A0 + +#define mmTPC2_CFG_DBGMEM_DATA_WR 0xE869A4 + +#define mmTPC2_CFG_DBGMEM_DATA_RD 0xE869A8 + +#define mmTPC2_CFG_DBGMEM_CTRL 0xE869AC + +#define mmTPC2_CFG_DBGMEM_RC 0xE869B0 + +#define mmTPC2_CFG_TSB_INFLIGHT_CNTR 0xE869B4 + +#define mmTPC2_CFG_WQ_INFLIGHT_CNTR 0xE869B8 + +#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR 0xE869BC + +#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR 0xE869C0 + +#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR 0xE869C4 + +#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE869D0 + +#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE869D4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE869D8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE869DC + +#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE869E0 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE869E4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE869E8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE869EC + +#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE869F0 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE869F4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE869F8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE869FC + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00 + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04 + +#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08 + +#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A18 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A1C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A20 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A24 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A28 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A2C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A30 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A34 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A38 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A3C + +#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A40 + +#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A44 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A48 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A4C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A50 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A54 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A58 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A5C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A60 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A64 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A68 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A6C + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A70 + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A74 + +#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86A78 + +#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86A7C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86A80 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86A84 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86A88 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86A8C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86A90 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86A94 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86A98 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86A9C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AA0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86AA4 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AA8 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AAC + +#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AB0 + +#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AB4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AB8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86ABC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86AC0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86AC4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86AC8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86ACC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86AD0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86AD4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86AD8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86ADC + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86AE0 + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86AE4 + +#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86AE8 + +#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86AEC + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86AF0 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86AF4 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86AF8 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86AFC + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B00 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B04 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B08 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B0C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B10 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B14 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B18 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B1C + +#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B20 + +#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B24 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B28 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B2C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B30 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B34 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86B38 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86B3C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86B40 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86B44 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86B48 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86B4C + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86B50 + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86B54 + +#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86B58 + +#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86B5C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86B60 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86B64 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86B68 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86B6C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86B70 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86B74 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86B78 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86B7C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86B80 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86B84 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86B88 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86B8C + +#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86B90 + +#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86B94 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86B98 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86B9C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86BA0 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86BA4 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86BA8 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86BAC + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86BB0 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86BB4 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86BB8 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86BBC + +#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE86BC0 + +#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE86BC4 + +#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE 0xE86BC8 + +#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE86BCC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE86BD0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE86BD4 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE86BD8 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE86BDC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE86BE0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE86BE4 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE86BE8 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE86BEC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE86BF0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE86BF4 + +#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE86BF8 + +#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE86BFC + +#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE 0xE86C00 + +#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE86C04 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE86C08 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE86C0C + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE86C10 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE86C14 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE86C18 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE86C1C + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE86C20 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE86C24 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE86C28 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE86C2C + +#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE86C30 + +#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE86C34 + +#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE 0xE86C38 + +#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE86C3C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE86C40 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE86C44 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE86C48 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE86C4C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE86C50 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE86C54 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE86C58 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE86C5C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE86C60 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE86C64 + +#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE86C68 + +#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE86C6C + +#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE 0xE86C70 + +#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE86C74 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE86C78 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE86C7C + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE86C80 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE86C84 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE86C88 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE86C8C + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE86C90 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE86C94 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE86C98 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE86C9C + +#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE86CA0 + +#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE86CA4 + +#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE 0xE86CA8 + +#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE86CAC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE86CB0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE86CB4 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE86CB8 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE86CBC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE86CC0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE86CC4 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE86CC8 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE86CCC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE86CD0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE86CD4 + +#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE86CD8 + +#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE86CDC + +#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE 0xE86CE0 + +#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE86CE4 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE86CE8 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE86CEC + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE86CF0 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE86CF4 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE86CF8 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE86CFC + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE86D00 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE86D04 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE86D08 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE86D0C + +#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE86D10 + +#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE86D14 + +#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE 0xE86D18 + +#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE86D1C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE86D20 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE86D24 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE86D28 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE86D2C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE86D30 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE86D34 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE86D38 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE86D3C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE86D40 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE86D44 + +#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE86D48 + +#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE86D4C + +#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE 0xE86D50 + +#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE86D54 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE86D58 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE86D5C + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE86D60 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE86D64 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE86D68 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE86D6C + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE86D70 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE86D74 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE86D78 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE86D7C + +#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D80 + +#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR 0xE86D84 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86D88 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86D8C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86D90 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86D94 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86D98 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86D9C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86DA0 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86DA4 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86DA8 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86DAC + +#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86DB0 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86DB4 + +#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86DB8 + +#define mmTPC2_CFG_QM_KERNEL_ID 0xE86DBC + +#define mmTPC2_CFG_QM_SRF_0 0xE86DC0 + +#define mmTPC2_CFG_QM_SRF_1 0xE86DC4 + +#define mmTPC2_CFG_QM_SRF_2 0xE86DC8 + +#define mmTPC2_CFG_QM_SRF_3 0xE86DCC + +#define mmTPC2_CFG_QM_SRF_4 0xE86DD0 + +#define mmTPC2_CFG_QM_SRF_5 0xE86DD4 + +#define mmTPC2_CFG_QM_SRF_6 0xE86DD8 + +#define mmTPC2_CFG_QM_SRF_7 0xE86DDC + +#define mmTPC2_CFG_QM_SRF_8 0xE86DE0 + +#define mmTPC2_CFG_QM_SRF_9 0xE86DE4 + +#define mmTPC2_CFG_QM_SRF_10 0xE86DE8 + +#define mmTPC2_CFG_QM_SRF_11 0xE86DEC + +#define mmTPC2_CFG_QM_SRF_12 0xE86DF0 + +#define mmTPC2_CFG_QM_SRF_13 0xE86DF4 + +#define mmTPC2_CFG_QM_SRF_14 0xE86DF8 + +#define mmTPC2_CFG_QM_SRF_15 0xE86DFC + +#define mmTPC2_CFG_QM_SRF_16 0xE86E00 + +#define mmTPC2_CFG_QM_SRF_17 0xE86E04 + +#define mmTPC2_CFG_QM_SRF_18 0xE86E08 + +#define mmTPC2_CFG_QM_SRF_19 0xE86E0C + +#define mmTPC2_CFG_QM_SRF_20 0xE86E10 + +#define mmTPC2_CFG_QM_SRF_21 0xE86E14 + +#define mmTPC2_CFG_QM_SRF_22 0xE86E18 + +#define mmTPC2_CFG_QM_SRF_23 0xE86E1C + +#define mmTPC2_CFG_QM_SRF_24 0xE86E20 + +#define mmTPC2_CFG_QM_SRF_25 0xE86E24 + +#define mmTPC2_CFG_QM_SRF_26 0xE86E28 + +#define mmTPC2_CFG_QM_SRF_27 0xE86E2C + +#define mmTPC2_CFG_QM_SRF_28 0xE86E30 + +#define mmTPC2_CFG_QM_SRF_29 0xE86E34 + +#define mmTPC2_CFG_QM_SRF_30 0xE86E38 + +#define mmTPC2_CFG_QM_SRF_31 0xE86E3C + +#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */ |