Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted

Pull networking updates from Jakub Kicinski:
 "Core:

   - Add dedicated kmem_cache for typical/small skb->head, avoid having
     to access struct page at kfree time, and improve memory use.

   - Introduce sysctl to set default RPS configuration for new netdevs.

   - Define Netlink protocol specification format which can be used to
     describe messages used by each family and auto-generate parsers.
     Add tools for generating kernel data structures and uAPI headers.

   - Expose all net/core sysctls inside netns.

   - Remove 4s sleep in netpoll if carrier is instantly detected on
     boot.

   - Add configurable limit of MDB entries per port, and port-vlan.

   - Continue populating drop reasons throughout the stack.

   - Retire a handful of legacy Qdiscs and classifiers.

  Protocols:

   - Support IPv4 big TCP (TSO frames larger than 64kB).

   - Add IP_LOCAL_PORT_RANGE socket option, to control local port range
     on socket by socket basis.

   - Track and report in procfs number of MPTCP sockets used.

   - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
     manager.

   - IPv6: don't check net.ipv6.route.max_size and rely on garbage
     collection to free memory (similarly to IPv4).

   - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).

   - ICMP: add per-rate limit counters.

   - Add support for user scanning requests in ieee802154.

   - Remove static WEP support.

   - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
     reporting.

   - WiFi 7 EHT channel puncturing support (client & AP).

  BPF:

   - Add a rbtree data structure following the "next-gen data structure"
     precedent set by recently added linked list, that is, by using
     kfunc + kptr instead of adding a new BPF map type.

   - Expose XDP hints via kfuncs with initial support for RX hash and
     timestamp metadata.

   - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
     better support decap on GRE tunnel devices not operating in collect
     metadata.

   - Improve x86 JIT's codegen for PROBE_MEM runtime error checks.

   - Remove the need for trace_printk_lock for bpf_trace_printk and
     bpf_trace_vprintk helpers.

   - Extend libbpf's bpf_tracing.h support for tracing arguments of
     kprobes/uprobes and syscall as a special case.

   - Significantly reduce the search time for module symbols by
     livepatch and BPF.

   - Enable cpumasks to be used as kptrs, which is useful for tracing
     programs tracking which tasks end up running on which CPUs in
     different time intervals.

   - Add support for BPF trampoline on s390x and riscv64.

   - Add capability to export the XDP features supported by the NIC.

   - Add __bpf_kfunc tag for marking kernel functions as kfuncs.

   - Add cgroup.memory=nobpf kernel parameter option to disable BPF
     memory accounting for container environments.

  Netfilter:

   - Remove the CLUSTERIP target. It has been marked as obsolete for
     years, and we still have WARN splats wrt races of the out-of-band
     /proc interface installed by this target.

   - Add 'destroy' commands to nf_tables. They are identical to the
     existing 'delete' commands, but do not return an error if the
     referenced object (set, chain, rule...) did not exist.

  Driver API:

   - Improve cpumask_local_spread() locality to help NICs set the right
     IRQ affinity on AMD platforms.

   - Separate C22 and C45 MDIO bus transactions more clearly.

   - Introduce new DCB table to control DSCP rewrite on egress.

   - Support configuration of Physical Layer Collision Avoidance (PLCA)
     Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
     shared medium Ethernet.

   - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
     preemption of low priority frames by high priority frames.

   - Add support for controlling MACSec offload using netlink SET.

   - Rework devlink instance refcounts to allow registration and
     de-registration under the instance lock. Split the code into
     multiple files, drop some of the unnecessarily granular locks and
     factor out common parts of netlink operation handling.

   - Add TX frame aggregation parameters (for USB drivers).

   - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
     messages with notifications for debug.

   - Allow offloading of UDP NEW connections via act_ct.

   - Add support for per action HW stats in TC.

   - Support hardware miss to TC action (continue processing in SW from
     a specific point in the action chain).

   - Warn if old Wireless Extension user space interface is used with
     modern cfg80211/mac80211 drivers. Do not support Wireless
     Extensions for Wi-Fi 7 devices at all. Everyone should switch to
     using nl80211 interface instead.

   - Improve the CAN bit timing configuration. Use extack to return
     error messages directly to user space, update the SJW handling,
     including the definition of a new default value that will benefit
     CAN-FD controllers, by increasing their oscillator tolerance.

  New hardware / drivers:

   - Ethernet:
      - nVidia BlueField-3 support (control traffic driver)
      - Ethernet support for imx93 SoCs
      - Motorcomm yt8531 gigabit Ethernet PHY
      - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
      - Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
      - Amlogic gxl MDIO mux

   - WiFi:
      - RealTek RTL8188EU (rtl8xxxu)
      - Qualcomm Wi-Fi 7 devices (ath12k)

   - CAN:
      - Renesas R-Car V4H

  Drivers:

   - Bluetooth:
      - Set Per Platform Antenna Gain (PPAG) for Intel controllers.

   - Ethernet NICs:
      - Intel (1G, igc):
         - support TSN / Qbv / packet scheduling features of i226 model
      - Intel (100G, ice):
         - use GNSS subsystem instead of TTY
         - multi-buffer XDP support
         - extend support for GPIO pins to E823 devices
      - nVidia/Mellanox:
         - update the shared buffer configuration on PFC commands
         - implement PTP adjphase function for HW offset control
         - TC support for Geneve and GRE with VF tunnel offload
         - more efficient crypto key management method
         - multi-port eswitch support
      - Netronome/Corigine:
         - add DCB IEEE support
         - support IPsec offloading for NFP3800
      - Freescale/NXP (enetc):
         - support XDP_REDIRECT for XDP non-linear buffers
         - improve reconfig, avoid link flap and waiting for idle
         - support MAC Merge layer
      - Other NICs:
         - sfc/ef100: add basic devlink support for ef100
         - ionic: rx_push mode operation (writing descriptors via MMIO)
         - bnxt: use the auxiliary bus abstraction for RDMA
         - r8169: disable ASPM and reset bus in case of tx timeout
         - cpsw: support QSGMII mode for J721e CPSW9G
         - cpts: support pulse-per-second output
         - ngbe: add an mdio bus driver
         - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
         - r8152: handle devices with FW with NCM support
         - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
         - virtio-net: support multi buffer XDP
         - virtio/vsock: replace virtio_vsock_pkt with sk_buff
         - tsnep: XDP support

   - Ethernet high-speed switches:
      - nVidia/Mellanox (mlxsw):
         - add support for latency TLV (in FW control messages)
      - Microchip (sparx5):
         - separate explicit and implicit traffic forwarding rules, make
           the implicit rules always active
         - add support for egress DSCP rewrite
         - IS0 VCAP support (Ingress Classification)
         - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
           etc.)
         - ES2 VCAP support (Egress Access Control)
         - support for Per-Stream Filtering and Policing (802.1Q,
           8.6.5.1)

   - Ethernet embedded switches:
      - Marvell (mv88e6xxx):
         - add MAB (port auth) offload support
         - enable PTP receive for mv88e6390
      - NXP (ocelot):
         - support MAC Merge layer
         - support for the the vsc7512 internal copper phys
      - Microchip:
         - lan9303: convert to PHYLINK
         - lan966x: support TC flower filter statistics
         - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
         - lan937x: support Credit Based Shaper configuration
         - ksz9477: support Energy Efficient Ethernet
      - other:
         - qca8k: convert to regmap read/write API, use bulk operations
         - rswitch: Improve TX timestamp accuracy

   - Intel WiFi (iwlwifi):
      - EHT (Wi-Fi 7) rate reporting
      - STEP equalizer support: transfer some STEP (connection to radio
        on platforms with integrated wifi) related parameters from the
        BIOS to the firmware.

   - Qualcomm 802.11ax WiFi (ath11k):
      - IPQ5018 support
      - Fine Timing Measurement (FTM) responder role support
      - channel 177 support

   - MediaTek WiFi (mt76):
      - per-PHY LED support
      - mt7996: EHT (Wi-Fi 7) support
      - Wireless Ethernet Dispatch (WED) reset support
      - switch to using page pool allocator

   - RealTek WiFi (rtw89):
      - support new version of Bluetooth co-existance

   - Mobile:
      - rmnet: support TX aggregation"

* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
  page_pool: add a comment explaining the fragment counter usage
  net: ethtool: fix __ethtool_dev_mm_supported() implementation
  ethtool: pse-pd: Fix double word in comments
  xsk: add linux/vmalloc.h to xsk.c
  sefltests: netdevsim: wait for devlink instance after netns removal
  selftest: fib_tests: Always cleanup before exit
  net/mlx5e: Align IPsec ASO result memory to be as required by hardware
  net/mlx5e: TC, Set CT miss to the specific ct action instance
  net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
  net/mlx5: Refactor tc miss handling to a single function
  net/mlx5: Kconfig: Make tc offload depend on tc skb extension
  net/sched: flower: Support hardware miss to tc action
  net/sched: flower: Move filter handle initialization earlier
  net/sched: cls_api: Support hardware miss to tc action
  net/sched: Rename user cookie and act cookie
  sfc: fix builds without CONFIG_RTC_LIB
  sfc: clean up some inconsistent indentings
  net/mlx4_en: Introduce flexible array to silence overflow warning
  net: lan966x: Fix possible deadlock inside PTP
  net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
  ...

1 files changed, 422 insertions, 0 deletions

diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
new file mode 100644
index 000000000..cc5842ec6
--- /dev/null
+++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
@@ -0,0 +1,422 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_DBI_REGS_H_
+#define ASIC_REG_PCIE_DBI_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_DBI
+ *   (Prototype: PCIE_DBI)
+ *****************************************
+ */
+
+#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0x4C02000
+
+#define mmPCIE_DBI_STATUS_COMMAND_REG 0x4C02004
+
+#define mmPCIE_DBI_CLASS_CODE_REVISION_ID 0x4C02008
+
+#define mmPCIE_DBI_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG 0x4C0200C
+
+#define mmPCIE_DBI_BAR0_REG 0x4C02010
+
+#define mmPCIE_DBI_BAR1_REG 0x4C02014
+
+#define mmPCIE_DBI_BAR2_REG 0x4C02018
+
+#define mmPCIE_DBI_BAR3_REG 0x4C0201C
+
+#define mmPCIE_DBI_BAR4_REG 0x4C02020
+
+#define mmPCIE_DBI_BAR5_REG 0x4C02024
+
+#define mmPCIE_DBI_CARDBUS_CIS_PTR_REG 0x4C02028
+
+#define mmPCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG 0x4C0202C
+
+#define mmPCIE_DBI_EXP_ROM_BASE_ADDR_REG 0x4C02030
+
+#define mmPCIE_DBI_PCI_CAP_PTR_REG 0x4C02034
+
+#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG \
+0x4C0203C
+
+#define mmPCIE_DBI_CAP_ID_NXT_PTR_REG 0x4C02040
+
+#define mmPCIE_DBI_CON_STATUS_REG 0x4C02044
+
+#define mmPCIE_DBI_PCI_MSI_CAP_ID_NEXT_CTRL_REG 0x4C02050
+
+#define mmPCIE_DBI_MSI_CAP_OFF_04H_REG 0x4C02054
+
+#define mmPCIE_DBI_MSI_CAP_OFF_08H_REG 0x4C02058
+
+#define mmPCIE_DBI_MSI_CAP_OFF_0CH_REG 0x4C0205C
+
+#define mmPCIE_DBI_MSI_CAP_OFF_10H_REG 0x4C02060
+
+#define mmPCIE_DBI_MSI_CAP_OFF_14H_REG 0x4C02064
+
+#define mmPCIE_DBI_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG 0x4C02070
+
+#define mmPCIE_DBI_DEVICE_CAPABILITIES_REG 0x4C02074
+
+#define mmPCIE_DBI_DEVICE_CONTROL_DEVICE_STATUS 0x4C02078
+
+#define mmPCIE_DBI_LINK_CAPABILITIES_REG 0x4C0207C
+
+#define mmPCIE_DBI_LINK_CONTROL_LINK_STATUS_REG 0x4C02080
+
+#define mmPCIE_DBI_DEVICE_CAPABILITIES2_REG 0x4C02094
+
+#define mmPCIE_DBI_DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x4C02098
+
+#define mmPCIE_DBI_LINK_CAPABILITIES2_REG 0x4C0209C
+
+#define mmPCIE_DBI_LINK_CONTROL2_LINK_STATUS2_REG 0x4C020A0
+
+#define mmPCIE_DBI_PCI_MSIX_CAP_ID_NEXT_CTRL_REG 0x4C020B0
+
+#define mmPCIE_DBI_MSIX_TABLE_OFFSET_REG 0x4C020B4
+
+#define mmPCIE_DBI_MSIX_PBA_OFFSET_REG 0x4C020B8
+
+#define mmPCIE_DBI_AER_EXT_CAP_HDR_OFF 0x4C02100
+
+#define mmPCIE_DBI_UNCORR_ERR_STATUS_OFF 0x4C02104
+
+#define mmPCIE_DBI_UNCORR_ERR_MASK_OFF 0x4C02108
+
+#define mmPCIE_DBI_UNCORR_ERR_SEV_OFF 0x4C0210C
+
+#define mmPCIE_DBI_CORR_ERR_STATUS_OFF 0x4C02110
+
+#define mmPCIE_DBI_CORR_ERR_MASK_OFF 0x4C02114
+
+#define mmPCIE_DBI_ADV_ERR_CAP_CTRL_OFF 0x4C02118
+
+#define mmPCIE_DBI_HDR_LOG_0_OFF 0x4C0211C
+
+#define mmPCIE_DBI_HDR_LOG_1_OFF 0x4C02120
+
+#define mmPCIE_DBI_HDR_LOG_2_OFF 0x4C02124
+
+#define mmPCIE_DBI_HDR_LOG_3_OFF 0x4C02128
+
+#define mmPCIE_DBI_TLP_PREFIX_LOG_1_OFF 0x4C02138
+
+#define mmPCIE_DBI_TLP_PREFIX_LOG_2_OFF 0x4C0213C
+
+#define mmPCIE_DBI_TLP_PREFIX_LOG_3_OFF 0x4C02140
+
+#define mmPCIE_DBI_TLP_PREFIX_LOG_4_OFF 0x4C02144
+
+#define mmPCIE_DBI_SPCIE_CAP_HEADER_REG 0x4C02148
+
+#define mmPCIE_DBI_LINK_CONTROL3_REG 0x4C0214C
+
+#define mmPCIE_DBI_LANE_ERR_STATUS_REG 0x4C02150
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_0CH_REG 0x4C02154
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_10H_REG 0x4C02158
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_14H_REG 0x4C0215C
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_18H_REG 0x4C02160
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_1CH_REG 0x4C02164
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_20H_REG 0x4C02168
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_24H_REG 0x4C0216C
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_28H_REG 0x4C02170
+
+#define mmPCIE_DBI_PL16G_EXT_CAP_HDR_REG 0x4C02178
+
+#define mmPCIE_DBI_PL16G_CAPABILITY_REG 0x4C0217C
+
+#define mmPCIE_DBI_PL16G_CONTROL_REG 0x4C02180
+
+#define mmPCIE_DBI_PL16G_STATUS_REG 0x4C02184
+
+#define mmPCIE_DBI_PL16G_LC_DPAR_STATUS_REG 0x4C02188
+
+#define mmPCIE_DBI_PL16G_FIRST_RETIMER_DPAR_STATUS_REG 0x4C0218C
+
+#define mmPCIE_DBI_PL16G_SECOND_RETIMER_DPAR_STATUS_REG 0x4C02190
+
+#define mmPCIE_DBI_PL16G_CAP_OFF_20H_REG 0x4C02198
+
+#define mmPCIE_DBI_PL16G_CAP_OFF_24H_REG 0x4C0219C
+
+#define mmPCIE_DBI_PL16G_CAP_OFF_28H_REG 0x4C021A0
+
+#define mmPCIE_DBI_PL16G_CAP_OFF_2CH_REG 0x4C021A4
+
+#define mmPCIE_DBI_MARGIN_EXT_CAP_HDR_REG 0x4C021A8
+
+#define mmPCIE_DBI_MARGIN_PORT_CAPABILITIES_STATUS_REG 0x4C021AC
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS0_REG 0x4C021B0
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS1_REG 0x4C021B4
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS2_REG 0x4C021B8
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS3_REG 0x4C021BC
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS4_REG 0x4C021C0
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS5_REG 0x4C021C4
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS6_REG 0x4C021C8
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS7_REG 0x4C021CC
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS8_REG 0x4C021D0
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS9_REG 0x4C021D4
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS10_REG 0x4C021D8
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS11_REG 0x4C021DC
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS12_REG 0x4C021E0
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS13_REG 0x4C021E4
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS14_REG 0x4C021E8
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS15_REG 0x4C021EC
+
+#define mmPCIE_DBI_LTR_CAP_HDR_REG 0x4C021F0
+
+#define mmPCIE_DBI_LTR_LATENCY_REG 0x4C021F4
+
+#define mmPCIE_DBI_RAS_DES_CAP_HEADER_REG 0x4C021F8
+
+#define mmPCIE_DBI_VENDOR_SPECIFIC_HEADER_REG 0x4C021FC
+
+#define mmPCIE_DBI_EVENT_COUNTER_CONTROL_REG 0x4C02200
+
+#define mmPCIE_DBI_EVENT_COUNTER_DATA_REG 0x4C02204
+
+#define mmPCIE_DBI_TIME_BASED_ANALYSIS_CONTROL_REG 0x4C02208
+
+#define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_REG 0x4C0220C
+
+#define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_63_32_REG 0x4C02210
+
+#define mmPCIE_DBI_EINJ_ENABLE_REG 0x4C02228
+
+#define mmPCIE_DBI_EINJ0_CRC_REG 0x4C0222C
+
+#define mmPCIE_DBI_EINJ1_SEQNUM_REG 0x4C02230
+
+#define mmPCIE_DBI_EINJ2_DLLP_REG 0x4C02234
+
+#define mmPCIE_DBI_EINJ3_SYMBOL_REG 0x4C02238
+
+#define mmPCIE_DBI_EINJ4_FC_REG 0x4C0223C
+
+#define mmPCIE_DBI_EINJ5_SP_TLP_REG 0x4C02240
+
+#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H0_REG 0x4C02244
+
+#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H1_REG 0x4C02248
+
+#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H2_REG 0x4C0224C
+
+#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H3_REG 0x4C02250
+
+#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H0_REG 0x4C02254
+
+#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H1_REG 0x4C02258
+
+#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H2_REG 0x4C0225C
+
+#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H3_REG 0x4C02260
+
+#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H0_REG 0x4C02264
+
+#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H1_REG 0x4C02268
+
+#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H2_REG 0x4C0226C
+
+#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H3_REG 0x4C02270
+
+#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H0_REG 0x4C02274
+
+#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H1_REG 0x4C02278
+
+#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H2_REG 0x4C0227C
+
+#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H3_REG 0x4C02280
+
+#define mmPCIE_DBI_EINJ6_TLP_REG 0x4C02284
+
+#define mmPCIE_DBI_SD_CONTROL1_REG 0x4C02298
+
+#define mmPCIE_DBI_SD_CONTROL2_REG 0x4C0229C
+
+#define mmPCIE_DBI_SD_STATUS_L1LANE_REG 0x4C022A8
+
+#define mmPCIE_DBI_SD_STATUS_L1LTSSM_REG 0x4C022AC
+
+#define mmPCIE_DBI_SD_STATUS_PM_REG 0x4C022B0
+
+#define mmPCIE_DBI_SD_STATUS_L2_REG 0x4C022B4
+
+#define mmPCIE_DBI_SD_STATUS_L3FC_REG 0x4C022B8
+
+#define mmPCIE_DBI_SD_STATUS_L3_REG 0x4C022BC
+
+#define mmPCIE_DBI_SD_EQ_CONTROL1_REG 0x4C022C8
+
+#define mmPCIE_DBI_SD_EQ_CONTROL2_REG 0x4C022CC
+
+#define mmPCIE_DBI_SD_EQ_CONTROL3_REG 0x4C022D0
+
+#define mmPCIE_DBI_SD_EQ_STATUS1_REG 0x4C022D8
+
+#define mmPCIE_DBI_SD_EQ_STATUS2_REG 0x4C022DC
+
+#define mmPCIE_DBI_SD_EQ_STATUS3_REG 0x4C022E0
+
+#define mmPCIE_DBI_DATA_LINK_FEATURE_EXT_HDR_OFF 0x4C022F8
+
+#define mmPCIE_DBI_DATA_LINK_FEATURE_CAP_OFF 0x4C022FC
+
+#define mmPCIE_DBI_DATA_LINK_FEATURE_STATUS_OFF 0x4C02300
+
+#define mmPCIE_DBI_ACK_LATENCY_TIMER_OFF 0x4C02700
+
+#define mmPCIE_DBI_VENDOR_SPEC_DLLP_OFF 0x4C02704
+
+#define mmPCIE_DBI_PORT_FORCE_OFF 0x4C02708
+
+#define mmPCIE_DBI_ACK_F_ASPM_CTRL_OFF 0x4C0270C
+
+#define mmPCIE_DBI_PORT_LINK_CTRL_OFF 0x4C02710
+
+#define mmPCIE_DBI_LANE_SKEW_OFF 0x4C02714
+
+#define mmPCIE_DBI_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x4C02718
+
+#define mmPCIE_DBI_SYMBOL_TIMER_FILTER_1_OFF 0x4C0271C
+
+#define mmPCIE_DBI_FILTER_MASK_2_OFF 0x4C02720
+
+#define mmPCIE_DBI_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF 0x4C02724
+
+#define mmPCIE_DBI_PL_DEBUG0_OFF 0x4C02728
+
+#define mmPCIE_DBI_PL_DEBUG1_OFF 0x4C0272C
+
+#define mmPCIE_DBI_TX_P_FC_CREDIT_STATUS_OFF 0x4C02730
+
+#define mmPCIE_DBI_TX_NP_FC_CREDIT_STATUS_OFF 0x4C02734
+
+#define mmPCIE_DBI_TX_CPL_FC_CREDIT_STATUS_OFF 0x4C02738
+
+#define mmPCIE_DBI_QUEUE_STATUS_OFF 0x4C0273C
+
+#define mmPCIE_DBI_VC_TX_ARBI_1_OFF 0x4C02740
+
+#define mmPCIE_DBI_VC_TX_ARBI_2_OFF 0x4C02744
+
+#define mmPCIE_DBI_VC0_P_RX_Q_CTRL_OFF 0x4C02748
+
+#define mmPCIE_DBI_VC0_NP_RX_Q_CTRL_OFF 0x4C0274C
+
+#define mmPCIE_DBI_VC0_CPL_RX_Q_CTRL_OFF 0x4C02750
+
+#define mmPCIE_DBI_GEN2_CTRL_OFF 0x4C0280C
+
+#define mmPCIE_DBI_PHY_STATUS_OFF 0x4C02810
+
+#define mmPCIE_DBI_PHY_CONTROL_OFF 0x4C02814
+
+#define mmPCIE_DBI_TRGT_MAP_CTRL_OFF 0x4C0281C
+
+#define mmPCIE_DBI_CLOCK_GATING_CTRL_OFF 0x4C0288C
+
+#define mmPCIE_DBI_GEN3_RELATED_OFF 0x4C02890
+
+#define mmPCIE_DBI_GEN3_EQ_CONTROL_OFF 0x4C028A8
+
+#define mmPCIE_DBI_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x4C028AC
+
+#define mmPCIE_DBI_ORDER_RULE_CTRL_OFF 0x4C028B4
+
+#define mmPCIE_DBI_PIPE_LOOPBACK_CONTROL_OFF 0x4C028B8
+
+#define mmPCIE_DBI_MISC_CONTROL_1_OFF 0x4C028BC
+
+#define mmPCIE_DBI_MULTI_LANE_CONTROL_OFF 0x4C028C0
+
+#define mmPCIE_DBI_PHY_INTEROP_CTRL_OFF 0x4C028C4
+
+#define mmPCIE_DBI_TRGT_CPL_LUT_DELETE_ENTRY_OFF 0x4C028C8
+
+#define mmPCIE_DBI_LINK_FLUSH_CONTROL_OFF 0x4C028CC
+
+#define mmPCIE_DBI_AMBA_ERROR_RESPONSE_DEFAULT_OFF 0x4C028D0
+
+#define mmPCIE_DBI_AMBA_LINK_TIMEOUT_OFF 0x4C028D4
+
+#define mmPCIE_DBI_AMBA_ORDERING_CTRL_OFF 0x4C028D8
+
+#define mmPCIE_DBI_COHERENCY_CONTROL_1_OFF 0x4C028E0
+
+#define mmPCIE_DBI_COHERENCY_CONTROL_2_OFF 0x4C028E4
+
+#define mmPCIE_DBI_COHERENCY_CONTROL_3_OFF 0x4C028E8
+
+#define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_LOW_OFF 0x4C028F0
+
+#define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_HIGH_OFF 0x4C028F4
+
+#define mmPCIE_DBI_PCIE_VERSION_NUMBER_OFF 0x4C028F8
+
+#define mmPCIE_DBI_PCIE_VERSION_TYPE_OFF 0x4C028FC
+
+#define mmPCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF 0x4C02940
+
+#define mmPCIE_DBI_MSIX_ADDRESS_MATCH_HIGH_OFF 0x4C02944
+
+#define mmPCIE_DBI_MSIX_DOORBELL_OFF 0x4C02948
+
+#define mmPCIE_DBI_MSIX_RAM_CTRL_OFF 0x4C0294C
+
+#define mmPCIE_DBI_PL_LTR_LATENCY_OFF 0x4C02B30
+
+#define mmPCIE_DBI_AUX_CLK_FREQ_OFF 0x4C02B40
+
+#define mmPCIE_DBI_POWERDOWN_CTRL_STATUS_OFF 0x4C02B48
+
+#define mmPCIE_DBI_PHY_VIEWPORT_CTLSTS_OFF 0x4C02B70
+
+#define mmPCIE_DBI_PHY_VIEWPORT_DATA_OFF 0x4C02B74
+
+#define mmPCIE_DBI_GEN4_LANE_MARGINING_1_OFF 0x4C02B80
+
+#define mmPCIE_DBI_GEN4_LANE_MARGINING_2_OFF 0x4C02B84
+
+#define mmPCIE_DBI_PIPE_RELATED_OFF 0x4C02B90
+
+#define mmPCIE_DBI_RX_SERIALIZATION_Q_CTRL_OFF 0x4C02C00
+
+#endif /* ASIC_REG_PCIE_DBI_REGS_H_ */