Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted

Pull networking updates from Jakub Kicinski:
 "Core:

   - Add dedicated kmem_cache for typical/small skb->head, avoid having
     to access struct page at kfree time, and improve memory use.

   - Introduce sysctl to set default RPS configuration for new netdevs.

   - Define Netlink protocol specification format which can be used to
     describe messages used by each family and auto-generate parsers.
     Add tools for generating kernel data structures and uAPI headers.

   - Expose all net/core sysctls inside netns.

   - Remove 4s sleep in netpoll if carrier is instantly detected on
     boot.

   - Add configurable limit of MDB entries per port, and port-vlan.

   - Continue populating drop reasons throughout the stack.

   - Retire a handful of legacy Qdiscs and classifiers.

  Protocols:

   - Support IPv4 big TCP (TSO frames larger than 64kB).

   - Add IP_LOCAL_PORT_RANGE socket option, to control local port range
     on socket by socket basis.

   - Track and report in procfs number of MPTCP sockets used.

   - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
     manager.

   - IPv6: don't check net.ipv6.route.max_size and rely on garbage
     collection to free memory (similarly to IPv4).

   - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).

   - ICMP: add per-rate limit counters.

   - Add support for user scanning requests in ieee802154.

   - Remove static WEP support.

   - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
     reporting.

   - WiFi 7 EHT channel puncturing support (client & AP).

  BPF:

   - Add a rbtree data structure following the "next-gen data structure"
     precedent set by recently added linked list, that is, by using
     kfunc + kptr instead of adding a new BPF map type.

   - Expose XDP hints via kfuncs with initial support for RX hash and
     timestamp metadata.

   - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
     better support decap on GRE tunnel devices not operating in collect
     metadata.

   - Improve x86 JIT's codegen for PROBE_MEM runtime error checks.

   - Remove the need for trace_printk_lock for bpf_trace_printk and
     bpf_trace_vprintk helpers.

   - Extend libbpf's bpf_tracing.h support for tracing arguments of
     kprobes/uprobes and syscall as a special case.

   - Significantly reduce the search time for module symbols by
     livepatch and BPF.

   - Enable cpumasks to be used as kptrs, which is useful for tracing
     programs tracking which tasks end up running on which CPUs in
     different time intervals.

   - Add support for BPF trampoline on s390x and riscv64.

   - Add capability to export the XDP features supported by the NIC.

   - Add __bpf_kfunc tag for marking kernel functions as kfuncs.

   - Add cgroup.memory=nobpf kernel parameter option to disable BPF
     memory accounting for container environments.

  Netfilter:

   - Remove the CLUSTERIP target. It has been marked as obsolete for
     years, and we still have WARN splats wrt races of the out-of-band
     /proc interface installed by this target.

   - Add 'destroy' commands to nf_tables. They are identical to the
     existing 'delete' commands, but do not return an error if the
     referenced object (set, chain, rule...) did not exist.

  Driver API:

   - Improve cpumask_local_spread() locality to help NICs set the right
     IRQ affinity on AMD platforms.

   - Separate C22 and C45 MDIO bus transactions more clearly.

   - Introduce new DCB table to control DSCP rewrite on egress.

   - Support configuration of Physical Layer Collision Avoidance (PLCA)
     Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
     shared medium Ethernet.

   - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
     preemption of low priority frames by high priority frames.

   - Add support for controlling MACSec offload using netlink SET.

   - Rework devlink instance refcounts to allow registration and
     de-registration under the instance lock. Split the code into
     multiple files, drop some of the unnecessarily granular locks and
     factor out common parts of netlink operation handling.

   - Add TX frame aggregation parameters (for USB drivers).

   - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
     messages with notifications for debug.

   - Allow offloading of UDP NEW connections via act_ct.

   - Add support for per action HW stats in TC.

   - Support hardware miss to TC action (continue processing in SW from
     a specific point in the action chain).

   - Warn if old Wireless Extension user space interface is used with
     modern cfg80211/mac80211 drivers. Do not support Wireless
     Extensions for Wi-Fi 7 devices at all. Everyone should switch to
     using nl80211 interface instead.

   - Improve the CAN bit timing configuration. Use extack to return
     error messages directly to user space, update the SJW handling,
     including the definition of a new default value that will benefit
     CAN-FD controllers, by increasing their oscillator tolerance.

  New hardware / drivers:

   - Ethernet:
      - nVidia BlueField-3 support (control traffic driver)
      - Ethernet support for imx93 SoCs
      - Motorcomm yt8531 gigabit Ethernet PHY
      - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
      - Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
      - Amlogic gxl MDIO mux

   - WiFi:
      - RealTek RTL8188EU (rtl8xxxu)
      - Qualcomm Wi-Fi 7 devices (ath12k)

   - CAN:
      - Renesas R-Car V4H

  Drivers:

   - Bluetooth:
      - Set Per Platform Antenna Gain (PPAG) for Intel controllers.

   - Ethernet NICs:
      - Intel (1G, igc):
         - support TSN / Qbv / packet scheduling features of i226 model
      - Intel (100G, ice):
         - use GNSS subsystem instead of TTY
         - multi-buffer XDP support
         - extend support for GPIO pins to E823 devices
      - nVidia/Mellanox:
         - update the shared buffer configuration on PFC commands
         - implement PTP adjphase function for HW offset control
         - TC support for Geneve and GRE with VF tunnel offload
         - more efficient crypto key management method
         - multi-port eswitch support
      - Netronome/Corigine:
         - add DCB IEEE support
         - support IPsec offloading for NFP3800
      - Freescale/NXP (enetc):
         - support XDP_REDIRECT for XDP non-linear buffers
         - improve reconfig, avoid link flap and waiting for idle
         - support MAC Merge layer
      - Other NICs:
         - sfc/ef100: add basic devlink support for ef100
         - ionic: rx_push mode operation (writing descriptors via MMIO)
         - bnxt: use the auxiliary bus abstraction for RDMA
         - r8169: disable ASPM and reset bus in case of tx timeout
         - cpsw: support QSGMII mode for J721e CPSW9G
         - cpts: support pulse-per-second output
         - ngbe: add an mdio bus driver
         - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
         - r8152: handle devices with FW with NCM support
         - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
         - virtio-net: support multi buffer XDP
         - virtio/vsock: replace virtio_vsock_pkt with sk_buff
         - tsnep: XDP support

   - Ethernet high-speed switches:
      - nVidia/Mellanox (mlxsw):
         - add support for latency TLV (in FW control messages)
      - Microchip (sparx5):
         - separate explicit and implicit traffic forwarding rules, make
           the implicit rules always active
         - add support for egress DSCP rewrite
         - IS0 VCAP support (Ingress Classification)
         - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
           etc.)
         - ES2 VCAP support (Egress Access Control)
         - support for Per-Stream Filtering and Policing (802.1Q,
           8.6.5.1)

   - Ethernet embedded switches:
      - Marvell (mv88e6xxx):
         - add MAB (port auth) offload support
         - enable PTP receive for mv88e6390
      - NXP (ocelot):
         - support MAC Merge layer
         - support for the the vsc7512 internal copper phys
      - Microchip:
         - lan9303: convert to PHYLINK
         - lan966x: support TC flower filter statistics
         - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
         - lan937x: support Credit Based Shaper configuration
         - ksz9477: support Energy Efficient Ethernet
      - other:
         - qca8k: convert to regmap read/write API, use bulk operations
         - rswitch: Improve TX timestamp accuracy

   - Intel WiFi (iwlwifi):
      - EHT (Wi-Fi 7) rate reporting
      - STEP equalizer support: transfer some STEP (connection to radio
        on platforms with integrated wifi) related parameters from the
        BIOS to the firmware.

   - Qualcomm 802.11ax WiFi (ath11k):
      - IPQ5018 support
      - Fine Timing Measurement (FTM) responder role support
      - channel 177 support

   - MediaTek WiFi (mt76):
      - per-PHY LED support
      - mt7996: EHT (Wi-Fi 7) support
      - Wireless Ethernet Dispatch (WED) reset support
      - switch to using page pool allocator

   - RealTek WiFi (rtw89):
      - support new version of Bluetooth co-existance

   - Mobile:
      - rmnet: support TX aggregation"

* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
  page_pool: add a comment explaining the fragment counter usage
  net: ethtool: fix __ethtool_dev_mm_supported() implementation
  ethtool: pse-pd: Fix double word in comments
  xsk: add linux/vmalloc.h to xsk.c
  sefltests: netdevsim: wait for devlink instance after netns removal
  selftest: fib_tests: Always cleanup before exit
  net/mlx5e: Align IPsec ASO result memory to be as required by hardware
  net/mlx5e: TC, Set CT miss to the specific ct action instance
  net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
  net/mlx5: Refactor tc miss handling to a single function
  net/mlx5: Kconfig: Make tc offload depend on tc skb extension
  net/sched: flower: Support hardware miss to tc action
  net/sched: flower: Move filter handle initialization earlier
  net/sched: cls_api: Support hardware miss to tc action
  net/sched: Rename user cookie and act cookie
  sfc: fix builds without CONFIG_RTC_LIB
  sfc: clean up some inconsistent indentings
  net/mlx4_en: Introduce flexible array to silence overflow warning
  net: lan966x: Fix possible deadlock inside PTP
  net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
  ...

1 files changed, 879 insertions, 0 deletions

diff --git a/drivers/net/ethernet/dnet.c b/drivers/net/ethernet/dnet.c
new file mode 100644
index 000000000..151ca9573
--- /dev/null
+++ b/drivers/net/ethernet/dnet.c
@@ -0,0 +1,879 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Dave DNET Ethernet Controller driver
+ *
+ * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
+ * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ */
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+
+#include "dnet.h"
+
+#undef DEBUG
+
+/* function for reading internal MAC register */
+static u16 dnet_readw_mac(struct dnet *bp, u16 reg)
+{
+	u16 data_read;
+
+	/* issue a read */
+	dnet_writel(bp, reg, MACREG_ADDR);
+
+	/* since a read/write op to the MAC is very slow,
+	 * we must wait before reading the data */
+	ndelay(500);
+
+	/* read data read from the MAC register */
+	data_read = dnet_readl(bp, MACREG_DATA);
+
+	/* all done */
+	return data_read;
+}
+
+/* function for writing internal MAC register */
+static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val)
+{
+	/* load data to write */
+	dnet_writel(bp, val, MACREG_DATA);
+
+	/* issue a write */
+	dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
+
+	/* since a read/write op to the MAC is very slow,
+	 * we must wait before exiting */
+	ndelay(500);
+}
+
+static void __dnet_set_hwaddr(struct dnet *bp)
+{
+	u16 tmp;
+
+	tmp = be16_to_cpup((const __be16 *)bp->dev->dev_addr);
+	dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
+	tmp = be16_to_cpup((const __be16 *)(bp->dev->dev_addr + 2));
+	dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
+	tmp = be16_to_cpup((const __be16 *)(bp->dev->dev_addr + 4));
+	dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
+}
+
+static void dnet_get_hwaddr(struct dnet *bp)
+{
+	u16 tmp;
+	u8 addr[6];
+
+	/*
+	 * from MAC docs:
+	 * "Note that the MAC address is stored in the registers in Hexadecimal
+	 * form. For example, to set the MAC Address to: AC-DE-48-00-00-80
+	 * would require writing 0xAC (octet 0) to address 0x0B (high byte of
+	 * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
+	 * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
+	 * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
+	 * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
+	 * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
+	 * Mac_addr[15:0]).
+	 */
+	tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG);
+	*((__be16 *)addr) = cpu_to_be16(tmp);
+	tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG);
+	*((__be16 *)(addr + 2)) = cpu_to_be16(tmp);
+	tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG);
+	*((__be16 *)(addr + 4)) = cpu_to_be16(tmp);
+
+	if (is_valid_ether_addr(addr))
+		eth_hw_addr_set(bp->dev, addr);
+}
+
+static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct dnet *bp = bus->priv;
+	u16 value;
+
+	while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
+				& DNET_INTERNAL_GMII_MNG_CMD_FIN))
+		cpu_relax();
+
+	/* only 5 bits allowed for phy-addr and reg_offset */
+	mii_id &= 0x1f;
+	regnum &= 0x1f;
+
+	/* prepare reg_value for a read */
+	value = (mii_id << 8);
+	value |= regnum;
+
+	/* write control word */
+	dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
+
+	/* wait for end of transfer */
+	while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
+				& DNET_INTERNAL_GMII_MNG_CMD_FIN))
+		cpu_relax();
+
+	value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG);
+
+	pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value);
+
+	return value;
+}
+
+static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+			   u16 value)
+{
+	struct dnet *bp = bus->priv;
+	u16 tmp;
+
+	pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value);
+
+	while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
+				& DNET_INTERNAL_GMII_MNG_CMD_FIN))
+		cpu_relax();
+
+	/* prepare for a write operation */
+	tmp = (1 << 13);
+
+	/* only 5 bits allowed for phy-addr and reg_offset */
+	mii_id &= 0x1f;
+	regnum &= 0x1f;
+
+	/* only 16 bits on data */
+	value &= 0xffff;
+
+	/* prepare reg_value for a write */
+	tmp |= (mii_id << 8);
+	tmp |= regnum;
+
+	/* write data to write first */
+	dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
+
+	/* write control word */
+	dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
+
+	while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
+				& DNET_INTERNAL_GMII_MNG_CMD_FIN))
+		cpu_relax();
+
+	return 0;
+}
+
+static void dnet_handle_link_change(struct net_device *dev)
+{
+	struct dnet *bp = netdev_priv(dev);
+	struct phy_device *phydev = dev->phydev;
+	unsigned long flags;
+	u32 mode_reg, ctl_reg;
+
+	int status_change = 0;
+
+	spin_lock_irqsave(&bp->lock, flags);
+
+	mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
+	ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
+
+	if (phydev->link) {
+		if (bp->duplex != phydev->duplex) {
+			if (phydev->duplex)
+				ctl_reg &=
+				    ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
+			else
+				ctl_reg |=
+				    DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
+
+			bp->duplex = phydev->duplex;
+			status_change = 1;
+		}
+
+		if (bp->speed != phydev->speed) {
+			status_change = 1;
+			switch (phydev->speed) {
+			case 1000:
+				mode_reg |= DNET_INTERNAL_MODE_GBITEN;
+				break;
+			case 100:
+			case 10:
+				mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
+				break;
+			default:
+				printk(KERN_WARNING
+				       "%s: Ack!  Speed (%d) is not "
+				       "10/100/1000!\n", dev->name,
+				       phydev->speed);
+				break;
+			}
+			bp->speed = phydev->speed;
+		}
+	}
+
+	if (phydev->link != bp->link) {
+		if (phydev->link) {
+			mode_reg |=
+			    (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
+		} else {
+			mode_reg &=
+			    ~(DNET_INTERNAL_MODE_RXEN |
+			      DNET_INTERNAL_MODE_TXEN);
+			bp->speed = 0;
+			bp->duplex = -1;
+		}
+		bp->link = phydev->link;
+
+		status_change = 1;
+	}
+
+	if (status_change) {
+		dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
+		dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);
+	}
+
+	spin_unlock_irqrestore(&bp->lock, flags);
+
+	if (status_change) {
+		if (phydev->link)
+			printk(KERN_INFO "%s: link up (%d/%s)\n",
+			       dev->name, phydev->speed,
+			       DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
+		else
+			printk(KERN_INFO "%s: link down\n", dev->name);
+	}
+}
+
+static int dnet_mii_probe(struct net_device *dev)
+{
+	struct dnet *bp = netdev_priv(dev);
+	struct phy_device *phydev = NULL;
+
+	/* find the first phy */
+	phydev = phy_find_first(bp->mii_bus);
+
+	if (!phydev) {
+		printk(KERN_ERR "%s: no PHY found\n", dev->name);
+		return -ENODEV;
+	}
+
+	/* TODO : add pin_irq */
+
+	/* attach the mac to the phy */
+	if (bp->capabilities & DNET_HAS_RMII) {
+		phydev = phy_connect(dev, phydev_name(phydev),
+				     &dnet_handle_link_change,
+				     PHY_INTERFACE_MODE_RMII);
+	} else {
+		phydev = phy_connect(dev, phydev_name(phydev),
+				     &dnet_handle_link_change,
+				     PHY_INTERFACE_MODE_MII);
+	}
+
+	if (IS_ERR(phydev)) {
+		printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+		return PTR_ERR(phydev);
+	}
+
+	/* mask with MAC supported features */
+	if (bp->capabilities & DNET_HAS_GIGABIT)
+		phy_set_max_speed(phydev, SPEED_1000);
+	else
+		phy_set_max_speed(phydev, SPEED_100);
+
+	phy_support_asym_pause(phydev);
+
+	bp->link = 0;
+	bp->speed = 0;
+	bp->duplex = -1;
+
+	return 0;
+}
+
+static int dnet_mii_init(struct dnet *bp)
+{
+	int err;
+
+	bp->mii_bus = mdiobus_alloc();
+	if (bp->mii_bus == NULL)
+		return -ENOMEM;
+
+	bp->mii_bus->name = "dnet_mii_bus";
+	bp->mii_bus->read = &dnet_mdio_read;
+	bp->mii_bus->write = &dnet_mdio_write;
+
+	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+		bp->pdev->name, bp->pdev->id);
+
+	bp->mii_bus->priv = bp;
+
+	if (mdiobus_register(bp->mii_bus)) {
+		err = -ENXIO;
+		goto err_out;
+	}
+
+	if (dnet_mii_probe(bp->dev) != 0) {
+		err = -ENXIO;
+		goto err_out_unregister_bus;
+	}
+
+	return 0;
+
+err_out_unregister_bus:
+	mdiobus_unregister(bp->mii_bus);
+err_out:
+	mdiobus_free(bp->mii_bus);
+	return err;
+}
+
+/* For Neptune board: LINK1000 as Link LED and TX as activity LED */
+static int dnet_phy_marvell_fixup(struct phy_device *phydev)
+{
+	return phy_write(phydev, 0x18, 0x4148);
+}
+
+static void dnet_update_stats(struct dnet *bp)
+{
+	u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT;
+	u32 *p = &bp->hw_stats.rx_pkt_ignr;
+	u32 *end = &bp->hw_stats.rx_byte + 1;
+
+	WARN_ON((unsigned long)(end - p - 1) !=
+		(DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4);
+
+	for (; p < end; p++, reg++)
+		*p += readl(reg);
+
+	reg = bp->regs + DNET_TX_UNICAST_CNT;
+	p = &bp->hw_stats.tx_unicast;
+	end = &bp->hw_stats.tx_byte + 1;
+
+	WARN_ON((unsigned long)(end - p - 1) !=
+		(DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4);
+
+	for (; p < end; p++, reg++)
+		*p += readl(reg);
+}
+
+static int dnet_poll(struct napi_struct *napi, int budget)
+{
+	struct dnet *bp = container_of(napi, struct dnet, napi);
+	struct net_device *dev = bp->dev;
+	int npackets = 0;
+	unsigned int pkt_len;
+	struct sk_buff *skb;
+	unsigned int *data_ptr;
+	u32 int_enable;
+	u32 cmd_word;
+	int i;
+
+	while (npackets < budget) {
+		/*
+		 * break out of while loop if there are no more
+		 * packets waiting
+		 */
+		if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16))
+			break;
+
+		cmd_word = dnet_readl(bp, RX_LEN_FIFO);
+		pkt_len = cmd_word & 0xFFFF;
+
+		if (cmd_word & 0xDF180000)
+			printk(KERN_ERR "%s packet receive error %x\n",
+			       __func__, cmd_word);
+
+		skb = netdev_alloc_skb(dev, pkt_len + 5);
+		if (skb != NULL) {
+			/* Align IP on 16 byte boundaries */
+			skb_reserve(skb, 2);
+			/*
+			 * 'skb_put()' points to the start of sk_buff
+			 * data area.
+			 */
+			data_ptr = skb_put(skb, pkt_len);
+			for (i = 0; i < (pkt_len + 3) >> 2; i++)
+				*data_ptr++ = dnet_readl(bp, RX_DATA_FIFO);
+			skb->protocol = eth_type_trans(skb, dev);
+			netif_receive_skb(skb);
+			npackets++;
+		} else
+			printk(KERN_NOTICE
+			       "%s: No memory to allocate a sk_buff of "
+			       "size %u.\n", dev->name, pkt_len);
+	}
+
+	if (npackets < budget) {
+		/* We processed all packets available.  Tell NAPI it can
+		 * stop polling then re-enable rx interrupts.
+		 */
+		napi_complete_done(napi, npackets);
+		int_enable = dnet_readl(bp, INTR_ENB);
+		int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
+		dnet_writel(bp, int_enable, INTR_ENB);
+	}
+
+	return npackets;
+}
+
+static irqreturn_t dnet_interrupt(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct dnet *bp = netdev_priv(dev);
+	u32 int_src, int_enable, int_current;
+	unsigned long flags;
+	unsigned int handled = 0;
+
+	spin_lock_irqsave(&bp->lock, flags);
+
+	/* read and clear the DNET irq (clear on read) */
+	int_src = dnet_readl(bp, INTR_SRC);
+	int_enable = dnet_readl(bp, INTR_ENB);
+	int_current = int_src & int_enable;
+
+	/* restart the queue if we had stopped it for TX fifo almost full */
+	if (int_current & DNET_INTR_SRC_TX_FIFOAE) {
+		int_enable = dnet_readl(bp, INTR_ENB);
+		int_enable &= ~DNET_INTR_ENB_TX_FIFOAE;
+		dnet_writel(bp, int_enable, INTR_ENB);
+		netif_wake_queue(dev);
+		handled = 1;
+	}
+
+	/* RX FIFO error checking */
+	if (int_current &
+	    (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) {
+		printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__,
+		       dnet_readl(bp, RX_STATUS), int_current);
+		/* we can only flush the RX FIFOs */
+		dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL);
+		ndelay(500);
+		dnet_writel(bp, 0, SYS_CTL);
+		handled = 1;
+	}
+
+	/* TX FIFO error checking */
+	if (int_current &
+	    (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) {
+		printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__,
+		       dnet_readl(bp, TX_STATUS), int_current);
+		/* we can only flush the TX FIFOs */
+		dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
+		ndelay(500);
+		dnet_writel(bp, 0, SYS_CTL);
+		handled = 1;
+	}
+
+	if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) {
+		if (napi_schedule_prep(&bp->napi)) {
+			/*
+			 * There's no point taking any more interrupts
+			 * until we have processed the buffers
+			 */
+			/* Disable Rx interrupts and schedule NAPI poll */
+			int_enable = dnet_readl(bp, INTR_ENB);
+			int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF;
+			dnet_writel(bp, int_enable, INTR_ENB);
+			__napi_schedule(&bp->napi);
+		}
+		handled = 1;
+	}
+
+	if (!handled)
+		pr_debug("%s: irq %x remains\n", __func__, int_current);
+
+	spin_unlock_irqrestore(&bp->lock, flags);
+
+	return IRQ_RETVAL(handled);
+}
+
+#ifdef DEBUG
+static inline void dnet_print_skb(struct sk_buff *skb)
+{
+	int k;
+	printk(KERN_DEBUG PFX "data:");
+	for (k = 0; k < skb->len; k++)
+		printk(" %02x", (unsigned int)skb->data[k]);
+	printk("\n");
+}
+#else
+#define dnet_print_skb(skb)	do {} while (0)
+#endif
+
+static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+
+	struct dnet *bp = netdev_priv(dev);
+	unsigned int i, tx_cmd, wrsz;
+	unsigned long flags;
+	unsigned int *bufp;
+	u32 irq_enable;
+
+	dnet_readl(bp, TX_STATUS);
+
+	pr_debug("start_xmit: len %u head %p data %p\n",
+	       skb->len, skb->head, skb->data);
+	dnet_print_skb(skb);
+
+	spin_lock_irqsave(&bp->lock, flags);
+
+	dnet_readl(bp, TX_STATUS);
+
+	bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL);
+	wrsz = (u32) skb->len + 3;
+	wrsz += ((unsigned long) skb->data) & 0x3;
+	wrsz >>= 2;
+	tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len;
+
+	/* check if there is enough room for the current frame */
+	if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) {
+		for (i = 0; i < wrsz; i++)
+			dnet_writel(bp, *bufp++, TX_DATA_FIFO);
+
+		/*
+		 * inform MAC that a packet's written and ready to be
+		 * shipped out
+		 */
+		dnet_writel(bp, tx_cmd, TX_LEN_FIFO);
+	}
+
+	if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) {
+		netif_stop_queue(dev);
+		dnet_readl(bp, INTR_SRC);
+		irq_enable = dnet_readl(bp, INTR_ENB);
+		irq_enable |= DNET_INTR_ENB_TX_FIFOAE;
+		dnet_writel(bp, irq_enable, INTR_ENB);
+	}
+
+	skb_tx_timestamp(skb);
+
+	spin_unlock_irqrestore(&bp->lock, flags);
+
+	/* free the buffer */
+	dev_kfree_skb(skb);
+
+	return NETDEV_TX_OK;
+}
+
+static void dnet_reset_hw(struct dnet *bp)
+{
+	/* put ts_mac in IDLE state i.e. disable rx/tx */
+	dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN);
+
+	/*
+	 * RX FIFO almost full threshold: only cmd FIFO almost full is
+	 * implemented for RX side
+	 */
+	dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH);
+	/*
+	 * TX FIFO almost empty threshold: only data FIFO almost empty
+	 * is implemented for TX side
+	 */
+	dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH);
+
+	/* flush rx/tx fifos */
+	dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
+			SYS_CTL);
+	msleep(1);
+	dnet_writel(bp, 0, SYS_CTL);
+}
+
+static void dnet_init_hw(struct dnet *bp)
+{
+	u32 config;
+
+	dnet_reset_hw(bp);
+	__dnet_set_hwaddr(bp);
+
+	config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
+
+	if (bp->dev->flags & IFF_PROMISC)
+		/* Copy All Frames */
+		config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC;
+	if (!(bp->dev->flags & IFF_BROADCAST))
+		/* No BroadCast */
+		config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST;
+
+	config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
+	    DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
+	    DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
+	    DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
+
+	dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config);
+
+	/* clear irq before enabling them */
+	config = dnet_readl(bp, INTR_SRC);
+
+	/* enable RX/TX interrupt, recv packet ready interrupt */
+	dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY |
+			DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR |
+			DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL |
+			DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM |
+			DNET_INTR_ENB_RX_PKTRDY, INTR_ENB);
+}
+
+static int dnet_open(struct net_device *dev)
+{
+	struct dnet *bp = netdev_priv(dev);
+
+	/* if the phy is not yet register, retry later */
+	if (!dev->phydev)
+		return -EAGAIN;
+
+	napi_enable(&bp->napi);
+	dnet_init_hw(bp);
+
+	phy_start_aneg(dev->phydev);
+
+	/* schedule a link state check */
+	phy_start(dev->phydev);
+
+	netif_start_queue(dev);
+
+	return 0;
+}
+
+static int dnet_close(struct net_device *dev)
+{
+	struct dnet *bp = netdev_priv(dev);
+
+	netif_stop_queue(dev);
+	napi_disable(&bp->napi);
+
+	if (dev->phydev)
+		phy_stop(dev->phydev);
+
+	dnet_reset_hw(bp);
+	netif_carrier_off(dev);
+
+	return 0;
+}
+
+static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat)
+{
+	pr_debug("%s\n", __func__);
+	pr_debug("----------------------------- RX statistics "
+		 "-------------------------------\n");
+	pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr);
+	pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err);
+	pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm);
+	pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm);
+	pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol);
+	pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err);
+	pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt);
+	pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm);
+	pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm);
+	pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast);
+	pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast);
+	pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag);
+	pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink);
+	pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib);
+	pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd);
+	pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte);
+	pr_debug("----------------------------- TX statistics "
+		 "-------------------------------\n");
+	pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast);
+	pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm);
+	pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast);
+	pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast);
+	pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag);
+	pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs);
+	pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo);
+	pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte);
+}
+
+static struct net_device_stats *dnet_get_stats(struct net_device *dev)
+{
+
+	struct dnet *bp = netdev_priv(dev);
+	struct net_device_stats *nstat = &dev->stats;
+	struct dnet_stats *hwstat = &bp->hw_stats;
+
+	/* read stats from hardware */
+	dnet_update_stats(bp);
+
+	/* Convert HW stats into netdevice stats */
+	nstat->rx_errors = (hwstat->rx_len_chk_err +
+			    hwstat->rx_lng_frm + hwstat->rx_shrt_frm +
+			    /* ignore IGP violation error
+			    hwstat->rx_ipg_viol + */
+			    hwstat->rx_crc_err +
+			    hwstat->rx_pre_shrink +
+			    hwstat->rx_drib_nib + hwstat->rx_unsup_opcd);
+	nstat->tx_errors = hwstat->tx_bad_fcs;
+	nstat->rx_length_errors = (hwstat->rx_len_chk_err +
+				   hwstat->rx_lng_frm +
+				   hwstat->rx_shrt_frm + hwstat->rx_pre_shrink);
+	nstat->rx_crc_errors = hwstat->rx_crc_err;
+	nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib;
+	nstat->rx_packets = hwstat->rx_ok_pkt;
+	nstat->tx_packets = (hwstat->tx_unicast +
+			     hwstat->tx_multicast + hwstat->tx_brdcast);
+	nstat->rx_bytes = hwstat->rx_byte;
+	nstat->tx_bytes = hwstat->tx_byte;
+	nstat->multicast = hwstat->rx_multicast;
+	nstat->rx_missed_errors = hwstat->rx_pkt_ignr;
+
+	dnet_print_pretty_hwstats(hwstat);
+
+	return nstat;
+}
+
+static void dnet_get_drvinfo(struct net_device *dev,
+			     struct ethtool_drvinfo *info)
+{
+	strscpy(info->driver, DRV_NAME, sizeof(info->driver));
+	strscpy(info->bus_info, "0", sizeof(info->bus_info));
+}
+
+static const struct ethtool_ops dnet_ethtool_ops = {
+	.get_drvinfo		= dnet_get_drvinfo,
+	.get_link		= ethtool_op_get_link,
+	.get_ts_info		= ethtool_op_get_ts_info,
+	.get_link_ksettings     = phy_ethtool_get_link_ksettings,
+	.set_link_ksettings     = phy_ethtool_set_link_ksettings,
+};
+
+static const struct net_device_ops dnet_netdev_ops = {
+	.ndo_open		= dnet_open,
+	.ndo_stop		= dnet_close,
+	.ndo_get_stats		= dnet_get_stats,
+	.ndo_start_xmit		= dnet_start_xmit,
+	.ndo_eth_ioctl		= phy_do_ioctl_running,
+	.ndo_set_mac_address	= eth_mac_addr,
+	.ndo_validate_addr	= eth_validate_addr,
+};
+
+static int dnet_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct net_device *dev;
+	struct dnet *bp;
+	struct phy_device *phydev;
+	int err;
+	unsigned int irq;
+
+	irq = platform_get_irq(pdev, 0);
+
+	dev = alloc_etherdev(sizeof(*bp));
+	if (!dev)
+		return -ENOMEM;
+
+	/* TODO: Actually, we have some interesting features... */
+	dev->features |= 0;
+
+	bp = netdev_priv(dev);
+	bp->dev = dev;
+
+	platform_set_drvdata(pdev, dev);
+	SET_NETDEV_DEV(dev, &pdev->dev);
+
+	spin_lock_init(&bp->lock);
+
+	bp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(bp->regs)) {
+		err = PTR_ERR(bp->regs);
+		goto err_out_free_dev;
+	}
+
+	dev->irq = irq;
+	err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev);
+	if (err) {
+		dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
+		       irq, err);
+		goto err_out_free_dev;
+	}
+
+	dev->netdev_ops = &dnet_netdev_ops;
+	netif_napi_add(dev, &bp->napi, dnet_poll);
+	dev->ethtool_ops = &dnet_ethtool_ops;
+
+	dev->base_addr = (unsigned long)bp->regs;
+
+	bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK;
+
+	dnet_get_hwaddr(bp);
+
+	if (!is_valid_ether_addr(dev->dev_addr)) {
+		/* choose a random ethernet address */
+		eth_hw_addr_random(dev);
+		__dnet_set_hwaddr(bp);
+	}
+
+	err = register_netdev(dev);
+	if (err) {
+		dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
+		goto err_out_free_irq;
+	}
+
+	/* register the PHY board fixup (for Marvell 88E1111) */
+	err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
+					 dnet_phy_marvell_fixup);
+	/* we can live without it, so just issue a warning */
+	if (err)
+		dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n");
+
+	err = dnet_mii_init(bp);
+	if (err)
+		goto err_out_unregister_netdev;
+
+	dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
+	       bp->regs, (unsigned int)res->start, dev->irq, dev->dev_addr);
+	dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n",
+	       (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ",
+	       (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ",
+	       (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ",
+	       (bp->capabilities & DNET_HAS_DMA) ? "" : "no ");
+	phydev = dev->phydev;
+	phy_attached_info(phydev);
+
+	return 0;
+
+err_out_unregister_netdev:
+	unregister_netdev(dev);
+err_out_free_irq:
+	free_irq(dev->irq, dev);
+err_out_free_dev:
+	free_netdev(dev);
+	return err;
+}
+
+static int dnet_remove(struct platform_device *pdev)
+{
+
+	struct net_device *dev;
+	struct dnet *bp;
+
+	dev = platform_get_drvdata(pdev);
+
+	if (dev) {
+		bp = netdev_priv(dev);
+		if (dev->phydev)
+			phy_disconnect(dev->phydev);
+		mdiobus_unregister(bp->mii_bus);
+		mdiobus_free(bp->mii_bus);
+		unregister_netdev(dev);
+		free_irq(dev->irq, dev);
+		free_netdev(dev);
+	}
+
+	return 0;
+}
+
+static struct platform_driver dnet_driver = {
+	.probe		= dnet_probe,
+	.remove		= dnet_remove,
+	.driver		= {
+		.name		= "dnet",
+	},
+};
+
+module_platform_driver(dnet_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Dave DNET Ethernet driver");
+MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
+	      "Matteo Vit <matteo.vit@dave.eu>");