Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted

Pull networking updates from Jakub Kicinski:
 "Core:

   - Add dedicated kmem_cache for typical/small skb->head, avoid having
     to access struct page at kfree time, and improve memory use.

   - Introduce sysctl to set default RPS configuration for new netdevs.

   - Define Netlink protocol specification format which can be used to
     describe messages used by each family and auto-generate parsers.
     Add tools for generating kernel data structures and uAPI headers.

   - Expose all net/core sysctls inside netns.

   - Remove 4s sleep in netpoll if carrier is instantly detected on
     boot.

   - Add configurable limit of MDB entries per port, and port-vlan.

   - Continue populating drop reasons throughout the stack.

   - Retire a handful of legacy Qdiscs and classifiers.

  Protocols:

   - Support IPv4 big TCP (TSO frames larger than 64kB).

   - Add IP_LOCAL_PORT_RANGE socket option, to control local port range
     on socket by socket basis.

   - Track and report in procfs number of MPTCP sockets used.

   - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
     manager.

   - IPv6: don't check net.ipv6.route.max_size and rely on garbage
     collection to free memory (similarly to IPv4).

   - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).

   - ICMP: add per-rate limit counters.

   - Add support for user scanning requests in ieee802154.

   - Remove static WEP support.

   - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
     reporting.

   - WiFi 7 EHT channel puncturing support (client & AP).

  BPF:

   - Add a rbtree data structure following the "next-gen data structure"
     precedent set by recently added linked list, that is, by using
     kfunc + kptr instead of adding a new BPF map type.

   - Expose XDP hints via kfuncs with initial support for RX hash and
     timestamp metadata.

   - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
     better support decap on GRE tunnel devices not operating in collect
     metadata.

   - Improve x86 JIT's codegen for PROBE_MEM runtime error checks.

   - Remove the need for trace_printk_lock for bpf_trace_printk and
     bpf_trace_vprintk helpers.

   - Extend libbpf's bpf_tracing.h support for tracing arguments of
     kprobes/uprobes and syscall as a special case.

   - Significantly reduce the search time for module symbols by
     livepatch and BPF.

   - Enable cpumasks to be used as kptrs, which is useful for tracing
     programs tracking which tasks end up running on which CPUs in
     different time intervals.

   - Add support for BPF trampoline on s390x and riscv64.

   - Add capability to export the XDP features supported by the NIC.

   - Add __bpf_kfunc tag for marking kernel functions as kfuncs.

   - Add cgroup.memory=nobpf kernel parameter option to disable BPF
     memory accounting for container environments.

  Netfilter:

   - Remove the CLUSTERIP target. It has been marked as obsolete for
     years, and we still have WARN splats wrt races of the out-of-band
     /proc interface installed by this target.

   - Add 'destroy' commands to nf_tables. They are identical to the
     existing 'delete' commands, but do not return an error if the
     referenced object (set, chain, rule...) did not exist.

  Driver API:

   - Improve cpumask_local_spread() locality to help NICs set the right
     IRQ affinity on AMD platforms.

   - Separate C22 and C45 MDIO bus transactions more clearly.

   - Introduce new DCB table to control DSCP rewrite on egress.

   - Support configuration of Physical Layer Collision Avoidance (PLCA)
     Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
     shared medium Ethernet.

   - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
     preemption of low priority frames by high priority frames.

   - Add support for controlling MACSec offload using netlink SET.

   - Rework devlink instance refcounts to allow registration and
     de-registration under the instance lock. Split the code into
     multiple files, drop some of the unnecessarily granular locks and
     factor out common parts of netlink operation handling.

   - Add TX frame aggregation parameters (for USB drivers).

   - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
     messages with notifications for debug.

   - Allow offloading of UDP NEW connections via act_ct.

   - Add support for per action HW stats in TC.

   - Support hardware miss to TC action (continue processing in SW from
     a specific point in the action chain).

   - Warn if old Wireless Extension user space interface is used with
     modern cfg80211/mac80211 drivers. Do not support Wireless
     Extensions for Wi-Fi 7 devices at all. Everyone should switch to
     using nl80211 interface instead.

   - Improve the CAN bit timing configuration. Use extack to return
     error messages directly to user space, update the SJW handling,
     including the definition of a new default value that will benefit
     CAN-FD controllers, by increasing their oscillator tolerance.

  New hardware / drivers:

   - Ethernet:
      - nVidia BlueField-3 support (control traffic driver)
      - Ethernet support for imx93 SoCs
      - Motorcomm yt8531 gigabit Ethernet PHY
      - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
      - Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
      - Amlogic gxl MDIO mux

   - WiFi:
      - RealTek RTL8188EU (rtl8xxxu)
      - Qualcomm Wi-Fi 7 devices (ath12k)

   - CAN:
      - Renesas R-Car V4H

  Drivers:

   - Bluetooth:
      - Set Per Platform Antenna Gain (PPAG) for Intel controllers.

   - Ethernet NICs:
      - Intel (1G, igc):
         - support TSN / Qbv / packet scheduling features of i226 model
      - Intel (100G, ice):
         - use GNSS subsystem instead of TTY
         - multi-buffer XDP support
         - extend support for GPIO pins to E823 devices
      - nVidia/Mellanox:
         - update the shared buffer configuration on PFC commands
         - implement PTP adjphase function for HW offset control
         - TC support for Geneve and GRE with VF tunnel offload
         - more efficient crypto key management method
         - multi-port eswitch support
      - Netronome/Corigine:
         - add DCB IEEE support
         - support IPsec offloading for NFP3800
      - Freescale/NXP (enetc):
         - support XDP_REDIRECT for XDP non-linear buffers
         - improve reconfig, avoid link flap and waiting for idle
         - support MAC Merge layer
      - Other NICs:
         - sfc/ef100: add basic devlink support for ef100
         - ionic: rx_push mode operation (writing descriptors via MMIO)
         - bnxt: use the auxiliary bus abstraction for RDMA
         - r8169: disable ASPM and reset bus in case of tx timeout
         - cpsw: support QSGMII mode for J721e CPSW9G
         - cpts: support pulse-per-second output
         - ngbe: add an mdio bus driver
         - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
         - r8152: handle devices with FW with NCM support
         - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
         - virtio-net: support multi buffer XDP
         - virtio/vsock: replace virtio_vsock_pkt with sk_buff
         - tsnep: XDP support

   - Ethernet high-speed switches:
      - nVidia/Mellanox (mlxsw):
         - add support for latency TLV (in FW control messages)
      - Microchip (sparx5):
         - separate explicit and implicit traffic forwarding rules, make
           the implicit rules always active
         - add support for egress DSCP rewrite
         - IS0 VCAP support (Ingress Classification)
         - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
           etc.)
         - ES2 VCAP support (Egress Access Control)
         - support for Per-Stream Filtering and Policing (802.1Q,
           8.6.5.1)

   - Ethernet embedded switches:
      - Marvell (mv88e6xxx):
         - add MAB (port auth) offload support
         - enable PTP receive for mv88e6390
      - NXP (ocelot):
         - support MAC Merge layer
         - support for the the vsc7512 internal copper phys
      - Microchip:
         - lan9303: convert to PHYLINK
         - lan966x: support TC flower filter statistics
         - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
         - lan937x: support Credit Based Shaper configuration
         - ksz9477: support Energy Efficient Ethernet
      - other:
         - qca8k: convert to regmap read/write API, use bulk operations
         - rswitch: Improve TX timestamp accuracy

   - Intel WiFi (iwlwifi):
      - EHT (Wi-Fi 7) rate reporting
      - STEP equalizer support: transfer some STEP (connection to radio
        on platforms with integrated wifi) related parameters from the
        BIOS to the firmware.

   - Qualcomm 802.11ax WiFi (ath11k):
      - IPQ5018 support
      - Fine Timing Measurement (FTM) responder role support
      - channel 177 support

   - MediaTek WiFi (mt76):
      - per-PHY LED support
      - mt7996: EHT (Wi-Fi 7) support
      - Wireless Ethernet Dispatch (WED) reset support
      - switch to using page pool allocator

   - RealTek WiFi (rtw89):
      - support new version of Bluetooth co-existance

   - Mobile:
      - rmnet: support TX aggregation"

* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
  page_pool: add a comment explaining the fragment counter usage
  net: ethtool: fix __ethtool_dev_mm_supported() implementation
  ethtool: pse-pd: Fix double word in comments
  xsk: add linux/vmalloc.h to xsk.c
  sefltests: netdevsim: wait for devlink instance after netns removal
  selftest: fib_tests: Always cleanup before exit
  net/mlx5e: Align IPsec ASO result memory to be as required by hardware
  net/mlx5e: TC, Set CT miss to the specific ct action instance
  net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
  net/mlx5: Refactor tc miss handling to a single function
  net/mlx5: Kconfig: Make tc offload depend on tc skb extension
  net/sched: flower: Support hardware miss to tc action
  net/sched: flower: Move filter handle initialization earlier
  net/sched: cls_api: Support hardware miss to tc action
  net/sched: Rename user cookie and act cookie
  sfc: fix builds without CONFIG_RTC_LIB
  sfc: clean up some inconsistent indentings
  net/mlx4_en: Introduce flexible array to silence overflow warning
  net: lan966x: Fix possible deadlock inside PTP
  net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
  ...

1 files changed, 971 insertions, 0 deletions

diff --git a/drivers/scsi/script_asm.pl b/drivers/scsi/script_asm.pl
new file mode 100644
index 000000000..0300f4c55
--- /dev/null
+++ b/drivers/scsi/script_asm.pl
@@ -0,0 +1,971 @@
+#!/usr/bin/perl -s
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NCR 53c810 script assembler
+# Sponsored by 
+#       iX Multiuser Multitasking Magazine
+#
+# Copyright 1993, Drew Eckhardt
+#      Visionary Computing 
+#      (Unix and Linux consulting and custom programming)
+#      drew@Colorado.EDU
+#      +1 (303) 786-7975 
+#
+#   Support for 53c710 (via -ncr7x0_family switch) added by Richard
+#   Hirst <richard@sleepie.demon.co.uk> - 15th March 1997
+#
+# TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
+#
+
+# 
+# Basically, I follow the NCR syntax documented in the NCR53c710 
+# Programmer's guide, with the new instructions, registers, etc.
+# from the NCR53c810.
+#
+# Differences between this assembler and NCR's are that 
+# 1.  PASS, REL (data, JUMPs work fine), and the option to start a new 
+#	script,  are unimplemented, since I didn't use them in my scripts.
+# 
+# 2.  I also emit a script_u.h file, which will undefine all of 
+# 	the A_*, E_*, etc. symbols defined in the script.  This 
+#	makes including multiple scripts in one program easier
+# 	
+# 3.  This is a single pass assembler, which only emits 
+#	.h files.
+#
+
+
+# XXX - set these with command line options
+$debug = 0;		# Print general debugging messages
+$debug_external = 0;	# Print external/forward reference messages
+$list_in_array = 1;	# Emit original SCRIPTS assembler in comments in
+			# script.h
+#$prefix;		# (set by perl -s)
+                        # define all arrays having this prefix so we 
+			# don't have name space collisions after 
+			# assembling this file in different ways for
+			# different host adapters
+
+# Constants
+
+
+# Table of the SCSI phase encodings
+%scsi_phases = ( 			
+    'DATA_OUT', 0x00_00_00_00, 'DATA_IN', 0x01_00_00_00, 'CMD', 0x02_00_00_00,
+    'STATUS', 0x03_00_00_00, 'MSG_OUT', 0x06_00_00_00, 'MSG_IN', 0x07_00_00_00
+);
+
+# XXX - replace references to the *_810 constants with general constants
+# assigned at compile time based on chip type.
+
+# Table of operator encodings
+# XXX - NCR53c710 only implements 
+# 	move (nop) = 0x00_00_00_00
+#	or = 0x02_00_00_00
+# 	and = 0x04_00_00_00
+# 	add = 0x06_00_00_00
+
+if ($ncr7x0_family) {
+  %operators = (
+    '|', 0x02_00_00_00, 'OR', 0x02_00_00_00,
+    '&', 0x04_00_00_00, 'AND', 0x04_00_00_00,
+    '+', 0x06_00_00_00
+  );
+}
+else {
+  %operators = (
+    'SHL',  0x01_00_00_00, 
+    '|', 0x02_00_00_00, 'OR', 0x02_00_00_00, 
+    'XOR', 0x03_00_00_00, 
+    '&', 0x04_00_00_00, 'AND', 0x04_00_00_00, 
+    'SHR', 0x05_00_00_00, 
+    # Note : low bit of the operator bit should be set for add with 
+    # carry.
+    '+', 0x06_00_00_00 
+  );
+}
+
+# Table of register addresses
+
+if ($ncr7x0_family) {
+  %registers = (
+    'SCNTL0', 0, 'SCNTL1', 1, 'SDID', 2, 'SIEN', 3,
+    'SCID', 4, 'SXFER', 5, 'SODL', 6, 'SOCL', 7,
+    'SFBR', 8, 'SIDL', 9, 'SBDL', 10, 'SBCL', 11,
+    'DSTAT', 12, 'SSTAT0', 13, 'SSTAT1', 14, 'SSTAT2', 15,
+    'DSA0', 16, 'DSA1', 17, 'DSA2', 18, 'DSA3', 19,
+    'CTEST0', 20, 'CTEST1', 21, 'CTEST2', 22, 'CTEST3', 23,
+    'CTEST4', 24, 'CTEST5', 25, 'CTEST6', 26, 'CTEST7', 27,
+    'TEMP0', 28, 'TEMP1', 29, 'TEMP2', 30, 'TEMP3', 31,
+    'DFIFO', 32, 'ISTAT', 33, 'CTEST8', 34, 'LCRC', 35,
+    'DBC0', 36, 'DBC1', 37, 'DBC2', 38, 'DCMD', 39,
+    'DNAD0', 40, 'DNAD1', 41, 'DNAD2', 42, 'DNAD3', 43,
+    'DSP0', 44, 'DSP1', 45, 'DSP2', 46, 'DSP3', 47,
+    'DSPS0', 48, 'DSPS1', 49, 'DSPS2', 50, 'DSPS3', 51,
+    'SCRATCH0', 52, 'SCRATCH1', 53, 'SCRATCH2', 54, 'SCRATCH3', 55,
+    'DMODE', 56, 'DIEN', 57, 'DWT', 58, 'DCNTL', 59,
+    'ADDER0', 60, 'ADDER1', 61, 'ADDER2', 62, 'ADDER3', 63,
+  );
+}
+else {
+  %registers = (
+    'SCNTL0', 0, 'SCNTL1', 1, 'SCNTL2', 2, 'SCNTL3', 3,
+    'SCID', 4, 'SXFER', 5, 'SDID', 6, 'GPREG', 7,
+    'SFBR', 8, 'SOCL', 9, 'SSID', 10, 'SBCL', 11,
+    'DSTAT', 12, 'SSTAT0', 13, 'SSTAT1', 14, 'SSTAT2', 15,
+    'DSA0', 16, 'DSA1', 17, 'DSA2', 18, 'DSA3', 19,
+    'ISTAT', 20,
+    'CTEST0', 24, 'CTEST1', 25, 'CTEST2', 26, 'CTEST3', 27,
+    'TEMP0', 28, 'TEMP1', 29, 'TEMP2', 30, 'TEMP3', 31,
+    'DFIFO', 32, 'CTEST4', 33, 'CTEST5', 34, 'CTEST6', 35,
+    'DBC0', 36, 'DBC1', 37, 'DBC2', 38, 'DCMD', 39,
+    'DNAD0', 40, 'DNAD1', 41, 'DNAD2', 42, 'DNAD3', 43,
+    'DSP0', 44, 'DSP1', 45, 'DSP2', 46, 'DSP3', 47,
+    'DSPS0', 48, 'DSPS1', 49, 'DSPS2', 50, 'DSPS3', 51,
+    'SCRATCH0', 52, 'SCRATCH1', 53, 'SCRATCH2', 54, 'SCRATCH3', 55,
+    'SCRATCHA0', 52, 'SCRATCHA1', 53, 'SCRATCHA2', 54, 'SCRATCHA3', 55,
+    'DMODE', 56, 'DIEN', 57, 'DWT', 58, 'DCNTL', 59,
+    'ADDER0', 60, 'ADDER1', 61, 'ADDER2', 62, 'ADDER3', 63,
+    'SIEN0', 64, 'SIEN1', 65, 'SIST0', 66, 'SIST1', 67,
+    'SLPAR', 68, 	      'MACNTL', 70, 'GPCNTL', 71,
+    'STIME0', 72, 'STIME1', 73, 'RESPID', 74, 
+    'STEST0', 76, 'STEST1', 77, 'STEST2', 78, 'STEST3', 79,
+    'SIDL', 80,
+    'SODL', 84,
+    'SBDL', 88,
+    'SCRATCHB0', 92, 'SCRATCHB1', 93, 'SCRATCHB2', 94, 'SCRATCHB3', 95
+  );
+}
+
+# Parsing regular expressions
+$identifier = '[A-Za-z_][A-Za-z_0-9]*';		
+$decnum = '-?\\d+';
+$hexnum = '0[xX][0-9A-Fa-f]+';		
+$constant = "$hexnum|$decnum";
+
+# yucky - since we can't control grouping of # $constant, we need to 
+# expand out each alternative for $value.
+
+$value = "$identifier|$identifier\\s*[+\-]\\s*$decnum|".
+    "$identifier\\s*[+-]\s*$hexnum|$constant";
+
+print STDERR "value regex = $value\n" if ($debug);
+
+$phase = join ('|', keys %scsi_phases);
+print STDERR "phase regex = $phase\n" if ($debug);
+$register = join ('|', keys %registers);
+
+# yucky - since %operators includes meta-characters which must
+# be escaped, I can't use the join() trick I used for the register
+# regex
+
+if ($ncr7x0_family) {
+  $operator = '\||OR|AND|\&|\+';
+}
+else {
+  $operator = '\||OR|AND|XOR|\&|\+';
+}
+
+# Global variables
+
+%symbol_values = (%registers) ;		# Traditional symbol table
+
+%symbol_references = () ;		# Table of symbol references, where
+					# the index is the symbol name, 
+					# and the contents a white space 
+					# delimited list of address,size
+					# tuples where size is in bytes.
+
+@code = ();				# Array of 32 bit words for SIOP 
+
+@entry = ();				# Array of entry point names
+
+@label = ();				# Array of label names
+
+@absolute = ();				# Array of absolute names
+
+@relative = ();				# Array of relative names
+
+@external = ();				# Array of external names
+
+$address = 0;				# Address of current instruction
+
+$lineno = 0;				# Line number we are parsing
+
+$output = 'script.h';			# Output file
+$outputu = 'scriptu.h';
+
+# &patch ($address, $offset, $length, $value) patches $code[$address]
+# 	so that the $length bytes at $offset have $value added to
+# 	them.  
+
+@inverted_masks = (0x00_00_00_00, 0x00_00_00_ff, 0x00_00_ff_ff, 0x00_ff_ff_ff, 
+    0xff_ff_ff_ff);
+
+sub patch {
+    local ($address, $offset, $length, $value) = @_;
+    if ($debug) {
+	print STDERR "Patching $address at offset $offset, length $length to $value\n";
+	printf STDERR "Old code : %08x\n", $code[$address];
+     }
+
+    $mask = ($inverted_masks[$length] << ($offset * 8));
+   
+    $code[$address] = ($code[$address] & ~$mask) | 
+	(($code[$address] & $mask) + ($value << ($offset * 8)) & 
+	$mask);
+    
+    printf STDERR "New code : %08x\n", $code[$address] if ($debug);
+}
+
+# &parse_value($value, $word, $offset, $length) where $value is 
+# 	an identifier or constant, $word is the word offset relative to 
+#	$address, $offset is the starting byte within that word, and 
+#	$length is the length of the field in bytes.
+#
+# Side effects are that the bytes are combined into the @code array
+#	relative to $address, and that the %symbol_references table is 
+# 	updated as appropriate.
+
+sub parse_value {
+    local ($value, $word, $offset, $length) = @_;
+    local ($tmp);
+
+    $symbol = '';
+
+    if ($value =~ /^REL\s*\(\s*($identifier)\s*\)\s*(.*)/i) {
+	$relative = 'REL';
+	$symbol = $1;
+	$value = $2;
+print STDERR "Relative reference $symbol\n" if ($debug);
+    } elsif ($value =~ /^($identifier)\s*(.*)/) {
+	$relative = 'ABS';
+	$symbol = $1;
+	$value = $2;
+print STDERR "Absolute reference $symbol\n" if ($debug);
+    } 
+
+    if ($symbol ne '') {
+print STDERR "Referencing symbol $1, length = $length in $_\n" if ($debug);
+     	$tmp = ($address + $word) * 4 + $offset;
+	if ($symbol_references{$symbol} ne undef) {
+	    $symbol_references{$symbol} = 
+		"$symbol_references{$symbol} $relative,$tmp,$length";
+	} else {
+	    if (!defined($symbol_values{$symbol})) {
+print STDERR "forward $1\n" if ($debug_external);
+		$forward{$symbol} = "line $lineno : $_";
+	    } 
+	    $symbol_references{$symbol} = "$relative,$tmp,$length";
+	}
+    } 
+
+    $value = eval $value;
+    &patch ($address + $word, $offset, $length, $value);
+}
+
+# &parse_conditional ($conditional) where $conditional is the conditional
+# clause from a transfer control instruction (RETURN, CALL, JUMP, INT).
+
+sub parse_conditional {
+    local ($conditional) = @_;
+    if ($conditional =~ /^\s*(IF|WHEN)\s*(.*)/i) {
+	$if = $1;
+	$conditional = $2;
+	if ($if =~ /WHEN/i) {
+	    $allow_atn = 0;
+	    $code[$address] |= 0x00_01_00_00;
+	    $allow_atn = 0;
+	    print STDERR "$0 : parsed WHEN\n" if ($debug);
+	} else {
+	    $allow_atn = 1;
+	    print STDERR "$0 : parsed IF\n" if ($debug);
+	}
+    } else {
+	    die "$0 : syntax error in line $lineno : $_
+	expected IF or WHEN
+";
+    }
+
+    if ($conditional =~ /^NOT\s+(.*)$/i) {
+	$not = 'NOT ';
+	$other = 'OR';
+	$conditional = $1;
+	print STDERR "$0 : parsed NOT\n" if ($debug);
+    } else {
+	$code[$address] |= 0x00_08_00_00;
+	$not = '';
+	$other = 'AND'
+    }
+
+    $need_data = 0;
+    if ($conditional =~ /^ATN\s*(.*)/i) {#
+	die "$0 : syntax error in line $lineno : $_
+	WHEN conditional is incompatible with ATN 
+" if (!$allow_atn);
+	$code[$address] |= 0x00_02_00_00;
+	$conditional = $1;
+	print STDERR "$0 : parsed ATN\n" if ($debug);
+    } elsif ($conditional =~ /^($phase)\s*(.*)/i) {
+	$phase_index = "\U$1\E";
+	$p = $scsi_phases{$phase_index};
+	$code[$address] |= $p | 0x00_02_00_00;
+	$conditional = $2;
+	print STDERR "$0 : parsed phase $phase_index\n" if ($debug);
+    } else {
+	$other = '';
+	$need_data = 1;
+    }
+
+print STDERR "Parsing conjunction, expecting $other\n" if ($debug);
+    if ($conditional =~ /^(AND|OR)\s*(.*)/i) {
+	$conjunction = $1;
+	$conditional = $2;
+	$need_data = 1;
+	die "$0 : syntax error in line $lineno : $_
+	    Illegal use of $1.  Valid uses are 
+	    ".$not."<phase> $1 data
+	    ".$not."ATN $1 data
+" if ($other eq '');
+	die "$0 : syntax error in line $lineno : $_
+	Illegal use of $conjunction.  Valid syntaxes are 
+		NOT <phase>|ATN OR data
+		<phase>|ATN AND data
+" if ($conjunction !~ /\s*$other\s*/i);
+	print STDERR "$0 : parsed $1\n" if ($debug);
+    }
+
+    if ($need_data) {
+print STDERR "looking for data in $conditional\n" if ($debug);
+	if ($conditional=~ /^($value)\s*(.*)/i) {
+	    $code[$address] |= 0x00_04_00_00;
+	    $conditional = $2;
+	    &parse_value($1, 0, 0, 1);
+	    print STDERR "$0 : parsed data\n" if ($debug);
+	} else {
+	die "$0 : syntax error in line $lineno : $_
+	expected <data>.
+";
+	}
+    }
+
+    if ($conditional =~ /^\s*,\s*(.*)/) {
+	$conditional = $1;
+	if ($conditional =~ /^AND\s\s*MASK\s\s*($value)\s*(.*)/i) {
+	    &parse_value ($1, 0, 1, 1);
+	    print STDERR "$0 parsed AND MASK $1\n" if ($debug);
+	    die "$0 : syntax error in line $lineno : $_
+	expected end of line, not \"$2\"
+" if ($2 ne '');
+	} else {
+	    die "$0 : syntax error in line $lineno : $_
+	expected \",AND MASK <data>\", not \"$2\"
+";
+	}
+    } elsif ($conditional !~ /^\s*$/) { 
+	die "$0 : syntax error in line $lineno : $_
+	expected end of line" . (($need_data) ? " or \"AND MASK <data>\"" : "") . "
+	not \"$conditional\"
+";
+    }
+}
+
+# Parse command line
+$output = shift;
+$outputu = shift;
+
+    
+# Main loop
+while (<STDIN>) {
+    $lineno = $lineno + 1;
+    $list[$address] = $list[$address].$_;
+    s/;.*$//;				# Strip comments
+
+
+    chop;				# Leave new line out of error messages
+
+# Handle symbol definitions of the form label:
+    if (/^\s*($identifier)\s*:(.*)/) {
+	if (!defined($symbol_values{$1})) {
+	    $symbol_values{$1} = $address * 4;	# Address is an index into
+	    delete $forward{$1};		# an array of longs
+	    push (@label, $1);
+	    $_ = $2;
+	} else {
+	    die "$0 : redefinition of symbol $1 in line $lineno : $_\n";
+	}
+    }
+
+# Handle symbol definitions of the form ABSOLUTE or RELATIVE identifier = 
+# value
+    if (/^\s*(ABSOLUTE|RELATIVE)\s+(.*)/i) {
+	$is_absolute = $1;
+	$rest = $2;
+	foreach $rest (split (/\s*,\s*/, $rest)) {
+	    if ($rest =~ /^($identifier)\s*=\s*($constant)\s*$/) {
+	        local ($id, $cnst) = ($1, $2);
+		if ($symbol_values{$id} eq undef) {
+		    $symbol_values{$id} = eval $cnst;
+		    delete $forward{$id};
+		    if ($is_absolute =~ /ABSOLUTE/i) {
+			push (@absolute , $id);
+		    } else {
+			push (@relative, $id);
+		    }
+		} else {
+		    die "$0 : redefinition of symbol $id in line $lineno : $_\n";
+		}
+	    } else {
+		die 
+"$0 : syntax error in line $lineno : $_
+	    expected <identifier> = <value>
+";
+	    }
+	}
+    } elsif (/^\s*EXTERNAL\s+(.*)/i) {
+	$externals = $1;
+	foreach $external (split (/,/,$externals)) {
+	    if ($external =~ /\s*($identifier)\s*$/) {
+		$external = $1;
+		push (@external, $external);
+		delete $forward{$external};
+		if (defined($symbol_values{$external})) {
+			die "$0 : redefinition of symbol $1 in line $lineno : $_\n";
+		}
+		$symbol_values{$external} = $external;
+print STDERR "defined external $1 to $external\n" if ($debug_external);
+	    } else {
+		die 
+"$0 : syntax error in line $lineno : $_
+	expected <identifier>, got $external
+";
+	    }
+	}
+# Process ENTRY identifier declarations
+    } elsif (/^\s*ENTRY\s+(.*)/i) {
+	if ($1 =~ /^($identifier)\s*$/) {
+	    push (@entry, $1);
+	} else {
+	    die
+"$0 : syntax error in line $lineno : $_
+	expected ENTRY <identifier>
+";
+	}
+# Process MOVE length, address, WITH|WHEN phase instruction
+    } elsif (/^\s*MOVE\s+(.*)/i) {
+	$rest = $1;
+	if ($rest =~ /^FROM\s+($value)\s*,\s*(WITH|WHEN)\s+($phase)\s*$/i) {
+	    $transfer_addr = $1;
+	    $with_when = $2;
+	    $scsi_phase = $3;
+print STDERR "Parsing MOVE FROM $transfer_addr, $with_when $3\n" if ($debug);
+	    $code[$address] = 0x18_00_00_00 | (($with_when =~ /WITH/i) ? 
+		0x00_00_00_00 : 0x08_00_00_00) | $scsi_phases{$scsi_phase};
+	    &parse_value ($transfer_addr, 1, 0, 4);
+	    $address += 2;
+	} elsif ($rest =~ /^($value)\s*,\s*(PTR\s+|)($value)\s*,\s*(WITH|WHEN)\s+($phase)\s*$/i) {
+	    $transfer_len = $1;
+	    $ptr = $2;
+	    $transfer_addr = $3;
+	    $with_when = $4;
+	    $scsi_phase = $5;
+	    $code[$address] = (($with_when =~ /WITH/i) ? 0x00_00_00_00 : 
+		0x08_00_00_00)  | (($ptr =~ /PTR/i) ? (1 << 29) : 0) | 
+		$scsi_phases{$scsi_phase};
+	    &parse_value ($transfer_len, 0, 0, 3);
+	    &parse_value ($transfer_addr, 1, 0, 4);
+	    $address += 2;
+	} elsif ($rest =~ /^MEMORY\s+(.*)/i) {
+	    $rest = $1;
+	    $code[$address] = 0xc0_00_00_00; 
+	    if ($rest =~ /^($value)\s*,\s*($value)\s*,\s*($value)\s*$/) {
+		$count = $1;
+		$source = $2;
+		$dest =  $3;
+print STDERR "Parsing MOVE MEMORY $count, $source, $dest\n" if ($debug);
+		&parse_value ($count, 0, 0, 3);
+		&parse_value ($source, 1, 0, 4);
+		&parse_value ($dest, 2, 0, 4);
+printf STDERR "Move memory instruction = %08x,%08x,%08x\n", 
+		$code[$address], $code[$address+1], $code[$address +2] if
+		($debug);
+		$address += 3;
+	
+	    } else {
+		die 
+"$0 : syntax error in line $lineno : $_
+	expected <count>, <source>, <destination>
+"
+	    }
+	} elsif ($1 =~ /^(.*)\s+(TO|SHL|SHR)\s+(.*)/i) {
+print STDERR "Parsing register to register move\n" if ($debug);
+	    $src = $1;
+	    $op = "\U$2\E";
+	    $rest = $3;
+
+	    $code[$address] = 0x40_00_00_00;
+	
+	    $force = ($op !~ /TO/i); 
+
+
+print STDERR "Forcing register source \n" if ($force && $debug);
+
+	    if (!$force && $src =~ 
+		/^($register)\s+(-|$operator)\s+($value)\s*$/i) {
+print STDERR "register operand  data8 source\n" if ($debug);
+		$src_reg = "\U$1\E";
+		$op = "\U$2\E";
+		if ($op ne '-') {
+		    $data8 = $3;
+		} else {
+		    die "- is not implemented yet.\n"
+		}
+	    } elsif ($src =~ /^($register)\s*$/i) {
+print STDERR "register source\n" if ($debug);
+		$src_reg = "\U$1\E";
+		# Encode register to register move as a register | 0 
+		# move to register.
+		if (!$force) {
+		    $op = '|';
+		}
+		$data8 = 0;
+	    } elsif (!$force && $src =~ /^($value)\s*$/i) {
+print STDERR "data8 source\n" if ($debug);
+		$src_reg = undef;
+		$op = 'NONE';
+		$data8 = $1;
+	    } else {
+		if (!$force) {
+		    die 
+"$0 : syntax error in line $lineno : $_
+	expected <register>
+		<data8>
+		<register> <operand> <data8>
+";
+		} else {
+		    die
+"$0 : syntax error in line $lineno : $_
+	expected <register>
+";
+		}
+	    }
+	    if ($rest =~ /^($register)\s*(.*)$/i) {
+		$dst_reg = "\U$1\E";
+		$rest = $2;
+	    } else {
+	    die 
+"$0 : syntax error in $lineno : $_
+	expected <register>, got $rest
+";
+	    }
+
+	    if ($rest =~ /^WITH\s+CARRY\s*(.*)/i) {
+		$rest = $1;
+		if ($op eq '+') {
+		    $code[$address] |= 0x01_00_00_00;
+		} else {
+		    die
+"$0 : syntax error in $lineno : $_
+	WITH CARRY option is incompatible with the $op operator.
+";
+		}
+	    }
+
+	    if ($rest !~ /^\s*$/) {
+		die
+"$0 : syntax error in $lineno : $_
+	Expected end of line, got $rest
+";
+	    }
+
+	    print STDERR "source = $src_reg, data = $data8 , destination = $dst_reg\n"
+		if ($debug);
+	    # Note that Move data8 to reg is encoded as a read-modify-write
+	    # instruction.
+	    if (($src_reg eq undef) || ($src_reg eq $dst_reg)) {
+		$code[$address] |= 0x38_00_00_00 | 
+		    ($registers{$dst_reg} << 16);
+	    } elsif ($dst_reg =~ /SFBR/i) {
+		$code[$address] |= 0x30_00_00_00 |
+		    ($registers{$src_reg} << 16);
+	    } elsif ($src_reg =~ /SFBR/i) {
+		$code[$address] |= 0x28_00_00_00 |
+		    ($registers{$dst_reg} << 16);
+	    } else {
+		die
+"$0 : Illegal combination of registers in line $lineno : $_
+	Either source and destination registers must be the same,
+	or either source or destination register must be SFBR.
+";
+	    }
+
+	    $code[$address] |= $operators{$op};
+	    
+	    &parse_value ($data8, 0, 1, 1);
+	    $code[$address] |= $operators{$op};
+	    $code[$address + 1] = 0x00_00_00_00;# Reserved
+	    $address += 2;
+	} else {
+	    die 
+"$0 : syntax error in line $lineno : $_
+	expected (initiator) <length>, <address>, WHEN <phase>
+		 (target) <length>, <address>, WITH <phase>
+		 MEMORY <length>, <source>, <destination>
+		 <expression> TO <register>
+";
+	}
+# Process SELECT {ATN|} id, fail_address
+    } elsif (/^\s*(SELECT|RESELECT)\s+(.*)/i) {
+	$rest = $2;
+	if ($rest =~ /^(ATN|)\s*($value)\s*,\s*($identifier)\s*$/i) {
+	    $atn = $1;
+	    $id = $2;
+	    $alt_addr = $3;
+	    $code[$address] = 0x40_00_00_00 | 
+		(($atn =~ /ATN/i) ? 0x01_00_00_00 : 0);
+	    $code[$address + 1] = 0x00_00_00_00;
+	    &parse_value($id, 0, 2, 1);
+	    &parse_value($alt_addr, 1, 0, 4);
+	    $address += 2;
+	} elsif ($rest =~ /^(ATN|)\s*FROM\s+($value)\s*,\s*($identifier)\s*$/i) {
+	    $atn = $1;
+	    $addr = $2;
+	    $alt_addr = $3;
+	    $code[$address] = 0x42_00_00_00 | 
+		(($atn =~ /ATN/i) ? 0x01_00_00_00 : 0);
+	    $code[$address + 1] = 0x00_00_00_00;
+	    &parse_value($addr, 0, 0, 3);
+	    &parse_value($alt_addr, 1, 0, 4);
+	    $address += 2;
+        } else {
+	    die 
+"$0 : syntax error in line $lineno : $_
+	expected SELECT id, alternate_address or 
+		SELECT FROM address, alternate_address or 
+		RESELECT id, alternate_address or
+		RESELECT FROM address, alternate_address
+";
+	}
+    } elsif (/^\s*WAIT\s+(.*)/i) {
+	    $rest = $1;
+print STDERR "Parsing WAIT $rest\n" if ($debug);
+	if ($rest =~ /^DISCONNECT\s*$/i) {
+	    $code[$address] = 0x48_00_00_00;
+	    $code[$address + 1] = 0x00_00_00_00;
+	    $address += 2;
+	} elsif ($rest =~ /^(RESELECT|SELECT)\s+($identifier)\s*$/i) {
+	    $alt_addr = $2;
+	    $code[$address] = 0x50_00_00_00;
+	    &parse_value ($alt_addr, 1, 0, 4);
+	    $address += 2;
+	} else {
+	    die
+"$0 : syntax error in line $lineno : $_
+	expected (initiator) WAIT DISCONNECT or 
+		 (initiator) WAIT RESELECT alternate_address or
+		 (target) WAIT SELECT alternate_address
+";
+	}
+# Handle SET and CLEAR instructions.  Note that we should also do something
+# with this syntax to set target mode.
+    } elsif (/^\s*(SET|CLEAR)\s+(.*)/i) {
+	$set = $1;
+	$list = $2;
+	$code[$address] = ($set =~ /SET/i) ?  0x58_00_00_00 : 
+	    0x60_00_00_00;
+	foreach $arg (split (/\s+AND\s+/i,$list)) {
+	    if ($arg =~ /ATN/i) {
+		$code[$address] |= 0x00_00_00_08;
+	    } elsif ($arg =~ /ACK/i) {
+		$code[$address] |= 0x00_00_00_40;
+	    } elsif ($arg =~ /TARGET/i) {
+		$code[$address] |= 0x00_00_02_00;
+	    } elsif ($arg =~ /CARRY/i) {
+		$code[$address] |= 0x00_00_04_00;
+	    } else {
+		die 
+"$0 : syntax error in line $lineno : $_
+	expected $set followed by a AND delimited list of one or 
+	more strings from the list ACK, ATN, CARRY, TARGET.
+";
+	    }
+	}
+	$code[$address + 1] = 0x00_00_00_00;
+	$address += 2;
+    } elsif (/^\s*(JUMP|CALL|INT)\s+(.*)/i) {
+	$instruction = $1;
+	$rest = $2;
+	if ($instruction =~ /JUMP/i) {
+	    $code[$address] = 0x80_00_00_00;
+	} elsif ($instruction =~ /CALL/i) {
+	    $code[$address] = 0x88_00_00_00;
+	} else {
+	    $code[$address] = 0x98_00_00_00;
+	}
+print STDERR "parsing JUMP, rest = $rest\n" if ($debug);
+
+# Relative jump. 
+	if ($rest =~ /^(REL\s*\(\s*$identifier\s*\))\s*(.*)/i) { 
+	    $addr = $1;
+	    $rest = $2;
+print STDERR "parsing JUMP REL, addr = $addr, rest = $rest\n" if ($debug);
+	    $code[$address]  |= 0x00_80_00_00;
+	    &parse_value($addr, 1, 0, 4);
+# Absolute jump, requires no more gunk
+	} elsif ($rest =~ /^($value)\s*(.*)/) {
+	    $addr = $1;
+	    $rest = $2;
+	    &parse_value($addr, 1, 0, 4);
+	} else {
+	    die
+"$0 : syntax error in line $lineno : $_
+	expected <address> or REL (address)
+";
+	}
+
+	if ($rest =~ /^,\s*(.*)/) {
+	    &parse_conditional($1);
+	} elsif ($rest =~ /^\s*$/) {
+	    $code[$address] |= (1 << 19);
+	} else {
+	    die
+"$0 : syntax error in line $lineno : $_
+	expected , <conditional> or end of line, got $1
+";
+	}
+	
+	$address += 2;
+    } elsif (/^\s*(RETURN|INTFLY)\s*(.*)/i) {
+	$instruction = $1;
+	$conditional = $2; 
+print STDERR "Parsing $instruction\n" if ($debug);
+	$code[$address] = ($instruction =~ /RETURN/i) ? 0x90_00_00_00 :
+	    0x98_10_00_00;
+	if ($conditional =~ /^,\s*(.*)/) {
+	    $conditional = $1;
+	    &parse_conditional ($conditional);
+	} elsif ($conditional !~ /^\s*$/) {
+	    die
+"$0 : syntax error in line $lineno : $_
+	expected , <conditional> 
+";
+	} else {
+	    $code[$address] |= 0x00_08_00_00;
+	}
+	   
+	$code[$address + 1] = 0x00_00_00_00;
+	$address += 2;
+    } elsif (/^\s*DISCONNECT\s*$/) {
+	$code[$address] = 0x48_00_00_00;
+	$code[$address + 1] = 0x00_00_00_00;
+	$address += 2;
+# I'm not sure that I should be including this extension, but 
+# what the hell?
+    } elsif (/^\s*NOP\s*$/i) {
+	$code[$address] = 0x80_88_00_00;
+	$code[$address + 1] = 0x00_00_00_00;
+	$address += 2;
+# Ignore lines consisting entirely of white space
+    } elsif (/^\s*$/) {
+    } else {
+	die 
+"$0 : syntax error in line $lineno: $_
+	expected label:, ABSOLUTE, CLEAR, DISCONNECT, EXTERNAL, MOVE, RESELECT,
+	    SELECT SET, or WAIT
+";
+    }
+}
+
+# Fill in label references
+
+@undefined = keys %forward;
+if ($#undefined >= 0) {
+    print STDERR "Undefined symbols : \n";
+    foreach $undef (@undefined) {
+	print STDERR "$undef in $forward{$undef}\n";
+    }
+    exit 1;
+}
+
+@label_patches = ();
+
+@external_patches = ();
+
+@absolute = sort @absolute;
+
+foreach $i (@absolute) {
+    foreach $j (split (/\s+/,$symbol_references{$i})) {
+	$j =~ /(REL|ABS),(.*),(.*)/;
+	$type = $1;
+	$address = $2;
+	$length = $3;
+	die 
+"$0 : $symbol $i has invalid relative reference at address $address,
+    size $length\n"
+	if ($type eq 'REL');
+	    
+	&patch ($address / 4, $address % 4, $length, $symbol_values{$i});
+    }
+}
+
+foreach $external (@external) {
+print STDERR "checking external $external \n" if ($debug_external);
+    if ($symbol_references{$external} ne undef) {
+	for $reference (split(/\s+/,$symbol_references{$external})) {
+	    $reference =~ /(REL|ABS),(.*),(.*)/;
+	    $type = $1;
+	    $address = $2;
+	    $length = $3;
+	    
+	    die 
+"$0 : symbol $label is external, has invalid relative reference at $address,
+    size $length\n"
+		if ($type eq 'REL');
+
+	    die 
+"$0 : symbol $label has invalid reference at $address, size $length\n"
+		if ((($address % 4) !=0) || ($length != 4));
+
+	    $symbol = $symbol_values{$external};
+	    $add = $code[$address / 4];
+	    if ($add eq 0) {
+		$code[$address / 4] = $symbol;
+	    } else {
+		$add = sprintf ("0x%08x", $add);
+		$code[$address / 4] = "$symbol + $add";
+	    }
+		
+print STDERR "referenced external $external at $1\n" if ($debug_external);
+	}
+    }
+}
+
+foreach $label (@label) {
+    if ($symbol_references{$label} ne undef) {
+	for $reference (split(/\s+/,$symbol_references{$label})) {
+	    $reference =~ /(REL|ABS),(.*),(.*)/;
+	    $type = $1;
+	    $address = $2;
+	    $length = $3;
+
+	    if ((($address % 4) !=0) || ($length != 4)) {
+		die "$0 : symbol $label has invalid reference at $1, size $2\n";
+	    }
+
+	    if ($type eq 'ABS') {
+		$code[$address / 4] += $symbol_values{$label};
+		push (@label_patches, $address / 4);
+	    } else {
+# 
+# - The address of the reference should be in the second and last word
+#	of an instruction
+# - Relative jumps, etc. are relative to the DSP of the _next_ instruction
+#
+# So, we need to add four to the address of the reference, to get 
+# the address of the next instruction, when computing the reference.
+  
+		$tmp = $symbol_values{$label} - 
+		    ($address + 4);
+		die 
+# Relative addressing is limited to 24 bits.
+"$0 : symbol $label is too far ($tmp) from $address to reference as 
+    relative/\n" if (($tmp >= 0x80_00_00) || ($tmp < -0x80_00_00));
+		$code[$address / 4] = $tmp & 0x00_ff_ff_ff;
+	    }
+	}
+    }
+}
+
+# Output SCRIPT[] array, one instruction per line.  Optionally 
+# print the original code too.
+
+open (OUTPUT, ">$output") || die "$0 : can't open $output for writing\n";
+open (OUTPUTU, ">$outputu") || die "$0 : can't open $outputu for writing\n";
+
+($_ = $0) =~ s:.*/::;
+print OUTPUT "/* DO NOT EDIT - Generated automatically by ".$_." */\n";
+print OUTPUT "static u32 ".$prefix."SCRIPT[] = {\n";
+$instructions = 0;
+for ($i = 0; $i < $#code; ) {
+    if ($list_in_array) {
+	printf OUTPUT "/*\n$list[$i]\nat 0x%08x : */", $i;
+    }
+    printf OUTPUT "\t0x%08x,", $code[$i];
+    printf STDERR "Address $i = %x\n", $code[$i] if ($debug);
+    if ($code[$i + 1] =~ /\s*($identifier)(.*)$/) {
+	push (@external_patches, $i+1, $1);
+	printf OUTPUT "0%s,", $2
+    } else {
+	printf OUTPUT "0x%08x,",$code[$i+1];
+    }
+
+    if (($code[$i] & 0xff_00_00_00) == 0xc0_00_00_00) {
+	if ($code[$i + 2] =~ /$identifier/) {
+	    push (@external_patches, $i+2, $code[$i+2]);
+	    printf OUTPUT "0,\n";
+	} else {
+	    printf OUTPUT "0x%08x,\n",$code[$i+2];
+	}
+	$i += 3;
+    } else {
+	printf OUTPUT "\n";
+	$i += 2;
+    }
+    $instructions += 1;
+}
+print OUTPUT "};\n\n";
+
+foreach $i (@absolute) {
+    printf OUTPUT "#define A_$i\t0x%08x\n", $symbol_values{$i};
+    if (defined($prefix) && $prefix ne '') {
+	printf OUTPUT "#define A_".$i."_used ".$prefix."A_".$i."_used\n";
+	printf OUTPUTU "#undef A_".$i."_used\n";
+    }
+    printf OUTPUTU "#undef A_$i\n";
+
+    printf OUTPUT "static u32 A_".$i."_used\[\] __attribute((unused)) = {\n";
+printf STDERR "$i is used $symbol_references{$i}\n" if ($debug);
+    foreach $j (split (/\s+/,$symbol_references{$i})) {
+	$j =~ /(ABS|REL),(.*),(.*)/;
+	if ($1 eq 'ABS') {
+	    $address = $2;
+	    $length = $3;
+	    printf OUTPUT "\t0x%08x,\n", $address / 4;
+	}
+    }
+    printf OUTPUT "};\n\n";
+}
+
+foreach $i (sort @entry) {
+    printf OUTPUT "#define Ent_$i\t0x%08x\n", $symbol_values{$i};
+    printf OUTPUTU "#undef Ent_$i\n", $symbol_values{$i};
+}
+
+#
+# NCR assembler outputs label patches in the form of indices into 
+# the code.
+#
+printf OUTPUT "static u32 ".$prefix."LABELPATCHES[] __attribute((unused)) = {\n";
+for $patch (sort {$a <=> $b} @label_patches) {
+    printf OUTPUT "\t0x%08x,\n", $patch;
+}
+printf OUTPUT "};\n\n";
+
+$num_external_patches = 0;
+printf OUTPUT "static struct {\n\tu32\toffset;\n\tvoid\t\t*address;\n".
+    "} ".$prefix."EXTERNAL_PATCHES[] __attribute((unused)) = {\n";
+while ($ident = pop(@external_patches)) {
+    $off = pop(@external_patches);
+    printf OUTPUT "\t{0x%08x, &%s},\n", $off, $ident;
+    ++$num_external_patches;
+}
+printf OUTPUT "};\n\n";
+
+printf OUTPUT "static u32 ".$prefix."INSTRUCTIONS __attribute((unused))\t= %d;\n", 
+    $instructions;
+printf OUTPUT "static u32 ".$prefix."PATCHES __attribute((unused))\t= %d;\n", 
+    $#label_patches+1;
+printf OUTPUT "static u32 ".$prefix."EXTERNAL_PATCHES_LEN __attribute((unused))\t= %d;\n",
+    $num_external_patches;
+close OUTPUT;
+close OUTPUTU;