aboutsummaryrefslogtreecommitdiff
path: root/include/video/tgafb.h
diff options
context:
space:
mode:
authorLibravatar Linus Torvalds <torvalds@linux-foundation.org>2023-02-21 18:24:12 -0800
committerLibravatar Linus Torvalds <torvalds@linux-foundation.org>2023-02-21 18:24:12 -0800
commit5b7c4cabbb65f5c469464da6c5f614cbd7f730f2 (patch)
treecc5c2d0a898769fd59549594fedb3ee6f84e59a0 /include/video/tgafb.h
downloadlinux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.tar.gz
linux-5b7c4cabbb65f5c469464da6c5f614cbd7f730f2.zip
Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted
Pull networking updates from Jakub Kicinski: "Core: - Add dedicated kmem_cache for typical/small skb->head, avoid having to access struct page at kfree time, and improve memory use. - Introduce sysctl to set default RPS configuration for new netdevs. - Define Netlink protocol specification format which can be used to describe messages used by each family and auto-generate parsers. Add tools for generating kernel data structures and uAPI headers. - Expose all net/core sysctls inside netns. - Remove 4s sleep in netpoll if carrier is instantly detected on boot. - Add configurable limit of MDB entries per port, and port-vlan. - Continue populating drop reasons throughout the stack. - Retire a handful of legacy Qdiscs and classifiers. Protocols: - Support IPv4 big TCP (TSO frames larger than 64kB). - Add IP_LOCAL_PORT_RANGE socket option, to control local port range on socket by socket basis. - Track and report in procfs number of MPTCP sockets used. - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path manager. - IPv6: don't check net.ipv6.route.max_size and rely on garbage collection to free memory (similarly to IPv4). - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986). - ICMP: add per-rate limit counters. - Add support for user scanning requests in ieee802154. - Remove static WEP support. - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate reporting. - WiFi 7 EHT channel puncturing support (client & AP). BPF: - Add a rbtree data structure following the "next-gen data structure" precedent set by recently added linked list, that is, by using kfunc + kptr instead of adding a new BPF map type. - Expose XDP hints via kfuncs with initial support for RX hash and timestamp metadata. - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to better support decap on GRE tunnel devices not operating in collect metadata. - Improve x86 JIT's codegen for PROBE_MEM runtime error checks. - Remove the need for trace_printk_lock for bpf_trace_printk and bpf_trace_vprintk helpers. - Extend libbpf's bpf_tracing.h support for tracing arguments of kprobes/uprobes and syscall as a special case. - Significantly reduce the search time for module symbols by livepatch and BPF. - Enable cpumasks to be used as kptrs, which is useful for tracing programs tracking which tasks end up running on which CPUs in different time intervals. - Add support for BPF trampoline on s390x and riscv64. - Add capability to export the XDP features supported by the NIC. - Add __bpf_kfunc tag for marking kernel functions as kfuncs. - Add cgroup.memory=nobpf kernel parameter option to disable BPF memory accounting for container environments. Netfilter: - Remove the CLUSTERIP target. It has been marked as obsolete for years, and we still have WARN splats wrt races of the out-of-band /proc interface installed by this target. - Add 'destroy' commands to nf_tables. They are identical to the existing 'delete' commands, but do not return an error if the referenced object (set, chain, rule...) did not exist. Driver API: - Improve cpumask_local_spread() locality to help NICs set the right IRQ affinity on AMD platforms. - Separate C22 and C45 MDIO bus transactions more clearly. - Introduce new DCB table to control DSCP rewrite on egress. - Support configuration of Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of shared medium Ethernet. - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing preemption of low priority frames by high priority frames. - Add support for controlling MACSec offload using netlink SET. - Rework devlink instance refcounts to allow registration and de-registration under the instance lock. Split the code into multiple files, drop some of the unnecessarily granular locks and factor out common parts of netlink operation handling. - Add TX frame aggregation parameters (for USB drivers). - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning messages with notifications for debug. - Allow offloading of UDP NEW connections via act_ct. - Add support for per action HW stats in TC. - Support hardware miss to TC action (continue processing in SW from a specific point in the action chain). - Warn if old Wireless Extension user space interface is used with modern cfg80211/mac80211 drivers. Do not support Wireless Extensions for Wi-Fi 7 devices at all. Everyone should switch to using nl80211 interface instead. - Improve the CAN bit timing configuration. Use extack to return error messages directly to user space, update the SJW handling, including the definition of a new default value that will benefit CAN-FD controllers, by increasing their oscillator tolerance. New hardware / drivers: - Ethernet: - nVidia BlueField-3 support (control traffic driver) - Ethernet support for imx93 SoCs - Motorcomm yt8531 gigabit Ethernet PHY - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA) - Microchip LAN8841 PHY (incl. cable diagnostics and PTP) - Amlogic gxl MDIO mux - WiFi: - RealTek RTL8188EU (rtl8xxxu) - Qualcomm Wi-Fi 7 devices (ath12k) - CAN: - Renesas R-Car V4H Drivers: - Bluetooth: - Set Per Platform Antenna Gain (PPAG) for Intel controllers. - Ethernet NICs: - Intel (1G, igc): - support TSN / Qbv / packet scheduling features of i226 model - Intel (100G, ice): - use GNSS subsystem instead of TTY - multi-buffer XDP support - extend support for GPIO pins to E823 devices - nVidia/Mellanox: - update the shared buffer configuration on PFC commands - implement PTP adjphase function for HW offset control - TC support for Geneve and GRE with VF tunnel offload - more efficient crypto key management method - multi-port eswitch support - Netronome/Corigine: - add DCB IEEE support - support IPsec offloading for NFP3800 - Freescale/NXP (enetc): - support XDP_REDIRECT for XDP non-linear buffers - improve reconfig, avoid link flap and waiting for idle - support MAC Merge layer - Other NICs: - sfc/ef100: add basic devlink support for ef100 - ionic: rx_push mode operation (writing descriptors via MMIO) - bnxt: use the auxiliary bus abstraction for RDMA - r8169: disable ASPM and reset bus in case of tx timeout - cpsw: support QSGMII mode for J721e CPSW9G - cpts: support pulse-per-second output - ngbe: add an mdio bus driver - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing - r8152: handle devices with FW with NCM support - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation - virtio-net: support multi buffer XDP - virtio/vsock: replace virtio_vsock_pkt with sk_buff - tsnep: XDP support - Ethernet high-speed switches: - nVidia/Mellanox (mlxsw): - add support for latency TLV (in FW control messages) - Microchip (sparx5): - separate explicit and implicit traffic forwarding rules, make the implicit rules always active - add support for egress DSCP rewrite - IS0 VCAP support (Ingress Classification) - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS etc.) - ES2 VCAP support (Egress Access Control) - support for Per-Stream Filtering and Policing (802.1Q, 8.6.5.1) - Ethernet embedded switches: - Marvell (mv88e6xxx): - add MAB (port auth) offload support - enable PTP receive for mv88e6390 - NXP (ocelot): - support MAC Merge layer - support for the the vsc7512 internal copper phys - Microchip: - lan9303: convert to PHYLINK - lan966x: support TC flower filter statistics - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x - lan937x: support Credit Based Shaper configuration - ksz9477: support Energy Efficient Ethernet - other: - qca8k: convert to regmap read/write API, use bulk operations - rswitch: Improve TX timestamp accuracy - Intel WiFi (iwlwifi): - EHT (Wi-Fi 7) rate reporting - STEP equalizer support: transfer some STEP (connection to radio on platforms with integrated wifi) related parameters from the BIOS to the firmware. - Qualcomm 802.11ax WiFi (ath11k): - IPQ5018 support - Fine Timing Measurement (FTM) responder role support - channel 177 support - MediaTek WiFi (mt76): - per-PHY LED support - mt7996: EHT (Wi-Fi 7) support - Wireless Ethernet Dispatch (WED) reset support - switch to using page pool allocator - RealTek WiFi (rtw89): - support new version of Bluetooth co-existance - Mobile: - rmnet: support TX aggregation" * tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits) page_pool: add a comment explaining the fragment counter usage net: ethtool: fix __ethtool_dev_mm_supported() implementation ethtool: pse-pd: Fix double word in comments xsk: add linux/vmalloc.h to xsk.c sefltests: netdevsim: wait for devlink instance after netns removal selftest: fib_tests: Always cleanup before exit net/mlx5e: Align IPsec ASO result memory to be as required by hardware net/mlx5e: TC, Set CT miss to the specific ct action instance net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG net/mlx5: Refactor tc miss handling to a single function net/mlx5: Kconfig: Make tc offload depend on tc skb extension net/sched: flower: Support hardware miss to tc action net/sched: flower: Move filter handle initialization earlier net/sched: cls_api: Support hardware miss to tc action net/sched: Rename user cookie and act cookie sfc: fix builds without CONFIG_RTC_LIB sfc: clean up some inconsistent indentings net/mlx4_en: Introduce flexible array to silence overflow warning net: lan966x: Fix possible deadlock inside PTP net/ulp: Remove redundant ->clone() test in inet_clone_ulp(). ...
Diffstat (limited to 'include/video/tgafb.h')
-rw-r--r--include/video/tgafb.h280
1 files changed, 280 insertions, 0 deletions
diff --git a/include/video/tgafb.h b/include/video/tgafb.h
new file mode 100644
index 000000000..7bc5e2c14
--- /dev/null
+++ b/include/video/tgafb.h
@@ -0,0 +1,280 @@
+/*
+ * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
+ *
+ * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
+ *
+ * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef TGAFB_H
+#define TGAFB_H
+
+/*
+ * TGA hardware description (minimal)
+ */
+
+#define TGA_TYPE_8PLANE 0
+#define TGA_TYPE_24PLANE 1
+#define TGA_TYPE_24PLUSZ 3
+
+/*
+ * Offsets within Memory Space
+ */
+
+#define TGA_ROM_OFFSET 0x0000000
+#define TGA_REGS_OFFSET 0x0100000
+#define TGA_8PLANE_FB_OFFSET 0x0200000
+#define TGA_24PLANE_FB_OFFSET 0x0804000
+#define TGA_24PLUSZ_FB_OFFSET 0x1004000
+
+#define TGA_FOREGROUND_REG 0x0020
+#define TGA_BACKGROUND_REG 0x0024
+#define TGA_PLANEMASK_REG 0x0028
+#define TGA_PIXELMASK_ONESHOT_REG 0x002c
+#define TGA_MODE_REG 0x0030
+#define TGA_RASTEROP_REG 0x0034
+#define TGA_PIXELSHIFT_REG 0x0038
+#define TGA_DEEP_REG 0x0050
+#define TGA_START_REG 0x0054
+#define TGA_PIXELMASK_REG 0x005c
+#define TGA_CURSOR_BASE_REG 0x0060
+#define TGA_HORIZ_REG 0x0064
+#define TGA_VERT_REG 0x0068
+#define TGA_BASE_ADDR_REG 0x006c
+#define TGA_VALID_REG 0x0070
+#define TGA_CURSOR_XY_REG 0x0074
+#define TGA_INTR_STAT_REG 0x007c
+#define TGA_DATA_REG 0x0080
+#define TGA_RAMDAC_SETUP_REG 0x00c0
+#define TGA_BLOCK_COLOR0_REG 0x0140
+#define TGA_BLOCK_COLOR1_REG 0x0144
+#define TGA_BLOCK_COLOR2_REG 0x0148
+#define TGA_BLOCK_COLOR3_REG 0x014c
+#define TGA_BLOCK_COLOR4_REG 0x0150
+#define TGA_BLOCK_COLOR5_REG 0x0154
+#define TGA_BLOCK_COLOR6_REG 0x0158
+#define TGA_BLOCK_COLOR7_REG 0x015c
+#define TGA_COPY64_SRC 0x0160
+#define TGA_COPY64_DST 0x0164
+#define TGA_CLOCK_REG 0x01e8
+#define TGA_RAMDAC_REG 0x01f0
+#define TGA_CMD_STAT_REG 0x01f8
+
+
+/*
+ * Useful defines for managing the registers
+ */
+
+#define TGA_HORIZ_ODD 0x80000000
+#define TGA_HORIZ_POLARITY 0x40000000
+#define TGA_HORIZ_ACT_MSB 0x30000000
+#define TGA_HORIZ_BP 0x0fe00000
+#define TGA_HORIZ_SYNC 0x001fc000
+#define TGA_HORIZ_FP 0x00007c00
+#define TGA_HORIZ_ACT_LSB 0x000001ff
+
+#define TGA_VERT_SE 0x80000000
+#define TGA_VERT_POLARITY 0x40000000
+#define TGA_VERT_RESERVED 0x30000000
+#define TGA_VERT_BP 0x0fc00000
+#define TGA_VERT_SYNC 0x003f0000
+#define TGA_VERT_FP 0x0000f800
+#define TGA_VERT_ACTIVE 0x000007ff
+
+#define TGA_VALID_VIDEO 0x01
+#define TGA_VALID_BLANK 0x02
+#define TGA_VALID_CURSOR 0x04
+
+#define TGA_MODE_SBM_8BPP 0x000
+#define TGA_MODE_SBM_24BPP 0x300
+
+#define TGA_MODE_SIMPLE 0x00
+#define TGA_MODE_SIMPLEZ 0x10
+#define TGA_MODE_OPAQUE_STIPPLE 0x01
+#define TGA_MODE_OPAQUE_FILL 0x21
+#define TGA_MODE_TRANSPARENT_STIPPLE 0x03
+#define TGA_MODE_TRANSPARENT_FILL 0x23
+#define TGA_MODE_BLOCK_STIPPLE 0x0d
+#define TGA_MODE_BLOCK_FILL 0x2d
+#define TGA_MODE_COPY 0x07
+#define TGA_MODE_DMA_READ_COPY_ND 0x17
+#define TGA_MODE_DMA_READ_COPY_D 0x37
+#define TGA_MODE_DMA_WRITE_COPY 0x1f
+
+
+/*
+ * Useful defines for managing the ICS1562 PLL clock
+ */
+
+#define TGA_PLL_BASE_FREQ 14318 /* .18 */
+#define TGA_PLL_MAX_FREQ 230000
+
+
+/*
+ * Useful defines for managing the BT485 on the 8-plane TGA
+ */
+
+#define BT485_READ_BIT 0x01
+#define BT485_WRITE_BIT 0x00
+
+#define BT485_ADDR_PAL_WRITE 0x00
+#define BT485_DATA_PAL 0x02
+#define BT485_PIXEL_MASK 0x04
+#define BT485_ADDR_PAL_READ 0x06
+#define BT485_ADDR_CUR_WRITE 0x08
+#define BT485_DATA_CUR 0x0a
+#define BT485_CMD_0 0x0c
+#define BT485_ADDR_CUR_READ 0x0e
+#define BT485_CMD_1 0x10
+#define BT485_CMD_2 0x12
+#define BT485_STATUS 0x14
+#define BT485_CMD_3 0x14
+#define BT485_CUR_RAM 0x16
+#define BT485_CUR_LOW_X 0x18
+#define BT485_CUR_HIGH_X 0x1a
+#define BT485_CUR_LOW_Y 0x1c
+#define BT485_CUR_HIGH_Y 0x1e
+
+
+/*
+ * Useful defines for managing the BT463 on the 24-plane TGAs/SFB+s
+ */
+
+#define BT463_ADDR_LO 0x0
+#define BT463_ADDR_HI 0x1
+#define BT463_REG_ACC 0x2
+#define BT463_PALETTE 0x3
+
+#define BT463_CUR_CLR_0 0x0100
+#define BT463_CUR_CLR_1 0x0101
+
+#define BT463_CMD_REG_0 0x0201
+#define BT463_CMD_REG_1 0x0202
+#define BT463_CMD_REG_2 0x0203
+
+#define BT463_READ_MASK_0 0x0205
+#define BT463_READ_MASK_1 0x0206
+#define BT463_READ_MASK_2 0x0207
+#define BT463_READ_MASK_3 0x0208
+
+#define BT463_BLINK_MASK_0 0x0209
+#define BT463_BLINK_MASK_1 0x020a
+#define BT463_BLINK_MASK_2 0x020b
+#define BT463_BLINK_MASK_3 0x020c
+
+#define BT463_WINDOW_TYPE_BASE 0x0300
+
+/*
+ * Useful defines for managing the BT459 on the 8-plane SFB+s
+ */
+
+#define BT459_ADDR_LO 0x0
+#define BT459_ADDR_HI 0x1
+#define BT459_REG_ACC 0x2
+#define BT459_PALETTE 0x3
+
+#define BT459_CUR_CLR_1 0x0181
+#define BT459_CUR_CLR_2 0x0182
+#define BT459_CUR_CLR_3 0x0183
+
+#define BT459_CMD_REG_0 0x0201
+#define BT459_CMD_REG_1 0x0202
+#define BT459_CMD_REG_2 0x0203
+
+#define BT459_READ_MASK 0x0204
+
+#define BT459_BLINK_MASK 0x0206
+
+#define BT459_CUR_CMD_REG 0x0300
+
+/*
+ * The framebuffer driver private data.
+ */
+
+struct tga_par {
+ /* PCI/TC device. */
+ struct device *dev;
+
+ /* Device dependent information. */
+ void __iomem *tga_mem_base;
+ void __iomem *tga_fb_base;
+ void __iomem *tga_regs_base;
+ u8 tga_type; /* TGA_TYPE_XXX */
+ u8 tga_chip_rev; /* dc21030 revision */
+
+ /* Remember blank mode. */
+ u8 vesa_blanked;
+
+ /* Define the video mode. */
+ u32 xres, yres; /* resolution in pixels */
+ u32 htimings; /* horizontal timing register */
+ u32 vtimings; /* vertical timing register */
+ u32 pll_freq; /* pixclock in mhz */
+ u32 bits_per_pixel; /* bits per pixel */
+ u32 sync_on_green; /* set if sync is on green */
+ u32 palette[16];
+};
+
+
+/*
+ * Macros for reading/writing TGA and RAMDAC registers
+ */
+
+static inline void
+TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
+{
+ writel(v, par->tga_regs_base +r);
+}
+
+static inline u32
+TGA_READ_REG(struct tga_par *par, u32 r)
+{
+ return readl(par->tga_regs_base +r);
+}
+
+static inline void
+BT485_WRITE(struct tga_par *par, u8 v, u8 r)
+{
+ TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
+}
+
+static inline void
+BT463_LOAD_ADDR(struct tga_par *par, u16 a)
+{
+ TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
+ TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
+}
+
+static inline void
+BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
+{
+ BT463_LOAD_ADDR(par, a);
+ TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
+}
+
+static inline void
+BT459_LOAD_ADDR(struct tga_par *par, u16 a)
+{
+ TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, a & 0xff, TGA_RAMDAC_REG);
+ TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, a >> 8, TGA_RAMDAC_REG);
+}
+
+static inline void
+BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
+{
+ BT459_LOAD_ADDR(par, a);
+ TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, v, TGA_RAMDAC_REG);
+}
+
+#endif /* TGAFB_H */