aboutsummaryrefslogtreecommitdiff
path: root/drivers/misc/habanalabs/include/gaudi2/asic_reg
ModeNameSize
-rw-r--r--arc_farm_arc0_acp_eng_regs.h16170logplainblame
-rw-r--r--arc_farm_arc0_aux_masks.h35435logplainblame
-rw-r--r--arc_farm_arc0_aux_regs.h17015logplainblame
-rw-r--r--arc_farm_arc0_dup_eng_axuser_regs.h1747logplainblame
-rw-r--r--arc_farm_arc0_dup_eng_regs.h17743logplainblame
-rw-r--r--arc_farm_kdma_ctx_axuser_masks.h5731logplainblame
-rw-r--r--arc_farm_kdma_ctx_axuser_regs.h1655logplainblame
-rw-r--r--arc_farm_kdma_ctx_masks.h8892logplainblame
-rw-r--r--arc_farm_kdma_ctx_regs.h2380logplainblame
-rw-r--r--arc_farm_kdma_kdma_cgm_regs.h709logplainblame
-rw-r--r--arc_farm_kdma_masks.h16583logplainblame
-rw-r--r--arc_farm_kdma_regs.h3883logplainblame
-rw-r--r--cpu_if_regs.h18149logplainblame
-rw-r--r--dcore0_dec0_cmd_masks.h9763logplainblame
-rw-r--r--dcore0_dec0_cmd_regs.h1920logplainblame
-rw-r--r--dcore0_edma0_core_ctx_axuser_regs.h1747logplainblame
-rw-r--r--dcore0_edma0_core_ctx_regs.h2540logplainblame
-rw-r--r--dcore0_edma0_core_masks.h17899logplainblame
-rw-r--r--dcore0_edma0_core_regs.h4167logplainblame
-rw-r--r--dcore0_edma0_qm_arc_aux_regs.h18743logplainblame
-rw-r--r--dcore0_edma0_qm_axuser_nonsecured_regs.h1862logplainblame
-rw-r--r--dcore0_edma0_qm_cgm_regs.h688logplainblame
-rw-r--r--dcore0_edma0_qm_masks.h51930logplainblame
-rw-r--r--dcore0_edma0_qm_regs.h28932logplainblame
-rw-r--r--dcore0_edma1_core_ctx_axuser_regs.h1747logplainblame
-rw-r--r--dcore0_edma1_qm_axuser_nonsecured_regs.h1862logplainblame
-rw-r--r--dcore0_hmmu0_mmu_masks.h13355logplainblame
-rw-r--r--dcore0_hmmu0_mmu_regs.h6841logplainblame
-rw-r--r--dcore0_hmmu0_stlb_masks.h15996logplainblame
-rw-r--r--dcore0_hmmu0_stlb_regs.h4011logplainblame
-rw-r--r--dcore0_mme_acc_regs.h1755logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h1040logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h1031logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h1040logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h1031logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h1022logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h1013logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h1022logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h1013logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h1022logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h1013logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h1022logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h1013logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h1022logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h1013logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_base_addr_regs.h1130logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h2406logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h1098logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_tensor_a_regs.h2125logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_tensor_b_regs.h2125logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h2203logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_masks.h22056logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_mme_axuser_regs.h1770logplainblame
-rw-r--r--dcore0_mme_ctrl_lo_regs.h4447logplainblame
-rw-r--r--dcore0_mme_qm_arc_acp_eng_regs.h17274logplainblame
-rw-r--r--dcore0_mme_qm_arc_aux_regs.h18167logplainblame
-rw-r--r--dcore0_mme_qm_arc_dup_eng_axuser_regs.h1839logplainblame
-rw-r--r--dcore0_mme_qm_arc_dup_eng_regs.h18863logplainblame
-rw-r--r--dcore0_mme_qm_axuser_nonsecured_regs.h1816logplainblame
-rw-r--r--dcore0_mme_qm_axuser_secured_regs.h1747logplainblame
-rw-r--r--dcore0_mme_qm_cgm_regs.h674logplainblame
-rw-r--r--dcore0_mme_qm_regs.h27890logplainblame
-rw-r--r--dcore0_mme_sbte0_masks.h3486logplainblame
-rw-r--r--dcore0_mme_sbte0_mstr_if_axuser_regs.h1816logplainblame
-rw-r--r--dcore0_mme_wb0_mstr_if_axuser_regs.h1770logplainblame
-rw-r--r--dcore0_rtr0_ctrl_regs.h8091logplainblame
-rw-r--r--dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h7682logplainblame
-rw-r--r--dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h6683logplainblame
-rw-r--r--dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h7682logplainblame
-rw-r--r--dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h6683logplainblame
-rw-r--r--dcore0_sync_mngr_glbl_masks.h5332logplainblame
-rw-r--r--dcore0_sync_mngr_glbl_regs.h34068logplainblame
-rw-r--r--dcore0_sync_mngr_mstr_if_axuser_masks.h6410logplainblame
-rw-r--r--dcore0_sync_mngr_mstr_if_axuser_regs.h1816logplainblame
-rw-r--r--dcore0_sync_mngr_objs_masks.h3557logplainblame
-rw-r--r--dcore0_sync_mngr_objs_regs.h1256314logplainblame
-rw-r--r--dcore0_tpc0_cfg_axuser_regs.h1609logplainblame
-rw-r--r--dcore0_tpc0_cfg_kernel_regs.h3500logplainblame
-rw-r--r--dcore0_tpc0_cfg_kernel_tensor_0_regs.h1966logplainblame
-rw-r--r--dcore0_tpc0_cfg_masks.h22268logplainblame
-rw-r--r--dcore0_tpc0_cfg_qm_regs.h3272logplainblame
-rw-r--r--dcore0_tpc0_cfg_qm_sync_object_regs.h716logplainblame
-rw-r--r--dcore0_tpc0_cfg_qm_tensor_0_regs.h1870logplainblame
-rw-r--r--dcore0_tpc0_cfg_regs.h5995logplainblame
-rw-r--r--dcore0_tpc0_cfg_special_regs.h5228logplainblame
-rw-r--r--dcore0_tpc0_eml_busmon_0_regs.h4177logplainblame
-rw-r--r--dcore0_tpc0_eml_etf_regs.h2614logplainblame
-rw-r--r--dcore0_tpc0_eml_funnel_regs.h1852logplainblame
-rw-r--r--dcore0_tpc0_eml_spmu_regs.h3742logplainblame
-rw-r--r--dcore0_tpc0_eml_stm_regs.h3160logplainblame
-rw-r--r--dcore0_tpc0_qm_arc_aux_regs.h18455logplainblame
-rw-r--r--dcore0_tpc0_qm_axuser_nonsecured_regs.h1839logplainblame
-rw-r--r--dcore0_tpc0_qm_cgm_regs.h681logplainblame
-rw-r--r--dcore0_tpc0_qm_regs.h28411logplainblame
-rw-r--r--dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h1862logplainblame
-rw-r--r--dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h2023logplainblame
-rw-r--r--dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h1977logplainblame
-rw-r--r--dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h1977logplainblame
-rw-r--r--dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h1977logplainblame
-rw-r--r--dcore0_vdec0_brdg_ctrl_masks.h28150logplainblame
-rw-r--r--dcore0_vdec0_brdg_ctrl_regs.h7529logplainblame
-rw-r--r--dcore0_vdec0_ctrl_special_regs.h5398logplainblame
-rw-r--r--dcore1_mme_ctrl_lo_regs.h4447logplainblame
-rw-r--r--dcore3_mme_ctrl_lo_regs.h4447logplainblame
-rw-r--r--gaudi2_blocks_linux_driver.h2456864logplainblame
-rw-r--r--gaudi2_regs.h25014logplainblame
-rw-r--r--nic0_qm0_cgm_regs.h639logplainblame
-rw-r--r--nic0_qm0_regs.h25285logplainblame
-rw-r--r--nic0_qm_arc_aux0_regs.h16727logplainblame
-rw-r--r--nic0_qpc0_regs.h22207logplainblame
-rw-r--r--nic0_umr0_0_completion_queue_ci_1_regs.h757logplainblame
-rw-r--r--nic0_umr0_0_unsecure_doorbell0_regs.h893logplainblame
-rw-r--r--pcie_aux_regs.h6788logplainblame
-rw-r--r--pcie_dbi_regs.h11034logplainblame
-rw-r--r--pcie_dec0_cmd_masks.h9405logplainblame
-rw-r--r--pcie_dec0_cmd_regs.h1850logplainblame
-rw-r--r--pcie_vdec0_brdg_ctrl_axuser_dec_regs.h1816logplainblame
-rw-r--r--pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h1977logplainblame
-rw-r--r--pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h1931logplainblame
-rw-r--r--pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h1931logplainblame
-rw-r--r--pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h1931logplainblame
-rw-r--r--pcie_vdec0_brdg_ctrl_masks.h27250logplainblame
-rw-r--r--pcie_vdec0_brdg_ctrl_regs.h7299logplainblame
-rw-r--r--pcie_vdec0_ctrl_special_regs.h5228logplainblame
-rw-r--r--pcie_wrap_regs.h14625logplainblame
-rw-r--r--pcie_wrap_special_regs.h4718logplainblame
-rw-r--r--pdma0_core_ctx_axuser_regs.h1586logplainblame
-rw-r--r--pdma0_core_ctx_regs.h2260logplainblame
-rw-r--r--pdma0_core_masks.h15596logplainblame
-rw-r--r--pdma0_core_regs.h3670logplainblame
-rw-r--r--pdma0_core_special_masks.h5901logplainblame
-rw-r--r--pdma0_qm_arc_aux_regs.h16727logplainblame
-rw-r--r--pdma0_qm_axuser_nonsecured_regs.h1701logplainblame
-rw-r--r--pdma0_qm_axuser_secured_regs.h1632logplainblame
-rw-r--r--pdma0_qm_cgm_regs.h639logplainblame
-rw-r--r--pdma0_qm_masks.h45224logplainblame
-rw-r--r--pdma0_qm_regs.h25285logplainblame
-rw-r--r--pdma1_core_ctx_axuser_regs.h1586logplainblame
-rw-r--r--pdma1_qm_axuser_nonsecured_regs.h1701logplainblame
-rw-r--r--pmmu_hbw_stlb_masks.h14948logplainblame
-rw-r--r--pmmu_hbw_stlb_regs.h3759logplainblame
-rw-r--r--pmmu_pif_regs.h3233logplainblame
-rw-r--r--psoc_etr_masks.h10146logplainblame
-rw-r--r--psoc_etr_regs.h2222logplainblame
-rw-r--r--psoc_global_conf_masks.h65365logplainblame
-rw-r--r--psoc_global_conf_regs.h35389logplainblame
-rw-r--r--psoc_reset_conf_masks.h100195logplainblame
-rw-r--r--psoc_reset_conf_regs.h27900logplainblame
-rw-r--r--psoc_timestamp_regs.h1251logplainblame
-rw-r--r--rot0_desc_regs.h3262logplainblame
-rw-r--r--rot0_masks.h9894logplainblame
-rw-r--r--rot0_qm_arc_aux_regs.h16439logplainblame
-rw-r--r--rot0_qm_axuser_nonsecured_regs.h1678logplainblame
-rw-r--r--rot0_qm_cgm_regs.h632logplainblame
-rw-r--r--rot0_qm_regs.h24764logplainblame
-rw-r--r--rot0_regs.h2180logplainblame
-rw-r--r--xbar_edge_0_regs.h4834logplainblame
-rw-r--r--xbar_mid_0_regs.h4742logplainblame