Merge tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextgrafted

Pull networking updates from Jakub Kicinski:
 "Core:

   - Add dedicated kmem_cache for typical/small skb->head, avoid having
     to access struct page at kfree time, and improve memory use.

   - Introduce sysctl to set default RPS configuration for new netdevs.

   - Define Netlink protocol specification format which can be used to
     describe messages used by each family and auto-generate parsers.
     Add tools for generating kernel data structures and uAPI headers.

   - Expose all net/core sysctls inside netns.

   - Remove 4s sleep in netpoll if carrier is instantly detected on
     boot.

   - Add configurable limit of MDB entries per port, and port-vlan.

   - Continue populating drop reasons throughout the stack.

   - Retire a handful of legacy Qdiscs and classifiers.

  Protocols:

   - Support IPv4 big TCP (TSO frames larger than 64kB).

   - Add IP_LOCAL_PORT_RANGE socket option, to control local port range
     on socket by socket basis.

   - Track and report in procfs number of MPTCP sockets used.

   - Support mixing IPv4 and IPv6 flows in the in-kernel MPTCP path
     manager.

   - IPv6: don't check net.ipv6.route.max_size and rely on garbage
     collection to free memory (similarly to IPv4).

   - Support Penultimate Segment Pop (PSP) flavor in SRv6 (RFC8986).

   - ICMP: add per-rate limit counters.

   - Add support for user scanning requests in ieee802154.

   - Remove static WEP support.

   - Support minimal Wi-Fi 7 Extremely High Throughput (EHT) rate
     reporting.

   - WiFi 7 EHT channel puncturing support (client & AP).

  BPF:

   - Add a rbtree data structure following the "next-gen data structure"
     precedent set by recently added linked list, that is, by using
     kfunc + kptr instead of adding a new BPF map type.

   - Expose XDP hints via kfuncs with initial support for RX hash and
     timestamp metadata.

   - Add BPF_F_NO_TUNNEL_KEY extension to bpf_skb_set_tunnel_key to
     better support decap on GRE tunnel devices not operating in collect
     metadata.

   - Improve x86 JIT's codegen for PROBE_MEM runtime error checks.

   - Remove the need for trace_printk_lock for bpf_trace_printk and
     bpf_trace_vprintk helpers.

   - Extend libbpf's bpf_tracing.h support for tracing arguments of
     kprobes/uprobes and syscall as a special case.

   - Significantly reduce the search time for module symbols by
     livepatch and BPF.

   - Enable cpumasks to be used as kptrs, which is useful for tracing
     programs tracking which tasks end up running on which CPUs in
     different time intervals.

   - Add support for BPF trampoline on s390x and riscv64.

   - Add capability to export the XDP features supported by the NIC.

   - Add __bpf_kfunc tag for marking kernel functions as kfuncs.

   - Add cgroup.memory=nobpf kernel parameter option to disable BPF
     memory accounting for container environments.

  Netfilter:

   - Remove the CLUSTERIP target. It has been marked as obsolete for
     years, and we still have WARN splats wrt races of the out-of-band
     /proc interface installed by this target.

   - Add 'destroy' commands to nf_tables. They are identical to the
     existing 'delete' commands, but do not return an error if the
     referenced object (set, chain, rule...) did not exist.

  Driver API:

   - Improve cpumask_local_spread() locality to help NICs set the right
     IRQ affinity on AMD platforms.

   - Separate C22 and C45 MDIO bus transactions more clearly.

   - Introduce new DCB table to control DSCP rewrite on egress.

   - Support configuration of Physical Layer Collision Avoidance (PLCA)
     Reconciliation Sublayer (RS) (802.3cg-2019). Modern version of
     shared medium Ethernet.

   - Support for MAC Merge layer (IEEE 802.3-2018 clause 99). Allowing
     preemption of low priority frames by high priority frames.

   - Add support for controlling MACSec offload using netlink SET.

   - Rework devlink instance refcounts to allow registration and
     de-registration under the instance lock. Split the code into
     multiple files, drop some of the unnecessarily granular locks and
     factor out common parts of netlink operation handling.

   - Add TX frame aggregation parameters (for USB drivers).

   - Add a new attr TCA_EXT_WARN_MSG to report TC (offload) warning
     messages with notifications for debug.

   - Allow offloading of UDP NEW connections via act_ct.

   - Add support for per action HW stats in TC.

   - Support hardware miss to TC action (continue processing in SW from
     a specific point in the action chain).

   - Warn if old Wireless Extension user space interface is used with
     modern cfg80211/mac80211 drivers. Do not support Wireless
     Extensions for Wi-Fi 7 devices at all. Everyone should switch to
     using nl80211 interface instead.

   - Improve the CAN bit timing configuration. Use extack to return
     error messages directly to user space, update the SJW handling,
     including the definition of a new default value that will benefit
     CAN-FD controllers, by increasing their oscillator tolerance.

  New hardware / drivers:

   - Ethernet:
      - nVidia BlueField-3 support (control traffic driver)
      - Ethernet support for imx93 SoCs
      - Motorcomm yt8531 gigabit Ethernet PHY
      - onsemi NCN26000 10BASE-T1S PHY (with support for PLCA)
      - Microchip LAN8841 PHY (incl. cable diagnostics and PTP)
      - Amlogic gxl MDIO mux

   - WiFi:
      - RealTek RTL8188EU (rtl8xxxu)
      - Qualcomm Wi-Fi 7 devices (ath12k)

   - CAN:
      - Renesas R-Car V4H

  Drivers:

   - Bluetooth:
      - Set Per Platform Antenna Gain (PPAG) for Intel controllers.

   - Ethernet NICs:
      - Intel (1G, igc):
         - support TSN / Qbv / packet scheduling features of i226 model
      - Intel (100G, ice):
         - use GNSS subsystem instead of TTY
         - multi-buffer XDP support
         - extend support for GPIO pins to E823 devices
      - nVidia/Mellanox:
         - update the shared buffer configuration on PFC commands
         - implement PTP adjphase function for HW offset control
         - TC support for Geneve and GRE with VF tunnel offload
         - more efficient crypto key management method
         - multi-port eswitch support
      - Netronome/Corigine:
         - add DCB IEEE support
         - support IPsec offloading for NFP3800
      - Freescale/NXP (enetc):
         - support XDP_REDIRECT for XDP non-linear buffers
         - improve reconfig, avoid link flap and waiting for idle
         - support MAC Merge layer
      - Other NICs:
         - sfc/ef100: add basic devlink support for ef100
         - ionic: rx_push mode operation (writing descriptors via MMIO)
         - bnxt: use the auxiliary bus abstraction for RDMA
         - r8169: disable ASPM and reset bus in case of tx timeout
         - cpsw: support QSGMII mode for J721e CPSW9G
         - cpts: support pulse-per-second output
         - ngbe: add an mdio bus driver
         - usbnet: optimize usbnet_bh() by avoiding unnecessary queuing
         - r8152: handle devices with FW with NCM support
         - amd-xgbe: support 10Mbps, 2.5GbE speeds and rx-adaptation
         - virtio-net: support multi buffer XDP
         - virtio/vsock: replace virtio_vsock_pkt with sk_buff
         - tsnep: XDP support

   - Ethernet high-speed switches:
      - nVidia/Mellanox (mlxsw):
         - add support for latency TLV (in FW control messages)
      - Microchip (sparx5):
         - separate explicit and implicit traffic forwarding rules, make
           the implicit rules always active
         - add support for egress DSCP rewrite
         - IS0 VCAP support (Ingress Classification)
         - IS2 VCAP filters (protos, L3 addrs, L4 ports, flags, ToS
           etc.)
         - ES2 VCAP support (Egress Access Control)
         - support for Per-Stream Filtering and Policing (802.1Q,
           8.6.5.1)

   - Ethernet embedded switches:
      - Marvell (mv88e6xxx):
         - add MAB (port auth) offload support
         - enable PTP receive for mv88e6390
      - NXP (ocelot):
         - support MAC Merge layer
         - support for the the vsc7512 internal copper phys
      - Microchip:
         - lan9303: convert to PHYLINK
         - lan966x: support TC flower filter statistics
         - lan937x: PTP support for KSZ9563/KSZ8563 and LAN937x
         - lan937x: support Credit Based Shaper configuration
         - ksz9477: support Energy Efficient Ethernet
      - other:
         - qca8k: convert to regmap read/write API, use bulk operations
         - rswitch: Improve TX timestamp accuracy

   - Intel WiFi (iwlwifi):
      - EHT (Wi-Fi 7) rate reporting
      - STEP equalizer support: transfer some STEP (connection to radio
        on platforms with integrated wifi) related parameters from the
        BIOS to the firmware.

   - Qualcomm 802.11ax WiFi (ath11k):
      - IPQ5018 support
      - Fine Timing Measurement (FTM) responder role support
      - channel 177 support

   - MediaTek WiFi (mt76):
      - per-PHY LED support
      - mt7996: EHT (Wi-Fi 7) support
      - Wireless Ethernet Dispatch (WED) reset support
      - switch to using page pool allocator

   - RealTek WiFi (rtw89):
      - support new version of Bluetooth co-existance

   - Mobile:
      - rmnet: support TX aggregation"

* tag 'net-next-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1872 commits)
  page_pool: add a comment explaining the fragment counter usage
  net: ethtool: fix __ethtool_dev_mm_supported() implementation
  ethtool: pse-pd: Fix double word in comments
  xsk: add linux/vmalloc.h to xsk.c
  sefltests: netdevsim: wait for devlink instance after netns removal
  selftest: fib_tests: Always cleanup before exit
  net/mlx5e: Align IPsec ASO result memory to be as required by hardware
  net/mlx5e: TC, Set CT miss to the specific ct action instance
  net/mlx5e: Rename CHAIN_TO_REG to MAPPED_OBJ_TO_REG
  net/mlx5: Refactor tc miss handling to a single function
  net/mlx5: Kconfig: Make tc offload depend on tc skb extension
  net/sched: flower: Support hardware miss to tc action
  net/sched: flower: Move filter handle initialization earlier
  net/sched: cls_api: Support hardware miss to tc action
  net/sched: Rename user cookie and act cookie
  sfc: fix builds without CONFIG_RTC_LIB
  sfc: clean up some inconsistent indentings
  net/mlx4_en: Introduce flexible array to silence overflow warning
  net: lan966x: Fix possible deadlock inside PTP
  net/ulp: Remove redundant ->clone() test in inet_clone_ulp().
  ...

1 files changed, 580 insertions, 0 deletions

diff --git a/drivers/net/ethernet/intel/ixgb/ixgb_ee.c b/drivers/net/ethernet/intel/ixgb/ixgb_ee.c
new file mode 100644
index 000000000..129286fc1
--- /dev/null
+++ b/drivers/net/ethernet/intel/ixgb/ixgb_ee.c
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 1999 - 2008 Intel Corporation. */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include "ixgb_hw.h"
+#include "ixgb_ee.h"
+/* Local prototypes */
+static u16 ixgb_shift_in_bits(struct ixgb_hw *hw);
+
+static void ixgb_shift_out_bits(struct ixgb_hw *hw,
+				u16 data,
+				u16 count);
+static void ixgb_standby_eeprom(struct ixgb_hw *hw);
+
+static bool ixgb_wait_eeprom_command(struct ixgb_hw *hw);
+
+static void ixgb_cleanup_eeprom(struct ixgb_hw *hw);
+
+/******************************************************************************
+ * Raises the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * eecd_reg - EECD's current value
+ *****************************************************************************/
+static void
+ixgb_raise_clock(struct ixgb_hw *hw,
+		  u32 *eecd_reg)
+{
+	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
+	 *  wait 50 microseconds.
+	 */
+	*eecd_reg = *eecd_reg | IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, *eecd_reg);
+	IXGB_WRITE_FLUSH(hw);
+	udelay(50);
+}
+
+/******************************************************************************
+ * Lowers the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * eecd_reg - EECD's current value
+ *****************************************************************************/
+static void
+ixgb_lower_clock(struct ixgb_hw *hw,
+		  u32 *eecd_reg)
+{
+	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
+	 * wait 50 microseconds.
+	 */
+	*eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, *eecd_reg);
+	IXGB_WRITE_FLUSH(hw);
+	udelay(50);
+}
+
+/******************************************************************************
+ * Shift data bits out to the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * data - data to send to the EEPROM
+ * count - number of bits to shift out
+ *****************************************************************************/
+static void
+ixgb_shift_out_bits(struct ixgb_hw *hw,
+					 u16 data,
+					 u16 count)
+{
+	u32 eecd_reg;
+	u32 mask;
+
+	/* We need to shift "count" bits out to the EEPROM. So, value in the
+	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
+	 * In order to do this, "data" must be broken down into bits.
+	 */
+	mask = 0x01 << (count - 1);
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+	eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
+	do {
+		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
+		 * and then raising and then lowering the clock (the SK bit controls
+		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
+		 * by setting "DI" to "0" and then raising and then lowering the clock.
+		 */
+		eecd_reg &= ~IXGB_EECD_DI;
+
+		if (data & mask)
+			eecd_reg |= IXGB_EECD_DI;
+
+		IXGB_WRITE_REG(hw, EECD, eecd_reg);
+		IXGB_WRITE_FLUSH(hw);
+
+		udelay(50);
+
+		ixgb_raise_clock(hw, &eecd_reg);
+		ixgb_lower_clock(hw, &eecd_reg);
+
+		mask = mask >> 1;
+
+	} while (mask);
+
+	/* We leave the "DI" bit set to "0" when we leave this routine. */
+	eecd_reg &= ~IXGB_EECD_DI;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+}
+
+/******************************************************************************
+ * Shift data bits in from the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static u16
+ixgb_shift_in_bits(struct ixgb_hw *hw)
+{
+	u32 eecd_reg;
+	u32 i;
+	u16 data;
+
+	/* In order to read a register from the EEPROM, we need to shift 16 bits
+	 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
+	 * the EEPROM (setting the SK bit), and then reading the value of the "DO"
+	 * bit.  During this "shifting in" process the "DI" bit should always be
+	 * clear..
+	 */
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
+	data = 0;
+
+	for (i = 0; i < 16; i++) {
+		data = data << 1;
+		ixgb_raise_clock(hw, &eecd_reg);
+
+		eecd_reg = IXGB_READ_REG(hw, EECD);
+
+		eecd_reg &= ~(IXGB_EECD_DI);
+		if (eecd_reg & IXGB_EECD_DO)
+			data |= 1;
+
+		ixgb_lower_clock(hw, &eecd_reg);
+	}
+
+	return data;
+}
+
+/******************************************************************************
+ * Prepares EEPROM for access
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
+ * function should be called before issuing a command to the EEPROM.
+ *****************************************************************************/
+static void
+ixgb_setup_eeprom(struct ixgb_hw *hw)
+{
+	u32 eecd_reg;
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	/*  Clear SK and DI  */
+	eecd_reg &= ~(IXGB_EECD_SK | IXGB_EECD_DI);
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+
+	/*  Set CS  */
+	eecd_reg |= IXGB_EECD_CS;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+}
+
+/******************************************************************************
+ * Returns EEPROM to a "standby" state
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+ixgb_standby_eeprom(struct ixgb_hw *hw)
+{
+	u32 eecd_reg;
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	/*  Deselect EEPROM  */
+	eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	IXGB_WRITE_FLUSH(hw);
+	udelay(50);
+
+	/*  Clock high  */
+	eecd_reg |= IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	IXGB_WRITE_FLUSH(hw);
+	udelay(50);
+
+	/*  Select EEPROM  */
+	eecd_reg |= IXGB_EECD_CS;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	IXGB_WRITE_FLUSH(hw);
+	udelay(50);
+
+	/*  Clock low  */
+	eecd_reg &= ~IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	IXGB_WRITE_FLUSH(hw);
+	udelay(50);
+}
+
+/******************************************************************************
+ * Raises then lowers the EEPROM's clock pin
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+ixgb_clock_eeprom(struct ixgb_hw *hw)
+{
+	u32 eecd_reg;
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	/*  Rising edge of clock  */
+	eecd_reg |= IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	IXGB_WRITE_FLUSH(hw);
+	udelay(50);
+
+	/*  Falling edge of clock  */
+	eecd_reg &= ~IXGB_EECD_SK;
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+	IXGB_WRITE_FLUSH(hw);
+	udelay(50);
+}
+
+/******************************************************************************
+ * Terminates a command by lowering the EEPROM's chip select pin
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+ixgb_cleanup_eeprom(struct ixgb_hw *hw)
+{
+	u32 eecd_reg;
+
+	eecd_reg = IXGB_READ_REG(hw, EECD);
+
+	eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_DI);
+
+	IXGB_WRITE_REG(hw, EECD, eecd_reg);
+
+	ixgb_clock_eeprom(hw);
+}
+
+/******************************************************************************
+ * Waits for the EEPROM to finish the current command.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * The command is done when the EEPROM's data out pin goes high.
+ *
+ * Returns:
+ *      true: EEPROM data pin is high before timeout.
+ *      false:  Time expired.
+ *****************************************************************************/
+static bool
+ixgb_wait_eeprom_command(struct ixgb_hw *hw)
+{
+	u32 eecd_reg;
+	u32 i;
+
+	/* Toggle the CS line.  This in effect tells to EEPROM to actually execute
+	 * the command in question.
+	 */
+	ixgb_standby_eeprom(hw);
+
+	/* Now read DO repeatedly until is high (equal to '1').  The EEPROM will
+	 * signal that the command has been completed by raising the DO signal.
+	 * If DO does not go high in 10 milliseconds, then error out.
+	 */
+	for (i = 0; i < 200; i++) {
+		eecd_reg = IXGB_READ_REG(hw, EECD);
+
+		if (eecd_reg & IXGB_EECD_DO)
+			return true;
+
+		udelay(50);
+	}
+	ASSERT(0);
+	return false;
+}
+
+/******************************************************************************
+ * Verifies that the EEPROM has a valid checksum
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Reads the first 64 16 bit words of the EEPROM and sums the values read.
+ * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
+ * valid.
+ *
+ * Returns:
+ *  true: Checksum is valid
+ *  false: Checksum is not valid.
+ *****************************************************************************/
+bool
+ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
+{
+	u16 checksum = 0;
+	u16 i;
+
+	for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
+		checksum += ixgb_read_eeprom(hw, i);
+
+	if (checksum == (u16) EEPROM_SUM)
+		return true;
+	else
+		return false;
+}
+
+/******************************************************************************
+ * Calculates the EEPROM checksum and writes it to the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
+ * Writes the difference to word offset 63 of the EEPROM.
+ *****************************************************************************/
+void
+ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
+{
+	u16 checksum = 0;
+	u16 i;
+
+	for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
+		checksum += ixgb_read_eeprom(hw, i);
+
+	checksum = (u16) EEPROM_SUM - checksum;
+
+	ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum);
+}
+
+/******************************************************************************
+ * Writes a 16 bit word to a given offset in the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * reg - offset within the EEPROM to be written to
+ * data - 16 bit word to be written to the EEPROM
+ *
+ * If ixgb_update_eeprom_checksum is not called after this function, the
+ * EEPROM will most likely contain an invalid checksum.
+ *
+ *****************************************************************************/
+void
+ixgb_write_eeprom(struct ixgb_hw *hw, u16 offset, u16 data)
+{
+	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	/* Prepare the EEPROM for writing */
+	ixgb_setup_eeprom(hw);
+
+	/*  Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit opcode
+	 *  plus 4-bit dummy).  This puts the EEPROM into write/erase mode.
+	 */
+	ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5);
+	ixgb_shift_out_bits(hw, 0, 4);
+
+	/*  Prepare the EEPROM  */
+	ixgb_standby_eeprom(hw);
+
+	/*  Send the Write command (3-bit opcode + 6-bit addr)  */
+	ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3);
+	ixgb_shift_out_bits(hw, offset, 6);
+
+	/*  Send the data  */
+	ixgb_shift_out_bits(hw, data, 16);
+
+	ixgb_wait_eeprom_command(hw);
+
+	/*  Recover from write  */
+	ixgb_standby_eeprom(hw);
+
+	/* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit
+	 * opcode plus 4-bit dummy).  This takes the EEPROM out of write/erase
+	 * mode.
+	 */
+	ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5);
+	ixgb_shift_out_bits(hw, 0, 4);
+
+	/*  Done with writing  */
+	ixgb_cleanup_eeprom(hw);
+
+	/* clear the init_ctrl_reg_1 to signify that the cache is invalidated */
+	ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR);
+}
+
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - offset of 16 bit word in the EEPROM to read
+ *
+ * Returns:
+ *  The 16-bit value read from the eeprom
+ *****************************************************************************/
+u16
+ixgb_read_eeprom(struct ixgb_hw *hw,
+		  u16 offset)
+{
+	u16 data;
+
+	/*  Prepare the EEPROM for reading  */
+	ixgb_setup_eeprom(hw);
+
+	/*  Send the READ command (opcode + addr)  */
+	ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3);
+	/*
+	 * We have a 64 word EEPROM, there are 6 address bits
+	 */
+	ixgb_shift_out_bits(hw, offset, 6);
+
+	/*  Read the data  */
+	data = ixgb_shift_in_bits(hw);
+
+	/*  End this read operation  */
+	ixgb_standby_eeprom(hw);
+
+	return data;
+}
+
+/******************************************************************************
+ * Reads eeprom and stores data in shared structure.
+ * Validates eeprom checksum and eeprom signature.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Returns:
+ *      true: if eeprom read is successful
+ *      false: otherwise.
+ *****************************************************************************/
+bool
+ixgb_get_eeprom_data(struct ixgb_hw *hw)
+{
+	u16 i;
+	u16 checksum = 0;
+	struct ixgb_ee_map_type *ee_map;
+
+	ENTER();
+
+	ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	pr_debug("Reading eeprom data\n");
+	for (i = 0; i < IXGB_EEPROM_SIZE ; i++) {
+		u16 ee_data;
+		ee_data = ixgb_read_eeprom(hw, i);
+		checksum += ee_data;
+		hw->eeprom[i] = cpu_to_le16(ee_data);
+	}
+
+	if (checksum != (u16) EEPROM_SUM) {
+		pr_debug("Checksum invalid\n");
+		/* clear the init_ctrl_reg_1 to signify that the cache is
+		 * invalidated */
+		ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR);
+		return false;
+	}
+
+	if ((ee_map->init_ctrl_reg_1 & cpu_to_le16(EEPROM_ICW1_SIGNATURE_MASK))
+		 != cpu_to_le16(EEPROM_ICW1_SIGNATURE_VALID)) {
+		pr_debug("Signature invalid\n");
+		return false;
+	}
+
+	return true;
+}
+
+/******************************************************************************
+ * Local function to check if the eeprom signature is good
+ * If the eeprom signature is good, calls ixgb)get_eeprom_data.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Returns:
+ *      true: eeprom signature was good and the eeprom read was successful
+ *      false: otherwise.
+ ******************************************************************************/
+static bool
+ixgb_check_and_get_eeprom_data (struct ixgb_hw* hw)
+{
+	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	if ((ee_map->init_ctrl_reg_1 & cpu_to_le16(EEPROM_ICW1_SIGNATURE_MASK))
+	    == cpu_to_le16(EEPROM_ICW1_SIGNATURE_VALID)) {
+		return true;
+	} else {
+		return ixgb_get_eeprom_data(hw);
+	}
+}
+
+/******************************************************************************
+ * return a word from the eeprom
+ *
+ * hw - Struct containing variables accessed by shared code
+ * index - Offset of eeprom word
+ *
+ * Returns:
+ *          Word at indexed offset in eeprom, if valid, 0 otherwise.
+ ******************************************************************************/
+__le16
+ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index)
+{
+
+	if (index < IXGB_EEPROM_SIZE && ixgb_check_and_get_eeprom_data(hw))
+		return hw->eeprom[index];
+
+	return 0;
+}
+
+/******************************************************************************
+ * return the mac address from EEPROM
+ *
+ * hw       - Struct containing variables accessed by shared code
+ * mac_addr - Ethernet Address if EEPROM contents are valid, 0 otherwise
+ *
+ * Returns: None.
+ ******************************************************************************/
+void
+ixgb_get_ee_mac_addr(struct ixgb_hw *hw,
+			u8 *mac_addr)
+{
+	int i;
+	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	ENTER();
+
+	if (ixgb_check_and_get_eeprom_data(hw)) {
+		for (i = 0; i < ETH_ALEN; i++) {
+			mac_addr[i] = ee_map->mac_addr[i];
+		}
+		pr_debug("eeprom mac address = %pM\n", mac_addr);
+	}
+}
+
+
+/******************************************************************************
+ * return the Printed Board Assembly number from EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Returns:
+ *          PBA number if EEPROM contents are valid, 0 otherwise
+ ******************************************************************************/
+u32
+ixgb_get_ee_pba_number(struct ixgb_hw *hw)
+{
+	if (ixgb_check_and_get_eeprom_data(hw))
+		return le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG])
+			| (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG])<<16);
+
+	return 0;
+}
+
+
+/******************************************************************************
+ * return the Device Id from EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Returns:
+ *          Device Id if EEPROM contents are valid, 0 otherwise
+ ******************************************************************************/
+u16
+ixgb_get_ee_device_id(struct ixgb_hw *hw)
+{
+	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
+
+	if (ixgb_check_and_get_eeprom_data(hw))
+		return le16_to_cpu(ee_map->device_id);
+
+	return 0;
+}
+